diff options
| -rw-r--r-- | src/arch/x86/isa/microops/fpop.isa | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa index 65c2fdb57..52193f2c0 100644 --- a/src/arch/x86/isa/microops/fpop.isa +++ b/src/arch/x86/isa/microops/fpop.isa @@ -380,29 +380,27 @@ let {{ class PremFp(FpBinaryOp): code = ''' - MiscReg new_fsw(FSW); + MiscReg new_fsw = FSW; int src1_exp; int src2_exp; std::frexp(FpSrcReg1, &src1_exp); std::frexp(FpSrcReg2, &src2_exp); - const int d(src2_exp - src1_exp); + const int d = src2_exp - src1_exp; if (d < 64) { - const int64_t q(std::trunc(FpSrcReg2 / FpSrcReg1)); + const int64_t q = std::trunc(FpSrcReg2 / FpSrcReg1); FpDestReg = FpSrcReg2 - FpSrcReg1 * q; new_fsw &= ~(CC0Bit | CC1Bit | CC2Bit | CC2Bit); new_fsw |= (q & 0x1) ? CC1Bit : 0; new_fsw |= (q & 0x2) ? CC3Bit : 0; new_fsw |= (q & 0x4) ? CC0Bit : 0; } else { - const int n(42); - const int64_t qq(std::trunc( - FpSrcReg2 / std::ldexp(FpSrcReg1, d - n))); + const int n = 42; + const int64_t qq = std::trunc( + FpSrcReg2 / std::ldexp(FpSrcReg1, d - n)); FpDestReg = FpSrcReg2 - std::ldexp(FpSrcReg1 * qq, d - n); new_fsw |= CC2Bit; } - DPRINTF(X86, "src1: %lf, src2: %lf, dest: %lf, FSW: 0x%x\\n", - FpSrcReg1, FpSrcReg2, FpDestReg, new_fsw); ''' op_class = 'FloatDivOp' |