diff options
45 files changed, 0 insertions, 37406 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/EMPTY b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/EMPTY new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/EMPTY diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini deleted file mode 100644 index 1ffb07f29..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ /dev/null @@ -1,2137 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxArmSystem -children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain -atags_addr=134217728 -boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb -early_kernel_symbols=false -enable_context_switch_stats_dump=false -eventq_index=0 -exit_on_work_items=false -flags_addr=469827632 -gic_cpu_addr=738205696 -have_large_asid_64=false -have_lpae=true -have_security=false -have_virtualization=false -highest_el_is_64=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 -kernel_addr_check=true -load_addr_mask=268435455 -load_offset=2147483648 -machine_type=VExpress_EMM -mem_mode=timing -mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.nvmem system.realview.vram -mmap_using_noreserve=false -multi_proc=true -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -panic_on_oops=true -panic_on_panic=true -phys_addr_range_64=40 -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -reset_addr_64=0 -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[1] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.cf0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.cf0.image - -[system.cf0.image] -type=CowDiskImage -children=child -child=system.cf0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.cf0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img -read_only=true - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer -LFSTSize=1024 -LQEntries=16 -LSQCheckLoads=true -LSQDepCheckShift=0 -SQEntries=16 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=system.cpu.checker -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=2 -decodeWidth=3 -default_p_state=UNDEFINED -dispatchWidth=6 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=16 -fetchQueueSize=32 -fetchToDecodeDelay=3 -fetchTrapLatency=1 -fetchWidth=3 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=32 -numPhysCCRegs=640 -numPhysFloatRegs=192 -numPhysIntRegs=128 -numROBEntries=40 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=1 -renameToROBDelay=1 -renameWidth=3 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BiModeBP -BTBEntries=2048 -BTBTagSize=18 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -numThreads=1 -useIndirect=true - -[system.cpu.checker] -type=O3Checker -children=dstage2_mmu dtb isa istage2_mmu itb tracer -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.checker.dstage2_mmu -dtb=system.cpu.checker.dtb -eventq_index=0 -exitOnError=false -function_trace=false -function_trace_start=0 -interrupts= -isa=system.cpu.checker.isa -istage2_mmu=system.cpu.checker.istage2_mmu -itb=system.cpu.checker.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.checker.tracer -updateOnError=true -warnOnlyOnLoadError=true -workload= - -[system.cpu.checker.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.checker.dtb - -[system.cpu.checker.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker - -[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.checker.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.checker.dtb.walker - -[system.cpu.checker.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[5] - -[system.cpu.checker.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.checker.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.checker.itb - -[system.cpu.checker.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker - -[system.cpu.checker.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.checker.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.checker.itb.walker - -[system.cpu.checker.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[4] - -[system.cpu.checker.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 opList2 -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList1.opList2] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList - -[system.cpu.fuPool.FUList2.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList - -[system.cpu.fuPool.FUList3.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 - -[system.cpu.fuPool.FUList4.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=9 -pipelined=true - -[system.cpu.fuPool.FUList4.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList4.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=9 -pipelined=true - -[system.cpu.fuPool.FUList4.opList20] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList21] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList22] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList23] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=9 -pipelined=false - -[system.cpu.fuPool.FUList4.opList24] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=33 -pipelined=false - -[system.cpu.fuPool.FUList4.opList25] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[2] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=2147483648:2415919103 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[3] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.membus] -type=CoherentXBar -children=badaddr_responder -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access=warn -pio=system.membus.default - -[system.physmem] -type=DRAMCtrl -IDD0=0.075000 -IDD02=0.000000 -IDD2N=0.050000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.000000 -IDD2P12=0.000000 -IDD3N=0.057000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.000000 -IDD3P12=0.000000 -IDD4R=0.187000 -IDD4R2=0.000000 -IDD4W=0.165000 -IDD4W2=0.000000 -IDD5=0.220000 -IDD52=0.000000 -IDD6=0.000000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=2147483648:2415919103 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=0 -tXPDLL=0 -tXS=0 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[5] - -[system.realview] -type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.realview.aaci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470024192 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[18] - -[system.realview.cf_ctrl] -type=IdeController -BAR0=471465984 -BAR0LegacyIO=true -BAR0Size=256 -BAR1=471466240 -BAR1LegacyIO=true -BAR1Size=4096 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=1 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=2 -default_p_state=UNDEFINED -disks= -eventq_index=0 -host=system.realview.pci_host -io_shift=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=2 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[2] -pio=system.iobus.master[9] - -[system.realview.clcd] -type=Pl111 -amba_id=1315089 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=46 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471793664 -pio_latency=10000 -pixel_clock=41667 -power_model=Null -system=system -vnc=system.vncserver -dma=system.iobus.slave[1] -pio=system.iobus.master[5] - -[system.realview.dcc] -type=SubSystem -children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys -eventq_index=0 -thermal_domain=Null - -[system.realview.dcc.osc_cpu] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_ddr] -type=RealViewOsc -dcc=0 -device=8 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_hsbm] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_pxl] -type=RealViewOsc -dcc=0 -device=5 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_smb] -type=RealViewOsc -dcc=0 -device=6 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_sys] -type=RealViewOsc -dcc=0 -device=7 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.energy_ctrl] -type=EnergyCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dvfs_handler=system.dvfs_handler -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470286336 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[22] - -[system.realview.ethernet] -type=IGbE -BAR0=0 -BAR0LegacyIO=false -BAR0Size=131072 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=0 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=4213 -ExpansionROM=0 -HeaderType=0 -InterruptLine=1 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=255 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=0 -SubClassCode=0 -SubsystemID=4104 -SubsystemVendorID=32902 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -eventq_index=0 -fetch_comp_delay=10000 -fetch_delay=10000 -hardware_address=00:90:00:00:00:01 -host=system.realview.pci_host -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -phy_epid=896 -phy_pid=680 -pio_latency=30000 -power_model=Null -rx_desc_cache_size=64 -rx_fifo_size=393216 -rx_write_delay=0 -system=system -tx_desc_cache_size=64 -tx_fifo_size=393216 -tx_read_delay=0 -wb_comp_delay=10000 -wb_delay=10000 -dma=system.iobus.slave[4] -pio=system.iobus.master[24] - -[system.realview.generic_timer] -type=GenericTimer -eventq_index=0 -gic=system.realview.gic -int_phys=29 -int_virt=27 -system=system - -[system.realview.gic] -type=Pl390 -clk_domain=system.clk_domain -cpu_addr=738205696 -cpu_pio_delay=10000 -default_p_state=UNDEFINED -dist_addr=738201600 -dist_pio_delay=10000 -eventq_index=0 -gem5_extensions=true -int_latency=10000 -it_lines=128 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -platform=system.realview -power_model=Null -system=system -pio=system.membus.master[2] - -[system.realview.hdlcd] -type=HDLcd -amba_id=1314816 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=117 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=721420288 -pio_latency=10000 -pixel_buffer_size=2048 -pixel_chunk=32 -power_model=Null -pxl_clk=system.realview.dcc.osc_pxl -system=system -vnc=system.vncserver -workaround_dma_line_count=true -workaround_swap_rb=true -dma=system.membus.slave[0] -pio=system.iobus.master[6] - -[system.realview.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=2 -InterruptPin=2 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.cf0 -eventq_index=0 -host=system.realview.pci_host -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[3] -pio=system.iobus.master[23] - -[system.realview.kmi0] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=44 -is_mouse=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470155264 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[7] - -[system.realview.kmi1] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=45 -is_mouse=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470220800 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[8] - -[system.realview.l2x0_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=739246080 -pio_latency=100000 -pio_size=4095 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.realview.lan_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=436207616 -pio_latency=100000 -pio_size=65535 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.realview.local_cpu_timer] -type=CpuLocalTimer -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num_timer=29 -int_num_watchdog=30 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=738721792 -pio_latency=100000 -power_model=Null -system=system -pio=system.membus.master[4] - -[system.realview.mcc] -type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl -eventq_index=0 -thermal_domain=Null - -[system.realview.mcc.osc_clcd] -type=RealViewOsc -dcc=0 -device=1 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_mcc] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_peripheral] -type=RealViewOsc -dcc=0 -device=2 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_system_bus] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.temp_crtl] -type=RealViewTemperatureSensor -dcc=0 -device=0 -eventq_index=0 -parent=system.realview.realview_io -position=0 -site=0 -system=system - -[system.realview.mmc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470089728 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.realview.nvmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:67108863 -port=system.membus.master[1] - -[system.realview.pci_host] -type=GenericPciHost -clk_domain=system.clk_domain -conf_base=805306368 -conf_device_bits=16 -conf_size=268435456 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=0 -pci_pio_base=0 -platform=system.realview -power_model=Null -system=system -pio=system.iobus.master[2] - -[system.realview.realview_io] -type=RealViewCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -idreg=35979264 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469827584 -pio_latency=100000 -power_model=Null -proc_id0=335544320 -proc_id1=335544320 -system=system -pio=system.iobus.master[1] - -[system.realview.rtc] -type=PL031 -amba_id=3412017 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=36 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471269376 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[10] - -[system.realview.sp810_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469893120 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[16] - -[system.realview.timer0] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=34 -int_num1=34 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470876160 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[3] - -[system.realview.timer1] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=35 -int_num1=35 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470941696 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[4] - -[system.realview.uart] -type=Pl011 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -end_on_eot=false -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=37 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470351872 -pio_latency=100000 -platform=system.realview -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[0] - -[system.realview.uart1_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470417408 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[13] - -[system.realview.uart2_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470482944 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[14] - -[system.realview.uart3_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470548480 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[15] - -[system.realview.usb_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=452984832 -pio_latency=100000 -pio_size=131071 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.realview.vgic] -type=VGic -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -hv_addr=738213888 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_delay=10000 -platform=system.realview -power_model=Null -ppint=25 -system=system -vcpu_addr=738222080 -pio=system.membus.master[3] - -[system.realview.vram] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=402653184:436207615 -port=system.iobus.master[11] - -[system.realview.watchdog_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470745088 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[17] - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.vncserver] -type=VncServer -eventq_index=0 -frame_capture=false -number=0 -port=5900 - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr deleted file mode 100755 index d158de479..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ /dev/null @@ -1,48 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting vnc client connections -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Existing EnergyCtrl, but no enabled DVFSHandler found. -warn: Not doing anything for miscreg ACTLR -warn: Not doing anything for miscreg ACTLR -warn: Not doing anything for write of miscreg ACTLR -warn: Not doing anything for write of miscreg ACTLR -warn: The clidr register always reports 0 caches. -warn: clidr LoUIS field of 0b001 to match current ARM implementations. -warn: The csselr register isn't implemented. -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr dccimvac' unimplemented -warn: Tried to read RealView I/O at offset 0x60 that doesn't exist -warn: 11084065000: Instruction results do not match! (Values may not actually be integers) Inst: 0xa, checker: 0 -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] -warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] -warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] -warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] -warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] -warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] -warn: Returning zero for read from miscreg pmcr -warn: Returning zero for read from miscreg pmcr -warn: Ignoring write to miscreg pmcntenclr -warn: Ignoring write to miscreg pmcntenclr -warn: Ignoring write to miscreg pmintenclr -warn: Ignoring write to miscreg pmintenclr -warn: Ignoring write to miscreg pmovsr -warn: Ignoring write to miscreg pmovsr -warn: Ignoring write to miscreg pmcr -warn: Ignoring write to miscreg pmcr -warn: instruction 'mcr dcisw' unimplemented -warn: instruction 'mcr bpiall' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout deleted file mode 100755 index 2379a9494..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ /dev/null @@ -1,47 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12228 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-checker - -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 -info: Using bootloader at address 0x10 -info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 -info: Entering event queue @ 0. Starting simulation... -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2832894126500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt deleted file mode 100644 index e59cf51bf..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ /dev/null @@ -1,1991 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.827853 # Number of seconds simulated -sim_ticks 2827853096000 # Number of ticks simulated -final_tick 2827853096000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70378 # Simulator instruction rate (inst/s) -host_op_rate 85367 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1758794234 # Simulator tick rate (ticks/s) -host_mem_usage 588628 # Number of bytes of host memory used -host_seconds 1607.84 # Real time elapsed on the host -sim_insts 113155640 # Number of instructions simulated -sim_ops 137255479 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1322240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9790440 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11115048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1322240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1322240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8407168 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8424692 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22907 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 153496 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 176440 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131362 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135743 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 467577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3462146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3930561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 467577 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 467577 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2972986 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2979183 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2972986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 467577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3468343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6909744 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 176441 # Number of read requests accepted -system.physmem.writeReqs 135743 # Number of write requests accepted -system.physmem.readBursts 176441 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 135743 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11282432 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue -system.physmem.bytesWritten 8437824 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11115112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8424692 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3886 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11743 # Per bank write bursts -system.physmem.perBankRdBursts::1 11227 # Per bank write bursts -system.physmem.perBankRdBursts::2 11041 # Per bank write bursts -system.physmem.perBankRdBursts::3 10652 # Per bank write bursts -system.physmem.perBankRdBursts::4 13485 # Per bank write bursts -system.physmem.perBankRdBursts::5 11002 # Per bank write bursts -system.physmem.perBankRdBursts::6 11432 # Per bank write bursts -system.physmem.perBankRdBursts::7 11844 # Per bank write bursts -system.physmem.perBankRdBursts::8 10383 # Per bank write bursts -system.physmem.perBankRdBursts::9 10947 # Per bank write bursts -system.physmem.perBankRdBursts::10 10471 # Per bank write bursts -system.physmem.perBankRdBursts::11 9569 # Per bank write bursts -system.physmem.perBankRdBursts::12 10361 # Per bank write bursts -system.physmem.perBankRdBursts::13 11110 # Per bank write bursts -system.physmem.perBankRdBursts::14 10361 # Per bank write bursts -system.physmem.perBankRdBursts::15 10660 # Per bank write bursts -system.physmem.perBankWrBursts::0 8764 # Per bank write bursts -system.physmem.perBankWrBursts::1 8604 # Per bank write bursts -system.physmem.perBankWrBursts::2 8676 # Per bank write bursts -system.physmem.perBankWrBursts::3 8310 # Per bank write bursts -system.physmem.perBankWrBursts::4 8074 # Per bank write bursts -system.physmem.perBankWrBursts::5 8230 # Per bank write bursts -system.physmem.perBankWrBursts::6 8228 # Per bank write bursts -system.physmem.perBankWrBursts::7 8800 # Per bank write bursts -system.physmem.perBankWrBursts::8 7938 # Per bank write bursts -system.physmem.perBankWrBursts::9 8472 # Per bank write bursts -system.physmem.perBankWrBursts::10 8080 # Per bank write bursts -system.physmem.perBankWrBursts::11 7388 # Per bank write bursts -system.physmem.perBankWrBursts::12 8035 # Per bank write bursts -system.physmem.perBankWrBursts::13 8487 # Per bank write bursts -system.physmem.perBankWrBursts::14 7854 # Per bank write bursts -system.physmem.perBankWrBursts::15 7901 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 2827852861000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 542 # Read request sizes (log2) -system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 2996 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 172889 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 4381 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131362 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 155219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 17999 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 829 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64990 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.434251 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.571710 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.070143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24166 37.18% 37.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15993 24.61% 61.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6821 10.50% 72.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3792 5.83% 78.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2758 4.24% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1633 2.51% 84.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1086 1.67% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1085 1.67% 88.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7656 11.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64990 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6662 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.461423 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 559.657587 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6661 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6662 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6662 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.790003 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.288798 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.351415 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5875 88.19% 88.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 70 1.05% 89.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 75 1.13% 90.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 36 0.54% 90.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 259 3.89% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 62 0.93% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 25 0.38% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 19 0.29% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 9 0.14% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.11% 96.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.05% 96.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.06% 96.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 160 2.40% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.12% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.03% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.09% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 10 0.15% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.12% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6662 # Writes before turning the bus around for reads -system.physmem.totQLat 2116192000 # Total ticks spent queuing -system.physmem.totMemAccLat 5421592000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 881440000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12004.17 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30754.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.93 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.03 # Average write queue length when enqueuing -system.physmem.readRowHits 145153 # Number of row buffer hits during reads -system.physmem.writeRowHits 97985 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.31 # Row buffer hit rate for writes -system.physmem.avgGap 9058288.90 # Average gap between requests -system.physmem.pageHitRate 78.90 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 256087440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 139730250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 720922800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 438605280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184701363600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 81077227785 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625589296250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1892923233405 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.386141 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2704185411500 # Time in different power states -system.physmem_0.memoryStateTime::REF 94428100000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29235954750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 235236960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 128353500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654115800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 415724400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184701363600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80292349755 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626277785750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1892704929765 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.308944 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2705344853000 # Time in different power states -system.physmem_1.memoryStateTime::REF 94428100000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 28080129500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46859222 # Number of BP lookups -system.cpu.branchPred.condPredicted 23995015 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1174256 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29489294 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13535968 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 45.901296 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11745095 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 35189 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7931554 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 7786304 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 145250 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 60170 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.checker.dtb.walker.walks 9867 # Table walker walks requested -system.cpu.checker.dtb.walker.walksShort 9867 # Table walker walks initiated with short descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 9867 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 9867 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 9867 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walksPending::samples 230261000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::0 230261000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::total 230261000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 6312 81.94% 81.94% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::1M 1391 18.06% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 7703 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9867 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9867 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7703 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7703 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 17570 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.inst_hits 0 # ITB inst hits -system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24589623 # DTB read hits -system.cpu.checker.dtb.read_misses 8439 # DTB read misses -system.cpu.checker.dtb.write_hits 19639356 # DTB write hits -system.cpu.checker.dtb.write_misses 1428 # DTB write misses -system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed -system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 4257 # Number of entries that have been flushed from TLB -system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 1816 # Number of TLB faults due to prefetch -system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24598062 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19640784 # DTB write accesses -system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44228979 # DTB hits -system.cpu.checker.dtb.misses 9867 # DTB misses -system.cpu.checker.dtb.accesses 44238846 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.checker.itb.walker.walks 4826 # Table walker walks requested -system.cpu.checker.itb.walker.walksShort 4826 # Table walker walks initiated with short descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 4826 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 4826 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 4826 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walksPending::samples 229845000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::0 229845000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::total 229845000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.24% 88.24% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::1M 373 11.76% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 3171 # Table walker page sizes translated -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 4826 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 4826 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3171 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3171 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 7997 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 115857502 # ITB inst hits -system.cpu.checker.itb.inst_misses 4826 # ITB inst misses -system.cpu.checker.itb.read_hits 0 # DTB read hits -system.cpu.checker.itb.read_misses 0 # DTB read misses -system.cpu.checker.itb.write_hits 0 # DTB write hits -system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 128 # Number of times complete TLB was flushed -system.cpu.checker.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 2913 # Number of entries that have been flushed from TLB -system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.itb.read_accesses 0 # DTB read accesses -system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115862328 # ITB inst accesses -system.cpu.checker.itb.hits 115857502 # DTB hits -system.cpu.checker.itb.misses 4826 # DTB misses -system.cpu.checker.itb.accesses 115862328 # DTB accesses -system.cpu.checker.pwrStateResidencyTicks::ON 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.checker.numCycles 139109385 # number of cpu cycles simulated -system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 72426 # Table walker walks requested -system.cpu.dtb.walker.walksShort 72426 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29716 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23400 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 19310 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 53116 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 407.485503 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2469.018740 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-8191 51917 97.74% 97.74% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-16383 937 1.76% 99.51% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-24575 190 0.36% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-32767 37 0.07% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-40959 15 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::40960-49151 16 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 53116 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 17396 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 9637.387905 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7803.906851 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 6813.601039 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 15561 89.45% 89.45% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1740 10.00% 99.45% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-49151 86 0.49% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::49152-65535 2 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::245760-262143 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 17396 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 117727604724 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.629848 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.489627 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 117677681224 99.96% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 34838500 0.03% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 7318000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 4585500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 935500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 533500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1306000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 397000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 117727604724 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6471 81.85% 81.85% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1435 18.15% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7906 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72426 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72426 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7906 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7906 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 80332 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25423365 # DTB read hits -system.cpu.dtb.read_misses 62664 # DTB read misses -system.cpu.dtb.write_hits 19868926 # DTB write hits -system.cpu.dtb.write_misses 9762 # DTB write misses -system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4289 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 358 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2236 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1258 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25486029 # DTB read accesses -system.cpu.dtb.write_accesses 19878688 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45292291 # DTB hits -system.cpu.dtb.misses 72426 # DTB misses -system.cpu.dtb.accesses 45364717 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 12855 # Table walker walks requested -system.cpu.itb.walker.walksShort 12855 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3590 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7693 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 1572 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11283 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 605.778605 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2805.757421 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-8191 10907 96.67% 96.67% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-16383 327 2.90% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-24575 40 0.35% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-32767 5 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::81920-90111 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11283 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 4887 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 8961.019030 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7007.167188 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7172.888707 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 3327 68.08% 68.08% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 829 16.96% 85.04% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 682 13.96% 99.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::24576-32767 38 0.78% 99.77% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-40959 1 0.02% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::40960-49151 7 0.14% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::49152-57343 1 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 4887 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 23237381212 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.774797 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.417824 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 5234024500 22.52% 22.52% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 18002578212 77.47% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 696500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 46500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 23237381212 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2980 89.89% 89.89% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 335 10.11% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3315 # Table walker page sizes translated -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12855 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 12855 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3315 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3315 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 16170 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66060204 # ITB inst hits -system.cpu.itb.inst_misses 12855 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 128 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3013 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2175 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66073059 # ITB inst accesses -system.cpu.itb.hits 66060204 # DTB hits -system.cpu.itb.misses 12855 # DTB misses -system.cpu.itb.accesses 66073059 # DTB accesses -system.cpu.numPwrStateTransitions 6076 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 3038 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 887319797.866359 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17420812025.908409 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 2966 97.63% 97.63% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 66 2.17% 99.80% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499973328096 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 3038 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 132175550082 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2695677545918 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 264351157 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 105007140 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184198118 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46859222 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33067367 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 149125653 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6062128 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 177509 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8064 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 342285 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 500656 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 149 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66059105 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1061874 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6140 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 258192520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.869926 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.232240 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 159207105 61.66% 61.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29153243 11.29% 72.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14041371 5.44% 78.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55790801 21.61% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 258192520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.177261 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.696793 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78121728 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 109293057 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64347286 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3858820 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2571629 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3404933 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 467397 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157054266 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3508469 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2571629 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83876272 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10707182 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 75777880 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62454434 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 22805123 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146493829 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 914752 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 447933 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 65579 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 19295 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 20059867 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150297562 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 677265731 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164029738 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 11047 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141819290 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8478266 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2841903 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2646616 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13881588 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26350743 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21216202 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1694356 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2155521 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143287156 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2116266 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143106706 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 261772 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8147939 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14286308 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 122067 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 258192520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.554264 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.878016 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 169987358 65.84% 65.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45210540 17.51% 83.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31907168 12.36% 95.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10268019 3.98% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 819402 0.32% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 258192520 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7338606 32.76% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 32 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5623411 25.10% 57.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9440852 42.14% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95896760 67.01% 67.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 115009 0.08% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8592 0.01% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26141404 18.27% 85.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 20942604 14.63% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143106706 # Type of FU issued -system.cpu.iq.rate 0.541351 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22402901 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156547 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 567034934 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 153556562 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140052264 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35671 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13288 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11499 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165483986 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23284 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 324130 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1434023 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 698 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18538 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 619510 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 88631 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6598 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2571629 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 994929 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 316385 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145584227 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26350743 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21216202 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1093451 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17658 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 280514 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18538 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 277676 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 470698 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 748374 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142207045 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25746206 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 827350 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 180805 # number of nop insts executed -system.cpu.iew.exec_refs 46576895 # number of memory reference insts executed -system.cpu.iew.exec_branches 26509940 # Number of branches executed -system.cpu.iew.exec_stores 20830689 # Number of stores executed -system.cpu.iew.exec_rate 0.537948 # Inst execution rate -system.cpu.iew.wb_sent 141837731 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140063763 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63261975 # num instructions producing a value -system.cpu.iew.wb_consumers 95760288 # num instructions consuming a value -system.cpu.iew.wb_rate 0.529840 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660628 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 7362260 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1994199 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 714821 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255299551 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.538232 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.139550 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 181839086 71.23% 71.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43295063 16.96% 88.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15470047 6.06% 94.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4367483 1.71% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6400805 2.51% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1643674 0.64% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 799411 0.31% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 417134 0.16% 99.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1066848 0.42% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255299551 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113310545 # Number of instructions committed -system.cpu.commit.committedOps 137410384 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45513412 # Number of memory references committed -system.cpu.commit.loads 24916720 # Number of loads committed -system.cpu.commit.membars 814165 # Number of memory barriers committed -system.cpu.commit.branches 26044798 # Number of branches committed -system.cpu.commit.fp_insts 11492 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120233477 # Number of committed integer instructions. -system.cpu.commit.function_calls 4891928 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91774855 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 113526 0.08% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8591 0.01% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24916720 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20596692 14.99% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137410384 # Class of committed instruction -system.cpu.commit.bw_lim_events 1066848 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 376774257 # The number of ROB reads -system.cpu.rob.rob_writes 292425270 # The number of ROB writes -system.cpu.timesIdled 893722 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6158637 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5391355036 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113155640 # Number of Instructions Simulated -system.cpu.committedOps 137255479 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.336173 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.336173 # CPI: Total CPI of All Threads -system.cpu.ipc 0.428050 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.428050 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155596461 # number of integer regfile reads -system.cpu.int_regfile_writes 88540194 # number of integer regfile writes -system.cpu.fp_regfile_reads 9674 # number of floating regfile reads -system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502394912 # number of cc regfile reads -system.cpu.cc_regfile_writes 53149715 # number of cc regfile writes -system.cpu.misc_regfile_reads 449419252 # number of misc regfile reads -system.cpu.misc_regfile_writes 1520020 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 839084 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.954165 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40069527 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 839596 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.724771 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 270911500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.954165 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999910 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999910 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179200286 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179200286 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23273566 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23273566 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15547100 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15547100 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 345314 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 345314 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441102 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441102 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 459566 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 459566 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38820666 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38820666 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39165980 # number of overall hits -system.cpu.dcache.overall_hits::total 39165980 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 709196 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 709196 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3610101 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3610101 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177382 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177382 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26835 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26835 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4319297 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4319297 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4496679 # number of overall misses -system.cpu.dcache.overall_misses::total 4496679 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10317292500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10317292500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 150336233192 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 150336233192 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 369753500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 369753500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 213000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 213000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 160653525692 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 160653525692 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 160653525692 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 160653525692 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23982762 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23982762 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19157201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19157201 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 522696 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 522696 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467937 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 467937 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 459571 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 459571 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43139963 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43139963 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43662659 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43662659 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029571 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029571 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188446 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.188446 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339360 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.339360 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057347 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057347 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.100123 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.100123 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.102987 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.102987 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14547.871815 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14547.871815 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41643.220838 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41643.220838 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13778.777716 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13778.777716 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42600 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42600 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37194.368827 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37194.368827 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35727.150124 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35727.150124 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 590933 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7520 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.581516 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 696178 # number of writebacks -system.cpu.dcache.writebacks::total 696178 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295013 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 295013 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3309632 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3309632 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18459 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18459 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3604645 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3604645 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3604645 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3604645 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414183 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 414183 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300469 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300469 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119358 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119358 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8376 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8376 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 714652 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 714652 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 834010 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 834010 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5890415000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5890415000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13426039479 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13426039479 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1622684000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1622684000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 130358500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 130358500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 208000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 208000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19316454479 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19316454479 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20939138479 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20939138479 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6279502000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6279502000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6279502000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6279502000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017270 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017270 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015684 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015684 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228351 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228351 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017900 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017900 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016566 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016566 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019101 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019101 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14221.769121 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14221.769121 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44683.609554 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44683.609554 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13595.100454 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13595.100454 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15563.335721 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15563.335721 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41600 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41600 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27029.175709 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27029.175709 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25106.579632 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25106.579632 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201738.105182 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201738.105182 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.141098 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.141098 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1887810 # number of replacements -system.cpu.icache.tags.tagsinuse 511.341026 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64075895 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1888322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.932716 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 13715039500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.341026 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998713 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998713 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 67944454 # Number of tag accesses -system.cpu.icache.tags.data_accesses 67944454 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 64075895 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64075895 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64075895 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64075895 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64075895 # number of overall hits -system.cpu.icache.overall_hits::total 64075895 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1980206 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1980206 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1980206 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1980206 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1980206 # number of overall misses -system.cpu.icache.overall_misses::total 1980206 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26984355494 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26984355494 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26984355494 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26984355494 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26984355494 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26984355494 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66056101 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66056101 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66056101 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66056101 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66056101 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66056101 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029978 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029978 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029978 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029978 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029978 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.029978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13627.044607 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13627.044607 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13627.044607 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13627.044607 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13627.044607 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13627.044607 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2643 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.144000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1887810 # number of writebacks -system.cpu.icache.writebacks::total 1887810 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91852 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 91852 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 91852 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 91852 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 91852 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 91852 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1888354 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1888354 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1888354 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1888354 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1888354 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1888354 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24226536497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24226536497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24226536497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24226536497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24226536497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24226536497 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 229048500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 229048500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 229048500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 229048500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028587 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028587 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028587 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.028587 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028587 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.028587 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12829.446437 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12829.446437 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12829.446437 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12829.446437 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12829.446437 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12829.446437 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76273.226773 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76273.226773 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76273.226773 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76273.226773 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 103423 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65159.012032 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5300281 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 168782 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 31.403118 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 93779484000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 9.961762 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 3.729813 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10177.791609 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 54967.528848 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000152 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000057 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.155301 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.838738 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994248 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65345 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5571 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59599 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997086 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43992446 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43992446 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54341 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10212 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 64553 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 696178 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 696178 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1850381 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1850381 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 2757 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 2757 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 158824 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 158824 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1868353 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1868353 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527348 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 527348 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 54341 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10212 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1868353 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 686172 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2619078 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 54341 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10212 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1868353 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 686172 # number of overall hits -system.cpu.l2cache.overall_hits::total 2619078 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 16 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 22 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 11 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 11 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 139010 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 139010 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19937 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 19937 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14436 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 14436 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 16 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 19937 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 153446 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 173405 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 16 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 19937 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 153446 # number of overall misses -system.cpu.l2cache.overall_misses::total 173405 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1497500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 502000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1999500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 320500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 320500 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 167000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 167000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11275740500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11275740500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1659086000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1659086000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1242944500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1242944500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1497500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 502000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1659086000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12518685000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14179770500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1497500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 502000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1659086000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12518685000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14179770500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 54357 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10218 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 64575 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 696178 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 696178 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1850381 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1850381 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2768 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2768 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 297834 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 297834 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1888290 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1888290 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 541784 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 541784 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54357 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10218 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1888290 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 839618 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2792483 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54357 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10218 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1888290 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 839618 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2792483 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000294 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000587 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000341 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003974 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003974 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.466737 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.466737 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010558 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010558 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026645 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026645 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000294 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000587 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010558 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.182757 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.062097 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000294 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000587 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010558 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.182757 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.062097 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93593.750000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83666.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 90886.363636 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29136.363636 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29136.363636 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 83500 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 83500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81114.599669 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81114.599669 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83216.431760 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83216.431760 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86100.339429 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86100.339429 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93593.750000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83666.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83216.431760 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81583.651578 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81772.558461 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93593.750000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83666.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83216.431760 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81583.651578 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81772.558461 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 95172 # number of writebacks -system.cpu.l2cache.writebacks::total 95172 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 23 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 23 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 112 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 112 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 135 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 135 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 16 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 22 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 11 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139010 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 139010 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19914 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19914 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14324 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14324 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 16 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 19914 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 153334 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 173270 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 16 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 19914 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 153334 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 173270 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34130 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61714 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1337500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 442000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1779500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 210500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 210500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 147000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 147000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9885640500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9885640500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1458480000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1458480000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1091561500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1091561500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1337500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 442000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1458480000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10977202000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12437461500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1337500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 442000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1458480000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10977202000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12437461500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 191510500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5890404500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6081915000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 191510500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5890404500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6081915000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000294 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000587 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000341 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003974 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003974 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.466737 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.466737 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010546 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010546 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026439 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026439 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000294 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000587 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010546 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.182624 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.062049 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000294 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000587 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010546 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.182624 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.062049 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80886.363636 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19136.363636 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19136.363636 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 73500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 73500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71114.599669 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71114.599669 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73238.927388 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73238.927388 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76205.075398 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76205.075398 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73238.927388 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.136565 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71780.813182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73238.927388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.136565 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71780.813182 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63773.060273 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189237.783917 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178198.505713 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63773.060273 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100328.805505 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98550.004861 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5488560 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2760615 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44763 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 238 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 238 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 129622 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2559974 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 791350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1887810 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 151157 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2768 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 297834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 297834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1888354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 542004 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 4368 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5670459 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2641503 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130873 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8472029 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241718384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98487773 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 217428 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 340464457 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 139207 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6232532 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2995964 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025358 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.157210 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2919992 97.46% 97.46% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 75972 2.54% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2995964 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5405204997 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 383377 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2836467127 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1305988986 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 18982487 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 76565899 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 30182 # Transaction distribution -system.iobus.trans_dist::ReadResp 30182 # Transaction distribution -system.iobus.trans_dist::WriteReq 59014 # Transaction distribution -system.iobus.trans_dist::WriteResp 59014 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 43094500 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 101000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 325500 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 649500 # Layer occupancy (ticks) -system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6172500 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33854000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187760330 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36423 # number of replacements -system.iocache.tags.tagsinuse 1.000676 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 252706881000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.000676 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328113 # Number of tag accesses -system.iocache.tags.data_accesses 328113 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses -system.iocache.ReadReq_misses::total 233 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36457 # number of demand (read+write) misses -system.iocache.demand_misses::total 36457 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36457 # number of overall misses -system.iocache.overall_misses::total 36457 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28964877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28964877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4277512453 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4277512453 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4306477330 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4306477330 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4306477330 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4306477330 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36457 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36457 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36457 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36457 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124312.776824 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124312.776824 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.039007 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118085.039007 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118124.841046 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118124.841046 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118124.841046 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118124.841046 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36457 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36457 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36457 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36457 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17314877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17314877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2464212681 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2464212681 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2481527558 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2481527558 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2481527558 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2481527558 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74312.776824 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74312.776824 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68027.072687 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68027.072687 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68067.245193 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68067.245193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68067.245193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68067.245193 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 349590 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 144366 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 34130 # Transaction distribution -system.membus.trans_dist::ReadResp 68622 # Transaction distribution -system.membus.trans_dist::WriteReq 27584 # Transaction distribution -system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 131362 # Transaction distribution -system.membus.trans_dist::CleanEvict 8484 # Transaction distribution -system.membus.trans_dist::UpgradeReq 130 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 138891 # Transaction distribution -system.membus.trans_dist::ReadExResp 138891 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34493 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 573007 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72895 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72895 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645902 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17222620 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17385997 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19703117 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 497 # Total snoops (count) -system.membus.snoopTraffic 31680 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 271454 # Request fanout histogram -system.membus.snoop_fanout::mean 0.017933 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.132708 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 266586 98.21% 98.21% # Request fanout histogram -system.membus.snoop_fanout::1 4868 1.79% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 271454 # Request fanout histogram -system.membus.reqLayer0.occupancy 84464500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1723499 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 908168519 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1012308500 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1273123 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks -system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks -system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks -system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks -system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks -system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks -system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks -system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed - ----------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/EMPTY b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/EMPTY new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/EMPTY diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini deleted file mode 100644 index b338c1186..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ /dev/null @@ -1,2973 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxArmSystem -children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain -atags_addr=134217728 -boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb -early_kernel_symbols=false -enable_context_switch_stats_dump=false -eventq_index=0 -exit_on_work_items=false -flags_addr=469827632 -gic_cpu_addr=738205696 -have_large_asid_64=false -have_lpae=true -have_security=false -have_virtualization=false -highest_el_is_64=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 -kernel_addr_check=true -load_addr_mask=268435455 -load_offset=2147483648 -machine_type=VExpress_EMM -mem_mode=atomic -mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.nvmem system.realview.vram -mmap_using_noreserve=false -multi_proc=true -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -panic_on_oops=true -panic_on_panic=true -phys_addr_range_64=40 -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -reset_addr_64=0 -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[1] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.cf0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.cf0.image - -[system.cf0.image] -type=CowDiskImage -children=child -child=system.cf0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.cf0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img -read_only=true - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu0] -type=AtomicSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu0.dstage2_mmu -dtb=system.cpu0.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu0.interrupts -isa=system.cpu0.isa -istage2_mmu=system.cpu0.istage2_mmu -itb=system.cpu0.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu0.tracer -width=1 -workload= -dcache_port=system.cpu0.dcache.cpu_side -icache_port=system.cpu0.icache.cpu_side - -[system.cpu0.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.slave[1] - -[system.cpu0.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu0.dtb - -[system.cpu0.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu0.dstage2_mmu.stage2_tlb.walker - -[system.cpu0.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu0.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu0.dtb.walker - -[system.cpu0.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.toL2Bus.slave[3] - -[system.cpu0.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.slave[0] - -[system.cpu0.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu0.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu0.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu0.itb - -[system.cpu0.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu0.istage2_mmu.stage2_tlb.walker - -[system.cpu0.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu0.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu0.itb.walker - -[system.cpu0.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.toL2Bus.slave[2] - -[system.cpu0.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu1] -type=TimingSimpleCPU -children=dstage2_mmu dtb isa istage2_mmu itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu1.dstage2_mmu -dtb=system.cpu1.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts= -isa=system.cpu1.isa -istage2_mmu=system.cpu1.istage2_mmu -itb=system.cpu1.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=true -system=system -tracer=system.cpu1.tracer -workload= - -[system.cpu1.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu1.dtb - -[system.cpu1.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu1.dstage2_mmu.stage2_tlb.walker - -[system.cpu1.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu1.dtb.walker - -[system.cpu1.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu1.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu1.itb - -[system.cpu1.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu1.istage2_mmu.stage2_tlb.walker - -[system.cpu1.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu1.itb.walker - -[system.cpu1.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu2] -type=MinorCPU -children=branchPred dstage2_mmu dtb executeFuncUnits isa istage2_mmu itb tracer -branchPred=system.cpu2.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu2.dstage2_mmu -dtb=system.cpu2.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu2.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts= -isa=system.cpu2.isa -istage2_mmu=system.cpu2.istage2_mmu -itb=system.cpu2.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=true -system=system -threadPolicy=RoundRobin -tracer=system.cpu2.tracer -workload= - -[system.cpu2.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu2.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu2.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu2.dtb - -[system.cpu2.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu2.dstage2_mmu.stage2_tlb.walker - -[system.cpu2.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu2.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu2.dtb.walker - -[system.cpu2.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu2.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu2.executeFuncUnits.funcUnits0 system.cpu2.executeFuncUnits.funcUnits1 system.cpu2.executeFuncUnits.funcUnits2 system.cpu2.executeFuncUnits.funcUnits3 system.cpu2.executeFuncUnits.funcUnits4 system.cpu2.executeFuncUnits.funcUnits5 system.cpu2.executeFuncUnits.funcUnits6 - -[system.cpu2.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu2.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu2.executeFuncUnits.funcUnits0.timings - -[system.cpu2.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu2.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu2.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu2.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu2.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu2.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu2.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu2.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu2.executeFuncUnits.funcUnits1.timings - -[system.cpu2.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu2.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu2.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu2.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu2.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu2.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu2.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu2.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu2.executeFuncUnits.funcUnits2.timings - -[system.cpu2.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu2.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu2.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu2.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu2.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu2.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu2.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu2.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu2.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu2.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu2.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu2.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu2.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu2.executeFuncUnits.funcUnits4.timings - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu2.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu2.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu2.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu2.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu2.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu2.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu2.executeFuncUnits.funcUnits5.timings - -[system.cpu2.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu2.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu2.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu2.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu2.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu2.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu2.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu2.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu2.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu2.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu2.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu2.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu2.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu2.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu2.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu2.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu2.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu2.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu2.itb - -[system.cpu2.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu2.istage2_mmu.stage2_tlb.walker - -[system.cpu2.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu2.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu2.itb.walker - -[system.cpu2.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu2.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu3] -type=DerivO3CPU -children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu3.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu3.dstage2_mmu -dtb=system.cpu3.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu3.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts= -isa=system.cpu3.isa -issueToExecuteDelay=1 -issueWidth=8 -istage2_mmu=system.cpu3.istage2_mmu -itb=system.cpu3.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=1280 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=true -system=system -tracer=system.cpu3.tracer -trapLatency=13 -wbWidth=8 -workload= - -[system.cpu3.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu3.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu3.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu3.dtb - -[system.cpu3.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu3.dstage2_mmu.stage2_tlb.walker - -[system.cpu3.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu3.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu3.dtb.walker - -[system.cpu3.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu3.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 -eventq_index=0 - -[system.cpu3.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu3.fuPool.FUList0.opList - -[system.cpu3.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 - -[system.cpu3.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu3.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu3.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 - -[system.cpu3.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu3.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu3.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu3.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 - -[system.cpu3.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu3.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu3.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu3.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu3.fuPool.FUList4.opList - -[system.cpu3.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 - -[system.cpu3.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu3.fuPool.FUList6.opList - -[system.cpu3.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 - -[system.cpu3.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu3.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu3.fuPool.FUList8.opList - -[system.cpu3.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu3.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu3.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu3.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu3.itb - -[system.cpu3.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu3.istage2_mmu.stage2_tlb.walker - -[system.cpu3.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu3.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu3.itb.walker - -[system.cpu3.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu3.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=2147483648:2415919103 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[3] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.l2c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.l2c.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - -[system.l2c.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access=warn -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.075000 -IDD02=0.000000 -IDD2N=0.050000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.000000 -IDD2P12=0.000000 -IDD3N=0.057000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.000000 -IDD3P12=0.000000 -IDD4R=0.187000 -IDD4R2=0.000000 -IDD4W=0.165000 -IDD4W2=0.000000 -IDD5=0.220000 -IDD52=0.000000 -IDD6=0.000000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=2147483648:2415919103 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=0 -tXPDLL=0 -tXS=0 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[5] - -[system.realview] -type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.realview.aaci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470024192 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[18] - -[system.realview.cf_ctrl] -type=IdeController -BAR0=471465984 -BAR0LegacyIO=true -BAR0Size=256 -BAR1=471466240 -BAR1LegacyIO=true -BAR1Size=4096 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=1 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=2 -default_p_state=UNDEFINED -disks= -eventq_index=0 -host=system.realview.pci_host -io_shift=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=2 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[2] -pio=system.iobus.master[9] - -[system.realview.clcd] -type=Pl111 -amba_id=1315089 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=46 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471793664 -pio_latency=10000 -pixel_clock=41667 -power_model=Null -system=system -vnc=system.vncserver -dma=system.iobus.slave[1] -pio=system.iobus.master[5] - -[system.realview.dcc] -type=SubSystem -children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys -eventq_index=0 -thermal_domain=Null - -[system.realview.dcc.osc_cpu] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_ddr] -type=RealViewOsc -dcc=0 -device=8 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_hsbm] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_pxl] -type=RealViewOsc -dcc=0 -device=5 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_smb] -type=RealViewOsc -dcc=0 -device=6 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_sys] -type=RealViewOsc -dcc=0 -device=7 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.energy_ctrl] -type=EnergyCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dvfs_handler=system.dvfs_handler -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470286336 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[22] - -[system.realview.ethernet] -type=IGbE -BAR0=0 -BAR0LegacyIO=false -BAR0Size=131072 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=0 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=4213 -ExpansionROM=0 -HeaderType=0 -InterruptLine=1 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=255 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=0 -SubClassCode=0 -SubsystemID=4104 -SubsystemVendorID=32902 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -eventq_index=0 -fetch_comp_delay=10000 -fetch_delay=10000 -hardware_address=00:90:00:00:00:01 -host=system.realview.pci_host -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -phy_epid=896 -phy_pid=680 -pio_latency=30000 -power_model=Null -rx_desc_cache_size=64 -rx_fifo_size=393216 -rx_write_delay=0 -system=system -tx_desc_cache_size=64 -tx_fifo_size=393216 -tx_read_delay=0 -wb_comp_delay=10000 -wb_delay=10000 -dma=system.iobus.slave[4] -pio=system.iobus.master[24] - -[system.realview.generic_timer] -type=GenericTimer -eventq_index=0 -gic=system.realview.gic -int_phys=29 -int_virt=27 -system=system - -[system.realview.gic] -type=Pl390 -clk_domain=system.clk_domain -cpu_addr=738205696 -cpu_pio_delay=10000 -default_p_state=UNDEFINED -dist_addr=738201600 -dist_pio_delay=10000 -eventq_index=0 -gem5_extensions=true -int_latency=10000 -it_lines=128 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -platform=system.realview -power_model=Null -system=system -pio=system.membus.master[2] - -[system.realview.hdlcd] -type=HDLcd -amba_id=1314816 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=117 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=721420288 -pio_latency=10000 -pixel_buffer_size=2048 -pixel_chunk=32 -power_model=Null -pxl_clk=system.realview.dcc.osc_pxl -system=system -vnc=system.vncserver -workaround_dma_line_count=true -workaround_swap_rb=true -dma=system.membus.slave[0] -pio=system.iobus.master[6] - -[system.realview.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=2 -InterruptPin=2 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.cf0 -eventq_index=0 -host=system.realview.pci_host -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[3] -pio=system.iobus.master[23] - -[system.realview.kmi0] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=44 -is_mouse=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470155264 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[7] - -[system.realview.kmi1] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=45 -is_mouse=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470220800 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[8] - -[system.realview.l2x0_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=739246080 -pio_latency=100000 -pio_size=4095 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.realview.lan_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=436207616 -pio_latency=100000 -pio_size=65535 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.realview.local_cpu_timer] -type=CpuLocalTimer -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num_timer=29 -int_num_watchdog=30 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=738721792 -pio_latency=100000 -power_model=Null -system=system -pio=system.membus.master[4] - -[system.realview.mcc] -type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl -eventq_index=0 -thermal_domain=Null - -[system.realview.mcc.osc_clcd] -type=RealViewOsc -dcc=0 -device=1 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_mcc] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_peripheral] -type=RealViewOsc -dcc=0 -device=2 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_system_bus] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.temp_crtl] -type=RealViewTemperatureSensor -dcc=0 -device=0 -eventq_index=0 -parent=system.realview.realview_io -position=0 -site=0 -system=system - -[system.realview.mmc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470089728 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.realview.nvmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:67108863 -port=system.membus.master[1] - -[system.realview.pci_host] -type=GenericPciHost -clk_domain=system.clk_domain -conf_base=805306368 -conf_device_bits=16 -conf_size=268435456 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=0 -pci_pio_base=0 -platform=system.realview -power_model=Null -system=system -pio=system.iobus.master[2] - -[system.realview.realview_io] -type=RealViewCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -idreg=35979264 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469827584 -pio_latency=100000 -power_model=Null -proc_id0=335544320 -proc_id1=335544320 -system=system -pio=system.iobus.master[1] - -[system.realview.rtc] -type=PL031 -amba_id=3412017 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=36 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471269376 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[10] - -[system.realview.sp810_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469893120 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[16] - -[system.realview.timer0] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=34 -int_num1=34 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470876160 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[3] - -[system.realview.timer1] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=35 -int_num1=35 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470941696 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[4] - -[system.realview.uart] -type=Pl011 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -end_on_eot=false -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=37 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470351872 -pio_latency=100000 -platform=system.realview -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[0] - -[system.realview.uart1_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470417408 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[13] - -[system.realview.uart2_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470482944 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[14] - -[system.realview.uart3_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470548480 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[15] - -[system.realview.usb_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=452984832 -pio_latency=100000 -pio_size=131071 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.realview.vgic] -type=VGic -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -hv_addr=738213888 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_delay=10000 -platform=system.realview -power_model=Null -ppint=25 -system=system -vcpu_addr=738222080 -pio=system.membus.master[3] - -[system.realview.vram] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=402653184:436207615 -port=system.iobus.master[11] - -[system.realview.watchdog_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470745088 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[17] - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port - -[system.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.vncserver] -type=VncServer -eventq_index=0 -frame_capture=false -number=0 -port=5900 - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr deleted file mode 100755 index 3ab4a9e43..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr +++ /dev/null @@ -1,136 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting vnc client connections -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Existing EnergyCtrl, but no enabled DVFSHandler found. -warn: Not doing anything for miscreg ACTLR -warn: Not doing anything for write of miscreg ACTLR -warn: The clidr register always reports 0 caches. -warn: clidr LoUIS field of 0b001 to match current ARM implementations. -warn: The csselr register isn't implemented. -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr dccimvac' unimplemented -warn: Tried to read RealView I/O at offset 0x60 that doesn't exist -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: ClockedObject: Already in the requested power state, request ignored -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] -warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] -warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] -warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] -warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] -WARNING: Bank is already active! -Command: 0, Timestamp: 10945, Bank: 2 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 11030, Bank: 2 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: Returning zero for read from miscreg pmcr -warn: Ignoring write to miscreg pmcntenclr -warn: Ignoring write to miscreg pmintenclr -warn: Ignoring write to miscreg pmovsr -warn: Ignoring write to miscreg pmcr -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is already active! -Command: 0, Timestamp: 8588, Bank: 0 -warn: CP14 unimplemented crn[10], opc1[0], crm[4], opc2[3] -warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2] -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5] -warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3] -warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3] -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: instruction 'mcr bpiall' unimplemented -warn: CP14 unimplemented crn[14], opc1[7], crm[1], opc2[0] -warn: CP14 unimplemented crn[14], opc1[7], crm[14], opc2[7] -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout deleted file mode 100755 index 7841978fe..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ /dev/null @@ -1,11 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:35 -gem5 executing on e108600-lin, pid 12240 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-switcheroo-full - -Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt deleted file mode 100644 index b158166a6..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ /dev/null @@ -1,3159 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.823713 # Number of seconds simulated -sim_ticks 2823712531500 # Number of ticks simulated -final_tick 2823712531500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 235362 # Simulator instruction rate (inst/s) -host_op_rate 285496 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5406413351 # Simulator tick rate (ticks/s) -host_mem_usage 591960 # Number of bytes of host memory used -host_seconds 522.29 # Real time elapsed on the host -sim_insts 122926882 # Number of instructions simulated -sim_ops 149111695 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 537508 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3136100 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 121472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 903168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 343232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1991872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 4544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 387072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 3526656 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10954952 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 537508 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 121472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 343232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 387072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1389284 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8237952 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8255476 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16852 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 49521 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1898 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 14112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 28 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5363 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 31123 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 71 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 6048 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 55104 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180144 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 128718 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 190355 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1110630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 43019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 319851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 121553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 705409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 137079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 1248943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3879627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 190355 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 43019 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 121553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 137079 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 492006 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2917419 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6206 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2923625 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2917419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 190355 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1116836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 43019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 319851 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 635 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 121553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 705409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 137079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 1248943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6803252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 113749 # Number of read requests accepted -system.physmem.writeReqs 69024 # Number of write requests accepted -system.physmem.readBursts 113749 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 69024 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 7272896 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue -system.physmem.bytesWritten 4416768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 7279936 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4417536 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 7641 # Per bank write bursts -system.physmem.perBankRdBursts::1 6876 # Per bank write bursts -system.physmem.perBankRdBursts::2 7409 # Per bank write bursts -system.physmem.perBankRdBursts::3 7470 # Per bank write bursts -system.physmem.perBankRdBursts::4 7337 # Per bank write bursts -system.physmem.perBankRdBursts::5 7030 # Per bank write bursts -system.physmem.perBankRdBursts::6 7627 # Per bank write bursts -system.physmem.perBankRdBursts::7 7716 # Per bank write bursts -system.physmem.perBankRdBursts::8 6884 # Per bank write bursts -system.physmem.perBankRdBursts::9 7545 # Per bank write bursts -system.physmem.perBankRdBursts::10 7008 # Per bank write bursts -system.physmem.perBankRdBursts::11 6374 # Per bank write bursts -system.physmem.perBankRdBursts::12 6408 # Per bank write bursts -system.physmem.perBankRdBursts::13 7193 # Per bank write bursts -system.physmem.perBankRdBursts::14 6835 # Per bank write bursts -system.physmem.perBankRdBursts::15 6286 # Per bank write bursts -system.physmem.perBankWrBursts::0 4484 # Per bank write bursts -system.physmem.perBankWrBursts::1 4020 # Per bank write bursts -system.physmem.perBankWrBursts::2 4489 # Per bank write bursts -system.physmem.perBankWrBursts::3 4613 # Per bank write bursts -system.physmem.perBankWrBursts::4 4310 # Per bank write bursts -system.physmem.perBankWrBursts::5 4320 # Per bank write bursts -system.physmem.perBankWrBursts::6 4621 # Per bank write bursts -system.physmem.perBankWrBursts::7 4483 # Per bank write bursts -system.physmem.perBankWrBursts::8 4167 # Per bank write bursts -system.physmem.perBankWrBursts::9 4860 # Per bank write bursts -system.physmem.perBankWrBursts::10 4381 # Per bank write bursts -system.physmem.perBankWrBursts::11 3929 # Per bank write bursts -system.physmem.perBankWrBursts::12 3827 # Per bank write bursts -system.physmem.perBankWrBursts::13 4631 # Per bank write bursts -system.physmem.perBankWrBursts::14 4137 # Per bank write bursts -system.physmem.perBankWrBursts::15 3740 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2822140482500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 113749 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 69024 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 85840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 24773 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39259 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 297.757559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.671784 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.464821 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15432 39.31% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9477 24.14% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3788 9.65% 73.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2095 5.34% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1555 3.96% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1004 2.56% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 603 1.54% 86.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 654 1.67% 88.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4651 11.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39259 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3667 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.985274 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 628.070623 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 3665 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-38911 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3667 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3667 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.819744 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.710166 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 9.565148 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 9 0.25% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 3 0.08% 0.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 3 0.08% 0.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 6 0.16% 0.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3283 89.53% 90.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 35 0.95% 91.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 47 1.28% 92.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 39 1.06% 93.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 88 2.40% 95.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 43 1.17% 96.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 6 0.16% 97.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.27% 97.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 7 0.19% 97.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.14% 97.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.11% 97.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.08% 97.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 62 1.69% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.03% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.03% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.11% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.11% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3667 # Writes before turning the bus around for reads -system.physmem.totQLat 1342938250 # Total ticks spent queuing -system.physmem.totMemAccLat 3473669500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 568195000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11817.58 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30567.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.55 # Average write queue length when enqueuing -system.physmem.readRowHits 93703 # Number of row buffer hits during reads -system.physmem.writeRowHits 49689 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.46 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.99 # Row buffer hit rate for writes -system.physmem.avgGap 15440685.89 # Average gap between requests -system.physmem.pageHitRate 78.50 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 158064480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 86055750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 461026800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 229003200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 179708321520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72025489845 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1621445025000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1874112986595 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.488376 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2641083296250 # Time in different power states -system.physmem_0.memoryStateTime::REF 91875160000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 18501220250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 138733560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 75508125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 425357400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 218194560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 179708321520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 71152837515 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1620392151000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1872111103680 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.495866 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2642358679500 # Time in different power states -system.physmem_1.memoryStateTime::REF 91875160000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17221255250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 4966 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 4966 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 4966 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 4966 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 4966 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 56881367876 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.265672 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -15111782124 -26.57% -26.57% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 71993150000 126.57% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 56881367876 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 2795 68.22% 68.22% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1302 31.78% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4097 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4966 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4966 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4097 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4097 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9063 # Table walker requests started/completed, data/inst -system.cpu0.dtb.inst_hits 0 # ITB inst hits -system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12103158 # DTB read hits -system.cpu0.dtb.read_misses 4250 # DTB read misses -system.cpu0.dtb.write_hits 9145748 # DTB write hits -system.cpu0.dtb.write_misses 716 # DTB write misses -system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2759 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 823 # Number of TLB faults due to prefetch -system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 174 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12107408 # DTB read accesses -system.cpu0.dtb.write_accesses 9146464 # DTB write accesses -system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21248906 # DTB hits -system.cpu0.dtb.misses 4966 # DTB misses -system.cpu0.dtb.accesses 21253872 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 2431 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2431 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2431 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2431 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2431 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 56881367876 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.265674 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -15111901124 -26.57% -26.57% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 71993269000 126.57% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 56881367876 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1314 74.83% 74.83% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 442 25.17% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1756 # Table walker page sizes translated -system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2431 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2431 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1756 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1756 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4187 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56926912 # ITB inst hits -system.cpu0.itb.inst_misses 2431 # ITB inst misses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 362 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1695 # Number of entries that have been flushed from TLB -system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56929343 # ITB inst accesses -system.cpu0.itb.hits 56926912 # DTB hits -system.cpu0.itb.misses 2431 # DTB misses -system.cpu0.itb.accesses 56929343 # DTB accesses -system.cpu0.numPwrStateTransitions 2564 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1282 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 2124006318.198128 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 53204391855.203163 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1267 98.83% 98.83% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 11 0.86% 99.69% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.08% 99.77% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.08% 99.84% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.08% 99.92% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 1 0.08% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 1799910947501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1282 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 100736431570 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2722976099930 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 68779411 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3087 # number of quiesce instructions executed -system.cpu0.committedInsts 55462034 # Number of instructions committed -system.cpu0.committedOps 67230601 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 59006165 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4380 # Number of float alu accesses -system.cpu0.num_func_calls 5788069 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7355854 # number of instructions that are conditional controls -system.cpu0.num_int_insts 59006165 # number of integer instructions -system.cpu0.num_fp_insts 4380 # number of float instructions -system.cpu0.num_int_register_reads 108801460 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41139310 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3339 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1042 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 204596465 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 24709161 # number of times the CC registers were written -system.cpu0.num_mem_refs 21836532 # number of memory refs -system.cpu0.num_load_insts 12252554 # Number of load instructions -system.cpu0.num_store_insts 9583978 # Number of store instructions -system.cpu0.num_idle_cycles 64960338.337804 # Number of idle cycles -system.cpu0.num_busy_cycles 3819072.662196 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055526 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944474 # Percentage of idle cycles -system.cpu0.Branches 13460127 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2178 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46428516 67.96% 67.96% # Class of executed instruction -system.cpu0.op_class::IntMult 50840 0.07% 68.03% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.03% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3886 0.01% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.04% # Class of executed instruction -system.cpu0.op_class::MemRead 12252554 17.93% 85.97% # Class of executed instruction -system.cpu0.op_class::MemWrite 9583978 14.03% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68321952 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 833218 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.996713 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 45933242 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 833730 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.093666 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.881738 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.691774 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.820044 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 13.603157 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.941175 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022835 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009414 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.026569 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 193157378 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 193157378 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 11470530 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 3604905 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4052935 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 6701965 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25830335 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 8807060 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 2683880 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3142868 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 4165696 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18799504 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178529 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 56901 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 67360 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 86083 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 388873 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 216810 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 75069 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 70446 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 88639 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 450964 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 217842 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 76721 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73321 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 92790 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460674 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20277590 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 6288785 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7195803 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 10867661 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 44629839 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20456119 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 6345686 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7263163 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 10953744 # number of overall hits -system.cpu0.dcache.overall_hits::total 45018712 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 170861 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 52117 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 78041 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 219706 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 520725 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 112296 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 34780 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 103289 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 1226440 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1476805 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 53971 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 19499 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 19151 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 42439 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 135060 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3703 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2347 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3778 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8109 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17937 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu3.data 27 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 283157 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 86897 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 181330 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu3.data 1446146 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1997530 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 337128 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 106396 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 200481 # number of overall misses -system.cpu0.dcache.overall_misses::cpu3.data 1488585 # number of overall misses -system.cpu0.dcache.overall_misses::total 2132590 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 838773500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1135742500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3358270500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5332786500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1269362500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 5008758996 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 61128343835 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 67406465331 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28849500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 56408000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 111440000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 196697500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 509500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 509500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 2108136000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 6144501496 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu3.data 64486614335 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 72739251831 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 2108136000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 6144501496 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu3.data 64486614335 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 72739251831 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11641391 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 3657022 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4130976 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu3.data 6921671 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26351060 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 8919356 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 2718660 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3246157 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu3.data 5392136 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 20276309 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 232500 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 76400 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 86511 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 128522 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 523933 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 220513 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 77416 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 74224 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 96748 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 468901 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 217843 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 76721 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73321 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 92817 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460702 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 20560747 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 6375682 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7377133 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu3.data 12313807 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 46627369 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 20793247 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 6452082 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7463644 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu3.data 12442329 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 47151302 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014677 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.014251 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.018892 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.031742 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.019761 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012590 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.012793 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.031819 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.227450 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.072834 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.232133 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.255223 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.221371 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.330208 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.257781 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016793 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.030317 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050900 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.083816 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038253 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000005 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000291 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000061 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013772 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013629 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.024580 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu3.data 0.117441 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.042840 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.016213 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.016490 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.026861 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu3.data 0.119639 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.045229 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16094.048007 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14553.151549 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15285.292618 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10241.080225 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36496.909143 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48492.666170 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 49842.098949 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45643.443333 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12292.074989 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14930.651138 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13742.754964 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10966.019959 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 18870.370370 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18196.428571 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24260.170086 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 33885.741444 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44592.049720 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36414.597944 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19814.053160 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30648.797123 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43320.747109 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34108.408945 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 335851 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 30410 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 12618 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 677 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 26.616817 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 44.918759 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 692039 # number of writebacks -system.cpu0.dcache.writebacks::total 692039 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 103 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 3007 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 107263 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 110373 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 47662 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1129952 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1177614 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1644 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2326 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5317 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9287 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 103 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 50669 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu3.data 1237215 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1287987 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 103 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 50669 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu3.data 1237215 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1287987 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 52014 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 75034 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 112443 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 239491 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 34780 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 55627 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 96488 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 186895 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 19172 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 15769 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 29454 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 64395 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 703 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1452 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 2792 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4947 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 27 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 27 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 86794 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 130661 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu3.data 208931 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 426386 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 105966 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 146430 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu3.data 238385 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 490781 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 3424 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 7112 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 7739 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18275 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 2828 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5192 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6207 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14227 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 6252 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 12304 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 13946 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32502 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 785366000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1020201000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1616061500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3421628500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1234582500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2622763500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 4843611917 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8700957917 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 247389500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 224319000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 453567500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 925276000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9229000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 27290500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 39997500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76517000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 482500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 482500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2019948500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3642964500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6459673417 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12122586417 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2267338000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3867283500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 6913240917 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13047862417 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 601508000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1489621000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1663692500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3754821500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 601508000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1489621000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1663692500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3754821500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014223 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018164 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016245 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009088 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012793 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017136 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017894 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009217 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.250942 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.182277 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.229175 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.122907 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.009081 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019562 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.028858 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010550 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000291 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000059 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013613 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017712 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016967 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.009145 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016424 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019619 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019159 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.010409 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15099.127158 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13596.516246 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14372.273063 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14287.085945 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35496.909143 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47149.109246 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50199.111983 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46555.327414 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12903.687670 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14225.315492 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15399.181775 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14368.755338 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13128.022760 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 18795.110193 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14325.752149 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15467.353952 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 17870.370370 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 17870.370370 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23272.904809 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27881.039484 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 30917.735602 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28431.014191 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21396.844271 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26410.458922 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29000.318464 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26585.915952 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175674.065421 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 209451.771654 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 214975.125985 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205462.188782 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 96210.492642 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 121068.026658 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 119295.317654 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115525.859947 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1969505 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.471624 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 93098332 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1970017 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 47.257629 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12499756500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 436.760332 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 13.051317 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 24.695920 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 36.964055 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.853048 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.025491 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.048234 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.072195 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998968 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 260 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 97080848 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 97080848 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 56184409 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 17633594 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 9977155 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu3.inst 9303174 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 93098332 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56184409 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 17633594 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 9977155 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu3.inst 9303174 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 93098332 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56184409 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 17633594 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 9977155 # number of overall hits -system.cpu0.icache.overall_hits::cpu3.inst 9303174 # number of overall hits -system.cpu0.icache.overall_hits::total 93098332 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 744259 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 211927 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 469274 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu3.inst 586995 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2012455 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 744259 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 211927 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 469274 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu3.inst 586995 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2012455 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 744259 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 211927 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 469274 # number of overall misses -system.cpu0.icache.overall_misses::cpu3.inst 586995 # number of overall misses -system.cpu0.icache.overall_misses::total 2012455 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2897125000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6498329500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 7981353488 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 17376807988 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2897125000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 6498329500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu3.inst 7981353488 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 17376807988 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2897125000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 6498329500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu3.inst 7981353488 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 17376807988 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 56928668 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 17845521 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 10446429 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu3.inst 9890169 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 95110787 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 56928668 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 17845521 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 10446429 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu3.inst 9890169 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 95110787 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 56928668 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 17845521 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 10446429 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu3.inst 9890169 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 95110787 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013074 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011876 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.044922 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.059351 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.021159 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013074 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011876 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.044922 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu3.inst 0.059351 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.021159 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013074 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011876 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.044922 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu3.inst 0.059351 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.021159 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13670.391220 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13847.623137 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13596.970141 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8634.631824 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13670.391220 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13847.623137 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13596.970141 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8634.631824 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13670.391220 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13847.623137 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13596.970141 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8634.631824 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4282 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 243 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.621399 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1969505 # number of writebacks -system.cpu0.icache.writebacks::total 1969505 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 42394 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 42394 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu3.inst 42394 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 42394 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu3.inst 42394 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 42394 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 211927 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 469274 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 544601 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1225802 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 211927 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 469274 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu3.inst 544601 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1225802 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 211927 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 469274 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu3.inst 544601 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1225802 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2685198000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6029055500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7046769990 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 15761023490 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2685198000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6029055500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7046769990 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 15761023490 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2685198000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6029055500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7046769990 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 15761023490 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.044922 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.055065 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012888 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.044922 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.055065 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.012888 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.044922 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.055065 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.012888 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12670.391220 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12847.623137 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12939.326204 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12857.723751 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12670.391220 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12847.623137 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12939.326204 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12857.723751 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12670.391220 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12847.623137 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12939.326204 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12857.723751 # average overall mshr miss latency -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 2001 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 2001 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 565 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1436 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 2001 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 2001 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 2001 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1629 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10353.898097 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9102.917994 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5277.363913 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.92% 0.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-6143 529 32.47% 33.39% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::6144-8191 134 8.23% 41.62% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::10240-12287 516 31.68% 73.30% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-14335 268 16.45% 89.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::14336-16383 35 2.15% 91.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::22528-24575 132 8.10% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1629 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1072 65.81% 65.81% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 557 34.19% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1629 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2001 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2001 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1629 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1629 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3630 # Table walker requests started/completed, data/inst -system.cpu1.dtb.inst_hits 0 # ITB inst hits -system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3814262 # DTB read hits -system.cpu1.dtb.read_misses 1730 # DTB read misses -system.cpu1.dtb.write_hits 2798296 # DTB write hits -system.cpu1.dtb.write_misses 271 # DTB write misses -system.cpu1.dtb.flush_tlb 154 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1231 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 257 # Number of TLB faults due to prefetch -system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 87 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3815992 # DTB read accesses -system.cpu1.dtb.write_accesses 2798567 # DTB write accesses -system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6612558 # DTB hits -system.cpu1.dtb.misses 2001 # DTB misses -system.cpu1.dtb.accesses 6614559 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 1010 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1010 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 203 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 807 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1010 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1010 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1010 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 742 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10898.247978 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9294.148205 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6181.528328 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 309 41.64% 41.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::6144-8191 2 0.27% 41.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 197 26.55% 68.46% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 117 15.77% 84.23% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 15 2.02% 86.25% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 102 13.75% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 742 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 539 72.64% 72.64% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 203 27.36% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 742 # Table walker page sizes translated -system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1010 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1010 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 742 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 742 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1752 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 17845521 # ITB inst hits -system.cpu1.itb.inst_misses 1010 # ITB inst misses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 154 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 179 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 709 # Number of entries that have been flushed from TLB -system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 17846531 # ITB inst accesses -system.cpu1.itb.hits 17845521 # DTB hits -system.cpu1.itb.misses 1010 # DTB misses -system.cpu1.itb.accesses 17846531 # DTB accesses -system.cpu1.numPwrStateTransitions 702 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 351 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 884610555.122507 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 11702380509.763947 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 346 98.58% 98.58% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 3 0.85% 99.43% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 2 0.57% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 156798063501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 351 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 2513214226652 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 310498304848 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 143755305 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 17251469 # Number of instructions committed -system.cpu1.committedOps 20813754 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 18573481 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1582 # Number of float alu accesses -system.cpu1.num_func_calls 1994080 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2178225 # number of instructions that are conditional controls -system.cpu1.num_int_insts 18573481 # number of integer instructions -system.cpu1.num_fp_insts 1582 # number of float instructions -system.cpu1.num_int_register_reads 34424804 # number of times the integer registers were read -system.cpu1.num_int_register_writes 13020587 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1129 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 454 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 75792524 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 7403118 # number of times the CC registers were written -system.cpu1.num_mem_refs 6816030 # number of memory refs -system.cpu1.num_load_insts 3857938 # Number of load instructions -system.cpu1.num_store_insts 2958092 # Number of store instructions -system.cpu1.num_idle_cycles 136763817.825679 # Number of idle cycles -system.cpu1.num_busy_cycles 6991487.174321 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048635 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951365 # Percentage of idle cycles -system.cpu1.Branches 4283308 # Number of branches fetched -system.cpu1.op_class::No_OpClass 49 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 14594706 68.11% 68.11% # Class of executed instruction -system.cpu1.op_class::IntMult 16119 0.08% 68.19% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 983 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.19% # Class of executed instruction -system.cpu1.op_class::MemRead 3857938 18.00% 86.20% # Class of executed instruction -system.cpu1.op_class::MemWrite 2958092 13.80% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21427887 # Class of executed instruction -system.cpu2.branchPred.lookups 5563559 # Number of BP lookups -system.cpu2.branchPred.condPredicted 2831152 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 495188 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3274111 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 1663178 # Number of BTB hits -system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 50.797850 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1571133 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 329841 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 676012 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 643238 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 32774 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 22078 # Number of mispredicted indirect branches. -system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu2.dtb.walker.walks 12042 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 12042 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7406 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4636 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 12042 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 12042 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 12042 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 2043 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 11062.897699 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 9694.627890 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 6045.581336 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-8191 687 33.63% 33.63% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1153 56.44% 90.06% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-24575 200 9.79% 99.85% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::81920-90111 3 0.15% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 2043 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 2000042500 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0 2000042500 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 2000042500 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 1264 61.87% 61.87% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 779 38.13% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 2043 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12042 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12042 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2043 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2043 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 14085 # Table walker requests started/completed, data/inst -system.cpu2.dtb.inst_hits 0 # ITB inst hits -system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 4331167 # DTB read hits -system.cpu2.dtb.read_misses 10867 # DTB read misses -system.cpu2.dtb.write_hits 3346265 # DTB write hits -system.cpu2.dtb.write_misses 1175 # DTB write misses -system.cpu2.dtb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 1411 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 255 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 303 # Number of TLB faults due to prefetch -system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 127 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 4342034 # DTB read accesses -system.cpu2.dtb.write_accesses 3347440 # DTB write accesses -system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 7677432 # DTB hits -system.cpu2.dtb.misses 12042 # DTB misses -system.cpu2.dtb.accesses 7689474 # DTB accesses -system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu2.itb.walker.walks 1330 # Table walker walks requested -system.cpu2.itb.walker.walksShort 1330 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 245 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1085 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 1330 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 1330 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 1330 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 845 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 11181.065089 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 9687.789458 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 6060.643085 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-6143 346 40.95% 40.95% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::6144-8191 3 0.36% 41.30% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::10240-12287 226 26.75% 68.05% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-14335 99 11.72% 79.76% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::14336-16383 48 5.68% 85.44% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::22528-24575 122 14.44% 99.88% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::24576-26623 1 0.12% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 845 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 2000028000 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 2000028000 100.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 2000028000 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 603 71.36% 71.36% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 242 28.64% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 845 # Table walker page sizes translated -system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1330 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1330 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 845 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 845 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 2175 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 10448237 # ITB inst hits -system.cpu2.itb.inst_misses 1330 # ITB inst misses -system.cpu2.itb.read_hits 0 # DTB read hits -system.cpu2.itb.read_misses 0 # DTB read misses -system.cpu2.itb.write_hits 0 # DTB write hits -system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 823 # Number of entries that have been flushed from TLB -system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1725 # Number of TLB faults due to permissions restrictions -system.cpu2.itb.read_accesses 0 # DTB read accesses -system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 10449567 # ITB inst accesses -system.cpu2.itb.hits 10448237 # DTB hits -system.cpu2.itb.misses 1330 # DTB misses -system.cpu2.itb.accesses 10449567 # DTB accesses -system.cpu2.numPwrStateTransitions 1076 # Number of power state transitions -system.cpu2.pwrStateClkGateDist::samples 538 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::mean 5085855532.985130 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::stdev 41244061935.633728 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::underflows 493 91.64% 91.64% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1000-5e+10 38 7.06% 98.70% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::5e+10-1e+11 1 0.19% 98.88% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 1 0.19% 99.07% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 1 0.19% 99.26% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 1 0.19% 99.44% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 2 0.37% 99.81% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.19% 100.00% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::max_value 500051113501 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::total 538 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateResidencyTicks::ON 87522254754 # Cumulative time (in ticks) in various power states -system.cpu2.pwrStateResidencyTicks::CLK_GATED 2736190276746 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 141975261 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 19207075 # Number of instructions committed -system.cpu2.committedOps 23282264 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 1390064 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 541 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 36123 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 7.391821 # CPI: cycles per instruction -system.cpu2.ipc 0.135285 # IPC: instructions per cycle -system.cpu2.op_class_0::No_OpClass 48 0.00% 0.00% # Class of committed instruction -system.cpu2.op_class_0::IntAlu 15551874 66.80% 66.80% # Class of committed instruction -system.cpu2.op_class_0::IntMult 18578 0.08% 66.88% # Class of committed instruction -system.cpu2.op_class_0::IntDiv 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::FloatAdd 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::FloatCmp 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::FloatCvt 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::FloatMult 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::FloatDiv 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::FloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdAdd 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdAddAcc 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdAlu 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdCmp 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdCvt 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdMisc 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdMult 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdMultAcc 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdShift 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMisc 1338 0.01% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu2.op_class_0::MemRead 4246805 18.24% 85.12% # Class of committed instruction -system.cpu2.op_class_0::MemWrite 3463621 14.88% 100.00% # Class of committed instruction -system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.op_class_0::total 23282264 # Class of committed instruction -system.cpu2.kern.inst.arm 0 # number of arm instructions executed -system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 38700481 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 103274780 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13558463 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7461726 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 297292 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 8389979 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 4437676 # Number of BTB hits -system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 52.892576 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 3087767 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 16069 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 2015433 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 1953316 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 62117 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 18167 # Number of mispredicted indirect branches. -system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu3.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu3.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu3.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu3.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu3.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu3.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu3.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu3.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu3.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu3.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu3.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu3.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu3.dtb.walker.walks 34483 # Table walker walks requested -system.cpu3.dtb.walker.walksShort 34483 # Table walker walks initiated with short descriptors -system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 10978 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 8165 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 15340 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 19143 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 456.015254 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 2830.743841 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-8191 18720 97.79% 97.79% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::8192-16383 307 1.60% 99.39% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::16384-24575 66 0.34% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::24576-32767 32 0.17% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-40959 6 0.03% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::40960-49151 8 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::73728-81919 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::81920-90111 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 19143 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 6521 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 10311.301948 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 8555.831863 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 6751.449027 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-8191 2865 43.93% 43.93% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::8192-16383 2966 45.48% 89.42% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::16384-24575 551 8.45% 97.87% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::24576-32767 84 1.29% 99.16% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-40959 31 0.48% 99.63% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::40960-49151 17 0.26% 99.89% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::90112-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 6521 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -8545598564 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.743431 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::stdev 0.275134 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-1 -8589277064 100.51% 100.51% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::2-3 31465000 -0.37% 100.14% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-5 6055500 -0.07% 100.07% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::6-7 2113000 -0.02% 100.05% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-9 1651500 -0.02% 100.03% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::10-11 591000 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-13 384000 -0.00% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::14-15 739000 -0.01% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-17 231000 -0.00% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::18-19 112500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-21 46500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::22-23 31000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-25 29500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::26-27 22000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-29 12000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::30-31 195000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -8545598564 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 1839 71.81% 71.81% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::1M 722 28.19% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 2561 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 34483 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 34483 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2561 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2561 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 37044 # Table walker requests started/completed, data/inst -system.cpu3.dtb.inst_hits 0 # ITB inst hits -system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7471341 # DTB read hits -system.cpu3.dtb.read_misses 28725 # DTB read misses -system.cpu3.dtb.write_hits 5714088 # DTB write hits -system.cpu3.dtb.write_misses 5758 # DTB write misses -system.cpu3.dtb.flush_tlb 157 # Number of times complete TLB was flushed -system.cpu3.dtb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA -system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 1650 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 393 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 706 # Number of TLB faults due to prefetch -system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 319 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7500066 # DTB read accesses -system.cpu3.dtb.write_accesses 5719846 # DTB write accesses -system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 13185429 # DTB hits -system.cpu3.dtb.misses 34483 # DTB misses -system.cpu3.dtb.accesses 13219912 # DTB accesses -system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu3.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu3.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu3.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu3.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu3.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu3.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu3.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu3.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu3.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu3.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu3.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu3.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu3.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.cpu3.itb.walker.walks 4240 # Table walker walks requested -system.cpu3.itb.walker.walksShort 4240 # Table walker walks initiated with short descriptors -system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1366 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2463 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 411 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 3829 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1196.395926 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 4662.983981 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-8191 3612 94.33% 94.33% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::8192-16383 152 3.97% 98.30% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::16384-24575 35 0.91% 99.22% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::24576-32767 19 0.50% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-40959 3 0.08% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::40960-49151 2 0.05% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::49152-57343 2 0.05% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::57344-65535 1 0.03% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-73727 2 0.05% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::81920-90111 1 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 3829 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 1597 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 10150.594865 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 8236.395815 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 7276.129645 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-8191 852 53.35% 53.35% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::8192-16383 514 32.19% 85.54% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::16384-24575 201 12.59% 98.12% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::24576-32767 13 0.81% 98.94% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-40959 11 0.69% 99.62% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::40960-49151 3 0.19% 99.81% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::49152-57343 2 0.13% 99.94% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::81920-90111 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 1597 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -8763056564 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.696085 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.459515 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -2661759664 30.37% 30.37% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -6102526900 69.64% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 1039000 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 149500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 41500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -8763056564 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 846 71.33% 71.33% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::1M 340 28.67% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 1186 # Table walker page sizes translated -system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4240 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4240 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1186 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1186 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 5426 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9891489 # ITB inst hits -system.cpu3.itb.inst_misses 4240 # ITB inst misses -system.cpu3.itb.read_hits 0 # DTB read hits -system.cpu3.itb.read_misses 0 # DTB read misses -system.cpu3.itb.write_hits 0 # DTB write hits -system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 157 # Number of times complete TLB was flushed -system.cpu3.itb.flush_tlb_mva 225 # Number of times TLB was flushed by MVA -system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 1134 # Number of entries that have been flushed from TLB -system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 708 # Number of TLB faults due to permissions restrictions -system.cpu3.itb.read_accesses 0 # DTB read accesses -system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 9895729 # ITB inst accesses -system.cpu3.itb.hits 9891489 # DTB hits -system.cpu3.itb.misses 4240 # DTB misses -system.cpu3.itb.accesses 9895729 # DTB accesses -system.cpu3.numPwrStateTransitions 1742 # Number of power state transitions -system.cpu3.pwrStateClkGateDist::samples 871 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::mean 24222914.443169 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::stdev 644616845.496373 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::underflows 856 98.28% 98.28% # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::1000-5e+10 15 1.72% 100.00% # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::max_value 18906422924 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::total 871 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateResidencyTicks::ON 2802614373020 # Cumulative time (in ticks) in various power states -system.cpu3.pwrStateResidencyTicks::CLK_GATED 21098158480 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 55804206 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20943122 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 53945813 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13558463 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 9478759 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 32366624 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1570295 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 59981 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 769 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 238 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 103755 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 71551 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 320 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9890169 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 205274 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 2246 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 54331487 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.197628 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.332891 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 39855672 73.36% 73.36% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 1851434 3.41% 76.76% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 1194487 2.20% 78.96% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3686492 6.79% 85.75% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 943670 1.74% 87.48% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 608106 1.12% 88.60% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2967627 5.46% 94.07% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 643917 1.19% 95.25% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2580082 4.75% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 54331487 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.242965 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.966698 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14668908 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 29986640 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 7957627 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 1016633 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 701473 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 1058313 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 84773 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 46874682 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 279635 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 701473 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15195365 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 3032088 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 21321904 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8439674 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 5640768 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 45002197 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 690 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1195883 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 108366 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 3949949 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 46926978 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 206658489 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 50587166 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 3902 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 39299186 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 7627792 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 720809 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 668593 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 5741274 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 7971579 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 6293429 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1156869 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1562249 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 43347954 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 520206 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 41277545 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 55280 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 6083084 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 14076683 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 54734 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 54331487 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.759735 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.457545 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 38079008 70.09% 70.09% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 5345699 9.84% 79.93% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 4107348 7.56% 87.49% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3341746 6.15% 93.64% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1375872 2.53% 96.17% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 821998 1.51% 97.68% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 871189 1.60% 99.28% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 257716 0.47% 99.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 130911 0.24% 100.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 54331487 # Number of insts issued each cycle -system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 64496 10.30% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 288888 46.14% 56.45% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 272662 43.55% 100.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 62 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 27558666 66.76% 66.76% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 30979 0.08% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.84% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 2332 0.01% 66.85% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.85% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 66.85% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.85% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7685963 18.62% 85.47% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 5999538 14.53% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 41277545 # Type of FU issued -system.cpu3.iq.rate 0.739685 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 626046 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.015167 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 137559508 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 49974445 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 40123728 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 8395 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 4805 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 3602 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 41898968 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 4561 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 173439 # Number of loads that had data forwarded from stores -system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1192109 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 1191 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 28578 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 580828 # Number of stores squashed -system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 104405 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 43387 # Number of times an access to memory failed due to the cache being blocked -system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 701473 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 2634873 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 283425 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 43928502 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 66531 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 7971579 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 6293429 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 268536 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 25934 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 251471 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 28578 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 127058 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 130735 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 257793 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 40956248 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7556430 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 286903 # Number of squashed instructions skipped in execute -system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 60342 # number of nop insts executed -system.cpu3.iew.exec_refs 13498971 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7544495 # Number of branches executed -system.cpu3.iew.exec_stores 5942541 # Number of stores executed -system.cpu3.iew.exec_rate 0.733928 # Inst execution rate -system.cpu3.iew.wb_sent 40664526 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 40127330 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 21123316 # num instructions producing a value -system.cpu3.iew.wb_consumers 37320445 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.719074 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.565999 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 6097313 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 465472 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 213597 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 53033650 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.713199 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.610019 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 38610990 72.80% 72.80% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 6319361 11.92% 84.72% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3213493 6.06% 90.78% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 1410131 2.66% 93.44% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 792140 1.49% 94.93% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 553402 1.04% 95.98% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 958153 1.81% 97.78% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 245496 0.46% 98.25% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 930484 1.75% 100.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 53033650 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 31044800 # Number of instructions committed -system.cpu3.commit.committedOps 37823572 # Number of ops (including micro ops) committed -system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 12492071 # Number of memory references committed -system.cpu3.commit.loads 6779470 # Number of loads committed -system.cpu3.commit.membars 181779 # Number of memory barriers committed -system.cpu3.commit.branches 7130164 # Number of branches committed -system.cpu3.commit.fp_insts 3347 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 32983556 # Number of committed integer instructions. -system.cpu3.commit.function_calls 1245135 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 25299125 66.89% 66.89% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 30044 0.08% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 2332 0.01% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.97% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 6779470 17.92% 84.90% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 5712601 15.10% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 37823572 # Class of committed instruction -system.cpu3.commit.bw_lim_events 930484 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 90425378 # The number of ROB reads -system.cpu3.rob.rob_writes 89139493 # The number of ROB writes -system.cpu3.timesIdled 227716 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1472719 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 5161848513 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 31006304 # Number of Instructions Simulated -system.cpu3.committedOps 37785076 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.799770 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.799770 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.555627 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.555627 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 44890181 # number of integer regfile reads -system.cpu3.int_regfile_writes 25156907 # number of integer regfile writes -system.cpu3.fp_regfile_reads 14457 # number of floating regfile reads -system.cpu3.fp_regfile_writes 12074 # number of floating regfile writes -system.cpu3.cc_regfile_reads 144431120 # number of cc regfile reads -system.cpu3.cc_regfile_writes 15956854 # number of cc regfile writes -system.cpu3.misc_regfile_reads 98347677 # number of misc regfile reads -system.cpu3.misc_regfile_writes 344757 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 30152 # Transaction distribution -system.iobus.trans_dist::ReadResp 30152 # Transaction distribution -system.iobus.trans_dist::WriteReq 59010 # Transaction distribution -system.iobus.trans_dist::WriteResp 59010 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105436 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178324 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67865 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159093 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480085 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 29764500 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 229000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 20500 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 4500 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 1000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40500 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 3967500 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 23290000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 72552043 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 50146000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 14254000 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.002362 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 248718607009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.002362 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062648 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062648 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 327996 # Number of tag accesses -system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses -system.iocache.ReadReq_misses::total 220 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36444 # number of demand (read+write) misses -system.iocache.demand_misses::total 36444 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36444 # number of overall misses -system.iocache.overall_misses::total 36444 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 16061914 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 16061914 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 1680216129 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 1680216129 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 1696278043 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1696278043 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 1696278043 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1696278043 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36444 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36444 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36444 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36444 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 73008.700000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 73008.700000 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 46384.058331 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 46384.058331 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 46544.782214 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 46544.782214 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 46544.782214 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 46544.782214 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 135 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 135 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 13984 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 13984 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 14119 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 14119 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 14119 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 14119 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 9311914 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 9311914 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 980165529 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 980165529 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 989477443 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 989477443 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 989477443 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 989477443 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.613636 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.613636 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.386042 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.386042 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.387416 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.387416 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.387416 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.387416 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68977.140741 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68977.140741 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70091.928561 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70091.928561 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70081.269424 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70081.269424 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70081.269424 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70081.269424 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 100900 # number of replacements -system.l2c.tags.tagsinuse 65188.817028 # Cycle average of tags in use -system.l2c.tags.total_refs 5432391 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 166232 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 32.679574 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 76153677500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.990870 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.930107 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.003315 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4645.223340 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 20148.450289 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.003029 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 771.166553 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6124.303836 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 20.124161 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2252.228504 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 10091.945751 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 55.278842 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 0.002282 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2987.422614 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 18086.743533 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.070880 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.307441 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011767 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.093449 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000307 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034366 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.153991 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000843 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.045584 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.275982 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994702 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 65 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65267 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 59 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5926 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 59314 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000992 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.995895 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45033905 # Number of tag accesses -system.l2c.tags.data_accesses 45033905 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 3242 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1702 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1228 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 661 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 12254 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 909 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 19814 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 3415 # number of ReadReq hits -system.l2c.ReadReq_hits::total 43225 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 692039 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 692039 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1932297 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1932297 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 1108 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 480 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 437 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 765 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2790 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu3.data 25 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 26 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 67205 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 22539 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 26172 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3.data 44897 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 160813 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 736420 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 210026 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 463898 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 538419 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1948763 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 223430 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 69477 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 90045 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 140227 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 523179 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3242 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1702 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 736420 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 290635 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 1228 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 210026 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 92016 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 12254 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 909 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 463898 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 116217 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.dtb.walker 19814 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.itb.walker 3415 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 538419 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 185124 # number of demand (read+write) hits -system.l2c.demand_hits::total 2675980 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3242 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1702 # number of overall hits -system.l2c.overall_hits::cpu0.inst 736420 # number of overall hits -system.l2c.overall_hits::cpu0.data 290635 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 1228 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 661 # number of overall hits -system.l2c.overall_hits::cpu1.inst 210026 # number of overall hits -system.l2c.overall_hits::cpu1.data 92016 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 12254 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 909 # number of overall hits -system.l2c.overall_hits::cpu2.inst 463898 # number of overall hits -system.l2c.overall_hits::cpu2.data 116217 # number of overall hits -system.l2c.overall_hits::cpu3.dtb.walker 19814 # number of overall hits -system.l2c.overall_hits::cpu3.itb.walker 3415 # number of overall hits -system.l2c.overall_hits::cpu3.inst 538419 # number of overall hits -system.l2c.overall_hits::cpu3.data 185124 # number of overall hits -system.l2c.overall_hits::total 2675980 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 28 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.dtb.walker 71 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 108 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 3 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 1 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu3.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 43978 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 11759 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 29016 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 50830 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 135583 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 7835 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1898 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 5370 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 6053 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 21156 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 5105 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 2412 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 2209 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3.data 4457 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 14183 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7835 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 49083 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1898 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 14171 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 28 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 5370 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 31225 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.dtb.walker 71 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 6053 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 55287 # number of demand (read+write) misses -system.l2c.demand_misses::total 171030 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7835 # number of overall misses -system.l2c.overall_misses::cpu0.data 49083 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1898 # number of overall misses -system.l2c.overall_misses::cpu1.data 14171 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 28 # number of overall misses -system.l2c.overall_misses::cpu2.inst 5370 # number of overall misses -system.l2c.overall_misses::cpu2.data 31225 # number of overall misses -system.l2c.overall_misses::cpu3.dtb.walker 71 # number of overall misses -system.l2c.overall_misses::cpu3.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu3.inst 6053 # number of overall misses -system.l2c.overall_misses::cpu3.data 55287 # number of overall misses -system.l2c.overall_misses::total 171030 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 83500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2403500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 6664000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.itb.walker 84000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 9235000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 59000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 86500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3.data 29500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 175000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu3.data 162500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 940228500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 2258171500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 4211938000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7410338000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 154678500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu2.inst 443554000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu3.inst 505532999 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1103765499 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 202470000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2.data 181243500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3.data 394790500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 778504000 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 83500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 154678500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1142698500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 2403500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 443554000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 2439415000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.dtb.walker 6664000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.itb.walker 84000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 505532999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 4606728500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9301842499 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 83500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 154678500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1142698500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 2403500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 443554000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 2439415000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.dtb.walker 6664000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.itb.walker 84000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 505532999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 4606728500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9301842499 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 3247 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1704 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 1229 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 661 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 12282 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 909 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.dtb.walker 19885 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.itb.walker 3416 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 43333 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 692039 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 692039 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1932297 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1932297 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1113 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 482 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 440 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 766 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2801 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu3.data 27 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111183 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 34298 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 55188 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 95727 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296396 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 744255 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 211924 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu2.inst 469268 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu3.inst 544472 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1969919 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 228535 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 71889 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2.data 92254 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3.data 144684 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 537362 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 3247 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1704 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 744255 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 339718 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 1229 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 661 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 211924 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 106187 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 12282 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 909 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 469268 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 147442 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.dtb.walker 19885 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.itb.walker 3416 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 544472 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 240411 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2847010 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 3247 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1704 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 744255 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 339718 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 1229 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 661 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 211924 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 106187 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 12282 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 909 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 469268 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 147442 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.dtb.walker 19885 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.itb.walker 3416 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 544472 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 240411 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2847010 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001540 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001174 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000814 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.002280 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.dtb.walker 0.003571 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.itb.walker 0.000293 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.002492 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.004492 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.004149 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.006818 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 0.001305 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.003927 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu3.data 0.074074 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.071429 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.395546 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.342848 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.525766 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 0.530989 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.457439 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.010527 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008956 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.011443 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.011117 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.010740 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.022338 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.033552 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.023945 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.030805 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.026394 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001540 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001174 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.010527 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.144482 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000814 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008956 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.133453 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.002280 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.011443 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.211778 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.itb.walker 0.000293 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.011117 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.229969 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.060074 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001540 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001174 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.010527 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.144482 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000814 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008956 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.133453 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.002280 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.011443 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.211778 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.itb.walker 0.000293 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.011117 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.229969 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.060074 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 85839.285714 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 93859.154930 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 84000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 85509.259259 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 29500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 28833.333333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 29500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 15909.090909 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 81250 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 81250 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 79958.202228 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 77825.044803 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 82863.230376 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 54655.362398 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81495.521602 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 82598.510242 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 83517.759623 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 52172.693279 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83942.786070 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82047.759167 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 88577.630693 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 54889.938659 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 81495.521602 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 80636.405335 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 85839.285714 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 82598.510242 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 78123.779023 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 93859.154930 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.itb.walker 84000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 83517.759623 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 83323.900736 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54387.198147 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 81495.521602 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 80636.405335 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 85839.285714 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 82598.510242 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 78123.779023 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 93859.154930 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.itb.walker 84000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 83517.759623 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 83323.900736 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54387.198147 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 92528 # number of writebacks -system.l2c.writebacks::total 92528 # number of writebacks -system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 4 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 5 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2.data 20 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3.data 46 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 66 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 20 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.data 46 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 20 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.data 46 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 28 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker 71 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 2 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 3 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 1 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu3.data 2 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 11759 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 29016 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3.data 50830 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 91605 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1898 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5366 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 6048 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 13312 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2412 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2.data 2189 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3.data 4411 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 9012 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1898 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 14171 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 28 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 5366 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 31205 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.dtb.walker 71 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 6048 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.data 55241 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 114030 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1898 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 14171 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 28 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 5366 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 31205 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.dtb.walker 71 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 6048 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.data 55241 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 114030 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3424 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2.data 7112 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3.data 7739 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 18275 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2828 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2.data 5192 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu3.data 6207 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 14227 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6252 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2.data 12304 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu3.data 13946 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 32502 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 73500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2123500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 5954000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker 74000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 8225000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 39000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 56500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 19500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 115000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data 142500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 142500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 822638500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1968011500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 3703638000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 6494288000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 135698500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 389778500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 444784999 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 970261999 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 178350000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 157962500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 346988500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 683301000 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 73500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 135698500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1000988500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2123500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 389778500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2125974000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 5954000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.itb.walker 74000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 444784999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 4050626500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8156075999 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 73500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 135698500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1000988500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2123500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 389778500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2125974000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 5954000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.itb.walker 74000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 444784999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 4050626500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8156075999 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 558689000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1400703000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1566927500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3526319500 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 558689000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 1400703000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3.data 1566927500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3526319500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000814 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002280 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003571 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.000293 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.002331 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.004149 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.006818 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.001305 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.002142 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.074074 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.071429 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.342848 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.525766 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.530989 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.309063 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.008956 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.011435 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.011108 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006758 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.033552 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.023728 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.030487 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016771 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000814 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008956 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.133453 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002280 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011435 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.211643 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003571 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.000293 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.011108 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.229777 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.040053 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000814 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008956 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.133453 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002280 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011435 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.211643 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003571 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.000293 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.011108 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.229777 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.040053 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75839.285714 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 83859.154930 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 81435.643564 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 18833.333333 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19166.666667 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 71250 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71250 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69958.202228 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67825.044803 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 72863.230376 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 70894.470826 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71495.521602 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72638.557585 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73542.493221 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72886.267954 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73942.786070 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72161.946094 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78664.361823 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75821.238349 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71495.521602 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70636.405335 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75839.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72638.557585 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 68129.274155 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 83859.154930 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73542.493221 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 73326.451368 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 71525.703753 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71495.521602 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70636.405335 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75839.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72638.557585 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68129.274155 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 83859.154930 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 74000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73542.493221 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 73326.451368 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 71525.703753 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163168.516355 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196949.240720 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202471.572555 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 192958.659371 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 89361.644274 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 113841.271131 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 112356.768966 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 108495.461818 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 344722 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 142063 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 40114 # Transaction distribution -system.membus.trans_dist::ReadResp 75706 # Transaction distribution -system.membus.trans_dist::WriteReq 27565 # Transaction distribution -system.membus.trans_dist::WriteResp 27565 # Transaction distribution -system.membus.trans_dist::WritebackDirty 128718 # Transaction distribution -system.membus.trans_dist::CleanEvict 8591 # Transaction distribution -system.membus.trans_dist::UpgradeReq 126 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40 # Transaction distribution -system.membus.trans_dist::ReadExReq 135468 # Transaction distribution -system.membus.trans_dist::ReadExResp 135468 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35592 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 22240 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 470452 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 577904 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95179 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 95179 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 673083 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16898684 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17061809 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2321600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19383409 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 336 # Total snoops (count) -system.membus.snoopTraffic 21376 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 338143 # Request fanout histogram -system.membus.snoop_fanout::mean 0.015650 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.124118 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 332851 98.43% 98.43% # Request fanout histogram -system.membus.snoop_fanout::1 5292 1.57% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 338143 # Request fanout histogram -system.membus.reqLayer0.occupancy 57431500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 684999 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 500677543 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 649758250 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 720586 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks -system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks -system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks -system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks -system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks -system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks -system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks -system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5637023 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2833220 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 44733 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 306 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 306 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2823712531500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 111093 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2618641 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 747081 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1969505 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 146278 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2801 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2829 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296396 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296396 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1970061 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 537497 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4488 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5927533 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2623831 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24350 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 98043 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8673757 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 252159480 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97841913 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37624 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 168032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 350207049 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 125784 # Total snoops (count) -system.toL2Bus.snoopTraffic 6024500 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 4134386 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021942 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.146494 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4043670 97.81% 97.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 90716 2.19% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4134386 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3408827455 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 230414 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1839308788 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 767442228 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10535976 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 47560224 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu3.kern.inst.arm 0 # number of arm instructions executed -system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed - ----------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal deleted file mode 100644 index ad91d76dd..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal +++ /dev/null @@ -1,208 +0,0 @@ -Booting Linux on physical CPU 0x0
-
Initializing cgroup subsys cpuset
-
Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014
-
Kernel was built at commit id ''
-
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
-
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
-
Machine model: V2P-CA15
-
bootconsole [earlycon0] enabled
-
Memory policy: Data cache writealloc
-
kdebugv2m: Following are test values to confirm proper working
-
kdebugv2m: Ranges 42000000 0
-
kdebugv2m: Regs 30000000 1000000
-
kdebugv2m: Virtual-Reg f0000000
-
kdebugv2m: pci node addr_cells 3
-
kdebugv2m: pci node size_cells 2
-
kdebugv2m: motherboard addr_cells 2
-
On node 0 totalpages: 65536
-
free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000
-
Normal zone: 512 pages used for memmap
-
Normal zone: 0 pages reserved
-
Normal zone: 65536 pages, LIFO batch:15
-
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
-
PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768
-
pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096
-
pcpu-alloc: [0] 0
-
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
-
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-
PID hash table entries: 1024 (order: 0, 4096 bytes)
-
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
-
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
-
Memory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem)
-
Virtual kernel memory layout:
-
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
-
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
-
vmalloc : 0x90800000 - 0xff000000 (1768 MB)
-
lowmem : 0x80000000 - 0x90000000 ( 256 MB)
-
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
-
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
-
.text : 0x80008000 - 0x806a942c (6790 kB)
-
.init : 0x806aa000 - 0x806f3d80 ( 296 kB)
-
.data : 0x806f4000 - 0x80732754 ( 250 kB)
-
.bss : 0x80732754 - 0x8078e9d8 ( 369 kB)
-
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
-
Preemptible hierarchical RCU implementation.
-
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
-
NR_IRQS:16 nr_irqs:16 16
-
Architected cp15 timer(s) running at 25.16MHz (phys).
-
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
-
Switching to timer-based delay loop
-
Console: colour dummy device 80x30
-
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-
pid_max: default: 32768 minimum: 301
-
Mount-cache hash table entries: 512
-
CPU: Testing write buffer coherency: ok
-
CPU0: update cpu_power 1024
-
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
-
Setting up static identity map for 0x804fee68 - 0x804fee9c
-
Brought up 1 CPUs
-
SMP: Total of 1 processors activated.
-
CPU: All CPU(s) started in SVC mode.
-
VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
-
NET: Registered protocol family 16
-
DMA: preallocated 256 KiB pool for atomic coherent allocations
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0
-
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0
-
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
-
hw-breakpoint: CPU 0 failed to disable vector catch
-
Serial: AMBA PL011 UART driver
-
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-
console [ttyAMA0] enabled
-console [ttyAMA0] enabled
-
bootconsole [earlycon0] disabled
-bootconsole [earlycon0] disabled
-
PCI host bridge to bus 0000:00
-pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]
-pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
-pci_bus 0000:00: root bus resource [bus 00-ff]
-pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-PCI: bus0: Fast back to back transfers disabled
-pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]
-pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]
-pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]
-pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]
-pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]
-pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]
-pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
-PCI map irq: slot 0, pin 1, devslot 0, irq: 68
-PCI map irq: slot 1, pin 2, devslot 1, irq: 69
-bio: create slab <bio-0> at 0
-vgaarb: loaded
-SCSI subsystem initialized
-libata version 3.00 loaded.
-usbcore: registered new interface driver usbfs
-usbcore: registered new interface driver hub
-usbcore: registered new device driver usb
-pps_core: LinuxPPS API ver. 1 registered
-pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-PTP clock support registered
-Advanced Linux Sound Architecture Driver Initialized.
-Switched to clocksource arch_sys_counter
-NET: Registered protocol family 2
-TCP established hash table entries: 2048 (order: 1, 8192 bytes)
-TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
-TCP: Hash tables configured (established 2048 bind 2048)
-TCP: reno registered
-UDP hash table entries: 256 (order: 1, 8192 bytes)
-UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-NET: Registered protocol family 1
-RPC: Registered named UNIX socket transport module.
-RPC: Registered udp transport module.
-RPC: Registered tcp transport module.
-RPC: Registered tcp NFSv4.1 backchannel transport module.
-PCI: CLS 64 bytes, default 64
-hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available
-jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
-msgmni has been set to 460
-io scheduler noop registered (default)
-brd: module loaded
-loop: module loaded
-ata_piix 0000:00:01.0: version 2.13
-PCI: enabling device 0000:00:01.0 (0040 -> 0041)
-scsi0 : ata_piix
-scsi1 : ata_piix
-ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69
-ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69
-e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
-e100: Copyright(c) 1999-2006 Intel Corporation
-e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-e1000: Copyright (c) 1999-2006 Intel Corporation.
-PCI: enabling device 0000:00:00.0 (0040 -> 0042)
-ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-ata1.00: 1048320 sectors, multi 0: LBA
-ata1.00: configured for UDMA/33
-scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
-sd 0:0:0:0: [sda] Write Protect is off
-sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
- sda: sda1
-sd 0:0:0:0: Attached scsi generic sg0 type 0
-sd 0:0:0:0: [sda] Attached SCSI disk
-e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-e1000e: Copyright(c) 1999 - 2013 Intel Corporation.
-igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-igb: Copyright (c) 2007-2013 Intel Corporation.
-igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k
-igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
-ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k
-ixgbe: Copyright (c) 1999-2013 Intel Corporation.
-ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k
-ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.
-ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI
-ixgb: Copyright (c) 1999-2008 Intel Corporation.
-smsc911x: Driver version 2008-10-21
-smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2
-nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller
-nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1
-nxp-isp1760 1b000000.usb: Scratch test failed.
-nxp-isp1760 1b000000.usb: can't setup: -19
-nxp-isp1760 1b000000.usb: USB bus 1 deregistered
-usbcore: registered new interface driver usb-storage
-mousedev: PS/2 mouse device common for all mice
-rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0
-usbcore: registered new interface driver usbhid
-usbhid: USB HID core driver
-ashmem: initialized
-logger: created 256K log 'log_main'
-logger: created 256K log 'log_events'
-logger: created 256K log 'log_radio'
-logger: created 256K log 'log_system'
-oprofile: using timer interrupt.
-TCP: cubic registered
-NET: Registered protocol family 10
-NET: Registered protocol family 17
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)
-ALSA device list:
- No soundcards found.
- -input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2
-VFS: Mounted root (ext2 filesystem) on device 8:1.
-Freeing unused kernel memory: 292K (806aa000 - 806f3000)
-
init started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)
-
starting pid 673, tty '': '/etc/rc.d/rc.local'
-warning: can't open /etc/mtab: No such file or directory
-Thu Jan 1 00:00:02 UTC 2009
-S: devpts
-Thu Jan 1 00:00:02 UTC 2009
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/EMPTY b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/EMPTY new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/EMPTY diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini deleted file mode 100644 index 99681c867..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ /dev/null @@ -1,2571 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxArmSystem -children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain -atags_addr=134217728 -boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb -early_kernel_symbols=false -enable_context_switch_stats_dump=false -eventq_index=0 -exit_on_work_items=false -flags_addr=469827632 -gic_cpu_addr=738205696 -have_large_asid_64=false -have_lpae=true -have_security=false -have_virtualization=false -highest_el_is_64=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 -kernel_addr_check=true -load_addr_mask=268435455 -load_offset=2147483648 -machine_type=VExpress_EMM -mem_mode=timing -mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.nvmem system.realview.vram -mmap_using_noreserve=false -multi_proc=true -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -panic_on_oops=true -panic_on_panic=true -phys_addr_range_64=40 -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -reset_addr_64=0 -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[1] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.cf0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.cf0.image - -[system.cf0.image] -type=CowDiskImage -children=child -child=system.cf0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.cf0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img -read_only=true - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu0] -type=DerivO3CPU -children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu0.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu0.dstage2_mmu -dtb=system.cpu0.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu0.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu0.interrupts -isa=system.cpu0.isa -issueToExecuteDelay=1 -issueWidth=8 -istage2_mmu=system.cpu0.istage2_mmu -itb=system.cpu0.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=1280 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu0.tracer -trapLatency=13 -wbWidth=8 -workload= -dcache_port=system.cpu0.dcache.cpu_side -icache_port=system.cpu0.icache.cpu_side - -[system.cpu0.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu0.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.slave[1] - -[system.cpu0.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu0.dtb - -[system.cpu0.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu0.dstage2_mmu.stage2_tlb.walker - -[system.cpu0.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu0.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu0.dtb.walker - -[system.cpu0.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.toL2Bus.slave[3] - -[system.cpu0.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 -eventq_index=0 - -[system.cpu0.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu0.fuPool.FUList0.opList - -[system.cpu0.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 - -[system.cpu0.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu0.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu0.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 - -[system.cpu0.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu0.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu0.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu0.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 - -[system.cpu0.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu0.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu0.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu0.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu0.fuPool.FUList4.opList - -[system.cpu0.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 - -[system.cpu0.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu0.fuPool.FUList6.opList - -[system.cpu0.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 - -[system.cpu0.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu0.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu0.fuPool.FUList8.opList - -[system.cpu0.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu0.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.slave[0] - -[system.cpu0.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu0.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu0.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu0.itb - -[system.cpu0.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu0.istage2_mmu.stage2_tlb.walker - -[system.cpu0.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu0.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu0.itb.walker - -[system.cpu0.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.toL2Bus.slave[2] - -[system.cpu0.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu1] -type=DerivO3CPU -children=branchPred dstage2_mmu dtb fuPool isa istage2_mmu itb tracer -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu1.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu1.dstage2_mmu -dtb=system.cpu1.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu1.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts= -isa=system.cpu1.isa -issueToExecuteDelay=1 -issueWidth=8 -istage2_mmu=system.cpu1.istage2_mmu -itb=system.cpu1.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=1280 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=true -system=system -tracer=system.cpu1.tracer -trapLatency=13 -wbWidth=8 -workload= - -[system.cpu1.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu1.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu1.dtb - -[system.cpu1.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu1.dstage2_mmu.stage2_tlb.walker - -[system.cpu1.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu1.dtb.walker - -[system.cpu1.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 -eventq_index=0 - -[system.cpu1.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu1.fuPool.FUList0.opList - -[system.cpu1.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 - -[system.cpu1.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu1.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu1.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 - -[system.cpu1.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu1.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu1.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu1.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 - -[system.cpu1.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu1.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu1.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu1.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu1.fuPool.FUList4.opList - -[system.cpu1.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 - -[system.cpu1.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu1.fuPool.FUList6.opList - -[system.cpu1.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 - -[system.cpu1.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu1.fuPool.FUList8.opList - -[system.cpu1.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu1.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu1.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu1.itb - -[system.cpu1.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu1.istage2_mmu.stage2_tlb.walker - -[system.cpu1.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu1.itb.walker - -[system.cpu1.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=2147483648:2415919103 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[3] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.l2c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.l2c.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - -[system.l2c.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access=warn -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.075000 -IDD02=0.000000 -IDD2N=0.050000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.000000 -IDD2P12=0.000000 -IDD3N=0.057000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.000000 -IDD3P12=0.000000 -IDD4R=0.187000 -IDD4R2=0.000000 -IDD4W=0.165000 -IDD4W2=0.000000 -IDD5=0.220000 -IDD52=0.000000 -IDD6=0.000000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=2147483648:2415919103 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=0 -tXPDLL=0 -tXS=0 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[5] - -[system.realview] -type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.realview.aaci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470024192 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[18] - -[system.realview.cf_ctrl] -type=IdeController -BAR0=471465984 -BAR0LegacyIO=true -BAR0Size=256 -BAR1=471466240 -BAR1LegacyIO=true -BAR1Size=4096 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=1 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=2 -default_p_state=UNDEFINED -disks= -eventq_index=0 -host=system.realview.pci_host -io_shift=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=2 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[2] -pio=system.iobus.master[9] - -[system.realview.clcd] -type=Pl111 -amba_id=1315089 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=46 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471793664 -pio_latency=10000 -pixel_clock=41667 -power_model=Null -system=system -vnc=system.vncserver -dma=system.iobus.slave[1] -pio=system.iobus.master[5] - -[system.realview.dcc] -type=SubSystem -children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys -eventq_index=0 -thermal_domain=Null - -[system.realview.dcc.osc_cpu] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_ddr] -type=RealViewOsc -dcc=0 -device=8 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_hsbm] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_pxl] -type=RealViewOsc -dcc=0 -device=5 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_smb] -type=RealViewOsc -dcc=0 -device=6 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_sys] -type=RealViewOsc -dcc=0 -device=7 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.energy_ctrl] -type=EnergyCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dvfs_handler=system.dvfs_handler -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470286336 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[22] - -[system.realview.ethernet] -type=IGbE -BAR0=0 -BAR0LegacyIO=false -BAR0Size=131072 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=0 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=4213 -ExpansionROM=0 -HeaderType=0 -InterruptLine=1 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=255 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=0 -SubClassCode=0 -SubsystemID=4104 -SubsystemVendorID=32902 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -eventq_index=0 -fetch_comp_delay=10000 -fetch_delay=10000 -hardware_address=00:90:00:00:00:01 -host=system.realview.pci_host -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -phy_epid=896 -phy_pid=680 -pio_latency=30000 -power_model=Null -rx_desc_cache_size=64 -rx_fifo_size=393216 -rx_write_delay=0 -system=system -tx_desc_cache_size=64 -tx_fifo_size=393216 -tx_read_delay=0 -wb_comp_delay=10000 -wb_delay=10000 -dma=system.iobus.slave[4] -pio=system.iobus.master[24] - -[system.realview.generic_timer] -type=GenericTimer -eventq_index=0 -gic=system.realview.gic -int_phys=29 -int_virt=27 -system=system - -[system.realview.gic] -type=Pl390 -clk_domain=system.clk_domain -cpu_addr=738205696 -cpu_pio_delay=10000 -default_p_state=UNDEFINED -dist_addr=738201600 -dist_pio_delay=10000 -eventq_index=0 -gem5_extensions=true -int_latency=10000 -it_lines=128 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -platform=system.realview -power_model=Null -system=system -pio=system.membus.master[2] - -[system.realview.hdlcd] -type=HDLcd -amba_id=1314816 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=117 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=721420288 -pio_latency=10000 -pixel_buffer_size=2048 -pixel_chunk=32 -power_model=Null -pxl_clk=system.realview.dcc.osc_pxl -system=system -vnc=system.vncserver -workaround_dma_line_count=true -workaround_swap_rb=true -dma=system.membus.slave[0] -pio=system.iobus.master[6] - -[system.realview.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=2 -InterruptPin=2 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.cf0 -eventq_index=0 -host=system.realview.pci_host -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[3] -pio=system.iobus.master[23] - -[system.realview.kmi0] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=44 -is_mouse=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470155264 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[7] - -[system.realview.kmi1] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=45 -is_mouse=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470220800 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[8] - -[system.realview.l2x0_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=739246080 -pio_latency=100000 -pio_size=4095 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.realview.lan_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=436207616 -pio_latency=100000 -pio_size=65535 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.realview.local_cpu_timer] -type=CpuLocalTimer -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num_timer=29 -int_num_watchdog=30 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=738721792 -pio_latency=100000 -power_model=Null -system=system -pio=system.membus.master[4] - -[system.realview.mcc] -type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl -eventq_index=0 -thermal_domain=Null - -[system.realview.mcc.osc_clcd] -type=RealViewOsc -dcc=0 -device=1 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_mcc] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_peripheral] -type=RealViewOsc -dcc=0 -device=2 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_system_bus] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.temp_crtl] -type=RealViewTemperatureSensor -dcc=0 -device=0 -eventq_index=0 -parent=system.realview.realview_io -position=0 -site=0 -system=system - -[system.realview.mmc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470089728 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.realview.nvmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:67108863 -port=system.membus.master[1] - -[system.realview.pci_host] -type=GenericPciHost -clk_domain=system.clk_domain -conf_base=805306368 -conf_device_bits=16 -conf_size=268435456 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=0 -pci_pio_base=0 -platform=system.realview -power_model=Null -system=system -pio=system.iobus.master[2] - -[system.realview.realview_io] -type=RealViewCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -idreg=35979264 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469827584 -pio_latency=100000 -power_model=Null -proc_id0=335544320 -proc_id1=335544320 -system=system -pio=system.iobus.master[1] - -[system.realview.rtc] -type=PL031 -amba_id=3412017 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=36 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471269376 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[10] - -[system.realview.sp810_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469893120 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[16] - -[system.realview.timer0] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=34 -int_num1=34 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470876160 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[3] - -[system.realview.timer1] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=35 -int_num1=35 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470941696 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[4] - -[system.realview.uart] -type=Pl011 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -end_on_eot=false -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=37 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470351872 -pio_latency=100000 -platform=system.realview -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[0] - -[system.realview.uart1_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470417408 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[13] - -[system.realview.uart2_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470482944 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[14] - -[system.realview.uart3_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470548480 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[15] - -[system.realview.usb_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=452984832 -pio_latency=100000 -pio_size=131071 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.realview.vgic] -type=VGic -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -hv_addr=738213888 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_delay=10000 -platform=system.realview -power_model=Null -ppint=25 -system=system -vcpu_addr=738222080 -pio=system.membus.master[3] - -[system.realview.vram] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=402653184:436207615 -port=system.iobus.master[11] - -[system.realview.watchdog_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470745088 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[17] - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port - -[system.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.vncserver] -type=VncServer -eventq_index=0 -frame_capture=false -number=0 -port=5900 - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr deleted file mode 100755 index 652b4376c..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr +++ /dev/null @@ -1,66 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting vnc client connections -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Existing EnergyCtrl, but no enabled DVFSHandler found. -warn: Not doing anything for miscreg ACTLR -warn: Not doing anything for write of miscreg ACTLR -warn: The clidr register always reports 0 caches. -warn: clidr LoUIS field of 0b001 to match current ARM implementations. -warn: The csselr register isn't implemented. -warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] -warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr dccimvac' unimplemented -warn: Tried to read RealView I/O at offset 0x60 that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4] -warn: CP14 unimplemented crn[1], opc1[4], crm[12], opc2[0] -warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] -warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] -warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] -warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] -warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] -warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] -warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1] -warn: Returning zero for read from miscreg pmcr -warn: Ignoring write to miscreg pmcntenclr -warn: Ignoring write to miscreg pmintenclr -warn: Ignoring write to miscreg pmovsr -warn: Ignoring write to miscreg pmcr -warn: CP14 unimplemented crn[5], opc1[4], crm[8], opc2[2] -warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2] -warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5] -warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0] -warn: CP14 unimplemented crn[3], opc1[4], crm[0], opc2[3] -warn: CP14 unimplemented crn[3], opc1[4], crm[4], opc2[3] -warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[0] -warn: instruction 'mcr dcisw' unimplemented -warn: CP14 unimplemented crn[14], opc1[7], crm[1], opc2[0] -warn: CP14 unimplemented crn[14], opc1[7], crm[14], opc2[7] -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: instruction 'mcr bpiall' unimplemented -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout deleted file mode 100755 index daaefa924..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout +++ /dev/null @@ -1,11 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12213 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 - -Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt deleted file mode 100644 index 21f94071a..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ /dev/null @@ -1,2704 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.804492 # Number of seconds simulated -sim_ticks 2804492191000 # Number of ticks simulated -final_tick 2804492191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104736 # Simulator instruction rate (inst/s) -host_op_rate 127120 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2512420654 # Simulator tick rate (ticks/s) -host_mem_usage 592468 # Number of bytes of host memory used -host_seconds 1116.25 # Real time elapsed on the host -sim_insts 116911529 # Number of instructions simulated -sim_ops 141898255 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 4032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 689856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4962016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 4288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 685888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4855432 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11202536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 689856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 685888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1375744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8427008 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8444532 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 63 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10779 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 78050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 67 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10717 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75868 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175560 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131672 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136053 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 245982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1769310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 244568 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1731305 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3994497 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 245982 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 244568 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 490550 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3004825 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3011073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3004825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 245982 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1775556 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 244568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1731308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7005571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175561 # Number of read requests accepted -system.physmem.writeReqs 136053 # Number of write requests accepted -system.physmem.readBursts 175561 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 136053 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11226560 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue -system.physmem.bytesWritten 8456704 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11202600 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8444532 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11215 # Per bank write bursts -system.physmem.perBankRdBursts::1 11147 # Per bank write bursts -system.physmem.perBankRdBursts::2 11273 # Per bank write bursts -system.physmem.perBankRdBursts::3 10737 # Per bank write bursts -system.physmem.perBankRdBursts::4 11860 # Per bank write bursts -system.physmem.perBankRdBursts::5 11441 # Per bank write bursts -system.physmem.perBankRdBursts::6 12346 # Per bank write bursts -system.physmem.perBankRdBursts::7 11875 # Per bank write bursts -system.physmem.perBankRdBursts::8 10047 # Per bank write bursts -system.physmem.perBankRdBursts::9 10348 # Per bank write bursts -system.physmem.perBankRdBursts::10 10556 # Per bank write bursts -system.physmem.perBankRdBursts::11 9541 # Per bank write bursts -system.physmem.perBankRdBursts::12 10610 # Per bank write bursts -system.physmem.perBankRdBursts::13 11371 # Per bank write bursts -system.physmem.perBankRdBursts::14 10552 # Per bank write bursts -system.physmem.perBankRdBursts::15 10496 # Per bank write bursts -system.physmem.perBankWrBursts::0 8375 # Per bank write bursts -system.physmem.perBankWrBursts::1 8461 # Per bank write bursts -system.physmem.perBankWrBursts::2 8703 # Per bank write bursts -system.physmem.perBankWrBursts::3 8182 # Per bank write bursts -system.physmem.perBankWrBursts::4 8713 # Per bank write bursts -system.physmem.perBankWrBursts::5 8565 # Per bank write bursts -system.physmem.perBankWrBursts::6 9253 # Per bank write bursts -system.physmem.perBankWrBursts::7 8873 # Per bank write bursts -system.physmem.perBankWrBursts::8 7587 # Per bank write bursts -system.physmem.perBankWrBursts::9 7750 # Per bank write bursts -system.physmem.perBankWrBursts::10 7865 # Per bank write bursts -system.physmem.perBankWrBursts::11 7197 # Per bank write bursts -system.physmem.perBankWrBursts::12 8117 # Per bank write bursts -system.physmem.perBankWrBursts::13 8726 # Per bank write bursts -system.physmem.perBankWrBursts::14 7969 # Per bank write bursts -system.physmem.perBankWrBursts::15 7800 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 2804492012500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 542 # Read request sizes (log2) -system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 175005 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 4381 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131672 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 103754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1717 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64611 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 304.641624 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.481113 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.031220 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24202 37.46% 37.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15601 24.15% 61.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6722 10.40% 72.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3765 5.83% 77.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2815 4.36% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1576 2.44% 84.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1095 1.69% 86.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1044 1.62% 87.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7791 12.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64611 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6681 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.254154 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 478.043046 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6679 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6681 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6681 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.777878 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.220598 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.301236 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 12 0.18% 0.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 6 0.09% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 6 0.09% 0.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 5 0.07% 0.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5747 86.02% 86.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 151 2.26% 88.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 95 1.42% 90.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 50 0.75% 90.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 278 4.16% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 50 0.75% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 23 0.34% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 15 0.22% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 16 0.24% 96.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.07% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.13% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 158 2.36% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.01% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.04% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.06% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.06% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 8 0.12% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.15% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6681 # Writes before turning the bus around for reads -system.physmem.totQLat 2656456250 # Total ticks spent queuing -system.physmem.totMemAccLat 5945487500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 877075000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15143.84 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33893.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.00 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.99 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.01 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.27 # Average write queue length when enqueuing -system.physmem.readRowHits 144956 # Number of row buffer hits during reads -system.physmem.writeRowHits 97983 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.14 # Row buffer hit rate for writes -system.physmem.avgGap 8999890.93 # Average gap between requests -system.physmem.pageHitRate 78.98 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 256646880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140035500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 716765400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 447930000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 183175683600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 77871232575 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1614386322750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1876994616705 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.281811 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2685576144250 # Time in different power states -system.physmem_0.memoryStateTime::REF 93648100000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 25267936250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 231812280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 126484875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 651463800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 408311280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 183175683600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 76860878220 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1615272598500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1876727232555 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.186470 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2687058026250 # Time in different power states -system.physmem_1.memoryStateTime::REF 93648100000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23784590000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 768 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 768 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 768 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 12 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 274 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 274 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 274 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 274 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 274 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 274 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 26597024 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13781156 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 500525 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 15548162 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8034631 # Number of BTB hits -system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 51.675761 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6612410 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28559 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 4512781 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 4401242 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 111539 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 32310 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 58420 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 58420 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17812 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14989 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 25619 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 32801 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 529.800921 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3188.709692 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 31978 97.49% 97.49% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 569 1.73% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 144 0.44% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 64 0.20% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 17 0.05% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 11 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-73727 7 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 32801 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 12297 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 10850.939253 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9044.162625 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7100.469115 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-8191 4812 39.13% 39.13% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::8192-16383 6113 49.71% 88.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-24575 1067 8.68% 97.52% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::24576-32767 142 1.15% 98.67% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-40959 98 0.80% 99.47% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::40960-49151 40 0.33% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-57343 6 0.05% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::57344-65535 3 0.02% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::73728-81919 1 0.01% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-90111 7 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::90112-98303 3 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-106495 4 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::106496-114687 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 12297 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 80893915836 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.682843 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.485602 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 80818881836 99.91% 99.91% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 52303000 0.06% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 11277500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4307500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2702500 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1677000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 813500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 1083500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 273500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 145500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-21 137500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::22-23 22500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-25 149000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::26-27 15000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-29 8000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::30-31 118500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 80893915836 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3573 69.87% 69.87% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1541 30.13% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5114 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 58420 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 58420 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5114 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5114 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 63534 # Table walker requests started/completed, data/inst -system.cpu0.dtb.inst_hits 0 # ITB inst hits -system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 13811519 # DTB read hits -system.cpu0.dtb.read_misses 49680 # DTB read misses -system.cpu0.dtb.write_hits 10255920 # DTB write hits -system.cpu0.dtb.write_misses 8740 # DTB write misses -system.cpu0.dtb.flush_tlb 180 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3407 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 831 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1345 # Number of TLB faults due to prefetch -system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 681 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 13861199 # DTB read accesses -system.cpu0.dtb.write_accesses 10264660 # DTB write accesses -system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24067439 # DTB hits -system.cpu0.dtb.misses 58420 # DTB misses -system.cpu0.dtb.accesses 24125859 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 7709 # Table walker walks requested -system.cpu0.itb.walker.walksShort 7709 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2350 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4518 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 841 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 6868 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1028.028538 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 4446.105505 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-8191 6539 95.21% 95.21% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-16383 228 3.32% 98.53% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-24575 54 0.79% 99.32% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-32767 25 0.36% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-40959 8 0.12% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-49151 8 0.12% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::57344-65535 3 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::73728-81919 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-106495 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 6868 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3155 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 10383.835182 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 8379.659125 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7218.357480 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1697 53.79% 53.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 897 28.43% 82.22% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 526 16.67% 98.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 22 0.70% 99.59% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 6 0.19% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 4 0.13% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 2 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3155 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 33631218080 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.664997 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.472178 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 11268855428 33.51% 33.51% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 22360574652 66.49% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 1449000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 215000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 92500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 31500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 33631218080 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1735 74.98% 74.98% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 579 25.02% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2314 # Table walker page sizes translated -system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7709 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7709 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2314 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2314 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 10023 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 19932883 # ITB inst hits -system.cpu0.itb.inst_misses 7709 # ITB inst misses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 180 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2198 # Number of entries that have been flushed from TLB -system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1360 # Number of TLB faults due to permissions restrictions -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 19940592 # ITB inst accesses -system.cpu0.itb.hits 19932883 # DTB hits -system.cpu0.itb.misses 7709 # DTB misses -system.cpu0.itb.accesses 19940592 # DTB accesses -system.cpu0.numPwrStateTransitions 3142 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1571 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 940850098.166136 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 18809432155.510696 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1535 97.71% 97.71% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 33 2.10% 99.81% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.06% 99.87% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.13% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499976941836 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1571 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 1326416686781 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1478075504219 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 106432025 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 39943206 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 102521046 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 26597024 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19048283 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 61908935 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3115038 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 100477 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 4639 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 343 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 145025 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 124692 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 417 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 19931005 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 352594 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3944 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 103785216 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.188198 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.291827 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 75467525 72.72% 72.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3816070 3.68% 76.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2355731 2.27% 78.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 7980688 7.69% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1585704 1.53% 87.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 994797 0.96% 88.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6063354 5.84% 94.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1019951 0.98% 95.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4501396 4.34% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 103785216 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.249897 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.963254 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 27593672 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58026004 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15320051 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1430610 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1414570 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1827863 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 144800 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 84662278 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 478152 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1414570 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28401012 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6705964 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 43841646 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 15935208 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7486513 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 81019638 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 3792 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1047421 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 274733 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 5461326 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 83455149 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 373514562 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 90323598 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 7046 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 70490289 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12964860 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1525331 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1431631 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8308638 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 14616199 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11309054 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1973588 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2673938 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 78051120 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1056498 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 74882378 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 90977 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10675596 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 23316802 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 112757 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 103785216 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.721513 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.414764 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 73772912 71.08% 71.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10078271 9.71% 80.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7660438 7.38% 88.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6348835 6.12% 94.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2285768 2.20% 96.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1455335 1.40% 97.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1487712 1.43% 99.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 476853 0.46% 99.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 219092 0.21% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 103785216 # Number of insts issued each cycle -system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 97071 8.87% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 526414 48.10% 56.97% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 471010 43.03% 100.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2186 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 49813565 66.52% 66.53% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57268 0.08% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.60% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4356 0.01% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14194612 18.96% 85.56% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10810388 14.44% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 74882378 # Type of FU issued -system.cpu0.iq.rate 0.703570 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1094496 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014616 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 254720610 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 89827638 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 72651171 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 14835 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 9007 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 6569 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 75966729 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 7959 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 355417 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2067343 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2157 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 54598 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1028774 # Number of stores squashed -system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 204196 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 85944 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1414570 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5871401 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 626694 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 79236238 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 107112 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 14616199 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11309054 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 550325 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 44645 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 570692 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 54598 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 206831 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 220981 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 427812 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 74329730 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 13972872 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 494338 # Number of squashed instructions skipped in execute -system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 128620 # number of nop insts executed -system.cpu0.iew.exec_refs 24687619 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14050828 # Number of branches executed -system.cpu0.iew.exec_stores 10714747 # Number of stores executed -system.cpu0.iew.exec_rate 0.698377 # Inst execution rate -system.cpu0.iew.wb_sent 73810336 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 72657740 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 37782988 # num instructions producing a value -system.cpu0.iew.wb_consumers 65726436 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.682668 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.574852 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 10630509 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 943741 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 357539 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 101347140 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.676054 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.564689 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 74567913 73.58% 73.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12119278 11.96% 85.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6061489 5.98% 91.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2574374 2.54% 94.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1279376 1.26% 95.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 838406 0.83% 96.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1806795 1.78% 97.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 395599 0.39% 98.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1703910 1.68% 100.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 101347140 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 56273825 # Number of instructions committed -system.cpu0.commit.committedOps 68516155 # Number of ops (including micro ops) committed -system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 22829136 # Number of memory references committed -system.cpu0.commit.loads 12548856 # Number of loads committed -system.cpu0.commit.membars 380096 # Number of memory barriers committed -system.cpu0.commit.branches 13320608 # Number of branches committed -system.cpu0.commit.fp_insts 6081 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 59986977 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2613752 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 45626966 66.59% 66.59% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55700 0.08% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.67% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4353 0.01% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.68% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12548856 18.32% 85.00% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10280280 15.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 68516155 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1703910 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 166404387 # The number of ROB reads -system.cpu0.rob.rob_writes 160730663 # The number of ROB writes -system.cpu0.timesIdled 403591 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2646809 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2956150979 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 56189692 # Number of Instructions Simulated -system.cpu0.committedOps 68432022 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.894156 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.894156 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.527940 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.527940 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 80895945 # number of integer regfile reads -system.cpu0.int_regfile_writes 46256017 # number of integer regfile writes -system.cpu0.fp_regfile_reads 17128 # number of floating regfile reads -system.cpu0.fp_regfile_writes 13236 # number of floating regfile writes -system.cpu0.cc_regfile_reads 262969083 # number of cc regfile reads -system.cpu0.cc_regfile_writes 27284448 # number of cc regfile writes -system.cpu0.misc_regfile_reads 188741772 # number of misc regfile reads -system.cpu0.misc_regfile_writes 723817 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 851102 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.984391 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42341917 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 851614 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.719611 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 92671500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.368893 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.615499 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.360095 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.639874 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189170266 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189170266 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 12276993 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12891400 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25168393 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7660658 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 8240277 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15900935 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178519 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 185010 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 363529 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 209836 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 236717 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 446553 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216124 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 243253 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459377 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 19937651 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21131677 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41069328 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20116170 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21316687 # number of overall hits -system.cpu0.dcache.overall_hits::total 41432857 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 401226 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 429872 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 831098 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1944439 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1754085 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 3698524 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 79996 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 103567 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 183563 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13679 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 13937 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 27616 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 39 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 31 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 70 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2345665 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2183957 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4529622 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2425661 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 2287524 # number of overall misses -system.cpu0.dcache.overall_misses::total 4713185 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6001869000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6540022000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 12541891000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85882896000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 79793795696 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 165676691696 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 178954000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 206024000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 384978000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 605500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 494000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 1099500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 91884765000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 86333817696 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 178218582696 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 91884765000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 86333817696 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 178218582696 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 12678219 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 13321272 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 25999491 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9605097 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9994362 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19599459 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 258515 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 288577 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 547092 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223515 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 250654 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 474169 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216163 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 243284 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 459447 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 22283316 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 23315634 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 45598950 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 22541831 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 23604211 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 46146042 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031647 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032270 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.031966 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.202438 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.175507 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.188705 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.309444 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.358889 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.335525 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061199 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.055603 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058241 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000180 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000127 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000152 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.105266 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.093669 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.099336 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107607 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.096912 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.102136 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14958.823705 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15213.882272 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15090.748624 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44168.470186 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45490.267402 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44795.353956 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13082.389064 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14782.521346 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13940.396871 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15525.641026 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15935.483871 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15707.142857 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39172.160134 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39530.914618 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39345.133589 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37880.299432 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37741.163676 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37812.770493 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1147990 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 183848 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 53098 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 2861 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.620212 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 64.260049 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 702238 # number of writebacks -system.cpu0.dcache.writebacks::total 702238 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 190024 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 217945 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 407969 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1788584 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1610518 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3399102 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9563 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8886 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18449 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1978608 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1828463 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3807071 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1978608 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1828463 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3807071 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 211202 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 211927 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 423129 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 155855 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 143567 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 299422 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 55758 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 66999 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 122757 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4116 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5051 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9167 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 39 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 31 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 70 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 367057 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 355494 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 722551 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 422815 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 422493 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 845308 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16331 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 14796 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15929 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 11655 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32260 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 26451 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3008616500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 3065906000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6074522500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7160903385 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6753725936 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13914629321 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 778587000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 955209000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1733796000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 53300000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84160500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137460500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 566500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 463000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1029500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10169519885 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9819631936 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 19989151821 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10948106885 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10774840936 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 21722947821 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3301571000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3002627500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6304198500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3301571000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3002627500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6304198500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016659 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015909 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016275 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016226 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014365 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015277 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.215686 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.232170 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224381 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018415 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020151 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019333 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000180 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000127 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000152 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016472 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015247 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015846 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018757 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017899 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018318 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14245.208379 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14466.802248 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14356.195156 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45945.932983 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47042.328223 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46471.633083 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13963.682342 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14257.063538 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14123.805567 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12949.465500 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16662.146110 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14995.145631 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14525.641026 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14935.483871 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14707.142857 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27705.560403 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27622.496965 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27664.693317 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25893.373899 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25503.004632 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25698.263616 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202165.880840 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 202935.083806 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202531.516047 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 102342.560446 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 113516.596726 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 107376.786292 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1935798 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.566475 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 38706343 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1936310 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 19.989745 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9778864500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 232.011267 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 279.555207 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.453147 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.546006 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999153 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 153 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 42727106 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 42727106 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 18888703 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19817640 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 38706343 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 18888703 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 19817640 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 38706343 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 18888703 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 19817640 # number of overall hits -system.cpu0.icache.overall_hits::total 38706343 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1041631 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 1042707 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2084338 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1041631 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 1042707 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2084338 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1041631 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 1042707 # number of overall misses -system.cpu0.icache.overall_misses::total 2084338 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14123286486 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14169720487 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 28293006973 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14123286486 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 14169720487 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 28293006973 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14123286486 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 14169720487 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 28293006973 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 19930334 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 20860347 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 40790681 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 19930334 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 20860347 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 40790681 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 19930334 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 20860347 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 40790681 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.052264 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.049985 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.051098 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.052264 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.049985 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.051098 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.052264 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.049985 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.051098 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13558.819281 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13589.359702 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13574.097374 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13558.819281 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13589.359702 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13574.097374 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13558.819281 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13589.359702 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13574.097374 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 11799 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 615 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.185366 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1935798 # number of writebacks -system.cpu0.icache.writebacks::total 1935798 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 72135 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 75777 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 147912 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 72135 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 75777 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 147912 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 72135 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 75777 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 147912 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 969496 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 966930 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1936426 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 969496 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 966930 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1936426 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 969496 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 966930 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1936426 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 667 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 667 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 667 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 667 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12493413990 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12512123492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 25005537482 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12493413990 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12512123492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 25005537482 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12493413990 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12512123492 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 25005537482 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 53482500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 53482500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 53482500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 53482500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.048644 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046353 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047472 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.048644 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046353 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047472 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.048644 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046353 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.047472 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12886.503905 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12940.050978 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12913.241963 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12886.503905 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12940.050978 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12913.241963 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12886.503905 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12940.050978 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12913.241963 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 80183.658171 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80183.658171 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 80183.658171 # average overall mshr uncacheable latency -system.cpu1.branchPred.lookups 27768467 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14444745 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 516645 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 16732156 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 8530484 # Number of BTB hits -system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 50.982575 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6847641 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 29585 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 4618056 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 4506231 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 111825 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 32588 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 59138 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 59138 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19056 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 14153 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 25929 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 33209 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 492.833268 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3043.837220 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-8191 32423 97.63% 97.63% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-16383 540 1.63% 99.26% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-24575 149 0.45% 99.71% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-32767 52 0.16% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-40959 16 0.05% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-49151 18 0.05% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-57343 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::57344-65535 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-73727 5 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 33209 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 12964 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10951.828139 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9214.622989 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6533.603209 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 4889 37.71% 37.71% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 6655 51.33% 89.05% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1022 7.88% 96.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 238 1.84% 98.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 117 0.90% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 38 0.29% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 2 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 12964 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 90072330428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.721128 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.470247 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 89999642928 99.92% 99.92% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 51122000 0.06% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 10756000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 3956500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 2349000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 1202000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 700500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 1277500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 267000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 187000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-21 117000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::22-23 117500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-25 238000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::26-27 36000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-29 19500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::30-31 342000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 90072330428 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3730 69.60% 69.60% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1629 30.40% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5359 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 59138 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 59138 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5359 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5359 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 64497 # Table walker requests started/completed, data/inst -system.cpu1.dtb.inst_hits 0 # ITB inst hits -system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14518023 # DTB read hits -system.cpu1.dtb.read_misses 50239 # DTB read misses -system.cpu1.dtb.write_hits 10641437 # DTB write hits -system.cpu1.dtb.write_misses 8899 # DTB write misses -system.cpu1.dtb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 475 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3373 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 787 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1128 # Number of TLB faults due to prefetch -system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 610 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14568262 # DTB read accesses -system.cpu1.dtb.write_accesses 10650336 # DTB write accesses -system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 25159460 # DTB hits -system.cpu1.dtb.misses 59138 # DTB misses -system.cpu1.dtb.accesses 25218598 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 7663 # Table walker walks requested -system.cpu1.itb.walker.walksShort 7663 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2322 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4510 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 831 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 6832 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 994.072014 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 4194.954654 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-8191 6528 95.55% 95.55% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-16383 212 3.10% 98.65% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-24575 44 0.64% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-32767 27 0.40% 99.69% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-40959 9 0.13% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::40960-49151 4 0.06% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::49152-57343 5 0.07% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 6832 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 3180 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10355.188679 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8393.071987 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7092.645451 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 28 0.88% 0.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 1663 52.30% 53.18% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 542 17.04% 70.22% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 404 12.70% 82.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 34 1.07% 83.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 470 14.78% 98.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 0.47% 99.25% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.22% 99.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 6 0.19% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.09% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 5 0.16% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 3 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 3180 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 25646768488 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.764516 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.424553 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 6041654948 23.56% 23.56% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 19603312040 76.44% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 1413500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 335000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 53000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 25646768488 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1773 75.48% 75.48% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 576 24.52% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2349 # Table walker page sizes translated -system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7663 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7663 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2349 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2349 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 10012 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 20862819 # ITB inst hits -system.cpu1.itb.inst_misses 7663 # ITB inst misses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 475 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2217 # Number of entries that have been flushed from TLB -system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1301 # Number of TLB faults due to permissions restrictions -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20870482 # ITB inst accesses -system.cpu1.itb.hits 20862819 # DTB hits -system.cpu1.itb.misses 7663 # DTB misses -system.cpu1.itb.accesses 20870482 # DTB accesses -system.cpu1.numPwrStateTransitions 2936 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 1468 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 829956972.596730 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 15801466276.187872 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1432 97.55% 97.55% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 33 2.25% 99.80% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.07% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.07% 99.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.07% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 499953982692 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 1468 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 1586115355228 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1218376835772 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 109612747 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 40790032 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 108316651 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27768467 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19884356 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 64224291 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3206570 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 101756 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 7200 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 365 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 143510 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 122842 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 226 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20860348 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 361284 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3826 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 106993471 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.215539 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.315939 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 77281815 72.23% 72.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3963095 3.70% 75.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2488318 2.33% 78.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8243119 7.70% 85.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1612889 1.51% 87.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1184021 1.11% 88.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6282411 5.87% 94.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1182908 1.11% 95.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4754895 4.44% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 106993471 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.253332 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.988176 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27827531 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 60076040 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15861302 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1770624 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1457723 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1995842 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 147467 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 90138607 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 489536 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1457723 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28780463 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 5201978 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 47127740 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16672085 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 7753197 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 86299553 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2624 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1735423 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 210199 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 5005527 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 89489706 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 397397955 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 96183965 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6079 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 76183985 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13305705 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1606232 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1504962 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10217330 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15336831 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11768795 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2172366 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2803589 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 83184481 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1153102 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 79902588 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 90974 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10871346 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24449389 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 102910 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 106993471 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.746799 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.430875 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 74936839 70.04% 70.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10763085 10.06% 80.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8157485 7.62% 87.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6811202 6.37% 94.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2499268 2.34% 96.42% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1551620 1.45% 97.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1531718 1.43% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 492585 0.46% 99.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 249669 0.23% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 106993471 # Number of insts issued each cycle -system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 113986 9.89% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 7 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 526393 45.65% 55.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 512676 44.46% 100.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 151 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 53671519 67.17% 67.17% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59014 0.07% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 3 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4219 0.01% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14905160 18.65% 85.90% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11262520 14.10% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 79902588 # Type of FU issued -system.cpu1.iq.rate 0.728953 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1153062 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014431 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 268029337 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 95251361 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 77606677 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 13346 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7483 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5728 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 81048267 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7232 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 350880 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2084815 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2040 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 50958 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1010162 # Number of stores squashed -system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 192812 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 110845 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1457723 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4213427 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 739361 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 84450588 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 107924 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15336831 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11768795 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 583687 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 43916 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 682784 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 50958 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 221001 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 225315 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 446316 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 79342272 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14681206 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 501344 # Number of squashed instructions skipped in execute -system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 113005 # number of nop insts executed -system.cpu1.iew.exec_refs 25846099 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14786732 # Number of branches executed -system.cpu1.iew.exec_stores 11164893 # Number of stores executed -system.cpu1.iew.exec_rate 0.723842 # Inst execution rate -system.cpu1.iew.wb_sent 78781509 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 77612405 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 40957824 # num instructions producing a value -system.cpu1.iew.wb_consumers 71653116 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.708060 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.571613 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 10899776 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1050192 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 371047 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 104491444 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.703761 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.593714 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 75982461 72.72% 72.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12681627 12.14% 84.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6552474 6.27% 91.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2740841 2.62% 93.75% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1432894 1.37% 95.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 937550 0.90% 96.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1880638 1.80% 97.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 438919 0.42% 98.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1844040 1.76% 100.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 104491444 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 60792609 # Number of instructions committed -system.cpu1.commit.committedOps 73537005 # Number of ops (including micro ops) committed -system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 24010649 # Number of memory references committed -system.cpu1.commit.loads 13252016 # Number of loads committed -system.cpu1.commit.membars 434207 # Number of memory barriers committed -system.cpu1.commit.branches 14055285 # Number of branches committed -system.cpu1.commit.fp_insts 5347 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 64446138 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2722289 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 49464791 67.27% 67.27% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57349 0.08% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4216 0.01% 67.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.35% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.35% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 13252016 18.02% 85.37% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10758633 14.63% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 73537005 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1844040 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 174349530 # The number of ROB reads -system.cpu1.rob.rob_writes 171375071 # The number of ROB writes -system.cpu1.timesIdled 393969 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2619276 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2436753643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 60721837 # Number of Instructions Simulated -system.cpu1.committedOps 73466233 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.805162 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.805162 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.553967 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.553967 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 86273419 # number of integer regfile reads -system.cpu1.int_regfile_writes 49465455 # number of integer regfile writes -system.cpu1.fp_regfile_reads 16586 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13020 # number of floating regfile writes -system.cpu1.cc_regfile_reads 280148251 # number of cc regfile reads -system.cpu1.cc_regfile_writes 29662918 # number of cc regfile writes -system.cpu1.misc_regfile_reads 196736132 # number of misc regfile reads -system.cpu1.misc_regfile_writes 795813 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 30198 # Transaction distribution -system.iobus.trans_dist::ReadResp 30198 # Transaction distribution -system.iobus.trans_dist::WriteReq 59014 # Transaction distribution -system.iobus.trans_dist::WriteResp 59014 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 49487000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 335000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 12500 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 87500 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 619500 # Layer occupancy (ticks) -system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 49000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6425500 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38207500 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187822672 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36409 # number of replacements -system.iocache.tags.tagsinuse 0.981311 # Cycle average of tags in use -system.iocache.tags.total_refs 30 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 234301648000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.981311 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.061332 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.061332 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328227 # Number of tag accesses -system.iocache.tags.data_accesses 328227 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits -system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits -system.iocache.demand_hits::realview.ide 29 # number of demand (read+write) hits -system.iocache.demand_hits::total 29 # number of demand (read+write) hits -system.iocache.overall_hits::realview.ide 29 # number of overall hits -system.iocache.overall_hits::total 29 # number of overall hits -system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses -system.iocache.ReadReq_misses::total 249 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36444 # number of demand (read+write) misses -system.iocache.demand_misses::total 36444 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36444 # number of overall misses -system.iocache.overall_misses::total 36444 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31226877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31226877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4279492795 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4279492795 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4310719672 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4310719672 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4310719672 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4310719672 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36473 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36473 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36473 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36473 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ide 0.999205 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 0.999205 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ide 0.999205 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 0.999205 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 125409.144578 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125409.144578 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118234.363724 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118234.363724 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118283.384700 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118283.384700 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118283.384700 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118283.384700 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 36160 # number of writebacks -system.iocache.writebacks::total 36160 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 36195 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 36195 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36444 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36444 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36444 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36444 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18776877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18776877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2467614128 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2467614128 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2486391005 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2486391005 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2486391005 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2486391005 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.999199 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.999205 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.999205 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.999205 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.999205 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75409.144578 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75409.144578 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68175.552645 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68175.552645 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68224.975442 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68224.975442 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68224.975442 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68224.975442 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 104452 # number of replacements -system.l2c.tags.tagsinuse 65213.501449 # Cycle average of tags in use -system.l2c.tags.total_refs 5432730 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169859 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 31.983763 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 79304011000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::cpu0.dtb.walker 47.675626 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999974 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4819.813719 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 29687.680351 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 45.444052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5864.770891 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 24747.116836 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000727 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073545 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.452998 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000693 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.089489 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.377611 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995079 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 81 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65326 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 81 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7443 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 57733 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.001236 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.996796 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45059004 # Number of tag accesses -system.l2c.tags.data_accesses 45059004 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 34072 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5784 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 34667 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5734 # number of ReadReq hits -system.l2c.ReadReq_hits::total 80257 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 702238 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 702238 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1896138 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1896138 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 1486 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1347 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2833 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 83730 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 74268 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 157998 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 959179 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 956058 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1915237 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 263950 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 275779 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 539729 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 34072 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5784 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 959179 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 347680 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 34667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5734 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 956058 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 350047 # number of demand (read+write) hits -system.l2c.demand_hits::total 2693221 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 34072 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5784 # number of overall hits -system.l2c.overall_hits::cpu0.inst 959179 # number of overall hits -system.l2c.overall_hits::cpu0.data 347680 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 34667 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5734 # number of overall hits -system.l2c.overall_hits::cpu1.inst 956058 # number of overall hits -system.l2c.overall_hits::cpu1.data 350047 # number of overall hits -system.l2c.overall_hits::total 2693221 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 63 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 67 # number of ReadReq misses -system.l2c.ReadReq_misses::total 131 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 70652 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 67960 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 138612 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 10133 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 10722 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 20855 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 7109 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 8186 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 15295 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 63 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10133 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 77761 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 67 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 10722 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 76146 # number of demand (read+write) misses -system.l2c.demand_misses::total 174893 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 63 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10133 # number of overall misses -system.l2c.overall_misses::cpu0.data 77761 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 67 # number of overall misses -system.l2c.overall_misses::cpu1.inst 10722 # number of overall misses -system.l2c.overall_misses::cpu1.data 76146 # number of overall misses -system.l2c.overall_misses::total 174893 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 5419500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 83500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 5672000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 11175000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 117000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 117000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 234000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 80500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 82000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6018936000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5732524500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11751460500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 841429998 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 896833500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1738263498 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 615939500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 732639500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 1348579000 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 5419500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 83500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 841429998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 6634875500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 5672000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 896833500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6465164000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 14849477998 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 5419500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 83500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 841429998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 6634875500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 5672000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 896833500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6465164000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 14849477998 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 34135 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 5785 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 34734 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5734 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 80388 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 702238 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 702238 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1896138 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1896138 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1490 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1351 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2841 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 39 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 31 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 70 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 154382 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 142228 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296610 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 969312 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 966780 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1936092 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 271059 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 283965 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 555024 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 34135 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 5785 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 969312 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 425441 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 34734 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5734 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 966780 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 426193 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2868114 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 34135 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5785 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 969312 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 425441 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 34734 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5734 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 966780 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 426193 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2868114 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001846 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000173 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001929 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.001630 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.002685 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.002961 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.002816 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.025641 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.032258 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.028571 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.457644 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.477824 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.467321 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.010454 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011090 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.010772 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.026227 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.028827 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.027557 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001846 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000173 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.010454 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.182777 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001929 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011090 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.178666 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.060978 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001846 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000173 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.010454 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.182777 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001929 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011090 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.178666 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.060978 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 86023.809524 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 83500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 84656.716418 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 85305.343511 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 29250 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 29250 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29250 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 80500 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 82000 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 81250 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 85191.303856 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84351.449382 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 84779.532075 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 83038.586598 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 83644.236150 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 83349.963942 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 86642.214095 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89499.083802 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 88171.232429 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86023.809524 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 83038.586598 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 85323.947737 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 84656.716418 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 83644.236150 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 84904.840701 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 84906.073988 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86023.809524 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 83038.586598 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 85323.947737 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 84656.716418 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 83644.236150 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 84904.840701 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 84906.073988 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 95512 # number of writebacks -system.l2c.writebacks::total 95512 # number of writebacks -system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 7 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.data 76 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.data 65 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 141 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 76 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 65 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 152 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 76 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 65 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 152 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 63 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 67 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 131 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 4 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 70652 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 67960 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 138612 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 10126 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10718 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 20844 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 7033 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 8121 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 15154 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 63 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 10126 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 77685 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 67 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 10718 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 76081 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 174741 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 63 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 10126 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 77685 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 67 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 10718 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 76081 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 174741 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 667 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16331 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 14796 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 31794 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15929 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11655 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 667 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 32260 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 26451 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 59378 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4789500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 73500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5002000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 9865000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 77000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 77000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 154000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 70500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 72000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 142500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5312416000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5052924500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 10365340500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 739815498 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 789414500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1529229998 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 540351500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 646874000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 1187225500 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 4789500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 73500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 739815498 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 5852767500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 5002000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 789414500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 5699798500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 13091660998 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 4789500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 73500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 739815498 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 5852767500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 5002000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 789414500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 5699798500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 13091660998 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 43103498 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3097371000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2817626000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5958100498 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 43103498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3097371000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2817626000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5958100498 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001846 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000173 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001929 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.001630 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002685 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.002961 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.002816 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.025641 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.032258 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.028571 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.457644 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.477824 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.467321 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010447 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011086 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010766 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.025946 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.028599 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.027303 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001846 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000173 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010447 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.182599 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001929 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011086 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.178513 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.060925 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001846 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000173 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010447 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.182599 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001929 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011086 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.178513 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.060925 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76023.809524 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74656.716418 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 75305.343511 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19250 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19250 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19250 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 70500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 72000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71250 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75191.303856 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74351.449382 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 74779.532075 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 73060.981434 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 73653.153573 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73365.476780 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76830.868762 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79654.476050 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78344.034578 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76023.809524 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73060.981434 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75339.737401 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74656.716418 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73653.153573 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74917.502399 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 74920.373570 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76023.809524 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73060.981434 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75339.737401 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74656.716418 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73653.153573 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74917.502399 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 74920.373570 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189662.053763 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 190431.603136 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 187397.008807 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64622.935532 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96012.740236 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 106522.475521 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 100341.885850 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 352067 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 145781 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 504 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 31794 # Transaction distribution -system.membus.trans_dist::ReadResp 68171 # Transaction distribution -system.membus.trans_dist::WriteReq 27584 # Transaction distribution -system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 131672 # Transaction distribution -system.membus.trans_dist::CleanEvict 9189 # Transaction distribution -system.membus.trans_dist::UpgradeReq 129 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 138492 # Transaction distribution -system.membus.trans_dist::ReadExResp 138492 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 36378 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 24 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464721 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 572293 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645161 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 768 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17331868 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17495901 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19811101 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 522 # Total snoops (count) -system.membus.snoopTraffic 33280 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 270575 # Request fanout histogram -system.membus.snoop_fanout::mean 0.019532 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.138387 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 265290 98.05% 98.05% # Request fanout histogram -system.membus.snoop_fanout::1 5285 1.95% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 270575 # Request fanout histogram -system.membus.reqLayer0.occupancy 95437500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 18156 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1702998 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 917027178 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1009264500 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1323623 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks -system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks -system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks -system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks -system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks -system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks -system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks -system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5615366 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2827339 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 47526 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 188 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 188 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2804492191000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 149674 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2641289 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 797750 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1935798 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 157804 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2842 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 70 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2911 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296610 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296610 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1936426 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 555260 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4760 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5809649 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2677780 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 34247 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 164021 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8685697 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 247843584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99641501 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 46076 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 275476 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 347806637 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 147441 # Total snoops (count) -system.toL2Bus.snoopTraffic 6294736 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 3081797 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.027693 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.164091 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2996454 97.23% 97.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 85343 2.77% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3081797 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5533506883 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 309877 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2907318131 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1324202245 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 22762929 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 95604083 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed - ----------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal deleted file mode 100644 index ad91d76dd..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal +++ /dev/null @@ -1,208 +0,0 @@ -Booting Linux on physical CPU 0x0
-
Initializing cgroup subsys cpuset
-
Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014
-
Kernel was built at commit id ''
-
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
-
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
-
Machine model: V2P-CA15
-
bootconsole [earlycon0] enabled
-
Memory policy: Data cache writealloc
-
kdebugv2m: Following are test values to confirm proper working
-
kdebugv2m: Ranges 42000000 0
-
kdebugv2m: Regs 30000000 1000000
-
kdebugv2m: Virtual-Reg f0000000
-
kdebugv2m: pci node addr_cells 3
-
kdebugv2m: pci node size_cells 2
-
kdebugv2m: motherboard addr_cells 2
-
On node 0 totalpages: 65536
-
free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000
-
Normal zone: 512 pages used for memmap
-
Normal zone: 0 pages reserved
-
Normal zone: 65536 pages, LIFO batch:15
-
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
-
PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768
-
pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096
-
pcpu-alloc: [0] 0
-
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
-
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-
PID hash table entries: 1024 (order: 0, 4096 bytes)
-
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
-
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
-
Memory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem)
-
Virtual kernel memory layout:
-
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
-
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
-
vmalloc : 0x90800000 - 0xff000000 (1768 MB)
-
lowmem : 0x80000000 - 0x90000000 ( 256 MB)
-
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
-
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
-
.text : 0x80008000 - 0x806a942c (6790 kB)
-
.init : 0x806aa000 - 0x806f3d80 ( 296 kB)
-
.data : 0x806f4000 - 0x80732754 ( 250 kB)
-
.bss : 0x80732754 - 0x8078e9d8 ( 369 kB)
-
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
-
Preemptible hierarchical RCU implementation.
-
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
-
NR_IRQS:16 nr_irqs:16 16
-
Architected cp15 timer(s) running at 25.16MHz (phys).
-
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
-
Switching to timer-based delay loop
-
Console: colour dummy device 80x30
-
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-
pid_max: default: 32768 minimum: 301
-
Mount-cache hash table entries: 512
-
CPU: Testing write buffer coherency: ok
-
CPU0: update cpu_power 1024
-
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
-
Setting up static identity map for 0x804fee68 - 0x804fee9c
-
Brought up 1 CPUs
-
SMP: Total of 1 processors activated.
-
CPU: All CPU(s) started in SVC mode.
-
VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
-
NET: Registered protocol family 16
-
DMA: preallocated 256 KiB pool for atomic coherent allocations
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0
-
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0
-
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
-
hw-breakpoint: CPU 0 failed to disable vector catch
-
Serial: AMBA PL011 UART driver
-
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-
console [ttyAMA0] enabled
-console [ttyAMA0] enabled
-
bootconsole [earlycon0] disabled
-bootconsole [earlycon0] disabled
-
PCI host bridge to bus 0000:00
-pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]
-pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
-pci_bus 0000:00: root bus resource [bus 00-ff]
-pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-PCI: bus0: Fast back to back transfers disabled
-pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]
-pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]
-pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]
-pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]
-pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]
-pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]
-pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
-PCI map irq: slot 0, pin 1, devslot 0, irq: 68
-PCI map irq: slot 1, pin 2, devslot 1, irq: 69
-bio: create slab <bio-0> at 0
-vgaarb: loaded
-SCSI subsystem initialized
-libata version 3.00 loaded.
-usbcore: registered new interface driver usbfs
-usbcore: registered new interface driver hub
-usbcore: registered new device driver usb
-pps_core: LinuxPPS API ver. 1 registered
-pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-PTP clock support registered
-Advanced Linux Sound Architecture Driver Initialized.
-Switched to clocksource arch_sys_counter
-NET: Registered protocol family 2
-TCP established hash table entries: 2048 (order: 1, 8192 bytes)
-TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
-TCP: Hash tables configured (established 2048 bind 2048)
-TCP: reno registered
-UDP hash table entries: 256 (order: 1, 8192 bytes)
-UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-NET: Registered protocol family 1
-RPC: Registered named UNIX socket transport module.
-RPC: Registered udp transport module.
-RPC: Registered tcp transport module.
-RPC: Registered tcp NFSv4.1 backchannel transport module.
-PCI: CLS 64 bytes, default 64
-hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available
-jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
-msgmni has been set to 460
-io scheduler noop registered (default)
-brd: module loaded
-loop: module loaded
-ata_piix 0000:00:01.0: version 2.13
-PCI: enabling device 0000:00:01.0 (0040 -> 0041)
-scsi0 : ata_piix
-scsi1 : ata_piix
-ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69
-ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69
-e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
-e100: Copyright(c) 1999-2006 Intel Corporation
-e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-e1000: Copyright (c) 1999-2006 Intel Corporation.
-PCI: enabling device 0000:00:00.0 (0040 -> 0042)
-ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-ata1.00: 1048320 sectors, multi 0: LBA
-ata1.00: configured for UDMA/33
-scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
-sd 0:0:0:0: [sda] Write Protect is off
-sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
- sda: sda1
-sd 0:0:0:0: Attached scsi generic sg0 type 0
-sd 0:0:0:0: [sda] Attached SCSI disk
-e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-e1000e: Copyright(c) 1999 - 2013 Intel Corporation.
-igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-igb: Copyright (c) 2007-2013 Intel Corporation.
-igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k
-igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
-ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k
-ixgbe: Copyright (c) 1999-2013 Intel Corporation.
-ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k
-ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.
-ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI
-ixgb: Copyright (c) 1999-2008 Intel Corporation.
-smsc911x: Driver version 2008-10-21
-smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2
-nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller
-nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1
-nxp-isp1760 1b000000.usb: Scratch test failed.
-nxp-isp1760 1b000000.usb: can't setup: -19
-nxp-isp1760 1b000000.usb: USB bus 1 deregistered
-usbcore: registered new interface driver usb-storage
-mousedev: PS/2 mouse device common for all mice
-rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0
-usbcore: registered new interface driver usbhid
-usbhid: USB HID core driver
-ashmem: initialized
-logger: created 256K log 'log_main'
-logger: created 256K log 'log_events'
-logger: created 256K log 'log_radio'
-logger: created 256K log 'log_system'
-oprofile: using timer interrupt.
-TCP: cubic registered
-NET: Registered protocol family 10
-NET: Registered protocol family 17
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)
-ALSA device list:
- No soundcards found.
- -input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2
-VFS: Mounted root (ext2 filesystem) on device 8:1.
-Freeing unused kernel memory: 292K (806aa000 - 806f3000)
-
init started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)
-
starting pid 673, tty '': '/etc/rc.d/rc.local'
-warning: can't open /etc/mtab: No such file or directory
-Thu Jan 1 00:00:02 UTC 2009
-S: devpts
-Thu Jan 1 00:00:02 UTC 2009
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/EMPTY b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/EMPTY new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/EMPTY diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini deleted file mode 100644 index 1432fcef9..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/config.ini +++ /dev/null @@ -1,2137 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxArmSystem -children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain -atags_addr=134217728 -boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb -early_kernel_symbols=false -enable_context_switch_stats_dump=false -eventq_index=0 -exit_on_work_items=false -flags_addr=469827632 -gic_cpu_addr=738205696 -have_large_asid_64=false -have_lpae=true -have_security=false -have_virtualization=false -highest_el_is_64=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 -kernel_addr_check=true -load_addr_mask=268435455 -load_offset=2147483648 -machine_type=VExpress_EMM64 -mem_mode=timing -mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.nvmem system.realview.vram -mmap_using_noreserve=false -multi_proc=true -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -panic_on_oops=true -panic_on_panic=true -phys_addr_range_64=40 -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -reset_addr_64=0 -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[1] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.cf0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.cf0.image - -[system.cf0.image] -type=CowDiskImage -children=child -child=system.cf0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.cf0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img -read_only=true - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred checker dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer -LFSTSize=1024 -LQEntries=16 -LSQCheckLoads=true -LSQDepCheckShift=0 -SQEntries=16 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=system.cpu.checker -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=2 -decodeWidth=3 -default_p_state=UNDEFINED -dispatchWidth=6 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=16 -fetchQueueSize=32 -fetchToDecodeDelay=3 -fetchTrapLatency=1 -fetchWidth=3 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=32 -numPhysCCRegs=640 -numPhysFloatRegs=192 -numPhysIntRegs=128 -numROBEntries=40 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=1 -renameToROBDelay=1 -renameWidth=3 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BiModeBP -BTBEntries=2048 -BTBTagSize=18 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -numThreads=1 -useIndirect=true - -[system.cpu.checker] -type=O3Checker -children=dstage2_mmu dtb isa istage2_mmu itb tracer -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.checker.dstage2_mmu -dtb=system.cpu.checker.dtb -eventq_index=0 -exitOnError=false -function_trace=false -function_trace_start=0 -interrupts= -isa=system.cpu.checker.isa -istage2_mmu=system.cpu.checker.istage2_mmu -itb=system.cpu.checker.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.checker.tracer -updateOnError=true -warnOnlyOnLoadError=true -workload= - -[system.cpu.checker.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.checker.dtb - -[system.cpu.checker.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker - -[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.checker.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.checker.dtb.walker - -[system.cpu.checker.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[5] - -[system.cpu.checker.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.checker.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.checker.itb - -[system.cpu.checker.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker - -[system.cpu.checker.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.checker.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.checker.itb.walker - -[system.cpu.checker.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[4] - -[system.cpu.checker.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 opList2 -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList1.opList2] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList - -[system.cpu.fuPool.FUList2.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList - -[system.cpu.fuPool.FUList3.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 - -[system.cpu.fuPool.FUList4.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=9 -pipelined=true - -[system.cpu.fuPool.FUList4.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList4.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=9 -pipelined=true - -[system.cpu.fuPool.FUList4.opList20] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList21] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList22] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList23] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=9 -pipelined=false - -[system.cpu.fuPool.FUList4.opList24] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=33 -pipelined=false - -[system.cpu.fuPool.FUList4.opList25] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[2] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=2147483648:2415919103 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[3] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.membus] -type=CoherentXBar -children=badaddr_responder -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access=warn -pio=system.membus.default - -[system.physmem] -type=DRAMCtrl -IDD0=0.075000 -IDD02=0.000000 -IDD2N=0.050000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.000000 -IDD2P12=0.000000 -IDD3N=0.057000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.000000 -IDD3P12=0.000000 -IDD4R=0.187000 -IDD4R2=0.000000 -IDD4W=0.165000 -IDD4W2=0.000000 -IDD5=0.220000 -IDD52=0.000000 -IDD6=0.000000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=2147483648:2415919103 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=0 -tXPDLL=0 -tXS=0 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[5] - -[system.realview] -type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.realview.aaci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470024192 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[18] - -[system.realview.cf_ctrl] -type=IdeController -BAR0=471465984 -BAR0LegacyIO=true -BAR0Size=256 -BAR1=471466240 -BAR1LegacyIO=true -BAR1Size=4096 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=1 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=2 -default_p_state=UNDEFINED -disks= -eventq_index=0 -host=system.realview.pci_host -io_shift=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=2 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[2] -pio=system.iobus.master[9] - -[system.realview.clcd] -type=Pl111 -amba_id=1315089 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=46 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471793664 -pio_latency=10000 -pixel_clock=41667 -power_model=Null -system=system -vnc=system.vncserver -dma=system.iobus.slave[1] -pio=system.iobus.master[5] - -[system.realview.dcc] -type=SubSystem -children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys -eventq_index=0 -thermal_domain=Null - -[system.realview.dcc.osc_cpu] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_ddr] -type=RealViewOsc -dcc=0 -device=8 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_hsbm] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_pxl] -type=RealViewOsc -dcc=0 -device=5 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_smb] -type=RealViewOsc -dcc=0 -device=6 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_sys] -type=RealViewOsc -dcc=0 -device=7 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.energy_ctrl] -type=EnergyCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dvfs_handler=system.dvfs_handler -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470286336 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[22] - -[system.realview.ethernet] -type=IGbE -BAR0=0 -BAR0LegacyIO=false -BAR0Size=131072 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=0 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=4213 -ExpansionROM=0 -HeaderType=0 -InterruptLine=1 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=255 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=0 -SubClassCode=0 -SubsystemID=4104 -SubsystemVendorID=32902 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -eventq_index=0 -fetch_comp_delay=10000 -fetch_delay=10000 -hardware_address=00:90:00:00:00:01 -host=system.realview.pci_host -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -phy_epid=896 -phy_pid=680 -pio_latency=30000 -power_model=Null -rx_desc_cache_size=64 -rx_fifo_size=393216 -rx_write_delay=0 -system=system -tx_desc_cache_size=64 -tx_fifo_size=393216 -tx_read_delay=0 -wb_comp_delay=10000 -wb_delay=10000 -dma=system.iobus.slave[4] -pio=system.iobus.master[24] - -[system.realview.generic_timer] -type=GenericTimer -eventq_index=0 -gic=system.realview.gic -int_phys=29 -int_virt=27 -system=system - -[system.realview.gic] -type=Pl390 -clk_domain=system.clk_domain -cpu_addr=738205696 -cpu_pio_delay=10000 -default_p_state=UNDEFINED -dist_addr=738201600 -dist_pio_delay=10000 -eventq_index=0 -gem5_extensions=true -int_latency=10000 -it_lines=128 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -platform=system.realview -power_model=Null -system=system -pio=system.membus.master[2] - -[system.realview.hdlcd] -type=HDLcd -amba_id=1314816 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=117 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=721420288 -pio_latency=10000 -pixel_buffer_size=2048 -pixel_chunk=32 -power_model=Null -pxl_clk=system.realview.dcc.osc_pxl -system=system -vnc=system.vncserver -workaround_dma_line_count=true -workaround_swap_rb=true -dma=system.membus.slave[0] -pio=system.iobus.master[6] - -[system.realview.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=2 -InterruptPin=2 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.cf0 -eventq_index=0 -host=system.realview.pci_host -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[3] -pio=system.iobus.master[23] - -[system.realview.kmi0] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=44 -is_mouse=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470155264 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[7] - -[system.realview.kmi1] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=45 -is_mouse=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470220800 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[8] - -[system.realview.l2x0_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=739246080 -pio_latency=100000 -pio_size=4095 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.realview.lan_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=436207616 -pio_latency=100000 -pio_size=65535 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.realview.local_cpu_timer] -type=CpuLocalTimer -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num_timer=29 -int_num_watchdog=30 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=738721792 -pio_latency=100000 -power_model=Null -system=system -pio=system.membus.master[4] - -[system.realview.mcc] -type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl -eventq_index=0 -thermal_domain=Null - -[system.realview.mcc.osc_clcd] -type=RealViewOsc -dcc=0 -device=1 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_mcc] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_peripheral] -type=RealViewOsc -dcc=0 -device=2 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_system_bus] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.temp_crtl] -type=RealViewTemperatureSensor -dcc=0 -device=0 -eventq_index=0 -parent=system.realview.realview_io -position=0 -site=0 -system=system - -[system.realview.mmc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470089728 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.realview.nvmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:67108863 -port=system.membus.master[1] - -[system.realview.pci_host] -type=GenericPciHost -clk_domain=system.clk_domain -conf_base=805306368 -conf_device_bits=12 -conf_size=268435456 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=0 -pci_pio_base=788529152 -platform=system.realview -power_model=Null -system=system -pio=system.iobus.master[2] - -[system.realview.realview_io] -type=RealViewCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -idreg=35979264 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469827584 -pio_latency=100000 -power_model=Null -proc_id0=335544320 -proc_id1=335544320 -system=system -pio=system.iobus.master[1] - -[system.realview.rtc] -type=PL031 -amba_id=3412017 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=36 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471269376 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[10] - -[system.realview.sp810_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469893120 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[16] - -[system.realview.timer0] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=34 -int_num1=34 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470876160 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[3] - -[system.realview.timer1] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=35 -int_num1=35 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470941696 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[4] - -[system.realview.uart] -type=Pl011 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -end_on_eot=false -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=37 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470351872 -pio_latency=100000 -platform=system.realview -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[0] - -[system.realview.uart1_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470417408 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[13] - -[system.realview.uart2_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470482944 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[14] - -[system.realview.uart3_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470548480 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[15] - -[system.realview.usb_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=452984832 -pio_latency=100000 -pio_size=131071 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.realview.vgic] -type=VGic -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -hv_addr=738213888 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_delay=10000 -platform=system.realview -power_model=Null -ppint=25 -system=system -vcpu_addr=738222080 -pio=system.membus.master[3] - -[system.realview.vram] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=402653184:436207615 -port=system.iobus.master[11] - -[system.realview.watchdog_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470745088 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[17] - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.vncserver] -type=VncServer -eventq_index=0 -frame_capture=false -number=0 -port=5900 - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr deleted file mode 100755 index c04cf2403..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simerr +++ /dev/null @@ -1,92 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match. -warn: Sockets disabled, not accepting vnc client connections -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Existing EnergyCtrl, but no enabled DVFSHandler found. -warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 -warn: Tried to read RealView I/O at offset 0x60 that doesn't exist -warn: Tried to read RealView I/O at offset 0x48 that doesn't exist -warn: 12465253480500: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d780, checker: 0 -warn: 12465256875500: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0 -warn: Tried to read RealView I/O at offset 0x8 that doesn't exist -warn: Tried to read RealView I/O at offset 0x48 that doesn't exist -warn: 13848743916500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13856080320500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13856660917500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13856932644000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13891365050500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13914492463500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13915494038500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13915724569500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13929415957500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 13975739128500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0 -warn: 14218303751000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14218304352000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14218304616500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14218304863000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14218305076500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14234303193500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14242116775500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14242117552500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14242117792000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14242117998500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14247408751000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14247409260500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14247409494500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14247409734000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14247409931000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14253842696500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14253843672000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14253843878500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14263637803000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14263638037500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14263638268000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14263638474500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14274868668500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14274868899000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14274869105500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14284684734000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14284685479000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14284685709500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14300304682500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14300304916500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14300305146500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14305416988000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14305417218000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14305417424500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14312475874500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14312476114000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14322624432500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14322624672000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14337182893000: Instruction results do not match! (Values may not actually be integers) Inst: 0x48, checker: 0x49 -warn: 14386098021000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14444180838500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14444181087000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14568925614000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14569017181500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14569017437000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93 -warn: 14569020030500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14569020349000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14569750354000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14569750626000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42 -warn: 14569750836000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14569821557500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 -warn: 14569821767500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14569822044000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1 -warn: 14569822614500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14569822870000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91 -warn: 14569823093500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14569823382500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14569823891500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14569824954500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14569825452500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14569825754500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3 -warn: 14618889380500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 -warn: 14618889688000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14618889945500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14618890194000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14618890463500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41 -warn: 14618890702500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout deleted file mode 100755 index 2667f123a..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/simout +++ /dev/null @@ -1,18 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:43 -gem5 executing on e108600-lin, pid 12252 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-o3-checker - -Selected 64-bit ARM architecture, updating default disk image... -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 -info: Using bootloader at address 0x10 -info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51327142820000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt deleted file mode 100644 index 12a2f6bdf..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ /dev/null @@ -1,2104 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 51.558015 # Number of seconds simulated -sim_ticks 51558014828000 # Number of ticks simulated -final_tick 51558014828000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110619 # Simulator instruction rate (inst/s) -host_op_rate 130023 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5152408080 # Simulator tick rate (ticks/s) -host_mem_usage 695916 # Number of bytes of host memory used -host_seconds 10006.59 # Real time elapsed on the host -sim_insts 1106923026 # Number of instructions simulated -sim_ops 1301083589 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 667968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 559488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 6546400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112650248 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 429376 # Number of bytes read from this memory -system.physmem.bytes_read::total 120853480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 6546400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6546400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 140957120 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 140977700 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 10437 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 8742 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 118240 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1760173 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6709 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1904301 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2202455 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2205028 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 12956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 10852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 126972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2184922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2344029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 126972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 126972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2733952 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2734351 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2733952 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 10852 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 126972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2185321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8328 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5078380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1904301 # Number of read requests accepted -system.physmem.writeReqs 2205028 # Number of write requests accepted -system.physmem.readBursts 1904301 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2205028 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 121838144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 37120 # Total number of bytes read from write queue -system.physmem.bytesWritten 140976896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 120853480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 140977700 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 580 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 114327 # Per bank write bursts -system.physmem.perBankRdBursts::1 123692 # Per bank write bursts -system.physmem.perBankRdBursts::2 118245 # Per bank write bursts -system.physmem.perBankRdBursts::3 117057 # Per bank write bursts -system.physmem.perBankRdBursts::4 115229 # Per bank write bursts -system.physmem.perBankRdBursts::5 125268 # Per bank write bursts -system.physmem.perBankRdBursts::6 115683 # Per bank write bursts -system.physmem.perBankRdBursts::7 119593 # Per bank write bursts -system.physmem.perBankRdBursts::8 115543 # Per bank write bursts -system.physmem.perBankRdBursts::9 144676 # Per bank write bursts -system.physmem.perBankRdBursts::10 112600 # Per bank write bursts -system.physmem.perBankRdBursts::11 120122 # Per bank write bursts -system.physmem.perBankRdBursts::12 113965 # Per bank write bursts -system.physmem.perBankRdBursts::13 118266 # Per bank write bursts -system.physmem.perBankRdBursts::14 113146 # Per bank write bursts -system.physmem.perBankRdBursts::15 116309 # Per bank write bursts -system.physmem.perBankWrBursts::0 135142 # Per bank write bursts -system.physmem.perBankWrBursts::1 141643 # Per bank write bursts -system.physmem.perBankWrBursts::2 136917 # Per bank write bursts -system.physmem.perBankWrBursts::3 137997 # Per bank write bursts -system.physmem.perBankWrBursts::4 135684 # Per bank write bursts -system.physmem.perBankWrBursts::5 143871 # Per bank write bursts -system.physmem.perBankWrBursts::6 135153 # Per bank write bursts -system.physmem.perBankWrBursts::7 138864 # Per bank write bursts -system.physmem.perBankWrBursts::8 135935 # Per bank write bursts -system.physmem.perBankWrBursts::9 142790 # Per bank write bursts -system.physmem.perBankWrBursts::10 134947 # Per bank write bursts -system.physmem.perBankWrBursts::11 140191 # Per bank write bursts -system.physmem.perBankWrBursts::12 134987 # Per bank write bursts -system.physmem.perBankWrBursts::13 137976 # Per bank write bursts -system.physmem.perBankWrBursts::14 134592 # Per bank write bursts -system.physmem.perBankWrBursts::15 136075 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 125 # Number of times write queue was full causing retry -system.physmem.totGap 51558013451500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 13 # Read request sizes (log2) -system.physmem.readPktSize::4 21272 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1883016 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 1 # Write request sizes (log2) -system.physmem.writePktSize::3 2572 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2202455 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1140639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 689076 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 609 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1348 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 38490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 83702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 117171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 125843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 130438 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 133004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 138248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 140822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 137539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 142466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 143357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 133954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 146358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 136372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 127299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 130102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 120942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 365 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 933198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 281.628105 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 167.352526 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 309.404332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 371108 39.77% 39.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 233427 25.01% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88383 9.47% 74.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 51664 5.54% 79.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 37413 4.01% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 26389 2.83% 86.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 21045 2.26% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 17945 1.92% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 85824 9.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 933198 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 116229 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.379053 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 52.340079 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 116223 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 116229 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 116228 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.951965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.478061 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 17.079115 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 111884 96.26% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 1770 1.52% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 397 0.34% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 626 0.54% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 488 0.42% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 246 0.21% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 362 0.31% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 120 0.10% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 64 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 59 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 51 0.04% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 11 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 17 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 10 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 37 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 24 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 14 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 5 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-623 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::624-639 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::752-767 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::768-783 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::976-991 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 116228 # Writes before turning the bus around for reads -system.physmem.totQLat 42075497859 # Total ticks spent queuing -system.physmem.totMemAccLat 77770266609 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9518605000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22101.71 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40851.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.34 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.73 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.62 # Average write queue length when enqueuing -system.physmem.readRowHits 1533744 # Number of row buffer hits during reads -system.physmem.writeRowHits 1639539 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.43 # Row buffer hit rate for writes -system.physmem.avgGap 12546577.18 # Average gap between requests -system.physmem.pageHitRate 77.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3530119320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1926156375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7402894200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 7162084800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1313077918185 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29782982922000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34483600624320 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.831109 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49545451951432 # Time in different power states -system.physmem_0.memoryStateTime::REF 1721635240000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 290927248568 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3524804640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1923256500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7446082800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 7111728720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3367518529440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1314046606680 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29782133195250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34483704204030 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.833118 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49544014933949 # Time in different power states -system.physmem_1.memoryStateTime::REF 1721635240000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 292364518051 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 290131106 # Number of BP lookups -system.cpu.branchPred.condPredicted 198353835 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 13679752 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 208494226 # Number of BTB lookups -system.cpu.branchPred.BTBHits 130534623 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.608268 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 37597374 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 402079 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 8125236 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 6045082 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2080154 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 800698 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.checker.dtb.walker.walks 345580 # Table walker walks requested -system.cpu.checker.dtb.walker.walksLong 345580 # Table walker walks initiated with long descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 345580 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 345580 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 345580 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walksPending::samples 1638693500 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::0 1638693500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::total 1638693500 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 271194 90.38% 90.38% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::2M 28860 9.62% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 300054 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 345580 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 345580 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 300054 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 300054 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 645634 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.inst_hits 0 # ITB inst hits -system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 205011929 # DTB read hits -system.cpu.checker.dtb.read_misses 252661 # DTB read misses -system.cpu.checker.dtb.write_hits 188856696 # DTB write hits -system.cpu.checker.dtb.write_misses 92919 # DTB write misses -system.cpu.checker.dtb.flush_tlb 22 # Number of times complete TLB was flushed -system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 126550 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 84606 # Number of entries that have been flushed from TLB -system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 10719 # Number of TLB faults due to prefetch -system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 24551 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 205264590 # DTB read accesses -system.cpu.checker.dtb.write_accesses 188949615 # DTB write accesses -system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 393868625 # DTB hits -system.cpu.checker.dtb.misses 345580 # DTB misses -system.cpu.checker.dtb.accesses 394214205 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.checker.itb.walker.walks 130718 # Table walker walks requested -system.cpu.checker.itb.walker.walksLong 130718 # Table walker walks initiated with long descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 130718 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 130718 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 130718 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walksPending::samples 1638085000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::0 1638085000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::total 1638085000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 116451 98.90% 98.90% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::2M 1296 1.10% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 117747 # Table walker page sizes translated -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 130718 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 130718 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 117747 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 117747 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 248465 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 1107463254 # ITB inst hits -system.cpu.checker.itb.inst_misses 130718 # ITB inst misses -system.cpu.checker.itb.read_hits 0 # DTB read hits -system.cpu.checker.itb.read_misses 0 # DTB read misses -system.cpu.checker.itb.write_hits 0 # DTB write hits -system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 22 # Number of times complete TLB was flushed -system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 126550 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 56882 # Number of entries that have been flushed from TLB -system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.itb.read_accesses 0 # DTB read accesses -system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 1107593972 # ITB inst accesses -system.cpu.checker.itb.hits 1107463254 # DTB hits -system.cpu.checker.itb.misses 130718 # DTB misses -system.cpu.checker.itb.accesses 1107593972 # DTB accesses -system.cpu.checker.pwrStateResidencyTicks::ON 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.checker.numCycles 1301797660 # number of cpu cycles simulated -system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 1423094 # Table walker walks requested -system.cpu.dtb.walker.walksLong 1423094 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 30587 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 273540 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 668841 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 754253 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2502.822660 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 16371.142747 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 747574 99.11% 99.11% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 4739 0.63% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 871 0.12% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 433 0.06% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 327 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 64 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 235 0.03% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 754253 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 795185 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 25800.017606 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 21033.129871 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 18337.040091 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 776690 97.67% 97.67% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 15553 1.96% 99.63% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1840 0.23% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 558 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 320 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 153 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 44 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 795185 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 1040609044948 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.747004 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.517062 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 1036648437448 99.62% 99.62% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 2501393000 0.24% 99.86% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 710900000 0.07% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 286069000 0.03% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 201203000 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 121106500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 48982500 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 87667500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 3189000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::18-19 41500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::20-21 55500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 1040609044948 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 273541 89.94% 89.94% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 30587 10.06% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 304128 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 1423094 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 1423094 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 304128 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 304128 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1727222 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 217549636 # DTB read hits -system.cpu.dtb.read_misses 1002675 # DTB read misses -system.cpu.dtb.write_hits 192429615 # DTB write hits -system.cpu.dtb.write_misses 420419 # DTB write misses -system.cpu.dtb.flush_tlb 22 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 126550 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 84838 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 110 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 16158 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 86326 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 218552311 # DTB read accesses -system.cpu.dtb.write_accesses 192850034 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 409979251 # DTB hits -system.cpu.dtb.misses 1423094 # DTB misses -system.cpu.dtb.accesses 411402345 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 177767 # Table walker walks requested -system.cpu.itb.walker.walksLong 177767 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1532 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 128663 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 19966 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 157801 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1393.783943 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 9971.559116 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 155663 98.65% 98.65% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 1042 0.66% 99.31% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 672 0.43% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 333 0.21% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 30 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 26 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 157801 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 150161 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28501.914612 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 23015.105793 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 23459.229673 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 144112 95.97% 95.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 5152 3.43% 99.40% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 475 0.32% 99.72% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 255 0.17% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 99 0.07% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 55 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 150161 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 911756921068 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.951043 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.216068 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 44693483152 4.90% 4.90% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 867007398416 95.09% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 55571500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 466000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 911756921068 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 128663 98.82% 98.82% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1532 1.18% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 130195 # Table walker page sizes translated -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 177767 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 177767 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 130195 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 130195 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 307962 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 462600046 # ITB inst hits -system.cpu.itb.inst_misses 177767 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 22 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 126550 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 2406 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 58185 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 440221 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 462777813 # ITB inst accesses -system.cpu.itb.hits 462600046 # DTB hits -system.cpu.itb.misses 177767 # DTB misses -system.cpu.itb.accesses 462777813 # DTB accesses -system.cpu.numPwrStateTransitions 34262 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 17131 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 2947433272.666569 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 58590018858.186401 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7811 45.60% 45.60% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9284 54.19% 99.79% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::9.5e+11-1e+12 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988780762168 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 17131 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1065535433949 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50492479394051 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2131080190 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 789533395 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1294232501 # Number of instructions fetch has processed -system.cpu.fetch.Branches 290131106 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 174177079 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1253396684 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29442936 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 4521296 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 28032 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11449142 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1221670 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 685 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 462141962 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6901101 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 52491 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 2074872372 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.731015 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.142682 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1354023092 65.26% 65.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 279633538 13.48% 78.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 86518146 4.17% 82.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 354697596 17.09% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 2074872372 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.136143 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.607313 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 615922756 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 835719938 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 532432043 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 80077312 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10720323 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 41258933 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4059445 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1407827153 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 33008479 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10720323 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 679035070 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 79966926 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 552687037 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 549603762 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 202859254 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1383638167 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 8109162 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7348509 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 966276 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1094350 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 119568064 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 22725 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1333397174 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2200696007 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1641425227 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1433031 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1254726296 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 78670875 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 43643507 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39180007 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 166278031 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 222554034 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 196867138 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12635283 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11114743 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1330840515 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 43953891 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1360477402 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4212137 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 73710813 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41934009 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 368799 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 2074872372 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.655692 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.916068 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 1226409345 59.11% 59.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 451307165 21.75% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 291780533 14.06% 94.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 95920964 4.62% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9425546 0.45% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 28819 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 2074872372 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 73561900 34.17% 34.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 90692 0.04% 34.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26794 0.01% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 484 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 57931960 26.91% 61.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 83660297 38.86% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 939889673 69.09% 69.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2936613 0.22% 69.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 130878 0.01% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 372 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 112363 0.01% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 222587367 16.36% 85.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 194820033 14.32% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1360477402 # Type of FU issued -system.cpu.iq.rate 0.638398 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215272127 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.158233 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5012901497 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1447776434 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1338315649 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2409942 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 914537 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 885572 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1574233532 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1515940 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5717597 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 17343387 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24124 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 187368 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7978529 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3596780 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1680866 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10720323 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12040487 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4569260 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1375079942 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 222554034 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 196867138 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 38644291 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 177419 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4207009 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 187368 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4048268 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6103351 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10151619 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1346834094 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 217554512 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 12249639 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 285536 # number of nop insts executed -system.cpu.iew.exec_refs 409993947 # number of memory reference insts executed -system.cpu.iew.exec_branches 255680172 # Number of branches executed -system.cpu.iew.exec_stores 192439435 # Number of stores executed -system.cpu.iew.exec_rate 0.631996 # Inst execution rate -system.cpu.iew.wb_sent 1340240150 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1339201221 # cumulative count of insts written-back -system.cpu.iew.wb_producers 574929948 # num instructions producing a value -system.cpu.iew.wb_consumers 943031378 # num instructions consuming a value -system.cpu.iew.wb_rate 0.628414 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.609662 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 62850702 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 43585092 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9678607 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 2060674246 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.631387 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.270689 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1383412740 67.13% 67.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 394991247 19.17% 86.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 150433823 7.30% 93.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 44582057 2.16% 95.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 36156812 1.75% 97.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 18175173 0.88% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10964042 0.53% 98.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5475656 0.27% 99.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 16482696 0.80% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 2060674246 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1106923026 # Number of instructions committed -system.cpu.commit.committedOps 1301083589 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 394099255 # Number of memory references committed -system.cpu.commit.loads 205210646 # Number of loads committed -system.cpu.commit.membars 9122435 # Number of memory barriers committed -system.cpu.commit.branches 247396089 # Number of branches committed -system.cpu.commit.fp_insts 873905 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1189215854 # Number of committed integer instructions. -system.cpu.commit.function_calls 30973786 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 904226715 69.50% 69.50% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2546778 0.20% 69.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 104952 0.01% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 105847 0.01% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 205210646 15.77% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 188888609 14.52% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1301083589 # Class of committed instruction -system.cpu.commit.bw_lim_events 16482696 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3398675710 # The number of ROB reads -system.cpu.rob.rob_writes 2741957858 # The number of ROB writes -system.cpu.timesIdled 9058128 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 56207818 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 100984949503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 1106923026 # Number of Instructions Simulated -system.cpu.committedOps 1301083589 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.925229 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.925229 # CPI: Total CPI of All Threads -system.cpu.ipc 0.519419 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.519419 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1599627417 # number of integer regfile reads -system.cpu.int_regfile_writes 942915982 # number of integer regfile writes -system.cpu.fp_regfile_reads 1421408 # number of floating regfile reads -system.cpu.fp_regfile_writes 762380 # number of floating regfile writes -system.cpu.cc_regfile_reads 312164706 # number of cc regfile reads -system.cpu.cc_regfile_writes 313034766 # number of cc regfile writes -system.cpu.misc_regfile_reads 3414318389 # number of misc regfile reads -system.cpu.misc_regfile_writes 44468731 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 13662519 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.983620 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 361203380 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 13663031 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 26.436548 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1659288500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.983620 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1599492126 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1599492126 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 186946586 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 186946586 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 163344159 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 163344159 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 463383 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 463383 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 333988 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 333988 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4793284 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4793284 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5278947 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5278947 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 350624733 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 350624733 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 351088116 # number of overall hits -system.cpu.dcache.overall_hits::total 351088116 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12788061 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12788061 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 18648516 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 18648516 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 2041461 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 2041461 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1270506 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1270506 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 548369 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 548369 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 9 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 32707083 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 32707083 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 34748544 # number of overall misses -system.cpu.dcache.overall_misses::total 34748544 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 205827865000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 205827865000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1003464059741 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1003464059741 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 29968640002 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 29968640002 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 8933513500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 8933513500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 300500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 300500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1239260564743 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1239260564743 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1239260564743 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1239260564743 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 199734647 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 199734647 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 181992675 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 181992675 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2504844 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2504844 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1604494 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1604494 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5341653 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5341653 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5278956 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5278956 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 383331816 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 383331816 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 385836660 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 385836660 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.064025 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.064025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.102468 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.102468 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.815005 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.815005 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791842 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.791842 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.102659 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.102659 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.085323 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.085323 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.090060 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.090060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16095.314606 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16095.314606 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53809.325082 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53809.325082 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 23587.956296 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 23587.956296 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16291.062223 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16291.062223 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 33388.888889 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 33388.888889 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37889.669487 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37889.669487 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35663.668807 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35663.668807 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24419954 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2093623 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.663969 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 10319802 # number of writebacks -system.cpu.dcache.writebacks::total 10319802 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5736139 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5736139 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15576096 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15576096 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 6849 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 6849 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 265006 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 265006 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 21319084 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 21319084 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 21319084 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 21319084 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7051922 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7051922 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3072420 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3072420 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 2034687 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 2034687 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1263657 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1263657 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 283363 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 283363 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 9 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 9 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 11387999 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 11387999 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 13422686 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 13422686 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 33692 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 67395 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 110827450000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 110827450000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 147154305213 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 147154305213 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 32559356000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 32559356000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 28426038502 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 28426038502 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 4117736500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 4117736500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 291500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 291500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286407793715 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 286407793715 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 318967149715 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 318967149715 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6225596500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6225596500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6225596500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6225596500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035306 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035306 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016882 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016882 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.812301 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.812301 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787574 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787574 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.053048 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.053048 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029708 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029708 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034789 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15715.921135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15715.921135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47895.243884 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47895.243884 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16002.144802 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16002.144802 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 22495.058787 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 22495.058787 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14531.666096 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14531.666096 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 32388.888889 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 32388.888889 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25149.966532 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25149.966532 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23763.287744 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23763.287744 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184779.665796 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184779.665796 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92374.753320 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92374.753320 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 16891256 # number of replacements -system.cpu.icache.tags.tagsinuse 511.956016 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 444441322 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 16891768 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26.311119 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 13164566500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.956016 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999914 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999914 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 112 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 479012658 # Number of tag accesses -system.cpu.icache.tags.data_accesses 479012658 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 444441322 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 444441322 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 444441322 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 444441322 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 444441322 # number of overall hits -system.cpu.icache.overall_hits::total 444441322 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17679342 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17679342 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17679342 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17679342 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17679342 # number of overall misses -system.cpu.icache.overall_misses::total 17679342 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 234300237389 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 234300237389 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 234300237389 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 234300237389 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 234300237389 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 234300237389 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 462120664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 462120664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 462120664 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 462120664 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 462120664 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 462120664 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.038257 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.038257 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.038257 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.038257 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.038257 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.038257 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13252.769101 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13252.769101 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13252.769101 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13252.769101 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13252.769101 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13252.769101 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 16371 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1212 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 13.507426 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 16891256 # number of writebacks -system.cpu.icache.writebacks::total 16891256 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 787348 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 787348 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 787348 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 787348 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 787348 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 787348 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16891994 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16891994 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16891994 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16891994 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16891994 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16891994 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 210691534398 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 210691534398 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 210691534398 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 210691534398 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 210691534398 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 210691534398 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1610722500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1610722500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1610722500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 1610722500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.036553 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.036553 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.036553 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.036553 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12472.863440 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12472.863440 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12472.863440 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12472.863440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12472.863440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12472.863440 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75642.082277 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75642.082277 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75642.082277 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75642.082277 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 2372905 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65457.290128 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 58959202 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2435994 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.203345 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2520974000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9397.889077 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 196.572797 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 228.214718 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6628.882550 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 49005.730985 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.143400 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.002999 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.003482 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101149 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.747768 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998799 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 222 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62867 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 222 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 376 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5588 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55850 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959274 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 505094110 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 505094110 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1274032 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 302472 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1576504 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 10319802 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 10319802 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 16888637 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 16888637 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 38922 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 38922 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 5 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1712070 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1712070 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16794801 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 16794801 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 8925946 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 8925946 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 673558 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 673558 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 1274032 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 302472 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 16794801 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 10638016 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 29009321 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 1274032 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 302472 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 16794801 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 10638016 # number of overall hits -system.cpu.l2cache.overall_hits::total 29009321 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 10437 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 8742 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 19179 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4078 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4078 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1333352 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1333352 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 96984 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 96984 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 428025 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 428025 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 590099 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 590099 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 10437 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 8742 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 96984 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1761377 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1877540 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 10437 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 8742 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 96984 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1761377 # number of overall misses -system.cpu.l2cache.overall_misses::total 1877540 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 936727000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 780169000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1716896000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 73235500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 73235500 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 191000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 191000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123861773500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 123861773500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8301693500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 8301693500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38723437000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 38723437000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 483000 # number of InvalidateReq miss cycles -system.cpu.l2cache.InvalidateReq_miss_latency::total 483000 # number of InvalidateReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 936727000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 780169000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 8301693500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 162585210500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 172603800000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 936727000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 780169000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 8301693500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 162585210500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 172603800000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1284469 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 311214 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1595683 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 10319802 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 10319802 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 16888637 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 16888637 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43000 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 43000 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 9 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3045422 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3045422 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 16891785 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 16891785 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 9353971 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 9353971 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1263657 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1263657 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1284469 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 311214 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 16891785 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 12399393 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 30886861 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1284469 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 311214 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 16891785 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 12399393 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 30886861 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.008126 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.028090 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.012019 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.094837 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.094837 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.444444 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.444444 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437822 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.437822 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005741 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005741 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045759 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045759 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.466977 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.466977 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.008126 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.028090 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005741 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.142053 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060788 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.008126 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.028090 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005741 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.142053 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060788 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89750.598831 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89243.765729 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 89519.578706 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17958.680726 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17958.680726 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 47750 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 47750 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92895.029595 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92895.029595 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85598.588427 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85598.588427 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90470.035629 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90470.035629 # average ReadSharedReq miss latency -system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 0.818507 # average InvalidateReq miss latency -system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 0.818507 # average InvalidateReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89750.598831 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89243.765729 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85598.588427 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92305.741758 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 91930.824377 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89750.598831 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89243.765729 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85598.588427 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92305.741758 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 91930.824377 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 2095825 # number of writebacks -system.cpu.l2cache.writebacks::total 2095825 # number of writebacks -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10437 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 8742 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 19179 # number of ReadReq MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 3 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 3 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4078 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4078 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1333352 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1333352 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 96984 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 96984 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 428004 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 428004 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 590099 # number of InvalidateReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::total 590099 # number of InvalidateReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10437 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 8742 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 96984 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1761356 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1877519 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10437 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 8742 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 96984 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1761356 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1877519 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33692 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54986 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33703 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33703 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67395 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88689 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 832356501 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 692749000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1525105501 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 77850000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 77850000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 181500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 181500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110528159195 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110528159195 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7331831049 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7331831049 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 34442081593 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 34442081593 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 12207320002 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 12207320002 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 832356501 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 692749000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7331831049 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 144970240788 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 153827177338 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 832356501 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 692749000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7331831049 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 144970240788 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 153827177338 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1344547500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5804287500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7148835000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1344547500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5804287500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 7148835000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012019 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.094837 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.094837 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.444444 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.444444 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437822 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437822 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005741 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045756 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045756 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.466977 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.466977 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060787 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.008126 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.028090 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005741 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.142052 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060787 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 79519.552688 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19090.240314 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19090.240314 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 45375 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 45375 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82894.958867 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82894.958867 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75598.356935 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75598.356935 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80471.401186 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80471.401186 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20686.901693 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20686.901693 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79750.551020 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 79243.765729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75598.356935 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82306.041929 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81931.089559 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172274.946575 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130011.912123 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63142.082277 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86123.414200 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 80605.655718 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 62084255 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 31529230 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3455 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 2242102 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 28488845 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 12415627 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16891256 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3619797 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43003 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43012 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3045422 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3045422 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 16891994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 9356331 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1295806 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1263657 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50717623 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 41210208 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 777423 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3005376 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 95710630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2162455328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1454268658 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2489712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 10275752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3629489450 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2999840 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 138927432 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 35281285 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.026592 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.160887 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 34343098 97.34% 97.34% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 938187 2.66% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 35281285 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 58941748976 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1470395 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25369728010 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 19308156079 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 466604190 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1721722349 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40300 # Transaction distribution -system.iobus.trans_dist::ReadResp 40300 # Transaction distribution -system.iobus.trans_dist::WriteReq 136571 # Transaction distribution -system.iobus.trans_dist::WriteResp 136571 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353742 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492184 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41887500 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 337000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25106500 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568968673 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147718000 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) -system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115465 # number of replacements -system.iocache.tags.tagsinuse 10.450543 # Cycle average of tags in use -system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13091229344000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 5.877255 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 4.573288 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.367328 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.285830 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653159 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039668 # Number of tag accesses -system.iocache.tags.data_accesses 1039668 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses -system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses -system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115479 # number of demand (read+write) misses -system.iocache.demand_misses::total 115519 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115479 # number of overall misses -system.iocache.overall_misses::total 115519 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1629675592 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1634761592 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12811525081 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12811525081 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14441200673 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14446637673 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14441200673 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14446637673 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115479 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115519 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115479 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115519 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 184875.279864 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 184677.089019 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120111.050411 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120111.050411 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125058.541651 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125054.777691 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125058.541651 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32070 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3415 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.390922 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115479 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115519 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115479 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115519 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1188925592 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1192161592 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7471582182 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7471582182 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8660507774 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8663944774 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 8660507774 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8663944774 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134875.279864 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 134677.089019 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70047.834152 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70047.834152 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74996.386997 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75000.171175 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 5074419 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2524015 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3002 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 54986 # Transaction distribution -system.membus.trans_dist::ReadResp 608005 # Transaction distribution -system.membus.trans_dist::WriteReq 33703 # Transaction distribution -system.membus.trans_dist::WriteResp 33703 # Transaction distribution -system.membus.trans_dist::WritebackDirty 2202455 # Transaction distribution -system.membus.trans_dist::CleanEvict 284620 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4643 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 1332798 # Transaction distribution -system.membus.trans_dist::ReadExResp 1332798 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 553019 # Transaction distribution -system.membus.trans_dist::InvalidateReq 696755 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6767333 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 6896995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237693 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237693 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7134688 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 254577484 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 254747538 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7253696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 262001234 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2809 # Total snoops (count) -system.membus.snoopTraffic 179264 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2675908 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013150 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.113918 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2640719 98.68% 98.68% # Request fanout histogram -system.membus.snoop_fanout::1 35189 1.32% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2675908 # Request fanout histogram -system.membus.reqLayer0.occupancy 103923000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 32500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5620000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 14223305475 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 10050154677 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44814659 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks -system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks -system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks -system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks -system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks -system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 13 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks -system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks -system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51558014828000 # Cumulative time (in ticks) in various power states -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 17131 # number of quiesce instructions executed - ----------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/system.terminal deleted file mode 100644 index 3c0eb417b..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/system.terminal +++ /dev/null @@ -1,183 +0,0 @@ -[ 0.000000] Initializing cgroup subsys cpu
-[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
-[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
-[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
-[ 0.000000] Memory limited to 256MB
-[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
-[ 0.000000] On node 0 totalpages: 65536
-[ 0.000000] DMA zone: 896 pages used for memmap
-[ 0.000000] DMA zone: 0 pages reserved
-[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
-[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
-[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
-[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
-[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
-[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
-[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
-[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
-[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
-[ 0.000000] Virtual kernel memory layout:
-[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
-[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
-[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
-[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
-[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
-[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
-[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
-[ 0.000000] Preemptible hierarchical RCU implementation.
-[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
-[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
-[ 0.000000] NR_IRQS:64 nr_irqs:64 0
-[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
-[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000021] Console: colour dummy device 80x25
-[ 0.000024] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000025] pid_max: default: 32768 minimum: 301
-[ 0.000036] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000037] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000147] hw perfevents: no hardware support available
-[ 1.060066] CPU1: failed to come online
-[ 2.080127] CPU2: failed to come online
-[ 3.100188] CPU3: failed to come online
-[ 3.100191] Brought up 1 CPUs
-[ 3.100192] SMP: Total of 1 processors activated.
-[ 3.100247] devtmpfs: initialized
-[ 3.100685] atomic64_test: passed
-[ 3.100727] regulator-dummy: no parameters
-[ 3.101141] NET: Registered protocol family 16
-[ 3.101262] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.101271] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.101633] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.101638] Serial: AMBA PL011 UART driver
-[ 3.101817] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.101850] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.102416] console [ttyAMA0] enabled
-[ 3.102495] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.102526] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.102557] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.102587] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130494] 3V3: 3300 mV
-[ 3.130534] vgaarb: loaded
-[ 3.130580] SCSI subsystem initialized
-[ 3.130617] libata version 3.00 loaded.
-[ 3.130659] usbcore: registered new interface driver usbfs
-[ 3.130676] usbcore: registered new interface driver hub
-[ 3.130707] usbcore: registered new device driver usb
-[ 3.130732] pps_core: LinuxPPS API ver. 1 registered
-[ 3.130740] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.130759] PTP clock support registered
-[ 3.130873] Switched to clocksource arch_sys_counter
-[ 3.131846] NET: Registered protocol family 2
-[ 3.131920] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.131938] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.131960] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.131975] TCP: reno registered
-[ 3.131982] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.131997] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.132036] NET: Registered protocol family 1
-[ 3.132085] RPC: Registered named UNIX socket transport module.
-[ 3.132095] RPC: Registered udp transport module.
-[ 3.132103] RPC: Registered tcp transport module.
-[ 3.132111] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.132123] PCI: CLS 0 bytes, default 64
-[ 3.132266] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.132363] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.133901] fuse init (API version 7.23)
-[ 3.133978] msgmni has been set to 469
-[ 3.136097] io scheduler noop registered
-[ 3.136147] io scheduler cfq registered (default)
-[ 3.136516] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.136528] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.136540] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.136552] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.136562] pci_bus 0000:00: scanning bus
-[ 3.136573] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.136586] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.136600] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.136636] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.136647] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.136658] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.136669] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.136679] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.136690] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.136701] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.136734] pci_bus 0000:00: fixups for bus
-[ 3.136742] pci_bus 0000:00: bus scan returning with max=00
-[ 3.136755] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.136774] pci 0000:00:00.0: fixup irq: got 33
-[ 3.136782] pci 0000:00:00.0: assigning IRQ 33
-[ 3.136793] pci 0000:00:01.0: fixup irq: got 34
-[ 3.136801] pci 0000:00:01.0: assigning IRQ 34
-[ 3.136812] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.136825] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.136838] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.136851] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.136862] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.136874] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.136885] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.136896] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.137335] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.137572] ata_piix 0000:00:01.0: version 2.13
-[ 3.137583] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.137604] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.137866] scsi0 : ata_piix
-[ 3.137956] scsi1 : ata_piix
-[ 3.137984] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.137996] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.138093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.138105] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.138120] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.138131] e1000 0000:00:00.0: enabling bus mastering
-[ 3.290899] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.290909] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.290935] ata1.00: configured for UDMA/33
-[ 3.290984] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.291086] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.291109] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.291146] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.291155] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.291174] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.291287] sda: sda1
-[ 3.291392] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.411166] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.411179] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.411199] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.411209] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.411229] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.411240] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.411304] usbcore: registered new interface driver usb-storage
-[ 3.411354] mousedev: PS/2 mouse device common for all mice
-[ 3.411491] usbcore: registered new interface driver usbhid
-[ 3.411501] usbhid: USB HID core driver
-[ 3.411531] TCP: cubic registered
-[ 3.411538] NET: Registered protocol family 17
- -[ 3.411900] devtmpfs: mounted
-[ 3.411930] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
- - -[ 3.450359] udevd[607]: starting version 182
-Starting Bootlog daemon: bootlogd.
-[ 3.543431] random: dd urandom read with 19 bits of entropy available
-Populating dev cache
-net.ipv4.conf.default.rp_filter = 1
-net.ipv4.conf.all.rp_filter = 1
-hwclock: can't open '/dev/misc/rtc': No such file or directory
-Mon Jan 27 08:00:00 UTC 2014
-hwclock: can't open '/dev/misc/rtc': No such file or directory
-
INIT: Entering runlevel: 5
-Configuring network interfaces... [ 3.671103] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
-udhcpc (v1.21.1) started
-Sending discover...
-Sending discover...
-Sending discover...
-No lease, forking to background
-done.
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6
-rpcbind: cannot create socket for tcp6
-done.
-rpcbind: cannot get uid of '': Success
-creating NFS state directory: done
-starting statd: done
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/EMPTY b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/EMPTY new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/EMPTY diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini deleted file mode 100644 index d912070c6..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.ini +++ /dev/null @@ -1,1559 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxArmSystem -children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain -atags_addr=134217728 -boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb -early_kernel_symbols=false -enable_context_switch_stats_dump=false -eventq_index=0 -exit_on_work_items=false -flags_addr=469827632 -gic_cpu_addr=738205696 -have_large_asid_64=false -have_lpae=true -have_security=false -have_virtualization=false -highest_el_is_64=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 -kernel_addr_check=true -load_addr_mask=268435455 -load_offset=2147483648 -machine_type=VExpress_EMM64 -mem_mode=atomic -mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.nvmem system.realview.vram -mmap_using_noreserve=false -multi_proc=true -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -panic_on_oops=true -panic_on_panic=true -phys_addr_range_64=40 -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -reset_addr_64=0 -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[1] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.cf0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.cf0.image - -[system.cf0.image] -type=CowDiskImage -children=child -child=system.cf0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.cf0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img -read_only=true - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[2] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=2147483648:2415919103 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[3] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.membus] -type=CoherentXBar -children=badaddr_responder -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access=warn -pio=system.membus.default - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=2147483648:2415919103 -port=system.membus.master[5] - -[system.realview] -type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.realview.aaci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470024192 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[18] - -[system.realview.cf_ctrl] -type=IdeController -BAR0=471465984 -BAR0LegacyIO=true -BAR0Size=256 -BAR1=471466240 -BAR1LegacyIO=true -BAR1Size=4096 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=1 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=2 -default_p_state=UNDEFINED -disks= -eventq_index=0 -host=system.realview.pci_host -io_shift=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=2 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[2] -pio=system.iobus.master[9] - -[system.realview.clcd] -type=Pl111 -amba_id=1315089 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=46 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471793664 -pio_latency=10000 -pixel_clock=41667 -power_model=Null -system=system -vnc=system.vncserver -dma=system.iobus.slave[1] -pio=system.iobus.master[5] - -[system.realview.dcc] -type=SubSystem -children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys -eventq_index=0 -thermal_domain=Null - -[system.realview.dcc.osc_cpu] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_ddr] -type=RealViewOsc -dcc=0 -device=8 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_hsbm] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_pxl] -type=RealViewOsc -dcc=0 -device=5 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_smb] -type=RealViewOsc -dcc=0 -device=6 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_sys] -type=RealViewOsc -dcc=0 -device=7 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.energy_ctrl] -type=EnergyCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dvfs_handler=system.dvfs_handler -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470286336 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[22] - -[system.realview.ethernet] -type=IGbE -BAR0=0 -BAR0LegacyIO=false -BAR0Size=131072 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=0 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=4213 -ExpansionROM=0 -HeaderType=0 -InterruptLine=1 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=255 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=0 -SubClassCode=0 -SubsystemID=4104 -SubsystemVendorID=32902 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -eventq_index=0 -fetch_comp_delay=10000 -fetch_delay=10000 -hardware_address=00:90:00:00:00:01 -host=system.realview.pci_host -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -phy_epid=896 -phy_pid=680 -pio_latency=30000 -power_model=Null -rx_desc_cache_size=64 -rx_fifo_size=393216 -rx_write_delay=0 -system=system -tx_desc_cache_size=64 -tx_fifo_size=393216 -tx_read_delay=0 -wb_comp_delay=10000 -wb_delay=10000 -dma=system.iobus.slave[4] -pio=system.iobus.master[24] - -[system.realview.generic_timer] -type=GenericTimer -eventq_index=0 -gic=system.realview.gic -int_phys=29 -int_virt=27 -system=system - -[system.realview.gic] -type=Pl390 -clk_domain=system.clk_domain -cpu_addr=738205696 -cpu_pio_delay=10000 -default_p_state=UNDEFINED -dist_addr=738201600 -dist_pio_delay=10000 -eventq_index=0 -gem5_extensions=true -int_latency=10000 -it_lines=128 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -platform=system.realview -power_model=Null -system=system -pio=system.membus.master[2] - -[system.realview.hdlcd] -type=HDLcd -amba_id=1314816 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=117 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=721420288 -pio_latency=10000 -pixel_buffer_size=2048 -pixel_chunk=32 -power_model=Null -pxl_clk=system.realview.dcc.osc_pxl -system=system -vnc=system.vncserver -workaround_dma_line_count=true -workaround_swap_rb=true -dma=system.membus.slave[0] -pio=system.iobus.master[6] - -[system.realview.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=2 -InterruptPin=2 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.cf0 -eventq_index=0 -host=system.realview.pci_host -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[3] -pio=system.iobus.master[23] - -[system.realview.kmi0] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=44 -is_mouse=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470155264 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[7] - -[system.realview.kmi1] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=45 -is_mouse=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470220800 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[8] - -[system.realview.l2x0_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=739246080 -pio_latency=100000 -pio_size=4095 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.realview.lan_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=436207616 -pio_latency=100000 -pio_size=65535 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.realview.local_cpu_timer] -type=CpuLocalTimer -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num_timer=29 -int_num_watchdog=30 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=738721792 -pio_latency=100000 -power_model=Null -system=system -pio=system.membus.master[4] - -[system.realview.mcc] -type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl -eventq_index=0 -thermal_domain=Null - -[system.realview.mcc.osc_clcd] -type=RealViewOsc -dcc=0 -device=1 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_mcc] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_peripheral] -type=RealViewOsc -dcc=0 -device=2 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_system_bus] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.temp_crtl] -type=RealViewTemperatureSensor -dcc=0 -device=0 -eventq_index=0 -parent=system.realview.realview_io -position=0 -site=0 -system=system - -[system.realview.mmc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470089728 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.realview.nvmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:67108863 -port=system.membus.master[1] - -[system.realview.pci_host] -type=GenericPciHost -clk_domain=system.clk_domain -conf_base=805306368 -conf_device_bits=12 -conf_size=268435456 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=0 -pci_pio_base=788529152 -platform=system.realview -power_model=Null -system=system -pio=system.iobus.master[2] - -[system.realview.realview_io] -type=RealViewCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -idreg=35979264 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469827584 -pio_latency=100000 -power_model=Null -proc_id0=335544320 -proc_id1=335544320 -system=system -pio=system.iobus.master[1] - -[system.realview.rtc] -type=PL031 -amba_id=3412017 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=36 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471269376 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[10] - -[system.realview.sp810_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469893120 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[16] - -[system.realview.timer0] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=34 -int_num1=34 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470876160 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[3] - -[system.realview.timer1] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=35 -int_num1=35 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470941696 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[4] - -[system.realview.uart] -type=Pl011 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -end_on_eot=false -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=37 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470351872 -pio_latency=100000 -platform=system.realview -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[0] - -[system.realview.uart1_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470417408 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[13] - -[system.realview.uart2_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470482944 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[14] - -[system.realview.uart3_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470548480 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[15] - -[system.realview.usb_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=452984832 -pio_latency=100000 -pio_size=131071 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.realview.vgic] -type=VGic -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -hv_addr=738213888 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_delay=10000 -platform=system.realview -power_model=Null -ppint=25 -system=system -vcpu_addr=738222080 -pio=system.membus.master[3] - -[system.realview.vram] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=402653184:436207615 -port=system.iobus.master[11] - -[system.realview.watchdog_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470745088 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[17] - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.vncserver] -type=VncServer -eventq_index=0 -frame_capture=false -number=0 -port=5900 - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json deleted file mode 100644 index bad452cca..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/config.json +++ /dev/null @@ -1,2038 +0,0 @@ -{ - "name": null, - "sim_quantum": 0, - "system": { - "have_virtualization": false, - "mmap_using_noreserve": false, - "kernel_addr_check": true, - "highest_el_is_64": false, - "kernel": "/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821", - "iobus": { - "forward_latency": 1, - "slave": { - "peer": [ - "system.bridge.master", - "system.realview.clcd.dma", - "system.realview.cf_ctrl.dma", - "system.realview.ide.dma", - "system.realview.ethernet.dma" - ], - "role": "SLAVE" - }, - "name": "iobus", - "p_state_clk_gate_min": 1000, - "p_state_clk_gate_bins": 20, - "cxx_class": "NoncoherentXBar", - "clk_domain": "system.clk_domain", - "power_model": null, - "width": 16, - "eventq_index": 0, - "master": { - "peer": [ - "system.realview.uart.pio", - "system.realview.realview_io.pio", - "system.realview.pci_host.pio", - "system.realview.timer0.pio", - "system.realview.timer1.pio", - "system.realview.clcd.pio", - "system.realview.hdlcd.pio", - "system.realview.kmi0.pio", - "system.realview.kmi1.pio", - "system.realview.cf_ctrl.pio", - "system.realview.rtc.pio", - "system.realview.vram.port", - "system.realview.l2x0_fake.pio", - "system.realview.uart1_fake.pio", - "system.realview.uart2_fake.pio", - "system.realview.uart3_fake.pio", - "system.realview.sp810_fake.pio", - "system.realview.watchdog_fake.pio", - "system.realview.aaci_fake.pio", - "system.realview.lan_fake.pio", - "system.realview.usb_fake.pio", - "system.realview.mmc_fake.pio", - "system.realview.energy_ctrl.pio", - "system.realview.ide.pio", - "system.realview.ethernet.pio", - "system.iocache.cpu_side" - ], - "role": "MASTER" - }, - "response_latency": 2, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.iobus", - "type": "NoncoherentXBar", - "use_default_range": false, - "frontend_latency": 2 - }, - "symbolfile": "", - "readfile": "/work/curdun01/gem5-external.hg/tests/testing/../halt.sh", - "have_large_asid_64": false, - "thermal_model": null, - "phys_addr_range_64": 40, - "work_begin_exit_count": 0, - "have_lpae": true, - "cxx_class": "LinuxArmSystem", - "work_begin_cpu_id_exit": -1, - "load_offset": 2147483648, - "vncserver": { - "name": "vncserver", - "number": 0, - "frame_capture": false, - "eventq_index": 0, - "cxx_class": "VncServer", - "path": "system.vncserver", - "type": "VncServer", - "port": 5900 - }, - "multi_proc": true, - "bridge": { - "ranges": [ - "788529152:805306367", - "721420288:725614591", - "805306368:1073741823", - "1073741824:1610612735", - "402653184:469762047", - "469762048:536870911" - ], - "slave": { - "peer": "system.membus.master[0]", - "role": "SLAVE" - }, - "name": "bridge", - "p_state_clk_gate_min": 1000, - "p_state_clk_gate_bins": 20, - "cxx_class": "Bridge", - "req_size": 16, - "clk_domain": "system.clk_domain", - "power_model": null, - "delay": 50000, - "eventq_index": 0, - "master": { - "peer": "system.iobus.slave[0]", - "role": "MASTER" - }, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.bridge", - "resp_size": 16, - "type": "Bridge" - }, - "early_kernel_symbols": false, - "panic_on_oops": true, - "dtb_filename": "/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb", - "panic_on_panic": true, - "enable_context_switch_stats_dump": false, - "work_begin_ckpt_count": 0, - "clk_domain": { - "name": "clk_domain", - "clock": [ - 1000 - ], - "init_perf_level": 0, - "voltage_domain": "system.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "mem_ranges": [ - "2147483648:2415919103" - ], - "realview": { - "hdlcd": { - "pio": { - "peer": "system.iobus.master[6]", - "role": "SLAVE" - }, - "system": "system", - "cxx_class": "HDLcd", - "enable_capture": true, - "pio_addr": 721420288, - "pixel_chunk": 32, - "pio_latency": 10000, - "clk_domain": "system.clk_domain", - "int_num": 117, - "gic": "system.realview.gic", - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "eventq_index": 0, - "pxl_clk": "system.realview.dcc.osc_pxl", - "type": "HDLcd", - "vnc": "system.vncserver", - "p_state_clk_gate_min": 1000, - "power_model": null, - "workaround_dma_line_count": true, - "pixel_buffer_size": 2048, - "path": "system.realview.hdlcd", - "workaround_swap_rb": true, - "dma": { - "peer": "system.membus.slave[0]", - "role": "MASTER" - }, - "name": "hdlcd", - "p_state_clk_gate_bins": 20, - "amba_id": 1314816 - }, - "mmc_fake": { - "p_state_clk_gate_bins": 20, - "name": "mmc_fake", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[21]", - "role": "SLAVE" - }, - "amba_id": 0, - "ignore_access": false, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "cxx_class": "AmbaFake", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.mmc_fake", - "pio_addr": 470089728, - "type": "AmbaFake" - }, - "rtc": { - "p_state_clk_gate_min": 1000, - "p_state_clk_gate_bins": 20, - "name": "rtc", - "int_delay": 100000, - "pio": { - "peer": "system.iobus.master[10]", - "role": "SLAVE" - }, - "amba_id": 3412017, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "gic": "system.realview.gic", - "int_num": 36, - "eventq_index": 0, - "time": "Thu Jan 1 00:00:00 2009", - "cxx_class": "PL031", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.rtc", - "pio_addr": 471269376, - "type": "PL031" - }, - "watchdog_fake": { - "p_state_clk_gate_bins": 20, - "name": "watchdog_fake", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[17]", - "role": "SLAVE" - }, - "amba_id": 0, - "ignore_access": false, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "cxx_class": "AmbaFake", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.watchdog_fake", - "pio_addr": 470745088, - "type": "AmbaFake" - }, - "vgic": { - "system": "system", - "name": "vgic", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.membus.master[3]", - "role": "SLAVE" - }, - "p_state_clk_gate_bins": 20, - "cxx_class": "VGic", - "clk_domain": "system.clk_domain", - "power_model": null, - "hv_addr": 738213888, - "gic": "system.realview.gic", - "platform": "system.realview", - "vcpu_addr": 738222080, - "eventq_index": 0, - "ppint": 25, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.vgic", - "type": "VGic", - "pio_delay": 10000 - }, - "cxx_class": "RealView", - "uart3_fake": { - "p_state_clk_gate_bins": 20, - "name": "uart3_fake", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[15]", - "role": "SLAVE" - }, - "amba_id": 0, - "ignore_access": false, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "cxx_class": "AmbaFake", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.uart3_fake", - "pio_addr": 470548480, - "type": "AmbaFake" - }, - "realview_io": { - "proc_id1": 335544320, - "name": "realview_io", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[1]", - "role": "SLAVE" - }, - "p_state_clk_gate_bins": 20, - "cxx_class": "RealViewCtrl", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "proc_id0": 335544320, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.realview_io", - "idreg": 35979264, - "type": "RealViewCtrl", - "pio_addr": 469827584 - }, - "l2x0_fake": { - "pio": { - "peer": "system.iobus.master[12]", - "role": "SLAVE" - }, - "ret_data64": 18446744073709551615, - "fake_mem": false, - "clk_domain": "system.clk_domain", - "cxx_class": "IsaFake", - "pio_addr": 739246080, - "update_data": false, - "warn_access": "", - "pio_latency": 100000, - "system": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "type": "IsaFake", - "p_state_clk_gate_min": 1000, - "power_model": null, - "ret_data32": 4294967295, - "path": "system.realview.l2x0_fake", - "ret_data16": 65535, - "ret_data8": 255, - "name": "l2x0_fake", - "ret_bad_addr": false, - "pio_size": 4095, - "p_state_clk_gate_bins": 20 - }, - "uart1_fake": { - "p_state_clk_gate_bins": 20, - "name": "uart1_fake", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[13]", - "role": "SLAVE" - }, - "amba_id": 0, - "ignore_access": false, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "cxx_class": "AmbaFake", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.uart1_fake", - "pio_addr": 470417408, - "type": "AmbaFake" - }, - "usb_fake": { - "pio": { - "peer": "system.iobus.master[20]", - "role": "SLAVE" - }, - "ret_data64": 18446744073709551615, - "fake_mem": false, - "clk_domain": "system.clk_domain", - "cxx_class": "IsaFake", - "pio_addr": 452984832, - "update_data": false, - "warn_access": "", - "pio_latency": 100000, - "system": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "type": "IsaFake", - "p_state_clk_gate_min": 1000, - "power_model": null, - "ret_data32": 4294967295, - "path": "system.realview.usb_fake", - "ret_data16": 65535, - "ret_data8": 255, - "name": "usb_fake", - "ret_bad_addr": false, - "pio_size": 131071, - "p_state_clk_gate_bins": 20 - }, - "system": "system", - "local_cpu_timer": { - "int_num_watchdog": 30, - "name": "local_cpu_timer", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.membus.master[4]", - "role": "SLAVE" - }, - "p_state_clk_gate_bins": 20, - "cxx_class": "CpuLocalTimer", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "gic": "system.realview.gic", - "int_num_timer": 29, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.local_cpu_timer", - "pio_addr": 738721792, - "type": "CpuLocalTimer" - }, - "generic_timer": { - "int_virt": 27, - "name": "generic_timer", - "int_phys": 29, - "cxx_class": "GenericTimer", - "system": "system", - "eventq_index": 0, - "gic": "system.realview.gic", - "path": "system.realview.generic_timer", - "type": "GenericTimer" - }, - "gic": { - "gem5_extensions": true, - "it_lines": 128, - "dist_pio_delay": 10000, - "name": "gic", - "p_state_clk_gate_min": 1000, - "dist_addr": 738201600, - "p_state_clk_gate_bins": 20, - "cpu_pio_delay": 10000, - "default_p_state": "UNDEFINED", - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "cpu_addr": 738205696, - "platform": "system.realview", - "int_latency": 10000, - "eventq_index": 0, - "cxx_class": "Pl390", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.gic", - "pio": { - "peer": "system.membus.master[2]", - "role": "SLAVE" - }, - "type": "Pl390" - }, - "timer1": { - "p_state_clk_gate_bins": 20, - "name": "timer1", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[4]", - "role": "SLAVE" - }, - "amba_id": 1316868, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "clock0": 1000000, - "clock1": 1000000, - "gic": "system.realview.gic", - "eventq_index": 0, - "cxx_class": "Sp804", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.timer1", - "int_num0": 35, - "int_num1": 35, - "type": "Sp804", - "pio_addr": 470941696 - }, - "timer0": { - "p_state_clk_gate_bins": 20, - "name": "timer0", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[3]", - "role": "SLAVE" - }, - "amba_id": 1316868, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "clock0": 1000000, - "clock1": 1000000, - "gic": "system.realview.gic", - "eventq_index": 0, - "cxx_class": "Sp804", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.timer0", - "int_num0": 34, - "int_num1": 34, - "type": "Sp804", - "pio_addr": 470876160 - }, - "uart2_fake": { - "p_state_clk_gate_bins": 20, - "name": "uart2_fake", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[14]", - "role": "SLAVE" - }, - "amba_id": 0, - "ignore_access": false, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "cxx_class": "AmbaFake", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.uart2_fake", - "pio_addr": 470482944, - "type": "AmbaFake" - }, - "eventq_index": 0, - "energy_ctrl": { - "name": "energy_ctrl", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[22]", - "role": "SLAVE" - }, - "p_state_clk_gate_bins": 20, - "cxx_class": "EnergyCtrl", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.energy_ctrl", - "dvfs_handler": "system.dvfs_handler", - "type": "EnergyCtrl", - "pio_addr": 470286336 - }, - "type": "RealView", - "pci_host": { - "p_state_clk_gate_min": 1000, - "default_p_state": "UNDEFINED", - "conf_size": 268435456, - "name": "pci_host", - "conf_device_bits": 12, - "pio": { - "peer": "system.iobus.master[2]", - "role": "SLAVE" - }, - "p_state_clk_gate_bins": 20, - "conf_base": 805306368, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "pci_dma_base": 0, - "platform": "system.realview", - "eventq_index": 0, - "cxx_class": "GenericPciHost", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.pci_host", - "pci_pio_base": 788529152, - "type": "GenericPciHost", - "pci_mem_base": 0 - }, - "lan_fake": { - "pio": { - "peer": "system.iobus.master[19]", - "role": "SLAVE" - }, - "ret_data64": 18446744073709551615, - "fake_mem": false, - "clk_domain": "system.clk_domain", - "cxx_class": "IsaFake", - "pio_addr": 436207616, - "update_data": false, - "warn_access": "", - "pio_latency": 100000, - "system": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "type": "IsaFake", - "p_state_clk_gate_min": 1000, - "power_model": null, - "ret_data32": 4294967295, - "path": "system.realview.lan_fake", - "ret_data16": 65535, - "ret_data8": 255, - "name": "lan_fake", - "ret_bad_addr": false, - "pio_size": 65535, - "p_state_clk_gate_bins": 20 - }, - "aaci_fake": { - "p_state_clk_gate_bins": 20, - "name": "aaci_fake", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[18]", - "role": "SLAVE" - }, - "amba_id": 0, - "ignore_access": false, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "cxx_class": "AmbaFake", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.aaci_fake", - "pio_addr": 470024192, - "type": "AmbaFake" - }, - "mcc": { - "osc_peripheral": { - "position": 0, - "name": "osc_peripheral", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 0, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 2, - "path": "system.realview.mcc.osc_peripheral", - "freq": 41667, - "type": "RealViewOsc" - }, - "name": "mcc", - "osc_mcc": { - "position": 0, - "name": "osc_mcc", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 0, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 0, - "path": "system.realview.mcc.osc_mcc", - "freq": 20000, - "type": "RealViewOsc" - }, - "osc_clcd": { - "position": 0, - "name": "osc_clcd", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 0, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 1, - "path": "system.realview.mcc.osc_clcd", - "freq": 42105, - "type": "RealViewOsc" - }, - "thermal_domain": null, - "eventq_index": 0, - "cxx_class": "SubSystem", - "path": "system.realview.mcc", - "temp_crtl": { - "system": "system", - "position": 0, - "name": "temp_crtl", - "parent": "system.realview.realview_io", - "dcc": 0, - "site": 0, - "eventq_index": 0, - "cxx_class": "RealViewTemperatureSensor", - "device": 0, - "path": "system.realview.mcc.temp_crtl", - "type": "RealViewTemperatureSensor" - }, - "type": "SubSystem", - "osc_system_bus": { - "position": 0, - "name": "osc_system_bus", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 0, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 4, - "path": "system.realview.mcc.osc_system_bus", - "freq": 41667, - "type": "RealViewOsc" - } - }, - "dcc": { - "name": "dcc", - "osc_hsbm": { - "position": 0, - "name": "osc_hsbm", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 1, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 4, - "path": "system.realview.dcc.osc_hsbm", - "freq": 25000, - "type": "RealViewOsc" - }, - "thermal_domain": null, - "osc_sys": { - "position": 0, - "name": "osc_sys", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 1, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 7, - "path": "system.realview.dcc.osc_sys", - "freq": 16667, - "type": "RealViewOsc" - }, - "osc_ddr": { - "position": 0, - "name": "osc_ddr", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 1, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 8, - "path": "system.realview.dcc.osc_ddr", - "freq": 25000, - "type": "RealViewOsc" - }, - "eventq_index": 0, - "osc_cpu": { - "position": 0, - "name": "osc_cpu", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 1, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 0, - "path": "system.realview.dcc.osc_cpu", - "freq": 16667, - "type": "RealViewOsc" - }, - "cxx_class": "SubSystem", - "path": "system.realview.dcc", - "osc_smb": { - "position": 0, - "name": "osc_smb", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 1, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 6, - "path": "system.realview.dcc.osc_smb", - "freq": 20000, - "type": "RealViewOsc" - }, - "type": "SubSystem", - "osc_pxl": { - "position": 0, - "name": "osc_pxl", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 1, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 5, - "path": "system.realview.dcc.osc_pxl", - "freq": 42105, - "type": "RealViewOsc" - } - }, - "path": "system.realview", - "vram": { - "range": "402653184:436207615", - "latency": 30000, - "name": "vram", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.clk_domain", - "power_model": null, - "latency_var": 0, - "bandwidth": "73.000000", - "conf_table_reported": false, - "cxx_class": "SimpleMemory", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.vram", - "null": false, - "type": "SimpleMemory", - "port": { - "peer": "system.iobus.master[11]", - "role": "SLAVE" - }, - "in_addr_map": true - }, - "nvmem": { - "range": "0:67108863", - "latency": 30000, - "name": "nvmem", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.clk_domain", - "power_model": null, - "latency_var": 0, - "bandwidth": "73.000000", - "conf_table_reported": true, - "cxx_class": "SimpleMemory", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.nvmem", - "null": false, - "type": "SimpleMemory", - "port": { - "peer": "system.membus.master[1]", - "role": "SLAVE" - }, - "in_addr_map": true - }, - "clcd": { - "pio": { - "peer": "system.iobus.master[5]", - "role": "SLAVE" - }, - "system": "system", - "cxx_class": "Pl111", - "enable_capture": true, - "pio_addr": 471793664, - "pio_latency": 10000, - "clk_domain": "system.clk_domain", - "int_num": 46, - "gic": "system.realview.gic", - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "eventq_index": 0, - "type": "Pl111", - "vnc": "system.vncserver", - "p_state_clk_gate_min": 1000, - "power_model": null, - "path": "system.realview.clcd", - "dma": { - "peer": "system.iobus.slave[1]", - "role": "MASTER" - }, - "name": "clcd", - "p_state_clk_gate_bins": 20, - "pixel_clock": 41667, - "amba_id": 1315089 - }, - "name": "realview", - "uart": { - "p_state_clk_gate_min": 1000, - "terminal": "system.terminal", - "pio": { - "peer": "system.iobus.master[0]", - "role": "SLAVE" - }, - "name": "uart", - "int_delay": 100000, - "platform": "system.realview", - "p_state_clk_gate_bins": 20, - "cxx_class": "Pl011", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "gic": "system.realview.gic", - "int_num": 37, - "eventq_index": 0, - "end_on_eot": false, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.uart", - "pio_addr": 470351872, - "type": "Pl011" - }, - "intrctrl": "system.intrctrl", - "kmi1": { - "p_state_clk_gate_min": 1000, - "p_state_clk_gate_bins": 20, - "vnc": "system.vncserver", - "name": "kmi1", - "int_delay": 1000000, - "pio": { - "peer": "system.iobus.master[8]", - "role": "SLAVE" - }, - "amba_id": 1314896, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "gic": "system.realview.gic", - "int_num": 45, - "eventq_index": 0, - "is_mouse": true, - "cxx_class": "Pl050", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.kmi1", - "pio_addr": 470220800, - "type": "Pl050" - }, - "kmi0": { - "p_state_clk_gate_min": 1000, - "p_state_clk_gate_bins": 20, - "vnc": "system.vncserver", - "name": "kmi0", - "int_delay": 1000000, - "pio": { - "peer": "system.iobus.master[7]", - "role": "SLAVE" - }, - "amba_id": 1314896, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "gic": "system.realview.gic", - "int_num": 44, - "eventq_index": 0, - "is_mouse": false, - "cxx_class": "Pl050", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.kmi0", - "pio_addr": 470155264, - "type": "Pl050" - }, - "cf_ctrl": { - "PMCAPNextCapability": 0, - "InterruptPin": 1, - "HeaderType": 0, - "VendorID": 32902, - "MSIXMsgCtrl": 0, - "MSIXCAPNextCapability": 0, - "PXCAPLinkCtrl": 0, - "Revision": 0, - "LegacyIOBase": 0, - "pio_latency": 30000, - "PXCAPLinkCap": 0, - "CapabilityPtr": 0, - "MSIXCAPBaseOffset": 0, - "PXCAPDevCapabilities": 0, - "MSIXCAPCapId": 0, - "BAR3Size": 4, - "power_model": null, - "PXCAPCapabilities": 0, - "SubsystemID": 0, - "PXCAPCapId": 0, - "BAR4": 1, - "BAR1": 471466240, - "BAR0": 471465984, - "BAR3": 1, - "BAR2": 1, - "BAR5": 1, - "PXCAPDevStatus": 0, - "disks": [], - "BAR2Size": 8, - "MSICAPNextCapability": 0, - "ExpansionROM": 0, - "MSICAPMsgCtrl": 0, - "BAR5Size": 0, - "CardbusCIS": 0, - "MSIXPbaOffset": 0, - "MSICAPBaseOffset": 0, - "MaximumLatency": 0, - "BAR2LegacyIO": false, - "LatencyTimer": 0, - "BAR4LegacyIO": false, - "p_state_clk_gate_max": 1000000000000, - "PXCAPLinkStatus": 0, - "PXCAPDevCap2": 0, - "p_state_clk_gate_min": 1000, - "PXCAPDevCtrl": 0, - "MSICAPMaskBits": 0, - "host": "system.realview.pci_host", - "Command": 1, - "SubClassCode": 1, - "pci_func": 0, - "BAR5LegacyIO": false, - "MSICAPMsgData": 0, - "BIST": 0, - "PXCAPDevCtrl2": 0, - "pci_bus": 2, - "InterruptLine": 31, - "MSICAPMsgAddr": 0, - "BAR3LegacyIO": false, - "BAR4Size": 16, - "path": "system.realview.cf_ctrl", - "MinimumGrant": 0, - "Status": 640, - "BAR0Size": 256, - "system": "system", - "name": "cf_ctrl", - "PXCAPNextCapability": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "type": "IdeController", - "ctrl_offset": 2, - "PXCAPBaseOffset": 0, - "DeviceID": 28945, - "io_shift": 2, - "CacheLineSize": 0, - "dma": { - "peer": "system.iobus.slave[2]", - "role": "MASTER" - }, - "PMCAPCapId": 0, - "config_latency": 20000, - "BAR1Size": 4096, - "pio": { - "peer": "system.iobus.master[9]", - "role": "SLAVE" - }, - "pci_dev": 0, - "PMCAPCtrlStatus": 0, - "cxx_class": "IdeController", - "clk_domain": "system.clk_domain", - "SubsystemVendorID": 0, - "PMCAPBaseOffset": 0, - "MSICAPPendingBits": 0, - "MSIXTableOffset": 0, - "MSICAPMsgUpperAddr": 0, - "MSICAPCapId": 0, - "BAR0LegacyIO": true, - "ProgIF": 133, - "BAR1LegacyIO": true, - "PMCAPCapabilities": 0, - "ClassCode": 1, - "p_state_clk_gate_bins": 20 - }, - "sp810_fake": { - "p_state_clk_gate_bins": 20, - "name": "sp810_fake", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[16]", - "role": "SLAVE" - }, - "amba_id": 0, - "ignore_access": true, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "cxx_class": "AmbaFake", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.sp810_fake", - "pio_addr": 469893120, - "type": "AmbaFake" - }, - "ethernet": { - "PMCAPNextCapability": 0, - "InterruptPin": 1, - "HeaderType": 0, - "VendorID": 32902, - "MSIXMsgCtrl": 0, - "MSIXCAPNextCapability": 0, - "PXCAPLinkCtrl": 0, - "Revision": 0, - "hardware_address": "00:90:00:00:00:01", - "LegacyIOBase": 0, - "pio_latency": 30000, - "PXCAPLinkCap": 0, - "CapabilityPtr": 0, - "MSIXCAPBaseOffset": 0, - "PXCAPDevCapabilities": 0, - "MSIXCAPCapId": 0, - "BAR3Size": 0, - "rx_desc_cache_size": 64, - "power_model": null, - "PXCAPCapabilities": 0, - "SubsystemID": 4104, - "PXCAPCapId": 0, - "BAR4": 0, - "BAR1": 0, - "BAR0": 0, - "BAR3": 0, - "BAR2": 0, - "BAR5": 0, - "PXCAPDevStatus": 0, - "BAR2Size": 0, - "MSICAPNextCapability": 0, - "ExpansionROM": 0, - "rx_write_delay": 0, - "MSICAPMsgCtrl": 0, - "BAR5Size": 0, - "CardbusCIS": 0, - "MSIXPbaOffset": 0, - "MSICAPBaseOffset": 0, - "MaximumLatency": 0, - "BAR2LegacyIO": false, - "LatencyTimer": 0, - "BAR4LegacyIO": false, - "p_state_clk_gate_max": 1000000000000, - "PXCAPLinkStatus": 0, - "PXCAPDevCap2": 0, - "p_state_clk_gate_min": 1000, - "PXCAPDevCtrl": 0, - "MSICAPMaskBits": 0, - "host": "system.realview.pci_host", - "Command": 0, - "SubClassCode": 0, - "pci_func": 0, - "BAR5LegacyIO": false, - "MSICAPMsgData": 0, - "BIST": 0, - "PXCAPDevCtrl2": 0, - "pci_bus": 0, - "InterruptLine": 1, - "fetch_delay": 10000, - "MSICAPMsgAddr": 0, - "BAR3LegacyIO": false, - "BAR4Size": 0, - "path": "system.realview.ethernet", - "MinimumGrant": 255, - "phy_epid": 896, - "Status": 0, - "BAR0Size": 131072, - "system": "system", - "name": "ethernet", - "PXCAPNextCapability": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "type": "IGbE", - "tx_fifo_size": 393216, - "PXCAPBaseOffset": 0, - "DeviceID": 4213, - "tx_read_delay": 0, - "CacheLineSize": 0, - "dma": { - "peer": "system.iobus.slave[4]", - "role": "MASTER" - }, - "PMCAPCapId": 0, - "tx_desc_cache_size": 64, - "config_latency": 20000, - "BAR1Size": 0, - "pio": { - "peer": "system.iobus.master[24]", - "role": "SLAVE" - }, - "pci_dev": 0, - "PMCAPCtrlStatus": 0, - "cxx_class": "IGbE", - "wb_delay": 10000, - "fetch_comp_delay": 10000, - "clk_domain": "system.clk_domain", - "SubsystemVendorID": 32902, - "PMCAPBaseOffset": 0, - "MSICAPPendingBits": 0, - "MSIXTableOffset": 0, - "MSICAPMsgUpperAddr": 0, - "MSICAPCapId": 0, - "BAR0LegacyIO": false, - "ProgIF": 0, - "BAR1LegacyIO": false, - "wb_comp_delay": 10000, - "PMCAPCapabilities": 0, - "ClassCode": 2, - "p_state_clk_gate_bins": 20, - "rx_fifo_size": 393216, - "phy_pid": 680 - }, - "ide": { - "PMCAPNextCapability": 0, - "InterruptPin": 2, - "HeaderType": 0, - "VendorID": 32902, - "MSIXMsgCtrl": 0, - "MSIXCAPNextCapability": 0, - "PXCAPLinkCtrl": 0, - "Revision": 0, - "LegacyIOBase": 0, - "pio_latency": 30000, - "PXCAPLinkCap": 0, - "CapabilityPtr": 0, - "MSIXCAPBaseOffset": 0, - "PXCAPDevCapabilities": 0, - "MSIXCAPCapId": 0, - "BAR3Size": 4, - "power_model": null, - "PXCAPCapabilities": 0, - "SubsystemID": 0, - "PXCAPCapId": 0, - "BAR4": 1, - "BAR1": 1, - "BAR0": 1, - "BAR3": 1, - "BAR2": 1, - "BAR5": 1, - "PXCAPDevStatus": 0, - "disks": [ - "system.cf0" - ], - "BAR2Size": 8, - "MSICAPNextCapability": 0, - "ExpansionROM": 0, - "MSICAPMsgCtrl": 0, - "BAR5Size": 0, - "CardbusCIS": 0, - "MSIXPbaOffset": 0, - "MSICAPBaseOffset": 0, - "MaximumLatency": 0, - "BAR2LegacyIO": false, - "LatencyTimer": 0, - "BAR4LegacyIO": false, - "p_state_clk_gate_max": 1000000000000, - "PXCAPLinkStatus": 0, - "PXCAPDevCap2": 0, - "p_state_clk_gate_min": 1000, - "PXCAPDevCtrl": 0, - "MSICAPMaskBits": 0, - "host": "system.realview.pci_host", - "Command": 0, - "SubClassCode": 1, - "pci_func": 0, - "BAR5LegacyIO": false, - "MSICAPMsgData": 0, - "BIST": 0, - "PXCAPDevCtrl2": 0, - "pci_bus": 0, - "InterruptLine": 2, - "MSICAPMsgAddr": 0, - "BAR3LegacyIO": false, - "BAR4Size": 16, - "path": "system.realview.ide", - "MinimumGrant": 0, - "Status": 640, - "BAR0Size": 8, - "system": "system", - "name": "ide", - "PXCAPNextCapability": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "type": "IdeController", - "ctrl_offset": 0, - "PXCAPBaseOffset": 0, - "DeviceID": 28945, - "io_shift": 0, - "CacheLineSize": 0, - "dma": { - "peer": "system.iobus.slave[3]", - "role": "MASTER" - }, - "PMCAPCapId": 0, - "config_latency": 20000, - "BAR1Size": 4, - "pio": { - "peer": "system.iobus.master[23]", - "role": "SLAVE" - }, - "pci_dev": 1, - "PMCAPCtrlStatus": 0, - "cxx_class": "IdeController", - "clk_domain": "system.clk_domain", - "SubsystemVendorID": 0, - "PMCAPBaseOffset": 0, - "MSICAPPendingBits": 0, - "MSIXTableOffset": 0, - "MSICAPMsgUpperAddr": 0, - "MSICAPCapId": 0, - "BAR0LegacyIO": false, - "ProgIF": 133, - "BAR1LegacyIO": false, - "PMCAPCapabilities": 0, - "ClassCode": 1, - "p_state_clk_gate_bins": 20 - } - }, - "membus": { - "point_of_coherency": true, - "system": "system", - "response_latency": 2, - "cxx_class": "CoherentXBar", - "badaddr_responder": { - "pio": { - "peer": "system.membus.default", - "role": "SLAVE" - }, - "ret_data64": 18446744073709551615, - "fake_mem": false, - "clk_domain": "system.clk_domain", - "cxx_class": "IsaFake", - "pio_addr": 0, - "update_data": false, - "warn_access": "warn", - "pio_latency": 100000, - "system": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "type": "IsaFake", - "p_state_clk_gate_min": 1000, - "power_model": null, - "ret_data32": 4294967295, - "path": "system.membus.badaddr_responder", - "ret_data16": 65535, - "ret_data8": 255, - "name": "badaddr_responder", - "ret_bad_addr": true, - "pio_size": 8, - "p_state_clk_gate_bins": 20 - }, - "forward_latency": 4, - "clk_domain": "system.clk_domain", - "width": 16, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "master": { - "peer": [ - "system.bridge.slave", - "system.realview.nvmem.port", - "system.realview.gic.pio", - "system.realview.vgic.pio", - "system.realview.local_cpu_timer.pio", - "system.physmem.port" - ], - "role": "MASTER" - }, - "type": "CoherentXBar", - "frontend_latency": 3, - "slave": { - "peer": [ - "system.realview.hdlcd.dma", - "system.system_port", - "system.cpu.l2cache.mem_side", - "system.iocache.mem_side" - ], - "role": "SLAVE" - }, - "p_state_clk_gate_min": 1000, - "snoop_filter": null, - "power_model": null, - "path": "system.membus", - "snoop_response_latency": 4, - "name": "membus", - "default": { - "peer": "system.membus.badaddr_responder.pio", - "role": "MASTER" - }, - "p_state_clk_gate_bins": 20, - "use_default_range": false - }, - "multi_thread": false, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "iocache": { - "cpu_side": { - "peer": "system.iobus.master[25]", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": null, - "system": "system", - "write_buffers": 8, - "response_latency": 50, - "cxx_class": "Cache", - "size": 1024, - "tags": { - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.clk_domain", - "power_model": null, - "sequential_access": false, - "assoc": 8, - "cxx_class": "LRU", - "p_state_clk_gate_max": 1000000000000, - "path": "system.iocache.tags", - "hit_latency": 50, - "block_size": 64, - "type": "LRU", - "size": 1024 - }, - "clk_domain": "system.clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.membus.slave[3]", - "role": "MASTER" - }, - "type": "Cache", - "writeback_clean": false, - "p_state_clk_gate_min": 1000, - "hit_latency": 50, - "tgts_per_mshr": 12, - "demand_mshr_reserve": 1, - "power_model": null, - "addr_ranges": [ - "2147483648:2415919103" - ], - "is_read_only": false, - "prefetch_on_access": false, - "path": "system.iocache", - "mshrs": 20, - "name": "iocache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 8 - }, - "dvfs_handler": { - "enable": false, - "name": "dvfs_handler", - "sys_clk_domain": "system.clk_domain", - "transition_latency": 100000000, - "eventq_index": 0, - "cxx_class": "DVFSHandler", - "domains": [], - "path": "system.dvfs_handler", - "type": "DVFSHandler" - }, - "work_end_exit_count": 0, - "type": "LinuxArmSystem", - "p_state_clk_gate_min": 1000, - "voltage_domain": { - "name": "voltage_domain", - "eventq_index": 0, - "voltage": [ - "1.0" - ], - "cxx_class": "VoltageDomain", - "path": "system.voltage_domain", - "type": "VoltageDomain" - }, - "cache_line_size": 64, - "boot_osflags": "earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1", - "system_port": { - "peer": "system.membus.slave[1]", - "role": "MASTER" - }, - "physmem": [ - { - "range": "2147483648:2415919103", - "latency": 30000, - "name": "physmem", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.clk_domain", - "power_model": null, - "latency_var": 0, - "bandwidth": "73.000000", - "conf_table_reported": true, - "cxx_class": "SimpleMemory", - "p_state_clk_gate_max": 1000000000000, - "path": "system.physmem", - "null": false, - "type": "SimpleMemory", - "port": { - "peer": "system.membus.master[5]", - "role": "SLAVE" - }, - "in_addr_map": true - } - ], - "terminal": { - "name": "terminal", - "output": true, - "number": 0, - "intr_control": "system.intrctrl", - "eventq_index": 0, - "cxx_class": "Terminal", - "path": "system.terminal", - "type": "Terminal", - "port": 3456 - }, - "power_model": null, - "reset_addr_64": 0, - "cpu": [ - { - "do_statistics_insts": true, - "numThreads": 1, - "itb": { - "name": "itb", - "is_stage2": false, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "p_state_clk_gate_min": 1000, - "name": "walker", - "is_stage2": false, - "p_state_clk_gate_bins": 20, - "cxx_class": "ArmISA::TableWalker", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sys": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.itb.walker", - "type": "ArmTableWalker", - "port": { - "peer": "system.cpu.toL2Bus.slave[2]", - "role": "MASTER" - }, - "num_squash_per_cycle": 2 - }, - "path": "system.cpu.itb", - "type": "ArmTLB", - "size": 64 - }, - "simulate_data_stalls": false, - "istage2_mmu": { - "name": "istage2_mmu", - "tlb": "system.cpu.itb", - "sys": "system", - "stage2_tlb": { - "name": "stage2_tlb", - "is_stage2": true, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "p_state_clk_gate_min": 1000, - "name": "walker", - "is_stage2": true, - "p_state_clk_gate_bins": 20, - "cxx_class": "ArmISA::TableWalker", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sys": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.istage2_mmu.stage2_tlb.walker", - "type": "ArmTableWalker", - "num_squash_per_cycle": 2 - }, - "path": "system.cpu.istage2_mmu.stage2_tlb", - "type": "ArmTLB", - "size": 32 - }, - "eventq_index": 0, - "cxx_class": "ArmISA::Stage2MMU", - "path": "system.cpu.istage2_mmu", - "type": "ArmStage2MMU" - }, - "icache": { - "cpu_side": { - "peer": "system.cpu.icache_port", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": null, - "system": "system", - "write_buffers": 8, - "response_latency": 2, - "cxx_class": "Cache", - "size": 32768, - "tags": { - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sequential_access": false, - "assoc": 1, - "cxx_class": "LRU", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.icache.tags", - "hit_latency": 2, - "block_size": 64, - "type": "LRU", - "size": 32768 - }, - "clk_domain": "system.cpu_clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.cpu.toL2Bus.slave[0]", - "role": "MASTER" - }, - "type": "Cache", - "writeback_clean": true, - "p_state_clk_gate_min": 1000, - "hit_latency": 2, - "tgts_per_mshr": 20, - "demand_mshr_reserve": 1, - "power_model": null, - "addr_ranges": [ - "0:18446744073709551615" - ], - "is_read_only": true, - "prefetch_on_access": false, - "path": "system.cpu.icache", - "mshrs": 4, - "name": "icache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 1 - }, - "function_trace": false, - "do_checkpoint_insts": true, - "cxx_class": "AtomicSimpleCPU", - "max_loads_all_threads": 0, - "system": "system", - "clk_domain": "system.cpu_clk_domain", - "function_trace_start": 0, - "cpu_id": 0, - "width": 1, - "checker": null, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "toL2Bus": { - "point_of_coherency": false, - "system": "system", - "response_latency": 1, - "cxx_class": "CoherentXBar", - "forward_latency": 0, - "clk_domain": "system.cpu_clk_domain", - "width": 32, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "master": { - "peer": [ - "system.cpu.l2cache.cpu_side" - ], - "role": "MASTER" - }, - "type": "CoherentXBar", - "frontend_latency": 1, - "slave": { - "peer": [ - "system.cpu.icache.mem_side", - "system.cpu.dcache.mem_side", - "system.cpu.itb.walker.port", - "system.cpu.dtb.walker.port" - ], - "role": "SLAVE" - }, - "p_state_clk_gate_min": 1000, - "snoop_filter": { - "name": "snoop_filter", - "system": "system", - "max_capacity": 8388608, - "eventq_index": 0, - "cxx_class": "SnoopFilter", - "path": "system.cpu.toL2Bus.snoop_filter", - "type": "SnoopFilter", - "lookup_latency": 0 - }, - "power_model": null, - "path": "system.cpu.toL2Bus", - "snoop_response_latency": 1, - "name": "toL2Bus", - "p_state_clk_gate_bins": 20, - "use_default_range": false - }, - "do_quiesce": true, - "type": "AtomicSimpleCPU", - "fastmem": false, - "profile": 0, - "icache_port": { - "peer": "system.cpu.icache.cpu_side", - "role": "MASTER" - }, - "p_state_clk_gate_bins": 20, - "p_state_clk_gate_min": 1000, - "interrupts": [ - { - "eventq_index": 0, - "path": "system.cpu.interrupts", - "type": "ArmInterrupts", - "name": "interrupts", - "cxx_class": "ArmISA::Interrupts" - } - ], - "dcache_port": { - "peer": "system.cpu.dcache.cpu_side", - "role": "MASTER" - }, - "socket_id": 0, - "power_model": null, - "max_insts_all_threads": 0, - "dstage2_mmu": { - "name": "dstage2_mmu", - "tlb": "system.cpu.dtb", - "sys": "system", - "stage2_tlb": { - "name": "stage2_tlb", - "is_stage2": true, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "p_state_clk_gate_min": 1000, - "name": "walker", - "is_stage2": true, - "p_state_clk_gate_bins": 20, - "cxx_class": "ArmISA::TableWalker", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sys": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.dstage2_mmu.stage2_tlb.walker", - "type": "ArmTableWalker", - "num_squash_per_cycle": 2 - }, - "path": "system.cpu.dstage2_mmu.stage2_tlb", - "type": "ArmTLB", - "size": 32 - }, - "eventq_index": 0, - "cxx_class": "ArmISA::Stage2MMU", - "path": "system.cpu.dstage2_mmu", - "type": "ArmStage2MMU" - }, - "l2cache": { - "cpu_side": { - "peer": "system.cpu.toL2Bus.master[0]", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": null, - "system": "system", - "write_buffers": 8, - "response_latency": 20, - "cxx_class": "Cache", - "size": 4194304, - "tags": { - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sequential_access": false, - "assoc": 8, - "cxx_class": "LRU", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.l2cache.tags", - "hit_latency": 20, - "block_size": 64, - "type": "LRU", - "size": 4194304 - }, - "clk_domain": "system.cpu_clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.membus.slave[2]", - "role": "MASTER" - }, - "type": "Cache", - "writeback_clean": false, - "p_state_clk_gate_min": 1000, - "hit_latency": 20, - "tgts_per_mshr": 12, - "demand_mshr_reserve": 1, - "power_model": null, - "addr_ranges": [ - "0:18446744073709551615" - ], - "is_read_only": false, - "prefetch_on_access": false, - "path": "system.cpu.l2cache", - "mshrs": 20, - "name": "l2cache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 8 - }, - "path": "system.cpu", - "max_loads_any_thread": 0, - "switched_out": false, - "workload": [], - "name": "cpu", - "dtb": { - "name": "dtb", - "is_stage2": false, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "p_state_clk_gate_min": 1000, - "name": "walker", - "is_stage2": false, - "p_state_clk_gate_bins": 20, - "cxx_class": "ArmISA::TableWalker", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sys": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.dtb.walker", - "type": "ArmTableWalker", - "port": { - "peer": "system.cpu.toL2Bus.slave[3]", - "role": "MASTER" - }, - "num_squash_per_cycle": 2 - }, - "path": "system.cpu.dtb", - "type": "ArmTLB", - "size": 64 - }, - "simpoint_start_insts": [], - "max_insts_any_thread": 0, - "simulate_inst_stalls": false, - "progress_interval": 0, - "branchPred": null, - "dcache": { - "cpu_side": { - "peer": "system.cpu.dcache_port", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": null, - "system": "system", - "write_buffers": 8, - "response_latency": 2, - "cxx_class": "Cache", - "size": 32768, - "tags": { - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sequential_access": false, - "assoc": 4, - "cxx_class": "LRU", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.dcache.tags", - "hit_latency": 2, - "block_size": 64, - "type": "LRU", - "size": 32768 - }, - "clk_domain": "system.cpu_clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.cpu.toL2Bus.slave[1]", - "role": "MASTER" - }, - "type": "Cache", - "writeback_clean": false, - "p_state_clk_gate_min": 1000, - "hit_latency": 2, - "tgts_per_mshr": 20, - "demand_mshr_reserve": 1, - "power_model": null, - "addr_ranges": [ - "0:18446744073709551615" - ], - "is_read_only": false, - "prefetch_on_access": false, - "path": "system.cpu.dcache", - "mshrs": 4, - "name": "dcache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 4 - }, - "isa": [ - { - "pmu": null, - "id_pfr1": 4113, - "id_pfr0": 49, - "id_isar1": 34677009, - "id_isar0": 34607377, - "id_isar3": 17899825, - "id_isar2": 555950401, - "id_isar5": 0, - "id_isar4": 268501314, - "cxx_class": "ArmISA::ISA", - "id_aa64mmfr1_el1": 0, - "id_aa64pfr1_el1": 0, - "system": "system", - "eventq_index": 0, - "type": "ArmISA", - "id_aa64dfr1_el1": 0, - "fpsid": 1090793632, - "id_mmfr0": 270536963, - "id_mmfr1": 0, - "id_mmfr2": 19070976, - "id_mmfr3": 34611729, - "id_aa64mmfr0_el1": 15728642, - "id_aa64dfr0_el1": 1052678, - "path": "system.cpu.isa", - "id_aa64isar0_el1": 0, - "decoderFlavour": "Generic", - "name": "isa", - "midr": 1091551472, - "id_aa64afr0_el1": 0, - "id_aa64isar1_el1": 0, - "id_aa64afr1_el1": 0, - "id_aa64pfr0_el1": 17 - } - ], - "tracer": { - "eventq_index": 0, - "path": "system.cpu.tracer", - "type": "ExeTracer", - "name": "tracer", - "cxx_class": "Trace::ExeTracer" - } - } - ], - "gic_cpu_addr": 738205696, - "work_cpus_ckpt_count": 0, - "thermal_components": [], - "machine_type": "VExpress_EMM64", - "flags_addr": 469827632, - "path": "system", - "cpu_clk_domain": { - "name": "cpu_clk_domain", - "clock": [ - 500 - ], - "init_perf_level": 0, - "voltage_domain": "system.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.cpu_clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "cf0": { - "driveID": "master", - "name": "cf0", - "image": { - "read_only": false, - "name": "image", - "cxx_class": "CowDiskImage", - "eventq_index": 0, - "child": { - "read_only": true, - "name": "child", - "eventq_index": 0, - "cxx_class": "RawDiskImage", - "path": "system.cf0.image.child", - "image_file": "/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img", - "type": "RawDiskImage" - }, - "path": "system.cf0.image", - "image_file": "", - "type": "CowDiskImage", - "table_size": 65536 - }, - "delay": 1000000, - "eventq_index": 0, - "cxx_class": "IdeDisk", - "path": "system.cf0", - "type": "IdeDisk" - }, - "work_end_ckpt_count": 0, - "mem_mode": "atomic", - "name": "system", - "init_param": 0, - "p_state_clk_gate_bins": 20, - "load_addr_mask": 268435455, - "work_item_id": -1, - "intrctrl": { - "name": "intrctrl", - "sys": "system", - "eventq_index": 0, - "cxx_class": "IntrControl", - "path": "system.intrctrl", - "type": "IntrControl" - }, - "have_security": false, - "atags_addr": 134217728, - "memories": [ - "system.physmem", - "system.realview.nvmem", - "system.realview.vram" - ], - "num_work_ids": 16, - "boot_loader": [ - "/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64" - ], - "exit_on_work_items": false - }, - "time_sync_period": 100000000000, - "eventq_index": 0, - "time_sync_spin_threshold": 100000000, - "cxx_class": "Root", - "path": "root", - "time_sync_enable": false, - "type": "Root", - "full_system": true -}
\ No newline at end of file diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt deleted file mode 100644 index a22c43be0..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt +++ /dev/null @@ -1,874 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 51.111167 # Number of seconds simulated -sim_ticks 51111167268500 # Number of ticks simulated -final_tick 51111167268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 926682 # Simulator instruction rate (inst/s) -host_op_rate 1089052 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48222226969 # Simulator tick rate (ticks/s) -host_mem_usage 681368 # Number of bytes of host memory used -host_seconds 1059.91 # Real time elapsed on the host -sim_insts 982198023 # Number of instructions simulated -sim_ops 1154295627 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5483444 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 74913992 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory -system.physmem.bytes_read::total 81622268 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5483444 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5483444 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103278528 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103299108 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 126086 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1170544 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315768 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613727 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616300 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 107285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1465707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1596956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2021067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1466110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3618023 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 266581 # Table walker walks requested -system.cpu.dtb.walker.walksLong 266581 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walkWaitTime::samples 266581 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 266581 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 266581 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 204774 89.35% 89.35% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 24411 10.65% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 229185 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266581 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266581 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229185 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229185 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 495766 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 183543984 # DTB read hits -system.cpu.dtb.read_misses 195343 # DTB read misses -system.cpu.dtb.write_hits 167774645 # DTB write hits -system.cpu.dtb.write_misses 71238 # DTB write misses -system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 82439 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9074 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 183739327 # DTB read accesses -system.cpu.dtb.write_accesses 167845883 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 351318629 # DTB hits -system.cpu.dtb.misses 266581 # DTB misses -system.cpu.dtb.accesses 351585210 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 126834 # Table walker walks requested -system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 126834 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 126834 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 113574 99.02% 99.02% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1122 0.98% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 114696 # Table walker page sizes translated -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126834 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 126834 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 982674869 # ITB inst hits -system.cpu.itb.inst_misses 126834 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 58009 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 982801703 # ITB inst accesses -system.cpu.itb.hits 982674869 # DTB hits -system.cpu.itb.misses 126834 # DTB misses -system.cpu.itb.accesses 982801703 # DTB accesses -system.cpu.numPwrStateTransitions 33550 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 16775 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3012440908.824083 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 59942517661.771744 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 7454 44.44% 44.44% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 9286 55.36% 99.79% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5e+10-1e+11 4 0.02% 99.82% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 4 0.02% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 3 0.02% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::3.5e+11-4e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 1988782931704 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 16775 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 577471022976 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50533696245524 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 102222351313 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu.committedInsts 982198023 # Number of instructions committed -system.cpu.committedOps 1154295627 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1057877135 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses -system.cpu.num_func_calls 56833843 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 151622640 # number of instructions that are conditional controls -system.cpu.num_int_insts 1057877135 # number of integer instructions -system.cpu.num_fp_insts 881349 # number of float instructions -system.cpu.num_int_register_reads 1560753668 # number of times the integer registers were read -system.cpu.num_int_register_writes 840513151 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read -system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written -system.cpu.num_cc_register_reads 264017457 # number of times the CC registers were read -system.cpu.num_cc_register_writes 263439679 # number of times the CC registers were written -system.cpu.num_mem_refs 351538055 # number of memory refs -system.cpu.num_load_insts 183711282 # Number of load instructions -system.cpu.num_store_insts 167826773 # Number of store instructions -system.cpu.num_idle_cycles 101067409077.505173 # Number of idle cycles -system.cpu.num_busy_cycles 1154942235.494823 # Number of busy cycles -system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.988702 # Percentage of idle cycles -system.cpu.Branches 219532189 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 800829443 69.34% 69.34% # Class of executed instruction -system.cpu.op_class::IntMult 2354388 0.20% 69.54% # Class of executed instruction -system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu.op_class::MemRead 183711282 15.91% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 167826773 14.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1154930294 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 11606056 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 339854782 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11606568 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.281247 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1417452033 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1417452033 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 171110167 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 171110167 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 159090000 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 159090000 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 424478 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 424478 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 336283 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 336283 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303639 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4303639 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4555644 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4555644 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 330536450 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 330536450 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 330960928 # number of overall hits -system.cpu.dcache.overall_hits::total 330960928 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6002834 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6002834 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2551547 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2551547 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1586190 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1586190 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1246772 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1246772 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 253808 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 253808 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 9801153 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9801153 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11387343 # number of overall misses -system.cpu.dcache.overall_misses::total 11387343 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 177113001 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177113001 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 161641547 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 161641547 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010668 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2010668 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557447 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4557447 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555645 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4555645 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 340337603 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 340337603 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 342348271 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 342348271 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033893 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033893 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015785 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015785 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788887 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788887 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787573 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.787573 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.028798 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.028798 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.033262 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.033262 # miss rate for overall accesses -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 8918956 # number of writebacks -system.cpu.dcache.writebacks::total 8918956 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 14265255 # number of replacements -system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 968523793 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14265767 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.891463 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6061932500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 997055337 # Number of tag accesses -system.cpu.icache.tags.data_accesses 997055337 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 968523793 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 968523793 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 968523793 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 968523793 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 968523793 # number of overall hits -system.cpu.icache.overall_hits::total 968523793 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14265772 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14265772 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14265772 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14265772 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14265772 # number of overall misses -system.cpu.icache.overall_misses::total 14265772 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 982789565 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 982789565 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 982789565 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 982789565 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 982789565 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 982789565 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014516 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 14265255 # number of writebacks -system.cpu.icache.writebacks::total 14265255 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1725823 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65403.901916 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 49389938 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1788899 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 27.609126 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 395496000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9615.361386 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 436.090806 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 495.840367 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.388739 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48781.220619 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.146719 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006654 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007566 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092703 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.744342 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997984 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 373 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62703 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 373 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1444 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55698 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005692 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956772 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 422564531 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 422564531 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 480106 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 237369 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 717475 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8918956 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 8918956 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 14263678 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 14263678 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 30692 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 30692 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1689371 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1689371 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182774 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 14182774 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7498712 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7498712 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 694558 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 694558 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 480106 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 237369 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14182774 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 9188083 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24088332 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 480106 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 237369 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14182774 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 9188083 # number of overall hits -system.cpu.l2cache.overall_hits::total 24088332 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6476 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5837 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 12313 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 3878 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 3878 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 827606 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 827606 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 82998 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 82998 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344120 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 344120 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 552214 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 552214 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 6476 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5837 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 82998 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1171726 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1267037 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 6476 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5837 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 82998 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1171726 # number of overall misses -system.cpu.l2cache.overall_misses::total 1267037 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 486582 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 243206 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 729788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 8918956 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 8918956 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 14263678 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 14263678 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 34570 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 34570 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2516977 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2516977 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265772 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 14265772 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7842832 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7842832 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246772 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1246772 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 486582 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 243206 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 14265772 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 10359809 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 25355369 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 486582 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 243206 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14265772 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 10359809 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 25355369 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.013309 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.024000 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016872 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.112178 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.112178 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328810 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.328810 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005818 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005818 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043877 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442915 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442915 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.013309 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.024000 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005818 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.113103 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.049971 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.013309 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.024000 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005818 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.113103 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.049971 # miss rate for overall accesses -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1507096 # number of writebacks -system.cpu.l2cache.writebacks::total 1507096 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 52368206 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 26495860 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2694 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2694 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 1229979 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23338583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8918956 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 14265255 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2687100 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 34570 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 34571 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2516977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2516977 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265772 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7842832 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1246772 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1246772 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883049 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35022680 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548392 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 80212329 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826158228 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234030630 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3069415258 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1762518 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 96494656 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 54803543 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.010878 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103729 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 54207383 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 596160 1.09% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 54803543 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40242 # Transaction distribution -system.iobus.trans_dist::ReadResp 40242 # Transaction distribution -system.iobus.trans_dist::WriteReq 136515 # Transaction distribution -system.iobus.trans_dist::WriteResp 136515 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353514 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115459 # number of replacements -system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use -system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13082113307009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039650 # Number of tag accesses -system.iocache.tags.data_accesses 1039650 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses -system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses -system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115477 # number of demand (read+write) misses -system.iocache.demand_misses::total 115517 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115477 # number of overall misses -system.iocache.overall_misses::total 115517 # number of overall misses -system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115477 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115517 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115477 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115517 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses -system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks -system.membus.snoop_filter.tot_requests 3778694 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1875355 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 2861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 524960 # Transaction distribution -system.membus.trans_dist::WriteReq 33606 # Transaction distribution -system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1613727 # Transaction distribution -system.membus.trans_dist::CleanEvict 226320 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4445 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4446 # Transaction distribution -system.membus.trans_dist::ReadExReq 827049 # Transaction distribution -system.membus.trans_dist::ReadExResp 827049 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 448281 # Transaction distribution -system.membus.trans_dist::InvalidateReq 658871 # Transaction distribution -system.membus.trans_dist::InvalidateResp 658871 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5462226 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5591418 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5937911 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 177701984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 177871034 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 185261818 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3888979 # Request fanout histogram -system.membus.snoop_fanout::mean 0.009406 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.096529 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3852398 99.06% 99.06% # Request fanout histogram -system.membus.snoop_fanout::1 36581 0.94% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3888979 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks -system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks -system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks -system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks -system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks -system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.txBytes 966 # Bytes Transmitted -system.realview.ethernet.txPackets 3 # Number of Packets Transmitted -system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device -system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device -system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) -system.realview.ethernet.totPackets 3 # Total Packets -system.realview.ethernet.totBytes 966 # Total Bytes -system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) -system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 13 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks -system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks -system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51111167268500 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/system.terminal deleted file mode 100644 index e00102254..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/system.terminal +++ /dev/null @@ -1,183 +0,0 @@ -[ 0.000000] Initializing cgroup subsys cpu
-[ 0.000000] Linux version 3.16.0-rc6 (tony@vamp) (gcc version 4.8.2 20140110 (prerelease) [ibm/gcc-4_8-branch merged from gcc-4_8-branch, revision 205847] (Ubuntu/Linaro 4.8.2-13ubuntu1) ) #1 SMP PREEMPT Wed Oct 1 14:39:23 EDT 2014
-[ 0.000000] CPU: AArch64 Processor [410fc0f0] revision 0
-[ 0.000000] No Cache Writeback Granule information, assuming cache line size 64
-[ 0.000000] Memory limited to 256MB
-[ 0.000000] cma: CMA: reserved 16 MiB at 8f000000
-[ 0.000000] On node 0 totalpages: 65536
-[ 0.000000] DMA zone: 896 pages used for memmap
-[ 0.000000] DMA zone: 0 pages reserved
-[ 0.000000] DMA zone: 65536 pages, LIFO batch:15
-[ 0.000000] PERCPU: Embedded 11 pages/cpu @ffffffc00efc5000 s12800 r8192 d24064 u45056
-[ 0.000000] pcpu-alloc: s12800 r8192 d24064 u45056 alloc=11*4096
-[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
-[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 64640
-[ 0.000000] Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-[ 0.000000] PID hash table entries: 1024 (order: 1, 8192 bytes)
-[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes)
-[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes)
-[ 0.000000] Memory: 223784K/262144K available (4569K kernel code, 308K rwdata, 1640K rodata, 208K init, 187K bss, 38360K reserved)
-[ 0.000000] Virtual kernel memory layout:
-[ 0.000000] vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000 (245759 MB)
-[ 0.000000] vmemmap : 0xffffffbc01c00000 - 0xffffffbc01f80000 ( 3 MB)
-[ 0.000000] modules : 0xffffffbffc000000 - 0xffffffc000000000 ( 64 MB)
-[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc010000000 ( 256 MB)
-[ 0.000000] .init : 0xffffffc000692000 - 0xffffffc0006c6200 ( 209 kB)
-[ 0.000000] .text : 0xffffffc000080000 - 0xffffffc0006914e4 ( 6214 kB)
-[ 0.000000] .data : 0xffffffc0006c7000 - 0xffffffc0007141e0 ( 309 kB)
-[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
-[ 0.000000] Preemptible hierarchical RCU implementation.
-[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
-[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
-[ 0.000000] NR_IRQS:64 nr_irqs:64 0
-[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000013] Console: colour dummy device 80x25
-[ 0.000014] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000015] pid_max: default: 32768 minimum: 301
-[ 0.000022] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000023] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000066] hw perfevents: no hardware support available
-[ 1.060049] CPU1: failed to come online
-[ 2.080098] CPU2: failed to come online
-[ 3.100148] CPU3: failed to come online
-[ 3.100150] Brought up 1 CPUs
-[ 3.100151] SMP: Total of 1 processors activated.
-[ 3.100177] devtmpfs: initialized
-[ 3.100579] atomic64_test: passed
-[ 3.100603] regulator-dummy: no parameters
-[ 3.100844] NET: Registered protocol family 16
-[ 3.100938] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.100941] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.100980] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.100981] Serial: AMBA PL011 UART driver
-[ 3.101103] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.101125] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.101160] console [ttyAMA0] enabled
-[ 3.101194] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.101208] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.101222] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.101235] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130356] 3V3: 3300 mV
-[ 3.130377] vgaarb: loaded
-[ 3.130406] SCSI subsystem initialized
-[ 3.130425] libata version 3.00 loaded.
-[ 3.130450] usbcore: registered new interface driver usbfs
-[ 3.130457] usbcore: registered new interface driver hub
-[ 3.130471] usbcore: registered new device driver usb
-[ 3.130482] pps_core: LinuxPPS API ver. 1 registered
-[ 3.130483] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.130487] PTP clock support registered
-[ 3.130559] Switched to clocksource arch_sys_counter
-[ 3.131204] NET: Registered protocol family 2
-[ 3.131250] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.131255] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.131259] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.131263] TCP: reno registered
-[ 3.131264] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.131266] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.131281] NET: Registered protocol family 1
-[ 3.131311] RPC: Registered named UNIX socket transport module.
-[ 3.131311] RPC: Registered udp transport module.
-[ 3.131312] RPC: Registered tcp transport module.
-[ 3.131313] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.131315] PCI: CLS 0 bytes, default 64
-[ 3.131413] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.131456] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.132687] fuse init (API version 7.23)
-[ 3.132738] msgmni has been set to 469
-[ 3.133992] io scheduler noop registered
-[ 3.134025] io scheduler cfq registered (default)
-[ 3.134296] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.134298] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.134299] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.134301] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.134302] pci_bus 0000:00: scanning bus
-[ 3.134304] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.134306] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.134309] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.134326] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.134328] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.134330] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.134331] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.134333] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.134335] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.134337] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.134354] pci_bus 0000:00: fixups for bus
-[ 3.134355] pci_bus 0000:00: bus scan returning with max=00
-[ 3.134357] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.134362] pci 0000:00:00.0: fixup irq: got 33
-[ 3.134363] pci 0000:00:00.0: assigning IRQ 33
-[ 3.134366] pci 0000:00:01.0: fixup irq: got 34
-[ 3.134367] pci 0000:00:01.0: assigning IRQ 34
-[ 3.134369] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.134371] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.134373] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.134374] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.134376] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.134378] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.134379] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.134381] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.134660] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.134813] ata_piix 0000:00:01.0: version 2.13
-[ 3.134815] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.134820] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.135009] scsi0 : ata_piix
-[ 3.135063] scsi1 : ata_piix
-[ 3.135081] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.135082] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.135143] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.135144] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.135148] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.135150] e1000 0000:00:00.0: enabling bus mastering
-[ 3.290565] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.290566] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.290572] ata1.00: configured for UDMA/33
-[ 3.290589] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.290650] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.290658] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.290672] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.290673] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.290680] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.290733] sda: sda1
-[ 3.290795] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.410824] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.410825] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.410832] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.410833] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.410841] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.410842] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.410886] usbcore: registered new interface driver usb-storage
-[ 3.410912] mousedev: PS/2 mouse device common for all mice
-[ 3.411009] usbcore: registered new interface driver usbhid
-[ 3.411010] usbhid: USB HID core driver
-[ 3.411025] TCP: cubic registered
-[ 3.411026] NET: Registered protocol family 17
- -[ 3.411214] devtmpfs: mounted
-[ 3.411222] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
- - -[ 3.446950] udevd[607]: starting version 182
-Starting Bootlog daemon: bootlogd.
-[ 3.532262] random: dd urandom read with 19 bits of entropy available
-Populating dev cache
-net.ipv4.conf.default.rp_filter = 1
-net.ipv4.conf.all.rp_filter = 1
-hwclock: can't open '/dev/misc/rtc': No such file or directory
-Mon Jan 27 08:00:00 UTC 2014
-hwclock: can't open '/dev/misc/rtc': No such file or directory
-
INIT: Entering runlevel: 5
-Configuring network interfaces... udhcpc (v1.21.1) started
-[ 3.640780] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
-Sending discover...
-Sending discover...
-Sending discover...
-No lease, forking to background
-done.
-Starting rpcbind daemon...rpcbind: cannot create socket for udp6
-rpcbind: cannot create socket for tcp6
-done.
-rpcbind: cannot get uid of '': Success
-creating NFS state directory: done
-starting statd: done
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/EMPTY b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/EMPTY new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/EMPTY diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini deleted file mode 100644 index 73c3099b7..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini +++ /dev/null @@ -1,1559 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxArmSystem -children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain -atags_addr=134217728 -boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb -early_kernel_symbols=false -enable_context_switch_stats_dump=false -eventq_index=0 -exit_on_work_items=false -flags_addr=469827632 -gic_cpu_addr=738205696 -have_large_asid_64=false -have_lpae=true -have_security=false -have_virtualization=false -highest_el_is_64=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 -kernel_addr_check=true -load_addr_mask=268435455 -load_offset=2147483648 -machine_type=VExpress_EMM -mem_mode=atomic -mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.nvmem system.realview.vram -mmap_using_noreserve=false -multi_proc=true -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -panic_on_oops=true -panic_on_panic=true -phys_addr_range_64=40 -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -reset_addr_64=0 -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[1] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.cf0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.cf0.image - -[system.cf0.image] -type=CowDiskImage -children=child -child=system.cf0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.cf0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img -read_only=true - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[2] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=2147483648:2415919103 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[3] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.membus] -type=CoherentXBar -children=badaddr_responder -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access=warn -pio=system.membus.default - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=2147483648:2415919103 -port=system.membus.master[5] - -[system.realview] -type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.realview.aaci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470024192 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[18] - -[system.realview.cf_ctrl] -type=IdeController -BAR0=471465984 -BAR0LegacyIO=true -BAR0Size=256 -BAR1=471466240 -BAR1LegacyIO=true -BAR1Size=4096 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=1 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=2 -default_p_state=UNDEFINED -disks= -eventq_index=0 -host=system.realview.pci_host -io_shift=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=2 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[2] -pio=system.iobus.master[9] - -[system.realview.clcd] -type=Pl111 -amba_id=1315089 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=46 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471793664 -pio_latency=10000 -pixel_clock=41667 -power_model=Null -system=system -vnc=system.vncserver -dma=system.iobus.slave[1] -pio=system.iobus.master[5] - -[system.realview.dcc] -type=SubSystem -children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys -eventq_index=0 -thermal_domain=Null - -[system.realview.dcc.osc_cpu] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_ddr] -type=RealViewOsc -dcc=0 -device=8 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_hsbm] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_pxl] -type=RealViewOsc -dcc=0 -device=5 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_smb] -type=RealViewOsc -dcc=0 -device=6 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_sys] -type=RealViewOsc -dcc=0 -device=7 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.energy_ctrl] -type=EnergyCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dvfs_handler=system.dvfs_handler -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470286336 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[22] - -[system.realview.ethernet] -type=IGbE -BAR0=0 -BAR0LegacyIO=false -BAR0Size=131072 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=0 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=4213 -ExpansionROM=0 -HeaderType=0 -InterruptLine=1 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=255 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=0 -SubClassCode=0 -SubsystemID=4104 -SubsystemVendorID=32902 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -eventq_index=0 -fetch_comp_delay=10000 -fetch_delay=10000 -hardware_address=00:90:00:00:00:01 -host=system.realview.pci_host -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -phy_epid=896 -phy_pid=680 -pio_latency=30000 -power_model=Null -rx_desc_cache_size=64 -rx_fifo_size=393216 -rx_write_delay=0 -system=system -tx_desc_cache_size=64 -tx_fifo_size=393216 -tx_read_delay=0 -wb_comp_delay=10000 -wb_delay=10000 -dma=system.iobus.slave[4] -pio=system.iobus.master[24] - -[system.realview.generic_timer] -type=GenericTimer -eventq_index=0 -gic=system.realview.gic -int_phys=29 -int_virt=27 -system=system - -[system.realview.gic] -type=Pl390 -clk_domain=system.clk_domain -cpu_addr=738205696 -cpu_pio_delay=10000 -default_p_state=UNDEFINED -dist_addr=738201600 -dist_pio_delay=10000 -eventq_index=0 -gem5_extensions=true -int_latency=10000 -it_lines=128 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -platform=system.realview -power_model=Null -system=system -pio=system.membus.master[2] - -[system.realview.hdlcd] -type=HDLcd -amba_id=1314816 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=117 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=721420288 -pio_latency=10000 -pixel_buffer_size=2048 -pixel_chunk=32 -power_model=Null -pxl_clk=system.realview.dcc.osc_pxl -system=system -vnc=system.vncserver -workaround_dma_line_count=true -workaround_swap_rb=true -dma=system.membus.slave[0] -pio=system.iobus.master[6] - -[system.realview.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=2 -InterruptPin=2 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.cf0 -eventq_index=0 -host=system.realview.pci_host -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[3] -pio=system.iobus.master[23] - -[system.realview.kmi0] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=44 -is_mouse=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470155264 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[7] - -[system.realview.kmi1] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=45 -is_mouse=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470220800 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[8] - -[system.realview.l2x0_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=739246080 -pio_latency=100000 -pio_size=4095 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.realview.lan_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=436207616 -pio_latency=100000 -pio_size=65535 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.realview.local_cpu_timer] -type=CpuLocalTimer -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num_timer=29 -int_num_watchdog=30 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=738721792 -pio_latency=100000 -power_model=Null -system=system -pio=system.membus.master[4] - -[system.realview.mcc] -type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl -eventq_index=0 -thermal_domain=Null - -[system.realview.mcc.osc_clcd] -type=RealViewOsc -dcc=0 -device=1 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_mcc] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_peripheral] -type=RealViewOsc -dcc=0 -device=2 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_system_bus] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.temp_crtl] -type=RealViewTemperatureSensor -dcc=0 -device=0 -eventq_index=0 -parent=system.realview.realview_io -position=0 -site=0 -system=system - -[system.realview.mmc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470089728 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.realview.nvmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:67108863 -port=system.membus.master[1] - -[system.realview.pci_host] -type=GenericPciHost -clk_domain=system.clk_domain -conf_base=805306368 -conf_device_bits=16 -conf_size=268435456 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=0 -pci_pio_base=0 -platform=system.realview -power_model=Null -system=system -pio=system.iobus.master[2] - -[system.realview.realview_io] -type=RealViewCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -idreg=35979264 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469827584 -pio_latency=100000 -power_model=Null -proc_id0=335544320 -proc_id1=335544320 -system=system -pio=system.iobus.master[1] - -[system.realview.rtc] -type=PL031 -amba_id=3412017 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=36 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471269376 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[10] - -[system.realview.sp810_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469893120 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[16] - -[system.realview.timer0] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=34 -int_num1=34 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470876160 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[3] - -[system.realview.timer1] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=35 -int_num1=35 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470941696 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[4] - -[system.realview.uart] -type=Pl011 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -end_on_eot=false -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=37 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470351872 -pio_latency=100000 -platform=system.realview -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[0] - -[system.realview.uart1_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470417408 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[13] - -[system.realview.uart2_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470482944 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[14] - -[system.realview.uart3_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470548480 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[15] - -[system.realview.usb_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=452984832 -pio_latency=100000 -pio_size=131071 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.realview.vgic] -type=VGic -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -hv_addr=738213888 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_delay=10000 -platform=system.realview -power_model=Null -ppint=25 -system=system -vcpu_addr=738222080 -pio=system.membus.master[3] - -[system.realview.vram] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=402653184:436207615 -port=system.iobus.master[11] - -[system.realview.watchdog_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470745088 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[17] - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.vncserver] -type=VncServer -eventq_index=0 -frame_capture=false -number=0 -port=5900 - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json deleted file mode 100644 index b4e2b05ca..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json +++ /dev/null @@ -1,2038 +0,0 @@ -{ - "name": null, - "sim_quantum": 0, - "system": { - "have_virtualization": false, - "mmap_using_noreserve": false, - "kernel_addr_check": true, - "highest_el_is_64": false, - "kernel": "/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5", - "iobus": { - "forward_latency": 1, - "slave": { - "peer": [ - "system.bridge.master", - "system.realview.clcd.dma", - "system.realview.cf_ctrl.dma", - "system.realview.ide.dma", - "system.realview.ethernet.dma" - ], - "role": "SLAVE" - }, - "name": "iobus", - "p_state_clk_gate_min": 1000, - "p_state_clk_gate_bins": 20, - "cxx_class": "NoncoherentXBar", - "clk_domain": "system.clk_domain", - "power_model": null, - "width": 16, - "eventq_index": 0, - "master": { - "peer": [ - "system.realview.uart.pio", - "system.realview.realview_io.pio", - "system.realview.pci_host.pio", - "system.realview.timer0.pio", - "system.realview.timer1.pio", - "system.realview.clcd.pio", - "system.realview.hdlcd.pio", - "system.realview.kmi0.pio", - "system.realview.kmi1.pio", - "system.realview.cf_ctrl.pio", - "system.realview.rtc.pio", - "system.realview.vram.port", - "system.realview.l2x0_fake.pio", - "system.realview.uart1_fake.pio", - "system.realview.uart2_fake.pio", - "system.realview.uart3_fake.pio", - "system.realview.sp810_fake.pio", - "system.realview.watchdog_fake.pio", - "system.realview.aaci_fake.pio", - "system.realview.lan_fake.pio", - "system.realview.usb_fake.pio", - "system.realview.mmc_fake.pio", - "system.realview.energy_ctrl.pio", - "system.realview.ide.pio", - "system.realview.ethernet.pio", - "system.iocache.cpu_side" - ], - "role": "MASTER" - }, - "response_latency": 2, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.iobus", - "type": "NoncoherentXBar", - "use_default_range": false, - "frontend_latency": 2 - }, - "symbolfile": "", - "readfile": "/work/curdun01/gem5-external.hg/tests/testing/../halt.sh", - "have_large_asid_64": false, - "thermal_model": null, - "phys_addr_range_64": 40, - "work_begin_exit_count": 0, - "have_lpae": true, - "cxx_class": "LinuxArmSystem", - "work_begin_cpu_id_exit": -1, - "load_offset": 2147483648, - "vncserver": { - "name": "vncserver", - "number": 0, - "frame_capture": false, - "eventq_index": 0, - "cxx_class": "VncServer", - "path": "system.vncserver", - "type": "VncServer", - "port": 5900 - }, - "multi_proc": true, - "bridge": { - "ranges": [ - "788529152:805306367", - "721420288:725614591", - "805306368:1073741823", - "1073741824:1610612735", - "402653184:469762047", - "469762048:536870911" - ], - "slave": { - "peer": "system.membus.master[0]", - "role": "SLAVE" - }, - "name": "bridge", - "p_state_clk_gate_min": 1000, - "p_state_clk_gate_bins": 20, - "cxx_class": "Bridge", - "req_size": 16, - "clk_domain": "system.clk_domain", - "power_model": null, - "delay": 50000, - "eventq_index": 0, - "master": { - "peer": "system.iobus.slave[0]", - "role": "MASTER" - }, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.bridge", - "resp_size": 16, - "type": "Bridge" - }, - "early_kernel_symbols": false, - "panic_on_oops": true, - "dtb_filename": "/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb", - "panic_on_panic": true, - "enable_context_switch_stats_dump": false, - "work_begin_ckpt_count": 0, - "clk_domain": { - "name": "clk_domain", - "clock": [ - 1000 - ], - "init_perf_level": 0, - "voltage_domain": "system.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "mem_ranges": [ - "2147483648:2415919103" - ], - "realview": { - "hdlcd": { - "pio": { - "peer": "system.iobus.master[6]", - "role": "SLAVE" - }, - "system": "system", - "cxx_class": "HDLcd", - "enable_capture": true, - "pio_addr": 721420288, - "pixel_chunk": 32, - "pio_latency": 10000, - "clk_domain": "system.clk_domain", - "int_num": 117, - "gic": "system.realview.gic", - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "eventq_index": 0, - "pxl_clk": "system.realview.dcc.osc_pxl", - "type": "HDLcd", - "vnc": "system.vncserver", - "p_state_clk_gate_min": 1000, - "power_model": null, - "workaround_dma_line_count": true, - "pixel_buffer_size": 2048, - "path": "system.realview.hdlcd", - "workaround_swap_rb": true, - "dma": { - "peer": "system.membus.slave[0]", - "role": "MASTER" - }, - "name": "hdlcd", - "p_state_clk_gate_bins": 20, - "amba_id": 1314816 - }, - "mmc_fake": { - "p_state_clk_gate_bins": 20, - "name": "mmc_fake", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[21]", - "role": "SLAVE" - }, - "amba_id": 0, - "ignore_access": false, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "cxx_class": "AmbaFake", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.mmc_fake", - "pio_addr": 470089728, - "type": "AmbaFake" - }, - "rtc": { - "p_state_clk_gate_min": 1000, - "p_state_clk_gate_bins": 20, - "name": "rtc", - "int_delay": 100000, - "pio": { - "peer": "system.iobus.master[10]", - "role": "SLAVE" - }, - "amba_id": 3412017, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "gic": "system.realview.gic", - "int_num": 36, - "eventq_index": 0, - "time": "Thu Jan 1 00:00:00 2009", - "cxx_class": "PL031", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.rtc", - "pio_addr": 471269376, - "type": "PL031" - }, - "watchdog_fake": { - "p_state_clk_gate_bins": 20, - "name": "watchdog_fake", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[17]", - "role": "SLAVE" - }, - "amba_id": 0, - "ignore_access": false, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "cxx_class": "AmbaFake", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.watchdog_fake", - "pio_addr": 470745088, - "type": "AmbaFake" - }, - "vgic": { - "system": "system", - "name": "vgic", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.membus.master[3]", - "role": "SLAVE" - }, - "p_state_clk_gate_bins": 20, - "cxx_class": "VGic", - "clk_domain": "system.clk_domain", - "power_model": null, - "hv_addr": 738213888, - "gic": "system.realview.gic", - "platform": "system.realview", - "vcpu_addr": 738222080, - "eventq_index": 0, - "ppint": 25, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.vgic", - "type": "VGic", - "pio_delay": 10000 - }, - "cxx_class": "RealView", - "uart3_fake": { - "p_state_clk_gate_bins": 20, - "name": "uart3_fake", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[15]", - "role": "SLAVE" - }, - "amba_id": 0, - "ignore_access": false, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "cxx_class": "AmbaFake", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.uart3_fake", - "pio_addr": 470548480, - "type": "AmbaFake" - }, - "realview_io": { - "proc_id1": 335544320, - "name": "realview_io", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[1]", - "role": "SLAVE" - }, - "p_state_clk_gate_bins": 20, - "cxx_class": "RealViewCtrl", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "proc_id0": 335544320, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.realview_io", - "idreg": 35979264, - "type": "RealViewCtrl", - "pio_addr": 469827584 - }, - "l2x0_fake": { - "pio": { - "peer": "system.iobus.master[12]", - "role": "SLAVE" - }, - "ret_data64": 18446744073709551615, - "fake_mem": false, - "clk_domain": "system.clk_domain", - "cxx_class": "IsaFake", - "pio_addr": 739246080, - "update_data": false, - "warn_access": "", - "pio_latency": 100000, - "system": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "type": "IsaFake", - "p_state_clk_gate_min": 1000, - "power_model": null, - "ret_data32": 4294967295, - "path": "system.realview.l2x0_fake", - "ret_data16": 65535, - "ret_data8": 255, - "name": "l2x0_fake", - "ret_bad_addr": false, - "pio_size": 4095, - "p_state_clk_gate_bins": 20 - }, - "uart1_fake": { - "p_state_clk_gate_bins": 20, - "name": "uart1_fake", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[13]", - "role": "SLAVE" - }, - "amba_id": 0, - "ignore_access": false, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "cxx_class": "AmbaFake", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.uart1_fake", - "pio_addr": 470417408, - "type": "AmbaFake" - }, - "usb_fake": { - "pio": { - "peer": "system.iobus.master[20]", - "role": "SLAVE" - }, - "ret_data64": 18446744073709551615, - "fake_mem": false, - "clk_domain": "system.clk_domain", - "cxx_class": "IsaFake", - "pio_addr": 452984832, - "update_data": false, - "warn_access": "", - "pio_latency": 100000, - "system": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "type": "IsaFake", - "p_state_clk_gate_min": 1000, - "power_model": null, - "ret_data32": 4294967295, - "path": "system.realview.usb_fake", - "ret_data16": 65535, - "ret_data8": 255, - "name": "usb_fake", - "ret_bad_addr": false, - "pio_size": 131071, - "p_state_clk_gate_bins": 20 - }, - "system": "system", - "local_cpu_timer": { - "int_num_watchdog": 30, - "name": "local_cpu_timer", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.membus.master[4]", - "role": "SLAVE" - }, - "p_state_clk_gate_bins": 20, - "cxx_class": "CpuLocalTimer", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "gic": "system.realview.gic", - "int_num_timer": 29, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.local_cpu_timer", - "pio_addr": 738721792, - "type": "CpuLocalTimer" - }, - "generic_timer": { - "int_virt": 27, - "name": "generic_timer", - "int_phys": 29, - "cxx_class": "GenericTimer", - "system": "system", - "eventq_index": 0, - "gic": "system.realview.gic", - "path": "system.realview.generic_timer", - "type": "GenericTimer" - }, - "gic": { - "gem5_extensions": true, - "it_lines": 128, - "dist_pio_delay": 10000, - "name": "gic", - "p_state_clk_gate_min": 1000, - "dist_addr": 738201600, - "p_state_clk_gate_bins": 20, - "cpu_pio_delay": 10000, - "default_p_state": "UNDEFINED", - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "cpu_addr": 738205696, - "platform": "system.realview", - "int_latency": 10000, - "eventq_index": 0, - "cxx_class": "Pl390", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.gic", - "pio": { - "peer": "system.membus.master[2]", - "role": "SLAVE" - }, - "type": "Pl390" - }, - "timer1": { - "p_state_clk_gate_bins": 20, - "name": "timer1", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[4]", - "role": "SLAVE" - }, - "amba_id": 1316868, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "clock0": 1000000, - "clock1": 1000000, - "gic": "system.realview.gic", - "eventq_index": 0, - "cxx_class": "Sp804", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.timer1", - "int_num0": 35, - "int_num1": 35, - "type": "Sp804", - "pio_addr": 470941696 - }, - "timer0": { - "p_state_clk_gate_bins": 20, - "name": "timer0", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[3]", - "role": "SLAVE" - }, - "amba_id": 1316868, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "clock0": 1000000, - "clock1": 1000000, - "gic": "system.realview.gic", - "eventq_index": 0, - "cxx_class": "Sp804", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.timer0", - "int_num0": 34, - "int_num1": 34, - "type": "Sp804", - "pio_addr": 470876160 - }, - "uart2_fake": { - "p_state_clk_gate_bins": 20, - "name": "uart2_fake", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[14]", - "role": "SLAVE" - }, - "amba_id": 0, - "ignore_access": false, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "cxx_class": "AmbaFake", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.uart2_fake", - "pio_addr": 470482944, - "type": "AmbaFake" - }, - "eventq_index": 0, - "energy_ctrl": { - "name": "energy_ctrl", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[22]", - "role": "SLAVE" - }, - "p_state_clk_gate_bins": 20, - "cxx_class": "EnergyCtrl", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.energy_ctrl", - "dvfs_handler": "system.dvfs_handler", - "type": "EnergyCtrl", - "pio_addr": 470286336 - }, - "type": "RealView", - "pci_host": { - "p_state_clk_gate_min": 1000, - "default_p_state": "UNDEFINED", - "conf_size": 268435456, - "name": "pci_host", - "conf_device_bits": 16, - "pio": { - "peer": "system.iobus.master[2]", - "role": "SLAVE" - }, - "p_state_clk_gate_bins": 20, - "conf_base": 805306368, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "pci_dma_base": 0, - "platform": "system.realview", - "eventq_index": 0, - "cxx_class": "GenericPciHost", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.pci_host", - "pci_pio_base": 0, - "type": "GenericPciHost", - "pci_mem_base": 0 - }, - "lan_fake": { - "pio": { - "peer": "system.iobus.master[19]", - "role": "SLAVE" - }, - "ret_data64": 18446744073709551615, - "fake_mem": false, - "clk_domain": "system.clk_domain", - "cxx_class": "IsaFake", - "pio_addr": 436207616, - "update_data": false, - "warn_access": "", - "pio_latency": 100000, - "system": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "type": "IsaFake", - "p_state_clk_gate_min": 1000, - "power_model": null, - "ret_data32": 4294967295, - "path": "system.realview.lan_fake", - "ret_data16": 65535, - "ret_data8": 255, - "name": "lan_fake", - "ret_bad_addr": false, - "pio_size": 65535, - "p_state_clk_gate_bins": 20 - }, - "aaci_fake": { - "p_state_clk_gate_bins": 20, - "name": "aaci_fake", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[18]", - "role": "SLAVE" - }, - "amba_id": 0, - "ignore_access": false, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "cxx_class": "AmbaFake", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.aaci_fake", - "pio_addr": 470024192, - "type": "AmbaFake" - }, - "mcc": { - "osc_peripheral": { - "position": 0, - "name": "osc_peripheral", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 0, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 2, - "path": "system.realview.mcc.osc_peripheral", - "freq": 41667, - "type": "RealViewOsc" - }, - "name": "mcc", - "osc_mcc": { - "position": 0, - "name": "osc_mcc", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 0, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 0, - "path": "system.realview.mcc.osc_mcc", - "freq": 20000, - "type": "RealViewOsc" - }, - "osc_clcd": { - "position": 0, - "name": "osc_clcd", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 0, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 1, - "path": "system.realview.mcc.osc_clcd", - "freq": 42105, - "type": "RealViewOsc" - }, - "thermal_domain": null, - "eventq_index": 0, - "cxx_class": "SubSystem", - "path": "system.realview.mcc", - "temp_crtl": { - "system": "system", - "position": 0, - "name": "temp_crtl", - "parent": "system.realview.realview_io", - "dcc": 0, - "site": 0, - "eventq_index": 0, - "cxx_class": "RealViewTemperatureSensor", - "device": 0, - "path": "system.realview.mcc.temp_crtl", - "type": "RealViewTemperatureSensor" - }, - "type": "SubSystem", - "osc_system_bus": { - "position": 0, - "name": "osc_system_bus", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 0, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 4, - "path": "system.realview.mcc.osc_system_bus", - "freq": 41667, - "type": "RealViewOsc" - } - }, - "dcc": { - "name": "dcc", - "osc_hsbm": { - "position": 0, - "name": "osc_hsbm", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 1, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 4, - "path": "system.realview.dcc.osc_hsbm", - "freq": 25000, - "type": "RealViewOsc" - }, - "thermal_domain": null, - "osc_sys": { - "position": 0, - "name": "osc_sys", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 1, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 7, - "path": "system.realview.dcc.osc_sys", - "freq": 16667, - "type": "RealViewOsc" - }, - "osc_ddr": { - "position": 0, - "name": "osc_ddr", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 1, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 8, - "path": "system.realview.dcc.osc_ddr", - "freq": 25000, - "type": "RealViewOsc" - }, - "eventq_index": 0, - "osc_cpu": { - "position": 0, - "name": "osc_cpu", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 1, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 0, - "path": "system.realview.dcc.osc_cpu", - "freq": 16667, - "type": "RealViewOsc" - }, - "cxx_class": "SubSystem", - "path": "system.realview.dcc", - "osc_smb": { - "position": 0, - "name": "osc_smb", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 1, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 6, - "path": "system.realview.dcc.osc_smb", - "freq": 20000, - "type": "RealViewOsc" - }, - "type": "SubSystem", - "osc_pxl": { - "position": 0, - "name": "osc_pxl", - "parent": "system.realview.realview_io", - "voltage_domain": "system.voltage_domain", - "dcc": 0, - "site": 1, - "eventq_index": 0, - "cxx_class": "RealViewOsc", - "device": 5, - "path": "system.realview.dcc.osc_pxl", - "freq": 42105, - "type": "RealViewOsc" - } - }, - "path": "system.realview", - "vram": { - "range": "402653184:436207615", - "latency": 30000, - "name": "vram", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.clk_domain", - "power_model": null, - "latency_var": 0, - "bandwidth": "73.000000", - "conf_table_reported": false, - "cxx_class": "SimpleMemory", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.vram", - "null": false, - "type": "SimpleMemory", - "port": { - "peer": "system.iobus.master[11]", - "role": "SLAVE" - }, - "in_addr_map": true - }, - "nvmem": { - "range": "0:67108863", - "latency": 30000, - "name": "nvmem", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.clk_domain", - "power_model": null, - "latency_var": 0, - "bandwidth": "73.000000", - "conf_table_reported": false, - "cxx_class": "SimpleMemory", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.nvmem", - "null": false, - "type": "SimpleMemory", - "port": { - "peer": "system.membus.master[1]", - "role": "SLAVE" - }, - "in_addr_map": true - }, - "clcd": { - "pio": { - "peer": "system.iobus.master[5]", - "role": "SLAVE" - }, - "system": "system", - "cxx_class": "Pl111", - "enable_capture": true, - "pio_addr": 471793664, - "pio_latency": 10000, - "clk_domain": "system.clk_domain", - "int_num": 46, - "gic": "system.realview.gic", - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "eventq_index": 0, - "type": "Pl111", - "vnc": "system.vncserver", - "p_state_clk_gate_min": 1000, - "power_model": null, - "path": "system.realview.clcd", - "dma": { - "peer": "system.iobus.slave[1]", - "role": "MASTER" - }, - "name": "clcd", - "p_state_clk_gate_bins": 20, - "pixel_clock": 41667, - "amba_id": 1315089 - }, - "name": "realview", - "uart": { - "p_state_clk_gate_min": 1000, - "terminal": "system.terminal", - "pio": { - "peer": "system.iobus.master[0]", - "role": "SLAVE" - }, - "name": "uart", - "int_delay": 100000, - "platform": "system.realview", - "p_state_clk_gate_bins": 20, - "cxx_class": "Pl011", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "gic": "system.realview.gic", - "int_num": 37, - "eventq_index": 0, - "end_on_eot": false, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.uart", - "pio_addr": 470351872, - "type": "Pl011" - }, - "intrctrl": "system.intrctrl", - "kmi1": { - "p_state_clk_gate_min": 1000, - "p_state_clk_gate_bins": 20, - "vnc": "system.vncserver", - "name": "kmi1", - "int_delay": 1000000, - "pio": { - "peer": "system.iobus.master[8]", - "role": "SLAVE" - }, - "amba_id": 1314896, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "gic": "system.realview.gic", - "int_num": 45, - "eventq_index": 0, - "is_mouse": true, - "cxx_class": "Pl050", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.kmi1", - "pio_addr": 470220800, - "type": "Pl050" - }, - "kmi0": { - "p_state_clk_gate_min": 1000, - "p_state_clk_gate_bins": 20, - "vnc": "system.vncserver", - "name": "kmi0", - "int_delay": 1000000, - "pio": { - "peer": "system.iobus.master[7]", - "role": "SLAVE" - }, - "amba_id": 1314896, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "gic": "system.realview.gic", - "int_num": 44, - "eventq_index": 0, - "is_mouse": false, - "cxx_class": "Pl050", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.kmi0", - "pio_addr": 470155264, - "type": "Pl050" - }, - "cf_ctrl": { - "PMCAPNextCapability": 0, - "InterruptPin": 1, - "HeaderType": 0, - "VendorID": 32902, - "MSIXMsgCtrl": 0, - "MSIXCAPNextCapability": 0, - "PXCAPLinkCtrl": 0, - "Revision": 0, - "LegacyIOBase": 0, - "pio_latency": 30000, - "PXCAPLinkCap": 0, - "CapabilityPtr": 0, - "MSIXCAPBaseOffset": 0, - "PXCAPDevCapabilities": 0, - "MSIXCAPCapId": 0, - "BAR3Size": 4, - "power_model": null, - "PXCAPCapabilities": 0, - "SubsystemID": 0, - "PXCAPCapId": 0, - "BAR4": 1, - "BAR1": 471466240, - "BAR0": 471465984, - "BAR3": 1, - "BAR2": 1, - "BAR5": 1, - "PXCAPDevStatus": 0, - "disks": [], - "BAR2Size": 8, - "MSICAPNextCapability": 0, - "ExpansionROM": 0, - "MSICAPMsgCtrl": 0, - "BAR5Size": 0, - "CardbusCIS": 0, - "MSIXPbaOffset": 0, - "MSICAPBaseOffset": 0, - "MaximumLatency": 0, - "BAR2LegacyIO": false, - "LatencyTimer": 0, - "BAR4LegacyIO": false, - "p_state_clk_gate_max": 1000000000000, - "PXCAPLinkStatus": 0, - "PXCAPDevCap2": 0, - "p_state_clk_gate_min": 1000, - "PXCAPDevCtrl": 0, - "MSICAPMaskBits": 0, - "host": "system.realview.pci_host", - "Command": 1, - "SubClassCode": 1, - "pci_func": 0, - "BAR5LegacyIO": false, - "MSICAPMsgData": 0, - "BIST": 0, - "PXCAPDevCtrl2": 0, - "pci_bus": 2, - "InterruptLine": 31, - "MSICAPMsgAddr": 0, - "BAR3LegacyIO": false, - "BAR4Size": 16, - "path": "system.realview.cf_ctrl", - "MinimumGrant": 0, - "Status": 640, - "BAR0Size": 256, - "system": "system", - "name": "cf_ctrl", - "PXCAPNextCapability": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "type": "IdeController", - "ctrl_offset": 2, - "PXCAPBaseOffset": 0, - "DeviceID": 28945, - "io_shift": 2, - "CacheLineSize": 0, - "dma": { - "peer": "system.iobus.slave[2]", - "role": "MASTER" - }, - "PMCAPCapId": 0, - "config_latency": 20000, - "BAR1Size": 4096, - "pio": { - "peer": "system.iobus.master[9]", - "role": "SLAVE" - }, - "pci_dev": 0, - "PMCAPCtrlStatus": 0, - "cxx_class": "IdeController", - "clk_domain": "system.clk_domain", - "SubsystemVendorID": 0, - "PMCAPBaseOffset": 0, - "MSICAPPendingBits": 0, - "MSIXTableOffset": 0, - "MSICAPMsgUpperAddr": 0, - "MSICAPCapId": 0, - "BAR0LegacyIO": true, - "ProgIF": 133, - "BAR1LegacyIO": true, - "PMCAPCapabilities": 0, - "ClassCode": 1, - "p_state_clk_gate_bins": 20 - }, - "sp810_fake": { - "p_state_clk_gate_bins": 20, - "name": "sp810_fake", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.iobus.master[16]", - "role": "SLAVE" - }, - "amba_id": 0, - "ignore_access": true, - "default_p_state": "UNDEFINED", - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "power_model": null, - "system": "system", - "eventq_index": 0, - "cxx_class": "AmbaFake", - "p_state_clk_gate_max": 1000000000000, - "path": "system.realview.sp810_fake", - "pio_addr": 469893120, - "type": "AmbaFake" - }, - "ethernet": { - "PMCAPNextCapability": 0, - "InterruptPin": 1, - "HeaderType": 0, - "VendorID": 32902, - "MSIXMsgCtrl": 0, - "MSIXCAPNextCapability": 0, - "PXCAPLinkCtrl": 0, - "Revision": 0, - "hardware_address": "00:90:00:00:00:01", - "LegacyIOBase": 0, - "pio_latency": 30000, - "PXCAPLinkCap": 0, - "CapabilityPtr": 0, - "MSIXCAPBaseOffset": 0, - "PXCAPDevCapabilities": 0, - "MSIXCAPCapId": 0, - "BAR3Size": 0, - "rx_desc_cache_size": 64, - "power_model": null, - "PXCAPCapabilities": 0, - "SubsystemID": 4104, - "PXCAPCapId": 0, - "BAR4": 0, - "BAR1": 0, - "BAR0": 0, - "BAR3": 0, - "BAR2": 0, - "BAR5": 0, - "PXCAPDevStatus": 0, - "BAR2Size": 0, - "MSICAPNextCapability": 0, - "ExpansionROM": 0, - "rx_write_delay": 0, - "MSICAPMsgCtrl": 0, - "BAR5Size": 0, - "CardbusCIS": 0, - "MSIXPbaOffset": 0, - "MSICAPBaseOffset": 0, - "MaximumLatency": 0, - "BAR2LegacyIO": false, - "LatencyTimer": 0, - "BAR4LegacyIO": false, - "p_state_clk_gate_max": 1000000000000, - "PXCAPLinkStatus": 0, - "PXCAPDevCap2": 0, - "p_state_clk_gate_min": 1000, - "PXCAPDevCtrl": 0, - "MSICAPMaskBits": 0, - "host": "system.realview.pci_host", - "Command": 0, - "SubClassCode": 0, - "pci_func": 0, - "BAR5LegacyIO": false, - "MSICAPMsgData": 0, - "BIST": 0, - "PXCAPDevCtrl2": 0, - "pci_bus": 0, - "InterruptLine": 1, - "fetch_delay": 10000, - "MSICAPMsgAddr": 0, - "BAR3LegacyIO": false, - "BAR4Size": 0, - "path": "system.realview.ethernet", - "MinimumGrant": 255, - "phy_epid": 896, - "Status": 0, - "BAR0Size": 131072, - "system": "system", - "name": "ethernet", - "PXCAPNextCapability": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "type": "IGbE", - "tx_fifo_size": 393216, - "PXCAPBaseOffset": 0, - "DeviceID": 4213, - "tx_read_delay": 0, - "CacheLineSize": 0, - "dma": { - "peer": "system.iobus.slave[4]", - "role": "MASTER" - }, - "PMCAPCapId": 0, - "tx_desc_cache_size": 64, - "config_latency": 20000, - "BAR1Size": 0, - "pio": { - "peer": "system.iobus.master[24]", - "role": "SLAVE" - }, - "pci_dev": 0, - "PMCAPCtrlStatus": 0, - "cxx_class": "IGbE", - "wb_delay": 10000, - "fetch_comp_delay": 10000, - "clk_domain": "system.clk_domain", - "SubsystemVendorID": 32902, - "PMCAPBaseOffset": 0, - "MSICAPPendingBits": 0, - "MSIXTableOffset": 0, - "MSICAPMsgUpperAddr": 0, - "MSICAPCapId": 0, - "BAR0LegacyIO": false, - "ProgIF": 0, - "BAR1LegacyIO": false, - "wb_comp_delay": 10000, - "PMCAPCapabilities": 0, - "ClassCode": 2, - "p_state_clk_gate_bins": 20, - "rx_fifo_size": 393216, - "phy_pid": 680 - }, - "ide": { - "PMCAPNextCapability": 0, - "InterruptPin": 2, - "HeaderType": 0, - "VendorID": 32902, - "MSIXMsgCtrl": 0, - "MSIXCAPNextCapability": 0, - "PXCAPLinkCtrl": 0, - "Revision": 0, - "LegacyIOBase": 0, - "pio_latency": 30000, - "PXCAPLinkCap": 0, - "CapabilityPtr": 0, - "MSIXCAPBaseOffset": 0, - "PXCAPDevCapabilities": 0, - "MSIXCAPCapId": 0, - "BAR3Size": 4, - "power_model": null, - "PXCAPCapabilities": 0, - "SubsystemID": 0, - "PXCAPCapId": 0, - "BAR4": 1, - "BAR1": 1, - "BAR0": 1, - "BAR3": 1, - "BAR2": 1, - "BAR5": 1, - "PXCAPDevStatus": 0, - "disks": [ - "system.cf0" - ], - "BAR2Size": 8, - "MSICAPNextCapability": 0, - "ExpansionROM": 0, - "MSICAPMsgCtrl": 0, - "BAR5Size": 0, - "CardbusCIS": 0, - "MSIXPbaOffset": 0, - "MSICAPBaseOffset": 0, - "MaximumLatency": 0, - "BAR2LegacyIO": false, - "LatencyTimer": 0, - "BAR4LegacyIO": false, - "p_state_clk_gate_max": 1000000000000, - "PXCAPLinkStatus": 0, - "PXCAPDevCap2": 0, - "p_state_clk_gate_min": 1000, - "PXCAPDevCtrl": 0, - "MSICAPMaskBits": 0, - "host": "system.realview.pci_host", - "Command": 0, - "SubClassCode": 1, - "pci_func": 0, - "BAR5LegacyIO": false, - "MSICAPMsgData": 0, - "BIST": 0, - "PXCAPDevCtrl2": 0, - "pci_bus": 0, - "InterruptLine": 2, - "MSICAPMsgAddr": 0, - "BAR3LegacyIO": false, - "BAR4Size": 16, - "path": "system.realview.ide", - "MinimumGrant": 0, - "Status": 640, - "BAR0Size": 8, - "system": "system", - "name": "ide", - "PXCAPNextCapability": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "type": "IdeController", - "ctrl_offset": 0, - "PXCAPBaseOffset": 0, - "DeviceID": 28945, - "io_shift": 0, - "CacheLineSize": 0, - "dma": { - "peer": "system.iobus.slave[3]", - "role": "MASTER" - }, - "PMCAPCapId": 0, - "config_latency": 20000, - "BAR1Size": 4, - "pio": { - "peer": "system.iobus.master[23]", - "role": "SLAVE" - }, - "pci_dev": 1, - "PMCAPCtrlStatus": 0, - "cxx_class": "IdeController", - "clk_domain": "system.clk_domain", - "SubsystemVendorID": 0, - "PMCAPBaseOffset": 0, - "MSICAPPendingBits": 0, - "MSIXTableOffset": 0, - "MSICAPMsgUpperAddr": 0, - "MSICAPCapId": 0, - "BAR0LegacyIO": false, - "ProgIF": 133, - "BAR1LegacyIO": false, - "PMCAPCapabilities": 0, - "ClassCode": 1, - "p_state_clk_gate_bins": 20 - } - }, - "membus": { - "point_of_coherency": true, - "system": "system", - "response_latency": 2, - "cxx_class": "CoherentXBar", - "badaddr_responder": { - "pio": { - "peer": "system.membus.default", - "role": "SLAVE" - }, - "ret_data64": 18446744073709551615, - "fake_mem": false, - "clk_domain": "system.clk_domain", - "cxx_class": "IsaFake", - "pio_addr": 0, - "update_data": false, - "warn_access": "warn", - "pio_latency": 100000, - "system": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "type": "IsaFake", - "p_state_clk_gate_min": 1000, - "power_model": null, - "ret_data32": 4294967295, - "path": "system.membus.badaddr_responder", - "ret_data16": 65535, - "ret_data8": 255, - "name": "badaddr_responder", - "ret_bad_addr": true, - "pio_size": 8, - "p_state_clk_gate_bins": 20 - }, - "forward_latency": 4, - "clk_domain": "system.clk_domain", - "width": 16, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "master": { - "peer": [ - "system.bridge.slave", - "system.realview.nvmem.port", - "system.realview.gic.pio", - "system.realview.vgic.pio", - "system.realview.local_cpu_timer.pio", - "system.physmem.port" - ], - "role": "MASTER" - }, - "type": "CoherentXBar", - "frontend_latency": 3, - "slave": { - "peer": [ - "system.realview.hdlcd.dma", - "system.system_port", - "system.cpu.l2cache.mem_side", - "system.iocache.mem_side" - ], - "role": "SLAVE" - }, - "p_state_clk_gate_min": 1000, - "snoop_filter": null, - "power_model": null, - "path": "system.membus", - "snoop_response_latency": 4, - "name": "membus", - "default": { - "peer": "system.membus.badaddr_responder.pio", - "role": "MASTER" - }, - "p_state_clk_gate_bins": 20, - "use_default_range": false - }, - "multi_thread": false, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "iocache": { - "cpu_side": { - "peer": "system.iobus.master[25]", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": null, - "system": "system", - "write_buffers": 8, - "response_latency": 50, - "cxx_class": "Cache", - "size": 1024, - "tags": { - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.clk_domain", - "power_model": null, - "sequential_access": false, - "assoc": 8, - "cxx_class": "LRU", - "p_state_clk_gate_max": 1000000000000, - "path": "system.iocache.tags", - "hit_latency": 50, - "block_size": 64, - "type": "LRU", - "size": 1024 - }, - "clk_domain": "system.clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.membus.slave[3]", - "role": "MASTER" - }, - "type": "Cache", - "writeback_clean": false, - "p_state_clk_gate_min": 1000, - "hit_latency": 50, - "tgts_per_mshr": 12, - "demand_mshr_reserve": 1, - "power_model": null, - "addr_ranges": [ - "2147483648:2415919103" - ], - "is_read_only": false, - "prefetch_on_access": false, - "path": "system.iocache", - "mshrs": 20, - "name": "iocache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 8 - }, - "dvfs_handler": { - "enable": false, - "name": "dvfs_handler", - "sys_clk_domain": "system.clk_domain", - "transition_latency": 100000000, - "eventq_index": 0, - "cxx_class": "DVFSHandler", - "domains": [], - "path": "system.dvfs_handler", - "type": "DVFSHandler" - }, - "work_end_exit_count": 0, - "type": "LinuxArmSystem", - "p_state_clk_gate_min": 1000, - "voltage_domain": { - "name": "voltage_domain", - "eventq_index": 0, - "voltage": [ - "1.0" - ], - "cxx_class": "VoltageDomain", - "path": "system.voltage_domain", - "type": "VoltageDomain" - }, - "cache_line_size": 64, - "boot_osflags": "earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1", - "system_port": { - "peer": "system.membus.slave[1]", - "role": "MASTER" - }, - "physmem": [ - { - "range": "2147483648:2415919103", - "latency": 30000, - "name": "physmem", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.clk_domain", - "power_model": null, - "latency_var": 0, - "bandwidth": "73.000000", - "conf_table_reported": true, - "cxx_class": "SimpleMemory", - "p_state_clk_gate_max": 1000000000000, - "path": "system.physmem", - "null": false, - "type": "SimpleMemory", - "port": { - "peer": "system.membus.master[5]", - "role": "SLAVE" - }, - "in_addr_map": true - } - ], - "terminal": { - "name": "terminal", - "output": true, - "number": 0, - "intr_control": "system.intrctrl", - "eventq_index": 0, - "cxx_class": "Terminal", - "path": "system.terminal", - "type": "Terminal", - "port": 3456 - }, - "power_model": null, - "reset_addr_64": 0, - "cpu": [ - { - "do_statistics_insts": true, - "numThreads": 1, - "itb": { - "name": "itb", - "is_stage2": false, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "p_state_clk_gate_min": 1000, - "name": "walker", - "is_stage2": false, - "p_state_clk_gate_bins": 20, - "cxx_class": "ArmISA::TableWalker", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sys": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.itb.walker", - "type": "ArmTableWalker", - "port": { - "peer": "system.cpu.toL2Bus.slave[2]", - "role": "MASTER" - }, - "num_squash_per_cycle": 2 - }, - "path": "system.cpu.itb", - "type": "ArmTLB", - "size": 64 - }, - "simulate_data_stalls": false, - "istage2_mmu": { - "name": "istage2_mmu", - "tlb": "system.cpu.itb", - "sys": "system", - "stage2_tlb": { - "name": "stage2_tlb", - "is_stage2": true, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "p_state_clk_gate_min": 1000, - "name": "walker", - "is_stage2": true, - "p_state_clk_gate_bins": 20, - "cxx_class": "ArmISA::TableWalker", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sys": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.istage2_mmu.stage2_tlb.walker", - "type": "ArmTableWalker", - "num_squash_per_cycle": 2 - }, - "path": "system.cpu.istage2_mmu.stage2_tlb", - "type": "ArmTLB", - "size": 32 - }, - "eventq_index": 0, - "cxx_class": "ArmISA::Stage2MMU", - "path": "system.cpu.istage2_mmu", - "type": "ArmStage2MMU" - }, - "icache": { - "cpu_side": { - "peer": "system.cpu.icache_port", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": null, - "system": "system", - "write_buffers": 8, - "response_latency": 2, - "cxx_class": "Cache", - "size": 32768, - "tags": { - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sequential_access": false, - "assoc": 1, - "cxx_class": "LRU", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.icache.tags", - "hit_latency": 2, - "block_size": 64, - "type": "LRU", - "size": 32768 - }, - "clk_domain": "system.cpu_clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.cpu.toL2Bus.slave[0]", - "role": "MASTER" - }, - "type": "Cache", - "writeback_clean": true, - "p_state_clk_gate_min": 1000, - "hit_latency": 2, - "tgts_per_mshr": 20, - "demand_mshr_reserve": 1, - "power_model": null, - "addr_ranges": [ - "0:18446744073709551615" - ], - "is_read_only": true, - "prefetch_on_access": false, - "path": "system.cpu.icache", - "mshrs": 4, - "name": "icache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 1 - }, - "function_trace": false, - "do_checkpoint_insts": true, - "cxx_class": "AtomicSimpleCPU", - "max_loads_all_threads": 0, - "system": "system", - "clk_domain": "system.cpu_clk_domain", - "function_trace_start": 0, - "cpu_id": 0, - "width": 1, - "checker": null, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "toL2Bus": { - "point_of_coherency": false, - "system": "system", - "response_latency": 1, - "cxx_class": "CoherentXBar", - "forward_latency": 0, - "clk_domain": "system.cpu_clk_domain", - "width": 32, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "master": { - "peer": [ - "system.cpu.l2cache.cpu_side" - ], - "role": "MASTER" - }, - "type": "CoherentXBar", - "frontend_latency": 1, - "slave": { - "peer": [ - "system.cpu.icache.mem_side", - "system.cpu.dcache.mem_side", - "system.cpu.itb.walker.port", - "system.cpu.dtb.walker.port" - ], - "role": "SLAVE" - }, - "p_state_clk_gate_min": 1000, - "snoop_filter": { - "name": "snoop_filter", - "system": "system", - "max_capacity": 8388608, - "eventq_index": 0, - "cxx_class": "SnoopFilter", - "path": "system.cpu.toL2Bus.snoop_filter", - "type": "SnoopFilter", - "lookup_latency": 0 - }, - "power_model": null, - "path": "system.cpu.toL2Bus", - "snoop_response_latency": 1, - "name": "toL2Bus", - "p_state_clk_gate_bins": 20, - "use_default_range": false - }, - "do_quiesce": true, - "type": "AtomicSimpleCPU", - "fastmem": false, - "profile": 0, - "icache_port": { - "peer": "system.cpu.icache.cpu_side", - "role": "MASTER" - }, - "p_state_clk_gate_bins": 20, - "p_state_clk_gate_min": 1000, - "interrupts": [ - { - "eventq_index": 0, - "path": "system.cpu.interrupts", - "type": "ArmInterrupts", - "name": "interrupts", - "cxx_class": "ArmISA::Interrupts" - } - ], - "dcache_port": { - "peer": "system.cpu.dcache.cpu_side", - "role": "MASTER" - }, - "socket_id": 0, - "power_model": null, - "max_insts_all_threads": 0, - "dstage2_mmu": { - "name": "dstage2_mmu", - "tlb": "system.cpu.dtb", - "sys": "system", - "stage2_tlb": { - "name": "stage2_tlb", - "is_stage2": true, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "p_state_clk_gate_min": 1000, - "name": "walker", - "is_stage2": true, - "p_state_clk_gate_bins": 20, - "cxx_class": "ArmISA::TableWalker", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sys": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.dstage2_mmu.stage2_tlb.walker", - "type": "ArmTableWalker", - "num_squash_per_cycle": 2 - }, - "path": "system.cpu.dstage2_mmu.stage2_tlb", - "type": "ArmTLB", - "size": 32 - }, - "eventq_index": 0, - "cxx_class": "ArmISA::Stage2MMU", - "path": "system.cpu.dstage2_mmu", - "type": "ArmStage2MMU" - }, - "l2cache": { - "cpu_side": { - "peer": "system.cpu.toL2Bus.master[0]", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": null, - "system": "system", - "write_buffers": 8, - "response_latency": 20, - "cxx_class": "Cache", - "size": 4194304, - "tags": { - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sequential_access": false, - "assoc": 8, - "cxx_class": "LRU", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.l2cache.tags", - "hit_latency": 20, - "block_size": 64, - "type": "LRU", - "size": 4194304 - }, - "clk_domain": "system.cpu_clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.membus.slave[2]", - "role": "MASTER" - }, - "type": "Cache", - "writeback_clean": false, - "p_state_clk_gate_min": 1000, - "hit_latency": 20, - "tgts_per_mshr": 12, - "demand_mshr_reserve": 1, - "power_model": null, - "addr_ranges": [ - "0:18446744073709551615" - ], - "is_read_only": false, - "prefetch_on_access": false, - "path": "system.cpu.l2cache", - "mshrs": 20, - "name": "l2cache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 8 - }, - "path": "system.cpu", - "max_loads_any_thread": 0, - "switched_out": false, - "workload": [], - "name": "cpu", - "dtb": { - "name": "dtb", - "is_stage2": false, - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "p_state_clk_gate_min": 1000, - "name": "walker", - "is_stage2": false, - "p_state_clk_gate_bins": 20, - "cxx_class": "ArmISA::TableWalker", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sys": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.dtb.walker", - "type": "ArmTableWalker", - "port": { - "peer": "system.cpu.toL2Bus.slave[3]", - "role": "MASTER" - }, - "num_squash_per_cycle": 2 - }, - "path": "system.cpu.dtb", - "type": "ArmTLB", - "size": 64 - }, - "simpoint_start_insts": [], - "max_insts_any_thread": 0, - "simulate_inst_stalls": false, - "progress_interval": 0, - "branchPred": null, - "dcache": { - "cpu_side": { - "peer": "system.cpu.dcache_port", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": null, - "system": "system", - "write_buffers": 8, - "response_latency": 2, - "cxx_class": "Cache", - "size": 32768, - "tags": { - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.cpu_clk_domain", - "power_model": null, - "sequential_access": false, - "assoc": 4, - "cxx_class": "LRU", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.dcache.tags", - "hit_latency": 2, - "block_size": 64, - "type": "LRU", - "size": 32768 - }, - "clk_domain": "system.cpu_clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.cpu.toL2Bus.slave[1]", - "role": "MASTER" - }, - "type": "Cache", - "writeback_clean": false, - "p_state_clk_gate_min": 1000, - "hit_latency": 2, - "tgts_per_mshr": 20, - "demand_mshr_reserve": 1, - "power_model": null, - "addr_ranges": [ - "0:18446744073709551615" - ], - "is_read_only": false, - "prefetch_on_access": false, - "path": "system.cpu.dcache", - "mshrs": 4, - "name": "dcache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 4 - }, - "isa": [ - { - "pmu": null, - "id_pfr1": 4113, - "id_pfr0": 49, - "id_isar1": 34677009, - "id_isar0": 34607377, - "id_isar3": 17899825, - "id_isar2": 555950401, - "id_isar5": 0, - "id_isar4": 268501314, - "cxx_class": "ArmISA::ISA", - "id_aa64mmfr1_el1": 0, - "id_aa64pfr1_el1": 0, - "system": "system", - "eventq_index": 0, - "type": "ArmISA", - "id_aa64dfr1_el1": 0, - "fpsid": 1090793632, - "id_mmfr0": 270536963, - "id_mmfr1": 0, - "id_mmfr2": 19070976, - "id_mmfr3": 34611729, - "id_aa64mmfr0_el1": 15728642, - "id_aa64dfr0_el1": 1052678, - "path": "system.cpu.isa", - "id_aa64isar0_el1": 0, - "decoderFlavour": "Generic", - "name": "isa", - "midr": 1091551472, - "id_aa64afr0_el1": 0, - "id_aa64isar1_el1": 0, - "id_aa64afr1_el1": 0, - "id_aa64pfr0_el1": 34 - } - ], - "tracer": { - "eventq_index": 0, - "path": "system.cpu.tracer", - "type": "ExeTracer", - "name": "tracer", - "cxx_class": "Trace::ExeTracer" - } - } - ], - "gic_cpu_addr": 738205696, - "work_cpus_ckpt_count": 0, - "thermal_components": [], - "machine_type": "VExpress_EMM", - "flags_addr": 469827632, - "path": "system", - "cpu_clk_domain": { - "name": "cpu_clk_domain", - "clock": [ - 500 - ], - "init_perf_level": 0, - "voltage_domain": "system.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.cpu_clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "cf0": { - "driveID": "master", - "name": "cf0", - "image": { - "read_only": false, - "name": "image", - "cxx_class": "CowDiskImage", - "eventq_index": 0, - "child": { - "read_only": true, - "name": "child", - "eventq_index": 0, - "cxx_class": "RawDiskImage", - "path": "system.cf0.image.child", - "image_file": "/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img", - "type": "RawDiskImage" - }, - "path": "system.cf0.image", - "image_file": "", - "type": "CowDiskImage", - "table_size": 65536 - }, - "delay": 1000000, - "eventq_index": 0, - "cxx_class": "IdeDisk", - "path": "system.cf0", - "type": "IdeDisk" - }, - "work_end_ckpt_count": 0, - "mem_mode": "atomic", - "name": "system", - "init_param": 0, - "p_state_clk_gate_bins": 20, - "load_addr_mask": 268435455, - "work_item_id": -1, - "intrctrl": { - "name": "intrctrl", - "sys": "system", - "eventq_index": 0, - "cxx_class": "IntrControl", - "path": "system.intrctrl", - "type": "IntrControl" - }, - "have_security": false, - "atags_addr": 134217728, - "memories": [ - "system.physmem", - "system.realview.nvmem", - "system.realview.vram" - ], - "num_work_ids": 16, - "boot_loader": [ - "/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm" - ], - "exit_on_work_items": false - }, - "time_sync_period": 100000000000, - "eventq_index": 0, - "time_sync_spin_threshold": 100000000, - "cxx_class": "Root", - "path": "root", - "time_sync_enable": false, - "type": "Root", - "full_system": true -}
\ No newline at end of file diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt deleted file mode 100644 index 7fca9a0be..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ /dev/null @@ -1,825 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.783855 # Number of seconds simulated -sim_ticks 2783854715000 # Number of ticks simulated -final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 492350 # Simulator instruction rate (inst/s) -host_op_rate 599357 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9600186649 # Simulator tick rate (ticks/s) -host_mem_usage 585092 # Number of bytes of host memory used -host_seconds 289.98 # Real time elapsed on the host -sim_insts 142771202 # Number of instructions simulated -sim_ops 173801044 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10324772 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11533320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 161844 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189181 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3708804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175775 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3182070 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3715099 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7325002 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 10028 # Table walker walks requested -system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31525882 # DTB read hits -system.cpu.dtb.read_misses 8580 # DTB read misses -system.cpu.dtb.write_hits 23124079 # DTB write hits -system.cpu.dtb.write_misses 1448 # DTB write misses -system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4285 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534462 # DTB read accesses -system.cpu.dtb.write_accesses 23125527 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54649961 # DTB hits -system.cpu.dtb.misses 10028 # DTB misses -system.cpu.dtb.accesses 54659989 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 4762 # Table walker walks requested -system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 147037694 # ITB inst hits -system.cpu.itb.inst_misses 4762 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147042456 # ITB inst accesses -system.cpu.itb.hits 147037694 # DTB hits -system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147042456 # DTB accesses -system.cpu.numPwrStateTransitions 6160 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 874939633.669805 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17329944405.377167 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 89040643297 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814071703 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5567712511 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu.committedInsts 142771202 # Number of instructions committed -system.cpu.committedOps 173801044 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153160791 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873864 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730220 # number of instructions that are conditional controls -system.cpu.num_int_insts 153160791 # number of integer instructions -system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285043206 # number of times the integer registers were read -system.cpu.num_int_register_writes 107178068 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530847827 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62363707 # number of times the CC registers were written -system.cpu.num_mem_refs 55938510 # number of memory refs -system.cpu.num_load_insts 31855508 # Number of load instructions -system.cpu.num_store_insts 24083002 # Number of store instructions -system.cpu.num_idle_cycles 5389631125.859330 # Number of idle cycles -system.cpu.num_busy_cycles 178081385.140670 # Number of busy cycles -system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36396820 # Number of branches fetched -system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121151571 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855508 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083002 13.59% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177217860 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 819387 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53783783 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819899 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.598059 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219234707 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219234707 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 30128737 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30128737 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22339767 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22339767 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 395067 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 395067 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457333 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457333 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52468504 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52468504 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52863571 # number of overall hits -system.cpu.dcache.overall_hits::total 52863571 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116119 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116119 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697939 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697939 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814058 # number of overall misses -system.cpu.dcache.overall_misses::total 814058 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525014 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641429 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641429 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53166443 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53166443 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53677629 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53677629 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227156 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.227156 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018483 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018483 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.013127 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.013127 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 682138 # number of writebacks -system.cpu.dcache.writebacks::total 682138 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1698988 # number of replacements -system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145341295 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699500 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.520032 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148740307 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148740307 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 145341295 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145341295 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145341295 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145341295 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145341295 # number of overall hits -system.cpu.icache.overall_hits::total 145341295 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699506 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699506 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699506 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699506 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699506 # number of overall misses -system.cpu.icache.overall_misses::total 1699506 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147040801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147040801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147040801 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147040801 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147040801 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147040801 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1698988 # number of writebacks -system.cpu.icache.writebacks::total 1698988 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 109912 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65246.862245 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4827688 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175338 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 27.533609 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.971735 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023390 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.132693 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734427 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139925 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.855617 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65421 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55480 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998245 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40257223 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40257223 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5671 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2714 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 8385 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 682138 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 682138 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1666989 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 2746 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 2746 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 152790 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 152790 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681191 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 5671 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2714 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681191 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 658230 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2347806 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 5671 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2714 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681191 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 658230 # number of overall hits -system.cpu.l2cache.overall_hits::total 2347806 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 146117 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 146117 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 15568 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 161685 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 179992 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 161685 # number of overall misses -system.cpu.l2cache.overall_misses::total 179992 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5678 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2716 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 8394 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 682138 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 682138 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2755 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699489 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1699489 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5678 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 2716 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699489 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819915 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2527798 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5678 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2716 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699489 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819915 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2527798 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001233 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000736 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001072 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003267 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.488838 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001233 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000736 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.197197 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.071205 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001233 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000736 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.197197 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.071205 # miss rate for overall accesses -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks -system.cpu.l2cache.writebacks::total 101949 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 5059872 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540470 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288314 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 682138 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 137249 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116044 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581953 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7753423 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96314145 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313964701 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 115326 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6541312 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5251057 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018717 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.135522 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5152775 98.13% 98.13% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98282 1.87% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5251057 # Request fanout histogram -system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 30164 # Transaction distribution -system.iobus.trans_dist::ReadResp 30164 # Transaction distribution -system.iobus.trans_dist::WriteReq 59002 # Transaction distribution -system.iobus.trans_dist::WriteResp 59002 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909890 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909890 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328176 # Number of tag accesses -system.iocache.tags.data_accesses 328176 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses -system.iocache.ReadReq_misses::total 240 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses -system.iocache.demand_misses::total 36464 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36464 # number of overall misses -system.iocache.overall_misses::total 36464 # number of overall misses -system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.membus.snoop_filter.tot_requests 362809 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 151023 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 40087 # Transaction distribution -system.membus.trans_dist::ReadResp 74202 # Transaction distribution -system.membus.trans_dist::WriteReq 27546 # Transaction distribution -system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution -system.membus.trans_dist::CleanEvict 8203 # Transaction distribution -system.membus.trans_dist::UpgradeReq 130 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 145996 # Transaction distribution -system.membus.trans_dist::ReadExResp 145996 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497824 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 605184 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 714542 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255321 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20586841 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 430442 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012836 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.112565 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 424917 98.72% 98.72% # Request fanout histogram -system.membus.snoop_fanout::1 5525 1.28% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 430442 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks -system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks -system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks -system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks -system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks -system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks -system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks -system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/system.terminal deleted file mode 100644 index ad91d76dd..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/system.terminal +++ /dev/null @@ -1,208 +0,0 @@ -Booting Linux on physical CPU 0x0
-
Initializing cgroup subsys cpuset
-
Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014
-
Kernel was built at commit id ''
-
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
-
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
-
Machine model: V2P-CA15
-
bootconsole [earlycon0] enabled
-
Memory policy: Data cache writealloc
-
kdebugv2m: Following are test values to confirm proper working
-
kdebugv2m: Ranges 42000000 0
-
kdebugv2m: Regs 30000000 1000000
-
kdebugv2m: Virtual-Reg f0000000
-
kdebugv2m: pci node addr_cells 3
-
kdebugv2m: pci node size_cells 2
-
kdebugv2m: motherboard addr_cells 2
-
On node 0 totalpages: 65536
-
free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000
-
Normal zone: 512 pages used for memmap
-
Normal zone: 0 pages reserved
-
Normal zone: 65536 pages, LIFO batch:15
-
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
-
PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768
-
pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096
-
pcpu-alloc: [0] 0
-
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
-
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-
PID hash table entries: 1024 (order: 0, 4096 bytes)
-
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
-
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
-
Memory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem)
-
Virtual kernel memory layout:
-
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
-
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
-
vmalloc : 0x90800000 - 0xff000000 (1768 MB)
-
lowmem : 0x80000000 - 0x90000000 ( 256 MB)
-
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
-
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
-
.text : 0x80008000 - 0x806a942c (6790 kB)
-
.init : 0x806aa000 - 0x806f3d80 ( 296 kB)
-
.data : 0x806f4000 - 0x80732754 ( 250 kB)
-
.bss : 0x80732754 - 0x8078e9d8 ( 369 kB)
-
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
-
Preemptible hierarchical RCU implementation.
-
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
-
NR_IRQS:16 nr_irqs:16 16
-
Architected cp15 timer(s) running at 25.16MHz (phys).
-
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
-
Switching to timer-based delay loop
-
Console: colour dummy device 80x30
-
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-
pid_max: default: 32768 minimum: 301
-
Mount-cache hash table entries: 512
-
CPU: Testing write buffer coherency: ok
-
CPU0: update cpu_power 1024
-
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
-
Setting up static identity map for 0x804fee68 - 0x804fee9c
-
Brought up 1 CPUs
-
SMP: Total of 1 processors activated.
-
CPU: All CPU(s) started in SVC mode.
-
VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
-
NET: Registered protocol family 16
-
DMA: preallocated 256 KiB pool for atomic coherent allocations
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0
-
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0
-
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
-
hw-breakpoint: CPU 0 failed to disable vector catch
-
Serial: AMBA PL011 UART driver
-
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-
console [ttyAMA0] enabled
-console [ttyAMA0] enabled
-
bootconsole [earlycon0] disabled
-bootconsole [earlycon0] disabled
-
PCI host bridge to bus 0000:00
-pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]
-pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
-pci_bus 0000:00: root bus resource [bus 00-ff]
-pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-PCI: bus0: Fast back to back transfers disabled
-pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]
-pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]
-pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]
-pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]
-pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]
-pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]
-pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
-PCI map irq: slot 0, pin 1, devslot 0, irq: 68
-PCI map irq: slot 1, pin 2, devslot 1, irq: 69
-bio: create slab <bio-0> at 0
-vgaarb: loaded
-SCSI subsystem initialized
-libata version 3.00 loaded.
-usbcore: registered new interface driver usbfs
-usbcore: registered new interface driver hub
-usbcore: registered new device driver usb
-pps_core: LinuxPPS API ver. 1 registered
-pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-PTP clock support registered
-Advanced Linux Sound Architecture Driver Initialized.
-Switched to clocksource arch_sys_counter
-NET: Registered protocol family 2
-TCP established hash table entries: 2048 (order: 1, 8192 bytes)
-TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
-TCP: Hash tables configured (established 2048 bind 2048)
-TCP: reno registered
-UDP hash table entries: 256 (order: 1, 8192 bytes)
-UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-NET: Registered protocol family 1
-RPC: Registered named UNIX socket transport module.
-RPC: Registered udp transport module.
-RPC: Registered tcp transport module.
-RPC: Registered tcp NFSv4.1 backchannel transport module.
-PCI: CLS 64 bytes, default 64
-hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available
-jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
-msgmni has been set to 460
-io scheduler noop registered (default)
-brd: module loaded
-loop: module loaded
-ata_piix 0000:00:01.0: version 2.13
-PCI: enabling device 0000:00:01.0 (0040 -> 0041)
-scsi0 : ata_piix
-scsi1 : ata_piix
-ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69
-ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69
-e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
-e100: Copyright(c) 1999-2006 Intel Corporation
-e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-e1000: Copyright (c) 1999-2006 Intel Corporation.
-PCI: enabling device 0000:00:00.0 (0040 -> 0042)
-ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-ata1.00: 1048320 sectors, multi 0: LBA
-ata1.00: configured for UDMA/33
-scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
-sd 0:0:0:0: [sda] Write Protect is off
-sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
- sda: sda1
-sd 0:0:0:0: Attached scsi generic sg0 type 0
-sd 0:0:0:0: [sda] Attached SCSI disk
-e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-e1000e: Copyright(c) 1999 - 2013 Intel Corporation.
-igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-igb: Copyright (c) 2007-2013 Intel Corporation.
-igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k
-igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
-ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k
-ixgbe: Copyright (c) 1999-2013 Intel Corporation.
-ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k
-ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.
-ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI
-ixgb: Copyright (c) 1999-2008 Intel Corporation.
-smsc911x: Driver version 2008-10-21
-smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2
-nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller
-nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1
-nxp-isp1760 1b000000.usb: Scratch test failed.
-nxp-isp1760 1b000000.usb: can't setup: -19
-nxp-isp1760 1b000000.usb: USB bus 1 deregistered
-usbcore: registered new interface driver usb-storage
-mousedev: PS/2 mouse device common for all mice
-rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0
-usbcore: registered new interface driver usbhid
-usbhid: USB HID core driver
-ashmem: initialized
-logger: created 256K log 'log_main'
-logger: created 256K log 'log_events'
-logger: created 256K log 'log_radio'
-logger: created 256K log 'log_system'
-oprofile: using timer interrupt.
-TCP: cubic registered
-NET: Registered protocol family 10
-NET: Registered protocol family 17
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)
-ALSA device list:
- No soundcards found.
- -input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2
-VFS: Mounted root (ext2 filesystem) on device 8:1.
-Freeing unused kernel memory: 292K (806aa000 - 806f3000)
-
init started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)
-
starting pid 673, tty '': '/etc/rc.d/rc.local'
-warning: can't open /etc/mtab: No such file or directory
-Thu Jan 1 00:00:02 UTC 2009
-S: devpts
-Thu Jan 1 00:00:02 UTC 2009
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/EMPTY b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/EMPTY new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/EMPTY diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini deleted file mode 100644 index f7978eb49..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini +++ /dev/null @@ -1,1743 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxArmSystem -children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain -atags_addr=134217728 -boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb -early_kernel_symbols=false -enable_context_switch_stats_dump=false -eventq_index=0 -exit_on_work_items=false -flags_addr=469827632 -gic_cpu_addr=738205696 -have_large_asid_64=false -have_lpae=true -have_security=false -have_virtualization=false -highest_el_is_64=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 -kernel_addr_check=true -load_addr_mask=268435455 -load_offset=2147483648 -machine_type=VExpress_EMM -mem_mode=atomic -mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.nvmem system.realview.vram -mmap_using_noreserve=false -multi_proc=true -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -panic_on_oops=true -panic_on_panic=true -phys_addr_range_64=40 -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -reset_addr_64=0 -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[1] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.cf0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.cf0.image - -[system.cf0.image] -type=CowDiskImage -children=child -child=system.cf0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.cf0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img -read_only=true - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu0] -type=AtomicSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu0.dstage2_mmu -dtb=system.cpu0.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu0.interrupts -isa=system.cpu0.isa -istage2_mmu=system.cpu0.istage2_mmu -itb=system.cpu0.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu0.tracer -width=1 -workload= -dcache_port=system.cpu0.dcache.cpu_side -icache_port=system.cpu0.icache.cpu_side - -[system.cpu0.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.slave[1] - -[system.cpu0.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu0.dtb - -[system.cpu0.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu0.dstage2_mmu.stage2_tlb.walker - -[system.cpu0.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu0.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu0.dtb.walker - -[system.cpu0.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.toL2Bus.slave[3] - -[system.cpu0.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.slave[0] - -[system.cpu0.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu0.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu0.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu0.itb - -[system.cpu0.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu0.istage2_mmu.stage2_tlb.walker - -[system.cpu0.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu0.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu0.itb.walker - -[system.cpu0.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.toL2Bus.slave[2] - -[system.cpu0.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu1] -type=AtomicSimpleCPU -children=dstage2_mmu dtb isa istage2_mmu itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu1.dstage2_mmu -dtb=system.cpu1.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts= -isa=system.cpu1.isa -istage2_mmu=system.cpu1.istage2_mmu -itb=system.cpu1.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=true -system=system -tracer=system.cpu1.tracer -width=1 -workload= - -[system.cpu1.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu1.dtb - -[system.cpu1.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu1.dstage2_mmu.stage2_tlb.walker - -[system.cpu1.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu1.dtb.walker - -[system.cpu1.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu1.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu1.itb - -[system.cpu1.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu1.istage2_mmu.stage2_tlb.walker - -[system.cpu1.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu1.itb.walker - -[system.cpu1.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=2147483648:2415919103 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[3] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.l2c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.l2c.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - -[system.l2c.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access=warn -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=2147483648:2415919103 -port=system.membus.master[5] - -[system.realview] -type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.realview.aaci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470024192 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[18] - -[system.realview.cf_ctrl] -type=IdeController -BAR0=471465984 -BAR0LegacyIO=true -BAR0Size=256 -BAR1=471466240 -BAR1LegacyIO=true -BAR1Size=4096 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=1 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=2 -default_p_state=UNDEFINED -disks= -eventq_index=0 -host=system.realview.pci_host -io_shift=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=2 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[2] -pio=system.iobus.master[9] - -[system.realview.clcd] -type=Pl111 -amba_id=1315089 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=46 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471793664 -pio_latency=10000 -pixel_clock=41667 -power_model=Null -system=system -vnc=system.vncserver -dma=system.iobus.slave[1] -pio=system.iobus.master[5] - -[system.realview.dcc] -type=SubSystem -children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys -eventq_index=0 -thermal_domain=Null - -[system.realview.dcc.osc_cpu] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_ddr] -type=RealViewOsc -dcc=0 -device=8 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_hsbm] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_pxl] -type=RealViewOsc -dcc=0 -device=5 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_smb] -type=RealViewOsc -dcc=0 -device=6 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_sys] -type=RealViewOsc -dcc=0 -device=7 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.energy_ctrl] -type=EnergyCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dvfs_handler=system.dvfs_handler -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470286336 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[22] - -[system.realview.ethernet] -type=IGbE -BAR0=0 -BAR0LegacyIO=false -BAR0Size=131072 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=0 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=4213 -ExpansionROM=0 -HeaderType=0 -InterruptLine=1 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=255 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=0 -SubClassCode=0 -SubsystemID=4104 -SubsystemVendorID=32902 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -eventq_index=0 -fetch_comp_delay=10000 -fetch_delay=10000 -hardware_address=00:90:00:00:00:01 -host=system.realview.pci_host -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -phy_epid=896 -phy_pid=680 -pio_latency=30000 -power_model=Null -rx_desc_cache_size=64 -rx_fifo_size=393216 -rx_write_delay=0 -system=system -tx_desc_cache_size=64 -tx_fifo_size=393216 -tx_read_delay=0 -wb_comp_delay=10000 -wb_delay=10000 -dma=system.iobus.slave[4] -pio=system.iobus.master[24] - -[system.realview.generic_timer] -type=GenericTimer -eventq_index=0 -gic=system.realview.gic -int_phys=29 -int_virt=27 -system=system - -[system.realview.gic] -type=Pl390 -clk_domain=system.clk_domain -cpu_addr=738205696 -cpu_pio_delay=10000 -default_p_state=UNDEFINED -dist_addr=738201600 -dist_pio_delay=10000 -eventq_index=0 -gem5_extensions=true -int_latency=10000 -it_lines=128 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -platform=system.realview -power_model=Null -system=system -pio=system.membus.master[2] - -[system.realview.hdlcd] -type=HDLcd -amba_id=1314816 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=117 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=721420288 -pio_latency=10000 -pixel_buffer_size=2048 -pixel_chunk=32 -power_model=Null -pxl_clk=system.realview.dcc.osc_pxl -system=system -vnc=system.vncserver -workaround_dma_line_count=true -workaround_swap_rb=true -dma=system.membus.slave[0] -pio=system.iobus.master[6] - -[system.realview.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=2 -InterruptPin=2 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.cf0 -eventq_index=0 -host=system.realview.pci_host -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[3] -pio=system.iobus.master[23] - -[system.realview.kmi0] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=44 -is_mouse=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470155264 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[7] - -[system.realview.kmi1] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=45 -is_mouse=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470220800 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[8] - -[system.realview.l2x0_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=739246080 -pio_latency=100000 -pio_size=4095 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.realview.lan_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=436207616 -pio_latency=100000 -pio_size=65535 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.realview.local_cpu_timer] -type=CpuLocalTimer -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num_timer=29 -int_num_watchdog=30 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=738721792 -pio_latency=100000 -power_model=Null -system=system -pio=system.membus.master[4] - -[system.realview.mcc] -type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl -eventq_index=0 -thermal_domain=Null - -[system.realview.mcc.osc_clcd] -type=RealViewOsc -dcc=0 -device=1 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_mcc] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_peripheral] -type=RealViewOsc -dcc=0 -device=2 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_system_bus] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.temp_crtl] -type=RealViewTemperatureSensor -dcc=0 -device=0 -eventq_index=0 -parent=system.realview.realview_io -position=0 -site=0 -system=system - -[system.realview.mmc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470089728 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.realview.nvmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:67108863 -port=system.membus.master[1] - -[system.realview.pci_host] -type=GenericPciHost -clk_domain=system.clk_domain -conf_base=805306368 -conf_device_bits=16 -conf_size=268435456 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=0 -pci_pio_base=0 -platform=system.realview -power_model=Null -system=system -pio=system.iobus.master[2] - -[system.realview.realview_io] -type=RealViewCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -idreg=35979264 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469827584 -pio_latency=100000 -power_model=Null -proc_id0=335544320 -proc_id1=335544320 -system=system -pio=system.iobus.master[1] - -[system.realview.rtc] -type=PL031 -amba_id=3412017 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=36 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471269376 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[10] - -[system.realview.sp810_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469893120 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[16] - -[system.realview.timer0] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=34 -int_num1=34 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470876160 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[3] - -[system.realview.timer1] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=35 -int_num1=35 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470941696 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[4] - -[system.realview.uart] -type=Pl011 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -end_on_eot=false -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=37 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470351872 -pio_latency=100000 -platform=system.realview -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[0] - -[system.realview.uart1_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470417408 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[13] - -[system.realview.uart2_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470482944 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[14] - -[system.realview.uart3_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470548480 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[15] - -[system.realview.usb_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=452984832 -pio_latency=100000 -pio_size=131071 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.realview.vgic] -type=VGic -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -hv_addr=738213888 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_delay=10000 -platform=system.realview -power_model=Null -ppint=25 -system=system -vcpu_addr=738222080 -pio=system.membus.master[3] - -[system.realview.vram] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=402653184:436207615 -port=system.iobus.master[11] - -[system.realview.watchdog_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470745088 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[17] - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port - -[system.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.vncserver] -type=VncServer -eventq_index=0 -frame_capture=false -number=0 -port=5900 - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr deleted file mode 100755 index 2db4f78f6..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr +++ /dev/null @@ -1,47 +0,0 @@ -warn: Sockets disabled, not accepting vnc client connections -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Existing EnergyCtrl, but no enabled DVFSHandler found. -warn: Not doing anything for miscreg ACTLR -warn: Not doing anything for write of miscreg ACTLR -warn: The clidr register always reports 0 caches. -warn: clidr LoUIS field of 0b001 to match current ARM implementations. -warn: The csselr register isn't implemented. -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr dccimvac' unimplemented -warn: Tried to read RealView I/O at offset 0x60 that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: ClockedObject: Already in the requested power state, request ignored -warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] -warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] -warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] -warn: Returning zero for read from miscreg pmcr -warn: Ignoring write to miscreg pmcntenclr -warn: Ignoring write to miscreg pmintenclr -warn: Ignoring write to miscreg pmovsr -warn: Ignoring write to miscreg pmcr -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout deleted file mode 100755 index 6555400fa..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout +++ /dev/null @@ -1,11 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic/simout -Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:17:36 -gem5 executing on e108600-lin, pid 12360 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic - -Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt deleted file mode 100644 index 5223c911e..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ /dev/null @@ -1,1156 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.783855 # Number of seconds simulated -sim_ticks 2783854715000 # Number of ticks simulated -final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 808320 # Simulator instruction rate (inst/s) -host_op_rate 984000 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15761202711 # Simulator tick rate (ticks/s) -host_mem_usage 583272 # Number of bytes of host memory used -host_seconds 176.63 # Real time elapsed on the host -sim_insts 142771202 # Number of instructions simulated -sim_ops 173801044 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 724388 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4660832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 482624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5663620 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11532936 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 724388 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 482624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840512 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858036 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 19772 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73344 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7541 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 88495 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189175 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138133 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142514 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 260210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1674237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 173365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2034452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260210 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 173365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175637 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181932 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1680529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 173365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2034455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7324726 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 5701 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5701 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5701 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5701 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5701 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3071 65.62% 65.62% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1609 34.38% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4680 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5701 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5701 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4680 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4680 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 10381 # Table walker requests started/completed, data/inst -system.cpu0.dtb.inst_hits 0 # ITB inst hits -system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15995747 # DTB read hits -system.cpu0.dtb.read_misses 4808 # DTB read misses -system.cpu0.dtb.write_hits 11281650 # DTB write hits -system.cpu0.dtb.write_misses 893 # DTB write misses -system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3166 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 769 # Number of TLB faults due to prefetch -system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16000555 # DTB read accesses -system.cpu0.dtb.write_accesses 11282543 # DTB write accesses -system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27277397 # DTB hits -system.cpu0.dtb.misses 5701 # DTB misses -system.cpu0.dtb.accesses 27283098 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 2588 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2588 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2588 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2588 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2588 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1363 72.73% 72.73% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 511 27.27% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1874 # Table walker page sizes translated -system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2588 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2588 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1874 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1874 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4462 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 74790987 # ITB inst hits -system.cpu0.itb.inst_misses 2588 # ITB inst misses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2813 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1841 # Number of entries that have been flushed from TLB -system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74793575 # ITB inst accesses -system.cpu0.itb.hits 74790987 # DTB hits -system.cpu0.itb.misses 2588 # DTB misses -system.cpu0.itb.accesses 74793575 # DTB accesses -system.cpu0.numPwrStateTransitions 3054 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1527 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1734298234.726916 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 24581216487.655636 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1468 96.14% 96.14% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 53 3.47% 99.61% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.07% 99.67% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.07% 99.74% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.07% 99.80% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 3 0.20% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1527 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 135581310572 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2648273404428 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 5536440740 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu0.committedInsts 72632991 # Number of instructions committed -system.cpu0.committedOps 87975246 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 77486299 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5273 # Number of float alu accesses -system.cpu0.num_func_calls 8693335 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9458955 # number of instructions that are conditional controls -system.cpu0.num_int_insts 77486299 # number of integer instructions -system.cpu0.num_fp_insts 5273 # number of float instructions -system.cpu0.num_int_register_reads 144060688 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54442960 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4051 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 268859447 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 31831121 # number of times the CC registers were written -system.cpu0.num_mem_refs 27908365 # number of memory refs -system.cpu0.num_load_insts 16163327 # Number of load instructions -system.cpu0.num_store_insts 11745038 # Number of store instructions -system.cpu0.num_idle_cycles 5353619045.925056 # Number of idle cycles -system.cpu0.num_busy_cycles 182821694.074943 # Number of busy cycles -system.cpu0.not_idle_fraction 0.033022 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.966978 # Percentage of idle cycles -system.cpu0.Branches 18598975 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2188 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 61771234 68.83% 68.83% # Class of executed instruction -system.cpu0.op_class::IntMult 59679 0.07% 68.90% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4413 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::MemRead 16163327 18.01% 86.91% # Class of executed instruction -system.cpu0.op_class::MemWrite 11745038 13.09% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 89745879 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 819387 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53783711 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819899 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.597971 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.709270 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.287904 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929120 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070875 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219234419 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219234419 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 15303909 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 14824794 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30128703 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10894549 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11445218 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22339767 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185793 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209252 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395045 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235001 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222316 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 457317 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236699 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223423 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26198458 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26270012 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52468470 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26384251 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26479264 # number of overall hits -system.cpu0.dcache.overall_hits::total 52863515 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197405 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 198906 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396311 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 137584 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 164078 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 301662 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54365 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61704 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 116069 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4662 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3966 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8628 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 334989 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 362984 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 697973 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389354 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 424688 # number of overall misses -system.cpu0.dcache.overall_misses::total 814042 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15501314 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 15023700 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11032133 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609296 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641429 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240158 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 270956 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511114 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239663 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226282 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236699 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223425 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26533447 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 26632996 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53166443 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26773605 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 26903952 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53677557 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012735 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013239 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012471 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014133 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226372 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227727 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227090 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019452 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017527 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018517 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012625 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013629 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014542 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015785 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.015165 # miss rate for overall accesses -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 682362 # number of writebacks -system.cpu0.dcache.writebacks::total 682362 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1698988 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 145341295 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1699500 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.520032 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.113855 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.549824 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888894 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110449 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 148740307 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 148740307 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 73948641 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 71392654 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 145341295 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 73948641 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 71392654 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 145341295 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 73948641 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 71392654 # number of overall hits -system.cpu0.icache.overall_hits::total 145341295 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844220 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855286 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1699506 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844220 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855286 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1699506 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844220 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855286 # number of overall misses -system.cpu0.icache.overall_misses::total 1699506 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74792861 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 72247940 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 147040801 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74792861 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 72247940 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 147040801 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74792861 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 72247940 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 147040801 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011287 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011838 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011287 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011838 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011287 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011838 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1698988 # number of writebacks -system.cpu0.icache.writebacks::total 1698988 # number of writebacks -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 6189 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6189 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 6189 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6189 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6189 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walksPending::samples 1000002000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000002000 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1000002000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3697 73.27% 73.27% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1349 26.73% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5046 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6189 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6189 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5046 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5046 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 11235 # Table walker requests started/completed, data/inst -system.cpu1.dtb.inst_hits 0 # ITB inst hits -system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 15528433 # DTB read hits -system.cpu1.dtb.read_misses 5402 # DTB read misses -system.cpu1.dtb.write_hits 11842197 # DTB write hits -system.cpu1.dtb.write_misses 787 # DTB write misses -system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3134 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 916 # Number of TLB faults due to prefetch -system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 243 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 15533835 # DTB read accesses -system.cpu1.dtb.write_accesses 11842984 # DTB write accesses -system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 27370630 # DTB hits -system.cpu1.dtb.misses 6189 # DTB misses -system.cpu1.dtb.accesses 27376819 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 3051 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3051 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walkWaitTime::samples 3051 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3051 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3051 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1721 81.56% 81.56% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 389 18.44% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2110 # Table walker page sizes translated -system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3051 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3051 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5161 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 72245830 # ITB inst hits -system.cpu1.itb.inst_misses 3051 # ITB inst misses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2817 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1961 # Number of entries that have been flushed from TLB -system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 72248881 # ITB inst accesses -system.cpu1.itb.hits 72245830 # DTB hits -system.cpu1.itb.misses 3051 # DTB misses -system.cpu1.itb.accesses 72248881 # DTB accesses -system.cpu1.numPwrStateTransitions 3094 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 1547 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1764387509.755010 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 61127772689.263474 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1530 98.90% 98.90% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 14 0.90% 99.81% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.06% 99.87% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.06% 99.94% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 1 0.06% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 2395080486501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 1547 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 54347237409 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2729507477591 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 88023752 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 70138211 # Number of instructions committed -system.cpu1.committedOps 85825798 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 75674492 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6211 # Number of float alu accesses -system.cpu1.num_func_calls 8180529 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9271265 # number of instructions that are conditional controls -system.cpu1.num_int_insts 75674492 # number of integer instructions -system.cpu1.num_fp_insts 6211 # number of float instructions -system.cpu1.num_int_register_reads 140982518 # number of times the integer registers were read -system.cpu1.num_int_register_writes 52735108 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4721 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 261988380 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 30532586 # number of times the CC registers were written -system.cpu1.num_mem_refs 28030145 # number of memory refs -system.cpu1.num_load_insts 15692181 # Number of load instructions -system.cpu1.num_store_insts 12337964 # Number of store instructions -system.cpu1.num_idle_cycles 85368728.542814 # Number of idle cycles -system.cpu1.num_busy_cycles 2655023.457186 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030163 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969837 # Percentage of idle cycles -system.cpu1.Branches 17797845 # Number of branches fetched -system.cpu1.op_class::No_OpClass 149 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 59380337 67.88% 67.89% # Class of executed instruction -system.cpu1.op_class::IntMult 57194 0.07% 67.95% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4156 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::MemRead 15692181 17.94% 85.89% # Class of executed instruction -system.cpu1.op_class::MemWrite 12337964 14.11% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 87471981 # Class of executed instruction -system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 30164 # Transaction distribution -system.iobus.trans_dist::ReadResp 30164 # Transaction distribution -system.iobus.trans_dist::WriteReq 59002 # Transaction distribution -system.iobus.trans_dist::WriteResp 59002 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909890 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909890 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328176 # Number of tag accesses -system.iocache.tags.data_accesses 328176 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses -system.iocache.ReadReq_misses::total 240 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses -system.iocache.demand_misses::total 36464 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36464 # number of overall misses -system.iocache.overall_misses::total 36464 # number of overall misses -system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 109906 # number of replacements -system.l2c.tags.tagsinuse 65246.862245 # Cycle average of tags in use -system.l2c.tags.total_refs 4830712 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 175332 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 27.551799 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.924122 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999998 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5146.889475 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 28219.641429 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978701 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4023.136773 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 27850.291746 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000075 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.078535 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.430598 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061388 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.424962 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65419 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55478 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.998215 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40281361 # Number of tag accesses -system.l2c.tags.data_accesses 40281361 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 3721 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1793 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 3957 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1933 # number of ReadReq hits -system.l2c.ReadReq_hits::total 11404 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 682362 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 682362 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1666989 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 1257 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1489 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2746 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 73078 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 79712 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 152790 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 833454 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 847737 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 246679 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 258766 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3721 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1793 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833454 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 319757 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 3957 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1933 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 847737 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 338478 # number of demand (read+write) hits -system.l2c.demand_hits::total 2350830 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3721 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1793 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833454 # number of overall hits -system.l2c.overall_hits::cpu0.data 319757 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 3957 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1933 # number of overall hits -system.l2c.overall_hits::cpu1.inst 847737 # number of overall hits -system.l2c.overall_hits::cpu1.data 338478 # number of overall hits -system.l2c.overall_hits::total 2350830 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::total 8 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 9 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63244 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 82873 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 146117 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 10757 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 7541 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9753 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 5810 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 15563 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10757 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 72997 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 7541 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 88683 # number of demand (read+write) misses -system.l2c.demand_misses::total 179986 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10757 # number of overall misses -system.l2c.overall_misses::cpu0.data 72997 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 7541 # number of overall misses -system.l2c.overall_misses::cpu1.data 88683 # number of overall misses -system.l2c.overall_misses::total 179986 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 3726 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1794 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 3959 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1933 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 11412 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 682362 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 682362 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1493 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 136322 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 162585 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 844211 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 855278 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1699489 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 256432 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 264576 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 3726 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1794 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 844211 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392754 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 3959 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1933 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855278 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 427161 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2530816 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 3726 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1794 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 844211 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392754 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 3959 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1933 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855278 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 427161 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2530816 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000557 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000505 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.000701 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.003962 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.002679 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.463931 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.509721 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.012742 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008817 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.038033 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021960 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.029871 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000557 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.012742 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.185859 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000505 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008817 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.207610 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.071118 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001342 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000557 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.012742 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.185859 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000505 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008817 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.207610 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.071118 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 101943 # number of writebacks -system.l2c.writebacks::total 101943 # number of writebacks -system.membus.snoop_filter.tot_requests 362797 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 151017 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 40087 # Transaction distribution -system.membus.trans_dist::ReadResp 74196 # Transaction distribution -system.membus.trans_dist::WriteReq 27546 # Transaction distribution -system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138133 # Transaction distribution -system.membus.trans_dist::CleanEvict 8203 # Transaction distribution -system.membus.trans_dist::UpgradeReq 130 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 145996 # Transaction distribution -system.membus.trans_dist::ReadExResp 145996 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34109 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 497806 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 605166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 714524 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18091580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18254553 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20586073 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 430430 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012836 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.112567 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 424905 98.72% 98.72% # Request fanout histogram -system.membus.snoop_fanout::1 5525 1.28% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 430430 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks -system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks -system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks -system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks -system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks -system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks -system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks -system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5060294 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2540892 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 71240 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2291754 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 682362 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 137025 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116044 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581953 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20756 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41550 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7760303 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96328481 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41512 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83100 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 313992797 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 115320 # Total snoops (count) -system.toL2Bus.snoopTraffic 6540928 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 5254491 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.018785 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.135764 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5155787 98.12% 98.12% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 98704 1.88% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5254491 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/system.terminal deleted file mode 100644 index ad91d76dd..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/system.terminal +++ /dev/null @@ -1,208 +0,0 @@ -Booting Linux on physical CPU 0x0
-
Initializing cgroup subsys cpuset
-
Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014
-
Kernel was built at commit id ''
-
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
-
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
-
Machine model: V2P-CA15
-
bootconsole [earlycon0] enabled
-
Memory policy: Data cache writealloc
-
kdebugv2m: Following are test values to confirm proper working
-
kdebugv2m: Ranges 42000000 0
-
kdebugv2m: Regs 30000000 1000000
-
kdebugv2m: Virtual-Reg f0000000
-
kdebugv2m: pci node addr_cells 3
-
kdebugv2m: pci node size_cells 2
-
kdebugv2m: motherboard addr_cells 2
-
On node 0 totalpages: 65536
-
free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000
-
Normal zone: 512 pages used for memmap
-
Normal zone: 0 pages reserved
-
Normal zone: 65536 pages, LIFO batch:15
-
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
-
PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768
-
pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096
-
pcpu-alloc: [0] 0
-
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
-
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-
PID hash table entries: 1024 (order: 0, 4096 bytes)
-
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
-
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
-
Memory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem)
-
Virtual kernel memory layout:
-
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
-
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
-
vmalloc : 0x90800000 - 0xff000000 (1768 MB)
-
lowmem : 0x80000000 - 0x90000000 ( 256 MB)
-
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
-
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
-
.text : 0x80008000 - 0x806a942c (6790 kB)
-
.init : 0x806aa000 - 0x806f3d80 ( 296 kB)
-
.data : 0x806f4000 - 0x80732754 ( 250 kB)
-
.bss : 0x80732754 - 0x8078e9d8 ( 369 kB)
-
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
-
Preemptible hierarchical RCU implementation.
-
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
-
NR_IRQS:16 nr_irqs:16 16
-
Architected cp15 timer(s) running at 25.16MHz (phys).
-
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
-
Switching to timer-based delay loop
-
Console: colour dummy device 80x30
-
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-
pid_max: default: 32768 minimum: 301
-
Mount-cache hash table entries: 512
-
CPU: Testing write buffer coherency: ok
-
CPU0: update cpu_power 1024
-
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
-
Setting up static identity map for 0x804fee68 - 0x804fee9c
-
Brought up 1 CPUs
-
SMP: Total of 1 processors activated.
-
CPU: All CPU(s) started in SVC mode.
-
VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
-
NET: Registered protocol family 16
-
DMA: preallocated 256 KiB pool for atomic coherent allocations
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0
-
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0
-
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
-
hw-breakpoint: CPU 0 failed to disable vector catch
-
Serial: AMBA PL011 UART driver
-
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-
console [ttyAMA0] enabled
-console [ttyAMA0] enabled
-
bootconsole [earlycon0] disabled
-bootconsole [earlycon0] disabled
-
PCI host bridge to bus 0000:00
-pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]
-pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
-pci_bus 0000:00: root bus resource [bus 00-ff]
-pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-PCI: bus0: Fast back to back transfers disabled
-pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]
-pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]
-pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]
-pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]
-pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]
-pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]
-pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
-PCI map irq: slot 0, pin 1, devslot 0, irq: 68
-PCI map irq: slot 1, pin 2, devslot 1, irq: 69
-bio: create slab <bio-0> at 0
-vgaarb: loaded
-SCSI subsystem initialized
-libata version 3.00 loaded.
-usbcore: registered new interface driver usbfs
-usbcore: registered new interface driver hub
-usbcore: registered new device driver usb
-pps_core: LinuxPPS API ver. 1 registered
-pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-PTP clock support registered
-Advanced Linux Sound Architecture Driver Initialized.
-Switched to clocksource arch_sys_counter
-NET: Registered protocol family 2
-TCP established hash table entries: 2048 (order: 1, 8192 bytes)
-TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
-TCP: Hash tables configured (established 2048 bind 2048)
-TCP: reno registered
-UDP hash table entries: 256 (order: 1, 8192 bytes)
-UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-NET: Registered protocol family 1
-RPC: Registered named UNIX socket transport module.
-RPC: Registered udp transport module.
-RPC: Registered tcp transport module.
-RPC: Registered tcp NFSv4.1 backchannel transport module.
-PCI: CLS 64 bytes, default 64
-hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available
-jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
-msgmni has been set to 460
-io scheduler noop registered (default)
-brd: module loaded
-loop: module loaded
-ata_piix 0000:00:01.0: version 2.13
-PCI: enabling device 0000:00:01.0 (0040 -> 0041)
-scsi0 : ata_piix
-scsi1 : ata_piix
-ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69
-ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69
-e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
-e100: Copyright(c) 1999-2006 Intel Corporation
-e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-e1000: Copyright (c) 1999-2006 Intel Corporation.
-PCI: enabling device 0000:00:00.0 (0040 -> 0042)
-ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-ata1.00: 1048320 sectors, multi 0: LBA
-ata1.00: configured for UDMA/33
-scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
-sd 0:0:0:0: [sda] Write Protect is off
-sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
- sda: sda1
-sd 0:0:0:0: Attached scsi generic sg0 type 0
-sd 0:0:0:0: [sda] Attached SCSI disk
-e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-e1000e: Copyright(c) 1999 - 2013 Intel Corporation.
-igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-igb: Copyright (c) 2007-2013 Intel Corporation.
-igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k
-igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
-ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k
-ixgbe: Copyright (c) 1999-2013 Intel Corporation.
-ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k
-ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.
-ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI
-ixgb: Copyright (c) 1999-2008 Intel Corporation.
-smsc911x: Driver version 2008-10-21
-smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2
-nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller
-nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1
-nxp-isp1760 1b000000.usb: Scratch test failed.
-nxp-isp1760 1b000000.usb: can't setup: -19
-nxp-isp1760 1b000000.usb: USB bus 1 deregistered
-usbcore: registered new interface driver usb-storage
-mousedev: PS/2 mouse device common for all mice
-rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0
-usbcore: registered new interface driver usbhid
-usbhid: USB HID core driver
-ashmem: initialized
-logger: created 256K log 'log_main'
-logger: created 256K log 'log_events'
-logger: created 256K log 'log_radio'
-logger: created 256K log 'log_system'
-oprofile: using timer interrupt.
-TCP: cubic registered
-NET: Registered protocol family 10
-NET: Registered protocol family 17
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)
-ALSA device list:
- No soundcards found.
- -input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2
-VFS: Mounted root (ext2 filesystem) on device 8:1.
-Freeing unused kernel memory: 292K (806aa000 - 806f3000)
-
init started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)
-
starting pid 673, tty '': '/etc/rc.d/rc.local'
-warning: can't open /etc/mtab: No such file or directory
-Thu Jan 1 00:00:02 UTC 2009
-S: devpts
-Thu Jan 1 00:00:02 UTC 2009
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/EMPTY b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/EMPTY new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/EMPTY diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini deleted file mode 100644 index 1edcbf2e1..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ /dev/null @@ -1,1799 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxArmSystem -children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain -atags_addr=134217728 -boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb -early_kernel_symbols=false -enable_context_switch_stats_dump=false -eventq_index=0 -exit_on_work_items=false -flags_addr=469827632 -gic_cpu_addr=738205696 -have_large_asid_64=false -have_lpae=true -have_security=false -have_virtualization=false -highest_el_is_64=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 -kernel_addr_check=true -load_addr_mask=268435455 -load_offset=2147483648 -machine_type=VExpress_EMM -mem_mode=timing -mem_ranges=2147483648:2415919103 -memories=system.physmem system.realview.nvmem system.realview.vram -mmap_using_noreserve=false -multi_proc=true -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -panic_on_oops=true -panic_on_panic=true -phys_addr_range_64=40 -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -reset_addr_64=0 -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[1] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.cf0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.cf0.image - -[system.cf0.image] -type=CowDiskImage -children=child -child=system.cf0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.cf0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img -read_only=true - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu0] -type=TimingSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu0.dstage2_mmu -dtb=system.cpu0.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu0.interrupts -isa=system.cpu0.isa -istage2_mmu=system.cpu0.istage2_mmu -itb=system.cpu0.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu0.tracer -workload= -dcache_port=system.cpu0.dcache.cpu_side -icache_port=system.cpu0.icache.cpu_side - -[system.cpu0.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.slave[1] - -[system.cpu0.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu0.dtb - -[system.cpu0.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu0.dstage2_mmu.stage2_tlb.walker - -[system.cpu0.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu0.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu0.dtb.walker - -[system.cpu0.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.toL2Bus.slave[3] - -[system.cpu0.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.slave[0] - -[system.cpu0.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu0.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu0.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu0.itb - -[system.cpu0.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu0.istage2_mmu.stage2_tlb.walker - -[system.cpu0.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu0.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu0.itb.walker - -[system.cpu0.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.toL2Bus.slave[2] - -[system.cpu0.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu1] -type=TimingSimpleCPU -children=dstage2_mmu dtb isa istage2_mmu itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu1.dstage2_mmu -dtb=system.cpu1.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts= -isa=system.cpu1.isa -istage2_mmu=system.cpu1.istage2_mmu -itb=system.cpu1.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=true -system=system -tracer=system.cpu1.tracer -workload= - -[system.cpu1.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu1.dtb - -[system.cpu1.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu1.dstage2_mmu.stage2_tlb.walker - -[system.cpu1.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu1.dtb.walker - -[system.cpu1.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -pmu=Null -system=system - -[system.cpu1.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu1.itb - -[system.cpu1.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu1.istage2_mmu.stage2_tlb.walker - -[system.cpu1.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu1.itb.walker - -[system.cpu1.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu1.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=2147483648:2415919103 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[3] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.l2c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.l2c.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - -[system.l2c.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.physmem.port -slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access=warn -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.075000 -IDD02=0.000000 -IDD2N=0.050000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.000000 -IDD2P12=0.000000 -IDD3N=0.057000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.000000 -IDD3P12=0.000000 -IDD4R=0.187000 -IDD4R2=0.000000 -IDD4W=0.165000 -IDD4W2=0.000000 -IDD5=0.220000 -IDD52=0.000000 -IDD6=0.000000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=2147483648:2415919103 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=0 -tXPDLL=0 -tXS=0 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[5] - -[system.realview] -type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.realview.aaci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470024192 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[18] - -[system.realview.cf_ctrl] -type=IdeController -BAR0=471465984 -BAR0LegacyIO=true -BAR0Size=256 -BAR1=471466240 -BAR1LegacyIO=true -BAR1Size=4096 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=1 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=2 -default_p_state=UNDEFINED -disks= -eventq_index=0 -host=system.realview.pci_host -io_shift=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=2 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[2] -pio=system.iobus.master[9] - -[system.realview.clcd] -type=Pl111 -amba_id=1315089 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=46 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471793664 -pio_latency=10000 -pixel_clock=41667 -power_model=Null -system=system -vnc=system.vncserver -dma=system.iobus.slave[1] -pio=system.iobus.master[5] - -[system.realview.dcc] -type=SubSystem -children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys -eventq_index=0 -thermal_domain=Null - -[system.realview.dcc.osc_cpu] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_ddr] -type=RealViewOsc -dcc=0 -device=8 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_hsbm] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_pxl] -type=RealViewOsc -dcc=0 -device=5 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_smb] -type=RealViewOsc -dcc=0 -device=6 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_sys] -type=RealViewOsc -dcc=0 -device=7 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.energy_ctrl] -type=EnergyCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dvfs_handler=system.dvfs_handler -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470286336 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[22] - -[system.realview.ethernet] -type=IGbE -BAR0=0 -BAR0LegacyIO=false -BAR0Size=131072 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=0 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=4213 -ExpansionROM=0 -HeaderType=0 -InterruptLine=1 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=255 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=0 -SubClassCode=0 -SubsystemID=4104 -SubsystemVendorID=32902 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -eventq_index=0 -fetch_comp_delay=10000 -fetch_delay=10000 -hardware_address=00:90:00:00:00:01 -host=system.realview.pci_host -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -phy_epid=896 -phy_pid=680 -pio_latency=30000 -power_model=Null -rx_desc_cache_size=64 -rx_fifo_size=393216 -rx_write_delay=0 -system=system -tx_desc_cache_size=64 -tx_fifo_size=393216 -tx_read_delay=0 -wb_comp_delay=10000 -wb_delay=10000 -dma=system.iobus.slave[4] -pio=system.iobus.master[24] - -[system.realview.generic_timer] -type=GenericTimer -eventq_index=0 -gic=system.realview.gic -int_phys=29 -int_virt=27 -system=system - -[system.realview.gic] -type=Pl390 -clk_domain=system.clk_domain -cpu_addr=738205696 -cpu_pio_delay=10000 -default_p_state=UNDEFINED -dist_addr=738201600 -dist_pio_delay=10000 -eventq_index=0 -gem5_extensions=true -int_latency=10000 -it_lines=128 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -platform=system.realview -power_model=Null -system=system -pio=system.membus.master[2] - -[system.realview.hdlcd] -type=HDLcd -amba_id=1314816 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=117 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=721420288 -pio_latency=10000 -pixel_buffer_size=2048 -pixel_chunk=32 -power_model=Null -pxl_clk=system.realview.dcc.osc_pxl -system=system -vnc=system.vncserver -workaround_dma_line_count=true -workaround_swap_rb=true -dma=system.membus.slave[0] -pio=system.iobus.master[6] - -[system.realview.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=2 -InterruptPin=2 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.cf0 -eventq_index=0 -host=system.realview.pci_host -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[3] -pio=system.iobus.master[23] - -[system.realview.kmi0] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=44 -is_mouse=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470155264 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[7] - -[system.realview.kmi1] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=45 -is_mouse=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470220800 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[8] - -[system.realview.l2x0_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=739246080 -pio_latency=100000 -pio_size=4095 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.realview.lan_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=436207616 -pio_latency=100000 -pio_size=65535 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.realview.local_cpu_timer] -type=CpuLocalTimer -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num_timer=29 -int_num_watchdog=30 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=738721792 -pio_latency=100000 -power_model=Null -system=system -pio=system.membus.master[4] - -[system.realview.mcc] -type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl -eventq_index=0 -thermal_domain=Null - -[system.realview.mcc.osc_clcd] -type=RealViewOsc -dcc=0 -device=1 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_mcc] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_peripheral] -type=RealViewOsc -dcc=0 -device=2 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_system_bus] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.temp_crtl] -type=RealViewTemperatureSensor -dcc=0 -device=0 -eventq_index=0 -parent=system.realview.realview_io -position=0 -site=0 -system=system - -[system.realview.mmc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470089728 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.realview.nvmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:67108863 -port=system.membus.master[1] - -[system.realview.pci_host] -type=GenericPciHost -clk_domain=system.clk_domain -conf_base=805306368 -conf_device_bits=16 -conf_size=268435456 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=0 -pci_pio_base=0 -platform=system.realview -power_model=Null -system=system -pio=system.iobus.master[2] - -[system.realview.realview_io] -type=RealViewCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -idreg=35979264 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469827584 -pio_latency=100000 -power_model=Null -proc_id0=335544320 -proc_id1=335544320 -system=system -pio=system.iobus.master[1] - -[system.realview.rtc] -type=PL031 -amba_id=3412017 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=36 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471269376 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[10] - -[system.realview.sp810_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469893120 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[16] - -[system.realview.timer0] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=34 -int_num1=34 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470876160 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[3] - -[system.realview.timer1] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=35 -int_num1=35 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470941696 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[4] - -[system.realview.uart] -type=Pl011 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -end_on_eot=false -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=37 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470351872 -pio_latency=100000 -platform=system.realview -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[0] - -[system.realview.uart1_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470417408 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[13] - -[system.realview.uart2_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470482944 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[14] - -[system.realview.uart3_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470548480 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[15] - -[system.realview.usb_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=452984832 -pio_latency=100000 -pio_size=131071 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.realview.vgic] -type=VGic -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -hv_addr=738213888 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_delay=10000 -platform=system.realview -power_model=Null -ppint=25 -system=system -vcpu_addr=738222080 -pio=system.membus.master[3] - -[system.realview.vram] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=402653184:436207615 -port=system.iobus.master[11] - -[system.realview.watchdog_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470745088 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[17] - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port - -[system.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.vncserver] -type=VncServer -eventq_index=0 -frame_capture=false -number=0 -port=5900 - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr deleted file mode 100755 index 1066aae7c..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr +++ /dev/null @@ -1,76 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting vnc client connections -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Existing EnergyCtrl, but no enabled DVFSHandler found. -warn: Not doing anything for miscreg ACTLR -warn: Not doing anything for write of miscreg ACTLR -warn: The clidr register always reports 0 caches. -warn: clidr LoUIS field of 0b001 to match current ARM implementations. -warn: The csselr register isn't implemented. -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr dccimvac' unimplemented -warn: Tried to read RealView I/O at offset 0x60 that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: ClockedObject: Already in the requested power state, request ignored -warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] -warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] -warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] -warn: Returning zero for read from miscreg pmcr -warn: Ignoring write to miscreg pmcntenclr -warn: Ignoring write to miscreg pmintenclr -warn: Ignoring write to miscreg pmovsr -warn: Ignoring write to miscreg pmcr -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout deleted file mode 100755 index 6e3fbd608..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout +++ /dev/null @@ -1,11 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing/simout -Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12210 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing - -Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt deleted file mode 100644 index 0051059a3..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ /dev/null @@ -1,2059 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.903767 # Number of seconds simulated -sim_ticks 2903766778500 # Number of ticks simulated -final_tick 2903766778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 556763 # Simulator instruction rate (inst/s) -host_op_rate 671289 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14374691055 # Simulator tick rate (ticks/s) -host_mem_usage 583268 # Number of bytes of host memory used -host_seconds 202.01 # Real time elapsed on the host -sim_insts 112469247 # Number of instructions simulated -sim_ops 135604005 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 555300 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4008928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 630848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4995972 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10192648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 555300 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 630848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1186148 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7610112 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 7627636 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 17130 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 63158 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9857 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 78063 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168233 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118908 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123289 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 191234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1380596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 217252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1720514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3510147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 191234 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 217252 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 408486 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2620772 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6032 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2626807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2620772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 191234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1386628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 110 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 217252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1720517 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6136954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168233 # Number of read requests accepted -system.physmem.writeReqs 123289 # Number of write requests accepted -system.physmem.readBursts 168233 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123289 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10759040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue -system.physmem.bytesWritten 7641600 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10192648 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7627636 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9792 # Per bank write bursts -system.physmem.perBankRdBursts::1 9632 # Per bank write bursts -system.physmem.perBankRdBursts::2 10568 # Per bank write bursts -system.physmem.perBankRdBursts::3 10165 # Per bank write bursts -system.physmem.perBankRdBursts::4 19064 # Per bank write bursts -system.physmem.perBankRdBursts::5 10189 # Per bank write bursts -system.physmem.perBankRdBursts::6 9914 # Per bank write bursts -system.physmem.perBankRdBursts::7 10188 # Per bank write bursts -system.physmem.perBankRdBursts::8 9623 # Per bank write bursts -system.physmem.perBankRdBursts::9 10301 # Per bank write bursts -system.physmem.perBankRdBursts::10 9773 # Per bank write bursts -system.physmem.perBankRdBursts::11 9030 # Per bank write bursts -system.physmem.perBankRdBursts::12 10231 # Per bank write bursts -system.physmem.perBankRdBursts::13 10348 # Per bank write bursts -system.physmem.perBankRdBursts::14 10027 # Per bank write bursts -system.physmem.perBankRdBursts::15 9265 # Per bank write bursts -system.physmem.perBankWrBursts::0 7302 # Per bank write bursts -system.physmem.perBankWrBursts::1 7227 # Per bank write bursts -system.physmem.perBankWrBursts::2 8385 # Per bank write bursts -system.physmem.perBankWrBursts::3 7804 # Per bank write bursts -system.physmem.perBankWrBursts::4 7523 # Per bank write bursts -system.physmem.perBankWrBursts::5 7419 # Per bank write bursts -system.physmem.perBankWrBursts::6 7240 # Per bank write bursts -system.physmem.perBankWrBursts::7 7527 # Per bank write bursts -system.physmem.perBankWrBursts::8 7332 # Per bank write bursts -system.physmem.perBankWrBursts::9 7919 # Per bank write bursts -system.physmem.perBankWrBursts::10 7392 # Per bank write bursts -system.physmem.perBankWrBursts::11 6920 # Per bank write bursts -system.physmem.perBankWrBursts::12 7696 # Per bank write bursts -system.physmem.perBankWrBursts::13 7626 # Per bank write bursts -system.physmem.perBankWrBursts::14 7423 # Per bank write bursts -system.physmem.perBankWrBursts::15 6665 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 2903766416500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 9558 # Read request sizes (log2) -system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 158661 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 4381 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118908 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 527 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58622 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 313.885163 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.743064 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.844549 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21439 36.57% 36.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14755 25.17% 61.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5499 9.38% 71.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3328 5.68% 76.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2438 4.16% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1485 2.53% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1033 1.76% 85.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1043 1.78% 87.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7602 12.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58622 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5829 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.840110 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 550.258858 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5827 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5829 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5829 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.483788 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.629212 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.311611 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 18 0.31% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 13 0.22% 0.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 4 0.07% 0.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 13 0.22% 0.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4877 83.67% 84.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 64 1.10% 85.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 110 1.89% 87.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 91 1.56% 89.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 303 5.20% 94.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 58 1.00% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 20 0.34% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.19% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 11 0.19% 95.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.10% 96.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.05% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.12% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 162 2.78% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.03% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.05% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.17% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.05% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 5 0.09% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 4 0.07% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.19% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.07% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5829 # Writes before turning the bus around for reads -system.physmem.totQLat 1480605750 # Total ticks spent queuing -system.physmem.totMemAccLat 4632668250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 840550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8807.36 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27557.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.78 # Average write queue length when enqueuing -system.physmem.readRowHits 138260 # Number of row buffer hits during reads -system.physmem.writeRowHits 90627 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.90 # Row buffer hit rate for writes -system.physmem.avgGap 9960711.08 # Average gap between requests -system.physmem.pageHitRate 79.61 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 228296880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 124566750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 698193600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 391566960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189659823600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 87381059850 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665609181500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1944092689140 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.507494 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2770726429250 # Time in different power states -system.physmem_0.memoryStateTime::REF 96963100000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 36075874500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214885440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 117249000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 613056600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 382145040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189659823600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85737221460 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1667051145000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943775526140 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.398269 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2773140927250 # Time in different power states -system.physmem_1.memoryStateTime::REF 96963100000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33662652750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 6919 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6919 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2260 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4659 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 6919 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6919 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6919 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5896 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11249.830393 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9924.741038 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5679.920137 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-8191 1980 33.58% 33.58% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::8192-16383 3242 54.99% 88.57% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-24575 672 11.40% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-90111 2 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5896 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 941563500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 941563500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 941563500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3659 62.06% 62.06% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 2237 37.94% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5896 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6919 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6919 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5896 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5896 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 12815 # Table walker requests started/completed, data/inst -system.cpu0.dtb.inst_hits 0 # ITB inst hits -system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12202364 # DTB read hits -system.cpu0.dtb.read_misses 6026 # DTB read misses -system.cpu0.dtb.write_hits 9652425 # DTB write hits -system.cpu0.dtb.write_misses 893 # DTB write misses -system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 471 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4544 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 884 # Number of TLB faults due to prefetch -system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 229 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12208390 # DTB read accesses -system.cpu0.dtb.write_accesses 9653318 # DTB write accesses -system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21854789 # DTB hits -system.cpu0.dtb.misses 6919 # DTB misses -system.cpu0.dtb.accesses 21861708 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 3587 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3587 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 847 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2740 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3587 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3587 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3587 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2736 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 11841.008772 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 10111.838069 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6604.852208 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 961 35.12% 35.12% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1280 46.78% 81.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 494 18.06% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2736 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 941232000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 941232000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 941232000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1889 69.04% 69.04% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 847 30.96% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2736 # Table walker page sizes translated -system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3587 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3587 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2736 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2736 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6323 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 57467408 # ITB inst hits -system.cpu0.itb.inst_misses 3587 # ITB inst misses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 471 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2707 # Number of entries that have been flushed from TLB -system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 57470995 # ITB inst accesses -system.cpu0.itb.hits 57467408 # DTB hits -system.cpu0.itb.misses 3587 # DTB misses -system.cpu0.itb.accesses 57470995 # DTB accesses -system.cpu0.numPwrStateTransitions 3112 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1556 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1547130345.667738 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23821374889.614185 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1511 97.11% 97.11% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 40 2.57% 99.68% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.06% 99.74% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.06% 99.81% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 3 0.19% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499963941844 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1556 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 496431960641 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2407334817859 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 2904051149 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3031 # number of quiesce instructions executed -system.cpu0.committedInsts 55929149 # Number of instructions committed -system.cpu0.committedOps 67264870 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 59473158 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5736 # Number of float alu accesses -system.cpu0.num_func_calls 4933883 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7554856 # number of instructions that are conditional controls -system.cpu0.num_int_insts 59473158 # number of integer instructions -system.cpu0.num_fp_insts 5736 # number of float instructions -system.cpu0.num_int_register_reads 108126384 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41101072 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4447 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1290 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 243127326 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25718334 # number of times the CC registers were written -system.cpu0.num_mem_refs 22505711 # number of memory refs -system.cpu0.num_load_insts 12365331 # Number of load instructions -system.cpu0.num_store_insts 10140380 # Number of store instructions -system.cpu0.num_idle_cycles 2686639067.561983 # Number of idle cycles -system.cpu0.num_busy_cycles 217412081.438017 # Number of busy cycles -system.cpu0.not_idle_fraction 0.074865 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.925135 # Percentage of idle cycles -system.cpu0.Branches 12899208 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46257774 67.21% 67.21% # Class of executed instruction -system.cpu0.op_class::IntMult 59366 0.09% 67.30% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4384 0.01% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::MemRead 12365331 17.97% 85.27% # Class of executed instruction -system.cpu0.op_class::MemWrite 10140380 14.73% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68829439 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 818958 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.827210 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43240509 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819470 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.766433 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1013369500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 311.506673 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 200.320536 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.608411 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.391251 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177126395 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177126395 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 11494682 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11621262 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23115944 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9265643 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9559561 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18825204 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200295 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192588 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392883 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 225246 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 218223 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443469 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 233094 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 227153 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460247 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20760325 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21180823 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41941148 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20960620 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21373411 # number of overall hits -system.cpu0.dcache.overall_hits::total 42334031 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 200460 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 199220 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 399680 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 142763 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 155795 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298558 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 57022 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61158 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 118180 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10816 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11741 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22557 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 343223 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 355015 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 698238 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 400245 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 416173 # number of overall misses -system.cpu0.dcache.overall_misses::total 816418 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2980896000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2983113000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5964009000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5727893000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6844158000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 12572051000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 131628000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 147568500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 279196500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 166000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8708789000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 9827271000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 18536060000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8708789000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 9827271000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 18536060000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11695142 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 11820482 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23515624 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9408406 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9715356 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19123762 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 257317 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 253746 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511063 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 236062 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 229964 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 466026 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 233096 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 227153 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460249 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 21103548 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 21535838 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42639386 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 21360865 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 21789584 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43150449 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017140 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.016854 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016996 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015174 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.016036 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015612 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.221602 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.241021 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.231244 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045818 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.051056 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048403 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000009 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016264 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016485 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016375 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018737 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019100 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018920 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14870.278360 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14973.963457 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14921.960068 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40121.691194 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 43930.536924 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42109.241755 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12169.748521 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12568.648326 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12377.377311 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 83000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25373.558882 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27681.283889 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 26546.908074 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21758.645330 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23613.427589 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22704.129502 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 683415 # number of writebacks -system.cpu0.dcache.writebacks::total 683415 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 291 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 383 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 674 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7100 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 6929 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14029 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 291 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 383 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 674 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 291 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 383 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 674 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 200169 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 198837 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 399006 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142763 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 155795 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 298558 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 56128 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 60039 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 116167 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3716 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4812 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8528 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 342932 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 354632 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 697564 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 399060 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 414671 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 813731 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14396 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16742 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15072 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 12517 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 29468 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 29259 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2774512000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2777407500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5551919500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5585130000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6688363000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12273493000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 725295500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 799071500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1524367000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 47708500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 61547000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 109255500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 164000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8359642000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9465770500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 17825412500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9084937500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10264842000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 19349779500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2828734500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3452490500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6281225000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2828734500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3452490500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6281225000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017116 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016821 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016968 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015174 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016036 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015612 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.218128 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.236611 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227305 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015742 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020925 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018299 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016250 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016467 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016360 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018682 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019031 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018858 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13860.847584 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13968.262949 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13914.375974 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39121.691194 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42930.536924 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41109.241755 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12922.168971 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13309.207349 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13122.203380 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12838.670614 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12790.315877 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12811.386023 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 82000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24376.966862 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26691.811512 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25553.802232 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22765.843482 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24754.183437 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23779.086086 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196494.477633 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 206217.327679 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201722.172265 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95993.433555 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 117997.556307 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 106956.340355 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1697713 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.728355 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113868966 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1698225 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.051755 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 25837690500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 418.792461 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 91.935894 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.817954 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.179562 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997516 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117265428 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117265428 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 56611241 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 57257725 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113868966 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56611241 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 57257725 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113868966 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56611241 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 57257725 # number of overall hits -system.cpu0.icache.overall_hits::total 113868966 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 856167 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 842064 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1698231 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 856167 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 842064 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1698231 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 856167 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 842064 # number of overall misses -system.cpu0.icache.overall_misses::total 1698231 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11730872000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11666474000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 23397346000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11730872000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 11666474000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 23397346000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11730872000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 11666474000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 23397346000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 57467408 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 58099789 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115567197 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 57467408 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 58099789 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115567197 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 57467408 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 58099789 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115567197 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014898 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014493 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014695 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014898 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014493 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014695 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014898 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014493 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014695 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13701.616624 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13854.616751 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13777.481391 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13701.616624 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13854.616751 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13777.481391 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13701.616624 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13854.616751 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13777.481391 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1697713 # number of writebacks -system.cpu0.icache.writebacks::total 1697713 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 856167 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 842064 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1698231 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 856167 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 842064 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1698231 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 856167 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 842064 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1698231 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10874705000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10824410000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 21699115000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10874705000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10824410000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 21699115000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10874705000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10824410000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 21699115000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 687287000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 687287000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 687287000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 687287000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014898 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014493 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014695 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014898 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014493 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014695 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014898 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014493 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014695 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12701.616624 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12854.616751 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12777.481391 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12701.616624 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12854.616751 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12777.481391 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12701.616624 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12854.616751 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12777.481391 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 76179.006872 # average overall mshr uncacheable latency -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 6570 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6570 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1884 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4686 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 6570 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6570 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6570 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5429 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10846.104255 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9462.707245 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6203.102162 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 4870 89.70% 89.70% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 555 10.22% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-98303 2 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-114687 1 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-180223 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5429 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1000192500 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000192500 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1000192500 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3569 65.74% 65.74% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1860 34.26% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5429 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6570 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6570 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5429 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5429 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 11999 # Table walker requests started/completed, data/inst -system.cpu1.dtb.inst_hits 0 # ITB inst hits -system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12320936 # DTB read hits -system.cpu1.dtb.read_misses 5629 # DTB read misses -system.cpu1.dtb.write_hits 9955242 # DTB write hits -system.cpu1.dtb.write_misses 941 # DTB write misses -system.cpu1.dtb.flush_tlb 2932 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3977 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 890 # Number of TLB faults due to prefetch -system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 216 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12326565 # DTB read accesses -system.cpu1.dtb.write_accesses 9956183 # DTB write accesses -system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22276178 # DTB hits -system.cpu1.dtb.misses 6570 # DTB misses -system.cpu1.dtb.accesses 22282748 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 3169 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3169 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 693 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2476 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3169 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3169 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3169 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2365 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11411.839323 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9688.359834 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6654.367944 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 919 38.86% 38.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 1055 44.61% 83.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 390 16.49% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2365 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1000178000 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1000178000 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1000178000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1672 70.70% 70.70% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 693 29.30% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2365 # Table walker page sizes translated -system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3169 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3169 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2365 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2365 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5534 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 58099789 # ITB inst hits -system.cpu1.itb.inst_misses 3169 # ITB inst misses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2932 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2313 # Number of entries that have been flushed from TLB -system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 58102958 # ITB inst accesses -system.cpu1.itb.hits 58099789 # DTB hits -system.cpu1.itb.misses 3169 # DTB misses -system.cpu1.itb.accesses 58102958 # DTB accesses -system.cpu1.numPwrStateTransitions 2934 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 1467 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1731723114.831629 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 49433684554.113754 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1454 99.11% 99.11% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 10 0.68% 99.80% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.07% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.07% 99.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 1 0.07% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 1799695172501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 1467 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 363328969042 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2540437809458 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 2903482408 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 56540098 # Number of instructions committed -system.cpu1.committedOps 68339135 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 60434834 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5361 # Number of float alu accesses -system.cpu1.num_func_calls 4961252 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7677275 # number of instructions that are conditional controls -system.cpu1.num_int_insts 60434834 # number of integer instructions -system.cpu1.num_fp_insts 5361 # number of float instructions -system.cpu1.num_int_register_reads 109950382 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41555809 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3938 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1426 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 246673704 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26181408 # number of times the CC registers were written -system.cpu1.num_mem_refs 22905703 # number of memory refs -system.cpu1.num_load_insts 12480329 # Number of load instructions -system.cpu1.num_store_insts 10425374 # Number of store instructions -system.cpu1.num_idle_cycles 2692560639.134501 # Number of idle cycles -system.cpu1.num_busy_cycles 210921768.865499 # Number of busy cycles -system.cpu1.not_idle_fraction 0.072644 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.927356 # Percentage of idle cycles -system.cpu1.Branches 13021982 # Number of branches fetched -system.cpu1.op_class::No_OpClass 133 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 46930380 67.14% 67.14% # Class of executed instruction -system.cpu1.op_class::IntMult 55203 0.08% 67.22% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4061 0.01% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::MemRead 12480329 17.86% 85.08% # Class of executed instruction -system.cpu1.op_class::MemWrite 10425374 14.92% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69895480 # Class of executed instruction -system.iobus.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 30183 # Transaction distribution -system.iobus.trans_dist::ReadResp 30183 # Transaction distribution -system.iobus.trans_dist::WriteReq 59014 # Transaction distribution -system.iobus.trans_dist::WriteResp 59014 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46333500 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 98000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 337000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 96000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 642500 # Layer occupancy (ticks) -system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 52000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6283500 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36461000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187683390 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.078668 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 309389193000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.078668 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067417 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067417 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328122 # Number of tag accesses -system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses -system.iocache.ReadReq_misses::total 234 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses -system.iocache.demand_misses::total 36458 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36458 # number of overall misses -system.iocache.overall_misses::total 36458 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28897377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28897377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4277880013 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4277880013 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4306777390 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4306777390 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4306777390 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4306777390 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123493.064103 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123493.064103 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118095.185871 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118095.185871 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118129.831313 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118129.831313 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118129.831313 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118129.831313 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17197377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17197377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2464564473 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2464564473 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2481761850 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2481761850 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2481761850 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2481761850 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73493.064103 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73493.064103 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68036.784259 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68036.784259 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68071.804542 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68071.804542 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68071.804542 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68071.804542 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 89096 # number of replacements -system.l2c.tags.tagsinuse 65019.507372 # Cycle average of tags in use -system.l2c.tags.total_refs 4852978 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 154522 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 31.406389 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 142568433000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.855347 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999676 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4118.843503 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 26763.314787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.933925 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.964521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5511.371420 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 28618.224194 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062849 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.408376 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000045 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.084097 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.436679 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.992119 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65419 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4596 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 60809 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.998215 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40264611 # Number of tag accesses -system.l2c.tags.data_accesses 40264611 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 5009 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2735 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4338 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2269 # number of ReadReq hits -system.l2c.ReadReq_hits::total 14351 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 683415 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 683415 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1666661 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1666661 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 1319 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1420 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2739 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 84291 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 82554 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 166845 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 848044 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 832191 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1680235 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 254366 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 257240 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 511606 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5009 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2735 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 848044 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 338657 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4338 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2269 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 832191 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 339794 # number of demand (read+write) hits -system.l2c.demand_hits::total 2373037 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5009 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2735 # number of overall hits -system.l2c.overall_hits::cpu0.inst 848044 # number of overall hits -system.l2c.overall_hits::cpu0.data 338657 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4338 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2269 # number of overall hits -system.l2c.overall_hits::cpu1.inst 832191 # number of overall hits -system.l2c.overall_hits::cpu1.data 339794 # number of overall hits -system.l2c.overall_hits::total 2373037 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 10 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 10 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 11 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 21 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 57143 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 71810 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 128953 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 8113 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 9859 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 17972 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 5647 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 6448 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 12095 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8113 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 62790 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 9859 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 78258 # number of demand (read+write) misses -system.l2c.demand_misses::total 159030 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 8113 # number of overall misses -system.l2c.overall_misses::cpu0.data 62790 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 9859 # number of overall misses -system.l2c.overall_misses::cpu1.data 78258 # number of overall misses -system.l2c.overall_misses::total 159030 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 251000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 84000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 433000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 84000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 852000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 288000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 321500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 609500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 161000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 161000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4469976500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5570866000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10040842500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 656455500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 793875000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1450330500 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 478141500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 532781500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 1010923000 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 251000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 84000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 656455500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4948118000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 433000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 84000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 793875000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6103647500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 12502948000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 251000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 84000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 656455500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4948118000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 433000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 84000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 793875000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6103647500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 12502948000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 5012 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2736 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4343 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2270 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 14361 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 683415 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 683415 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1666661 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1666661 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1329 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1431 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2760 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 141434 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 154364 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295798 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 856157 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 842050 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1698207 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 260013 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 263688 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 523701 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 5012 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2736 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 856157 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 401447 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4343 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2270 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 842050 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 418052 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2532067 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 5012 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2736 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 856157 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 401447 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4343 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2270 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 842050 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 418052 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2532067 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000599 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000365 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001151 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000441 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.000696 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.007524 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.007687 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.007609 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.404026 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.465199 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.435950 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.009476 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011708 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.010583 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.021718 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.024453 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.023095 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000599 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000365 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.009476 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.156409 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001151 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000441 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011708 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.187197 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.062806 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000599 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000365 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.009476 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.156409 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001151 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000441 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011708 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.187197 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.062806 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83666.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 84000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 86600 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 84000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 85200 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 28800 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 29227.272727 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29023.809524 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 80500 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 78224.393189 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77577.858237 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 77864.357557 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 80914.026870 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80522.872502 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 80699.449143 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 84671.772623 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82627.403846 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 83581.893344 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83666.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 80914.026870 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 78804.236343 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 86600 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 84000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 80522.872502 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 77993.911166 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 78620.059108 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83666.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 84000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 80914.026870 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 78804.236343 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 86600 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 84000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 80522.872502 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 77993.911166 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 78620.059108 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 82718 # number of writebacks -system.l2c.writebacks::total 82718 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 5 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 10 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 10 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 11 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 21 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 2 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 57143 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 71810 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 128953 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 8113 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 9859 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 17972 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 5647 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 6448 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 12095 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 8113 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 62790 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 5 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 9859 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 78258 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 159030 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 8113 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 62790 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 5 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 9859 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 78258 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 159030 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 14396 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16742 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15072 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 12517 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 29468 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 29259 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 221000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 74000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 383000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 74000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 752000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 188000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 211500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 399500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 141000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 141000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3898546500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4852766000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8751312500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 575325500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 695285000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1270610500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 421671500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 468301500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 889973000 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 221000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 74000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 575325500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4320218000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 383000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 74000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 695285000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 5321067500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 10912648000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 221000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 74000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 575325500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4320218000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 383000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 74000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 695285000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 5321067500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 10912648000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 574512000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2648734000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3243164500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6466410500 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 574512000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2648734000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3243164500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 6466410500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000599 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000365 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001151 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000441 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.000696 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.007524 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.007687 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.007609 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.404026 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.465199 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.435950 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009476 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011708 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010583 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.021718 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.024453 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023095 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000599 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000365 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009476 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.156409 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001151 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000441 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011708 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.187197 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.062806 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000599 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000365 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009476 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.156409 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001151 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000441 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011708 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.187197 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.062806 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76600 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 74000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 75200 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18800 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19227.272727 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19023.809524 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 70500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68224.393189 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67577.858237 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 67864.357557 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 70914.026870 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70522.872502 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 70699.449143 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74671.772623 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72627.403846 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 73581.893344 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70914.026870 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68804.236343 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76600 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 74000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70522.872502 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67993.911166 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 68620.059108 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70914.026870 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68804.236343 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76600 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 74000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70522.872502 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67993.911166 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 68620.059108 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63679.006872 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183990.969714 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193714.281448 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 161016.197709 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63679.006872 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 89885.095697 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 110843.313169 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 95446.582237 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 321037 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 130073 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70471 # Transaction distribution -system.membus.trans_dist::WriteReq 27589 # Transaction distribution -system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118908 # Transaction distribution -system.membus.trans_dist::CleanEvict 6612 # Transaction distribution -system.membus.trans_dist::UpgradeReq 128 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 128846 # Transaction distribution -system.membus.trans_dist::ReadExResp 128846 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30311 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 434701 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 542293 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 615190 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15503164 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15666517 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17983637 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 498 # Total snoops (count) -system.membus.snoopTraffic 31744 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 263260 # Request fanout histogram -system.membus.snoop_fanout::mean 0.018617 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.135167 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 258359 98.14% 98.14% # Request fanout histogram -system.membus.snoop_fanout::1 4901 1.86% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 263260 # Request fanout histogram -system.membus.reqLayer0.occupancy 90452000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1733000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 826968490 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 951904000 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1219623 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks -system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks -system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks -system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks -system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks -system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks -system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks -system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5057608 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2539902 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 38289 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 250 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2903766778500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 74966 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2297117 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 766133 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1697713 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 141921 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2760 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2762 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295798 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295798 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1698231 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 523922 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4401 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5112195 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581153 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16978 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 32189 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7742515 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217374968 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96383645 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20024 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 37420 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 313816057 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 114406 # Total snoops (count) -system.toL2Bus.snoopTraffic 5391284 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2716765 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021720 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.145768 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2657757 97.83% 97.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 59008 2.17% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2716765 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4964781500 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 389377 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2556368500 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1275563497 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11972000 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22834000 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal deleted file mode 100644 index ad91d76dd..000000000 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal +++ /dev/null @@ -1,208 +0,0 @@ -Booting Linux on physical CPU 0x0
-
Initializing cgroup subsys cpuset
-
Linux version 3.13.0-rc2 (tony@vamp) (gcc version 4.8.2 (Ubuntu/Linaro 4.8.2-16ubuntu4) ) #1 SMP PREEMPT Mon Oct 13 15:09:23 EDT 2014
-
Kernel was built at commit id ''
-
CPU: ARMv7 Processor [410fc0f0] revision 0 (ARMv7), cr=10c53c7d
-
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
-
Machine model: V2P-CA15
-
bootconsole [earlycon0] enabled
-
Memory policy: Data cache writealloc
-
kdebugv2m: Following are test values to confirm proper working
-
kdebugv2m: Ranges 42000000 0
-
kdebugv2m: Regs 30000000 1000000
-
kdebugv2m: Virtual-Reg f0000000
-
kdebugv2m: pci node addr_cells 3
-
kdebugv2m: pci node size_cells 2
-
kdebugv2m: motherboard addr_cells 2
-
On node 0 totalpages: 65536
-
free_area_init_node: node 0, pgdat 8072dcc0, node_mem_map 8078f000
-
Normal zone: 512 pages used for memmap
-
Normal zone: 0 pages reserved
-
Normal zone: 65536 pages, LIFO batch:15
-
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956969942ns
-
PERCPU: Embedded 8 pages/cpu @80996000 s11648 r8192 d12928 u32768
-
pcpu-alloc: s11648 r8192 d12928 u32768 alloc=8*4096
-
pcpu-alloc: [0] 0
-
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
-
Kernel command line: earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
-
PID hash table entries: 1024 (order: 0, 4096 bytes)
-
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
-
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
-
Memory: 235688K/262144K available (5248K kernel code, 249K rwdata, 1540K rodata, 295K init, 368K bss, 26456K reserved, 0K highmem)
-
Virtual kernel memory layout:
-
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
-
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
-
vmalloc : 0x90800000 - 0xff000000 (1768 MB)
-
lowmem : 0x80000000 - 0x90000000 ( 256 MB)
-
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
-
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
-
.text : 0x80008000 - 0x806a942c (6790 kB)
-
.init : 0x806aa000 - 0x806f3d80 ( 296 kB)
-
.data : 0x806f4000 - 0x80732754 ( 250 kB)
-
.bss : 0x80732754 - 0x8078e9d8 ( 369 kB)
-
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
-
Preemptible hierarchical RCU implementation.
-
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
-
NR_IRQS:16 nr_irqs:16 16
-
Architected cp15 timer(s) running at 25.16MHz (phys).
-
sched_clock: 56 bits at 25MHz, resolution 39ns, wraps every 2730666655744ns
-
Switching to timer-based delay loop
-
Console: colour dummy device 80x30
-
Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-
pid_max: default: 32768 minimum: 301
-
Mount-cache hash table entries: 512
-
CPU: Testing write buffer coherency: ok
-
CPU0: update cpu_power 1024
-
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
-
Setting up static identity map for 0x804fee68 - 0x804fee9c
-
Brought up 1 CPUs
-
SMP: Total of 1 processors activated.
-
CPU: All CPU(s) started in SVC mode.
-
VFP support v0.3: implementor 41 architecture 4 part 30 variant a rev 0
-
NET: Registered protocol family 16
-
DMA: preallocated 256 KiB pool for atomic coherent allocations
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/aaci@040000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/mmci@050000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-
of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-
hw-breakpoint: Debug register access (0xee113e93) caused undefined instruction on CPU 0
-
hw-breakpoint: Debug register access (0xee013e90) caused undefined instruction on CPU 0
-
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
-
hw-breakpoint: CPU 0 failed to disable vector catch
-
Serial: AMBA PL011 UART driver
-
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-
console [ttyAMA0] enabled
-console [ttyAMA0] enabled
-
bootconsole [earlycon0] disabled
-bootconsole [earlycon0] disabled
-
PCI host bridge to bus 0000:00
-pci_bus 0000:00: root bus resource [io 0x0000-0xffffffff]
-pci_bus 0000:00: root bus resource [mem 0x00000000-0xffffffff]
-pci_bus 0000:00: root bus resource [bus 00-ff]
-pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-PCI: bus0: Fast back to back transfers disabled
-pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-pci 0000:00:01.0: BAR 4: assigned [io 0x2f000000-0x2f00000f]
-pci 0000:00:01.0: BAR 0: assigned [io 0x2f000010-0x2f000017]
-pci 0000:00:01.0: BAR 2: assigned [io 0x2f000018-0x2f00001f]
-pci 0000:00:01.0: BAR 1: assigned [io 0x2f000020-0x2f000023]
-pci 0000:00:01.0: BAR 3: assigned [io 0x2f000024-0x2f000027]
-pci_bus 0000:00: resource 4 [io 0x0000-0xffffffff]
-pci_bus 0000:00: resource 5 [mem 0x00000000-0xffffffff]
-PCI map irq: slot 0, pin 1, devslot 0, irq: 68
-PCI map irq: slot 1, pin 2, devslot 1, irq: 69
-bio: create slab <bio-0> at 0
-vgaarb: loaded
-SCSI subsystem initialized
-libata version 3.00 loaded.
-usbcore: registered new interface driver usbfs
-usbcore: registered new interface driver hub
-usbcore: registered new device driver usb
-pps_core: LinuxPPS API ver. 1 registered
-pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-PTP clock support registered
-Advanced Linux Sound Architecture Driver Initialized.
-Switched to clocksource arch_sys_counter
-NET: Registered protocol family 2
-TCP established hash table entries: 2048 (order: 1, 8192 bytes)
-TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
-TCP: Hash tables configured (established 2048 bind 2048)
-TCP: reno registered
-UDP hash table entries: 256 (order: 1, 8192 bytes)
-UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-NET: Registered protocol family 1
-RPC: Registered named UNIX socket transport module.
-RPC: Registered udp transport module.
-RPC: Registered tcp transport module.
-RPC: Registered tcp NFSv4.1 backchannel transport module.
-PCI: CLS 64 bytes, default 64
-hw perfevents: enabled with ARMv7_Cortex_A15 PMU driver, 1 counters available
-jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
-msgmni has been set to 460
-io scheduler noop registered (default)
-brd: module loaded
-loop: module loaded
-ata_piix 0000:00:01.0: version 2.13
-PCI: enabling device 0000:00:01.0 (0040 -> 0041)
-scsi0 : ata_piix
-scsi1 : ata_piix
-ata1: PATA max UDMA/33 cmd 0x2f000010 ctl 0x2f000020 bmdma 0x2f000000 irq 69
-ata2: PATA max UDMA/33 cmd 0x2f000018 ctl 0x2f000024 bmdma 0x2f000008 irq 69
-e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI
-e100: Copyright(c) 1999-2006 Intel Corporation
-e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-e1000: Copyright (c) 1999-2006 Intel Corporation.
-PCI: enabling device 0000:00:00.0 (0040 -> 0042)
-ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-ata1.00: 1048320 sectors, multi 0: LBA
-ata1.00: configured for UDMA/33
-scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
-sd 0:0:0:0: [sda] Write Protect is off
-sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
- sda: sda1
-sd 0:0:0:0: Attached scsi generic sg0 type 0
-sd 0:0:0:0: [sda] Attached SCSI disk
-e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-e1000e: Copyright(c) 1999 - 2013 Intel Corporation.
-igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-igb: Copyright (c) 2007-2013 Intel Corporation.
-igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.0.2-k
-igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
-ixgbe: Intel(R) 10 Gigabit PCI Express Network Driver - version 3.15.1-k
-ixgbe: Copyright (c) 1999-2013 Intel Corporation.
-ixgbevf: Intel(R) 10 Gigabit PCI Express Virtual Function Network Driver - version 2.11.3-k
-ixgbevf: Copyright (c) 2009 - 2012 Intel Corporation.
-ixgb: Intel(R) PRO/10GbE Network Driver - version 1.0.135-k2-NAPI
-ixgb: Copyright (c) 1999-2008 Intel Corporation.
-smsc911x: Driver version 2008-10-21
-smsc911x 1a000000.ethernet (unregistered net_device): couldn't get clock -2
-nxp-isp1760 1b000000.usb: NXP ISP1760 USB Host Controller
-nxp-isp1760 1b000000.usb: new USB bus registered, assigned bus number 1
-nxp-isp1760 1b000000.usb: Scratch test failed.
-nxp-isp1760 1b000000.usb: can't setup: -19
-nxp-isp1760 1b000000.usb: USB bus 1 deregistered
-usbcore: registered new interface driver usb-storage
-mousedev: PS/2 mouse device common for all mice
-rtc-pl031 1c170000.rtc: rtc core: registered pl031 as rtc0
-usbcore: registered new interface driver usbhid
-usbhid: USB HID core driver
-ashmem: initialized
-logger: created 256K log 'log_main'
-logger: created 256K log 'log_events'
-logger: created 256K log 'log_radio'
-logger: created 256K log 'log_system'
-oprofile: using timer interrupt.
-TCP: cubic registered
-NET: Registered protocol family 10
-NET: Registered protocol family 17
-rtc-pl031 1c170000.rtc: setting system clock to 2009-01-01 00:00:00 UTC (1230768000)
-ALSA device list:
- No soundcards found.
- -input: touchkitPS/2 eGalax Touchscreen as /devices/smb.14/motherboard.15/iofpga.17/1c070000.kmi/serio1/input/input2
-VFS: Mounted root (ext2 filesystem) on device 8:1.
-Freeing unused kernel memory: 292K (806aa000 - 806f3000)
-
init started: BusyBox v1.15.3 (2010-05-07 01:27:07 BST)
-
starting pid 673, tty '': '/etc/rc.d/rc.local'
-warning: can't open /etc/mtab: No such file or directory
-Thu Jan 1 00:00:02 UTC 2009
-S: devpts
-Thu Jan 1 00:00:02 UTC 2009
|