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-rw-r--r--src/arch/alpha/isa/decoder.isa6
-rw-r--r--src/arch/mips/isa/decoder.isa4
-rw-r--r--src/arch/x86/isa/decoder/one_byte_opcodes.isa2
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa4
-rw-r--r--src/cpu/base.hh2
-rw-r--r--src/sim/full_system.hh12
-rw-r--r--src/sim/root.cc2
7 files changed, 23 insertions, 9 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 4bbf83cce..9785e217c 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -805,14 +805,14 @@ decode OPCODE default Unknown::unknown() {
0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
}
- 0xe000: decode FullSystem {
+ 0xe000: decode FullSystemInt {
0: FailUnimpl::rc_se();
default: BasicOperate::rc({{
Ra = IntrFlag;
IntrFlag = 0;
}}, IsNonSpeculative, IsUnverifiable);
}
- 0xf000: decode FullSystem {
+ 0xf000: decode FullSystemInt {
0: FailUnimpl::rs_se();
default: BasicOperate::rs({{
Ra = IntrFlag;
@@ -821,7 +821,7 @@ decode OPCODE default Unknown::unknown() {
}
}
- 0x00: decode FullSystem {
+ 0x00: decode FullSystemInt {
0: decode PALFUNC {
format EmulatedCallPal {
0x00: halt ({{
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 034133f96..1091e67a0 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -163,7 +163,7 @@ decode OPCODE_HI default Unknown::unknown() {
format BasicOp {
0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
- 0x4: decode FullSystem {
+ 0x4: decode FullSystemInt {
0: syscall_se({{ xc->syscall(R2); }},
IsSerializeAfter, IsNonSpeculative);
default: syscall({{ fault = new SystemCallFault(); }});
@@ -2431,7 +2431,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
}
0x3: decode OP default FailUnimpl::rdhwr() {
- 0x0: decode FullSystem {
+ 0x0: decode FullSystemInt {
0: decode RD {
29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
}
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 4ebf23032..66a0c8c46 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -394,7 +394,7 @@
default: Inst::RET_FAR();
}
0x4: int3();
- 0x5: decode FullSystem default int_Ib() {
+ 0x5: decode FullSystemInt default int_Ib() {
0: decode IMMEDIATE {
// Really only the LSB matters, but the predecoder
// will sign extend it, and there's no easy way to
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 030e36404..378d426e3 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -216,7 +216,7 @@
default: Inst::UD2();
}
}
- 0x05: decode FullSystem {
+ 0x05: decode FullSystemInt {
0: SyscallInst::syscall('xc->syscall(Rax)',
IsSyscall, IsNonSpeculative, IsSerializeAfter);
default: decode MODE_MODE {
@@ -398,7 +398,7 @@
0x1: Inst::RDTSC();
0x2: Inst::RDMSR();
0x3: rdpmc();
- 0x4: decode FullSystem {
+ 0x4: decode FullSystemInt {
0: SyscallInst::sysenter('xc->syscall(Rax)',
IsSyscall, IsNonSpeculative, IsSerializeAfter);
default: sysenter();
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 74bb8dc12..149d26aa3 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -58,7 +58,7 @@
#include "sim/full_system.hh"
#include "sim/insttracer.hh"
-class BaseCPUParams;
+struct BaseCPUParams;
class BranchPred;
class CheckerCPU;
class ThreadContext;
diff --git a/src/sim/full_system.hh b/src/sim/full_system.hh
index e67fc11a9..18cf34d09 100644
--- a/src/sim/full_system.hh
+++ b/src/sim/full_system.hh
@@ -31,6 +31,18 @@
#ifndef __SIM_FULL_SYSTEM_HH__
#define __SIM_FULL_SYSTEM_HH__
+/**
+ * The FullSystem variable can be used to determine the current mode
+ * of simulation.
+ */
extern bool FullSystem;
+/**
+ * In addition to the boolean flag we make use of an unsigned int
+ * since the CPU instruction decoder makes use of the variable in
+ * switch statements. A value of 0 signifies syscall emulation, and
+ * any other value full system.
+ */
+extern unsigned int FullSystemInt;
+
#endif // __SIM_FULL_SYSTEM_HH__
diff --git a/src/sim/root.cc b/src/sim/root.cc
index c47ada30e..2d28499a7 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -125,6 +125,7 @@ Root::loadState(Checkpoint *cp)
}
bool FullSystem;
+unsigned int FullSystemInt;
Root *
RootParams::create()
@@ -136,6 +137,7 @@ RootParams::create()
created = true;
FullSystem = full_system;
+ FullSystemInt = full_system ? 1 : 0;
return new Root(this);
}