diff options
| -rw-r--r-- | arch/mips/isa/formats/branch.isa | 57 | ||||
| -rw-r--r-- | cpu/base.hh | 4 | ||||
| -rw-r--r-- | cpu/exec_context.hh | 40 | ||||
| -rw-r--r-- | cpu/static_inst.hh | 10 |
4 files changed, 81 insertions, 30 deletions
diff --git a/arch/mips/isa/formats/branch.isa b/arch/mips/isa/formats/branch.isa index c003cb63d..d9dd433e3 100644 --- a/arch/mips/isa/formats/branch.isa +++ b/arch/mips/isa/formats/branch.isa @@ -116,6 +116,12 @@ output decoder {{ } Addr + BranchLikely::branchTarget(Addr branchPC) const + { + return branchPC + 4 + disp; + } + + Addr Jump::branchTarget(ExecContext *xc) const { Addr NPC = xc->readPC() + 4; @@ -181,6 +187,44 @@ output decoder {{ } std::string + BranchLikely::generateDisassembly(Addr pc, const SymbolTable *symtab) const + { + std::stringstream ss; + + ccprintf(ss, "%-10s ", mnemonic); + + // There's only one register arg (RA), but it could be + // either a source (the condition for conditional + // branches) or a destination (the link reg for + // unconditional branches) + if (_numSrcRegs > 0) { + printReg(ss, _srcRegIdx[0]); + ss << ","; + } + else if (_numDestRegs > 0) { + printReg(ss, _destRegIdx[0]); + ss << ","; + } + +#ifdef SS_COMPATIBLE_DISASSEMBLY + if (_numSrcRegs == 0 && _numDestRegs == 0) { + printReg(ss, 31); + ss << ","; + } +#endif + + Addr target = pc + 4 + disp; + + std::string str; + if (symtab && symtab->findSymbol(target, str)) + ss << str; + else + ccprintf(ss, "0x%x", target); + + return ss.str(); + } + + std::string Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; @@ -205,16 +249,10 @@ output decoder {{ } }}; - -def template JumpOrBranchDecode {{ - return (RD == 0) - ? (StaticInst<MipsISA> *)new %(class_name)s(machInst) - : (StaticInst<MipsISA> *)new %(class_name)sAndLink(machInst); -}}; - def format Branch(code,*flags) {{ code = 'bool cond;\n\t' + code + '\n' + #Add Link Code if Link instruction strlen = len(name) if name[strlen-2:] == 'al': code += 'R31 = NPC + 8;\n' @@ -230,12 +268,15 @@ def format Branch(code,*flags) {{ }}; def format BranchLikely(code,*flags) {{ - code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n'; + code = 'bool cond;\n\t\t\t' + code + #Add Link Code if Link instruction strlen = len(name) if name[strlen-3:] == 'all': code += 'R31 = NPC + 8;\n' + code = '\t\t\tif (cond) NPC = NPC + disp;\n'; + iop = InstObjParams(name, Name, 'Branch', CodeBlock(code), ('IsDirectControl', 'IsCondControl','IsCondDelaySlot')) header_output = BasicDeclare.subst(iop) diff --git a/cpu/base.hh b/cpu/base.hh index 2bd1210d8..09a73ab16 100644 --- a/cpu/base.hh +++ b/cpu/base.hh @@ -36,7 +36,7 @@ #include "cpu/sampler/sampler.hh" #include "sim/eventq.hh" #include "sim/sim_object.hh" -#include "arch/isa_traits.hh" +#include "targetarch/isa_traits.hh" #if FULL_SYSTEM class System; @@ -140,6 +140,8 @@ class BaseCPU : public SimObject virtual void startup(); virtual void regStats(); + virtual void activateWhenReady(int tid) {}; + void registerExecContexts(); /// Prepare for another CPU to take over execution. When it is diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index 7e195af23..845f9264b 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -80,7 +80,7 @@ class ExecContext Active, /// Temporarily inactive. Entered while waiting for - /// synchronization, etc. + /// initialization,synchronization, etc. Suspended, /// Permanently shut down. Entered when target executes @@ -95,6 +95,8 @@ class ExecContext public: Status status() const { return _status; } + void setStatus(Status newStatus) { _status = newStatus; } + /// Set the status to Active. Optional delay indicates number of /// cycles to wait before beginning execution. void activate(int delay = 1); @@ -206,17 +208,17 @@ class ExecContext int getInstAsid() { return regs.instAsid(); } int getDataAsid() { return regs.dataAsid(); } - Fault * translateInstReq(MemReqPtr &req) + Fault translateInstReq(MemReqPtr &req) { return itb->translate(req); } - Fault * translateDataReadReq(MemReqPtr &req) + Fault translateDataReadReq(MemReqPtr &req) { return dtb->translate(req, false); } - Fault * translateDataWriteReq(MemReqPtr &req) + Fault translateDataWriteReq(MemReqPtr &req) { return dtb->translate(req, true); } @@ -231,7 +233,7 @@ class ExecContext int getInstAsid() { return asid; } int getDataAsid() { return asid; } - Fault * dummyTranslation(MemReqPtr &req) + Fault dummyTranslation(MemReqPtr &req) { #if 0 assert((req->vaddr >> 48 & 0xffff) == 0); @@ -240,17 +242,17 @@ class ExecContext // put the asid in the upper 16 bits of the paddr req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; - return NoFault; + return No_Fault; } - Fault * translateInstReq(MemReqPtr &req) + Fault translateInstReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault * translateDataReadReq(MemReqPtr &req) + Fault translateDataReadReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault * translateDataWriteReq(MemReqPtr &req) + Fault translateDataWriteReq(MemReqPtr &req) { return dummyTranslation(req); } @@ -258,7 +260,7 @@ class ExecContext #endif template <class T> - Fault * read(MemReqPtr &req, T &data) + Fault read(MemReqPtr &req, T &data) { #if FULL_SYSTEM && defined(TARGET_ALPHA) if (req->flags & LOCKED) { @@ -268,14 +270,14 @@ class ExecContext } #endif - Fault * error; + Fault error; error = mem->read(req, data); data = LittleEndianGuest::gtoh(data); return error; } template <class T> - Fault * write(MemReqPtr &req, T &data) + Fault write(MemReqPtr &req, T &data) { #if FULL_SYSTEM && defined(TARGET_ALPHA) @@ -301,7 +303,7 @@ class ExecContext << "on cpu " << req->xc->cpu_id << std::endl; } - return NoFault; + return No_Fault; } else req->xc->storeCondFailures = 0; } @@ -333,7 +335,7 @@ class ExecContext inst = new_inst; } - Fault * instRead(MemReqPtr &req) + Fault instRead(MemReqPtr &req) { return mem->read(req, inst); } @@ -412,13 +414,13 @@ class ExecContext } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault * &fault); - Fault * setIpr(int idx, uint64_t val); + uint64_t readIpr(int idx, Fault &fault); + Fault setIpr(int idx, uint64_t val); int readIntrFlag() { return regs.intrflag; } void setIntrFlag(int val) { regs.intrflag = val; } - Fault * hwrei(); + Fault hwrei(); bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } - void ev5_trap(Fault * fault); + void ev5_trap(Fault fault); bool simPalCheck(int palFunc); #endif @@ -428,7 +430,7 @@ class ExecContext * @todo How to do this properly so it's dependent upon ISA only? */ - void trap(Fault * fault); + void trap(Fault fault); #if !FULL_SYSTEM IntReg getSyscallArg(int i) diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index 24997eadc..c574173c2 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -36,7 +36,7 @@ #include "base/refcnt.hh" #include "encumbered/cpu/full/op_class.hh" #include "sim/host.hh" -#include "arch/isa_traits.hh" +#include "targetarch/isa_traits.hh" // forward declarations struct AlphaSimpleImpl; @@ -113,6 +113,8 @@ class StaticInstBase : public RefCounted IsSerializing, ///< Serializes pipeline: won't execute until all /// older instructions have committed. + IsSerializeBefore, + IsSerializeAfter, IsMemBarrier, ///< Is a memory barrier IsWriteBarrier, ///< Is a write barrier @@ -196,7 +198,11 @@ class StaticInstBase : public RefCounted bool isUncondCtrl() const { return flags[IsUncondControl]; } bool isThreadSync() const { return flags[IsThreadSync]; } - bool isSerializing() const { return flags[IsSerializing]; } + bool isSerializing() const { return flags[IsSerializing] || + flags[IsSerializeBefore] || + flags[IsSerializeAfter]; } + bool isSerializeBefore() const { return flags[IsSerializeBefore]; } + bool isSerializeAfter() const { return flags[IsSerializeAfter]; } bool isMemBarrier() const { return flags[IsMemBarrier]; } bool isWriteBarrier() const { return flags[IsWriteBarrier]; } bool isNonSpeculative() const { return flags[IsNonSpeculative]; } |