diff options
| -rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 32 |
1 files changed, 26 insertions, 6 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index a45048ff9..f22383506 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -1021,13 +1021,33 @@ LSQUnit<Impl>::updateVisibleState() inst->seqNum, inst->pcState()); } inst->fenceDelay(false); - }else { - if (!inst->fenceDelay()){ - DPRINTF(LSQUnit, "Deffering an inst [sn:%lli] PC %s" - " due to virtual fence\n", - inst->seqNum, inst->pcState()); + } else { + if (!useIFT) { + if (!inst->fenceDelay()){ + DPRINTF(LSQUnit, "Deffering an inst [sn:%lli] PC %s" + " due to virtual fence\n", + inst->seqNum, inst->pcState()); + } + inst->fenceDelay(true); + } else { + /* set taint for dst registers */ + inst->taintDestRegs(true, "unsafe load"); + bool doSpecLoad = false; + if (inst->afterTaintedBranch) { + doSpecLoad = true; + DPRINTF(LSQUnit, "load inst [sn:%lli] %s is after a tainted branch.\n", inst->seqNum, inst->pcState()); + } else if (inst->srcTainted()) { + doSpecLoad = true; + DPRINTF(LSQUnit, "source registers of load inst [sn:%lli] %s is tainted.\n", inst->seqNum, inst->pcState()); + } + if (doSpecLoad) { + DPRINTF(LSQUnit, "load inst [sn:%lli] %s not safe, defer it.\n", inst->seqNum, inst->pcState()); + inst->fenceDelay(true); + } else { + DPRINTF(LSQUnit, "load inst [sn:%lli] %s is an unsafe speculated load, but source registers are not tainted.\n", inst->seqNum, inst->pcState()); + inst->fenceDelay(false); + } } - inst->fenceDelay(true); } inst->readyToExpose(true); } else if (loadInExec && isInvisibleSpec){ |