diff options
122 files changed, 232 insertions, 22 deletions
diff --git a/src/SConscript b/src/SConscript index 69a452ac6..9af71c9a6 100755 --- a/src/SConscript +++ b/src/SConscript @@ -451,6 +451,12 @@ sys.meta_path.remove(importer) sim_objects = m5.SimObject.allClasses all_enums = m5.params.allEnums +if m5.SimObject.noCxxHeader: + print >> sys.stderr, \ + "warning: At least one SimObject lacks a header specification. " \ + "This can cause unexpected results in the generated SWIG " \ + "wrappers." + # Find param types that need to be explicitly wrapped with swig. # These will be recognized because the ParamDesc will have a # swig_decl() method. Most param types are based on types that don't diff --git a/src/arch/alpha/AlphaInterrupts.py b/src/arch/alpha/AlphaInterrupts.py index ecfcf5c21..a75b11fc0 100644 --- a/src/arch/alpha/AlphaInterrupts.py +++ b/src/arch/alpha/AlphaInterrupts.py @@ -31,3 +31,4 @@ from m5.SimObject import SimObject class AlphaInterrupts(SimObject): type = 'AlphaInterrupts' cxx_class = 'AlphaISA::Interrupts' + cxx_header = "arch/alpha/interrupts.hh" diff --git a/src/arch/alpha/AlphaSystem.py b/src/arch/alpha/AlphaSystem.py index fcbe81edd..2486ec059 100644 --- a/src/arch/alpha/AlphaSystem.py +++ b/src/arch/alpha/AlphaSystem.py @@ -32,6 +32,7 @@ from System import System class AlphaSystem(System): type = 'AlphaSystem' + cxx_header = "arch/alpha/system.hh" console = Param.String("file that contains the console code") pal = Param.String("file that contains palcode") system_type = Param.UInt64("Type of system we are emulating") @@ -40,6 +41,7 @@ class AlphaSystem(System): class LinuxAlphaSystem(AlphaSystem): type = 'LinuxAlphaSystem' + cxx_header = "arch/alpha/linux/system.hh" system_type = 34 system_rev = 1 << 10 @@ -48,10 +50,12 @@ class LinuxAlphaSystem(AlphaSystem): class FreebsdAlphaSystem(AlphaSystem): type = 'FreebsdAlphaSystem' + cxx_header = "arch/alpha/freebsd/system.hh" system_type = 34 system_rev = 1 << 10 class Tru64AlphaSystem(AlphaSystem): type = 'Tru64AlphaSystem' + cxx_header = "arch/alpha/tru64/system.hh" system_type = 12 system_rev = 2<<1 diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py index 51f636ec2..8031c719f 100644 --- a/src/arch/alpha/AlphaTLB.py +++ b/src/arch/alpha/AlphaTLB.py @@ -34,6 +34,7 @@ from BaseTLB import BaseTLB class AlphaTLB(BaseTLB): type = 'AlphaTLB' cxx_class = 'AlphaISA::TLB' + cxx_header = "arch/alpha/tlb.hh" size = Param.Int("TLB size") class AlphaDTB(AlphaTLB): diff --git a/src/arch/arm/ArmInterrupts.py b/src/arch/arm/ArmInterrupts.py index f21d49e95..68a58958d 100644 --- a/src/arch/arm/ArmInterrupts.py +++ b/src/arch/arm/ArmInterrupts.py @@ -31,3 +31,4 @@ from m5.SimObject import SimObject class ArmInterrupts(SimObject): type = 'ArmInterrupts' cxx_class = 'ArmISA::Interrupts' + cxx_header = "arch/arm/interrupts.hh" diff --git a/src/arch/arm/ArmNativeTrace.py b/src/arch/arm/ArmNativeTrace.py index 0a76913e3..91da1ed76 100644 --- a/src/arch/arm/ArmNativeTrace.py +++ b/src/arch/arm/ArmNativeTrace.py @@ -33,5 +33,6 @@ from NativeTrace import NativeTrace class ArmNativeTrace(NativeTrace): type = 'ArmNativeTrace' cxx_class = 'Trace::ArmNativeTrace' + cxx_header = "arch/arm/nativetrace.hh" stop_on_pc_error = Param.Bool(True, "Stop M5 if it and statetrace's pcs are different") diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py index 3ca9b8573..ce363865c 100644 --- a/src/arch/arm/ArmSystem.py +++ b/src/arch/arm/ArmSystem.py @@ -48,6 +48,7 @@ class ArmMachineType(Enum): class ArmSystem(System): type = 'ArmSystem' + cxx_header = "arch/arm/system.hh" load_addr_mask = 0xffffffff # 0x35 Implementor is '5' from "M5" # 0x0 Variant @@ -62,6 +63,7 @@ class ArmSystem(System): class LinuxArmSystem(ArmSystem): type = 'LinuxArmSystem' + cxx_header = "arch/arm/linux/system.hh" load_addr_mask = 0x0fffffff machine_type = Param.ArmMachineType('RealView_PBX', "Machine id from http://www.arm.linux.org.uk/developer/machines/") diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index 0a931b7e5..c70dd80c8 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -45,6 +45,7 @@ from MemObject import MemObject class ArmTableWalker(MemObject): type = 'ArmTableWalker' cxx_class = 'ArmISA::TableWalker' + cxx_header = "arch/arm/table_walker.hh" port = MasterPort("Port for TableWalker to do walk the translation with") sys = Param.System(Parent.any, "system object parameter") num_squash_per_cycle = Param.Unsigned(2, @@ -53,5 +54,6 @@ class ArmTableWalker(MemObject): class ArmTLB(SimObject): type = 'ArmTLB' cxx_class = 'ArmISA::TLB' + cxx_header = "arch/arm/tlb.hh" size = Param.Int(64, "TLB size") walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker") diff --git a/src/arch/mips/MipsInterrupts.py b/src/arch/mips/MipsInterrupts.py index 06cd54263..9cde5daef 100644 --- a/src/arch/mips/MipsInterrupts.py +++ b/src/arch/mips/MipsInterrupts.py @@ -31,3 +31,4 @@ from m5.SimObject import SimObject class MipsInterrupts(SimObject): type = 'MipsInterrupts' cxx_class = 'MipsISA::Interrupts' + cxx_header = 'arch/mips/interrupts.hh' diff --git a/src/arch/mips/MipsSystem.py b/src/arch/mips/MipsSystem.py index 4a0851eba..c6ceb71db 100644 --- a/src/arch/mips/MipsSystem.py +++ b/src/arch/mips/MipsSystem.py @@ -36,6 +36,7 @@ from System import System class MipsSystem(System): type = 'MipsSystem' + cxx_header = 'arch/mips/system.hh' console = Param.String("file that contains the console code") bare_iron = Param.Bool(False, "Using Bare Iron Mode?") hex_file_name = Param.String("test.hex","hex file that contains [address,data] pairs") @@ -45,6 +46,7 @@ class MipsSystem(System): class LinuxMipsSystem(MipsSystem): type = 'LinuxMipsSystem' + cxx_header = 'arch/mips/linux/system.hh' system_type = 34 system_rev = 1 << 10 @@ -53,6 +55,7 @@ class LinuxMipsSystem(MipsSystem): class BareIronMipsSystem(MipsSystem): type = 'BareIronMipsSystem' + cxx_header = 'arch/mips/bare_iron/system.hh' bare_iron = True system_type = 34 system_rev = 1 << 10 diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py index 16cbe6879..c43cee717 100644 --- a/src/arch/mips/MipsTLB.py +++ b/src/arch/mips/MipsTLB.py @@ -37,4 +37,5 @@ from BaseTLB import BaseTLB class MipsTLB(BaseTLB): type = 'MipsTLB' cxx_class = 'MipsISA::TLB' + cxx_header = 'arch/mips/tlb.hh' size = Param.Int(64, "TLB size") diff --git a/src/arch/power/PowerInterrupts.py b/src/arch/power/PowerInterrupts.py index 82d614077..2c6a5c2c3 100644 --- a/src/arch/power/PowerInterrupts.py +++ b/src/arch/power/PowerInterrupts.py @@ -31,3 +31,4 @@ from m5.SimObject import SimObject class PowerInterrupts(SimObject): type = 'PowerInterrupts' cxx_class = 'PowerISA::Interrupts' + cxx_header = 'arch/power/interrupts.hh' diff --git a/src/arch/power/PowerTLB.py b/src/arch/power/PowerTLB.py index 36dff5333..ae6503a1f 100644 --- a/src/arch/power/PowerTLB.py +++ b/src/arch/power/PowerTLB.py @@ -34,4 +34,5 @@ from m5.params import * class PowerTLB(SimObject): type = 'PowerTLB' cxx_class = 'PowerISA::TLB' + cxx_header = 'arch/power/tlb.hh' size = Param.Int(64, "TLB size") diff --git a/src/arch/sparc/SparcInterrupts.py b/src/arch/sparc/SparcInterrupts.py index 2cc964c2d..c11176164 100644 --- a/src/arch/sparc/SparcInterrupts.py +++ b/src/arch/sparc/SparcInterrupts.py @@ -31,3 +31,4 @@ from m5.SimObject import SimObject class SparcInterrupts(SimObject): type = 'SparcInterrupts' cxx_class = 'SparcISA::Interrupts' + cxx_header = 'arch/sparc/interrupts.hh' diff --git a/src/arch/sparc/SparcNativeTrace.py b/src/arch/sparc/SparcNativeTrace.py index 0a92764ef..cdc34b541 100644 --- a/src/arch/sparc/SparcNativeTrace.py +++ b/src/arch/sparc/SparcNativeTrace.py @@ -33,3 +33,4 @@ from NativeTrace import NativeTrace class SparcNativeTrace(NativeTrace): type = 'SparcNativeTrace' cxx_class = 'Trace::SparcNativeTrace' + cxx_header = 'arch/sparc/nativetrace.hh' diff --git a/src/arch/sparc/SparcSystem.py b/src/arch/sparc/SparcSystem.py index b0fddf311..9d8be5d06 100644 --- a/src/arch/sparc/SparcSystem.py +++ b/src/arch/sparc/SparcSystem.py @@ -33,6 +33,7 @@ from System import System class SparcSystem(System): type = 'SparcSystem' + cxx_header = 'arch/sparc/system.hh' _rom_base = 0xfff0000000 _nvram_base = 0x1f11000000 _hypervisor_desc_base = 0x1f12080000 diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py index 0c3fdc7fb..219f6842a 100644 --- a/src/arch/sparc/SparcTLB.py +++ b/src/arch/sparc/SparcTLB.py @@ -34,4 +34,5 @@ from BaseTLB import BaseTLB class SparcTLB(BaseTLB): type = 'SparcTLB' cxx_class = 'SparcISA::TLB' + cxx_header = 'arch/sparc/tlb.hh' size = Param.Int(64, "TLB size") diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py index 0bc36612d..5c14679c2 100644 --- a/src/arch/x86/X86LocalApic.py +++ b/src/arch/x86/X86LocalApic.py @@ -46,6 +46,7 @@ from Device import BasicPioDevice class X86LocalApic(BasicPioDevice): type = 'X86LocalApic' cxx_class = 'X86ISA::Interrupts' + cxx_header = 'arch/x86/interrupts.hh' int_master = MasterPort("Port for sending interrupt messages") int_slave = SlavePort("Port for receiving interrupt messages") int_latency = Param.Latency('1ns', \ diff --git a/src/arch/x86/X86NativeTrace.py b/src/arch/x86/X86NativeTrace.py index cbed77f37..281a2df50 100644 --- a/src/arch/x86/X86NativeTrace.py +++ b/src/arch/x86/X86NativeTrace.py @@ -33,3 +33,4 @@ from NativeTrace import NativeTrace class X86NativeTrace(NativeTrace): type = 'X86NativeTrace' cxx_class = 'Trace::X86NativeTrace' + cxx_header = 'arch/x86/nativetrace.hh' diff --git a/src/arch/x86/X86System.py b/src/arch/x86/X86System.py index 8b294fb86..02185b648 100644 --- a/src/arch/x86/X86System.py +++ b/src/arch/x86/X86System.py @@ -44,6 +44,7 @@ from System import System class X86System(System): type = 'X86System' + cxx_header = 'arch/x86/system.hh' smbios_table = Param.X86SMBiosSMBiosTable( X86SMBiosSMBiosTable(), 'table of smbios/dmi information') intel_mp_pointer = Param.X86IntelMPFloatingPointer( @@ -58,6 +59,7 @@ class X86System(System): class LinuxX86System(X86System): type = 'LinuxX86System' + cxx_header = 'arch/x86/linux/system.hh' e820_table = Param.X86E820Table( X86E820Table(), 'E820 map of physical memory') diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index 334d2a0cf..a08dbb138 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -44,12 +44,14 @@ from MemObject import MemObject class X86PagetableWalker(MemObject): type = 'X86PagetableWalker' cxx_class = 'X86ISA::Walker' + cxx_header = 'arch/x86/pagetable_walker.hh' port = MasterPort("Port for the hardware table walker") system = Param.System(Parent.any, "system object") class X86TLB(BaseTLB): type = 'X86TLB' cxx_class = 'X86ISA::TLB' + cxx_header = 'arch/x86/tlb.hh' size = Param.Int(64, "TLB size") walker = Param.X86PagetableWalker(\ X86PagetableWalker(), "page table walker") diff --git a/src/arch/x86/bios/ACPI.py b/src/arch/x86/bios/ACPI.py index 671ed902d..77de42f92 100644 --- a/src/arch/x86/bios/ACPI.py +++ b/src/arch/x86/bios/ACPI.py @@ -41,6 +41,7 @@ from m5.SimObject import SimObject class X86ACPISysDescTable(SimObject): type = 'X86ACPISysDescTable' cxx_class = 'X86ISA::ACPI::SysDescTable' + cxx_header = 'arch/x86/bios/acpi.hh' abstract = True oem_id = Param.String('', 'string identifying the oem') @@ -55,12 +56,14 @@ class X86ACPISysDescTable(SimObject): class X86ACPIRSDT(X86ACPISysDescTable): type = 'X86ACPIRSDT' cxx_class = 'X86ISA::ACPI::RSDT' + cxx_header = 'arch/x86/bios/acpi.hh' entries = VectorParam.X86ACPISysDescTable([], 'system description tables') class X86ACPIXSDT(X86ACPISysDescTable): type = 'X86ACPIXSDT' cxx_class = 'X86ISA::ACPI::XSDT' + cxx_header = 'arch/x86/bios/acpi.hh' entries = VectorParam.X86ACPISysDescTable([], 'system description tables') @@ -68,6 +71,7 @@ class X86ACPIXSDT(X86ACPISysDescTable): class X86ACPIRSDP(SimObject): type = 'X86ACPIRSDP' cxx_class = 'X86ISA::ACPI::RSDP' + cxx_header = 'arch/x86/bios/acpi.hh' oem_id = Param.String('', 'string identifying the oem') # Because 0 encodes ACPI 1.0, 2 encodes ACPI 3.0, the version implemented diff --git a/src/arch/x86/bios/E820.py b/src/arch/x86/bios/E820.py index 78b5faee0..9fa18edbd 100644 --- a/src/arch/x86/bios/E820.py +++ b/src/arch/x86/bios/E820.py @@ -41,6 +41,7 @@ from m5.SimObject import SimObject class X86E820Entry(SimObject): type = 'X86E820Entry' cxx_class = 'X86ISA::E820Entry' + cxx_header = 'arch/x86/bios/e820.hh' addr = Param.Addr(0, 'address of the beginning of the region') size = Param.MemorySize('0B', 'size of the region') @@ -49,5 +50,6 @@ class X86E820Entry(SimObject): class X86E820Table(SimObject): type = 'X86E820Table' cxx_class = 'X86ISA::E820Table' + cxx_header = 'arch/x86/bios/e820.hh' entries = VectorParam.X86E820Entry('entries for the e820 table') diff --git a/src/arch/x86/bios/IntelMP.py b/src/arch/x86/bios/IntelMP.py index 713f62960..21f93eaad 100644 --- a/src/arch/x86/bios/IntelMP.py +++ b/src/arch/x86/bios/IntelMP.py @@ -41,6 +41,7 @@ from m5.SimObject import SimObject class X86IntelMPFloatingPointer(SimObject): type = 'X86IntelMPFloatingPointer' cxx_class = 'X86ISA::IntelMP::FloatingPointer' + cxx_header = 'arch/x86/bios/intelmp.hh' # The minor revision of the spec to support. The major version is assumed # to be 1 in accordance with the spec. @@ -53,6 +54,7 @@ class X86IntelMPFloatingPointer(SimObject): class X86IntelMPConfigTable(SimObject): type = 'X86IntelMPConfigTable' cxx_class = 'X86ISA::IntelMP::ConfigTable' + cxx_header = 'arch/x86/bios/intelmp.hh' spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported') oem_id = Param.String("", 'system manufacturer') @@ -80,16 +82,19 @@ class X86IntelMPConfigTable(SimObject): class X86IntelMPBaseConfigEntry(SimObject): type = 'X86IntelMPBaseConfigEntry' cxx_class = 'X86ISA::IntelMP::BaseConfigEntry' + cxx_header = 'arch/x86/bios/intelmp.hh' abstract = True class X86IntelMPExtConfigEntry(SimObject): type = 'X86IntelMPExtConfigEntry' cxx_class = 'X86ISA::IntelMP::ExtConfigEntry' + cxx_header = 'arch/x86/bios/intelmp.hh' abstract = True class X86IntelMPProcessor(X86IntelMPBaseConfigEntry): type = 'X86IntelMPProcessor' cxx_class = 'X86ISA::IntelMP::Processor' + cxx_header = 'arch/x86/bios/intelmp.hh' local_apic_id = Param.UInt8(0, 'local APIC id') local_apic_version = Param.UInt8(0, @@ -106,6 +111,7 @@ class X86IntelMPProcessor(X86IntelMPBaseConfigEntry): class X86IntelMPBus(X86IntelMPBaseConfigEntry): type = 'X86IntelMPBus' cxx_class = 'X86ISA::IntelMP::Bus' + cxx_header = 'arch/x86/bios/intelmp.hh' bus_id = Param.UInt8(0, 'bus id assigned by the bios') bus_type = Param.String("", 'string that identify the bus type') @@ -118,6 +124,7 @@ class X86IntelMPBus(X86IntelMPBaseConfigEntry): class X86IntelMPIOAPIC(X86IntelMPBaseConfigEntry): type = 'X86IntelMPIOAPIC' cxx_class = 'X86ISA::IntelMP::IOAPIC' + cxx_header = 'arch/x86/bios/intelmp.hh' id = Param.UInt8(0, 'id of this APIC') version = Param.UInt8(0, 'bits 0-7 of the version register') @@ -148,6 +155,7 @@ class X86IntelMPTriggerMode(Enum): class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry): type = 'X86IntelMPIOIntAssignment' cxx_class = 'X86ISA::IntelMP::IOIntAssignment' + cxx_header = 'arch/x86/bios/intelmp.hh' interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt') @@ -167,6 +175,7 @@ class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry): class X86IntelMPLocalIntAssignment(X86IntelMPBaseConfigEntry): type = 'X86IntelMPLocalIntAssignment' cxx_class = 'X86ISA::IntelMP::LocalIntAssignment' + cxx_header = 'arch/x86/bios/intelmp.hh' interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt') @@ -192,6 +201,7 @@ class X86IntelMPAddressType(Enum): class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry): type = 'X86IntelMPAddrSpaceMapping' cxx_class = 'X86ISA::IntelMP::AddrSpaceMapping' + cxx_header = 'arch/x86/bios/intelmp.hh' bus_id = Param.UInt8(0, 'id of the bus the address space is mapped to') address_type = Param.X86IntelMPAddressType('IOAddress', @@ -202,6 +212,7 @@ class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry): class X86IntelMPBusHierarchy(X86IntelMPExtConfigEntry): type = 'X86IntelMPBusHierarchy' cxx_class = 'X86ISA::IntelMP::BusHierarchy' + cxx_header = 'arch/x86/bios/intelmp.hh' bus_id = Param.UInt8(0, 'id of the bus being described') subtractive_decode = Param.Bool(False, @@ -216,6 +227,7 @@ class X86IntelMPRangeList(Enum): class X86IntelMPCompatAddrSpaceMod(X86IntelMPExtConfigEntry): type = 'X86IntelMPCompatAddrSpaceMod' cxx_class = 'X86ISA::IntelMP::CompatAddrSpaceMod' + cxx_header = 'arch/x86/bios/intelmp.hh' bus_id = Param.UInt8(0, 'id of the bus being described') add = Param.Bool(False, diff --git a/src/arch/x86/bios/SMBios.py b/src/arch/x86/bios/SMBios.py index 8fd3d57d8..918d43c2e 100644 --- a/src/arch/x86/bios/SMBios.py +++ b/src/arch/x86/bios/SMBios.py @@ -41,6 +41,7 @@ from m5.SimObject import SimObject class X86SMBiosSMBiosStructure(SimObject): type = 'X86SMBiosSMBiosStructure' cxx_class = 'X86ISA::SMBios::SMBiosStructure' + cxx_header = 'arch/x86/bios/smbios.hh' abstract = True class Characteristic(Enum): @@ -93,6 +94,7 @@ class ExtCharacteristic(Enum): class X86SMBiosBiosInformation(X86SMBiosSMBiosStructure): type = 'X86SMBiosBiosInformation' cxx_class = 'X86ISA::SMBios::BiosInformation' + cxx_header = 'arch/x86/bios/smbios.hh' vendor = Param.String("", "vendor name string") version = Param.String("", "version string") @@ -115,6 +117,7 @@ class X86SMBiosBiosInformation(X86SMBiosSMBiosStructure): class X86SMBiosSMBiosTable(SimObject): type = 'X86SMBiosSMBiosTable' cxx_class = 'X86ISA::SMBios::SMBiosTable' + cxx_header = 'arch/x86/bios/smbios.hh' major_version = Param.UInt8(2, "major version number") minor_version = Param.UInt8(5, "minor version number") diff --git a/src/base/CPA.py b/src/base/CPA.py index c0beaedef..cbed29a37 100644 --- a/src/base/CPA.py +++ b/src/base/CPA.py @@ -3,6 +3,7 @@ from m5.params import * class CPA(SimObject): type = 'CPA' + cxx_header = "base/cp_annotate.hh" enabled = Param.Bool(False, "Is Annotation enabled?") user_apps = VectorParam.String([], "List of apps to get symbols for") diff --git a/src/base/vnc/Vnc.py b/src/base/vnc/Vnc.py index 4e8e18512..a7faefb41 100644 --- a/src/base/vnc/Vnc.py +++ b/src/base/vnc/Vnc.py @@ -40,9 +40,11 @@ from m5.params import * class VncInput(SimObject): type = 'VncInput' + cxx_header = "base/vnc/vncinput.hh" frame_capture = Param.Bool(False, "capture changed frames to files") class VncServer(VncInput): type = 'VncServer' + cxx_header = "base/vnc/vncserver.hh" port = Param.TcpPort(5900, "listen port") number = Param.Int(0, "vnc client number") diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 331957749..dfbd459fd 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -76,11 +76,7 @@ elif buildEnv['TARGET_ISA'] == 'power': class BaseCPU(MemObject): type = 'BaseCPU' abstract = True - - @classmethod - def export_method_cxx_predecls(cls, code): - code('#include "cpu/base.hh"') - + cxx_header = "cpu/base.hh" @classmethod def export_methods(cls, code): diff --git a/src/cpu/CheckerCPU.py b/src/cpu/CheckerCPU.py index a6b5da5d7..f08b59f20 100644 --- a/src/cpu/CheckerCPU.py +++ b/src/cpu/CheckerCPU.py @@ -32,6 +32,7 @@ from BaseCPU import BaseCPU class CheckerCPU(BaseCPU): type = 'CheckerCPU' abstract = True + cxx_header = "cpu/checker/cpu.hh" exitOnError = Param.Bool(False, "Exit on an error") updateOnError = Param.Bool(False, "Update the checker with the main CPU's state on an error") diff --git a/src/cpu/ExeTracer.py b/src/cpu/ExeTracer.py index 5754f5d5b..f672fd65f 100644 --- a/src/cpu/ExeTracer.py +++ b/src/cpu/ExeTracer.py @@ -33,3 +33,4 @@ from InstTracer import InstTracer class ExeTracer(InstTracer): type = 'ExeTracer' cxx_class = 'Trace::ExeTracer' + cxx_header = "cpu/exetrace.hh" diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py index 92d7e13ca..0bb23e876 100644 --- a/src/cpu/FuncUnit.py +++ b/src/cpu/FuncUnit.py @@ -53,11 +53,13 @@ class OpClass(Enum): class OpDesc(SimObject): type = 'OpDesc' + cxx_header = "cpu/func_unit.hh" issueLat = Param.Cycles(1, "cycles until another can be issued") opClass = Param.OpClass("type of operation") opLat = Param.Cycles(1, "cycles until result is available") class FUDesc(SimObject): type = 'FUDesc' + cxx_header = "cpu/func_unit.hh" count = Param.Int("number of these FU's available") opList = VectorParam.OpDesc("operation classes for this FU type") diff --git a/src/cpu/IntelTrace.py b/src/cpu/IntelTrace.py index 3642f3174..6319ed1aa 100644 --- a/src/cpu/IntelTrace.py +++ b/src/cpu/IntelTrace.py @@ -33,3 +33,4 @@ from InstTracer import InstTracer class IntelTrace(InstTracer): type = 'IntelTrace' cxx_class = 'Trace::IntelTrace' + cxx_header = "cpu/inteltrace.hh" diff --git a/src/cpu/IntrControl.py b/src/cpu/IntrControl.py index eb4b1696b..72ea6ccb9 100644 --- a/src/cpu/IntrControl.py +++ b/src/cpu/IntrControl.py @@ -31,4 +31,5 @@ from m5.params import * from m5.proxy import * class IntrControl(SimObject): type = 'IntrControl' + cxx_header = "cpu/intr_control.hh" sys = Param.System(Parent.any, "the system we are part of") diff --git a/src/cpu/LegionTrace.py b/src/cpu/LegionTrace.py index d450dd00e..8b2a7cd85 100644 --- a/src/cpu/LegionTrace.py +++ b/src/cpu/LegionTrace.py @@ -33,3 +33,4 @@ from InstTracer import InstTracer class LegionTrace(InstTracer): type = 'LegionTrace' cxx_class = 'Trace::LegionTrace' + cxx_header = "cpu/legiontrace.hh" diff --git a/src/cpu/NativeTrace.py b/src/cpu/NativeTrace.py index dba6de067..fbcb341f0 100644 --- a/src/cpu/NativeTrace.py +++ b/src/cpu/NativeTrace.py @@ -34,3 +34,4 @@ class NativeTrace(ExeTracer): abstract = True type = 'NativeTrace' cxx_class = 'Trace::NativeTrace' + cxx_header = "cpu/nativetrace.hh" diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index 119de7f1c..811549bae 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -35,6 +35,7 @@ class ThreadModel(Enum): class InOrderCPU(BaseCPU): type = 'InOrderCPU' + cxx_header = "cpu/inorder/cpu.hh" activity = Param.Unsigned(0, "Initial count") threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)") diff --git a/src/cpu/inorder/InOrderTrace.py b/src/cpu/inorder/InOrderTrace.py index 3453fa675..fd4e00ed1 100644 --- a/src/cpu/inorder/InOrderTrace.py +++ b/src/cpu/inorder/InOrderTrace.py @@ -33,3 +33,4 @@ from InstTracer import InstTracer class InOrderTrace(InstTracer): type = 'InOrderTrace' cxx_class = 'Trace::InOrderTrace' + cxx_header = "cpu/inorder/inorder_trace.hh" diff --git a/src/cpu/inteltrace.hh b/src/cpu/inteltrace.hh index dbb6300ac..e5f88bf1a 100644 --- a/src/cpu/inteltrace.hh +++ b/src/cpu/inteltrace.hh @@ -35,13 +35,12 @@ #include "base/trace.hh" #include "base/types.hh" #include "cpu/static_inst.hh" +#include "cpu/thread_context.hh" #include "debug/ExecEnable.hh" #include "debug/ExecSpeculative.hh" #include "params/IntelTrace.hh" #include "sim/insttracer.hh" -class ThreadContext; - namespace Trace { class IntelTraceRecord : public InstRecord diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py index 1d3afbc6b..0f4ea67c7 100644 --- a/src/cpu/o3/FUPool.py +++ b/src/cpu/o3/FUPool.py @@ -33,6 +33,7 @@ from FuncUnitConfig import * class FUPool(SimObject): type = 'FUPool' + cxx_header = "cpu/o3/fu_pool.hh" FUList = VectorParam.FUDesc("list of FU's for this pool") class DefaultFUPool(FUPool): diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index 54daaec63..1927a5862 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -43,6 +43,7 @@ from BaseSimpleCPU import BaseSimpleCPU class AtomicSimpleCPU(BaseSimpleCPU): type = 'AtomicSimpleCPU' + cxx_header = "cpu/simple/atomic.hh" width = Param.Int(1, "CPU width") simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py index d9b963890..a4ae7e34b 100644 --- a/src/cpu/simple/BaseSimpleCPU.py +++ b/src/cpu/simple/BaseSimpleCPU.py @@ -34,6 +34,7 @@ from DummyChecker import DummyChecker class BaseSimpleCPU(BaseCPU): type = 'BaseSimpleCPU' abstract = True + cxx_header = "cpu/simple/base.hh" def addCheckerCpu(self): if buildEnv['TARGET_ISA'] in ['arm']: diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py index 61491b087..72560366e 100644 --- a/src/cpu/simple/TimingSimpleCPU.py +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -31,3 +31,4 @@ from BaseSimpleCPU import BaseSimpleCPU class TimingSimpleCPU(BaseSimpleCPU): type = 'TimingSimpleCPU' + cxx_header = "cpu/simple/timing.hh" diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index db2cd817d..507decbdf 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -42,13 +42,13 @@ #include "config/the_isa.hh" #include "cpu/op_class.hh" #include "cpu/static_inst_fwd.hh" +#include "cpu/thread_context.hh" #include "sim/fault_fwd.hh" // forward declarations struct AlphaSimpleImpl; struct OzoneImpl; struct SimpleImpl; -class ThreadContext; class DynInst; class Packet; diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py index bf3eace08..f6a625735 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.py +++ b/src/cpu/testers/directedtest/RubyDirectedTester.py @@ -34,20 +34,24 @@ from m5.proxy import * class DirectedGenerator(SimObject): type = 'DirectedGenerator' abstract = True + cxx_header = "cpu/testers/directedtest/DirectedGenerator.hh" num_cpus = Param.Int("num of cpus") system = Param.System(Parent.any, "System we belong to") class SeriesRequestGenerator(DirectedGenerator): type = 'SeriesRequestGenerator' + cxx_header = "cpu/testers/directedtest/SeriesRequestGenerator.hh" addr_increment_size = Param.Int(64, "address increment size") issue_writes = Param.Bool(True, "issue writes if true, otherwise reads") class InvalidateGenerator(DirectedGenerator): type = 'InvalidateGenerator' + cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh" addr_increment_size = Param.Int(64, "address increment size") class RubyDirectedTester(MemObject): type = 'RubyDirectedTester' + cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh" cpuPort = VectorMasterPort("the cpu ports") requests_to_complete = Param.Int("checks to complete") generator = Param.DirectedGenerator("the request generator") diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py index 1b4d6767c..ad3ee9233 100644 --- a/src/cpu/testers/memtest/MemTest.py +++ b/src/cpu/testers/memtest/MemTest.py @@ -32,6 +32,7 @@ from m5.proxy import * class MemTest(MemObject): type = 'MemTest' + cxx_header = "cpu/testers/memtest/memtest.hh" max_loads = Param.Counter(0, "number of loads to execute") atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n") memory_size = Param.Int(65536, "memory size") diff --git a/src/cpu/testers/networktest/NetworkTest.py b/src/cpu/testers/networktest/NetworkTest.py index 7d6ed576b..25b2bb690 100644 --- a/src/cpu/testers/networktest/NetworkTest.py +++ b/src/cpu/testers/networktest/NetworkTest.py @@ -32,6 +32,7 @@ from m5.proxy import * class NetworkTest(MemObject): type = 'NetworkTest' + cxx_header = "cpu/testers/networktest/networktest.hh" block_offset = Param.Int(6, "block offset in bits") num_memories = Param.Int(1, "Num Memories") memory_size = Param.Int(65536, "memory size") diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py index 2eaeb8efd..7af70cae0 100644 --- a/src/cpu/testers/rubytest/RubyTester.py +++ b/src/cpu/testers/rubytest/RubyTester.py @@ -32,6 +32,7 @@ from m5.proxy import * class RubyTester(MemObject): type = 'RubyTester' + cxx_header = "cpu/testers/rubytest/RubyTester.hh" num_cpus = Param.Int("number of cpus / RubyPorts") cpuDataPort = VectorMasterPort("the cpu data cache ports") cpuInstPort = VectorMasterPort("the cpu inst cache ports") diff --git a/src/cpu/testers/traffic_gen/TrafficGen.py b/src/cpu/testers/traffic_gen/TrafficGen.py index 15e9d7a9b..916279f91 100644 --- a/src/cpu/testers/traffic_gen/TrafficGen.py +++ b/src/cpu/testers/traffic_gen/TrafficGen.py @@ -61,6 +61,7 @@ from MemObject import MemObject # probabilities, effectively making it a Markov Chain. class TrafficGen(MemObject): type = 'TrafficGen' + cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh" # Port used for sending requests and receiving responses port = MasterPort("Master port") diff --git a/src/dev/BadDevice.py b/src/dev/BadDevice.py index 4fc592184..d6d68f86d 100644 --- a/src/dev/BadDevice.py +++ b/src/dev/BadDevice.py @@ -31,4 +31,5 @@ from Device import BasicPioDevice class BadDevice(BasicPioDevice): type = 'BadDevice' + cxx_header = "dev/baddev.hh" devicename = Param.String("Name of device to error on") diff --git a/src/dev/CopyEngine.py b/src/dev/CopyEngine.py index 9aa0e1fe5..68332e0a0 100644 --- a/src/dev/CopyEngine.py +++ b/src/dev/CopyEngine.py @@ -33,6 +33,7 @@ from Pci import PciDevice class CopyEngine(PciDevice): type = 'CopyEngine' + cxx_header = "dev/copy_engine.hh" dma = VectorMasterPort("Copy engine DMA port") VendorID = 0x8086 DeviceID = 0x1a38 diff --git a/src/dev/Device.py b/src/dev/Device.py index 3a06444cb..3b86ffb7d 100644 --- a/src/dev/Device.py +++ b/src/dev/Device.py @@ -32,24 +32,28 @@ from MemObject import MemObject class PioDevice(MemObject): type = 'PioDevice' + cxx_header = "dev/io_device.hh" abstract = True pio = SlavePort("Programmed I/O port") system = Param.System(Parent.any, "System this device is part of") class BasicPioDevice(PioDevice): type = 'BasicPioDevice' + cxx_header = "dev/io_device.hh" abstract = True pio_addr = Param.Addr("Device Address") pio_latency = Param.Latency('100ns', "Programmed IO latency") class DmaDevice(PioDevice): type = 'DmaDevice' + cxx_header = "dev/io_device.hh" abstract = True dma = MasterPort("DMA port") class IsaFake(BasicPioDevice): type = 'IsaFake' + cxx_header = "dev/io_device.hh" pio_size = Param.Addr(0x8, "Size of address range") ret_data8 = Param.UInt8(0xFF, "Default data to return") ret_data16 = Param.UInt16(0xFFFF, "Default data to return") diff --git a/src/dev/DiskImage.py b/src/dev/DiskImage.py index 92eb0553c..38cc6e75d 100644 --- a/src/dev/DiskImage.py +++ b/src/dev/DiskImage.py @@ -31,14 +31,17 @@ from m5.params import * class DiskImage(SimObject): type = 'DiskImage' abstract = True + cxx_header = "dev/disk_image.hh" image_file = Param.String("disk image file") read_only = Param.Bool(False, "read only image") class RawDiskImage(DiskImage): type = 'RawDiskImage' + cxx_header = "dev/disk_image.hh" class CowDiskImage(DiskImage): type = 'CowDiskImage' + cxx_header = "dev/disk_image.hh" child = Param.DiskImage(RawDiskImage(read_only=True), "child image") table_size = Param.Int(65536, "initial table size") diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py index 1afbce8ee..57d867fbe 100644 --- a/src/dev/Ethernet.py +++ b/src/dev/Ethernet.py @@ -34,9 +34,11 @@ from Pci import PciDevice class EtherObject(SimObject): type = 'EtherObject' abstract = True + cxx_header = "dev/etherobject.hh" class EtherLink(EtherObject): type = 'EtherLink' + cxx_header = "dev/etherlink.hh" int0 = SlavePort("interface 0") int1 = SlavePort("interface 1") delay = Param.Latency('0us', "packet transmit delay") @@ -46,29 +48,34 @@ class EtherLink(EtherObject): class EtherBus(EtherObject): type = 'EtherBus' + cxx_header = "dev/etherbus.hh" loopback = Param.Bool(True, "send packet back to the sending interface") dump = Param.EtherDump(NULL, "dump object") speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second") class EtherTap(EtherObject): type = 'EtherTap' + cxx_header = "dev/ethertap.hh" bufsz = Param.Int(10000, "tap buffer size") dump = Param.EtherDump(NULL, "dump object") port = Param.UInt16(3500, "tap port") class EtherDump(SimObject): type = 'EtherDump' + cxx_header = "dev/etherdump.hh" file = Param.String("dump file") maxlen = Param.Int(96, "max portion of packet data to dump") class EtherDevice(PciDevice): type = 'EtherDevice' abstract = True + cxx_header = "dev/etherdevice.hh" interface = MasterPort("Ethernet Interface") class IGbE(EtherDevice): # Base class for two IGbE adapters listed above type = 'IGbE' + cxx_header = "dev/i8254xGBe.hh" hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") use_flow_control = Param.Bool(False, @@ -149,6 +156,7 @@ class EtherDevBase(EtherDevice): class NSGigE(EtherDevBase): type = 'NSGigE' + cxx_header = "dev/ns_gige.hh" dma_data_free = Param.Bool(False, "DMA of Data is free") dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") @@ -178,6 +186,7 @@ class NSGigE(EtherDevBase): class Sinic(EtherDevBase): type = 'Sinic' cxx_class = 'Sinic::Device' + cxx_header = "dev/sinic.hh" rx_max_copy = Param.MemorySize('1514B', "rx max copy") tx_max_copy = Param.MemorySize('16kB', "tx max copy") diff --git a/src/dev/Ide.py b/src/dev/Ide.py index 7d97c42b6..c5eef9f54 100644 --- a/src/dev/Ide.py +++ b/src/dev/Ide.py @@ -34,12 +34,14 @@ class IdeID(Enum): vals = ['master', 'slave'] class IdeDisk(SimObject): type = 'IdeDisk' + cxx_header = "dev/ide_disk.hh" delay = Param.Latency('1us', "Fixed disk delay in microseconds") driveID = Param.IdeID('master', "Drive ID") image = Param.DiskImage("Disk image") class IdeController(PciDevice): type = 'IdeController' + cxx_header = "dev/ide_ctrl.hh" disks = VectorParam.IdeDisk("IDE disks attached to this controller") VendorID = 0x8086 diff --git a/src/dev/Pci.py b/src/dev/Pci.py index 8b4fd7b2f..df7c773c4 100644 --- a/src/dev/Pci.py +++ b/src/dev/Pci.py @@ -33,6 +33,7 @@ from Device import BasicPioDevice, DmaDevice, PioDevice class PciConfigAll(PioDevice): type = 'PciConfigAll' + cxx_header = "dev/pciconfigall.hh" platform = Param.Platform(Parent.any, "Platform this device is part of.") pio_latency = Param.Latency('30ns', "Programmed IO latency") bus = Param.UInt8(0x00, "PCI bus to act as config space for") @@ -42,6 +43,7 @@ class PciConfigAll(PioDevice): class PciDevice(DmaDevice): type = 'PciDevice' cxx_class = 'PciDev' + cxx_header = "dev/pcidev.hh" abstract = True platform = Param.Platform(Parent.any, "Platform this device is part of.") config = SlavePort("PCI configuration space port") diff --git a/src/dev/Platform.py b/src/dev/Platform.py index cb414121b..8a9871b35 100644 --- a/src/dev/Platform.py +++ b/src/dev/Platform.py @@ -32,4 +32,5 @@ from m5.proxy import * class Platform(SimObject): type = 'Platform' abstract = True + cxx_header = "dev/platform.hh" intrctrl = Param.IntrControl(Parent.any, "interrupt controller") diff --git a/src/dev/SimpleDisk.py b/src/dev/SimpleDisk.py index cf28c9c19..88bf5dbfb 100644 --- a/src/dev/SimpleDisk.py +++ b/src/dev/SimpleDisk.py @@ -31,5 +31,6 @@ from m5.params import * from m5.proxy import * class SimpleDisk(SimObject): type = 'SimpleDisk' + cxx_header = "dev/simple_disk.hh" disk = Param.DiskImage("Disk Image") system = Param.System(Parent.any, "System Pointer") diff --git a/src/dev/Terminal.py b/src/dev/Terminal.py index d67019198..2b54f9d5e 100644 --- a/src/dev/Terminal.py +++ b/src/dev/Terminal.py @@ -32,6 +32,7 @@ from m5.proxy import * class Terminal(SimObject): type = 'Terminal' + cxx_header = "dev/terminal.hh" intr_control = Param.IntrControl(Parent.any, "interrupt controller") port = Param.TcpPort(3456, "listen port") number = Param.Int(0, "terminal number") diff --git a/src/dev/Uart.py b/src/dev/Uart.py index 3dfc885eb..c3bc9dd0f 100644 --- a/src/dev/Uart.py +++ b/src/dev/Uart.py @@ -33,8 +33,10 @@ from Device import BasicPioDevice class Uart(BasicPioDevice): type = 'Uart' abstract = True + cxx_header = "dev/uart.hh" platform = Param.Platform(Parent.any, "Platform this device is part of.") terminal = Param.Terminal(Parent.any, "The terminal") class Uart8250(Uart): type = 'Uart8250' + cxx_header = "dev/uart8250.hh" diff --git a/src/dev/alpha/AlphaBackdoor.py b/src/dev/alpha/AlphaBackdoor.py index 14894b863..29372bce8 100644 --- a/src/dev/alpha/AlphaBackdoor.py +++ b/src/dev/alpha/AlphaBackdoor.py @@ -33,6 +33,7 @@ from Device import BasicPioDevice class AlphaBackdoor(BasicPioDevice): type = 'AlphaBackdoor' + cxx_header = "dev/alpha/backdoor.hh" cpu = Param.BaseCPU(Parent.cpu[0], "Processor") disk = Param.SimpleDisk("Simple Disk") terminal = Param.Terminal(Parent.any, "The console terminal") diff --git a/src/dev/alpha/Tsunami.py b/src/dev/alpha/Tsunami.py index 9a3ec0593..1a29b25d9 100644 --- a/src/dev/alpha/Tsunami.py +++ b/src/dev/alpha/Tsunami.py @@ -37,10 +37,12 @@ from Uart import Uart8250 class TsunamiCChip(BasicPioDevice): type = 'TsunamiCChip' + cxx_header = "dev/alpha/tsunami_cchip.hh" tsunami = Param.Tsunami(Parent.any, "Tsunami") class TsunamiIO(BasicPioDevice): type = 'TsunamiIO' + cxx_header = "dev/alpha/tsunami_io.hh" time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") year_is_bcd = Param.Bool(False, @@ -50,10 +52,12 @@ class TsunamiIO(BasicPioDevice): class TsunamiPChip(BasicPioDevice): type = 'TsunamiPChip' + cxx_header = "dev/alpha/tsunami_pchip.hh" tsunami = Param.Tsunami(Parent.any, "Tsunami") class Tsunami(Platform): type = 'Tsunami' + cxx_header = "dev/alpha/tsunami.hh" system = Param.System(Parent.any, "system") cchip = TsunamiCChip(pio_addr=0x801a0000000) diff --git a/src/dev/alpha/tsunami_io.hh b/src/dev/alpha/tsunami_io.hh index 212e2a3d5..7477fb124 100644 --- a/src/dev/alpha/tsunami_io.hh +++ b/src/dev/alpha/tsunami_io.hh @@ -38,6 +38,7 @@ #define __DEV_TSUNAMI_IO_HH__ #include "dev/alpha/tsunami.hh" +#include "dev/alpha/tsunami_cchip.hh" #include "dev/intel_8254_timer.hh" #include "dev/io_device.hh" #include "dev/mc146818.hh" diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index f0b629b38..87d4d9b16 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -54,11 +54,13 @@ from SimpleMemory import SimpleMemory class AmbaDevice(BasicPioDevice): type = 'AmbaDevice' abstract = True + cxx_header = "dev/arm/amba_device.hh" amba_id = Param.UInt32("ID of AMBA device for kernel detection") class AmbaIntDevice(AmbaDevice): type = 'AmbaIntDevice' abstract = True + cxx_header = "dev/arm/amba_device.hh" gic = Param.Gic(Parent.any, "Gic to use for interrupting") int_num = Param.UInt32("Interrupt number that connects to GIC") int_delay = Param.Latency("100ns", @@ -67,6 +69,7 @@ class AmbaIntDevice(AmbaDevice): class AmbaDmaDevice(DmaDevice): type = 'AmbaDmaDevice' abstract = True + cxx_header = "dev/arm/amba_device.hh" pio_addr = Param.Addr("Address for AMBA slave interface") pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") gic = Param.Gic(Parent.any, "Gic to use for interrupting") @@ -75,15 +78,18 @@ class AmbaDmaDevice(DmaDevice): class A9SCU(BasicPioDevice): type = 'A9SCU' + cxx_header = "dev/arm/a9scu.hh" class RealViewCtrl(BasicPioDevice): type = 'RealViewCtrl' + cxx_header = "dev/arm/rv_ctrl.hh" proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") class Gic(PioDevice): type = 'Gic' + cxx_header = "dev/arm/gic.hh" platform = Param.Platform(Parent.any, "Platform this device is part of.") dist_addr = Param.Addr(0x1f001000, "Address for distributor") cpu_addr = Param.Addr(0x1f000100, "Address for cpu") @@ -94,11 +100,13 @@ class Gic(PioDevice): class AmbaFake(AmbaDevice): type = 'AmbaFake' + cxx_header = "dev/arm/amba_fake.hh" ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") amba_id = 0; class Pl011(Uart): type = 'Pl011' + cxx_header = "dev/arm/pl011.hh" gic = Param.Gic(Parent.any, "Gic to use for interrupting") int_num = Param.UInt32("Interrupt number that connects to GIC") end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") @@ -106,6 +114,7 @@ class Pl011(Uart): class Sp804(AmbaDevice): type = 'Sp804' + cxx_header = "dev/arm/timer_sp804.hh" gic = Param.Gic(Parent.any, "Gic to use for interrupting") int_num0 = Param.UInt32("Interrupt number that connects to GIC") clock0 = Param.Clock('1MHz', "Clock speed of the input") @@ -115,6 +124,7 @@ class Sp804(AmbaDevice): class CpuLocalTimer(BasicPioDevice): type = 'CpuLocalTimer' + cxx_header = "dev/arm/timer_cpulocal.hh" gic = Param.Gic(Parent.any, "Gic to use for interrupting") int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") @@ -123,11 +133,13 @@ class CpuLocalTimer(BasicPioDevice): class PL031(AmbaIntDevice): type = 'PL031' + cxx_header = "dev/arm/rtc_pl031.hh" time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") amba_id = 0x00341031 class Pl050(AmbaIntDevice): type = 'Pl050' + cxx_header = "dev/arm/kmi.hh" vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") int_delay = '1us' @@ -135,6 +147,7 @@ class Pl050(AmbaIntDevice): class Pl111(AmbaDmaDevice): type = 'Pl111' + cxx_header = "dev/arm/pl111.hh" # Override the default clock clock = '24MHz' vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") @@ -142,6 +155,7 @@ class Pl111(AmbaDmaDevice): class RealView(Platform): type = 'RealView' + cxx_header = "dev/arm/realview.hh" system = Param.System(Parent.any, "system") pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") mem_start_addr = Param.Addr(0, "Start address of main memory") diff --git a/src/dev/arm/pl011.hh b/src/dev/arm/pl011.hh index dbd8bd539..e96d33d83 100644 --- a/src/dev/arm/pl011.hh +++ b/src/dev/arm/pl011.hh @@ -48,6 +48,8 @@ #ifndef __DEV_ARM_PL011_H__ #define __DEV_ARM_PL011_H__ +#include "base/bitfield.hh" +#include "base/bitunion.hh" #include "dev/io_device.hh" #include "dev/uart.hh" #include "params/Pl011.hh" diff --git a/src/dev/arm/realview.hh b/src/dev/arm/realview.hh index 70647d47c..f38aa69fc 100644 --- a/src/dev/arm/realview.hh +++ b/src/dev/arm/realview.hh @@ -52,6 +52,7 @@ #include "dev/platform.hh" #include "params/RealView.hh" +class Gic; class IdeController; class System; diff --git a/src/dev/arm/timer_cpulocal.hh b/src/dev/arm/timer_cpulocal.hh index cf7e46496..9b60db4ec 100644 --- a/src/dev/arm/timer_cpulocal.hh +++ b/src/dev/arm/timer_cpulocal.hh @@ -41,6 +41,7 @@ #ifndef __DEV_ARM_LOCALTIMER_HH__ #define __DEV_ARM_LOCALTIMER_HH__ +#include "base/bitunion.hh" #include "dev/io_device.hh" #include "params/CpuLocalTimer.hh" diff --git a/src/dev/copy_engine.hh b/src/dev/copy_engine.hh index 41b4a631e..9a0cb0628 100644 --- a/src/dev/copy_engine.hh +++ b/src/dev/copy_engine.hh @@ -50,6 +50,7 @@ #include <vector> +#include "base/cp_annotate.hh" #include "base/statistics.hh" #include "dev/copy_engine_defs.hh" #include "dev/pcidev.hh" diff --git a/src/dev/mips/Malta.py b/src/dev/mips/Malta.py index 23a5e5c8f..290dabf01 100755 --- a/src/dev/mips/Malta.py +++ b/src/dev/mips/Malta.py @@ -37,10 +37,12 @@ from Uart import Uart8250 class MaltaCChip(BasicPioDevice): type = 'MaltaCChip' + cxx_header = "dev/mips/malta_cchip.hh" malta = Param.Malta(Parent.any, "Malta") class MaltaIO(BasicPioDevice): type = 'MaltaIO' + cxx_header = "dev/mips/malta_io.hh" time = Param.Time('01/01/2009', "System time to use (0 for actual time, default is 1/1/06)") year_is_bcd = Param.Bool(False, @@ -50,10 +52,12 @@ class MaltaIO(BasicPioDevice): class MaltaPChip(BasicPioDevice): type = 'MaltaPChip' + cxx_header = "dev/mips/malta_pchip.hh" malta = Param.Malta(Parent.any, "Malta") class Malta(Platform): type = 'Malta' + cxx_header = "dev/mips/malta.hh" system = Param.System(Parent.any, "system") cchip = MaltaCChip(pio_addr=0x801a0000000) io = MaltaIO(pio_addr=0x801fc000000) diff --git a/src/dev/mips/malta_io.hh b/src/dev/mips/malta_io.hh index 9311d7c22..9f49f20cc 100755 --- a/src/dev/mips/malta_io.hh +++ b/src/dev/mips/malta_io.hh @@ -38,6 +38,7 @@ #define __DEV_MALTA_IO_HH__ #include "dev/mips/malta.hh" +#include "dev/mips/malta_cchip.hh" #include "dev/intel_8254_timer.hh" #include "dev/io_device.hh" #include "dev/mc146818.hh" diff --git a/src/dev/sparc/T1000.py b/src/dev/sparc/T1000.py index 03a59ac67..511f54b2c 100644 --- a/src/dev/sparc/T1000.py +++ b/src/dev/sparc/T1000.py @@ -36,22 +36,26 @@ from Uart import Uart8250 class MmDisk(BasicPioDevice): type = 'MmDisk' + cxx_header = "dev/sparc/mm_disk.hh" image = Param.DiskImage("Disk Image") pio_addr = 0x1F40000000 class DumbTOD(BasicPioDevice): type = 'DumbTOD' + cxx_header = "dev/sparc/dtod.hh" time = Param.Time('01/01/2009', "System time to use ('Now' for real time)") pio_addr = 0xfff0c1fff8 class Iob(PioDevice): type = 'Iob' + cxx_header = "dev/sparc/iob.hh" platform = Param.Platform(Parent.any, "Platform this device is part of.") pio_latency = Param.Latency('1ns', "Programed IO latency") class T1000(Platform): type = 'T1000' + cxx_header = "dev/sparc/t1000.hh" system = Param.System(Parent.any, "system") fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000) diff --git a/src/dev/x86/Cmos.py b/src/dev/x86/Cmos.py index 266fb8937..c0b2be58a 100644 --- a/src/dev/x86/Cmos.py +++ b/src/dev/x86/Cmos.py @@ -34,6 +34,7 @@ from X86IntPin import X86IntSourcePin class Cmos(BasicPioDevice): type = 'Cmos' cxx_class='X86ISA::Cmos' + cxx_header = "dev/x86/cmos.hh" time = Param.Time('01/01/2012', "System time to use ('Now' for actual time)") int_pin = Param.X86IntSourcePin(X86IntSourcePin(), diff --git a/src/dev/x86/I8042.py b/src/dev/x86/I8042.py index 57bf32ca0..d13a13341 100644 --- a/src/dev/x86/I8042.py +++ b/src/dev/x86/I8042.py @@ -34,6 +34,7 @@ from X86IntPin import X86IntSourcePin class I8042(BasicPioDevice): type = 'I8042' cxx_class = 'X86ISA::I8042' + cxx_header = "dev/x86/i8042.hh" # This isn't actually used for anything here. pio_addr = 0x0 data_port = Param.Addr('Data port address') diff --git a/src/dev/x86/I82094AA.py b/src/dev/x86/I82094AA.py index 3b076a9d6..7e71cdfc1 100644 --- a/src/dev/x86/I82094AA.py +++ b/src/dev/x86/I82094AA.py @@ -34,6 +34,7 @@ from X86IntPin import X86IntSinkPin class I82094AA(BasicPioDevice): type = 'I82094AA' cxx_class = 'X86ISA::I82094AA' + cxx_header = "dev/x86/i82094aa.hh" apic_id = Param.Int(1, 'APIC id for this IO APIC') int_master = MasterPort("Port for sending interrupt messages") int_latency = Param.Latency('1ns', \ diff --git a/src/dev/x86/I8237.py b/src/dev/x86/I8237.py index 0121c3d24..a4c5e3ad5 100644 --- a/src/dev/x86/I8237.py +++ b/src/dev/x86/I8237.py @@ -33,3 +33,4 @@ from Device import BasicPioDevice class I8237(BasicPioDevice): type = 'I8237' cxx_class = 'X86ISA::I8237' + cxx_header = "dev/x86/i8237.hh" diff --git a/src/dev/x86/I8254.py b/src/dev/x86/I8254.py index 6fdcb1c8d..574dd81c2 100644 --- a/src/dev/x86/I8254.py +++ b/src/dev/x86/I8254.py @@ -34,5 +34,6 @@ from X86IntPin import X86IntSourcePin class I8254(BasicPioDevice): type = 'I8254' cxx_class = 'X86ISA::I8254' + cxx_header = "dev/x86/i8254.hh" int_pin = Param.X86IntSourcePin(X86IntSourcePin(), 'Pin to signal timer interrupts to') diff --git a/src/dev/x86/I8259.py b/src/dev/x86/I8259.py index 30ea14225..4403c3f53 100644 --- a/src/dev/x86/I8259.py +++ b/src/dev/x86/I8259.py @@ -40,6 +40,7 @@ class X86I8259CascadeMode(Enum): class I8259(BasicPioDevice): type = 'I8259' cxx_class='X86ISA::I8259' + cxx_header = "dev/x86/i8259.hh" output = Param.X86IntSourcePin(X86IntSourcePin(), 'The pin this I8259 drives') mode = Param.X86I8259CascadeMode('How this I8259 is cascaded') diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py index 91292788c..3fc2382b7 100644 --- a/src/dev/x86/Pc.py +++ b/src/dev/x86/Pc.py @@ -42,6 +42,7 @@ def x86IOAddress(port): class Pc(Platform): type = 'Pc' + cxx_header = "dev/x86/pc.hh" system = Param.System(Parent.any, "system") pciconfig = PciConfigAll() diff --git a/src/dev/x86/PcSpeaker.py b/src/dev/x86/PcSpeaker.py index cc1f5517a..f1c23157b 100644 --- a/src/dev/x86/PcSpeaker.py +++ b/src/dev/x86/PcSpeaker.py @@ -33,4 +33,5 @@ from Device import BasicPioDevice class PcSpeaker(BasicPioDevice): type = 'PcSpeaker' cxx_class = 'X86ISA::Speaker' + cxx_header = "dev/x86/speaker.hh" i8254 = Param.I8254('Timer that drives the speaker') diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index 7ac208d5e..45c49ce3a 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -45,6 +45,7 @@ def x86IOAddress(port): class SouthBridge(SimObject): type = 'SouthBridge' + cxx_header = "dev/x86/south_bridge.hh" platform = Param.Platform(Parent.any, "Platform this device is part of") _pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master') diff --git a/src/dev/x86/X86IntPin.py b/src/dev/x86/X86IntPin.py index 35e274624..53760b496 100644 --- a/src/dev/x86/X86IntPin.py +++ b/src/dev/x86/X86IntPin.py @@ -33,11 +33,13 @@ from m5.SimObject import SimObject class X86IntSourcePin(SimObject): type = 'X86IntSourcePin' cxx_class = 'X86ISA::IntSourcePin' + cxx_header = "dev/x86/intdev.hh" # A generic pin to receive an interrupt signal generated by another device. class X86IntSinkPin(SimObject): type = 'X86IntSinkPin' cxx_class = 'X86ISA::IntSinkPin' + cxx_header = "dev/x86/intdev.hh" device = Param.SimObject("Device this pin belongs to") number = Param.Int("The pin number on the device") @@ -46,6 +48,7 @@ class X86IntSinkPin(SimObject): class X86IntLine(SimObject): type = 'X86IntLine' cxx_class = 'X86ISA::IntLine' + cxx_header = "dev/x86/intdev.hh" source = Param.X86IntSourcePin("Pin driving this line") sink = Param.X86IntSinkPin("Pin driven by this line") diff --git a/src/dev/x86/speaker.hh b/src/dev/x86/speaker.hh index 5aa1ccf0a..2886a76d7 100644 --- a/src/dev/x86/speaker.hh +++ b/src/dev/x86/speaker.hh @@ -32,6 +32,7 @@ #define __DEV_X86_SPEAKER_HH__ #include "base/bitunion.hh" +#include "dev/io_device.hh" #include "params/PcSpeaker.hh" namespace X86ISA diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py index ce3f04c49..f96ca5b78 100644 --- a/src/mem/AbstractMemory.py +++ b/src/mem/AbstractMemory.py @@ -45,6 +45,7 @@ from MemObject import MemObject class AbstractMemory(MemObject): type = 'AbstractMemory' abstract = True + cxx_header = "mem/abstract_mem.hh" range = Param.AddrRange(AddrRange('128MB'), "Address range") null = Param.Bool(False, "Do not store data, always return zero") zero = Param.Bool(False, "Initialize memory with zeros") diff --git a/src/mem/AddrMapper.py b/src/mem/AddrMapper.py index 2b999ee92..f6e943ed1 100644 --- a/src/mem/AddrMapper.py +++ b/src/mem/AddrMapper.py @@ -46,6 +46,7 @@ from MemObject import MemObject # currently not modified. class AddrMapper(MemObject): type = 'AddrMapper' + cxx_header = 'mem/addr_mapper.hh' abstract = True # one port in each direction @@ -58,6 +59,7 @@ class AddrMapper(MemObject): # (original and remapped), only with an offset. class RangeAddrMapper(AddrMapper): type = 'RangeAddrMapper' + cxx_header = 'mem/addr_mapper.hh' # These two vectors should be the exact same length and each range # should be the exact same size. Each range in original_ranges is diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py index 62dfb7351..5f2cc9f40 100644 --- a/src/mem/Bridge.py +++ b/src/mem/Bridge.py @@ -44,6 +44,7 @@ from MemObject import MemObject class Bridge(MemObject): type = 'Bridge' + cxx_header = "mem/bridge.hh" slave = SlavePort('Slave port') master = MasterPort('Master port') req_size = Param.Int(16, "The number of requests to buffer") diff --git a/src/mem/Bus.py b/src/mem/Bus.py index 45b1f1b0a..4637b0ebc 100644 --- a/src/mem/Bus.py +++ b/src/mem/Bus.py @@ -45,6 +45,7 @@ from m5.params import * class BaseBus(MemObject): type = 'BaseBus' abstract = True + cxx_header = "mem/bus.hh" slave = VectorSlavePort("vector port for connecting masters") master = VectorMasterPort("vector port for connecting slaves") header_cycles = Param.Cycles(1, "cycles of overhead per transaction") @@ -66,6 +67,8 @@ class BaseBus(MemObject): class NoncoherentBus(BaseBus): type = 'NoncoherentBus' + cxx_header = "mem/noncoherent_bus.hh" class CoherentBus(BaseBus): type = 'CoherentBus' + cxx_header = "mem/coherent_bus.hh" diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py index 3621942d9..a34a57db4 100644 --- a/src/mem/CommMonitor.py +++ b/src/mem/CommMonitor.py @@ -43,6 +43,7 @@ from MemObject import MemObject # with periodic dumping and resetting of stats using schedStatEvent class CommMonitor(MemObject): type = 'CommMonitor' + cxx_header = "mem/comm_monitor.hh" # one port in each direction master = MasterPort("Master port") diff --git a/src/mem/MemObject.py b/src/mem/MemObject.py index 0f33cc0bf..0827218aa 100644 --- a/src/mem/MemObject.py +++ b/src/mem/MemObject.py @@ -31,3 +31,4 @@ from ClockedObject import ClockedObject class MemObject(ClockedObject): type = 'MemObject' abstract = True + cxx_header = "mem/mem_object.hh" diff --git a/src/mem/SimpleDRAM.py b/src/mem/SimpleDRAM.py index c87425610..3211f576a 100644 --- a/src/mem/SimpleDRAM.py +++ b/src/mem/SimpleDRAM.py @@ -57,6 +57,7 @@ class PageManage(Enum): vals = ['open', 'close'] # itself. class SimpleDRAM(AbstractMemory): type = 'SimpleDRAM' + cxx_header = "mem/simple_dram.hh" # single-ported on the system interface side, instantiate with a # bus in front of the controller for multiple ports diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py index 9361b45d8..0cf6dece3 100644 --- a/src/mem/SimpleMemory.py +++ b/src/mem/SimpleMemory.py @@ -44,6 +44,7 @@ from AbstractMemory import * class SimpleMemory(AbstractMemory): type = 'SimpleMemory' + cxx_header = "mem/simple_mem.hh" port = SlavePort("Slave ports") latency = Param.Latency('30ns', "Request to response latency") latency_var = Param.Latency('0ns', "Request to response latency variance") diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 6fe73a9c2..fe0d9ceb0 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -46,6 +46,7 @@ from Prefetcher import BasePrefetcher class BaseCache(MemObject): type = 'BaseCache' + cxx_header = "mem/cache/base.hh" assoc = Param.Int("associativity") block_size = Param.Int("block size in bytes") hit_latency = Param.Cycles("The hit latency for this cache") diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index e590410ae..af67f40b6 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -45,6 +45,7 @@ from m5.proxy import * class BasePrefetcher(ClockedObject): type = 'BasePrefetcher' abstract = True + cxx_header = "mem/cache/prefetch/base.hh" size = Param.Int(100, "Number of entries in the hardware prefetch queue") cross_pages = Param.Bool(False, @@ -63,14 +64,17 @@ class BasePrefetcher(ClockedObject): class GHBPrefetcher(BasePrefetcher): type = 'GHBPrefetcher' cxx_class = 'GHBPrefetcher' + cxx_header = "mem/cache/prefetch/ghb.hh" class StridePrefetcher(BasePrefetcher): type = 'StridePrefetcher' cxx_class = 'StridePrefetcher' + cxx_header = "mem/cache/prefetch/stride.hh" class TaggedPrefetcher(BasePrefetcher): type = 'TaggedPrefetcher' cxx_class = 'TaggedPrefetcher' + cxx_header = "mem/cache/prefetch/tagged.hh" diff --git a/src/mem/cache/tags/iic_repl/Repl.py b/src/mem/cache/tags/iic_repl/Repl.py index 4c333e897..577eb8fed 100644 --- a/src/mem/cache/tags/iic_repl/Repl.py +++ b/src/mem/cache/tags/iic_repl/Repl.py @@ -31,9 +31,11 @@ from m5.params import * class Repl(SimObject): type = 'Repl' abstract = True + cxx_header = "mem/cache/tags/iic_repl/repl.hh" class GenRepl(Repl): type = 'GenRepl' + cxx_header = "mem/cache/tags/iic_repl/gen.hh" fresh_res = Param.Int("Fresh pool residency time") num_pools = Param.Int("Number of priority pools") pool_res = Param.Int("Pool residency time") diff --git a/src/mem/ruby/network/BasicLink.py b/src/mem/ruby/network/BasicLink.py index f73f5d977..841208578 100644 --- a/src/mem/ruby/network/BasicLink.py +++ b/src/mem/ruby/network/BasicLink.py @@ -32,6 +32,7 @@ from m5.SimObject import SimObject class BasicLink(SimObject): type = 'BasicLink' + cxx_header = "mem/ruby/network/BasicLink.hh" link_id = Param.Int("ID in relation to other links") latency = Param.Int(1, "latency") # The following banwidth factor does not translate to the same value for @@ -43,12 +44,14 @@ class BasicLink(SimObject): class BasicExtLink(BasicLink): type = 'BasicExtLink' + cxx_header = "mem/ruby/network/BasicLink.hh" ext_node = Param.RubyController("External node") int_node = Param.BasicRouter("ID of internal node") bandwidth_factor = 16 class BasicIntLink(BasicLink): type = 'BasicIntLink' + cxx_header = "mem/ruby/network/BasicLink.hh" node_a = Param.BasicRouter("Router on one end") node_b = Param.BasicRouter("Router on other end") bandwidth_factor = 16 diff --git a/src/mem/ruby/network/BasicRouter.py b/src/mem/ruby/network/BasicRouter.py index 0ff41c33c..0c8e5cb54 100644 --- a/src/mem/ruby/network/BasicRouter.py +++ b/src/mem/ruby/network/BasicRouter.py @@ -32,4 +32,5 @@ from m5.SimObject import SimObject class BasicRouter(SimObject): type = 'BasicRouter' + cxx_header = "mem/ruby/network/BasicRouter.hh" router_id = Param.Int("ID in relation to other routers") diff --git a/src/mem/ruby/network/Network.py b/src/mem/ruby/network/Network.py index 9642b046e..4bc35b30c 100644 --- a/src/mem/ruby/network/Network.py +++ b/src/mem/ruby/network/Network.py @@ -33,6 +33,7 @@ from BasicLink import BasicLink class Topology(SimObject): type = 'Topology' + cxx_header = "mem/ruby/network/Topology.hh" description = Param.String("Not Specified", "the name of the imported topology module") ext_links = VectorParam.BasicExtLink("Links to external nodes") @@ -44,6 +45,7 @@ class Topology(SimObject): class RubyNetwork(SimObject): type = 'RubyNetwork' cxx_class = 'Network' + cxx_header = "mem/ruby/network/Network.hh" abstract = True number_of_virtual_networks = Param.Int(10, ""); topology = Param.Topology(""); diff --git a/src/mem/ruby/network/fault_model/FaultModel.py b/src/mem/ruby/network/fault_model/FaultModel.py index 5117491f2..b1532150b 100644 --- a/src/mem/ruby/network/fault_model/FaultModel.py +++ b/src/mem/ruby/network/fault_model/FaultModel.py @@ -39,6 +39,7 @@ from m5.SimObject import SimObject class FaultModel(SimObject): type = 'FaultModel' cxx_class = 'FaultModel' + cxx_header = "mem/ruby/network/fault_model/FaultModel.hh" baseline_fault_vector_database = VectorParam.Float([ 5, 40, 0.080892, 0.109175, 0.018864, 0.130408, 0.059724, 0.077571, 0.034830, 0.083430, 0.067500, 0.121500, diff --git a/src/mem/ruby/network/garnet/BaseGarnetNetwork.py b/src/mem/ruby/network/garnet/BaseGarnetNetwork.py index 2431db203..0bcb0484d 100644 --- a/src/mem/ruby/network/garnet/BaseGarnetNetwork.py +++ b/src/mem/ruby/network/garnet/BaseGarnetNetwork.py @@ -33,6 +33,7 @@ from Network import RubyNetwork class BaseGarnetNetwork(RubyNetwork): type = 'BaseGarnetNetwork' + cxx_header = "mem/ruby/network/garnet/BaseGarnetNetwork.hh" abstract = True ni_flit_size = Param.Int(16, "network interface flit size in bytes") vcs_per_vnet = Param.Int(4, "virtual channels per virtual network"); diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py index 1fb7e0b7b..e5de4ecaf 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py @@ -35,6 +35,7 @@ from BasicLink import BasicIntLink, BasicExtLink class NetworkLink_d(SimObject): type = 'NetworkLink_d' + cxx_header = "mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh" link_id = Param.Int(Parent.link_id, "link id") link_latency = Param.Int(Parent.latency, "link latency") vcs_per_vnet = Param.Int(Parent.vcs_per_vnet, @@ -46,10 +47,12 @@ class NetworkLink_d(SimObject): class CreditLink_d(NetworkLink_d): type = 'CreditLink_d' + cxx_header = "mem/ruby/network/garnet/fixed-pipeline/CreditLink_d.hh" # Interior fixed pipeline links between routers class GarnetIntLink_d(BasicIntLink): type = 'GarnetIntLink_d' + cxx_header = "mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh" # The detailed fixed pipeline bi-directional link include two main # forward links and two backward flow-control links, one per direction nls = [] @@ -69,6 +72,7 @@ class GarnetIntLink_d(BasicIntLink): # Exterior fixed pipeline links between a router and a controller class GarnetExtLink_d(BasicExtLink): type = 'GarnetExtLink_d' + cxx_header = "mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh" # The detailed fixed pipeline bi-directional link include two main # forward links and two backward flow-control links, one per direction nls = [] diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py index a3a00525d..6ebf94e04 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py @@ -33,5 +33,6 @@ from BaseGarnetNetwork import BaseGarnetNetwork class GarnetNetwork_d(BaseGarnetNetwork): type = 'GarnetNetwork_d' + cxx_header = "mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh" buffers_per_data_vc = Param.Int(4, "buffers per data virtual channel"); buffers_per_ctrl_vc = Param.Int(1, "buffers per ctrl virtual channel"); diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py index b2a01fb46..cd009a807 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py @@ -35,6 +35,7 @@ from BasicRouter import BasicRouter class GarnetRouter_d(BasicRouter): type = 'GarnetRouter_d' cxx_class = 'Router_d' + cxx_header = "mem/ruby/network/garnet/fixed-pipeline/Router_d.hh" vcs_per_vnet = Param.Int(Parent.vcs_per_vnet, "virtual channels per virtual network") virt_nets = Param.Int(Parent.number_of_virtual_networks, diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py index 591ab4beb..d5b55c1ec 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py +++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py @@ -35,6 +35,7 @@ from BasicLink import BasicIntLink, BasicExtLink class NetworkLink(SimObject): type = 'NetworkLink' + cxx_header = "mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh" link_id = Param.Int(Parent.link_id, "link id") link_latency = Param.Int(Parent.latency, "link latency") vcs_per_vnet = Param.Int(Parent.vcs_per_vnet, @@ -47,6 +48,7 @@ class NetworkLink(SimObject): # Interior fixed pipeline links between routers class GarnetIntLink(BasicIntLink): type = 'GarnetIntLink' + cxx_header = "mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh" # The flexible pipeline bi-directional link only include two main # forward links and no backward flow-control links nls = [] @@ -59,6 +61,7 @@ class GarnetIntLink(BasicIntLink): # Exterior fixed pipeline links between a router and a controller class GarnetExtLink(BasicExtLink): type = 'GarnetExtLink' + cxx_header = "mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh" # The flexible pipeline bi-directional link only include two main # forward links and no backward flow-control links nls = [] diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.py b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.py index 7ad61a5ce..28f81d732 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.py +++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.py @@ -33,6 +33,7 @@ from BaseGarnetNetwork import BaseGarnetNetwork class GarnetNetwork(BaseGarnetNetwork): type = 'GarnetNetwork' + cxx_header = "mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh" buffer_size = Param.Int(0, "default buffer size; 0 indicates infinite buffering"); number_of_pipe_stages = Param.Int(4, "router pipeline stages"); diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py index a39348c46..22d8c8670 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py +++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py @@ -35,6 +35,7 @@ from BasicRouter import BasicRouter class GarnetRouter(BasicRouter): type = 'GarnetRouter' cxx_class = 'Router' + cxx_header = "mem/ruby/network/garnet/flexible-pipeline/Router.hh" vcs_per_vnet = Param.Int(Parent.vcs_per_vnet, "virtual channels per virtual network") virt_nets = Param.Int(Parent.number_of_virtual_networks, diff --git a/src/mem/ruby/network/simple/SimpleLink.py b/src/mem/ruby/network/simple/SimpleLink.py index 55b21562e..716a21eec 100644 --- a/src/mem/ruby/network/simple/SimpleLink.py +++ b/src/mem/ruby/network/simple/SimpleLink.py @@ -34,6 +34,8 @@ from BasicLink import BasicIntLink, BasicExtLink class SimpleExtLink(BasicExtLink): type = 'SimpleExtLink' + cxx_header = "mem/ruby/network/simple/SimpleLink.hh" class SimpleIntLink(BasicIntLink): type = 'SimpleIntLink' + cxx_header = "mem/ruby/network/simple/SimpleLink.hh" diff --git a/src/mem/ruby/network/simple/SimpleNetwork.py b/src/mem/ruby/network/simple/SimpleNetwork.py index 0603546ce..217dc20ec 100644 --- a/src/mem/ruby/network/simple/SimpleNetwork.py +++ b/src/mem/ruby/network/simple/SimpleNetwork.py @@ -34,6 +34,7 @@ from BasicRouter import BasicRouter class SimpleNetwork(RubyNetwork): type = 'SimpleNetwork' + cxx_header = "mem/ruby/network/simple/SimpleNetwork.hh" buffer_size = Param.Int(0, "default buffer size; 0 indicates infinite buffering"); endpoint_bandwidth = Param.Int(1000, "bandwidth adjustment factor"); diff --git a/src/mem/ruby/profiler/Profiler.py b/src/mem/ruby/profiler/Profiler.py index 3521911c2..0bb1bbc3d 100644 --- a/src/mem/ruby/profiler/Profiler.py +++ b/src/mem/ruby/profiler/Profiler.py @@ -33,6 +33,7 @@ from m5.SimObject import SimObject class RubyProfiler(SimObject): type = 'RubyProfiler' cxx_class = 'Profiler' + cxx_header = "mem/ruby/profiler/Profiler.hh" hot_lines = Param.Bool(False, "") all_instructions = Param.Bool(False, "") num_of_sequencers = Param.Int("") diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py index 44e08ecdc..9787b5ce7 100644 --- a/src/mem/ruby/slicc_interface/Controller.py +++ b/src/mem/ruby/slicc_interface/Controller.py @@ -33,6 +33,7 @@ from m5.SimObject import SimObject class RubyController(SimObject): type = 'RubyController' cxx_class = 'AbstractController' + cxx_header = "mem/ruby/slicc_interface/AbstractController.hh" abstract = True version = Param.Int("") cntrl_id = Param.Int("") diff --git a/src/mem/ruby/system/Cache.py b/src/mem/ruby/system/Cache.py index 57326c3c6..4b0269822 100644 --- a/src/mem/ruby/system/Cache.py +++ b/src/mem/ruby/system/Cache.py @@ -34,6 +34,7 @@ from Controller import RubyController class RubyCache(SimObject): type = 'RubyCache' cxx_class = 'CacheMemory' + cxx_header = "mem/ruby/system/CacheMemory.hh" size = Param.MemorySize("capacity in bytes"); latency = Param.Int(""); assoc = Param.Int(""); diff --git a/src/mem/ruby/system/DirectoryMemory.py b/src/mem/ruby/system/DirectoryMemory.py index d3b6bc591..ac4dd5934 100644 --- a/src/mem/ruby/system/DirectoryMemory.py +++ b/src/mem/ruby/system/DirectoryMemory.py @@ -34,6 +34,7 @@ from m5.SimObject import SimObject class RubyDirectoryMemory(SimObject): type = 'RubyDirectoryMemory' cxx_class = 'DirectoryMemory' + cxx_header = "mem/ruby/system/DirectoryMemory.hh" version = Param.Int(0, "") size = Param.MemorySize("1GB", "capacity in bytes") use_map = Param.Bool(False, "enable sparse memory") diff --git a/src/mem/ruby/system/MemoryControl.py b/src/mem/ruby/system/MemoryControl.py index 09c940fee..ad18efec5 100644 --- a/src/mem/ruby/system/MemoryControl.py +++ b/src/mem/ruby/system/MemoryControl.py @@ -34,5 +34,6 @@ class MemoryControl(ClockedObject): abstract = True type = 'MemoryControl' cxx_class = 'MemoryControl' + cxx_header = "mem/ruby/system/MemoryControl.hh" version = Param.Int(""); ruby_system = Param.RubySystem("") diff --git a/src/mem/ruby/system/RubyMemoryControl.py b/src/mem/ruby/system/RubyMemoryControl.py index e65b6f5cc..7764938d3 100644 --- a/src/mem/ruby/system/RubyMemoryControl.py +++ b/src/mem/ruby/system/RubyMemoryControl.py @@ -34,6 +34,7 @@ from MemoryControl import MemoryControl class RubyMemoryControl(MemoryControl): type = 'RubyMemoryControl' cxx_class = 'RubyMemoryControl' + cxx_header = "mem/ruby/system/RubyMemoryControl.hh" version = Param.Int(""); # Override the default clock diff --git a/src/mem/ruby/system/RubySystem.py b/src/mem/ruby/system/RubySystem.py index c9d2e96ac..b1f625723 100644 --- a/src/mem/ruby/system/RubySystem.py +++ b/src/mem/ruby/system/RubySystem.py @@ -32,6 +32,7 @@ from ClockedObject import ClockedObject class RubySystem(ClockedObject): type = 'RubySystem' + cxx_header = "mem/ruby/system/System.hh" random_seed = Param.Int(1234, "random seed used by the simulation"); randomization = Param.Bool(False, "insert random delays on message enqueue times"); diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index deef6e714..9b243a8b9 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -34,6 +34,7 @@ from MemObject import MemObject class RubyPort(MemObject): type = 'RubyPort' abstract = True + cxx_header = "mem/ruby/system/RubyPort.hh" slave = VectorSlavePort("CPU slave port") master = VectorMasterPort("CPU master port") version = Param.Int(0, "") @@ -50,10 +51,12 @@ class RubyPort(MemObject): class RubyPortProxy(RubyPort): type = 'RubyPortProxy' + cxx_header = "mem/ruby/system/RubyPortProxy.hh" class RubySequencer(RubyPort): type = 'RubySequencer' cxx_class = 'Sequencer' + cxx_header = "mem/ruby/system/Sequencer.hh" icache = Param.RubyCache("") dcache = Param.RubyCache("") max_outstanding_requests = Param.Int(16, @@ -63,3 +66,4 @@ class RubySequencer(RubyPort): class DMASequencer(RubyPort): type = 'DMASequencer' + cxx_header = "mem/ruby/system/DMASequencer.hh" diff --git a/src/mem/ruby/system/WireBuffer.py b/src/mem/ruby/system/WireBuffer.py index bca19b4df..f48ab1f95 100644 --- a/src/mem/ruby/system/WireBuffer.py +++ b/src/mem/ruby/system/WireBuffer.py @@ -32,3 +32,4 @@ from m5.SimObject import SimObject class RubyWireBuffer(SimObject): type = 'RubyWireBuffer' cxx_class = 'WireBuffer' + cxx_header = "mem/ruby/system/WireBuffer.hh" diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 427dbf700..f07e521d3 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -185,6 +185,7 @@ from Controller import RubyController class $py_ident(RubyController): type = '$py_ident' + cxx_header = 'mem/protocol/${c_ident}.hh' ''') code.indent() for param in self.config_parameters: diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index b63aa22d5..c01db2a80 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -105,6 +105,9 @@ allClasses = {} # dict to look up SimObjects based on path instanceDict = {} +# Did any of the SimObjects lack a header file? +noCxxHeader = False + def public_value(key, value): return key.startswith('_') or \ isinstance(value, (FunctionType, MethodType, ModuleType, @@ -119,6 +122,7 @@ class MetaSimObject(type): init_keywords = { 'abstract' : bool, 'cxx_class' : str, 'cxx_type' : str, + 'cxx_header' : str, 'type' : str } # Attributes that can be set any time keywords = { 'check' : FunctionType } @@ -203,6 +207,12 @@ class MetaSimObject(type): cls._value_dict['cxx_type'] = '%s *' % cls._value_dict['cxx_class'] + if 'cxx_header' not in cls._value_dict: + global noCxxHeader + noCxxHeader = True + print >> sys.stderr, \ + "warning: No header file specified for SimObject: %s" % name + # Export methods are automatically inherited via C++, so we # don't want the method declarations to get inherited on the # python side (and thus end up getting repeated in the wrapped @@ -407,6 +417,7 @@ class MetaSimObject(type): code('#include "params/$cls.hh"') for param in params: param.cxx_predecls(code) + code('#include "${{cls.cxx_header}}"') cls.export_method_cxx_predecls(code) code('''\ /** @@ -568,15 +579,7 @@ class SimObject(object): __metaclass__ = MetaSimObject type = 'SimObject' abstract = True - - @classmethod - def export_method_cxx_predecls(cls, code): - code(''' -#include <Python.h> - -#include "sim/serialize.hh" -#include "sim/sim_object.hh" -''') + cxx_header = "sim/sim_object.hh" @classmethod def export_method_swig_predecls(cls, code): @@ -1099,10 +1102,11 @@ baseClasses = allClasses.copy() baseInstances = instanceDict.copy() def clear(): - global allClasses, instanceDict + global allClasses, instanceDict, noCxxHeader allClasses = baseClasses.copy() instanceDict = baseInstances.copy() + noCxxHeader = False # __all__ defines the list of symbols that get exported when # 'from config import *' is invoked. Try to keep this reasonably diff --git a/src/sim/BaseTLB.py b/src/sim/BaseTLB.py index 9aca4a97c..8a03413a9 100644 --- a/src/sim/BaseTLB.py +++ b/src/sim/BaseTLB.py @@ -31,3 +31,4 @@ from m5.SimObject import SimObject class BaseTLB(SimObject): type = 'BaseTLB' abstract = True + cxx_header = "sim/tlb.hh" diff --git a/src/sim/ClockedObject.py b/src/sim/ClockedObject.py index 26b0e2348..8bc4031a4 100644 --- a/src/sim/ClockedObject.py +++ b/src/sim/ClockedObject.py @@ -42,6 +42,7 @@ from m5.proxy import * class ClockedObject(SimObject): type = 'ClockedObject' abstract = True + cxx_header = "sim/clocked_object.hh" # Clock period of this object, with the default value being the # clock period of the parent object, unproxied at instantiation diff --git a/src/sim/InstTracer.py b/src/sim/InstTracer.py index 9ba91a019..7405ecbc6 100644 --- a/src/sim/InstTracer.py +++ b/src/sim/InstTracer.py @@ -33,3 +33,4 @@ class InstTracer(SimObject): type = 'InstTracer' cxx_class = 'Trace::InstTracer' abstract = True + cxx_header = "sim/insttracer.hh" diff --git a/src/sim/Process.py b/src/sim/Process.py index bb76b5cf7..55ccc50d0 100644 --- a/src/sim/Process.py +++ b/src/sim/Process.py @@ -33,6 +33,7 @@ from m5.proxy import * class Process(SimObject): type = 'Process' abstract = True + cxx_header = "sim/process.hh" input = Param.String('cin', "filename for stdin") output = Param.String('cout', 'filename for stdout') errout = Param.String('cerr', 'filename for stderr') @@ -40,15 +41,12 @@ class Process(SimObject): max_stack_size = Param.MemorySize('64MB', 'maximum size of the stack') @classmethod - def export_method_cxx_predecls(cls, code): - code('#include "sim/process.hh"') - - @classmethod def export_methods(cls, code): code('bool map(Addr vaddr, Addr paddr, int size);') class LiveProcess(Process): type = 'LiveProcess' + cxx_header = "sim/process.hh" executable = Param.String('', "executable (overrides cmd[0] if set)") cmd = VectorParam.String("command line (executable plus arguments)") env = VectorParam.String([], "environment settings") diff --git a/src/sim/Root.py b/src/sim/Root.py index daa0a903f..44f768c0b 100644 --- a/src/sim/Root.py +++ b/src/sim/Root.py @@ -58,6 +58,7 @@ class Root(SimObject): return 'root' type = 'Root' + cxx_header = "sim/root.hh" full_system = Param.Bool("if this is a full system simulation") diff --git a/src/sim/System.py b/src/sim/System.py index 92883b299..3d45c23c0 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -39,6 +39,7 @@ class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing'] class System(MemObject): type = 'System' + cxx_header = "sim/system.hh" system_port = MasterPort("System port") # Override the clock from the ClockedObject which looks at the |