diff options
| -rw-r--r-- | src/arch/arm/insts/misc.cc | 15 | ||||
| -rw-r--r-- | src/arch/arm/insts/misc.hh | 18 | ||||
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 2 | ||||
| -rw-r--r-- | src/arch/arm/isa/templates/misc.isa | 26 |
4 files changed, 61 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index b5ae61f5a..3ad49bb9d 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -169,6 +169,21 @@ RegRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const } std::string +RegRegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss); + printReg(ss, dest); + ss << ", "; + printReg(ss, op1); + ss << ", "; + printReg(ss, op2); + ss << ", "; + printReg(ss, op3); + return ss.str(); +} + +std::string RegRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream ss; diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh index 8ab0b352a..7ee2d95f9 100644 --- a/src/arch/arm/insts/misc.hh +++ b/src/arch/arm/insts/misc.hh @@ -142,6 +142,24 @@ class RegRegRegImmOp : public PredOp std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; +class RegRegRegRegOp : public PredOp +{ + protected: + IntRegIndex dest; + IntRegIndex op1; + IntRegIndex op2; + IntRegIndex op3; + + RegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, + IntRegIndex _dest, IntRegIndex _op1, + IntRegIndex _op2, IntRegIndex _op3) : + PredOp(mnem, _machInst, __opClass), + dest(_dest), op1(_op1), op2(_op2), op3(_op3) + {} + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; +}; + class RegRegRegOp : public PredOp { protected: diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index c845acc94..e2b73e2e2 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -102,6 +102,8 @@ def operands {{ maybePCRead, maybePCWrite), 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4, maybePCRead, maybePCWrite), + 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4, + maybePCRead, maybePCWrite), 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5, maybePCRead, maybePCWrite), 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6, diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index 8e781b540..7a9a35ec9 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -146,6 +146,32 @@ def template RegRegRegImmOpConstructor {{ } }}; +def template RegRegRegRegOpDeclare {{ +class %(class_name)s : public %(base_class)s +{ + protected: + public: + // Constructor + %(class_name)s(ExtMachInst machInst, + IntRegIndex _dest, IntRegIndex _op1, + IntRegIndex _op2, IntRegIndex _op3); + %(BasicExecDeclare)s +}; +}}; + +def template RegRegRegRegOpConstructor {{ + inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + IntRegIndex _dest, + IntRegIndex _op1, + IntRegIndex _op2, + IntRegIndex _op3) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, + _dest, _op1, _op2, _op3) + { + %(constructor)s; + } +}}; + def template RegRegRegOpDeclare {{ class %(class_name)s : public %(base_class)s { |