diff options
105 files changed, 231 insertions, 246 deletions
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index c5a8122dd..4a6b3e7cd 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -40,11 +40,11 @@ from m5.SimObject import SimObject from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject from m5.objects.BaseTLB import BaseTLB +from m5.objects.ClockedObject import ClockedObject # Basic stage 1 translation objects -class ArmTableWalker(MemObject): +class ArmTableWalker(ClockedObject): type = 'ArmTableWalker' cxx_class = 'ArmISA::TableWalker' cxx_header = "arch/arm/table_walker.hh" diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index d310e9ee6..6f06b7112 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -57,7 +57,7 @@ using namespace ArmISA; TableWalker::TableWalker(const Params *p) - : MemObject(p), + : ClockedObject(p), stage2Mmu(NULL), port(NULL), masterId(Request::invldMasterId), isStage2(p->is_stage2), tlb(NULL), currState(NULL), pending(false), @@ -124,7 +124,7 @@ TableWalker::getPort(const std::string &if_name, PortID idx) fatal("Cannot access table walker port through stage-two walker\n"); } } - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } TableWalker::WalkerState::WalkerState() : diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index 8176fc7f5..752b57a64 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh @@ -48,6 +48,7 @@ #include "arch/arm/tlb.hh" #include "mem/request.hh" #include "params/ArmTableWalker.hh" +#include "sim/clocked_object.hh" #include "sim/eventq.hh" class ThreadContext; @@ -59,7 +60,7 @@ class Translation; class TLB; class Stage2MMU; -class TableWalker : public MemObject +class TableWalker : public ClockedObject { public: class WalkerState; diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py index 688117a66..64531b9c5 100644 --- a/src/arch/generic/BaseTLB.py +++ b/src/arch/generic/BaseTLB.py @@ -29,9 +29,9 @@ # Ivan Pizarro from m5.params import * -from m5.objects.MemObject import MemObject +from m5.SimObject import SimObject -class BaseTLB(MemObject): +class BaseTLB(SimObject): type = 'BaseTLB' abstract = True cxx_header = "arch/generic/tlb.hh" diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh index ba07b1057..cd33ef4c9 100644 --- a/src/arch/generic/tlb.hh +++ b/src/arch/generic/tlb.hh @@ -44,18 +44,16 @@ #define __ARCH_GENERIC_TLB_HH__ #include "base/logging.hh" -#include "mem/mem_object.hh" #include "mem/request.hh" +#include "sim/sim_object.hh" class ThreadContext; class BaseMasterPort; -class BaseTLB : public MemObject +class BaseTLB : public SimObject { protected: - BaseTLB(const Params *p) - : MemObject(p) - {} + BaseTLB(const Params *p) : SimObject(p) {} public: diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index 1b2f63d1d..2e61d027f 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -39,9 +39,9 @@ from m5.params import * from m5.proxy import * from m5.objects.BaseTLB import BaseTLB -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class X86PagetableWalker(MemObject): +class X86PagetableWalker(ClockedObject): type = 'X86PagetableWalker' cxx_class = 'X86ISA::Walker' cxx_header = 'arch/x86/pagetable_walker.hh' diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc index 0741dc2ed..932eb8eef 100644 --- a/src/arch/x86/pagetable_walker.cc +++ b/src/arch/x86/pagetable_walker.cc @@ -173,7 +173,7 @@ Walker::getPort(const std::string &if_name, PortID idx) if (if_name == "port") return port; else - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } void diff --git a/src/arch/x86/pagetable_walker.hh b/src/arch/x86/pagetable_walker.hh index c1f4ed2c4..88b8147cf 100644 --- a/src/arch/x86/pagetable_walker.hh +++ b/src/arch/x86/pagetable_walker.hh @@ -45,9 +45,9 @@ #include "arch/x86/pagetable.hh" #include "arch/x86/tlb.hh" #include "base/types.hh" -#include "mem/mem_object.hh" #include "mem/packet.hh" #include "params/X86PagetableWalker.hh" +#include "sim/clocked_object.hh" #include "sim/faults.hh" #include "sim/system.hh" @@ -55,7 +55,7 @@ class ThreadContext; namespace X86ISA { - class Walker : public MemObject + class Walker : public ClockedObject { protected: // Port for accessing memory @@ -201,7 +201,7 @@ namespace X86ISA } Walker(const Params *params) : - MemObject(params), port(name() + ".port", this), + ClockedObject(params), port(name() + ".port", this), funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system), masterId(sys->getMasterId(this)), numSquashable(params->num_squash_per_cycle), diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 93cb6e071..6dd460cbe 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -52,10 +52,10 @@ from m5.params import * from m5.proxy import * from m5.util.fdthelper import * +from m5.objects.ClockedObject import ClockedObject from m5.objects.XBar import L2XBar from m5.objects.InstTracer import InstTracer from m5.objects.CPUTracers import ExeTracer -from m5.objects.MemObject import MemObject from m5.objects.SubSystem import SubSystem from m5.objects.ClockDomain import * from m5.objects.Platform import Platform @@ -99,7 +99,7 @@ elif buildEnv['TARGET_ISA'] == 'riscv': from m5.objects.RiscvISA import RiscvISA default_isa_class = RiscvISA -class BaseCPU(MemObject): +class BaseCPU(ClockedObject): type = 'BaseCPU' abstract = True cxx_header = "cpu/base.hh" diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 8e49fb103..a9f68bb26 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -126,7 +126,7 @@ CPUProgressEvent::description() const } BaseCPU::BaseCPU(Params *p, bool is_checker) - : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), + : ClockedObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id), _instMasterId(p->system->getMasterId(this, "inst")), _dataMasterId(p->system->getMasterId(this, "data")), _taskId(ContextSwitchTaskId::Unknown), _pid(invldPid), @@ -421,7 +421,7 @@ BaseCPU::probeInstCommit(const StaticInstPtr &inst, Addr pc) void BaseCPU::regStats() { - MemObject::regStats(); + ClockedObject::regStats(); using namespace Stats; @@ -462,7 +462,7 @@ BaseCPU::getPort(const string &if_name, PortID idx) else if (if_name == "icache_port") return getInstPort(); else - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } void diff --git a/src/cpu/base.hh b/src/cpu/base.hh index f9b24b923..f013a3e02 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -58,7 +58,7 @@ #include "arch/isa_traits.hh" #include "arch/microcode_rom.hh" #include "base/statistics.hh" -#include "mem/mem_object.hh" +#include "sim/clocked_object.hh" #include "sim/eventq.hh" #include "sim/full_system.hh" #include "sim/insttracer.hh" @@ -106,7 +106,7 @@ class CPUProgressEvent : public Event virtual const char *description() const; }; -class BaseCPU : public MemObject +class BaseCPU : public ClockedObject { protected: diff --git a/src/cpu/o3/checker.cc b/src/cpu/o3/checker.cc index 970af5300..16c5a8704 100644 --- a/src/cpu/o3/checker.cc +++ b/src/cpu/o3/checker.cc @@ -45,8 +45,6 @@ #include "cpu/checker/cpu_impl.hh" #include "params/O3Checker.hh" -class MemObject; - template class Checker<O3CPUImpl>; diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 21cae444b..c2c48535f 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -76,7 +76,6 @@ template <class> class O3ThreadContext; class Checkpoint; -class MemObject; class Process; struct BaseCPUParams; diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 49bc1ad73..b687a17e0 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -70,7 +70,6 @@ #include "debug/Decode.hh" #include "debug/Fetch.hh" #include "debug/Quiesce.hh" -#include "mem/mem_object.hh" #include "mem/packet.hh" #include "mem/request.hh" #include "params/BaseSimpleCPU.hh" diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc b/src/cpu/testers/directedtest/RubyDirectedTester.cc index cd367b498..afe2b1447 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.cc +++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc @@ -47,7 +47,7 @@ #include "sim/sim_exit.hh" RubyDirectedTester::RubyDirectedTester(const Params *p) - : MemObject(p), + : ClockedObject(p), directedStartEvent([this]{ wakeup(); }, "Directed tick", false, Event::CPU_Tick_Pri), m_requests_to_complete(p->requests_to_complete), @@ -83,7 +83,7 @@ RubyDirectedTester::getPort(const std::string &if_name, PortID idx) { if (if_name != "cpuPort") { // pass it along to our super class - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } else { if (idx >= static_cast<int>(ports.size())) { panic("RubyDirectedTester::getPort: unknown index %d\n", idx); diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh index 740843562..f0c694e82 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.hh +++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh @@ -34,16 +34,17 @@ #include <string> #include <vector> +#include "mem/packet.hh" +#include "mem/port.hh" #include "mem/ruby/common/DataBlock.hh" #include "mem/ruby/common/SubBlock.hh" #include "mem/ruby/common/TypeDefines.hh" -#include "mem/mem_object.hh" -#include "mem/packet.hh" #include "params/RubyDirectedTester.hh" +#include "sim/clocked_object.hh" class DirectedGenerator; -class RubyDirectedTester : public MemObject +class RubyDirectedTester : public ClockedObject { public: class CpuPort : public MasterPort diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py index 9f90c9b41..5b513e42e 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.py +++ b/src/cpu/testers/directedtest/RubyDirectedTester.py @@ -30,7 +30,7 @@ from m5.SimObject import SimObject from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject class DirectedGenerator(SimObject): type = 'DirectedGenerator' @@ -52,7 +52,7 @@ class InvalidateGenerator(DirectedGenerator): cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh" addr_increment_size = Param.Int(64, "address increment size") -class RubyDirectedTester(MemObject): +class RubyDirectedTester(ClockedObject): type = 'RubyDirectedTester' cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh" cpuPort = VectorMasterPort("the cpu ports") diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc index 1a07205e6..5b542bc19 100644 --- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc +++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.cc @@ -40,7 +40,6 @@ #include "base/random.hh" #include "base/statistics.hh" #include "debug/GarnetSyntheticTraffic.hh" -#include "mem/mem_object.hh" #include "mem/packet.hh" #include "mem/port.hh" #include "mem/request.hh" @@ -75,7 +74,7 @@ GarnetSyntheticTraffic::sendPkt(PacketPtr pkt) } GarnetSyntheticTraffic::GarnetSyntheticTraffic(const Params *p) - : MemObject(p), + : ClockedObject(p), tickEvent([this]{ tick(); }, "GarnetSyntheticTraffic tick", false, Event::CPU_Tick_Pri), cachePort("GarnetSyntheticTraffic", this), @@ -116,7 +115,7 @@ GarnetSyntheticTraffic::getPort(const std::string &if_name, PortID idx) if (if_name == "test") return cachePort; else - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } void diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh index 7f9ca5f7c..3e77e9e0c 100644 --- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh +++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh @@ -34,9 +34,9 @@ #include <set> #include "base/statistics.hh" -#include "mem/mem_object.hh" #include "mem/port.hh" #include "params/GarnetSyntheticTraffic.hh" +#include "sim/clocked_object.hh" #include "sim/eventq.hh" #include "sim/sim_exit.hh" #include "sim/sim_object.hh" @@ -53,7 +53,7 @@ enum TrafficType {BIT_COMPLEMENT_ = 0, NUM_TRAFFIC_PATTERNS_}; class Packet; -class GarnetSyntheticTraffic : public MemObject +class GarnetSyntheticTraffic : public ClockedObject { public: typedef GarnetSyntheticTrafficParams Params; diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py index 4c7772348..ba99db455 100644 --- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py +++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py @@ -26,11 +26,11 @@ # # Authors: Tushar Krishna -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject from m5.params import * from m5.proxy import * -class GarnetSyntheticTraffic(MemObject): +class GarnetSyntheticTraffic(ClockedObject): type = 'GarnetSyntheticTraffic' cxx_header = \ "cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh" diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py index 5585b1f70..b4eb0b528 100644 --- a/src/cpu/testers/memtest/MemTest.py +++ b/src/cpu/testers/memtest/MemTest.py @@ -41,9 +41,9 @@ from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class MemTest(MemObject): +class MemTest(ClockedObject): type = 'MemTest' cxx_header = "cpu/testers/memtest/memtest.hh" diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc index 346f88246..93a6ac6b9 100644 --- a/src/cpu/testers/memtest/memtest.cc +++ b/src/cpu/testers/memtest/memtest.cc @@ -48,7 +48,6 @@ #include "base/statistics.hh" #include "base/trace.hh" #include "debug/MemTest.hh" -#include "mem/mem_object.hh" #include "sim/sim_exit.hh" #include "sim/stats.hh" #include "sim/system.hh" @@ -85,7 +84,7 @@ MemTest::sendPkt(PacketPtr pkt) { } MemTest::MemTest(const Params *p) - : MemObject(p), + : ClockedObject(p), tickEvent([this]{ tick(); }, name()), noRequestEvent([this]{ noRequest(); }, name()), noResponseEvent([this]{ noResponse(); }, name()), @@ -130,7 +129,7 @@ MemTest::getPort(const std::string &if_name, PortID idx) if (if_name == "port") return port; else - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } void @@ -197,7 +196,7 @@ MemTest::completeRequest(PacketPtr pkt, bool functional) void MemTest::regStats() { - MemObject::regStats(); + ClockedObject::regStats(); using namespace Stats; diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh index b429fed69..f536f0369 100644 --- a/src/cpu/testers/memtest/memtest.hh +++ b/src/cpu/testers/memtest/memtest.hh @@ -49,8 +49,9 @@ #include <unordered_map> #include "base/statistics.hh" -#include "mem/mem_object.hh" +#include "mem/port.hh" #include "params/MemTest.hh" +#include "sim/clocked_object.hh" #include "sim/eventq.hh" #include "sim/stats.hh" @@ -67,7 +68,7 @@ * both requests and responses, thus checking that the memory-system * is making progress. */ -class MemTest : public MemObject +class MemTest : public ClockedObject { public: diff --git a/src/cpu/testers/rubytest/RubyTester.cc b/src/cpu/testers/rubytest/RubyTester.cc index cb23688c4..30af47586 100644 --- a/src/cpu/testers/rubytest/RubyTester.cc +++ b/src/cpu/testers/rubytest/RubyTester.cc @@ -50,7 +50,7 @@ #include "sim/system.hh" RubyTester::RubyTester(const Params *p) - : MemObject(p), + : ClockedObject(p), checkStartEvent([this]{ wakeup(); }, "RubyTester tick", false, Event::CPU_Tick_Pri), _masterId(p->system->getMasterId(this)), @@ -134,7 +134,7 @@ RubyTester::getPort(const std::string &if_name, PortID idx) if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" && if_name != "cpuDataPort") { // pass it along to our super class - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } else { if (if_name == "cpuInstPort") { if (idx > m_num_inst_only_ports) { diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh index 3ca71f608..4ac553b4c 100644 --- a/src/cpu/testers/rubytest/RubyTester.hh +++ b/src/cpu/testers/rubytest/RubyTester.hh @@ -47,13 +47,14 @@ #include <vector> #include "cpu/testers/rubytest/CheckTable.hh" -#include "mem/mem_object.hh" #include "mem/packet.hh" +#include "mem/port.hh" #include "mem/ruby/common/SubBlock.hh" #include "mem/ruby/common/TypeDefines.hh" #include "params/RubyTester.hh" +#include "sim/clocked_object.hh" -class RubyTester : public MemObject +class RubyTester : public ClockedObject { public: class CpuPort : public MasterPort diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py index 2ac1697fd..ecf52b668 100644 --- a/src/cpu/testers/rubytest/RubyTester.py +++ b/src/cpu/testers/rubytest/RubyTester.py @@ -28,9 +28,9 @@ from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class RubyTester(MemObject): +class RubyTester(ClockedObject): type = 'RubyTester' cxx_header = "cpu/testers/rubytest/RubyTester.hh" num_cpus = Param.Int("number of cpus / RubyPorts") diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py b/src/cpu/testers/traffic_gen/BaseTrafficGen.py index 94e3319d5..7fd8b3066 100644 --- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py +++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py @@ -39,7 +39,7 @@ from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject # Types of Stream Generators. # Those are orthogonal to the other generators in the TrafficGen @@ -55,7 +55,7 @@ class StreamGenType(Enum): vals = [ 'none', 'fixed', 'random' ] # controllers, or function as a black-box replacement for system # components that are not yet modelled in detail, e.g. a video engine # or baseband subsystem in an SoC. -class BaseTrafficGen(MemObject): +class BaseTrafficGen(ClockedObject): type = 'BaseTrafficGen' abstract = True cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh" diff --git a/src/cpu/testers/traffic_gen/base.cc b/src/cpu/testers/traffic_gen/base.cc index 80fa8a9d6..43a1b831a 100644 --- a/src/cpu/testers/traffic_gen/base.cc +++ b/src/cpu/testers/traffic_gen/base.cc @@ -68,7 +68,7 @@ using namespace std; BaseTrafficGen::BaseTrafficGen(const BaseTrafficGenParams* p) - : MemObject(p), + : ClockedObject(p), system(p->system), elasticReq(p->elastic_req), progressCheck(p->progress_check), @@ -94,14 +94,14 @@ BaseTrafficGen::getPort(const string &if_name, PortID idx) if (if_name == "port") { return port; } else { - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } } void BaseTrafficGen::init() { - MemObject::init(); + ClockedObject::init(); if (!port.isConnected()) fatal("The port of %s is not connected!\n", name()); diff --git a/src/cpu/testers/traffic_gen/base.hh b/src/cpu/testers/traffic_gen/base.hh index 2443e6223..811770fe4 100644 --- a/src/cpu/testers/traffic_gen/base.hh +++ b/src/cpu/testers/traffic_gen/base.hh @@ -46,8 +46,8 @@ #include <tuple> #include "base/statistics.hh" -#include "mem/mem_object.hh" #include "mem/qport.hh" +#include "sim/clocked_object.hh" class BaseGen; class StreamGen; @@ -63,7 +63,7 @@ struct BaseTrafficGenParams; * system components that are not yet modelled in detail, e.g. a video * engine or baseband subsystem. */ -class BaseTrafficGen : public MemObject +class BaseTrafficGen : public ClockedObject { friend class BaseGen; diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index e3b6af9da..574193d0e 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -36,7 +36,6 @@ #include "cpu/base.hh" #include "cpu/profile.hh" #include "cpu/thread_context.hh" -#include "mem/mem_object.hh" #include "sim/process.hh" class EndQuiesceEvent; diff --git a/src/dev/Device.py b/src/dev/Device.py index c137ce66d..cb990104d 100644 --- a/src/dev/Device.py +++ b/src/dev/Device.py @@ -43,9 +43,9 @@ from m5.params import * from m5.proxy import * from m5.util.fdthelper import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class PioDevice(MemObject): +class PioDevice(ClockedObject): type = 'PioDevice' cxx_header = "dev/io_device.hh" abstract = True diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc index 047eef1d7..327c92436 100644 --- a/src/dev/dma_device.cc +++ b/src/dev/dma_device.cc @@ -51,9 +51,10 @@ #include "debug/DMA.hh" #include "debug/Drain.hh" #include "mem/port_proxy.hh" +#include "sim/clocked_object.hh" #include "sim/system.hh" -DmaPort::DmaPort(MemObject *dev, System *s) +DmaPort::DmaPort(ClockedObject *dev, System *s) : MasterPort(dev->name() + ".dma", dev), device(dev), sys(s), masterId(s->getMasterId(dev)), sendEvent([this]{ sendDma(); }, dev->name()), diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh index f556e14e3..4ea062654 100644 --- a/src/dev/dma_device.hh +++ b/src/dev/dma_device.hh @@ -54,6 +54,8 @@ #include "sim/drain.hh" #include "sim/system.hh" +class ClockedObject; + class DmaPort : public MasterPort, public Drainable { private: @@ -109,7 +111,7 @@ class DmaPort : public MasterPort, public Drainable public: /** The device that owns this port. */ - MemObject *const device; + ClockedObject *const device; /** The system that device/port are in. This is used to select which mode * we are currently operating in. */ @@ -141,7 +143,7 @@ class DmaPort : public MasterPort, public Drainable public: - DmaPort(MemObject *dev, System *s); + DmaPort(ClockedObject *dev, System *s); RequestPtr dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, uint8_t *data, Tick delay, Request::Flags flag = 0); diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc index 1cec2bf4a..425c2f41f 100644 --- a/src/dev/io_device.cc +++ b/src/dev/io_device.cc @@ -72,7 +72,7 @@ PioPort::getAddrRanges() const } PioDevice::PioDevice(const Params *p) - : MemObject(p), sys(p->system), pioPort(this) + : ClockedObject(p), sys(p->system), pioPort(this) {} PioDevice::~PioDevice() @@ -93,7 +93,7 @@ PioDevice::getPort(const std::string &if_name, PortID idx) if (if_name == "pio") { return pioPort; } - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } BasicPioDevice::BasicPioDevice(const Params *p, Addr size) diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh index 8dc3f943a..c9e25d224 100644 --- a/src/dev/io_device.hh +++ b/src/dev/io_device.hh @@ -44,10 +44,10 @@ #ifndef __DEV_IO_DEVICE_HH__ #define __DEV_IO_DEVICE_HH__ -#include "mem/mem_object.hh" #include "mem/tport.hh" #include "params/BasicPioDevice.hh" #include "params/PioDevice.hh" +#include "sim/clocked_object.hh" class PioDevice; class System; @@ -81,7 +81,7 @@ class PioPort : public SimpleTimingPort * mode we are in, etc is handled by the PioPort so the device doesn't have to * bother. */ -class PioDevice : public MemObject +class PioDevice : public ClockedObject { protected: System *sys; diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh index 1a49bb3e2..2e3e99df0 100644 --- a/src/dev/x86/intdev.hh +++ b/src/dev/x86/intdev.hh @@ -49,7 +49,6 @@ #include "arch/x86/intmessage.hh" #include "arch/x86/x86_traits.hh" -#include "mem/mem_object.hh" #include "mem/mport.hh" #include "params/X86IntLine.hh" #include "params/X86IntSinkPin.hh" @@ -68,7 +67,7 @@ class IntDevice IntDevice * device; public: - IntSlavePort(const std::string& _name, MemObject* _parent, + IntSlavePort(const std::string& _name, SimObject* _parent, IntDevice* dev) : MessageSlavePort(_name, _parent), device(dev) { @@ -92,7 +91,7 @@ class IntDevice IntDevice* device; Tick latency; public: - IntMasterPort(const std::string& _name, MemObject* _parent, + IntMasterPort(const std::string& _name, SimObject* _parent, IntDevice* dev, Tick _latency) : MessageMasterPort(_name, _parent), device(dev), latency(_latency) { @@ -112,7 +111,7 @@ class IntDevice IntMasterPort intMasterPort; public: - IntDevice(MemObject * parent, Tick latency = 0) : + IntDevice(SimObject * parent, Tick latency = 0) : intMasterPort(parent->name() + ".int_master", parent, this, latency) { } diff --git a/src/doc/memory_system.doxygen b/src/doc/memory_system.doxygen index 061a289ee..4fe982068 100644 --- a/src/doc/memory_system.doxygen +++ b/src/doc/memory_system.doxygen @@ -51,13 +51,13 @@ configs/example/fs.py --caches --cpu-type=arm_detailed --num-cpus=2 - Gem5 uses Memory Objects (MemObject) derived objects as basic blocks for + Gem5 uses Simulation Objects (SimObject) derived objects as basic blocks for building memory system. They are connected via ports with established master/slave hierarchy. Data flow is initiated on master port while the response messages and snoop queries appear on the slave port. The following - figure shows the hierarchy of Memory Objects used in this document: + figure shows the hierarchy of Simulation Objects used in this document: - \image html "gem5_MS_Fig1.PNG" "Memory Object hierarchy of the model" width=3cm + \image html "gem5_MS_Fig1.PNG" "Simulation Object hierarchy of the model" width=3cm \section gem5_CPU CPU @@ -77,7 +77,7 @@ Load & store buffers (for read and write access) don’t impose any restriction on the number of active memory accesses. Therefore, the maximum number of outstanding CPU’s memory access requests is not limited by CPU - Memory Object but by underlying memory system model. + Simulation Object but by underlying memory system model. <b>Split memory access</b> is implemented. @@ -89,7 +89,7 @@ Data Cache object implements a standard cache structure: - \image html "gem5_MS_Fig2.PNG" "DCache Memory Object" width=3cm + \image html "gem5_MS_Fig2.PNG" "DCache Simulation Object" width=3cm <b>Cached memory reads</b> that match particular cache tag (with Valid & Read flags) will be completed (by sending ReadResp to CPU) after a configurable time. diff --git a/src/gpu-compute/GPU.py b/src/gpu-compute/GPU.py index 9eb662abc..fee025435 100644 --- a/src/gpu-compute/GPU.py +++ b/src/gpu-compute/GPU.py @@ -40,7 +40,6 @@ from m5.SimObject import SimObject from m5.objects.ClockedObject import ClockedObject from m5.objects.Device import DmaDevice -from m5.objects.MemObject import MemObject from m5.objects.Process import EmulatedDriver from m5.objects.Bridge import Bridge from m5.objects.LdsState import LdsState @@ -72,7 +71,7 @@ class Wavefront(SimObject): wf_slot_id = Param.Int('wavefront id (0-ComputeUnit.max_wfs)') wfSize = Param.Int(64, 'Wavefront size (in work items)') -class ComputeUnit(MemObject): +class ComputeUnit(ClockedObject): type = 'ComputeUnit' cxx_class = 'ComputeUnit' cxx_header = 'gpu-compute/compute_unit.hh' diff --git a/src/gpu-compute/LdsState.py b/src/gpu-compute/LdsState.py index f1f8cd18a..a21bde06e 100644 --- a/src/gpu-compute/LdsState.py +++ b/src/gpu-compute/LdsState.py @@ -35,9 +35,9 @@ from m5.defines import buildEnv from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class LdsState(MemObject): +class LdsState(ClockedObject): type = 'LdsState' cxx_class = 'LdsState' cxx_header = 'gpu-compute/lds_state.hh' diff --git a/src/gpu-compute/X86GPUTLB.py b/src/gpu-compute/X86GPUTLB.py index 963e2d147..a0ac9e9e6 100644 --- a/src/gpu-compute/X86GPUTLB.py +++ b/src/gpu-compute/X86GPUTLB.py @@ -35,16 +35,17 @@ from m5.defines import buildEnv from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject +from m5.SimObject import SimObject if buildEnv['FULL_SYSTEM']: - class X86PagetableWalker(MemObject): + class X86PagetableWalker(SimObject): type = 'X86PagetableWalker' cxx_class = 'X86ISA::Walker' port = SlavePort("Port for the hardware table walker") system = Param.System(Parent.any, "system object") -class X86GPUTLB(MemObject): +class X86GPUTLB(ClockedObject): type = 'X86GPUTLB' cxx_class = 'X86ISA::GpuTLB' cxx_header = 'gpu-compute/gpu_tlb.hh' @@ -64,7 +65,7 @@ class X86GPUTLB(MemObject): allocationPolicy = Param.Bool(True, "Allocate on an access") accessDistance = Param.Bool(False, "print accessDistance stats") -class TLBCoalescer(MemObject): +class TLBCoalescer(ClockedObject): type = 'TLBCoalescer' cxx_class = 'TLBCoalescer' cxx_header = 'gpu-compute/tlb_coalescer.hh' diff --git a/src/gpu-compute/compute_unit.cc b/src/gpu-compute/compute_unit.cc index fd328adca..a9571eed1 100644 --- a/src/gpu-compute/compute_unit.cc +++ b/src/gpu-compute/compute_unit.cc @@ -58,7 +58,7 @@ #include "mem/page_table.hh" #include "sim/process.hh" -ComputeUnit::ComputeUnit(const Params *p) : MemObject(p), fetchStage(p), +ComputeUnit::ComputeUnit(const Params *p) : ClockedObject(p), fetchStage(p), scoreboardCheckStage(p), scheduleStage(p), execStage(p), globalMemoryPipe(p), localMemoryPipe(p), rrNextMemID(0), rrNextALUWp(0), cu_id(p->cu_id), vrf(p->vector_register_file), numSIMDs(p->num_SIMDs), @@ -1397,7 +1397,7 @@ ComputeUnit::ITLBPort::recvReqRetry() void ComputeUnit::regStats() { - MemObject::regStats(); + ClockedObject::regStats(); vALUInsts .name(name() + ".valu_insts") diff --git a/src/gpu-compute/compute_unit.hh b/src/gpu-compute/compute_unit.hh index cfe25d7d8..adf3c21d2 100644 --- a/src/gpu-compute/compute_unit.hh +++ b/src/gpu-compute/compute_unit.hh @@ -53,8 +53,8 @@ #include "gpu-compute/qstruct.hh" #include "gpu-compute/schedule_stage.hh" #include "gpu-compute/scoreboard_check_stage.hh" -#include "mem/mem_object.hh" #include "mem/port.hh" +#include "sim/clocked_object.hh" static const int MAX_REGS_FOR_NON_VEC_MEM_INST = 1; static const int MAX_WIDTH_FOR_MEM_INST = 32; @@ -91,7 +91,7 @@ enum TLB_CACHE TLB_HIT_CACHE_HIT }; -class ComputeUnit : public MemObject +class ComputeUnit : public ClockedObject { public: FetchStage fetchStage; diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc index c23b9986f..ee405e872 100644 --- a/src/gpu-compute/gpu_tlb.cc +++ b/src/gpu-compute/gpu_tlb.cc @@ -61,7 +61,7 @@ namespace X86ISA { GpuTLB::GpuTLB(const Params *p) - : MemObject(p), configAddress(0), size(p->size), + : ClockedObject(p), configAddress(0), size(p->size), cleanupEvent([this]{ cleanup(); }, name(), false, Event::Maximum_Pri), exitEvent([this]{ exitCallback(); }, name()) @@ -950,7 +950,7 @@ namespace X86ISA void GpuTLB::regStats() { - MemObject::regStats(); + ClockedObject::regStats(); localNumTLBAccesses .name(name() + ".local_TLB_accesses") diff --git a/src/gpu-compute/gpu_tlb.hh b/src/gpu-compute/gpu_tlb.hh index 80510d7a0..766d2d1b9 100644 --- a/src/gpu-compute/gpu_tlb.hh +++ b/src/gpu-compute/gpu_tlb.hh @@ -50,10 +50,10 @@ #include "base/logging.hh" #include "base/statistics.hh" #include "gpu-compute/compute_unit.hh" -#include "mem/mem_object.hh" #include "mem/port.hh" #include "mem/request.hh" #include "params/X86GPUTLB.hh" +#include "sim/clocked_object.hh" #include "sim/sim_object.hh" class BaseTLB; @@ -62,7 +62,7 @@ class ThreadContext; namespace X86ISA { - class GpuTLB : public MemObject + class GpuTLB : public ClockedObject { protected: friend class Walker; diff --git a/src/gpu-compute/lds_state.cc b/src/gpu-compute/lds_state.cc index 48827c514..459a7a4cc 100644 --- a/src/gpu-compute/lds_state.cc +++ b/src/gpu-compute/lds_state.cc @@ -48,7 +48,7 @@ * the default constructor that works with SWIG */ LdsState::LdsState(const Params *params) : - MemObject(params), + ClockedObject(params), tickEvent(this), cuPort(name() + ".port", this), maximumSize(params->size), diff --git a/src/gpu-compute/lds_state.hh b/src/gpu-compute/lds_state.hh index 05bc11ed6..9b9cb1264 100644 --- a/src/gpu-compute/lds_state.hh +++ b/src/gpu-compute/lds_state.hh @@ -46,9 +46,9 @@ #include "enums/MemType.hh" #include "gpu-compute/misc.hh" -#include "mem/mem_object.hh" #include "mem/port.hh" #include "params/LdsState.hh" +#include "sim/clocked_object.hh" class ComputeUnit; @@ -108,7 +108,7 @@ class LdsChunk // Local Data Share (LDS) State per Wavefront (contents of the LDS region // allocated to the WorkGroup of this Wavefront) -class LdsState: public MemObject +class LdsState: public ClockedObject { protected: diff --git a/src/gpu-compute/tlb_coalescer.cc b/src/gpu-compute/tlb_coalescer.cc index 3b7631a74..999007c13 100644 --- a/src/gpu-compute/tlb_coalescer.cc +++ b/src/gpu-compute/tlb_coalescer.cc @@ -42,7 +42,7 @@ #include "sim/process.hh" TLBCoalescer::TLBCoalescer(const Params *p) - : MemObject(p), + : ClockedObject(p), clock(p->clk_domain->clockPeriod()), TLBProbesPerCycle(p->probesPerCycle), coalescingWindow(p->coalescingWindow), @@ -525,7 +525,7 @@ TLBCoalescer::processCleanupEvent() void TLBCoalescer::regStats() { - MemObject::regStats(); + ClockedObject::regStats(); uncoalescedAccesses .name(name() + ".uncoalesced_accesses") diff --git a/src/gpu-compute/tlb_coalescer.hh b/src/gpu-compute/tlb_coalescer.hh index 2aff81027..b65f1b0fb 100644 --- a/src/gpu-compute/tlb_coalescer.hh +++ b/src/gpu-compute/tlb_coalescer.hh @@ -49,23 +49,23 @@ #include "base/logging.hh" #include "base/statistics.hh" #include "gpu-compute/gpu_tlb.hh" -#include "mem/mem_object.hh" #include "mem/port.hh" #include "mem/request.hh" #include "params/TLBCoalescer.hh" +#include "sim/clocked_object.hh" class BaseTLB; class Packet; class ThreadContext; /** - * The TLBCoalescer is a MemObject sitting on the front side (CPUSide) of + * The TLBCoalescer is a ClockedObject sitting on the front side (CPUSide) of * each TLB. It receives packets and issues coalesced requests to the * TLB below it. It controls how requests are coalesced (the rules) * and the permitted number of TLB probes per cycle (i.e., how many * coalesced requests it feeds the TLB per cycle). */ -class TLBCoalescer : public MemObject +class TLBCoalescer : public ClockedObject { protected: // TLB clock: will inherit clock from shader's clock period in terms diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py index 5bffc30af..5b4c718c2 100644 --- a/src/mem/AbstractMemory.py +++ b/src/mem/AbstractMemory.py @@ -40,9 +40,9 @@ # Andreas Hansson from m5.params import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class AbstractMemory(MemObject): +class AbstractMemory(ClockedObject): type = 'AbstractMemory' abstract = True cxx_header = "mem/abstract_mem.hh" diff --git a/src/mem/AddrMapper.py b/src/mem/AddrMapper.py index a1ddaeb7a..d2136f504 100644 --- a/src/mem/AddrMapper.py +++ b/src/mem/AddrMapper.py @@ -36,7 +36,7 @@ # Authors: Andreas Hansson from m5.params import * -from m5.objects.MemObject import MemObject +from m5.SimObject import SimObject # An address mapper changes the packet addresses in going from the # slave port side of the mapper to the master port side. When the @@ -44,7 +44,7 @@ from m5.objects.MemObject import MemObject # necessary range updates. Note that snoop requests that travel from # the master port (i.e. the memory side) to the slave port are # currently not modified. -class AddrMapper(MemObject): +class AddrMapper(SimObject): type = 'AddrMapper' cxx_header = 'mem/addr_mapper.hh' abstract = True diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py index 34af552e3..9e86c1a41 100644 --- a/src/mem/Bridge.py +++ b/src/mem/Bridge.py @@ -40,9 +40,9 @@ # Andreas Hansson from m5.params import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class Bridge(MemObject): +class Bridge(ClockedObject): type = 'Bridge' cxx_header = "mem/bridge.hh" slave = SlavePort('Slave port') diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py index fc53ef1f0..d63243722 100644 --- a/src/mem/CommMonitor.py +++ b/src/mem/CommMonitor.py @@ -38,12 +38,12 @@ from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject from m5.objects.System import System +from m5.SimObject import SimObject # The communication monitor will most typically be used in combination # with periodic dumping and resetting of stats using schedStatEvent -class CommMonitor(MemObject): +class CommMonitor(SimObject): type = 'CommMonitor' cxx_header = "mem/comm_monitor.hh" diff --git a/src/mem/ExternalMaster.py b/src/mem/ExternalMaster.py index 883e27727..5a9a5bf9d 100644 --- a/src/mem/ExternalMaster.py +++ b/src/mem/ExternalMaster.py @@ -39,9 +39,9 @@ from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.SimObject import SimObject -class ExternalMaster(MemObject): +class ExternalMaster(SimObject): type = 'ExternalMaster' cxx_header = "mem/external_master.hh" diff --git a/src/mem/ExternalSlave.py b/src/mem/ExternalSlave.py index 7be5fd8a9..c5fd628f7 100644 --- a/src/mem/ExternalSlave.py +++ b/src/mem/ExternalSlave.py @@ -36,9 +36,9 @@ # Authors: Andrew Bardsley from m5.params import * -from m5.objects.MemObject import MemObject +from m5.SimObject import SimObject -class ExternalSlave(MemObject): +class ExternalSlave(SimObject): type = 'ExternalSlave' cxx_header = "mem/external_slave.hh" diff --git a/src/mem/MemChecker.py b/src/mem/MemChecker.py index 7460cd13b..4a7adc8fe 100644 --- a/src/mem/MemChecker.py +++ b/src/mem/MemChecker.py @@ -35,7 +35,6 @@ # # Authors: Marco Elver -from m5.objects.MemObject import MemObject from m5.SimObject import SimObject from m5.params import * from m5.proxy import * @@ -44,7 +43,7 @@ class MemChecker(SimObject): type = 'MemChecker' cxx_header = "mem/mem_checker.hh" -class MemCheckerMonitor(MemObject): +class MemCheckerMonitor(SimObject): type = 'MemCheckerMonitor' cxx_header = "mem/mem_checker_monitor.hh" diff --git a/src/mem/MemDelay.py b/src/mem/MemDelay.py index 415cef4ce..2dedf3267 100644 --- a/src/mem/MemDelay.py +++ b/src/mem/MemDelay.py @@ -36,9 +36,9 @@ # Authors: Andreas Sandberg from m5.params import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class MemDelay(MemObject): +class MemDelay(ClockedObject): type = 'MemDelay' cxx_header = 'mem/mem_delay.hh' abstract = True diff --git a/src/mem/SerialLink.py b/src/mem/SerialLink.py index 02dcd4c7e..3331aeea6 100644 --- a/src/mem/SerialLink.py +++ b/src/mem/SerialLink.py @@ -42,12 +42,12 @@ # Erfan Azarkhish from m5.params import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject # SerialLink is a simple variation of the Bridge class, with the ability to # account for the latency of packet serialization. -class SerialLink(MemObject): +class SerialLink(ClockedObject): type = 'SerialLink' cxx_header = "mem/serial_link.hh" slave = SlavePort('Slave port') diff --git a/src/mem/XBar.py b/src/mem/XBar.py index c9f35f3e5..976a290eb 100644 --- a/src/mem/XBar.py +++ b/src/mem/XBar.py @@ -44,9 +44,9 @@ from m5.params import * from m5.proxy import * from m5.SimObject import SimObject -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class BaseXBar(MemObject): +class BaseXBar(ClockedObject): type = 'BaseXBar' abstract = True cxx_header = "mem/xbar.hh" diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc index 3f2d50713..f7b02ce17 100644 --- a/src/mem/abstract_mem.cc +++ b/src/mem/abstract_mem.cc @@ -57,7 +57,7 @@ using namespace std; AbstractMemory::AbstractMemory(const Params *p) : - MemObject(p), range(params()->range), pmemAddr(NULL), + ClockedObject(p), range(params()->range), pmemAddr(NULL), backdoor(params()->range, nullptr, (MemBackdoor::Flags)(MemBackdoor::Readable | MemBackdoor::Writeable)), @@ -91,7 +91,7 @@ AbstractMemory::setBackingStore(uint8_t* pmem_addr) void AbstractMemory::regStats() { - MemObject::regStats(); + ClockedObject::regStats(); using namespace Stats; diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh index cf9ca7439..18d8ee909 100644 --- a/src/mem/abstract_mem.hh +++ b/src/mem/abstract_mem.hh @@ -50,8 +50,9 @@ #define __MEM_ABSTRACT_MEMORY_HH__ #include "mem/backdoor.hh" -#include "mem/mem_object.hh" +#include "mem/port.hh" #include "params/AbstractMemory.hh" +#include "sim/clocked_object.hh" #include "sim/stats.hh" @@ -98,10 +99,10 @@ class LockedAddr { * An abstract memory represents a contiguous block of physical * memory, with an associated address range, and also provides basic * functionality for reading and writing this memory without any - * timing information. It is a MemObject since any subclass must have - * at least one slave port. + * timing information. It is a ClockedObject since subclasses may need timing + * information. */ -class AbstractMemory : public MemObject +class AbstractMemory : public ClockedObject { protected: diff --git a/src/mem/addr_mapper.cc b/src/mem/addr_mapper.cc index 958a8ad4c..246c039ee 100644 --- a/src/mem/addr_mapper.cc +++ b/src/mem/addr_mapper.cc @@ -40,7 +40,7 @@ #include "mem/addr_mapper.hh" AddrMapper::AddrMapper(const AddrMapperParams* p) - : MemObject(p), + : SimObject(p), masterPort(name() + "-master", *this), slavePort(name() + "-slave", *this) { @@ -61,7 +61,7 @@ AddrMapper::getPort(const std::string &if_name, PortID idx) } else if (if_name == "slave") { return slavePort; } else { - return MemObject::getPort(if_name, idx); + return SimObject::getPort(if_name, idx); } } diff --git a/src/mem/addr_mapper.hh b/src/mem/addr_mapper.hh index aaefdedc3..e6229d67a 100644 --- a/src/mem/addr_mapper.hh +++ b/src/mem/addr_mapper.hh @@ -40,9 +40,10 @@ #ifndef __MEM_ADDR_MAPPER_HH__ #define __MEM_ADDR_MAPPER_HH__ -#include "mem/mem_object.hh" +#include "mem/port.hh" #include "params/AddrMapper.hh" #include "params/RangeAddrMapper.hh" +#include "sim/sim_object.hh" /** * An address mapper changes the packet addresses in going from the @@ -53,7 +54,7 @@ * currently not modified. */ -class AddrMapper : public MemObject +class AddrMapper : public SimObject { public: diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index 7428e7f77..9c4241097 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -77,7 +77,7 @@ Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name, } Bridge::Bridge(Params *p) - : MemObject(p), + : ClockedObject(p), slavePort(p->name + ".slave", *this, masterPort, ticksToCycles(p->delay), p->resp_size, p->ranges), masterPort(p->name + ".master", *this, slavePort, @@ -94,7 +94,7 @@ Bridge::getPort(const std::string &if_name, PortID idx) return slavePort; else // pass it along to our super class - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } void diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index b3fb90d93..16b21addf 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -54,8 +54,9 @@ #include <deque> #include "base/types.hh" -#include "mem/mem_object.hh" +#include "mem/port.hh" #include "params/Bridge.hh" +#include "sim/clocked_object.hh" /** * A bridge is used to interface two different crossbars (or in general a @@ -70,7 +71,7 @@ * the bridge will delay accepting the packet until space becomes * available. */ -class Bridge : public MemObject +class Bridge : public ClockedObject { protected: diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py index 0a590c2ca..b2f478472 100644 --- a/src/mem/cache/Cache.py +++ b/src/mem/cache/Cache.py @@ -43,7 +43,7 @@ from m5.params import * from m5.proxy import * from m5.SimObject import SimObject -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject from m5.objects.Prefetcher import BasePrefetcher from m5.objects.ReplacementPolicies import * from m5.objects.Tags import * @@ -72,7 +72,7 @@ class WriteAllocator(SimObject): block_size = Param.Int(Parent.cache_line_size, "block size in bytes") -class BaseCache(MemObject): +class BaseCache(ClockedObject): type = 'BaseCache' abstract = True cxx_header = "mem/cache/base.hh" diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 554a61eb0..f087618c7 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -77,7 +77,7 @@ BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, } BaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) - : MemObject(p), + : ClockedObject(p), cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"), memSidePort(p->name + ".mem_side", this, "MemSidePort"), mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below @@ -193,7 +193,7 @@ BaseCache::getPort(const std::string &if_name, PortID idx) } else if (if_name == "cpu_side") { return cpuSidePort; } else { - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } } @@ -1696,7 +1696,7 @@ BaseCache::unserialize(CheckpointIn &cp) void BaseCache::regStats() { - MemObject::regStats(); + ClockedObject::regStats(); using namespace Stats; diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index 8d5ed11d0..b995a6e47 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -68,12 +68,12 @@ #include "mem/cache/tags/base.hh" #include "mem/cache/write_queue.hh" #include "mem/cache/write_queue_entry.hh" -#include "mem/mem_object.hh" #include "mem/packet.hh" #include "mem/packet_queue.hh" #include "mem/qport.hh" #include "mem/request.hh" #include "params/WriteAllocator.hh" +#include "sim/clocked_object.hh" #include "sim/eventq.hh" #include "sim/probe/probe.hh" #include "sim/serialize.hh" @@ -91,7 +91,7 @@ struct BaseCacheParams; /** * A basic cache interface. Implements some common functions for speed. */ -class BaseCache : public MemObject +class BaseCache : public ClockedObject { protected: /** diff --git a/src/mem/comm_monitor.cc b/src/mem/comm_monitor.cc index f27027dfd..90268bf3f 100644 --- a/src/mem/comm_monitor.cc +++ b/src/mem/comm_monitor.cc @@ -49,7 +49,7 @@ #include "sim/stats.hh" CommMonitor::CommMonitor(Params* params) - : MemObject(params), + : SimObject(params), masterPort(name() + "-master", *this), slavePort(name() + "-slave", *this), samplePeriodicEvent([this]{ samplePeriodic(); }, name()), @@ -91,7 +91,7 @@ CommMonitor::getPort(const std::string &if_name, PortID idx) } else if (if_name == "slave") { return slavePort; } else { - return MemObject::getPort(if_name, idx); + return SimObject::getPort(if_name, idx); } } @@ -381,7 +381,7 @@ CommMonitor::recvRangeChange() void CommMonitor::regStats() { - MemObject::regStats(); + SimObject::regStats(); // Initialise all the monitor stats using namespace Stats; diff --git a/src/mem/comm_monitor.hh b/src/mem/comm_monitor.hh index 1eea6a535..350155924 100644 --- a/src/mem/comm_monitor.hh +++ b/src/mem/comm_monitor.hh @@ -46,12 +46,13 @@ #define __MEM_COMM_MONITOR_HH__ #include "base/statistics.hh" -#include "mem/mem_object.hh" +#include "mem/port.hh" #include "params/CommMonitor.hh" #include "sim/probe/mem.hh" +#include "sim/sim_object.hh" /** - * The communication monitor is a MemObject which can monitor statistics of + * The communication monitor is a SimObject which can monitor statistics of * the communication happening between two ports in the memory system. * * Currently the following stats are implemented: Histograms of read/write @@ -61,7 +62,7 @@ * to capture the number of accesses to an address over time ("heat map"). * All stats can be disabled from Python. */ -class CommMonitor : public MemObject +class CommMonitor : public SimObject { public: // Construction & SimObject interfaces @@ -83,7 +84,7 @@ class CommMonitor : public MemObject void startup() override; void regProbePoints() override; - public: // MemObject interfaces + public: // SimObject interfaces Port &getPort(const std::string &if_name, PortID idx=InvalidPortID) override; diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc index 429e9ef5e..08465aa70 100644 --- a/src/mem/dram_ctrl.cc +++ b/src/mem/dram_ctrl.cc @@ -2849,7 +2849,7 @@ Port & DRAMCtrl::getPort(const string &if_name, PortID idx) { if (if_name != "port") { - return MemObject::getPort(if_name, idx); + return QoS::MemCtrl::getPort(if_name, idx); } else { return port; } diff --git a/src/mem/dramsim2.cc b/src/mem/dramsim2.cc index f0c612120..3f20bb3ec 100644 --- a/src/mem/dramsim2.cc +++ b/src/mem/dramsim2.cc @@ -340,7 +340,7 @@ Port & DRAMSim2::getPort(const std::string &if_name, PortID idx) { if (if_name != "port") { - return MemObject::getPort(if_name, idx); + return AbstractMemory::getPort(if_name, idx); } else { return port; } diff --git a/src/mem/external_master.cc b/src/mem/external_master.cc index 799f85036..d530d9ad0 100644 --- a/src/mem/external_master.cc +++ b/src/mem/external_master.cc @@ -52,7 +52,7 @@ std::map<std::string, ExternalMaster::Handler *> ExternalMaster::portHandlers; ExternalMaster::ExternalMaster(ExternalMasterParams *params) : - MemObject(params), + SimObject(params), externalPort(NULL), portName(params->name + ".port"), portType(params->port_type), @@ -83,7 +83,7 @@ ExternalMaster::getPort(const std::string &if_name, PortID idx) } return *externalPort; } else { - return MemObject::getPort(if_name, idx); + return SimObject::getPort(if_name, idx); } } diff --git a/src/mem/external_master.hh b/src/mem/external_master.hh index f105054b4..debc86269 100644 --- a/src/mem/external_master.hh +++ b/src/mem/external_master.hh @@ -60,10 +60,11 @@ #ifndef __MEM_EXTERNAL_MASTER_HH__ #define __MEM_EXTERNAL_MASTER_HH__ -#include "mem/mem_object.hh" +#include "mem/port.hh" #include "params/ExternalMaster.hh" +#include "sim/sim_object.hh" -class ExternalMaster : public MemObject +class ExternalMaster : public SimObject { public: /** Derive from this class to create an external port interface */ diff --git a/src/mem/external_slave.cc b/src/mem/external_slave.cc index 6266f6649..ae81e1b15 100644 --- a/src/mem/external_slave.cc +++ b/src/mem/external_slave.cc @@ -181,7 +181,7 @@ ExternalSlave::ExternalPort::getAddrRanges() const } ExternalSlave::ExternalSlave(ExternalSlaveParams *params) : - MemObject(params), + SimObject(params), externalPort(NULL), portName(params->name + ".port"), portType(params->port_type), @@ -216,7 +216,7 @@ ExternalSlave::getPort(const std::string &if_name, PortID idx) } return *externalPort; } else { - return MemObject::getPort(if_name, idx); + return SimObject::getPort(if_name, idx); } } diff --git a/src/mem/external_slave.hh b/src/mem/external_slave.hh index cfe89b98a..ab33fc53b 100644 --- a/src/mem/external_slave.hh +++ b/src/mem/external_slave.hh @@ -60,10 +60,11 @@ #ifndef __MEM_EXTERNAL_SLAVE_HH__ #define __MEM_EXTERNAL_SLAVE_HH__ -#include "mem/mem_object.hh" +#include "mem/port.hh" #include "params/ExternalSlave.hh" +#include "sim/sim_object.hh" -class ExternalSlave : public MemObject +class ExternalSlave : public SimObject { public: /** Derive from this class to create an external port interface */ diff --git a/src/mem/mem_checker_monitor.cc b/src/mem/mem_checker_monitor.cc index 8364b9198..6879f951b 100644 --- a/src/mem/mem_checker_monitor.cc +++ b/src/mem/mem_checker_monitor.cc @@ -49,7 +49,7 @@ #include "debug/MemCheckerMonitor.hh" MemCheckerMonitor::MemCheckerMonitor(Params* params) - : MemObject(params), + : SimObject(params), masterPort(name() + "-master", *this), slavePort(name() + "-slave", *this), warnOnly(params->warn_only), @@ -81,7 +81,7 @@ MemCheckerMonitor::getPort(const std::string &if_name, PortID idx) } else if (if_name == "slave" || if_name == "cpu_side") { return slavePort; } else { - return MemObject::getPort(if_name, idx); + return SimObject::getPort(if_name, idx); } } diff --git a/src/mem/mem_checker_monitor.hh b/src/mem/mem_checker_monitor.hh index ba150493f..09465a236 100644 --- a/src/mem/mem_checker_monitor.hh +++ b/src/mem/mem_checker_monitor.hh @@ -44,14 +44,14 @@ #include "base/statistics.hh" #include "mem/mem_checker.hh" -#include "mem/mem_object.hh" #include "params/MemCheckerMonitor.hh" +#include "sim/sim_object.hh" #include "sim/system.hh" /** * Implements a MemChecker monitor, to be inserted between two ports. */ -class MemCheckerMonitor : public MemObject +class MemCheckerMonitor : public SimObject { public: diff --git a/src/mem/mem_delay.cc b/src/mem/mem_delay.cc index 67a9664f8..f1a0f2151 100644 --- a/src/mem/mem_delay.cc +++ b/src/mem/mem_delay.cc @@ -43,7 +43,7 @@ #include "params/SimpleMemDelay.hh" MemDelay::MemDelay(const MemDelayParams *p) - : MemObject(p), + : ClockedObject(p), masterPort(name() + "-master", *this), slavePort(name() + "-slave", *this), reqQueue(*this, masterPort), @@ -68,7 +68,7 @@ MemDelay::getPort(const std::string &if_name, PortID idx) } else if (if_name == "slave") { return slavePort; } else { - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } } diff --git a/src/mem/mem_delay.hh b/src/mem/mem_delay.hh index 789d965c8..894ddc02d 100644 --- a/src/mem/mem_delay.hh +++ b/src/mem/mem_delay.hh @@ -40,8 +40,8 @@ #ifndef __MEM_MEM_DELAY_HH__ #define __MEM_MEM_DELAY_HH__ -#include "mem/mem_object.hh" #include "mem/qport.hh" +#include "sim/clocked_object.hh" struct MemDelayParams; struct SimpleMemDelayParams; @@ -61,7 +61,7 @@ struct SimpleMemDelayParams; * * NOTE: Packets may be reordered if the delays aren't constant. */ -class MemDelay : public MemObject +class MemDelay : public ClockedObject { public: diff --git a/src/mem/mport.hh b/src/mem/mport.hh index 72d0b0962..6655b1143 100644 --- a/src/mem/mport.hh +++ b/src/mem/mport.hh @@ -43,8 +43,8 @@ #ifndef __MEM_MPORT_HH__ #define __MEM_MPORT_HH__ -#include "mem/mem_object.hh" #include "mem/tport.hh" +#include "sim/sim_object.hh" /* * This file defines a port class which is used for sending and receiving @@ -57,7 +57,7 @@ class MessageSlavePort : public SimpleTimingPort { public: - MessageSlavePort(const std::string &name, MemObject *owner) : + MessageSlavePort(const std::string &name, SimObject *owner) : SimpleTimingPort(name, owner) {} @@ -75,7 +75,7 @@ class MessageMasterPort : public QueuedMasterPort { public: - MessageMasterPort(const std::string &name, MemObject *owner) : + MessageMasterPort(const std::string &name, SimObject *owner) : QueuedMasterPort(name, owner, reqQueue, snoopRespQueue), reqQueue(*owner, *this), snoopRespQueue(*owner, *this) {} diff --git a/src/mem/packet.hh b/src/mem/packet.hh index f942e8ddd..93b3ad5de 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -387,16 +387,16 @@ class Packet : public Printable /** * A virtual base opaque structure used to hold state associated - * with the packet (e.g., an MSHR), specific to a MemObject that + * with the packet (e.g., an MSHR), specific to a SimObject that * sees the packet. A pointer to this state is returned in the - * packet's response so that the MemObject in question can quickly + * packet's response so that the SimObject in question can quickly * look up the state needed to process it. A specific subclass * would be derived from this to carry state specific to a * particular sending device. * - * As multiple MemObjects may add their SenderState throughout the + * As multiple SimObjects may add their SenderState throughout the * memory system, the SenderStates create a stack, where a - * MemObject can add a new Senderstate, as long as the + * SimObject can add a new Senderstate, as long as the * predecessing SenderState is restored when the response comes * back. For this reason, the predecessor should always be * populated with the current SenderState of a packet before diff --git a/src/mem/port.cc b/src/mem/port.cc index 933e98243..ee312eac7 100644 --- a/src/mem/port.cc +++ b/src/mem/port.cc @@ -49,7 +49,7 @@ #include "mem/port.hh" #include "base/trace.hh" -#include "mem/mem_object.hh" +#include "sim/sim_object.hh" BaseMasterPort::BaseMasterPort(const std::string &name, PortID _id) : Port(name, _id), _baseSlavePort(NULL) @@ -92,7 +92,7 @@ BaseSlavePort::getMasterPort() const /** * Master port */ -MasterPort::MasterPort(const std::string& name, MemObject* _owner, PortID _id) +MasterPort::MasterPort(const std::string& name, SimObject* _owner, PortID _id) : BaseMasterPort(name, _id), _slavePort(NULL), owner(*_owner) { } @@ -201,7 +201,7 @@ MasterPort::printAddr(Addr a) /** * Slave port */ -SlavePort::SlavePort(const std::string& name, MemObject* _owner, PortID id) +SlavePort::SlavePort(const std::string& name, SimObject* _owner, PortID id) : BaseSlavePort(name, id), _masterPort(NULL), defaultBackdoorWarned(false), owner(*_owner) { diff --git a/src/mem/port.hh b/src/mem/port.hh index 72a02711c..76ad3bd63 100644 --- a/src/mem/port.hh +++ b/src/mem/port.hh @@ -55,7 +55,7 @@ #include "mem/packet.hh" #include "sim/port.hh" -class MemObject; +class SimObject; /** Forward declaration */ class BaseSlavePort; @@ -123,11 +123,11 @@ class MasterPort : public BaseMasterPort protected: - MemObject& owner; + SimObject& owner; public: - MasterPort(const std::string& name, MemObject* _owner, + MasterPort(const std::string& name, SimObject* _owner, PortID id=InvalidPortID); virtual ~MasterPort(); @@ -317,11 +317,11 @@ class SlavePort : public BaseSlavePort protected: - MemObject& owner; + SimObject& owner; public: - SlavePort(const std::string& name, MemObject* _owner, + SlavePort(const std::string& name, SimObject* _owner, PortID id=InvalidPortID); virtual ~SlavePort(); diff --git a/src/mem/qos/mem_sink.cc b/src/mem/qos/mem_sink.cc index 3ff2339d5..1f104e432 100644 --- a/src/mem/qos/mem_sink.cc +++ b/src/mem/qos/mem_sink.cc @@ -110,7 +110,7 @@ Port & MemSinkCtrl::getPort(const std::string &interface, PortID idx) { if (interface != "port") { - return MemObject::getPort(interface, idx); + return MemCtrl::getPort(interface, idx); } else { return port; } diff --git a/src/mem/qport.hh b/src/mem/qport.hh index 77d8dfafa..6d9655f41 100644 --- a/src/mem/qport.hh +++ b/src/mem/qport.hh @@ -47,6 +47,7 @@ #include "mem/packet_queue.hh" #include "mem/port.hh" +#include "sim/sim_object.hh" /** * A queued port is a port that has an infinite queue for outgoing @@ -75,7 +76,7 @@ class QueuedSlavePort : public SlavePort * behaviuor in a subclass, and provide the latter to the * QueuePort constructor. */ - QueuedSlavePort(const std::string& name, MemObject* owner, + QueuedSlavePort(const std::string& name, SimObject* owner, RespPacketQueue &resp_queue, PortID id = InvalidPortID) : SlavePort(name, owner, id), respQueue(resp_queue) { } @@ -128,7 +129,7 @@ class QueuedMasterPort : public MasterPort * behaviuor in a subclass, and provide the latter to the * QueuePort constructor. */ - QueuedMasterPort(const std::string& name, MemObject* owner, + QueuedMasterPort(const std::string& name, SimObject* owner, ReqPacketQueue &req_queue, SnoopRespPacketQueue &snoop_resp_queue, PortID id = InvalidPortID) : diff --git a/src/mem/ruby/network/dummy_port.hh b/src/mem/ruby/network/dummy_port.hh index ca1ef4155..2d675aa60 100644 --- a/src/mem/ruby/network/dummy_port.hh +++ b/src/mem/ruby/network/dummy_port.hh @@ -43,7 +43,7 @@ class RubyDummyPort : public Port // No need to connect anything here currently. MessageBuffer // port connections only serve to print the connections in // the config output. - // TODO: Add real ports to MessageBuffers and use MemObject connect + // TODO: Add real ports to MessageBuffers and use SimObject connect // code below to bind MessageBuffer senders and receivers } void unbind() override {} diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc index fa1c936b7..68edcba59 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -49,7 +49,7 @@ #include "sim/system.hh" AbstractController::AbstractController(const Params *p) - : MemObject(p), Consumer(this), m_version(p->version), + : ClockedObject(p), Consumer(this), m_version(p->version), m_clusterID(p->cluster_id), m_masterId(p->system->getMasterId(this)), m_is_blocking(false), m_number_of_TBEs(p->number_of_TBEs), @@ -90,7 +90,7 @@ AbstractController::resetStats() void AbstractController::regStats() { - MemObject::regStats(); + ClockedObject::regStats(); m_fully_busy_cycles .name(name() + ".fully_busy_cycles") diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index 5e39a28d2..4d0654698 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -47,7 +47,6 @@ #include "base/addr_range.hh" #include "base/callback.hh" -#include "mem/mem_object.hh" #include "mem/packet.hh" #include "mem/protocol/AccessPermission.hh" #include "mem/qport.hh" @@ -59,6 +58,7 @@ #include "mem/ruby/network/MessageBuffer.hh" #include "mem/ruby/system/CacheRecorder.hh" #include "params/RubyController.hh" +#include "sim/clocked_object.hh" class Network; class GPUCoalescer; @@ -70,7 +70,7 @@ class RejectException: public std::exception { return "Port rejected message based on type"; } }; -class AbstractController : public MemObject, public Consumer +class AbstractController : public ClockedObject, public Consumer { public: typedef RubyControllerParams Params; diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py index 0eb704916..4d3c1900e 100644 --- a/src/mem/ruby/slicc_interface/Controller.py +++ b/src/mem/ruby/slicc_interface/Controller.py @@ -41,9 +41,9 @@ from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class RubyController(MemObject): +class RubyController(ClockedObject): type = 'RubyController' cxx_class = 'AbstractController' cxx_header = "mem/ruby/slicc_interface/AbstractController.hh" diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index 795b473c7..ff3bbe8f0 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -52,7 +52,7 @@ #include "sim/system.hh" RubyPort::RubyPort(const Params *p) - : MemObject(p), m_ruby_system(p->ruby_system), m_version(p->version), + : ClockedObject(p), m_ruby_system(p->ruby_system), m_version(p->version), m_controller(NULL), m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester), system(p->system), pioMasterPort(csprintf("%s.pio-master-port", name()), this), @@ -117,7 +117,7 @@ RubyPort::getPort(const std::string &if_name, PortID idx) } // pass it along to our super class - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } RubyPort::PioMasterPort::PioMasterPort(const std::string &_name, diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index 922b3a973..20bc03a07 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -49,13 +49,13 @@ #include "mem/ruby/common/MachineID.hh" #include "mem/ruby/network/MessageBuffer.hh" #include "mem/ruby/system/RubySystem.hh" -#include "mem/mem_object.hh" #include "mem/tport.hh" #include "params/RubyPort.hh" +#include "sim/clocked_object.hh" class AbstractController; -class RubyPort : public MemObject +class RubyPort : public ClockedObject { public: class MemMasterPort : public QueuedMasterPort diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index 35460438c..2aede349d 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -29,9 +29,9 @@ from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class RubyPort(MemObject): +class RubyPort(ClockedObject): type = 'RubyPort' abstract = True cxx_header = "mem/ruby/system/RubyPort.hh" diff --git a/src/mem/ruby/system/WeightedLRUReplacementPolicy.py b/src/mem/ruby/system/WeightedLRUReplacementPolicy.py index 77ee60554..fa50c95dc 100644 --- a/src/mem/ruby/system/WeightedLRUReplacementPolicy.py +++ b/src/mem/ruby/system/WeightedLRUReplacementPolicy.py @@ -33,7 +33,6 @@ from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject from m5.objects.ReplacementPolicy import ReplacementPolicy class WeightedLRUReplacementPolicy(ReplacementPolicy): diff --git a/src/mem/serial_link.cc b/src/mem/serial_link.cc index 438fb0e68..b39ac5946 100644 --- a/src/mem/serial_link.cc +++ b/src/mem/serial_link.cc @@ -82,7 +82,7 @@ SerialLink::SerialLinkMasterPort::SerialLinkMasterPort(const std::string& } SerialLink::SerialLink(SerialLinkParams *p) - : MemObject(p), + : ClockedObject(p), slavePort(p->name + ".slave", *this, masterPort, ticksToCycles(p->delay), p->resp_size, p->ranges), masterPort(p->name + ".master", *this, slavePort, @@ -102,7 +102,7 @@ SerialLink::getPort(const std::string &if_name, PortID idx) return slavePort; else // pass it along to our super class - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } void diff --git a/src/mem/serial_link.hh b/src/mem/serial_link.hh index 0bb1692ed..3dac18045 100644 --- a/src/mem/serial_link.hh +++ b/src/mem/serial_link.hh @@ -56,8 +56,9 @@ #include <deque> #include "base/types.hh" -#include "mem/mem_object.hh" +#include "mem/port.hh" #include "params/SerialLink.hh" +#include "sim/clocked_object.hh" /** * SerialLink is a simple variation of the Bridge class, with the ability to @@ -66,7 +67,7 @@ * whole packet to start the serialization. But the deserializer waits for the * complete packet to check its integrity first. */ -class SerialLink : public MemObject +class SerialLink : public ClockedObject { protected: diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc index fcc1cff23..9e7dfc815 100644 --- a/src/mem/simple_mem.cc +++ b/src/mem/simple_mem.cc @@ -245,7 +245,7 @@ Port & SimpleMemory::getPort(const std::string &if_name, PortID idx) { if (if_name != "port") { - return MemObject::getPort(if_name, idx); + return AbstractMemory::getPort(if_name, idx); } else { return port; } diff --git a/src/mem/tport.cc b/src/mem/tport.cc index 9f0f08814..4de495e22 100644 --- a/src/mem/tport.cc +++ b/src/mem/tport.cc @@ -42,11 +42,10 @@ */ #include "mem/tport.hh" - -#include "mem/mem_object.hh" +#include "sim/sim_object.hh" SimpleTimingPort::SimpleTimingPort(const std::string& _name, - MemObject* _owner) : + SimObject* _owner) : QueuedSlavePort(_name, _owner, queueImpl), queueImpl(*_owner, *this) { } diff --git a/src/mem/tport.hh b/src/mem/tport.hh index d7e4bbc74..d62b1405d 100644 --- a/src/mem/tport.hh +++ b/src/mem/tport.hh @@ -52,6 +52,8 @@ #include "mem/qport.hh" +class SimObject; + /** * The simple timing port uses a queued port to implement * recvFunctional and recvTimingReq through recvAtomic. It is always a @@ -99,7 +101,7 @@ class SimpleTimingPort : public QueuedSlavePort * @param name port name * @param owner structural owner */ - SimpleTimingPort(const std::string& name, MemObject* owner); + SimpleTimingPort(const std::string& name, SimObject* owner); virtual ~SimpleTimingPort() { } diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc index 9328c2990..de32c0b32 100644 --- a/src/mem/xbar.cc +++ b/src/mem/xbar.cc @@ -56,7 +56,7 @@ #include "debug/XBar.hh" BaseXBar::BaseXBar(const BaseXBarParams *p) - : MemObject(p), + : ClockedObject(p), frontendLatency(p->frontend_latency), forwardLatency(p->forward_latency), responseLatency(p->response_latency), @@ -88,7 +88,7 @@ BaseXBar::getPort(const std::string &if_name, PortID idx) // the slave port index translates directly to the vector position return *slavePorts[idx]; } else { - return MemObject::getPort(if_name, idx); + return ClockedObject::getPort(if_name, idx); } } diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh index b688f309a..8de7af46f 100644 --- a/src/mem/xbar.hh +++ b/src/mem/xbar.hh @@ -56,9 +56,9 @@ #include "base/addr_range_map.hh" #include "base/types.hh" -#include "mem/mem_object.hh" #include "mem/qport.hh" #include "params/BaseXBar.hh" +#include "sim/clocked_object.hh" #include "sim/stats.hh" /** @@ -70,7 +70,7 @@ * The BaseXBar is responsible for the basic flow control (busy or * not), the administration of retries, and the address decoding. */ -class BaseXBar : public MemObject +class BaseXBar : public ClockedObject { protected: diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 0e29980c6..dca7d4095 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -172,10 +172,6 @@ def createCxxConfigDirectoryEntryFile(code, name, simobj, is_header): code('#include "base/str.hh"') code('#include "cxx_config/${name}.hh"') - if simobj._ports: - code('#include "mem/mem_object.hh"') - code('#include "mem/port.hh"') - code() code('${member_prefix}DirectoryEntry::DirectoryEntry()'); code('{') diff --git a/src/sim/System.py b/src/sim/System.py index c012cb256..9928887b9 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -51,7 +51,7 @@ from m5.objects.SimpleMemory import * class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing', 'atomic_noncaching'] -class System(MemObject): +class System(SimObject): type = 'System' cxx_header = "sim/system.hh" system_port = MasterPort("System port") diff --git a/src/sim/cxx_manager.cc b/src/sim/cxx_manager.cc index 35d008d58..2ea3eaf0c 100644 --- a/src/sim/cxx_manager.cc +++ b/src/sim/cxx_manager.cc @@ -45,8 +45,8 @@ #include "base/str.hh" #include "base/trace.hh" #include "debug/CxxConfig.hh" -#include "mem/mem_object.hh" #include "sim/serialize.hh" +#include "sim/sim_object.hh" CxxConfigManager::CxxConfigManager(CxxConfigFileBase &configFile_) : configFile(configFile_), flags(configFile_.getFlags()), @@ -451,29 +451,14 @@ CxxConfigManager::bindPort( SimObject *slave_object, const std::string &slave_port_name, PortID slave_port_index) { - MemObject *master_mem_object = dynamic_cast<MemObject *>(master_object); - MemObject *slave_mem_object = dynamic_cast<MemObject *>(slave_object); - - if (!master_mem_object) { - throw Exception(master_object->name(), csprintf( - "Object isn't a mem object and so can have master port:" - " %s[%d]", master_port_name, master_port_index)); - } - - if (!slave_mem_object) { - throw Exception(slave_object->name(), csprintf( - "Object isn't a mem object and so can have slave port:" - " %s[%d]", slave_port_name, slave_port_index)); - } - /* FIXME, check slave_port_index against connection_count * defined for port, need getPortConnectionCount and a * getCxxConfigDirectoryEntry for each object. */ /* It would be nice to be able to catch the errors from these calls. */ - Port &master_port = master_mem_object->getPort( + Port &master_port = master_object->getPort( master_port_name, master_port_index); - Port &slave_port = slave_mem_object->getPort( + Port &slave_port = slave_object->getPort( slave_port_name, slave_port_index); if (master_port.isConnected()) { diff --git a/src/sim/system.cc b/src/sim/system.cc index 65ad6cdb0..74769654b 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -89,7 +89,7 @@ vector<System *> System::systemList; int System::numSystemsRunning = 0; System::System(Params *p) - : MemObject(p), _systemPort("system_port", this), + : SimObject(p), _systemPort("system_port", this), multiThread(p->multi_thread), pagePtr(0), init_param(p->init_param), @@ -444,7 +444,7 @@ System::unserialize(CheckpointIn &cp) void System::regStats() { - MemObject::regStats(); + SimObject::regStats(); for (uint32_t j = 0; j < numWorkIds ; j++) { workItemStats[j] = new Stats::Histogram(); diff --git a/src/sim/system.hh b/src/sim/system.hh index 6227ae660..d7a3b2008 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -58,7 +58,6 @@ #include "config/the_isa.hh" #include "enums/MemoryMode.hh" #include "mem/mem_master.hh" -#include "mem/mem_object.hh" #include "mem/physical.hh" #include "mem/port.hh" #include "mem/port_proxy.hh" @@ -66,6 +65,7 @@ #include "sim/futex_map.hh" #include "sim/redirect_path.hh" #include "sim/se_signal.hh" +#include "sim/sim_object.hh" /** * To avoid linking errors with LTO, only include the header if we @@ -81,7 +81,7 @@ class KvmVM; class ObjectFile; class ThreadContext; -class System : public MemObject +class System : public SimObject { private: @@ -97,7 +97,7 @@ class System : public MemObject /** * Create a system port with a name and an owner. */ - SystemPort(const std::string &_name, MemObject *_owner) + SystemPort(const std::string &_name, SimObject *_owner) : MasterPort(_name, _owner) { } bool recvTimingResp(PacketPtr pkt) override |