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-rw-r--r--SConstruct3
-rw-r--r--cpu/activity.cc122
-rw-r--r--cpu/activity.hh67
-rw-r--r--cpu/checker/cpu.cc757
-rw-r--r--cpu/checker/cpu.hh326
-rw-r--r--cpu/checker/cpu_builder.cc126
-rw-r--r--cpu/checker/exec_context.hh259
-rw-r--r--cpu/checker/o3_cpu_builder.cc126
-rw-r--r--cpu/o3/dep_graph.hh213
-rw-r--r--cpu/o3/fu_pool.cc295
-rw-r--r--cpu/o3/fu_pool.hh162
-rw-r--r--cpu/o3/lsq.cc36
-rw-r--r--cpu/o3/lsq.hh324
-rw-r--r--cpu/o3/lsq_impl.hh538
-rw-r--r--cpu/o3/lsq_unit.cc36
-rw-r--r--cpu/o3/lsq_unit.hh632
-rw-r--r--cpu/o3/lsq_unit_impl.hh873
-rw-r--r--cpu/o3/scoreboard.cc106
-rw-r--r--cpu/o3/scoreboard.hh114
-rw-r--r--cpu/o3/thread_state.hh120
-rw-r--r--cpu/ozone/back_end.cc5
-rw-r--r--cpu/ozone/back_end.hh516
-rw-r--r--cpu/ozone/back_end_impl.hh1904
-rw-r--r--cpu/ozone/cpu_builder.cc830
-rw-r--r--cpu/ozone/dyn_inst.cc35
-rw-r--r--cpu/ozone/dyn_inst.hh231
-rw-r--r--cpu/ozone/dyn_inst_impl.hh315
-rw-r--r--cpu/ozone/front_end.cc7
-rw-r--r--cpu/ozone/front_end.hh284
-rw-r--r--cpu/ozone/front_end_impl.hh920
-rw-r--r--cpu/ozone/inorder_back_end.cc5
-rw-r--r--cpu/ozone/inorder_back_end.hh450
-rw-r--r--cpu/ozone/inorder_back_end_impl.hh519
-rw-r--r--cpu/ozone/inst_queue.cc36
-rw-r--r--cpu/ozone/inst_queue.hh506
-rw-r--r--cpu/ozone/inst_queue_impl.hh1341
-rw-r--r--cpu/ozone/lsq_unit.cc34
-rw-r--r--cpu/ozone/lsq_unit.hh637
-rw-r--r--cpu/ozone/lsq_unit_impl.hh846
-rw-r--r--cpu/ozone/lw_back_end.cc5
-rw-r--r--cpu/ozone/lw_back_end.hh473
-rw-r--r--cpu/ozone/lw_back_end_impl.hh1693
-rw-r--r--cpu/ozone/lw_lsq.cc34
-rw-r--r--cpu/ozone/lw_lsq.hh657
-rw-r--r--cpu/ozone/lw_lsq_impl.hh874
-rw-r--r--cpu/ozone/null_predictor.hh76
-rw-r--r--cpu/ozone/ozone_impl.hh75
-rw-r--r--cpu/ozone/rename_table.cc7
-rw-r--r--cpu/ozone/rename_table.hh53
-rw-r--r--cpu/ozone/rename_table_impl.hh23
-rw-r--r--cpu/ozone/simple_impl.hh69
-rw-r--r--cpu/ozone/simple_params.hh165
-rw-r--r--cpu/ozone/thread_state.hh194
-rw-r--r--cpu/quiesce_event.cc20
-rw-r--r--cpu/quiesce_event.hh23
-rw-r--r--cpu/thread_state.hh129
-rw-r--r--python/m5/objects/FUPool.py8
-rw-r--r--python/m5/objects/OzoneCPU.py89
-rw-r--r--python/m5/objects/SimpleOzoneCPU.py86
-rw-r--r--src/SConscript2
-rw-r--r--src/arch/alpha/ev5.cc23
-rw-r--r--src/arch/alpha/isa/decoder.isa30
-rw-r--r--src/arch/alpha/isa/pal.isa6
-rw-r--r--src/base/traceflags.py47
-rw-r--r--src/cpu/SConscript40
-rw-r--r--src/cpu/base.cc25
-rw-r--r--src/cpu/base.hh9
-rw-r--r--src/cpu/base_dyn_inst.cc168
-rw-r--r--src/cpu/base_dyn_inst.hh386
-rw-r--r--src/cpu/cpu_exec_context.cc64
-rw-r--r--src/cpu/cpu_exec_context.hh28
-rw-r--r--src/cpu/cpu_models.py9
-rw-r--r--src/cpu/exec_context.hh53
-rw-r--r--src/cpu/exetrace.cc6
-rw-r--r--src/cpu/exetrace.hh1
-rw-r--r--src/cpu/inst_seq.hh2
-rw-r--r--src/cpu/o3/2bit_local_pred.cc31
-rw-r--r--src/cpu/o3/2bit_local_pred.hh25
-rw-r--r--src/cpu/o3/alpha_cpu.hh331
-rw-r--r--src/cpu/o3/alpha_cpu_builder.cc297
-rw-r--r--src/cpu/o3/alpha_cpu_impl.hh742
-rw-r--r--src/cpu/o3/alpha_dyn_inst.hh82
-rw-r--r--src/cpu/o3/alpha_dyn_inst_impl.hh102
-rw-r--r--src/cpu/o3/alpha_impl.hh17
-rw-r--r--src/cpu/o3/alpha_params.hh66
-rw-r--r--src/cpu/o3/bpred_unit.cc6
-rw-r--r--src/cpu/o3/bpred_unit.hh161
-rw-r--r--src/cpu/o3/bpred_unit_impl.hh202
-rw-r--r--src/cpu/o3/btb.cc34
-rw-r--r--src/cpu/o3/btb.hh65
-rw-r--r--src/cpu/o3/comm.hh98
-rw-r--r--src/cpu/o3/commit.cc2
-rw-r--r--src/cpu/o3/commit.hh320
-rw-r--r--src/cpu/o3/commit_impl.hh1247
-rw-r--r--src/cpu/o3/cpu.cc994
-rw-r--r--src/cpu/o3/cpu.hh374
-rw-r--r--src/cpu/o3/cpu_policy.hh33
-rw-r--r--src/cpu/o3/decode.cc2
-rw-r--r--src/cpu/o3/decode.hh175
-rw-r--r--src/cpu/o3/decode_impl.hh710
-rw-r--r--src/cpu/o3/fetch.cc2
-rw-r--r--src/cpu/o3/fetch.hh254
-rw-r--r--src/cpu/o3/fetch_impl.hh1142
-rw-r--r--src/cpu/o3/free_list.cc36
-rw-r--r--src/cpu/o3/free_list.hh82
-rw-r--r--src/cpu/o3/iew.cc2
-rw-r--r--src/cpu/o3/iew.hh362
-rw-r--r--src/cpu/o3/iew_impl.hh1592
-rw-r--r--src/cpu/o3/inst_queue.cc4
-rw-r--r--src/cpu/o3/inst_queue.hh429
-rw-r--r--src/cpu/o3/inst_queue_impl.hh1471
-rw-r--r--src/cpu/o3/mem_dep_unit.cc10
-rw-r--r--src/cpu/o3/mem_dep_unit.hh227
-rw-r--r--src/cpu/o3/mem_dep_unit_impl.hh550
-rw-r--r--src/cpu/o3/ras.cc23
-rw-r--r--src/cpu/o3/ras.hh37
-rw-r--r--src/cpu/o3/regfile.hh116
-rw-r--r--src/cpu/o3/rename.cc2
-rw-r--r--src/cpu/o3/rename.hh355
-rw-r--r--src/cpu/o3/rename_impl.hh1437
-rw-r--r--src/cpu/o3/rename_map.cc279
-rw-r--r--src/cpu/o3/rename_map.hh64
-rw-r--r--src/cpu/o3/rob.hh232
-rw-r--r--src/cpu/o3/rob_impl.hh621
-rw-r--r--src/cpu/o3/sat_counter.cc26
-rw-r--r--src/cpu/o3/sat_counter.hh49
-rw-r--r--src/cpu/o3/store_set.cc154
-rw-r--r--src/cpu/o3/store_set.hh47
-rw-r--r--src/cpu/o3/tournament_pred.cc47
-rw-r--r--src/cpu/o3/tournament_pred.hh33
-rw-r--r--src/cpu/ozone/cpu.cc9
-rw-r--r--src/cpu/ozone/cpu.hh713
-rw-r--r--src/cpu/ozone/cpu_impl.hh1029
-rw-r--r--src/cpu/static_inst.hh15
-rw-r--r--src/kern/system_events.cc11
-rw-r--r--src/kern/tru64/tru64.hh2
-rw-r--r--src/python/m5/objects/AlphaFullCPU.py39
-rw-r--r--src/sim/pseudo_inst.cc20
138 files changed, 32812 insertions, 5135 deletions
diff --git a/SConstruct b/SConstruct
index 63858dc2b..6a05b2339 100644
--- a/SConstruct
+++ b/SConstruct
@@ -239,7 +239,8 @@ env['ALL_ISA_LIST'] = ['alpha', 'sparc', 'mips']
# Define the universe of supported CPU models
env['ALL_CPU_LIST'] = ['AtomicSimpleCPU', 'TimingSimpleCPU',
- 'FullCPU', 'AlphaFullCPU']
+ 'FullCPU', 'AlphaFullCPU',
+ 'OzoneSimpleCPU', 'OzoneCPU', 'CheckerCPU']
# Sticky options get saved in the options file so they persist from
# one invocation to the next (unless overridden, in which case the new
diff --git a/cpu/activity.cc b/cpu/activity.cc
new file mode 100644
index 000000000..6dcb6e341
--- /dev/null
+++ b/cpu/activity.cc
@@ -0,0 +1,122 @@
+
+#include "base/timebuf.hh"
+#include "cpu/activity.hh"
+
+ActivityRecorder::ActivityRecorder(int num_stages, int longest_latency,
+ int activity)
+ : activityBuffer(longest_latency, 0), longestLatency(longest_latency),
+ activityCount(activity), numStages(num_stages)
+{
+ stageActive = new bool[numStages];
+ memset(stageActive, 0, numStages);
+}
+
+void
+ActivityRecorder::activity()
+{
+ if (activityBuffer[0]) {
+ return;
+ }
+
+ activityBuffer[0] = true;
+
+ ++activityCount;
+
+ DPRINTF(Activity, "Activity: %i\n", activityCount);
+}
+
+void
+ActivityRecorder::advance()
+{
+ if (activityBuffer[-longestLatency]) {
+ --activityCount;
+
+ assert(activityCount >= 0);
+
+ DPRINTF(Activity, "Activity: %i\n", activityCount);
+
+ if (activityCount == 0) {
+ DPRINTF(Activity, "No activity left!\n");
+ }
+ }
+
+ activityBuffer.advance();
+}
+
+void
+ActivityRecorder::activateStage(const int idx)
+{
+ if (!stageActive[idx]) {
+ ++activityCount;
+
+ stageActive[idx] = true;
+
+ DPRINTF(Activity, "Activity: %i\n", activityCount);
+ } else {
+ DPRINTF(Activity, "Stage %i already active.\n", idx);
+ }
+
+// assert(activityCount < longestLatency + numStages + 1);
+}
+
+void
+ActivityRecorder::deactivateStage(const int idx)
+{
+ if (stageActive[idx]) {
+ --activityCount;
+
+ stageActive[idx] = false;
+
+ DPRINTF(Activity, "Activity: %i\n", activityCount);
+ } else {
+ DPRINTF(Activity, "Stage %i already inactive.\n", idx);
+ }
+
+ assert(activityCount >= 0);
+}
+
+void
+ActivityRecorder::reset()
+{
+ activityCount = 0;
+ memset(stageActive, 0, numStages);
+ for (int i = 0; i < longestLatency + 1; ++i)
+ activityBuffer.advance();
+}
+
+void
+ActivityRecorder::dump()
+{
+ for (int i = 0; i <= longestLatency; ++i) {
+ cprintf("[Idx:%i %i] ", i, activityBuffer[-i]);
+ }
+
+ cprintf("\n");
+
+ for (int i = 0; i < numStages; ++i) {
+ cprintf("[Stage:%i %i]\n", i, stageActive[i]);
+ }
+
+ cprintf("\n");
+
+ cprintf("Activity count: %i\n", activityCount);
+}
+
+void
+ActivityRecorder::validate()
+{
+ int count = 0;
+ for (int i = 0; i <= longestLatency; ++i) {
+ if (activityBuffer[-i]) {
+ count++;
+ }
+ }
+
+ for (int i = 0; i < numStages; ++i) {
+ if (stageActive[i]) {
+ count++;
+ }
+ }
+
+ assert(count == activityCount);
+}
diff --git a/cpu/activity.hh b/cpu/activity.hh
new file mode 100644
index 000000000..2d53dc4bb
--- /dev/null
+++ b/cpu/activity.hh
@@ -0,0 +1,67 @@
+
+#ifndef __CPU_ACTIVITY_HH__
+#define __CPU_ACTIVITY_HH__
+
+#include "base/timebuf.hh"
+#include "base/trace.hh"
+
+class ActivityRecorder {
+ public:
+ ActivityRecorder(int num_stages, int longest_latency, int count);
+
+ /** Records that there is activity this cycle. */
+ void activity();
+ /** Advances the activity buffer, decrementing the activityCount if active
+ * communication just left the time buffer, and descheduling the CPU if
+ * there is no activity.
+ */
+ void advance();
+ /** Marks a stage as active. */
+ void activateStage(const int idx);
+ /** Deactivates a stage. */
+ void deactivateStage(const int idx);
+
+ int getActivityCount() { return activityCount; }
+
+ void setActivityCount(int count)
+ { activityCount = count; }
+
+ bool active() { return activityCount; }
+
+ void reset();
+
+ void dump();
+
+ void validate();
+
+ private:
+ /** Time buffer that tracks if any cycles has active communication
+ * in them. It should be as long as the longest communication
+ * latency in the system. Each time any time buffer is written,
+ * the activity buffer should also be written to. The
+ * activityBuffer is advanced along with all the other time
+ * buffers, so it should have a 1 somewhere in it only if there
+ * is active communication in a time buffer.
+ */
+ TimeBuffer<bool> activityBuffer;
+
+ int longestLatency;
+
+ /** Tracks how many stages and cycles of time buffer have
+ * activity. Stages increment this count when they switch to
+ * active, and decrement it when they switch to
+ * inactive. Whenever a cycle that previously had no information
+ * is written in the time buffer, this is incremented. When a
+ * cycle that had information exits the time buffer due to age,
+ * this count is decremented. When the count is 0, there is no
+ * activity in the CPU, and it can be descheduled.
+ */
+ int activityCount;
+
+ int numStages;
+
+ /** Records which stages are active/inactive. */
+ bool *stageActive;
+};
+
+#endif // __CPU_ACTIVITY_HH__
diff --git a/cpu/checker/cpu.cc b/cpu/checker/cpu.cc
new file mode 100644
index 000000000..41ff6e769
--- /dev/null
+++ b/cpu/checker/cpu.cc
@@ -0,0 +1,757 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <list>
+#include <string>
+
+#include "base/refcnt.hh"
+#include "cpu/base.hh"
+#include "cpu/base_dyn_inst.hh"
+#include "cpu/checker/cpu.hh"
+#include "cpu/cpu_exec_context.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+#include "sim/byteswap.hh"
+#include "sim/sim_object.hh"
+#include "sim/stats.hh"
+
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+
+#include "cpu/ozone/dyn_inst.hh"
+#include "cpu/ozone/ozone_impl.hh"
+#include "cpu/ozone/simple_impl.hh"
+
+#if FULL_SYSTEM
+#include "sim/system.hh"
+#include "arch/vtophys.hh"
+#endif // FULL_SYSTEM
+
+using namespace std;
+//The CheckerCPU does alpha only
+using namespace AlphaISA;
+
+void
+CheckerCPU::init()
+{
+}
+
+CheckerCPU::CheckerCPU(Params *p)
+ : BaseCPU(p), cpuXC(NULL), xcProxy(NULL)
+{
+ memReq = new MemReq();
+ memReq->xc = xcProxy;
+ memReq->asid = 0;
+ memReq->data = new uint8_t[64];
+
+ numInst = 0;
+ startNumInst = 0;
+ numLoad = 0;
+ startNumLoad = 0;
+ youngestSN = 0;
+
+ changedPC = willChangePC = changedNextPC = false;
+
+ exitOnError = p->exitOnError;
+#if FULL_SYSTEM
+ itb = p->itb;
+ dtb = p->dtb;
+ systemPtr = NULL;
+ memPtr = NULL;
+#endif
+}
+
+CheckerCPU::~CheckerCPU()
+{
+}
+
+void
+CheckerCPU::setMemory(FunctionalMemory *mem)
+{
+ memPtr = mem;
+#if !FULL_SYSTEM
+ cpuXC = new CPUExecContext(this, /* thread_num */ 0, mem,
+ /* asid */ 0);
+
+ cpuXC->setStatus(ExecContext::Suspended);
+ xcProxy = cpuXC->getProxy();
+ execContexts.push_back(xcProxy);
+#else
+ if (systemPtr) {
+ cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false);
+
+ cpuXC->setStatus(ExecContext::Suspended);
+ xcProxy = cpuXC->getProxy();
+ execContexts.push_back(xcProxy);
+ memReq->xc = xcProxy;
+ delete cpuXC->kernelStats;
+ cpuXC->kernelStats = NULL;
+ }
+#endif
+}
+
+#if FULL_SYSTEM
+void
+CheckerCPU::setSystem(System *system)
+{
+ systemPtr = system;
+
+ if (memPtr) {
+ cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false);
+
+ cpuXC->setStatus(ExecContext::Suspended);
+ xcProxy = cpuXC->getProxy();
+ execContexts.push_back(xcProxy);
+ memReq->xc = xcProxy;
+ delete cpuXC->kernelStats;
+ cpuXC->kernelStats = NULL;
+ }
+}
+#endif
+
+void
+CheckerCPU::serialize(ostream &os)
+{
+/*
+ BaseCPU::serialize(os);
+ SERIALIZE_SCALAR(inst);
+ nameOut(os, csprintf("%s.xc", name()));
+ cpuXC->serialize(os);
+ cacheCompletionEvent.serialize(os);
+*/
+}
+
+void
+CheckerCPU::unserialize(Checkpoint *cp, const string &section)
+{
+/*
+ BaseCPU::unserialize(cp, section);
+ UNSERIALIZE_SCALAR(inst);
+ cpuXC->unserialize(cp, csprintf("%s.xc", section));
+*/
+}
+
+Fault
+CheckerCPU::copySrcTranslate(Addr src)
+{
+ panic("Unimplemented!");
+}
+
+Fault
+CheckerCPU::copy(Addr dest)
+{
+ panic("Unimplemented!");
+}
+
+template <class T>
+Fault
+CheckerCPU::read(Addr addr, T &data, unsigned flags)
+{
+ memReq->reset(addr, sizeof(T), flags);
+
+ // translate to physical address
+ translateDataReadReq(memReq);
+
+ memReq->cmd = Read;
+ memReq->completionEvent = NULL;
+ memReq->time = curTick;
+ memReq->flags &= ~INST_READ;
+
+ if (!(memReq->flags & UNCACHEABLE)) {
+ // Access memory to see if we have the same data
+ cpuXC->read(memReq, data);
+ } else {
+ // Assume the data is correct if it's an uncached access
+ memcpy(&data, &unverifiedResult.integer, sizeof(T));
+ }
+
+ return NoFault;
+}
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+
+template
+Fault
+CheckerCPU::read(Addr addr, uint64_t &data, unsigned flags);
+
+template
+Fault
+CheckerCPU::read(Addr addr, uint32_t &data, unsigned flags);
+
+template
+Fault
+CheckerCPU::read(Addr addr, uint16_t &data, unsigned flags);
+
+template
+Fault
+CheckerCPU::read(Addr addr, uint8_t &data, unsigned flags);
+
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+template<>
+Fault
+CheckerCPU::read(Addr addr, double &data, unsigned flags)
+{
+ return read(addr, *(uint64_t*)&data, flags);
+}
+
+template<>
+Fault
+CheckerCPU::read(Addr addr, float &data, unsigned flags)
+{
+ return read(addr, *(uint32_t*)&data, flags);
+}
+
+template<>
+Fault
+CheckerCPU::read(Addr addr, int32_t &data, unsigned flags)
+{
+ return read(addr, (uint32_t&)data, flags);
+}
+
+template <class T>
+Fault
+CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
+{
+ memReq->reset(addr, sizeof(T), flags);
+
+ // translate to physical address
+ cpuXC->translateDataWriteReq(memReq);
+
+ // Can compare the write data and result only if it's cacheable,
+ // not a store conditional, or is a store conditional that
+ // succeeded.
+ // @todo: Verify that actual memory matches up with these values.
+ // Right now it only verifies that the instruction data is the
+ // same as what was in the request that got sent to memory; there
+ // is no verification that it is the same as what is in memory.
+ // This is because the LSQ would have to be snooped in the CPU to
+ // verify this data.
+ if (unverifiedReq &&
+ !(unverifiedReq->flags & UNCACHEABLE) &&
+ (!(unverifiedReq->flags & LOCKED) ||
+ ((unverifiedReq->flags & LOCKED) &&
+ unverifiedReq->result == 1))) {
+#if 0
+ memReq->cmd = Read;
+ memReq->completionEvent = NULL;
+ memReq->time = curTick;
+ memReq->flags &= ~INST_READ;
+ cpuXC->read(memReq, inst_data);
+#endif
+ T inst_data;
+ memcpy(&inst_data, unverifiedReq->data, sizeof(T));
+
+ if (data != inst_data) {
+ warn("%lli: Store value does not match value in memory! "
+ "Instruction: %#x, memory: %#x",
+ curTick, inst_data, data);
+ handleError();
+ }
+ }
+
+ // Assume the result was the same as the one passed in. This checker
+ // doesn't check if the SC should succeed or fail, it just checks the
+ // value.
+ if (res)
+ *res = unverifiedReq->result;
+
+ return NoFault;
+}
+
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+template
+Fault
+CheckerCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
+
+template
+Fault
+CheckerCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
+
+template
+Fault
+CheckerCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
+
+template
+Fault
+CheckerCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
+
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+template<>
+Fault
+CheckerCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
+{
+ return write(*(uint64_t*)&data, addr, flags, res);
+}
+
+template<>
+Fault
+CheckerCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
+{
+ return write(*(uint32_t*)&data, addr, flags, res);
+}
+
+template<>
+Fault
+CheckerCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
+{
+ return write((uint32_t)data, addr, flags, res);
+}
+
+
+#if FULL_SYSTEM
+Addr
+CheckerCPU::dbg_vtophys(Addr addr)
+{
+ return vtophys(xcProxy, addr);
+}
+#endif // FULL_SYSTEM
+
+bool
+CheckerCPU::translateInstReq(MemReqPtr &req)
+{
+#if FULL_SYSTEM
+ return (cpuXC->translateInstReq(req) == NoFault);
+#else
+ cpuXC->translateInstReq(req);
+ return true;
+#endif
+}
+
+void
+CheckerCPU::translateDataReadReq(MemReqPtr &req)
+{
+ cpuXC->translateDataReadReq(req);
+
+ if (req->vaddr != unverifiedReq->vaddr) {
+ warn("%lli: Request virtual addresses do not match! Inst: %#x, "
+ "checker: %#x",
+ curTick, unverifiedReq->vaddr, req->vaddr);
+ handleError();
+ }
+ req->paddr = unverifiedReq->paddr;
+
+ if (checkFlags(req)) {
+ warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
+ curTick, unverifiedReq->flags, req->flags);
+ handleError();
+ }
+}
+
+void
+CheckerCPU::translateDataWriteReq(MemReqPtr &req)
+{
+ cpuXC->translateDataWriteReq(req);
+
+ if (req->vaddr != unverifiedReq->vaddr) {
+ warn("%lli: Request virtual addresses do not match! Inst: %#x, "
+ "checker: %#x",
+ curTick, unverifiedReq->vaddr, req->vaddr);
+ handleError();
+ }
+ req->paddr = unverifiedReq->paddr;
+
+ if (checkFlags(req)) {
+ warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
+ curTick, unverifiedReq->flags, req->flags);
+ handleError();
+ }
+}
+
+bool
+CheckerCPU::checkFlags(MemReqPtr &req)
+{
+ // Remove any dynamic flags that don't have to do with the request itself.
+ unsigned flags = unverifiedReq->flags;
+ unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE | NO_FAULT;
+ flags = flags & (mask);
+ if (flags == req->flags) {
+ return false;
+ } else {
+ return true;
+ }
+}
+
+template <class DynInstPtr>
+void
+Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
+{
+ DynInstPtr inst;
+
+ // Either check this instruction, or add it to a list of
+ // instructions waiting to be checked. Instructions must be
+ // checked in program order, so if a store has committed yet not
+ // completed, there may be some instructions that are waiting
+ // behind it that have completed and must be checked.
+ if (!instList.empty()) {
+ if (youngestSN < completed_inst->seqNum) {
+ DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
+ completed_inst->seqNum, completed_inst->readPC());
+ instList.push_back(completed_inst);
+ youngestSN = completed_inst->seqNum;
+ }
+
+ if (!instList.front()->isCompleted()) {
+ return;
+ } else {
+ inst = instList.front();
+ instList.pop_front();
+ }
+ } else {
+ if (!completed_inst->isCompleted()) {
+ if (youngestSN < completed_inst->seqNum) {
+ DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
+ completed_inst->seqNum, completed_inst->readPC());
+ instList.push_back(completed_inst);
+ youngestSN = completed_inst->seqNum;
+ }
+ return;
+ } else {
+ if (youngestSN < completed_inst->seqNum) {
+ inst = completed_inst;
+ youngestSN = completed_inst->seqNum;
+ } else {
+ return;
+ }
+ }
+ }
+
+ // Try to check all instructions that are completed, ending if we
+ // run out of instructions to check or if an instruction is not
+ // yet completed.
+ while (1) {
+ DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%#x.\n",
+ inst->seqNum, inst->readPC());
+ unverifiedResult.integer = inst->readIntResult();
+ unverifiedReq = inst->req;
+ numCycles++;
+
+ Fault fault = NoFault;
+
+ // maintain $r0 semantics
+ cpuXC->setIntReg(ZeroReg, 0);
+#ifdef TARGET_ALPHA
+ cpuXC->setFloatRegDouble(ZeroReg, 0.0);
+#endif // TARGET_ALPHA
+
+ // Check if any recent PC changes match up with anything we
+ // expect to happen. This is mostly to check if traps or
+ // PC-based events have occurred in both the checker and CPU.
+ if (changedPC) {
+ DPRINTF(Checker, "Changed PC recently to %#x\n",
+ cpuXC->readPC());
+ if (willChangePC) {
+ if (newPC == cpuXC->readPC()) {
+ DPRINTF(Checker, "Changed PC matches expected PC\n");
+ } else {
+ warn("%lli: Changed PC does not match expected PC, "
+ "changed: %#x, expected: %#x",
+ curTick, cpuXC->readPC(), newPC);
+ handleError();
+ }
+ willChangePC = false;
+ }
+ changedPC = false;
+ }
+ if (changedNextPC) {
+ DPRINTF(Checker, "Changed NextPC recently to %#x\n",
+ cpuXC->readNextPC());
+ changedNextPC = false;
+ }
+
+ // Try to fetch the instruction
+
+#if FULL_SYSTEM
+#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
+#else
+#define IFETCH_FLAGS(pc) 0
+#endif
+
+ // set up memory request for instruction fetch
+ memReq->cmd = Read;
+ memReq->reset(cpuXC->readPC() & ~3, sizeof(uint32_t),
+ IFETCH_FLAGS(cpuXC->readPC()));
+
+ bool succeeded = translateInstReq(memReq);
+
+ if (!succeeded) {
+ if (inst->getFault() == NoFault) {
+ // In this case the instruction was not a dummy
+ // instruction carrying an ITB fault. In the single
+ // threaded case the ITB should still be able to
+ // translate this instruction; in the SMT case it's
+ // possible that its ITB entry was kicked out.
+ warn("%lli: Instruction PC %#x was not found in the ITB!",
+ curTick, cpuXC->readPC());
+ handleError();
+
+ // go to the next instruction
+ cpuXC->setPC(cpuXC->readNextPC());
+ cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
+
+ return;
+ } else {
+ // The instruction is carrying an ITB fault. Handle
+ // the fault and see if our results match the CPU on
+ // the next tick().
+ fault = inst->getFault();
+ }
+ }
+
+ if (fault == NoFault) {
+ cpuXC->mem->read(memReq, machInst);
+
+ // keep an instruction count
+ numInst++;
+
+ // decode the instruction
+ machInst = gtoh(machInst);
+ // Checks that the instruction matches what we expected it to be.
+ // Checks both the machine instruction and the PC.
+ validateInst(inst);
+
+ curStaticInst = StaticInst::decode(makeExtMI(machInst,
+ cpuXC->readPC()));
+
+#if FULL_SYSTEM
+ cpuXC->setInst(machInst);
+#endif // FULL_SYSTEM
+
+ fault = inst->getFault();
+ }
+
+ // Either the instruction was a fault and we should process the fault,
+ // or we should just go ahead execute the instruction. This assumes
+ // that the instruction is properly marked as a fault.
+ if (fault == NoFault) {
+
+ cpuXC->func_exe_inst++;
+
+ fault = curStaticInst->execute(this, NULL);
+
+ // Checks to make sure instrution results are correct.
+ validateExecution(inst);
+
+ if (curStaticInst->isLoad()) {
+ ++numLoad;
+ }
+ }
+
+ if (fault != NoFault) {
+#if FULL_SYSTEM
+ fault->invoke(xcProxy);
+ willChangePC = true;
+ newPC = cpuXC->readPC();
+ DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
+#else // !FULL_SYSTEM
+ fatal("fault (%d) detected @ PC 0x%08p", fault, cpuXC->readPC());
+#endif // FULL_SYSTEM
+ } else {
+#if THE_ISA != MIPS_ISA
+ // go to the next instruction
+ cpuXC->setPC(cpuXC->readNextPC());
+ cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
+#else
+ // go to the next instruction
+ cpuXC->setPC(cpuXC->readNextPC());
+ cpuXC->setNextPC(cpuXC->readNextNPC());
+ cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst));
+#endif
+
+ }
+
+#if FULL_SYSTEM
+ // @todo: Determine if these should happen only if the
+ // instruction hasn't faulted. In the SimpleCPU case this may
+ // not be true, but in the O3 or Ozone case this may be true.
+ Addr oldpc;
+ int count = 0;
+ do {
+ oldpc = cpuXC->readPC();
+ system->pcEventQueue.service(xcProxy);
+ count++;
+ } while (oldpc != cpuXC->readPC());
+ if (count > 1) {
+ willChangePC = true;
+ newPC = cpuXC->readPC();
+ DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
+ }
+#endif
+
+ // @todo: Optionally can check all registers. (Or just those
+ // that have been modified).
+ validateState();
+
+ // Continue verifying instructions if there's another completed
+ // instruction waiting to be verified.
+ if (instList.empty()) {
+ break;
+ } else if (instList.front()->isCompleted()) {
+ inst = instList.front();
+ instList.pop_front();
+ } else {
+ break;
+ }
+ }
+}
+
+template <class DynInstPtr>
+void
+Checker<DynInstPtr>::switchOut(Sampler *s)
+{
+ instList.clear();
+}
+
+template <class DynInstPtr>
+void
+Checker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU)
+{
+}
+
+template <class DynInstPtr>
+void
+Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
+{
+ if (inst->readPC() != cpuXC->readPC()) {
+ warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
+ curTick, inst->readPC(), cpuXC->readPC());
+ if (changedPC) {
+ warn("%lli: Changed PCs recently, may not be an error",
+ curTick);
+ } else {
+ handleError();
+ }
+ }
+
+ MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
+
+ if (mi != machInst) {
+ warn("%lli: Binary instructions do not match! Inst: %#x, "
+ "checker: %#x",
+ curTick, mi, machInst);
+ handleError();
+ }
+}
+
+template <class DynInstPtr>
+void
+Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
+{
+ if (inst->numDestRegs()) {
+ // @todo: Support more destination registers.
+ if (inst->isUnverifiable()) {
+ // Unverifiable instructions assume they were executed
+ // properly by the CPU. Grab the result from the
+ // instruction and write it to the register.
+ RegIndex idx = inst->destRegIdx(0);
+ if (idx < TheISA::FP_Base_DepTag) {
+ cpuXC->setIntReg(idx, inst->readIntResult());
+ } else if (idx < TheISA::Fpcr_DepTag) {
+ cpuXC->setFloatRegInt(idx, inst->readIntResult());
+ } else {
+ cpuXC->setMiscReg(idx, inst->readIntResult());
+ }
+ } else if (result.integer != inst->readIntResult()) {
+ warn("%lli: Instruction results do not match! (Results may not "
+ "actually be integers) Inst: %#x, checker: %#x",
+ curTick, inst->readIntResult(), result.integer);
+ handleError();
+ }
+ }
+
+ if (inst->readNextPC() != cpuXC->readNextPC()) {
+ warn("%lli: Instruction next PCs do not match! Inst: %#x, "
+ "checker: %#x",
+ curTick, inst->readNextPC(), cpuXC->readNextPC());
+ handleError();
+ }
+
+ // Checking side effect registers can be difficult if they are not
+ // checked simultaneously with the execution of the instruction.
+ // This is because other valid instructions may have modified
+ // these registers in the meantime, and their values are not
+ // stored within the DynInst.
+ while (!miscRegIdxs.empty()) {
+ int misc_reg_idx = miscRegIdxs.front();
+ miscRegIdxs.pop();
+
+ if (inst->xcBase()->readMiscReg(misc_reg_idx) !=
+ cpuXC->readMiscReg(misc_reg_idx)) {
+ warn("%lli: Misc reg idx %i (side effect) does not match! "
+ "Inst: %#x, checker: %#x",
+ curTick, misc_reg_idx,
+ inst->xcBase()->readMiscReg(misc_reg_idx),
+ cpuXC->readMiscReg(misc_reg_idx));
+ handleError();
+ }
+ }
+}
+
+template <class DynInstPtr>
+void
+Checker<DynInstPtr>::validateState()
+{
+}
+
+template <class DynInstPtr>
+void
+Checker<DynInstPtr>::dumpInsts()
+{
+ int num = 0;
+
+ InstListIt inst_list_it = --(instList.end());
+
+ cprintf("Inst list size: %i\n", instList.size());
+
+ while (inst_list_it != instList.end())
+ {
+ cprintf("Instruction:%i\n",
+ num);
+
+ cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
+ "Completed:%i\n",
+ (*inst_list_it)->readPC(),
+ (*inst_list_it)->seqNum,
+ (*inst_list_it)->threadNumber,
+ (*inst_list_it)->isCompleted());
+
+ cprintf("\n");
+
+ inst_list_it--;
+ ++num;
+ }
+
+}
+
+template
+class Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >;
+
+template
+class Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >;
diff --git a/cpu/checker/cpu.hh b/cpu/checker/cpu.hh
new file mode 100644
index 000000000..37fe59d95
--- /dev/null
+++ b/cpu/checker/cpu.hh
@@ -0,0 +1,326 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_CHECKER_CPU_HH__
+#define __CPU_CHECKER_CPU_HH__
+
+#include <list>
+#include <queue>
+#include <map>
+
+#include "base/statistics.hh"
+#include "config/full_system.hh"
+#include "cpu/base.hh"
+#include "cpu/base_dyn_inst.hh"
+#include "cpu/cpu_exec_context.hh"
+#include "cpu/pc_event.hh"
+#include "cpu/static_inst.hh"
+#include "sim/eventq.hh"
+
+// forward declarations
+#if FULL_SYSTEM
+class Processor;
+class AlphaITB;
+class AlphaDTB;
+class PhysicalMemory;
+
+class RemoteGDB;
+class GDBListener;
+
+#else
+
+class Process;
+
+#endif // FULL_SYSTEM
+template <class>
+class BaseDynInst;
+class ExecContext;
+class MemInterface;
+class Checkpoint;
+class Sampler;
+
+class CheckerCPU : public BaseCPU
+{
+ protected:
+ typedef TheISA::MachInst MachInst;
+ typedef TheISA::MiscReg MiscReg;
+ public:
+ // main simulation loop (one cycle)
+ virtual void init();
+
+ struct Params : public BaseCPU::Params
+ {
+#if FULL_SYSTEM
+ AlphaITB *itb;
+ AlphaDTB *dtb;
+ FunctionalMemory *mem;
+#else
+ Process *process;
+#endif
+ bool exitOnError;
+ };
+
+ public:
+ CheckerCPU(Params *p);
+ virtual ~CheckerCPU();
+
+ void setMemory(FunctionalMemory *mem);
+
+ FunctionalMemory *memPtr;
+
+#if FULL_SYSTEM
+ void setSystem(System *system);
+
+ System *systemPtr;
+#endif
+ public:
+ // execution context
+ CPUExecContext *cpuXC;
+
+ ExecContext *xcProxy;
+
+ AlphaITB *itb;
+ AlphaDTB *dtb;
+
+#if FULL_SYSTEM
+ Addr dbg_vtophys(Addr addr);
+#endif
+
+ union Result {
+ uint64_t integer;
+ float fp;
+ double dbl;
+ };
+
+ Result result;
+
+ // current instruction
+ MachInst machInst;
+
+ // Refcounted pointer to the one memory request.
+ MemReqPtr memReq;
+
+ StaticInstPtr curStaticInst;
+
+ // number of simulated instructions
+ Counter numInst;
+ Counter startNumInst;
+
+ std::queue<int> miscRegIdxs;
+
+ virtual Counter totalInstructions() const
+ {
+ return numInst - startNumInst;
+ }
+
+ // number of simulated loads
+ Counter numLoad;
+ Counter startNumLoad;
+
+ virtual void serialize(std::ostream &os);
+ virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+ template <class T>
+ Fault read(Addr addr, T &data, unsigned flags);
+
+ template <class T>
+ Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
+
+ // These functions are only used in CPU models that split
+ // effective address computation from the actual memory access.
+ void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
+ Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
+
+ void prefetch(Addr addr, unsigned flags)
+ {
+ // need to do this...
+ }
+
+ void writeHint(Addr addr, int size, unsigned flags)
+ {
+ // need to do this...
+ }
+
+ Fault copySrcTranslate(Addr src);
+
+ Fault copy(Addr dest);
+
+ // The register accessor methods provide the index of the
+ // instruction's operand (e.g., 0 or 1), not the architectural
+ // register index, to simplify the implementation of register
+ // renaming. We find the architectural register index by indexing
+ // into the instruction's own operand index table. Note that a
+ // raw pointer to the StaticInst is provided instead of a
+ // ref-counted StaticInstPtr to redice overhead. This is fine as
+ // long as these methods don't copy the pointer into any long-term
+ // storage (which is pretty hard to imagine they would have reason
+ // to do).
+
+ uint64_t readIntReg(const StaticInst *si, int idx)
+ {
+ return cpuXC->readIntReg(si->srcRegIdx(idx));
+ }
+
+ float readFloatRegSingle(const StaticInst *si, int idx)
+ {
+ int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+ return cpuXC->readFloatRegSingle(reg_idx);
+ }
+
+ double readFloatRegDouble(const StaticInst *si, int idx)
+ {
+ int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+ return cpuXC->readFloatRegDouble(reg_idx);
+ }
+
+ uint64_t readFloatRegInt(const StaticInst *si, int idx)
+ {
+ int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+ return cpuXC->readFloatRegInt(reg_idx);
+ }
+
+ void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ {
+ cpuXC->setIntReg(si->destRegIdx(idx), val);
+ result.integer = val;
+ }
+
+ void setFloatRegSingle(const StaticInst *si, int idx, float val)
+ {
+ int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+ cpuXC->setFloatRegSingle(reg_idx, val);
+ result.fp = val;
+ }
+
+ void setFloatRegDouble(const StaticInst *si, int idx, double val)
+ {
+ int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+ cpuXC->setFloatRegDouble(reg_idx, val);
+ result.dbl = val;
+ }
+
+ void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
+ {
+ int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+ cpuXC->setFloatRegInt(reg_idx, val);
+ result.integer = val;
+ }
+
+ uint64_t readPC() { return cpuXC->readPC(); }
+ void setNextPC(uint64_t val) {
+ cpuXC->setNextPC(val);
+ }
+
+ MiscReg readMiscReg(int misc_reg)
+ {
+ return cpuXC->readMiscReg(misc_reg);
+ }
+
+ MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+ {
+ return cpuXC->readMiscRegWithEffect(misc_reg, fault);
+ }
+
+ Fault setMiscReg(int misc_reg, const MiscReg &val)
+ {
+ result.integer = val;
+ miscRegIdxs.push(misc_reg);
+ return cpuXC->setMiscReg(misc_reg, val);
+ }
+
+ Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+ {
+ miscRegIdxs.push(misc_reg);
+ return cpuXC->setMiscRegWithEffect(misc_reg, val);
+ }
+
+ void recordPCChange(uint64_t val) { changedPC = true; }
+ void recordNextPCChange(uint64_t val) { changedNextPC = true; }
+
+ bool translateInstReq(MemReqPtr &req);
+ void translateDataWriteReq(MemReqPtr &req);
+ void translateDataReadReq(MemReqPtr &req);
+
+#if FULL_SYSTEM
+ Fault hwrei() { return cpuXC->hwrei(); }
+ int readIntrFlag() { return cpuXC->readIntrFlag(); }
+ void setIntrFlag(int val) { cpuXC->setIntrFlag(val); }
+ bool inPalMode() { return cpuXC->inPalMode(); }
+ void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
+ bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); }
+#else
+ // Assume that the normal CPU's call to syscall was successful.
+ // The checker's state would have already been updated by the syscall.
+ void syscall() { }
+#endif
+
+ void handleError()
+ {
+ if (exitOnError)
+ panic("Checker found error!");
+ }
+ bool checkFlags(MemReqPtr &req);
+
+ ExecContext *xcBase() { return xcProxy; }
+ CPUExecContext *cpuXCBase() { return cpuXC; }
+
+ Result unverifiedResult;
+ MemReqPtr unverifiedReq;
+
+ bool changedPC;
+ bool willChangePC;
+ uint64_t newPC;
+ bool changedNextPC;
+ bool exitOnError;
+
+ InstSeqNum youngestSN;
+};
+
+template <class DynInstPtr>
+class Checker : public CheckerCPU
+{
+ public:
+ Checker(Params *p)
+ : CheckerCPU(p)
+ { }
+
+ void switchOut(Sampler *s);
+ void takeOverFrom(BaseCPU *oldCPU);
+
+ void tick(DynInstPtr &inst);
+
+ void validateInst(DynInstPtr &inst);
+ void validateExecution(DynInstPtr &inst);
+ void validateState();
+
+ std::list<DynInstPtr> instList;
+ typedef typename std::list<DynInstPtr>::iterator InstListIt;
+ void dumpInsts();
+};
+
+#endif // __CPU_CHECKER_CPU_HH__
diff --git a/cpu/checker/cpu_builder.cc b/cpu/checker/cpu_builder.cc
new file mode 100644
index 000000000..397ccab14
--- /dev/null
+++ b/cpu/checker/cpu_builder.cc
@@ -0,0 +1,126 @@
+
+#include <string>
+
+#include "cpu/checker/cpu.hh"
+#include "cpu/inst_seq.hh"
+#include "cpu/ozone/dyn_inst.hh"
+#include "cpu/ozone/ozone_impl.hh"
+#include "mem/base_mem.hh"
+#include "sim/builder.hh"
+#include "sim/process.hh"
+#include "sim/sim_object.hh"
+
+class OzoneChecker : public Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >
+{
+ public:
+ OzoneChecker(Params *p)
+ : Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >(p)
+ { }
+};
+
+////////////////////////////////////////////////////////////////////////
+//
+// CheckerCPU Simulation Object
+//
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
+
+ Param<Counter> max_insts_any_thread;
+ Param<Counter> max_insts_all_threads;
+ Param<Counter> max_loads_any_thread;
+ Param<Counter> max_loads_all_threads;
+
+#if FULL_SYSTEM
+ SimObjectParam<AlphaITB *> itb;
+ SimObjectParam<AlphaDTB *> dtb;
+ SimObjectParam<FunctionalMemory *> mem;
+ SimObjectParam<System *> system;
+ Param<int> cpu_id;
+ Param<Tick> profile;
+#else
+ SimObjectParam<Process *> workload;
+#endif // FULL_SYSTEM
+ Param<int> clock;
+ SimObjectParam<BaseMem *> icache;
+ SimObjectParam<BaseMem *> dcache;
+
+ Param<bool> defer_registration;
+ Param<bool> exitOnError;
+ Param<bool> function_trace;
+ Param<Tick> function_trace_start;
+
+END_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
+
+ INIT_PARAM(max_insts_any_thread,
+ "terminate when any thread reaches this inst count"),
+ INIT_PARAM(max_insts_all_threads,
+ "terminate when all threads have reached this inst count"),
+ INIT_PARAM(max_loads_any_thread,
+ "terminate when any thread reaches this load count"),
+ INIT_PARAM(max_loads_all_threads,
+ "terminate when all threads have reached this load count"),
+
+#if FULL_SYSTEM
+ INIT_PARAM(itb, "Instruction TLB"),
+ INIT_PARAM(dtb, "Data TLB"),
+ INIT_PARAM(mem, "memory"),
+ INIT_PARAM(system, "system object"),
+ INIT_PARAM(cpu_id, "processor ID"),
+ INIT_PARAM(profile, ""),
+#else
+ INIT_PARAM(workload, "processes to run"),
+#endif // FULL_SYSTEM
+
+ INIT_PARAM(clock, "clock speed"),
+ INIT_PARAM(icache, "L1 instruction cache object"),
+ INIT_PARAM(dcache, "L1 data cache object"),
+
+ INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
+ INIT_PARAM(exitOnError, "exit on error"),
+ INIT_PARAM(function_trace, "Enable function trace"),
+ INIT_PARAM(function_trace_start, "Cycle to start function trace")
+
+END_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
+
+
+CREATE_SIM_OBJECT(OzoneChecker)
+{
+ OzoneChecker::Params *params = new OzoneChecker::Params();
+ params->name = getInstanceName();
+ params->numberOfThreads = 1;
+ params->max_insts_any_thread = 0;
+ params->max_insts_all_threads = 0;
+ params->max_loads_any_thread = 0;
+ params->max_loads_all_threads = 0;
+ params->exitOnError = exitOnError;
+ params->deferRegistration = defer_registration;
+ params->functionTrace = function_trace;
+ params->functionTraceStart = function_trace_start;
+ params->clock = clock;
+ // Hack to touch all parameters. Consider not deriving Checker
+ // from BaseCPU..it's not really a CPU in the end.
+ Counter temp;
+ temp = max_insts_any_thread;
+ temp = max_insts_all_threads;
+ temp = max_loads_any_thread;
+ temp = max_loads_all_threads;
+ BaseMem *cache = icache;
+ cache = dcache;
+
+#if FULL_SYSTEM
+ params->itb = itb;
+ params->dtb = dtb;
+ params->mem = mem;
+ params->system = system;
+ params->cpu_id = cpu_id;
+ params->profile = profile;
+#else
+ params->process = workload;
+#endif
+
+ OzoneChecker *cpu = new OzoneChecker(params);
+ return cpu;
+}
+
+REGISTER_SIM_OBJECT("OzoneChecker", OzoneChecker)
diff --git a/cpu/checker/exec_context.hh b/cpu/checker/exec_context.hh
new file mode 100644
index 000000000..38784867d
--- /dev/null
+++ b/cpu/checker/exec_context.hh
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_CHECKER_EXEC_CONTEXT_HH__
+#define __CPU_CHECKER_EXEC_CONTEXT_HH__
+
+#include "cpu/checker/cpu.hh"
+#include "cpu/cpu_exec_context.hh"
+#include "cpu/exec_context.hh"
+
+class EndQuiesceEvent;
+namespace Kernel {
+ class Statistics;
+};
+
+template <class XC>
+class CheckerExecContext : public ExecContext
+{
+ public:
+ CheckerExecContext(XC *actual_xc,
+ CheckerCPU *checker_cpu)
+ : actualXC(actual_xc), checkerXC(checker_cpu->cpuXC),
+ checkerCPU(checker_cpu)
+ { }
+
+ private:
+ XC *actualXC;
+ CPUExecContext *checkerXC;
+ CheckerCPU *checkerCPU;
+
+ public:
+
+ BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); }
+
+ void setCpuId(int id)
+ {
+ actualXC->setCpuId(id);
+ checkerXC->setCpuId(id);
+ }
+
+ int readCpuId() { return actualXC->readCpuId(); }
+
+ FunctionalMemory *getMemPtr() { return actualXC->getMemPtr(); }
+
+#if FULL_SYSTEM
+ System *getSystemPtr() { return actualXC->getSystemPtr(); }
+
+ PhysicalMemory *getPhysMemPtr() { return actualXC->getPhysMemPtr(); }
+
+ AlphaITB *getITBPtr() { return actualXC->getITBPtr(); }
+
+ AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
+
+ Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); }
+#else
+ Process *getProcessPtr() { return actualXC->getProcessPtr(); }
+#endif
+
+ Status status() const { return actualXC->status(); }
+
+ void setStatus(Status new_status)
+ {
+ actualXC->setStatus(new_status);
+ checkerXC->setStatus(new_status);
+ }
+
+ /// Set the status to Active. Optional delay indicates number of
+ /// cycles to wait before beginning execution.
+ void activate(int delay = 1) { actualXC->activate(delay); }
+
+ /// Set the status to Suspended.
+ void suspend() { actualXC->suspend(); }
+
+ /// Set the status to Unallocated.
+ void deallocate() { actualXC->deallocate(); }
+
+ /// Set the status to Halted.
+ void halt() { actualXC->halt(); }
+
+#if FULL_SYSTEM
+ void dumpFuncProfile() { actualXC->dumpFuncProfile(); }
+#endif
+
+ void takeOverFrom(ExecContext *oldContext)
+ {
+ actualXC->takeOverFrom(oldContext);
+ checkerXC->takeOverFrom(oldContext);
+ }
+
+ void regStats(const std::string &name) { actualXC->regStats(name); }
+
+ void serialize(std::ostream &os) { actualXC->serialize(os); }
+ void unserialize(Checkpoint *cp, const std::string &section)
+ { actualXC->unserialize(cp, section); }
+
+#if FULL_SYSTEM
+ EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
+
+ Tick readLastActivate() { return actualXC->readLastActivate(); }
+ Tick readLastSuspend() { return actualXC->readLastSuspend(); }
+
+ void profileClear() { return actualXC->profileClear(); }
+ void profileSample() { return actualXC->profileSample(); }
+#endif
+
+ int getThreadNum() { return actualXC->getThreadNum(); }
+
+ // @todo: Do I need this?
+ MachInst getInst() { return actualXC->getInst(); }
+
+ // @todo: Do I need this?
+ void copyArchRegs(ExecContext *xc)
+ {
+ actualXC->copyArchRegs(xc);
+ checkerXC->copyArchRegs(xc);
+ }
+
+ void clearArchRegs()
+ {
+ actualXC->clearArchRegs();
+ checkerXC->clearArchRegs();
+ }
+
+ //
+ // New accessors for new decoder.
+ //
+ uint64_t readIntReg(int reg_idx)
+ { return actualXC->readIntReg(reg_idx); }
+
+ float readFloatRegSingle(int reg_idx)
+ { return actualXC->readFloatRegSingle(reg_idx); }
+
+ double readFloatRegDouble(int reg_idx)
+ { return actualXC->readFloatRegDouble(reg_idx); }
+
+ uint64_t readFloatRegInt(int reg_idx)
+ { return actualXC->readFloatRegInt(reg_idx); }
+
+ void setIntReg(int reg_idx, uint64_t val)
+ {
+ actualXC->setIntReg(reg_idx, val);
+ checkerXC->setIntReg(reg_idx, val);
+ }
+
+ void setFloatRegSingle(int reg_idx, float val)
+ {
+ actualXC->setFloatRegSingle(reg_idx, val);
+ checkerXC->setFloatRegSingle(reg_idx, val);
+ }
+
+ void setFloatRegDouble(int reg_idx, double val)
+ {
+ actualXC->setFloatRegDouble(reg_idx, val);
+ checkerXC->setFloatRegSingle(reg_idx, val);
+ }
+
+ void setFloatRegInt(int reg_idx, uint64_t val)
+ {
+ actualXC->setFloatRegInt(reg_idx, val);
+ checkerXC->setFloatRegInt(reg_idx, val);
+ }
+
+ uint64_t readPC() { return actualXC->readPC(); }
+
+ void setPC(uint64_t val)
+ {
+ actualXC->setPC(val);
+ checkerXC->setPC(val);
+ checkerCPU->recordPCChange(val);
+ }
+
+ uint64_t readNextPC() { return actualXC->readNextPC(); }
+
+ void setNextPC(uint64_t val)
+ {
+ actualXC->setNextPC(val);
+ checkerXC->setNextPC(val);
+ checkerCPU->recordNextPCChange(val);
+ }
+
+ MiscReg readMiscReg(int misc_reg)
+ { return actualXC->readMiscReg(misc_reg); }
+
+ MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+ { return actualXC->readMiscRegWithEffect(misc_reg, fault); }
+
+ Fault setMiscReg(int misc_reg, const MiscReg &val)
+ {
+ checkerXC->setMiscReg(misc_reg, val);
+ return actualXC->setMiscReg(misc_reg, val);
+ }
+
+ Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+ {
+ checkerXC->setMiscRegWithEffect(misc_reg, val);
+ return actualXC->setMiscRegWithEffect(misc_reg, val);
+ }
+
+ unsigned readStCondFailures()
+ { return actualXC->readStCondFailures(); }
+
+ void setStCondFailures(unsigned sc_failures)
+ {
+ checkerXC->setStCondFailures(sc_failures);
+ actualXC->setStCondFailures(sc_failures);
+ }
+#if FULL_SYSTEM
+ bool inPalMode() { return actualXC->inPalMode(); }
+#endif
+
+ // @todo: Fix this!
+ bool misspeculating() { return actualXC->misspeculating(); }
+
+#if !FULL_SYSTEM
+ IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); }
+
+ // used to shift args for indirect syscall
+ void setSyscallArg(int i, IntReg val)
+ {
+ checkerXC->setSyscallArg(i, val);
+ actualXC->setSyscallArg(i, val);
+ }
+
+ void setSyscallReturn(SyscallReturn return_value)
+ {
+ checkerXC->setSyscallReturn(return_value);
+ actualXC->setSyscallReturn(return_value);
+ }
+
+ Counter readFuncExeInst() { return actualXC->readFuncExeInst(); }
+#endif
+};
+
+#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
diff --git a/cpu/checker/o3_cpu_builder.cc b/cpu/checker/o3_cpu_builder.cc
new file mode 100644
index 000000000..125bfa398
--- /dev/null
+++ b/cpu/checker/o3_cpu_builder.cc
@@ -0,0 +1,126 @@
+
+#include <string>
+
+#include "cpu/checker/cpu.hh"
+#include "cpu/inst_seq.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "mem/base_mem.hh"
+#include "sim/builder.hh"
+#include "sim/process.hh"
+#include "sim/sim_object.hh"
+
+class O3Checker : public Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >
+{
+ public:
+ O3Checker(Params *p)
+ : Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >(p)
+ { }
+};
+
+////////////////////////////////////////////////////////////////////////
+//
+// CheckerCPU Simulation Object
+//
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
+
+ Param<Counter> max_insts_any_thread;
+ Param<Counter> max_insts_all_threads;
+ Param<Counter> max_loads_any_thread;
+ Param<Counter> max_loads_all_threads;
+
+#if FULL_SYSTEM
+ SimObjectParam<AlphaITB *> itb;
+ SimObjectParam<AlphaDTB *> dtb;
+ SimObjectParam<FunctionalMemory *> mem;
+ SimObjectParam<System *> system;
+ Param<int> cpu_id;
+ Param<Tick> profile;
+#else
+ SimObjectParam<Process *> workload;
+#endif // FULL_SYSTEM
+ Param<int> clock;
+ SimObjectParam<BaseMem *> icache;
+ SimObjectParam<BaseMem *> dcache;
+
+ Param<bool> defer_registration;
+ Param<bool> exitOnError;
+ Param<bool> function_trace;
+ Param<Tick> function_trace_start;
+
+END_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
+
+ INIT_PARAM(max_insts_any_thread,
+ "terminate when any thread reaches this inst count"),
+ INIT_PARAM(max_insts_all_threads,
+ "terminate when all threads have reached this inst count"),
+ INIT_PARAM(max_loads_any_thread,
+ "terminate when any thread reaches this load count"),
+ INIT_PARAM(max_loads_all_threads,
+ "terminate when all threads have reached this load count"),
+
+#if FULL_SYSTEM
+ INIT_PARAM(itb, "Instruction TLB"),
+ INIT_PARAM(dtb, "Data TLB"),
+ INIT_PARAM(mem, "memory"),
+ INIT_PARAM(system, "system object"),
+ INIT_PARAM(cpu_id, "processor ID"),
+ INIT_PARAM(profile, ""),
+#else
+ INIT_PARAM(workload, "processes to run"),
+#endif // FULL_SYSTEM
+
+ INIT_PARAM(clock, "clock speed"),
+ INIT_PARAM(icache, "L1 instruction cache object"),
+ INIT_PARAM(dcache, "L1 data cache object"),
+
+ INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
+ INIT_PARAM(exitOnError, "exit on error"),
+ INIT_PARAM(function_trace, "Enable function trace"),
+ INIT_PARAM(function_trace_start, "Cycle to start function trace")
+
+END_INIT_SIM_OBJECT_PARAMS(O3Checker)
+
+
+CREATE_SIM_OBJECT(O3Checker)
+{
+ O3Checker::Params *params = new O3Checker::Params();
+ params->name = getInstanceName();
+ params->numberOfThreads = 1;
+ params->max_insts_any_thread = 0;
+ params->max_insts_all_threads = 0;
+ params->max_loads_any_thread = 0;
+ params->max_loads_all_threads = 0;
+ params->exitOnError = exitOnError;
+ params->deferRegistration = defer_registration;
+ params->functionTrace = function_trace;
+ params->functionTraceStart = function_trace_start;
+ params->clock = clock;
+ // Hack to touch all parameters. Consider not deriving Checker
+ // from BaseCPU..it's not really a CPU in the end.
+ Counter temp;
+ temp = max_insts_any_thread;
+ temp = max_insts_all_threads;
+ temp = max_loads_any_thread;
+ temp = max_loads_all_threads;
+ BaseMem *cache = icache;
+ cache = dcache;
+
+#if FULL_SYSTEM
+ params->itb = itb;
+ params->dtb = dtb;
+ params->mem = mem;
+ params->system = system;
+ params->cpu_id = cpu_id;
+ params->profile = profile;
+#else
+ params->process = workload;
+#endif
+
+ O3Checker *cpu = new O3Checker(params);
+ return cpu;
+}
+
+REGISTER_SIM_OBJECT("O3Checker", O3Checker)
diff --git a/cpu/o3/dep_graph.hh b/cpu/o3/dep_graph.hh
new file mode 100644
index 000000000..f8ae38da4
--- /dev/null
+++ b/cpu/o3/dep_graph.hh
@@ -0,0 +1,213 @@
+
+#ifndef __CPU_O3_DEP_GRAPH_HH__
+#define __CPU_O3_DEP_GRAPH_HH__
+
+#include "cpu/o3/comm.hh"
+
+template <class DynInstPtr>
+class DependencyEntry
+{
+ public:
+ DependencyEntry()
+ : inst(NULL), next(NULL)
+ { }
+
+ DynInstPtr inst;
+ //Might want to include data about what arch. register the
+ //dependence is waiting on.
+ DependencyEntry<DynInstPtr> *next;
+};
+
+template <class DynInstPtr>
+class DependencyGraph
+{
+ public:
+ typedef DependencyEntry<DynInstPtr> DepEntry;
+
+ DependencyGraph()
+ : numEntries(0), memAllocCounter(0), nodesTraversed(0), nodesRemoved(0)
+ { }
+
+ void resize(int num_entries);
+
+ void reset();
+
+ void insert(PhysRegIndex idx, DynInstPtr &new_inst);
+
+ void setInst(PhysRegIndex idx, DynInstPtr &new_inst)
+ { dependGraph[idx].inst = new_inst; }
+
+ void clearInst(PhysRegIndex idx)
+ { dependGraph[idx].inst = NULL; }
+
+ void remove(PhysRegIndex idx, DynInstPtr &inst_to_remove);
+
+ DynInstPtr pop(PhysRegIndex idx);
+
+ bool empty(PhysRegIndex idx) { return !dependGraph[idx].next; }
+
+ /** Debugging function to dump out the dependency graph.
+ */
+ void dump();
+
+ private:
+ /** Array of linked lists. Each linked list is a list of all the
+ * instructions that depend upon a given register. The actual
+ * register's index is used to index into the graph; ie all
+ * instructions in flight that are dependent upon r34 will be
+ * in the linked list of dependGraph[34].
+ */
+ DepEntry *dependGraph;
+
+ int numEntries;
+
+ // Debug variable, remove when done testing.
+ unsigned memAllocCounter;
+
+ public:
+ uint64_t nodesTraversed;
+ uint64_t nodesRemoved;
+};
+
+template <class DynInstPtr>
+void
+DependencyGraph<DynInstPtr>::resize(int num_entries)
+{
+ numEntries = num_entries;
+ dependGraph = new DepEntry[numEntries];
+}
+
+template <class DynInstPtr>
+void
+DependencyGraph<DynInstPtr>::reset()
+{
+ // Clear the dependency graph
+ DepEntry *curr;
+ DepEntry *prev;
+
+ for (int i = 0; i < numEntries; ++i) {
+ curr = dependGraph[i].next;
+
+ while (curr) {
+ memAllocCounter--;
+
+ prev = curr;
+ curr = prev->next;
+ prev->inst = NULL;
+
+ delete prev;
+ }
+
+ if (dependGraph[i].inst) {
+ dependGraph[i].inst = NULL;
+ }
+
+ dependGraph[i].next = NULL;
+ }
+}
+
+template <class DynInstPtr>
+void
+DependencyGraph<DynInstPtr>::insert(PhysRegIndex idx, DynInstPtr &new_inst)
+{
+ //Add this new, dependent instruction at the head of the dependency
+ //chain.
+
+ // First create the entry that will be added to the head of the
+ // dependency chain.
+ DepEntry *new_entry = new DepEntry;
+ new_entry->next = dependGraph[idx].next;
+ new_entry->inst = new_inst;
+
+ // Then actually add it to the chain.
+ dependGraph[idx].next = new_entry;
+
+ ++memAllocCounter;
+}
+
+
+template <class DynInstPtr>
+void
+DependencyGraph<DynInstPtr>::remove(PhysRegIndex idx,
+ DynInstPtr &inst_to_remove)
+{
+ DepEntry *prev = &dependGraph[idx];
+ DepEntry *curr = dependGraph[idx].next;
+
+ // Make sure curr isn't NULL. Because this instruction is being
+ // removed from a dependency list, it must have been placed there at
+ // an earlier time. The dependency chain should not be empty,
+ // unless the instruction dependent upon it is already ready.
+ if (curr == NULL) {
+ return;
+ }
+
+ nodesRemoved++;
+
+ // Find the instruction to remove within the dependency linked list.
+ while (curr->inst != inst_to_remove) {
+ prev = curr;
+ curr = curr->next;
+ nodesTraversed++;
+
+ assert(curr != NULL);
+ }
+
+ // Now remove this instruction from the list.
+ prev->next = curr->next;
+
+ --memAllocCounter;
+
+ // Could push this off to the destructor of DependencyEntry
+ curr->inst = NULL;
+
+ delete curr;
+}
+
+template <class DynInstPtr>
+DynInstPtr
+DependencyGraph<DynInstPtr>::pop(PhysRegIndex idx)
+{
+ DepEntry *node;
+ node = dependGraph[idx].next;
+ DynInstPtr inst = NULL;
+ if (node) {
+ inst = node->inst;
+ dependGraph[idx].next = node->next;
+ node->inst = NULL;
+ memAllocCounter--;
+ delete node;
+ }
+ return inst;
+}
+
+template <class DynInstPtr>
+void
+DependencyGraph<DynInstPtr>::dump()
+{
+ DepEntry *curr;
+
+ for (int i = 0; i < numEntries; ++i)
+ {
+ curr = &dependGraph[i];
+
+ if (curr->inst) {
+ cprintf("dependGraph[%i]: producer: %#x [sn:%lli] consumer: ",
+ i, curr->inst->readPC(), curr->inst->seqNum);
+ } else {
+ cprintf("dependGraph[%i]: No producer. consumer: ", i);
+ }
+
+ while (curr->next != NULL) {
+ curr = curr->next;
+
+ cprintf("%#x [sn:%lli] ",
+ curr->inst->readPC(), curr->inst->seqNum);
+ }
+
+ cprintf("\n");
+ }
+ cprintf("memAllocCounter: %i\n", memAllocCounter);
+}
+
+#endif // __CPU_O3_DEP_GRAPH_HH__
diff --git a/cpu/o3/fu_pool.cc b/cpu/o3/fu_pool.cc
new file mode 100644
index 000000000..fb2b5c00d
--- /dev/null
+++ b/cpu/o3/fu_pool.cc
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sstream>
+
+#include "cpu/o3/fu_pool.hh"
+#include "encumbered/cpu/full/fu_pool.hh"
+#include "sim/builder.hh"
+
+using namespace std;
+
+////////////////////////////////////////////////////////////////////////////
+//
+// A pool of function units
+//
+
+inline void
+FUPool::FUIdxQueue::addFU(int fu_idx)
+{
+ funcUnitsIdx.push_back(fu_idx);
+ ++size;
+}
+
+inline int
+FUPool::FUIdxQueue::getFU()
+{
+ int retval = funcUnitsIdx[idx++];
+
+ if (idx == size)
+ idx = 0;
+
+ return retval;
+}
+
+FUPool::~FUPool()
+{
+ fuListIterator i = funcUnits.begin();
+ fuListIterator end = funcUnits.end();
+ for (; i != end; ++i)
+ delete *i;
+}
+
+
+// Constructor
+FUPool::FUPool(string name, vector<FUDesc *> paramList)
+ : SimObject(name)
+{
+ numFU = 0;
+
+ funcUnits.clear();
+
+ for (int i = 0; i < Num_OpClasses; ++i) {
+ maxOpLatencies[i] = 0;
+ maxIssueLatencies[i] = 0;
+ }
+
+ //
+ // Iterate through the list of FUDescData structures
+ //
+ for (FUDDiterator i = paramList.begin(); i != paramList.end(); ++i) {
+
+ //
+ // Don't bother with this if we're not going to create any FU's
+ //
+ if ((*i)->number) {
+ //
+ // Create the FuncUnit object from this structure
+ // - add the capabilities listed in the FU's operation
+ // description
+ //
+ // We create the first unit, then duplicate it as needed
+ //
+ FuncUnit *fu = new FuncUnit;
+
+ OPDDiterator j = (*i)->opDescList.begin();
+ OPDDiterator end = (*i)->opDescList.end();
+ for (; j != end; ++j) {
+ // indicate that this pool has this capability
+ capabilityList.set((*j)->opClass);
+
+ // Add each of the FU's that will have this capability to the
+ // appropriate queue.
+ for (int k = 0; k < (*i)->number; ++k)
+ fuPerCapList[(*j)->opClass].addFU(numFU + k);
+
+ // indicate that this FU has the capability
+ fu->addCapability((*j)->opClass, (*j)->opLat, (*j)->issueLat);
+
+ if ((*j)->opLat > maxOpLatencies[(*j)->opClass])
+ maxOpLatencies[(*j)->opClass] = (*j)->opLat;
+
+ if ((*j)->issueLat > maxIssueLatencies[(*j)->opClass])
+ maxIssueLatencies[(*j)->opClass] = (*j)->issueLat;
+ }
+
+ numFU++;
+
+ // Add the appropriate number of copies of this FU to the list
+ ostringstream s;
+
+ s << (*i)->name() << "(0)";
+ fu->name = s.str();
+ funcUnits.push_back(fu);
+
+ for (int c = 1; c < (*i)->number; ++c) {
+ ostringstream s;
+ numFU++;
+ FuncUnit *fu2 = new FuncUnit(*fu);
+
+ s << (*i)->name() << "(" << c << ")";
+ fu2->name = s.str();
+ funcUnits.push_back(fu2);
+ }
+ }
+ }
+
+ unitBusy.resize(numFU);
+
+ for (int i = 0; i < numFU; i++) {
+ unitBusy[i] = false;
+ }
+}
+
+void
+FUPool::annotateMemoryUnits(unsigned hit_latency)
+{
+ maxOpLatencies[MemReadOp] = hit_latency;
+
+ fuListIterator i = funcUnits.begin();
+ fuListIterator iend = funcUnits.end();
+ for (; i != iend; ++i) {
+ if ((*i)->provides(MemReadOp))
+ (*i)->opLatency(MemReadOp) = hit_latency;
+
+ if ((*i)->provides(MemWriteOp))
+ (*i)->opLatency(MemWriteOp) = hit_latency;
+ }
+}
+
+int
+FUPool::getUnit(OpClass capability)
+{
+ // If this pool doesn't have the specified capability,
+ // return this information to the caller
+ if (!capabilityList[capability])
+ return -2;
+
+ int fu_idx = fuPerCapList[capability].getFU();
+ int start_idx = fu_idx;
+
+ // Iterate through the circular queue if needed, stopping if we've reached
+ // the first element again.
+ while (unitBusy[fu_idx]) {
+ fu_idx = fuPerCapList[capability].getFU();
+ if (fu_idx == start_idx) {
+ // No FU available
+ return -1;
+ }
+ }
+
+ unitBusy[fu_idx] = true;
+
+ return fu_idx;
+}
+
+void
+FUPool::freeUnitNextCycle(int fu_idx)
+{
+ assert(unitBusy[fu_idx]);
+ unitsToBeFreed.push_back(fu_idx);
+}
+
+void
+FUPool::processFreeUnits()
+{
+ while (!unitsToBeFreed.empty()) {
+ int fu_idx = unitsToBeFreed.back();
+ unitsToBeFreed.pop_back();
+
+ assert(unitBusy[fu_idx]);
+
+ unitBusy[fu_idx] = false;
+ }
+}
+
+void
+FUPool::dump()
+{
+ cout << "Function Unit Pool (" << name() << ")\n";
+ cout << "======================================\n";
+ cout << "Free List:\n";
+
+ for (int i = 0; i < numFU; ++i) {
+ if (unitBusy[i]) {
+ continue;
+ }
+
+ cout << " [" << i << "] : ";
+
+ cout << funcUnits[i]->name << " ";
+
+ cout << "\n";
+ }
+
+ cout << "======================================\n";
+ cout << "Busy List:\n";
+ for (int i = 0; i < numFU; ++i) {
+ if (!unitBusy[i]) {
+ continue;
+ }
+
+ cout << " [" << i << "] : ";
+
+ cout << funcUnits[i]->name << " ";
+
+ cout << "\n";
+ }
+}
+
+void
+FUPool::switchOut()
+{
+}
+
+void
+FUPool::takeOverFrom()
+{
+ for (int i = 0; i < numFU; i++) {
+ unitBusy[i] = false;
+ }
+ unitsToBeFreed.clear();
+}
+
+//
+
+////////////////////////////////////////////////////////////////////////////
+//
+// The SimObjects we use to get the FU information into the simulator
+//
+////////////////////////////////////////////////////////////////////////////
+
+//
+// FUPool - Contails a list of FUDesc objects to make available
+//
+
+//
+// The FuPool object
+//
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUPool)
+
+ SimObjectVectorParam<FUDesc *> FUList;
+
+END_DECLARE_SIM_OBJECT_PARAMS(FUPool)
+
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(FUPool)
+
+ INIT_PARAM(FUList, "list of FU's for this pool")
+
+END_INIT_SIM_OBJECT_PARAMS(FUPool)
+
+
+CREATE_SIM_OBJECT(FUPool)
+{
+ return new FUPool(getInstanceName(), FUList);
+}
+
+REGISTER_SIM_OBJECT("FUPool", FUPool)
+
diff --git a/cpu/o3/fu_pool.hh b/cpu/o3/fu_pool.hh
new file mode 100644
index 000000000..da6fdc802
--- /dev/null
+++ b/cpu/o3/fu_pool.hh
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_O3_FU_POOL_HH__
+#define __CPU_O3_FU_POOL_HH__
+
+#include <bitset>
+#include <list>
+#include <string>
+#include <vector>
+
+#include "base/sched_list.hh"
+#include "encumbered/cpu/full/op_class.hh"
+#include "sim/sim_object.hh"
+
+class FUDesc;
+class FuncUnit;
+
+/**
+ * Pool of FU's, specific to the new CPU model. The old FU pool had lists of
+ * free units and busy units, and whenever a FU was needed it would iterate
+ * through the free units to find a FU that provided the capability. This pool
+ * has lists of units specific to each of the capabilities, and whenever a FU
+ * is needed, it iterates through that list to find a free unit. The previous
+ * FU pool would have to be ticked each cycle to update which units became
+ * free. This FU pool lets the IEW stage handle freeing units, which frees
+ * them as their scheduled execution events complete. This limits units in this
+ * model to either have identical issue and op latencies, or 1 cycle issue
+ * latencies.
+ */
+class FUPool : public SimObject
+{
+ private:
+ /** Maximum op execution latencies, per op class. */
+ unsigned maxOpLatencies[Num_OpClasses];
+ /** Maximum issue latencies, per op class. */
+ unsigned maxIssueLatencies[Num_OpClasses];
+
+ /** Bitvector listing capabilities of this FU pool. */
+ std::bitset<Num_OpClasses> capabilityList;
+
+ /** Bitvector listing which FUs are busy. */
+ std::vector<bool> unitBusy;
+
+ /** List of units to be freed at the end of this cycle. */
+ std::vector<int> unitsToBeFreed;
+
+ /**
+ * Class that implements a circular queue to hold FU indices. The hope is
+ * that FUs that have been just used will be moved to the end of the queue
+ * by iterating through it, thus leaving free units at the head of the
+ * queue.
+ */
+ class FUIdxQueue {
+ public:
+ /** Constructs a circular queue of FU indices. */
+ FUIdxQueue()
+ : idx(0), size(0)
+ { }
+
+ /** Adds a FU to the queue. */
+ inline void addFU(int fu_idx);
+
+ /** Returns the index of the FU at the head of the queue, and changes
+ * the index to the next element.
+ */
+ inline int getFU();
+
+ private:
+ /** Circular queue index. */
+ int idx;
+
+ /** Size of the queue. */
+ int size;
+
+ /** Queue of FU indices. */
+ std::vector<int> funcUnitsIdx;
+ };
+
+ /** Per op class queues of FUs that provide that capability. */
+ FUIdxQueue fuPerCapList[Num_OpClasses];
+
+ /** Number of FUs. */
+ int numFU;
+
+ /** Functional units. */
+ std::vector<FuncUnit *> funcUnits;
+
+ typedef std::vector<FuncUnit *>::iterator fuListIterator;
+
+ public:
+
+ /** Constructs a FU pool. */
+ FUPool(std::string name, std::vector<FUDesc *> l);
+ ~FUPool();
+
+ /** Annotates units that provide memory operations. Included only because
+ * old FU pool provided this function.
+ */
+ void annotateMemoryUnits(unsigned hit_latency);
+
+ /**
+ * Gets a FU providing the requested capability. Will mark the unit as busy,
+ * but leaves the freeing of the unit up to the IEW stage.
+ * @param capability The capability requested.
+ * @return Returns -2 if the FU pool does not have the capability, -1 if
+ * there is no free FU, and the FU's index otherwise.
+ */
+ int getUnit(OpClass capability);
+
+ /** Frees a FU at the end of this cycle. */
+ void freeUnitNextCycle(int fu_idx);
+
+ /** Frees all FUs on the list. */
+ void processFreeUnits();
+
+ /** Returns the total number of FUs. */
+ int size() { return numFU; }
+
+ /** Debugging function used to dump FU information. */
+ void dump();
+
+ /** Returns the operation execution latency of the given capability. */
+ unsigned getOpLatency(OpClass capability) {
+ return maxOpLatencies[capability];
+ }
+
+ /** Returns the issue latency of the given capability. */
+ unsigned getIssueLatency(OpClass capability) {
+ return maxIssueLatencies[capability];
+ }
+
+ void switchOut();
+ void takeOverFrom();
+};
+
+#endif // __CPU_O3_FU_POOL_HH__
diff --git a/cpu/o3/lsq.cc b/cpu/o3/lsq.cc
new file mode 100644
index 000000000..8991ab8f8
--- /dev/null
+++ b/cpu/o3/lsq.cc
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_cpu.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/lsq_impl.hh"
+
+// Force the instantiation of LDSTQ for all the implementations we care about.
+template class LSQ<AlphaSimpleImpl>;
+
diff --git a/cpu/o3/lsq.hh b/cpu/o3/lsq.hh
new file mode 100644
index 000000000..a1eeccbe7
--- /dev/null
+++ b/cpu/o3/lsq.hh
@@ -0,0 +1,324 @@
+/*
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_O3_LSQ_HH__
+#define __CPU_O3_LSQ_HH__
+
+#include <map>
+#include <queue>
+
+#include "config/full_system.hh"
+#include "cpu/inst_seq.hh"
+//#include "cpu/o3/cpu_policy.hh"
+#include "cpu/o3/lsq_unit.hh"
+#include "mem/mem_interface.hh"
+//#include "mem/page_table.hh"
+#include "sim/sim_object.hh"
+
+template <class Impl>
+class LSQ {
+ public:
+ typedef typename Impl::Params Params;
+ typedef typename Impl::FullCPU FullCPU;
+ typedef typename Impl::DynInstPtr DynInstPtr;
+ typedef typename Impl::CPUPol::IEW IEW;
+ typedef typename Impl::CPUPol::LSQUnit LSQUnit;
+
+ enum LSQPolicy {
+ Dynamic,
+ Partitioned,
+ Threshold
+ };
+
+ /** Constructs an LSQ with the given parameters. */
+ LSQ(Params *params);
+
+ /** Returns the name of the LSQ. */
+ std::string name() const;
+
+ /** Sets the pointer to the list of active threads. */
+ void setActiveThreads(std::list<unsigned> *at_ptr);
+ /** Sets the CPU pointer. */
+ void setCPU(FullCPU *cpu_ptr);
+ /** Sets the IEW stage pointer. */
+ void setIEW(IEW *iew_ptr);
+ /** Sets the page table pointer. */
+// void setPageTable(PageTable *pt_ptr);
+
+ void switchOut();
+ void takeOverFrom();
+
+ /** Number of entries needed for the given amount of threads.*/
+ int entryAmount(int num_threads);
+ void removeEntries(unsigned tid);
+ /** Reset the max entries for each thread. */
+ void resetEntries();
+ /** Resize the max entries for a thread. */
+ void resizeEntries(unsigned size, unsigned tid);
+
+ /** Ticks the LSQ. */
+ void tick();
+ /** Ticks a specific LSQ Unit. */
+ void tick(unsigned tid)
+ { thread[tid].tick(); }
+
+ /** Inserts a load into the LSQ. */
+ void insertLoad(DynInstPtr &load_inst);
+ /** Inserts a store into the LSQ. */
+ void insertStore(DynInstPtr &store_inst);
+
+ /** Executes a load. */
+ Fault executeLoad(DynInstPtr &inst);
+
+ Fault executeLoad(int lq_idx, unsigned tid)
+ { return thread[tid].executeLoad(lq_idx); }
+
+ /** Executes a store. */
+ Fault executeStore(DynInstPtr &inst);
+
+ /**
+ * Commits loads up until the given sequence number for a specific thread.
+ */
+ void commitLoads(InstSeqNum &youngest_inst, unsigned tid)
+ { thread[tid].commitLoads(youngest_inst); }
+
+ /**
+ * Commits stores up until the given sequence number for a specific thread.
+ */
+ void commitStores(InstSeqNum &youngest_inst, unsigned tid)
+ { thread[tid].commitStores(youngest_inst); }
+
+ /**
+ * Attempts to write back stores until all cache ports are used or the
+ * interface becomes blocked.
+ */
+ void writebackStores();
+ /** Same as above, but only for one thread. */
+ void writebackStores(unsigned tid);
+
+ /**
+ * Squash instructions from a thread until the specified sequence number.
+ */
+ void squash(const InstSeqNum &squashed_num, unsigned tid)
+ { thread[tid].squash(squashed_num); }
+
+ /** Returns whether or not there was a memory ordering violation. */
+ bool violation();
+ /**
+ * Returns whether or not there was a memory ordering violation for a
+ * specific thread.
+ */
+ bool violation(unsigned tid)
+ { return thread[tid].violation(); }
+
+ /** Returns if a load is blocked due to the memory system for a specific
+ * thread.
+ */
+ bool loadBlocked(unsigned tid)
+ { return thread[tid].loadBlocked(); }
+
+ bool isLoadBlockedHandled(unsigned tid)
+ { return thread[tid].isLoadBlockedHandled(); }
+
+ void setLoadBlockedHandled(unsigned tid)
+ { thread[tid].setLoadBlockedHandled(); }
+
+ /** Gets the instruction that caused the memory ordering violation. */
+ DynInstPtr getMemDepViolator(unsigned tid)
+ { return thread[tid].getMemDepViolator(); }
+
+ /** Returns the head index of the load queue for a specific thread. */
+ int getLoadHead(unsigned tid)
+ { return thread[tid].getLoadHead(); }
+
+ /** Returns the sequence number of the head of the load queue. */
+ InstSeqNum getLoadHeadSeqNum(unsigned tid)
+ {
+ return thread[tid].getLoadHeadSeqNum();
+ }
+
+ /** Returns the head index of the store queue. */
+ int getStoreHead(unsigned tid)
+ { return thread[tid].getStoreHead(); }
+
+ /** Returns the sequence number of the head of the store queue. */
+ InstSeqNum getStoreHeadSeqNum(unsigned tid)
+ {
+ return thread[tid].getStoreHeadSeqNum();
+ }
+
+ /** Returns the number of instructions in all of the queues. */
+ int getCount();
+ /** Returns the number of instructions in the queues of one thread. */
+ int getCount(unsigned tid)
+ { return thread[tid].getCount(); }
+
+ /** Returns the total number of loads in the load queue. */
+ int numLoads();
+ /** Returns the total number of loads for a single thread. */
+ int numLoads(unsigned tid)
+ { return thread[tid].numLoads(); }
+
+ /** Returns the total number of stores in the store queue. */
+ int numStores();
+ /** Returns the total number of stores for a single thread. */
+ int numStores(unsigned tid)
+ { return thread[tid].numStores(); }
+
+ /** Returns the total number of loads that are ready. */
+ int numLoadsReady();
+ /** Returns the number of loads that are ready for a single thread. */
+ int numLoadsReady(unsigned tid)
+ { return thread[tid].numLoadsReady(); }
+
+ /** Returns the number of free entries. */
+ unsigned numFreeEntries();
+ /** Returns the number of free entries for a specific thread. */
+ unsigned numFreeEntries(unsigned tid);
+
+ /** Returns if the LSQ is full (either LQ or SQ is full). */
+ bool isFull();
+ /**
+ * Returns if the LSQ is full for a specific thread (either LQ or SQ is
+ * full).
+ */
+ bool isFull(unsigned tid);
+
+ /** Returns if any of the LQs are full. */
+ bool lqFull();
+ /** Returns if the LQ of a given thread is full. */
+ bool lqFull(unsigned tid);
+
+ /** Returns if any of the SQs are full. */
+ bool sqFull();
+ /** Returns if the SQ of a given thread is full. */
+ bool sqFull(unsigned tid);
+
+ /**
+ * Returns if the LSQ is stalled due to a memory operation that must be
+ * replayed.
+ */
+ bool isStalled();
+ /**
+ * Returns if the LSQ of a specific thread is stalled due to a memory
+ * operation that must be replayed.
+ */
+ bool isStalled(unsigned tid);
+
+ /** Returns whether or not there are any stores to write back to memory. */
+ bool hasStoresToWB();
+
+ /** Returns whether or not a specific thread has any stores to write back
+ * to memory.
+ */
+ bool hasStoresToWB(unsigned tid)
+ { return thread[tid].hasStoresToWB(); }
+
+ /** Returns the number of stores a specific thread has to write back. */
+ int numStoresToWB(unsigned tid)
+ { return thread[tid].numStoresToWB(); }
+
+ /** Returns if the LSQ will write back to memory this cycle. */
+ bool willWB();
+ /** Returns if the LSQ of a specific thread will write back to memory this
+ * cycle.
+ */
+ bool willWB(unsigned tid)
+ { return thread[tid].willWB(); }
+
+ /** Debugging function to print out all instructions. */
+ void dumpInsts();
+ /** Debugging function to print out instructions from a specific thread. */
+ void dumpInsts(unsigned tid)
+ { thread[tid].dumpInsts(); }
+
+ /** Executes a read operation, using the load specified at the load index. */
+ template <class T>
+ Fault read(MemReqPtr &req, T &data, int load_idx);
+
+ /** Executes a store operation, using the store specified at the store
+ * index.
+ */
+ template <class T>
+ Fault write(MemReqPtr &req, T &data, int store_idx);
+
+ private:
+ /** The LSQ policy for SMT mode. */
+ LSQPolicy lsqPolicy;
+
+ /** The LSQ units for individual threads. */
+ LSQUnit thread[Impl::MaxThreads];
+
+ /** The CPU pointer. */
+ FullCPU *cpu;
+
+ /** The IEW stage pointer. */
+ IEW *iewStage;
+
+ /** The pointer to the page table. */
+// PageTable *pTable;
+
+ /** List of Active Threads in System. */
+ std::list<unsigned> *activeThreads;
+
+ /** Total Size of LQ Entries. */
+ unsigned LQEntries;
+ /** Total Size of SQ Entries. */
+ unsigned SQEntries;
+
+ /** Max LQ Size - Used to Enforce Sharing Policies. */
+ unsigned maxLQEntries;
+
+ /** Max SQ Size - Used to Enforce Sharing Policies. */
+ unsigned maxSQEntries;
+
+ /** Number of Threads. */
+ unsigned numThreads;
+};
+
+template <class Impl>
+template <class T>
+Fault
+LSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx)
+{
+ unsigned tid = req->thread_num;
+
+ return thread[tid].read(req, data, load_idx);
+}
+
+template <class Impl>
+template <class T>
+Fault
+LSQ<Impl>::write(MemReqPtr &req, T &data, int store_idx)
+{
+ unsigned tid = req->thread_num;
+
+ return thread[tid].write(req, data, store_idx);
+}
+
+#endif // __CPU_O3_LSQ_HH__
diff --git a/cpu/o3/lsq_impl.hh b/cpu/o3/lsq_impl.hh
new file mode 100644
index 000000000..a6ad27522
--- /dev/null
+++ b/cpu/o3/lsq_impl.hh
@@ -0,0 +1,538 @@
+/*
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <algorithm>
+#include <string>
+
+#include "cpu/o3/lsq.hh"
+
+using namespace std;
+
+template <class Impl>
+LSQ<Impl>::LSQ(Params *params)
+ : LQEntries(params->LQEntries), SQEntries(params->SQEntries),
+ numThreads(params->numberOfThreads)
+{
+ DPRINTF(LSQ, "Creating LSQ object.\n");
+
+ //**********************************************/
+ //************ Handle SMT Parameters ***********/
+ //**********************************************/
+ string policy = params->smtLSQPolicy;
+
+ //Convert string to lowercase
+ std::transform(policy.begin(), policy.end(), policy.begin(),
+ (int(*)(int)) tolower);
+
+ //Figure out fetch policy
+ if (policy == "dynamic") {
+ lsqPolicy = Dynamic;
+
+ maxLQEntries = LQEntries;
+ maxSQEntries = SQEntries;
+
+ DPRINTF(LSQ, "LSQ sharing policy set to Dynamic\n");
+
+ } else if (policy == "partitioned") {
+ lsqPolicy = Partitioned;
+
+ //@todo:make work if part_amt doesnt divide evenly.
+ maxLQEntries = LQEntries / numThreads;
+ maxSQEntries = SQEntries / numThreads;
+
+ DPRINTF(Fetch, "LSQ sharing policy set to Partitioned: "
+ "%i entries per LQ | %i entries per SQ",
+ maxLQEntries,maxSQEntries);
+
+ } else if (policy == "threshold") {
+ lsqPolicy = Threshold;
+
+ assert(params->smtLSQThreshold > LQEntries);
+ assert(params->smtLSQThreshold > SQEntries);
+
+ //Divide up by threshold amount
+ //@todo: Should threads check the max and the total
+ //amount of the LSQ
+ maxLQEntries = params->smtLSQThreshold;
+ maxSQEntries = params->smtLSQThreshold;
+
+ DPRINTF(LSQ, "LSQ sharing policy set to Threshold: "
+ "%i entries per LQ | %i entries per SQ",
+ maxLQEntries,maxSQEntries);
+
+ } else {
+ assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic,"
+ "Partitioned, Threshold}");
+ }
+
+ //Initialize LSQs
+ for (int tid=0; tid < numThreads; tid++) {
+ thread[tid].init(params, maxLQEntries, maxSQEntries, tid);
+ }
+}
+
+
+template<class Impl>
+std::string
+LSQ<Impl>::name() const
+{
+ return iewStage->name() + ".lsq";
+}
+
+template<class Impl>
+void
+LSQ<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+{
+ activeThreads = at_ptr;
+ assert(activeThreads != 0);
+}
+
+template<class Impl>
+void
+LSQ<Impl>::setCPU(FullCPU *cpu_ptr)
+{
+ cpu = cpu_ptr;
+
+ for (int tid=0; tid < numThreads; tid++) {
+ thread[tid].setCPU(cpu_ptr);
+ }
+}
+
+template<class Impl>
+void
+LSQ<Impl>::setIEW(IEW *iew_ptr)
+{
+ iewStage = iew_ptr;
+
+ for (int tid=0; tid < numThreads; tid++) {
+ thread[tid].setIEW(iew_ptr);
+ }
+}
+
+#if 0
+template<class Impl>
+void
+LSQ<Impl>::setPageTable(PageTable *pt_ptr)
+{
+ for (int tid=0; tid < numThreads; tid++) {
+ thread[tid].setPageTable(pt_ptr);
+ }
+}
+#endif
+
+template <class Impl>
+void
+LSQ<Impl>::switchOut()
+{
+ for (int tid = 0; tid < numThreads; tid++) {
+ thread[tid].switchOut();
+ }
+}
+
+template <class Impl>
+void
+LSQ<Impl>::takeOverFrom()
+{
+ for (int tid = 0; tid < numThreads; tid++) {
+ thread[tid].takeOverFrom();
+ }
+}
+
+template <class Impl>
+int
+LSQ<Impl>::entryAmount(int num_threads)
+{
+ if (lsqPolicy == Partitioned) {
+ return LQEntries / num_threads;
+ } else {
+ return 0;
+ }
+}
+
+template <class Impl>
+void
+LSQ<Impl>::resetEntries()
+{
+ if (lsqPolicy != Dynamic || numThreads > 1) {
+ int active_threads = (*activeThreads).size();
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+ list<unsigned>::iterator list_end = (*activeThreads).end();
+
+ int maxEntries;
+
+ if (lsqPolicy == Partitioned) {
+ maxEntries = LQEntries / active_threads;
+ } else if (lsqPolicy == Threshold && active_threads == 1) {
+ maxEntries = LQEntries;
+ } else {
+ maxEntries = LQEntries;
+ }
+
+ while (threads != list_end) {
+ resizeEntries(maxEntries,*threads++);
+ }
+ }
+}
+
+template<class Impl>
+void
+LSQ<Impl>::removeEntries(unsigned tid)
+{
+ thread[tid].clearLQ();
+ thread[tid].clearSQ();
+}
+
+template<class Impl>
+void
+LSQ<Impl>::resizeEntries(unsigned size,unsigned tid)
+{
+ thread[tid].resizeLQ(size);
+ thread[tid].resizeSQ(size);
+}
+
+template<class Impl>
+void
+LSQ<Impl>::tick()
+{
+ list<unsigned>::iterator active_threads = (*activeThreads).begin();
+
+ while (active_threads != (*activeThreads).end()) {
+ unsigned tid = *active_threads++;
+
+ thread[tid].tick();
+ }
+}
+
+template<class Impl>
+void
+LSQ<Impl>::insertLoad(DynInstPtr &load_inst)
+{
+ unsigned tid = load_inst->threadNumber;
+
+ thread[tid].insertLoad(load_inst);
+}
+
+template<class Impl>
+void
+LSQ<Impl>::insertStore(DynInstPtr &store_inst)
+{
+ unsigned tid = store_inst->threadNumber;
+
+ thread[tid].insertStore(store_inst);
+}
+
+template<class Impl>
+Fault
+LSQ<Impl>::executeLoad(DynInstPtr &inst)
+{
+ unsigned tid = inst->threadNumber;
+
+ return thread[tid].executeLoad(inst);
+}
+
+template<class Impl>
+Fault
+LSQ<Impl>::executeStore(DynInstPtr &inst)
+{
+ unsigned tid = inst->threadNumber;
+
+ return thread[tid].executeStore(inst);
+}
+
+template<class Impl>
+void
+LSQ<Impl>::writebackStores()
+{
+ list<unsigned>::iterator active_threads = (*activeThreads).begin();
+
+ while (active_threads != (*activeThreads).end()) {
+ unsigned tid = *active_threads++;
+
+ if (numStoresToWB(tid) > 0) {
+ DPRINTF(Writeback,"[tid:%i] Writing back stores. %i stores "
+ "available for Writeback.\n", tid, numStoresToWB(tid));
+ }
+
+ thread[tid].writebackStores();
+ }
+}
+
+template<class Impl>
+bool
+LSQ<Impl>::violation()
+{
+ /* Answers: Does Anybody Have a Violation?*/
+ list<unsigned>::iterator active_threads = (*activeThreads).begin();
+
+ while (active_threads != (*activeThreads).end()) {
+ unsigned tid = *active_threads++;
+ if (thread[tid].violation())
+ return true;
+ }
+
+ return false;
+}
+
+template<class Impl>
+int
+LSQ<Impl>::getCount()
+{
+ unsigned total = 0;
+
+ list<unsigned>::iterator active_threads = (*activeThreads).begin();
+
+ while (active_threads != (*activeThreads).end()) {
+ unsigned tid = *active_threads++;
+ total += getCount(tid);
+ }
+
+ return total;
+}
+
+template<class Impl>
+int
+LSQ<Impl>::numLoads()
+{
+ unsigned total = 0;
+
+ list<unsigned>::iterator active_threads = (*activeThreads).begin();
+
+ while (active_threads != (*activeThreads).end()) {
+ unsigned tid = *active_threads++;
+ total += numLoads(tid);
+ }
+
+ return total;
+}
+
+template<class Impl>
+int
+LSQ<Impl>::numStores()
+{
+ unsigned total = 0;
+
+ list<unsigned>::iterator active_threads = (*activeThreads).begin();
+
+ while (active_threads != (*activeThreads).end()) {
+ unsigned tid = *active_threads++;
+ total += thread[tid].numStores();
+ }
+
+ return total;
+}
+
+template<class Impl>
+int
+LSQ<Impl>::numLoadsReady()
+{
+ unsigned total = 0;
+
+ list<unsigned>::iterator active_threads = (*activeThreads).begin();
+
+ while (active_threads != (*activeThreads).end()) {
+ unsigned tid = *active_threads++;
+ total += thread[tid].numLoadsReady();
+ }
+
+ return total;
+}
+
+template<class Impl>
+unsigned
+LSQ<Impl>::numFreeEntries()
+{
+ unsigned total = 0;
+
+ list<unsigned>::iterator active_threads = (*activeThreads).begin();
+
+ while (active_threads != (*activeThreads).end()) {
+ unsigned tid = *active_threads++;
+ total += thread[tid].numFreeEntries();
+ }
+
+ return total;
+}
+
+template<class Impl>
+unsigned
+LSQ<Impl>::numFreeEntries(unsigned tid)
+{
+ //if( lsqPolicy == Dynamic )
+ //return numFreeEntries();
+ //else
+ return thread[tid].numFreeEntries();
+}
+
+template<class Impl>
+bool
+LSQ<Impl>::isFull()
+{
+ list<unsigned>::iterator active_threads = (*activeThreads).begin();
+
+ while (active_threads != (*activeThreads).end()) {
+ unsigned tid = *active_threads++;
+ if (! (thread[tid].lqFull() || thread[tid].sqFull()) )
+ return false;
+ }
+
+ return true;
+}
+
+template<class Impl>
+bool
+LSQ<Impl>::isFull(unsigned tid)
+{
+ //@todo: Change to Calculate All Entries for
+ //Dynamic Policy
+ if( lsqPolicy == Dynamic )
+ return isFull();
+ else
+ return thread[tid].lqFull() || thread[tid].sqFull();
+}
+
+template<class Impl>
+bool
+LSQ<Impl>::lqFull()
+{
+ list<unsigned>::iterator active_threads = (*activeThreads).begin();
+
+ while (active_threads != (*activeThreads).end()) {
+ unsigned tid = *active_threads++;
+ if (!thread[tid].lqFull())
+ return false;
+ }
+
+ return true;
+}
+
+template<class Impl>
+bool
+LSQ<Impl>::lqFull(unsigned tid)
+{
+ //@todo: Change to Calculate All Entries for
+ //Dynamic Policy
+ if( lsqPolicy == Dynamic )
+ return lqFull();
+ else
+ return thread[tid].lqFull();
+}
+
+template<class Impl>
+bool
+LSQ<Impl>::sqFull()
+{
+ list<unsigned>::iterator active_threads = (*activeThreads).begin();
+
+ while (active_threads != (*activeThreads).end()) {
+ unsigned tid = *active_threads++;
+ if (!sqFull(tid))
+ return false;
+ }
+
+ return true;
+}
+
+template<class Impl>
+bool
+LSQ<Impl>::sqFull(unsigned tid)
+{
+ //@todo: Change to Calculate All Entries for
+ //Dynamic Policy
+ if( lsqPolicy == Dynamic )
+ return sqFull();
+ else
+ return thread[tid].sqFull();
+}
+
+template<class Impl>
+bool
+LSQ<Impl>::isStalled()
+{
+ list<unsigned>::iterator active_threads = (*activeThreads).begin();
+
+ while (active_threads != (*activeThreads).end()) {
+ unsigned tid = *active_threads++;
+ if (!thread[tid].isStalled())
+ return false;
+ }
+
+ return true;
+}
+
+template<class Impl>
+bool
+LSQ<Impl>::isStalled(unsigned tid)
+{
+ if( lsqPolicy == Dynamic )
+ return isStalled();
+ else
+ return thread[tid].isStalled();
+}
+
+template<class Impl>
+bool
+LSQ<Impl>::hasStoresToWB()
+{
+ list<unsigned>::iterator active_threads = (*activeThreads).begin();
+
+ while (active_threads != (*activeThreads).end()) {
+ unsigned tid = *active_threads++;
+ if (!hasStoresToWB(tid))
+ return false;
+ }
+
+ return true;
+}
+
+template<class Impl>
+bool
+LSQ<Impl>::willWB()
+{
+ list<unsigned>::iterator active_threads = (*activeThreads).begin();
+
+ while (active_threads != (*activeThreads).end()) {
+ unsigned tid = *active_threads++;
+ if (!willWB(tid))
+ return false;
+ }
+
+ return true;
+}
+
+template<class Impl>
+void
+LSQ<Impl>::dumpInsts()
+{
+ list<unsigned>::iterator active_threads = (*activeThreads).begin();
+
+ while (active_threads != (*activeThreads).end()) {
+ unsigned tid = *active_threads++;
+ thread[tid].dumpInsts();
+ }
+}
diff --git a/cpu/o3/lsq_unit.cc b/cpu/o3/lsq_unit.cc
new file mode 100644
index 000000000..dd29007bc
--- /dev/null
+++ b/cpu/o3/lsq_unit.cc
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_cpu.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/lsq_unit_impl.hh"
+
+// Force the instantiation of LDSTQ for all the implementations we care about.
+template class LSQUnit<AlphaSimpleImpl>;
+
diff --git a/cpu/o3/lsq_unit.hh b/cpu/o3/lsq_unit.hh
new file mode 100644
index 000000000..942b4583d
--- /dev/null
+++ b/cpu/o3/lsq_unit.hh
@@ -0,0 +1,632 @@
+/*
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_O3_LSQ_UNIT_HH__
+#define __CPU_O3_LSQ_UNIT_HH__
+
+#include <algorithm>
+#include <map>
+#include <queue>
+
+#include "arch/faults.hh"
+#include "config/full_system.hh"
+#include "base/hashmap.hh"
+#include "cpu/inst_seq.hh"
+#include "mem/mem_interface.hh"
+//#include "mem/page_table.hh"
+//#include "sim/debug.hh"
+//#include "sim/sim_object.hh"
+
+/**
+ * Class that implements the actual LQ and SQ for each specific
+ * thread. Both are circular queues; load entries are freed upon
+ * committing, while store entries are freed once they writeback. The
+ * LSQUnit tracks if there are memory ordering violations, and also
+ * detects partial load to store forwarding cases (a store only has
+ * part of a load's data) that requires the load to wait until the
+ * store writes back. In the former case it holds onto the instruction
+ * until the dependence unit looks at it, and in the latter it stalls
+ * the LSQ until the store writes back. At that point the load is
+ * replayed.
+ */
+template <class Impl>
+class LSQUnit {
+ protected:
+ typedef TheISA::IntReg IntReg;
+ public:
+ typedef typename Impl::Params Params;
+ typedef typename Impl::FullCPU FullCPU;
+ typedef typename Impl::DynInstPtr DynInstPtr;
+ typedef typename Impl::CPUPol::IEW IEW;
+ typedef typename Impl::CPUPol::IssueStruct IssueStruct;
+
+ private:
+ class StoreCompletionEvent : public Event {
+ public:
+ /** Constructs a store completion event. */
+ StoreCompletionEvent(int store_idx, Event *wb_event, LSQUnit *lsq_ptr);
+
+ /** Processes the store completion event. */
+ void process();
+
+ /** Returns the description of this event. */
+ const char *description();
+
+ /** The writeback event for the store. Needed for store
+ * conditionals.
+ */
+ Event *wbEvent;
+
+ private:
+ /** The store index of the store being written back. */
+ int storeIdx;
+ private:
+ /** The pointer to the LSQ unit that issued the store. */
+ LSQUnit<Impl> *lsqPtr;
+ };
+
+ public:
+ /** Constructs an LSQ unit. init() must be called prior to use. */
+ LSQUnit();
+
+ /** Initializes the LSQ unit with the specified number of entries. */
+ void init(Params *params, unsigned maxLQEntries,
+ unsigned maxSQEntries, unsigned id);
+
+ /** Returns the name of the LSQ unit. */
+ std::string name() const;
+
+ /** Sets the CPU pointer. */
+ void setCPU(FullCPU *cpu_ptr)
+ { cpu = cpu_ptr; }
+
+ /** Sets the IEW stage pointer. */
+ void setIEW(IEW *iew_ptr)
+ { iewStage = iew_ptr; }
+
+ /** Sets the page table pointer. */
+// void setPageTable(PageTable *pt_ptr);
+
+ void switchOut();
+
+ void takeOverFrom();
+
+ bool isSwitchedOut() { return switchedOut; }
+
+ /** Ticks the LSQ unit, which in this case only resets the number of
+ * used cache ports.
+ * @todo: Move the number of used ports up to the LSQ level so it can
+ * be shared by all LSQ units.
+ */
+ void tick() { usedPorts = 0; }
+
+ /** Inserts an instruction. */
+ void insert(DynInstPtr &inst);
+ /** Inserts a load instruction. */
+ void insertLoad(DynInstPtr &load_inst);
+ /** Inserts a store instruction. */
+ void insertStore(DynInstPtr &store_inst);
+
+ /** Executes a load instruction. */
+ Fault executeLoad(DynInstPtr &inst);
+
+ Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; }
+ /** Executes a store instruction. */
+ Fault executeStore(DynInstPtr &inst);
+
+ /** Commits the head load. */
+ void commitLoad();
+ /** Commits loads older than a specific sequence number. */
+ void commitLoads(InstSeqNum &youngest_inst);
+
+ /** Commits stores older than a specific sequence number. */
+ void commitStores(InstSeqNum &youngest_inst);
+
+ /** Writes back stores. */
+ void writebackStores();
+
+ // @todo: Include stats in the LSQ unit.
+ //void regStats();
+
+ /** Clears all the entries in the LQ. */
+ void clearLQ();
+
+ /** Clears all the entries in the SQ. */
+ void clearSQ();
+
+ /** Resizes the LQ to a given size. */
+ void resizeLQ(unsigned size);
+
+ /** Resizes the SQ to a given size. */
+ void resizeSQ(unsigned size);
+
+ /** Squashes all instructions younger than a specific sequence number. */
+ void squash(const InstSeqNum &squashed_num);
+
+ /** Returns if there is a memory ordering violation. Value is reset upon
+ * call to getMemDepViolator().
+ */
+ bool violation() { return memDepViolator; }
+
+ /** Returns the memory ordering violator. */
+ DynInstPtr getMemDepViolator();
+
+ /** Returns if a load became blocked due to the memory system. */
+ bool loadBlocked()
+ { return isLoadBlocked; }
+
+ void clearLoadBlocked()
+ { isLoadBlocked = false; }
+
+ bool isLoadBlockedHandled()
+ { return loadBlockedHandled; }
+
+ void setLoadBlockedHandled()
+ { loadBlockedHandled = true; }
+
+ /** Returns the number of free entries (min of free LQ and SQ entries). */
+ unsigned numFreeEntries();
+
+ /** Returns the number of loads ready to execute. */
+ int numLoadsReady();
+
+ /** Returns the number of loads in the LQ. */
+ int numLoads() { return loads; }
+
+ /** Returns the number of stores in the SQ. */
+ int numStores() { return stores; }
+
+ /** Returns if either the LQ or SQ is full. */
+ bool isFull() { return lqFull() || sqFull(); }
+
+ /** Returns if the LQ is full. */
+ bool lqFull() { return loads >= (LQEntries - 1); }
+
+ /** Returns if the SQ is full. */
+ bool sqFull() { return stores >= (SQEntries - 1); }
+
+ /** Returns the number of instructions in the LSQ. */
+ unsigned getCount() { return loads + stores; }
+
+ /** Returns if there are any stores to writeback. */
+ bool hasStoresToWB() { return storesToWB; }
+
+ /** Returns the number of stores to writeback. */
+ int numStoresToWB() { return storesToWB; }
+
+ /** Returns if the LSQ unit will writeback on this cycle. */
+ bool willWB() { return storeQueue[storeWBIdx].canWB &&
+ !storeQueue[storeWBIdx].completed &&
+ !dcacheInterface->isBlocked(); }
+
+ private:
+ /** Completes the store at the specified index. */
+ void completeStore(int store_idx);
+
+ /** Increments the given store index (circular queue). */
+ inline void incrStIdx(int &store_idx);
+ /** Decrements the given store index (circular queue). */
+ inline void decrStIdx(int &store_idx);
+ /** Increments the given load index (circular queue). */
+ inline void incrLdIdx(int &load_idx);
+ /** Decrements the given load index (circular queue). */
+ inline void decrLdIdx(int &load_idx);
+
+ public:
+ /** Debugging function to dump instructions in the LSQ. */
+ void dumpInsts();
+
+ private:
+ /** Pointer to the CPU. */
+ FullCPU *cpu;
+
+ /** Pointer to the IEW stage. */
+ IEW *iewStage;
+
+ /** Pointer to the D-cache. */
+ MemInterface *dcacheInterface;
+
+ /** Pointer to the page table. */
+// PageTable *pTable;
+
+ public:
+ struct SQEntry {
+ /** Constructs an empty store queue entry. */
+ SQEntry()
+ : inst(NULL), req(NULL), size(0), data(0),
+ canWB(0), committed(0), completed(0)
+ { }
+
+ /** Constructs a store queue entry for a given instruction. */
+ SQEntry(DynInstPtr &_inst)
+ : inst(_inst), req(NULL), size(0), data(0),
+ canWB(0), committed(0), completed(0)
+ { }
+
+ /** The store instruction. */
+ DynInstPtr inst;
+ /** The memory request for the store. */
+ MemReqPtr req;
+ /** The size of the store. */
+ int size;
+ /** The store data. */
+ IntReg data;
+ /** Whether or not the store can writeback. */
+ bool canWB;
+ /** Whether or not the store is committed. */
+ bool committed;
+ /** Whether or not the store is completed. */
+ bool completed;
+ };
+
+ private:
+ /** The LSQUnit thread id. */
+ unsigned lsqID;
+
+ /** The store queue. */
+ std::vector<SQEntry> storeQueue;
+
+ /** The load queue. */
+ std::vector<DynInstPtr> loadQueue;
+
+ /** The number of LQ entries, plus a sentinel entry (circular queue).
+ * @todo: Consider having var that records the true number of LQ entries.
+ */
+ unsigned LQEntries;
+ /** The number of SQ entries, plus a sentinel entry (circular queue).
+ * @todo: Consider having var that records the true number of SQ entries.
+ */
+ unsigned SQEntries;
+
+ /** The number of load instructions in the LQ. */
+ int loads;
+ /** The number of store instructions in the SQ. */
+ int stores;
+ /** The number of store instructions in the SQ waiting to writeback. */
+ int storesToWB;
+
+ /** The index of the head instruction in the LQ. */
+ int loadHead;
+ /** The index of the tail instruction in the LQ. */
+ int loadTail;
+
+ /** The index of the head instruction in the SQ. */
+ int storeHead;
+ /** The index of the first instruction that may be ready to be
+ * written back, and has not yet been written back.
+ */
+ int storeWBIdx;
+ /** The index of the tail instruction in the SQ. */
+ int storeTail;
+
+ /// @todo Consider moving to a more advanced model with write vs read ports
+ /** The number of cache ports available each cycle. */
+ int cachePorts;
+
+ /** The number of used cache ports in this cycle. */
+ int usedPorts;
+
+ bool switchedOut;
+
+ //list<InstSeqNum> mshrSeqNums;
+
+ /** Wire to read information from the issue stage time queue. */
+ typename TimeBuffer<IssueStruct>::wire fromIssue;
+
+ /** Whether or not the LSQ is stalled. */
+ bool stalled;
+ /** The store that causes the stall due to partial store to load
+ * forwarding.
+ */
+ InstSeqNum stallingStoreIsn;
+ /** The index of the above store. */
+ int stallingLoadIdx;
+
+ /** Whether or not a load is blocked due to the memory system. */
+ bool isLoadBlocked;
+
+ bool loadBlockedHandled;
+
+ InstSeqNum blockedLoadSeqNum;
+
+ /** The oldest load that caused a memory ordering violation. */
+ DynInstPtr memDepViolator;
+
+ // Will also need how many read/write ports the Dcache has. Or keep track
+ // of that in stage that is one level up, and only call executeLoad/Store
+ // the appropriate number of times.
+/*
+ // total number of loads forwaded from LSQ stores
+ Stats::Vector<> lsq_forw_loads;
+
+ // total number of loads ignored due to invalid addresses
+ Stats::Vector<> inv_addr_loads;
+
+ // total number of software prefetches ignored due to invalid addresses
+ Stats::Vector<> inv_addr_swpfs;
+
+ // total non-speculative bogus addresses seen (debug var)
+ Counter sim_invalid_addrs;
+ Stats::Vector<> fu_busy; //cumulative fu busy
+
+ // ready loads blocked due to memory disambiguation
+ Stats::Vector<> lsq_blocked_loads;
+
+ Stats::Scalar<> lsqInversion;
+*/
+ public:
+ /** Executes the load at the given index. */
+ template <class T>
+ Fault read(MemReqPtr &req, T &data, int load_idx);
+
+ /** Executes the store at the given index. */
+ template <class T>
+ Fault write(MemReqPtr &req, T &data, int store_idx);
+
+ /** Returns the index of the head load instruction. */
+ int getLoadHead() { return loadHead; }
+ /** Returns the sequence number of the head load instruction. */
+ InstSeqNum getLoadHeadSeqNum()
+ {
+ if (loadQueue[loadHead]) {
+ return loadQueue[loadHead]->seqNum;
+ } else {
+ return 0;
+ }
+
+ }
+
+ /** Returns the index of the head store instruction. */
+ int getStoreHead() { return storeHead; }
+ /** Returns the sequence number of the head store instruction. */
+ InstSeqNum getStoreHeadSeqNum()
+ {
+ if (storeQueue[storeHead].inst) {
+ return storeQueue[storeHead].inst->seqNum;
+ } else {
+ return 0;
+ }
+
+ }
+
+ /** Returns whether or not the LSQ unit is stalled. */
+ bool isStalled() { return stalled; }
+};
+
+template <class Impl>
+template <class T>
+Fault
+LSQUnit<Impl>::read(MemReqPtr &req, T &data, int load_idx)
+{
+ assert(loadQueue[load_idx]);
+
+ assert(!loadQueue[load_idx]->isExecuted());
+
+ // Make sure this isn't an uncacheable access
+ // A bit of a hackish way to get uncached accesses to work only if they're
+ // at the head of the LSQ and are ready to commit (at the head of the ROB
+ // too).
+ if (req->flags & UNCACHEABLE &&
+ (load_idx != loadHead || !loadQueue[load_idx]->reachedCommit)) {
+ iewStage->rescheduleMemInst(loadQueue[load_idx]);
+ return TheISA::genMachineCheckFault();
+ }
+
+ // Check the SQ for any previous stores that might lead to forwarding
+ int store_idx = loadQueue[load_idx]->sqIdx;
+
+ int store_size = 0;
+
+ DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, "
+ "storeHead: %i addr: %#x\n",
+ load_idx, store_idx, storeHead, req->paddr);
+
+#if 0
+ if (req->flags & LOCKED) {
+ cpu->lockAddr = req->paddr;
+ cpu->lockFlag = true;
+ }
+#endif
+ req->cmd = Read;
+ assert(!req->completionEvent);
+ req->completionEvent = NULL;
+ req->time = curTick;
+
+ while (store_idx != -1) {
+ // End once we've reached the top of the LSQ
+ if (store_idx == storeWBIdx) {
+ break;
+ }
+
+ // Move the index to one younger
+ if (--store_idx < 0)
+ store_idx += SQEntries;
+
+ assert(storeQueue[store_idx].inst);
+
+ store_size = storeQueue[store_idx].size;
+
+ if (store_size == 0)
+ continue;
+
+ // Check if the store data is within the lower and upper bounds of
+ // addresses that the request needs.
+ bool store_has_lower_limit =
+ req->vaddr >= storeQueue[store_idx].inst->effAddr;
+ bool store_has_upper_limit =
+ (req->vaddr + req->size) <= (storeQueue[store_idx].inst->effAddr +
+ store_size);
+ bool lower_load_has_store_part =
+ req->vaddr < (storeQueue[store_idx].inst->effAddr +
+ store_size);
+ bool upper_load_has_store_part =
+ (req->vaddr + req->size) > storeQueue[store_idx].inst->effAddr;
+
+ // If the store's data has all of the data needed, we can forward.
+ if (store_has_lower_limit && store_has_upper_limit) {
+ // Get shift amount for offset into the store's data.
+ int shift_amt = req->vaddr & (store_size - 1);
+ // @todo: Magic number, assumes byte addressing
+ shift_amt = shift_amt << 3;
+
+ // Cast this to type T?
+ data = storeQueue[store_idx].data >> shift_amt;
+
+ assert(!req->data);
+ req->data = new uint8_t[64];
+
+ memcpy(req->data, &data, req->size);
+
+ DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
+ "addr %#x, data %#x\n",
+ store_idx, req->vaddr, *(req->data));
+
+ typename IEW::LdWritebackEvent *wb =
+ new typename IEW::LdWritebackEvent(loadQueue[load_idx],
+ iewStage);
+
+ // We'll say this has a 1 cycle load-store forwarding latency
+ // for now.
+ // @todo: Need to make this a parameter.
+ wb->schedule(curTick);
+
+ // Should keep track of stat for forwarded data
+ return NoFault;
+ } else if ((store_has_lower_limit && lower_load_has_store_part) ||
+ (store_has_upper_limit && upper_load_has_store_part) ||
+ (lower_load_has_store_part && upper_load_has_store_part)) {
+ // This is the partial store-load forwarding case where a store
+ // has only part of the load's data.
+
+ // If it's already been written back, then don't worry about
+ // stalling on it.
+ if (storeQueue[store_idx].completed) {
+ continue;
+ }
+
+ // Must stall load and force it to retry, so long as it's the oldest
+ // load that needs to do so.
+ if (!stalled ||
+ (stalled &&
+ loadQueue[load_idx]->seqNum <
+ loadQueue[stallingLoadIdx]->seqNum)) {
+ stalled = true;
+ stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
+ stallingLoadIdx = load_idx;
+ }
+
+ // Tell IQ/mem dep unit that this instruction will need to be
+ // rescheduled eventually
+ iewStage->rescheduleMemInst(loadQueue[load_idx]);
+
+ // Do not generate a writeback event as this instruction is not
+ // complete.
+ DPRINTF(LSQUnit, "Load-store forwarding mis-match. "
+ "Store idx %i to load addr %#x\n",
+ store_idx, req->vaddr);
+
+ return NoFault;
+ }
+ }
+
+ // If there's no forwarding case, then go access memory
+ DynInstPtr inst = loadQueue[load_idx];
+
+ DPRINTF(LSQUnit, "Doing functional access for inst [sn:%lli] PC %#x\n",
+ loadQueue[load_idx]->seqNum, loadQueue[load_idx]->readPC());
+
+ assert(!req->data);
+ req->data = new uint8_t[64];
+ Fault fault = cpu->read(req, data);
+ memcpy(req->data, &data, sizeof(T));
+
+ ++usedPorts;
+
+ // if we have a cache, do cache access too
+ if (fault == NoFault && dcacheInterface) {
+ if (dcacheInterface->isBlocked()) {
+ // There's an older load that's already going to squash.
+ if (isLoadBlocked && blockedLoadSeqNum < inst->seqNum)
+ return NoFault;
+
+ // Record that the load was blocked due to memory. This
+ // load will squash all instructions after it, be
+ // refetched, and re-executed.
+ isLoadBlocked = true;
+ loadBlockedHandled = false;
+ blockedLoadSeqNum = inst->seqNum;
+ // No fault occurred, even though the interface is blocked.
+ return NoFault;
+ }
+
+ DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n",
+ loadQueue[load_idx]->readPC());
+
+ assert(!req->completionEvent);
+ req->completionEvent =
+ new typename IEW::LdWritebackEvent(loadQueue[load_idx], iewStage);
+ MemAccessResult result = dcacheInterface->access(req);
+
+ assert(dcacheInterface->doEvents());
+
+ if (result != MA_HIT) {
+ DPRINTF(LSQUnit, "LSQUnit: D-cache miss!\n");
+ DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
+ inst->seqNum);
+ } else {
+ DPRINTF(LSQUnit, "LSQUnit: D-cache hit!\n");
+ DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n",
+ inst->seqNum);
+ }
+ }
+
+ return fault;
+}
+
+template <class Impl>
+template <class T>
+Fault
+LSQUnit<Impl>::write(MemReqPtr &req, T &data, int store_idx)
+{
+ assert(storeQueue[store_idx].inst);
+
+ DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x"
+ " | storeHead:%i [sn:%i]\n",
+ store_idx, req->paddr, data, storeHead,
+ storeQueue[store_idx].inst->seqNum);
+
+ storeQueue[store_idx].req = req;
+ storeQueue[store_idx].size = sizeof(T);
+ storeQueue[store_idx].data = data;
+
+ // This function only writes the data to the store queue, so no fault
+ // can happen here.
+ return NoFault;
+}
+
+#endif // __CPU_O3_LSQ_UNIT_HH__
diff --git a/cpu/o3/lsq_unit_impl.hh b/cpu/o3/lsq_unit_impl.hh
new file mode 100644
index 000000000..7974ddaad
--- /dev/null
+++ b/cpu/o3/lsq_unit_impl.hh
@@ -0,0 +1,873 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu/checker/cpu.hh"
+#include "cpu/o3/lsq_unit.hh"
+#include "base/str.hh"
+
+template <class Impl>
+LSQUnit<Impl>::StoreCompletionEvent::StoreCompletionEvent(int store_idx,
+ Event *wb_event,
+ LSQUnit<Impl> *lsq_ptr)
+ : Event(&mainEventQueue),
+ wbEvent(wb_event),
+ storeIdx(store_idx),
+ lsqPtr(lsq_ptr)
+{
+ this->setFlags(Event::AutoDelete);
+}
+
+template <class Impl>
+void
+LSQUnit<Impl>::StoreCompletionEvent::process()
+{
+ DPRINTF(LSQ, "Cache miss complete for store idx:%i\n", storeIdx);
+ DPRINTF(Activity, "Activity: st writeback event idx:%i\n", storeIdx);
+
+ //lsqPtr->removeMSHR(lsqPtr->storeQueue[storeIdx].inst->seqNum);
+
+ if (lsqPtr->isSwitchedOut())
+ return;
+
+ lsqPtr->cpu->wakeCPU();
+ if (wbEvent)
+ wbEvent->process();
+ lsqPtr->completeStore(storeIdx);
+}
+
+template <class Impl>
+const char *
+LSQUnit<Impl>::StoreCompletionEvent::description()
+{
+ return "LSQ store completion event";
+}
+
+template <class Impl>
+LSQUnit<Impl>::LSQUnit()
+ : loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false),
+ loadBlockedHandled(false)
+{
+}
+
+template<class Impl>
+void
+LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries,
+ unsigned maxSQEntries, unsigned id)
+
+{
+ DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
+
+ switchedOut = false;
+
+ lsqID = id;
+
+ // Add 1 for the sentinel entry (they are circular queues).
+ LQEntries = maxLQEntries + 1;
+ SQEntries = maxSQEntries + 1;
+
+ loadQueue.resize(LQEntries);
+ storeQueue.resize(SQEntries);
+
+ loadHead = loadTail = 0;
+
+ storeHead = storeWBIdx = storeTail = 0;
+
+ usedPorts = 0;
+ cachePorts = params->cachePorts;
+
+ dcacheInterface = params->dcacheInterface;
+
+ memDepViolator = NULL;
+
+ blockedLoadSeqNum = 0;
+}
+
+template<class Impl>
+std::string
+LSQUnit<Impl>::name() const
+{
+ if (Impl::MaxThreads == 1) {
+ return iewStage->name() + ".lsq";
+ } else {
+ return iewStage->name() + ".lsq.thread." + to_string(lsqID);
+ }
+}
+
+template<class Impl>
+void
+LSQUnit<Impl>::clearLQ()
+{
+ loadQueue.clear();
+}
+
+template<class Impl>
+void
+LSQUnit<Impl>::clearSQ()
+{
+ storeQueue.clear();
+}
+
+#if 0
+template<class Impl>
+void
+LSQUnit<Impl>::setPageTable(PageTable *pt_ptr)
+{
+ DPRINTF(LSQUnit, "Setting the page table pointer.\n");
+ pTable = pt_ptr;
+}
+#endif
+
+template<class Impl>
+void
+LSQUnit<Impl>::switchOut()
+{
+ switchedOut = true;
+ for (int i = 0; i < loadQueue.size(); ++i)
+ loadQueue[i] = NULL;
+
+ assert(storesToWB == 0);
+
+ while (storesToWB > 0 &&
+ storeWBIdx != storeTail &&
+ storeQueue[storeWBIdx].inst &&
+ storeQueue[storeWBIdx].canWB) {
+
+ if (storeQueue[storeWBIdx].size == 0 ||
+ storeQueue[storeWBIdx].inst->isDataPrefetch() ||
+ storeQueue[storeWBIdx].committed ||
+ storeQueue[storeWBIdx].req->flags & LOCKED) {
+ incrStIdx(storeWBIdx);
+
+ continue;
+ }
+
+ assert(storeQueue[storeWBIdx].req);
+ assert(!storeQueue[storeWBIdx].committed);
+
+ MemReqPtr req = storeQueue[storeWBIdx].req;
+ storeQueue[storeWBIdx].committed = true;
+
+ req->cmd = Write;
+ req->completionEvent = NULL;
+ req->time = curTick;
+ assert(!req->data);
+ req->data = new uint8_t[64];
+ memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size);
+
+ DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
+ "to Addr:%#x, data:%#x [sn:%lli]\n",
+ storeWBIdx,storeQueue[storeWBIdx].inst->readPC(),
+ req->paddr, *(req->data),
+ storeQueue[storeWBIdx].inst->seqNum);
+
+ switch(storeQueue[storeWBIdx].size) {
+ case 1:
+ cpu->write(req, (uint8_t &)storeQueue[storeWBIdx].data);
+ break;
+ case 2:
+ cpu->write(req, (uint16_t &)storeQueue[storeWBIdx].data);
+ break;
+ case 4:
+ cpu->write(req, (uint32_t &)storeQueue[storeWBIdx].data);
+ break;
+ case 8:
+ cpu->write(req, (uint64_t &)storeQueue[storeWBIdx].data);
+ break;
+ default:
+ panic("Unexpected store size!\n");
+ }
+ incrStIdx(storeWBIdx);
+ }
+}
+
+template<class Impl>
+void
+LSQUnit<Impl>::takeOverFrom()
+{
+ switchedOut = false;
+ loads = stores = storesToWB = 0;
+
+ loadHead = loadTail = 0;
+
+ storeHead = storeWBIdx = storeTail = 0;
+
+ usedPorts = 0;
+
+ memDepViolator = NULL;
+
+ blockedLoadSeqNum = 0;
+
+ stalled = false;
+ isLoadBlocked = false;
+ loadBlockedHandled = false;
+}
+
+template<class Impl>
+void
+LSQUnit<Impl>::resizeLQ(unsigned size)
+{
+ unsigned size_plus_sentinel = size + 1;
+ assert(size_plus_sentinel >= LQEntries);
+
+ if (size_plus_sentinel > LQEntries) {
+ while (size_plus_sentinel > loadQueue.size()) {
+ DynInstPtr dummy;
+ loadQueue.push_back(dummy);
+ LQEntries++;
+ }
+ } else {
+ LQEntries = size_plus_sentinel;
+ }
+
+}
+
+template<class Impl>
+void
+LSQUnit<Impl>::resizeSQ(unsigned size)
+{
+ unsigned size_plus_sentinel = size + 1;
+ if (size_plus_sentinel > SQEntries) {
+ while (size_plus_sentinel > storeQueue.size()) {
+ SQEntry dummy;
+ storeQueue.push_back(dummy);
+ SQEntries++;
+ }
+ } else {
+ SQEntries = size_plus_sentinel;
+ }
+}
+
+template <class Impl>
+void
+LSQUnit<Impl>::insert(DynInstPtr &inst)
+{
+ assert(inst->isMemRef());
+
+ assert(inst->isLoad() || inst->isStore());
+
+ if (inst->isLoad()) {
+ insertLoad(inst);
+ } else {
+ insertStore(inst);
+ }
+
+ inst->setInLSQ();
+}
+
+template <class Impl>
+void
+LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
+{
+ assert((loadTail + 1) % LQEntries != loadHead);
+ assert(loads < LQEntries);
+
+ DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
+ load_inst->readPC(), loadTail, load_inst->seqNum);
+
+ load_inst->lqIdx = loadTail;
+
+ if (stores == 0) {
+ load_inst->sqIdx = -1;
+ } else {
+ load_inst->sqIdx = storeTail;
+ }
+
+ loadQueue[loadTail] = load_inst;
+
+ incrLdIdx(loadTail);
+
+ ++loads;
+}
+
+template <class Impl>
+void
+LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
+{
+ // Make sure it is not full before inserting an instruction.
+ assert((storeTail + 1) % SQEntries != storeHead);
+ assert(stores < SQEntries);
+
+ DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
+ store_inst->readPC(), storeTail, store_inst->seqNum);
+
+ store_inst->sqIdx = storeTail;
+ store_inst->lqIdx = loadTail;
+
+ storeQueue[storeTail] = SQEntry(store_inst);
+
+ incrStIdx(storeTail);
+
+ ++stores;
+}
+
+template <class Impl>
+typename Impl::DynInstPtr
+LSQUnit<Impl>::getMemDepViolator()
+{
+ DynInstPtr temp = memDepViolator;
+
+ memDepViolator = NULL;
+
+ return temp;
+}
+
+template <class Impl>
+unsigned
+LSQUnit<Impl>::numFreeEntries()
+{
+ unsigned free_lq_entries = LQEntries - loads;
+ unsigned free_sq_entries = SQEntries - stores;
+
+ // Both the LQ and SQ entries have an extra dummy entry to differentiate
+ // empty/full conditions. Subtract 1 from the free entries.
+ if (free_lq_entries < free_sq_entries) {
+ return free_lq_entries - 1;
+ } else {
+ return free_sq_entries - 1;
+ }
+}
+
+template <class Impl>
+int
+LSQUnit<Impl>::numLoadsReady()
+{
+ int load_idx = loadHead;
+ int retval = 0;
+
+ while (load_idx != loadTail) {
+ assert(loadQueue[load_idx]);
+
+ if (loadQueue[load_idx]->readyToIssue()) {
+ ++retval;
+ }
+ }
+
+ return retval;
+}
+
+template <class Impl>
+Fault
+LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
+{
+ // Execute a specific load.
+ Fault load_fault = NoFault;
+
+ DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
+ inst->readPC(),inst->seqNum);
+
+// load_fault = inst->initiateAcc();
+ load_fault = inst->execute();
+
+ // If the instruction faulted, then we need to send it along to commit
+ // without the instruction completing.
+ if (load_fault != NoFault) {
+ // Send this instruction to commit, also make sure iew stage
+ // realizes there is activity.
+ iewStage->instToCommit(inst);
+ iewStage->activityThisCycle();
+ }
+
+ return load_fault;
+}
+
+template <class Impl>
+Fault
+LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
+{
+ using namespace TheISA;
+ // Make sure that a store exists.
+ assert(stores != 0);
+
+ int store_idx = store_inst->sqIdx;
+
+ DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
+ store_inst->readPC(), store_inst->seqNum);
+
+ // Check the recently completed loads to see if any match this store's
+ // address. If so, then we have a memory ordering violation.
+ int load_idx = store_inst->lqIdx;
+
+ Fault store_fault = store_inst->initiateAcc();
+// Fault store_fault = store_inst->execute();
+
+ if (storeQueue[store_idx].size == 0) {
+ DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
+ store_inst->readPC(),store_inst->seqNum);
+
+ return store_fault;
+ }
+
+ assert(store_fault == NoFault);
+
+ if (store_inst->isStoreConditional()) {
+ // Store conditionals need to set themselves as able to
+ // writeback if we haven't had a fault by here.
+ storeQueue[store_idx].canWB = true;
+
+ ++storesToWB;
+ }
+
+ if (!memDepViolator) {
+ while (load_idx != loadTail) {
+ // Really only need to check loads that have actually executed
+ // It's safe to check all loads because effAddr is set to
+ // InvalAddr when the dyn inst is created.
+
+ // @todo: For now this is extra conservative, detecting a
+ // violation if the addresses match assuming all accesses
+ // are quad word accesses.
+
+ // @todo: Fix this, magic number being used here
+ if ((loadQueue[load_idx]->effAddr >> 8) ==
+ (store_inst->effAddr >> 8)) {
+ // A load incorrectly passed this store. Squash and refetch.
+ // For now return a fault to show that it was unsuccessful.
+ memDepViolator = loadQueue[load_idx];
+
+ return genMachineCheckFault();
+ }
+
+ incrLdIdx(load_idx);
+ }
+
+ // If we've reached this point, there was no violation.
+ memDepViolator = NULL;
+ }
+
+ return store_fault;
+}
+
+template <class Impl>
+void
+LSQUnit<Impl>::commitLoad()
+{
+ assert(loadQueue[loadHead]);
+
+ DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
+ loadQueue[loadHead]->readPC());
+
+
+ loadQueue[loadHead] = NULL;
+
+ incrLdIdx(loadHead);
+
+ --loads;
+}
+
+template <class Impl>
+void
+LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
+{
+ assert(loads == 0 || loadQueue[loadHead]);
+
+ while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
+ commitLoad();
+ }
+}
+
+template <class Impl>
+void
+LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
+{
+ assert(stores == 0 || storeQueue[storeHead].inst);
+
+ int store_idx = storeHead;
+
+ while (store_idx != storeTail) {
+ assert(storeQueue[store_idx].inst);
+ // Mark any stores that are now committed and have not yet
+ // been marked as able to write back.
+ if (!storeQueue[store_idx].canWB) {
+ if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
+ break;
+ }
+ DPRINTF(LSQUnit, "Marking store as able to write back, PC "
+ "%#x [sn:%lli]\n",
+ storeQueue[store_idx].inst->readPC(),
+ storeQueue[store_idx].inst->seqNum);
+
+ storeQueue[store_idx].canWB = true;
+
+ ++storesToWB;
+ }
+
+ incrStIdx(store_idx);
+ }
+}
+
+template <class Impl>
+void
+LSQUnit<Impl>::writebackStores()
+{
+ while (storesToWB > 0 &&
+ storeWBIdx != storeTail &&
+ storeQueue[storeWBIdx].inst &&
+ storeQueue[storeWBIdx].canWB &&
+ usedPorts < cachePorts) {
+
+ // Store didn't write any data so no need to write it back to
+ // memory.
+ if (storeQueue[storeWBIdx].size == 0) {
+ completeStore(storeWBIdx);
+
+ incrStIdx(storeWBIdx);
+
+ continue;
+ }
+
+ if (dcacheInterface && dcacheInterface->isBlocked()) {
+ DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
+ " is blocked!\n");
+ break;
+ }
+
+ ++usedPorts;
+
+ if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
+ incrStIdx(storeWBIdx);
+
+ continue;
+ }
+
+ assert(storeQueue[storeWBIdx].req);
+ assert(!storeQueue[storeWBIdx].committed);
+
+ MemReqPtr req = storeQueue[storeWBIdx].req;
+ storeQueue[storeWBIdx].committed = true;
+
+ req->cmd = Write;
+ req->completionEvent = NULL;
+ req->time = curTick;
+ assert(!req->data);
+ req->data = new uint8_t[64];
+ memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size);
+
+ DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
+ "to Addr:%#x, data:%#x [sn:%lli]\n",
+ storeWBIdx,storeQueue[storeWBIdx].inst->readPC(),
+ req->paddr, *(req->data),
+ storeQueue[storeWBIdx].inst->seqNum);
+
+ switch(storeQueue[storeWBIdx].size) {
+ case 1:
+ cpu->write(req, (uint8_t &)storeQueue[storeWBIdx].data);
+ break;
+ case 2:
+ cpu->write(req, (uint16_t &)storeQueue[storeWBIdx].data);
+ break;
+ case 4:
+ cpu->write(req, (uint32_t &)storeQueue[storeWBIdx].data);
+ break;
+ case 8:
+ cpu->write(req, (uint64_t &)storeQueue[storeWBIdx].data);
+ break;
+ default:
+ panic("Unexpected store size!\n");
+ }
+
+ // Stores other than store conditionals are completed at this
+ // time. Mark them as completed and, if we have a checker,
+ // tell it that the instruction is completed.
+ // @todo: Figure out what time I can say stores are complete in
+ // the timing memory.
+ if (!(req->flags & LOCKED)) {
+ storeQueue[storeWBIdx].inst->setCompleted();
+ if (cpu->checker) {
+ cpu->checker->tick(storeQueue[storeWBIdx].inst);
+ }
+ }
+
+ if (dcacheInterface) {
+ assert(!req->completionEvent);
+ StoreCompletionEvent *store_event = new
+ StoreCompletionEvent(storeWBIdx, NULL, this);
+ req->completionEvent = store_event;
+
+ MemAccessResult result = dcacheInterface->access(req);
+
+ if (isStalled() &&
+ storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
+ DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
+ "load idx:%i\n",
+ stallingStoreIsn, stallingLoadIdx);
+ stalled = false;
+ stallingStoreIsn = 0;
+ iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
+ }
+
+ typename IEW::LdWritebackEvent *wb = NULL;
+ if (req->flags & LOCKED) {
+ // Stx_C should not generate a system port transaction
+ // if it misses in the cache, but that might be hard
+ // to accomplish without explicit cache support.
+ wb = new typename
+ IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
+ iewStage);
+ store_event->wbEvent = wb;
+ }
+
+ if (result != MA_HIT && dcacheInterface->doEvents()) {
+ DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
+ storeWBIdx);
+
+ DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
+ storeQueue[storeWBIdx].inst->seqNum);
+
+ //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
+
+ //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
+
+ // @todo: Increment stat here.
+ } else {
+ DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
+ storeWBIdx);
+
+ DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
+ storeQueue[storeWBIdx].inst->seqNum);
+ }
+
+ incrStIdx(storeWBIdx);
+ } else {
+ panic("Must HAVE DCACHE!!!!!\n");
+ }
+ }
+
+ // Not sure this should set it to 0.
+ usedPorts = 0;
+
+ assert(stores >= 0 && storesToWB >= 0);
+}
+
+/*template <class Impl>
+void
+LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
+{
+ list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
+ mshrSeqNums.end(),
+ seqNum);
+
+ if (mshr_it != mshrSeqNums.end()) {
+ mshrSeqNums.erase(mshr_it);
+ DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
+ }
+}*/
+
+template <class Impl>
+void
+LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
+{
+ DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
+ "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
+
+ int load_idx = loadTail;
+ decrLdIdx(load_idx);
+
+ while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
+ DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
+ "[sn:%lli]\n",
+ loadQueue[load_idx]->readPC(),
+ loadQueue[load_idx]->seqNum);
+
+ if (isStalled() && load_idx == stallingLoadIdx) {
+ stalled = false;
+ stallingStoreIsn = 0;
+ stallingLoadIdx = 0;
+ }
+
+ // Clear the smart pointer to make sure it is decremented.
+ loadQueue[load_idx]->squashed = true;
+ loadQueue[load_idx] = NULL;
+ --loads;
+
+ // Inefficient!
+ loadTail = load_idx;
+
+ decrLdIdx(load_idx);
+ }
+
+ if (isLoadBlocked) {
+ if (squashed_num < blockedLoadSeqNum) {
+ isLoadBlocked = false;
+ loadBlockedHandled = false;
+ blockedLoadSeqNum = 0;
+ }
+ }
+
+ int store_idx = storeTail;
+ decrStIdx(store_idx);
+
+ while (stores != 0 &&
+ storeQueue[store_idx].inst->seqNum > squashed_num) {
+ // Instructions marked as can WB are already committed.
+ if (storeQueue[store_idx].canWB) {
+ break;
+ }
+
+ DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
+ "idx:%i [sn:%lli]\n",
+ storeQueue[store_idx].inst->readPC(),
+ store_idx, storeQueue[store_idx].inst->seqNum);
+
+ // I don't think this can happen. It should have been cleared
+ // by the stalling load.
+ if (isStalled() &&
+ storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
+ panic("Is stalled should have been cleared by stalling load!\n");
+ stalled = false;
+ stallingStoreIsn = 0;
+ }
+
+ // Clear the smart pointer to make sure it is decremented.
+ storeQueue[store_idx].inst->squashed = true;
+ storeQueue[store_idx].inst = NULL;
+ storeQueue[store_idx].canWB = 0;
+
+ if (storeQueue[store_idx].req) {
+ // There should not be a completion event if the store has
+ // not yet committed.
+ assert(!storeQueue[store_idx].req->completionEvent);
+ }
+
+ storeQueue[store_idx].req = NULL;
+ --stores;
+
+ // Inefficient!
+ storeTail = store_idx;
+
+ decrStIdx(store_idx);
+ }
+}
+
+template <class Impl>
+void
+LSQUnit<Impl>::completeStore(int store_idx)
+{
+ assert(storeQueue[store_idx].inst);
+ storeQueue[store_idx].completed = true;
+ --storesToWB;
+ // A bit conservative because a store completion may not free up entries,
+ // but hopefully avoids two store completions in one cycle from making
+ // the CPU tick twice.
+ cpu->activityThisCycle();
+
+ if (store_idx == storeHead) {
+ do {
+ incrStIdx(storeHead);
+
+ --stores;
+ } while (storeQueue[storeHead].completed &&
+ storeHead != storeTail);
+
+ iewStage->updateLSQNextCycle = true;
+ }
+
+ DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
+ "idx:%i\n",
+ storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
+
+ if (isStalled() &&
+ storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
+ DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
+ "load idx:%i\n",
+ stallingStoreIsn, stallingLoadIdx);
+ stalled = false;
+ stallingStoreIsn = 0;
+ iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
+ }
+
+ storeQueue[store_idx].inst->setCompleted();
+
+ // Tell the checker we've completed this instruction. Some stores
+ // may get reported twice to the checker, but the checker can
+ // handle that case.
+ if (cpu->checker) {
+ cpu->checker->tick(storeQueue[store_idx].inst);
+ }
+}
+
+template <class Impl>
+inline void
+LSQUnit<Impl>::incrStIdx(int &store_idx)
+{
+ if (++store_idx >= SQEntries)
+ store_idx = 0;
+}
+
+template <class Impl>
+inline void
+LSQUnit<Impl>::decrStIdx(int &store_idx)
+{
+ if (--store_idx < 0)
+ store_idx += SQEntries;
+}
+
+template <class Impl>
+inline void
+LSQUnit<Impl>::incrLdIdx(int &load_idx)
+{
+ if (++load_idx >= LQEntries)
+ load_idx = 0;
+}
+
+template <class Impl>
+inline void
+LSQUnit<Impl>::decrLdIdx(int &load_idx)
+{
+ if (--load_idx < 0)
+ load_idx += LQEntries;
+}
+
+template <class Impl>
+void
+LSQUnit<Impl>::dumpInsts()
+{
+ cprintf("Load store queue: Dumping instructions.\n");
+ cprintf("Load queue size: %i\n", loads);
+ cprintf("Load queue: ");
+
+ int load_idx = loadHead;
+
+ while (load_idx != loadTail && loadQueue[load_idx]) {
+ cprintf("%#x ", loadQueue[load_idx]->readPC());
+
+ incrLdIdx(load_idx);
+ }
+
+ cprintf("Store queue size: %i\n", stores);
+ cprintf("Store queue: ");
+
+ int store_idx = storeHead;
+
+ while (store_idx != storeTail && storeQueue[store_idx].inst) {
+ cprintf("%#x ", storeQueue[store_idx].inst->readPC());
+
+ incrStIdx(store_idx);
+ }
+
+ cprintf("\n");
+}
diff --git a/cpu/o3/scoreboard.cc b/cpu/o3/scoreboard.cc
new file mode 100644
index 000000000..b0e433620
--- /dev/null
+++ b/cpu/o3/scoreboard.cc
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu/o3/scoreboard.hh"
+
+Scoreboard::Scoreboard(unsigned activeThreads,
+ unsigned _numLogicalIntRegs,
+ unsigned _numPhysicalIntRegs,
+ unsigned _numLogicalFloatRegs,
+ unsigned _numPhysicalFloatRegs,
+ unsigned _numMiscRegs,
+ unsigned _zeroRegIdx)
+ : numLogicalIntRegs(_numLogicalIntRegs),
+ numPhysicalIntRegs(_numPhysicalIntRegs),
+ numLogicalFloatRegs(_numLogicalFloatRegs),
+ numPhysicalFloatRegs(_numPhysicalFloatRegs),
+ numMiscRegs(_numMiscRegs),
+ zeroRegIdx(_zeroRegIdx)
+{
+ //Get Register Sizes
+ numLogicalRegs = numLogicalIntRegs + numLogicalFloatRegs;
+ numPhysicalRegs = numPhysicalIntRegs + numPhysicalFloatRegs;
+
+ //Resize scoreboard appropriately
+ regScoreBoard.resize(numPhysicalRegs + (numMiscRegs * activeThreads));
+
+ //Initialize values
+ for (int i=0; i < numLogicalIntRegs * activeThreads; i++) {
+ regScoreBoard[i] = 1;
+ }
+
+ for (int i= numPhysicalIntRegs;
+ i < numPhysicalIntRegs + (numLogicalFloatRegs * activeThreads);
+ i++) {
+ regScoreBoard[i] = 1;
+ }
+
+ for (int i = numPhysicalRegs;
+ i < numPhysicalRegs + (numMiscRegs * activeThreads);
+ i++) {
+ regScoreBoard[i] = 1;
+ }
+}
+
+std::string
+Scoreboard::name() const
+{
+ return "cpu.scoreboard";
+}
+
+bool
+Scoreboard::getReg(PhysRegIndex phys_reg)
+{
+ // Always ready if int or fp zero reg.
+ if (phys_reg == zeroRegIdx ||
+ phys_reg == (zeroRegIdx + numPhysicalIntRegs)) {
+ return 1;
+ }
+
+ return regScoreBoard[phys_reg];
+}
+
+void
+Scoreboard::setReg(PhysRegIndex phys_reg)
+{
+ DPRINTF(Scoreboard, "Setting reg %i as ready\n", phys_reg);
+
+ regScoreBoard[phys_reg] = 1;
+}
+
+void
+Scoreboard::unsetReg(PhysRegIndex ready_reg)
+{
+ if (ready_reg == zeroRegIdx ||
+ ready_reg == (zeroRegIdx + numPhysicalIntRegs)) {
+ // Don't do anything if int or fp zero reg.
+ return;
+ }
+
+ regScoreBoard[ready_reg] = 0;
+}
diff --git a/cpu/o3/scoreboard.hh b/cpu/o3/scoreboard.hh
new file mode 100644
index 000000000..77f2cf157
--- /dev/null
+++ b/cpu/o3/scoreboard.hh
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_O3_SCOREBOARD_HH__
+#define __CPU_O3_SCOREBOARD_HH__
+
+#include <iostream>
+#include <utility>
+#include <vector>
+#include "arch/alpha/isa_traits.hh"
+#include "base/trace.hh"
+#include "base/traceflags.hh"
+#include "cpu/o3/comm.hh"
+
+/**
+ * Implements a simple scoreboard to track which registers are ready.
+ * This class assumes that the fp registers start, index wise, right after
+ * the integer registers. The misc. registers start, index wise, right after
+ * the fp registers.
+ * @todo: Fix up handling of the zero register in case the decoder does not
+ * automatically make insts that write the zero register into nops.
+ */
+class Scoreboard
+{
+ public:
+ /** Constructs a scoreboard.
+ * @param activeThreads The number of active threads.
+ * @param _numLogicalIntRegs Number of logical integer registers.
+ * @param _numPhysicalIntRegs Number of physical integer registers.
+ * @param _numLogicalFloatRegs Number of logical fp registers.
+ * @param _numPhysicalFloatRegs Number of physical fp registers.
+ * @param _numMiscRegs Number of miscellaneous registers.
+ * @param _zeroRegIdx Index of the zero register.
+ */
+ Scoreboard(unsigned activeThreads,
+ unsigned _numLogicalIntRegs,
+ unsigned _numPhysicalIntRegs,
+ unsigned _numLogicalFloatRegs,
+ unsigned _numPhysicalFloatRegs,
+ unsigned _numMiscRegs,
+ unsigned _zeroRegIdx);
+
+ /** Destructor. */
+ ~Scoreboard() {}
+
+ /** Returns the name of the scoreboard. */
+ std::string name() const;
+
+ /** Checks if the register is ready. */
+ bool getReg(PhysRegIndex ready_reg);
+
+ /** Sets the register as ready. */
+ void setReg(PhysRegIndex phys_reg);
+
+ /** Sets the register as not ready. */
+ void unsetReg(PhysRegIndex ready_reg);
+
+ private:
+ /** Scoreboard of physical integer registers, saying whether or not they
+ * are ready.
+ */
+ std::vector<bool> regScoreBoard;
+
+ /** Number of logical integer registers. */
+ int numLogicalIntRegs;
+
+ /** Number of physical integer registers. */
+ int numPhysicalIntRegs;
+
+ /** Number of logical floating point registers. */
+ int numLogicalFloatRegs;
+
+ /** Number of physical floating point registers. */
+ int numPhysicalFloatRegs;
+
+ /** Number of miscellaneous registers. */
+ int numMiscRegs;
+
+ /** Number of logical integer + float registers. */
+ int numLogicalRegs;
+
+ /** Number of physical integer + float registers. */
+ int numPhysicalRegs;
+
+ /** The logical index of the zero register. */
+ int zeroRegIdx;
+};
+
+#endif
diff --git a/cpu/o3/thread_state.hh b/cpu/o3/thread_state.hh
new file mode 100644
index 000000000..2c9788e4b
--- /dev/null
+++ b/cpu/o3/thread_state.hh
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_O3_THREAD_STATE_HH__
+#define __CPU_O3_THREAD_STATE_HH__
+
+#include "arch/faults.hh"
+#include "arch/isa_traits.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/thread_state.hh"
+
+class Event;
+class Process;
+
+#if FULL_SYSTEM
+class EndQuiesceEvent;
+class FunctionProfile;
+class ProfileNode;
+#else
+class FunctionalMemory;
+class Process;
+#endif
+
+/**
+ * Class that has various thread state, such as the status, the
+ * current instruction being processed, whether or not the thread has
+ * a trap pending or is being externally updated, the ExecContext
+ * proxy pointer, etc. It also handles anything related to a specific
+ * thread's process, such as syscalls and checking valid addresses.
+ */
+template <class Impl>
+struct O3ThreadState : public ThreadState {
+ typedef ExecContext::Status Status;
+ typedef typename Impl::FullCPU FullCPU;
+
+ Status _status;
+
+ // Current instruction
+ TheISA::MachInst inst;
+ private:
+ FullCPU *cpu;
+ public:
+
+ bool inSyscall;
+
+ bool trapPending;
+
+#if FULL_SYSTEM
+ O3ThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem)
+ : ThreadState(-1, _thread_num, _mem),
+ inSyscall(0), trapPending(0)
+ { }
+#else
+ O3ThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid)
+ : ThreadState(-1, _thread_num, _process->getMemory(), _process, _asid),
+ cpu(_cpu), inSyscall(0), trapPending(0)
+ { }
+
+ O3ThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
+ int _asid)
+ : ThreadState(-1, _thread_num, _mem, NULL, _asid),
+ cpu(_cpu), inSyscall(0), trapPending(0)
+ { }
+#endif
+
+ ExecContext *xcProxy;
+
+ ExecContext *getXCProxy() { return xcProxy; }
+
+ Status status() const { return _status; }
+
+ void setStatus(Status new_status) { _status = new_status; }
+
+#if !FULL_SYSTEM
+ bool validInstAddr(Addr addr)
+ { return process->validInstAddr(addr); }
+
+ bool validDataAddr(Addr addr)
+ { return process->validDataAddr(addr); }
+#endif
+
+ bool misspeculating() { return false; }
+
+ void setInst(TheISA::MachInst _inst) { inst = _inst; }
+
+ Counter readFuncExeInst() { return funcExeInst; }
+
+ void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
+
+#if !FULL_SYSTEM
+ void syscall() { process->syscall(xcProxy); }
+#endif
+};
+
+#endif // __CPU_O3_THREAD_STATE_HH__
diff --git a/cpu/ozone/back_end.cc b/cpu/ozone/back_end.cc
new file mode 100644
index 000000000..cb014e4cc
--- /dev/null
+++ b/cpu/ozone/back_end.cc
@@ -0,0 +1,5 @@
+
+#include "cpu/ozone/back_end_impl.hh"
+#include "cpu/ozone/ozone_impl.hh"
+
+//template class BackEnd<OzoneImpl>;
diff --git a/cpu/ozone/back_end.hh b/cpu/ozone/back_end.hh
new file mode 100644
index 000000000..14b011ab8
--- /dev/null
+++ b/cpu/ozone/back_end.hh
@@ -0,0 +1,516 @@
+
+#ifndef __CPU_OZONE_BACK_END_HH__
+#define __CPU_OZONE_BACK_END_HH__
+
+#include <list>
+#include <queue>
+#include <string>
+
+#include "arch/faults.hh"
+#include "base/timebuf.hh"
+#include "cpu/inst_seq.hh"
+#include "cpu/ozone/rename_table.hh"
+#include "cpu/ozone/thread_state.hh"
+#include "mem/functional/functional.hh"
+#include "mem/mem_interface.hh"
+#include "mem/mem_req.hh"
+#include "sim/eventq.hh"
+
+class ExecContext;
+
+template <class Impl>
+class OzoneThreadState;
+
+template <class Impl>
+class BackEnd
+{
+ public:
+ typedef OzoneThreadState<Impl> Thread;
+
+ typedef typename Impl::Params Params;
+ typedef typename Impl::DynInst DynInst;
+ typedef typename Impl::DynInstPtr DynInstPtr;
+ typedef typename Impl::FullCPU FullCPU;
+ typedef typename Impl::FrontEnd FrontEnd;
+ typedef typename Impl::FullCPU::CommStruct CommStruct;
+
+ struct SizeStruct {
+ int size;
+ };
+
+ typedef SizeStruct DispatchToIssue;
+ typedef SizeStruct IssueToExec;
+ typedef SizeStruct ExecToCommit;
+ typedef SizeStruct Writeback;
+
+ TimeBuffer<DispatchToIssue> d2i;
+ typename TimeBuffer<DispatchToIssue>::wire instsToDispatch;
+ TimeBuffer<IssueToExec> i2e;
+ typename TimeBuffer<IssueToExec>::wire instsToExecute;
+ TimeBuffer<ExecToCommit> e2c;
+ TimeBuffer<Writeback> numInstsToWB;
+
+ TimeBuffer<CommStruct> *comm;
+ typename TimeBuffer<CommStruct>::wire toIEW;
+ typename TimeBuffer<CommStruct>::wire fromCommit;
+
+ class InstQueue {
+ enum queue {
+ NonSpec,
+ IQ,
+ ToBeScheduled,
+ ReadyList,
+ ReplayList
+ };
+ struct pqCompare {
+ bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
+ {
+ return lhs->seqNum > rhs->seqNum;
+ }
+ };
+ public:
+ InstQueue(Params *params);
+
+ std::string name() const;
+
+ void regStats();
+
+ void setIssueExecQueue(TimeBuffer<IssueToExec> *i2e_queue);
+
+ void setBE(BackEnd *_be) { be = _be; }
+
+ void insert(DynInstPtr &inst);
+
+ void scheduleReadyInsts();
+
+ void scheduleNonSpec(const InstSeqNum &sn);
+
+ DynInstPtr getReadyInst();
+
+ void commit(const InstSeqNum &sn) {}
+
+ void squash(const InstSeqNum &sn);
+
+ int wakeDependents(DynInstPtr &inst);
+
+ /** Tells memory dependence unit that a memory instruction needs to be
+ * rescheduled. It will re-execute once replayMemInst() is called.
+ */
+ void rescheduleMemInst(DynInstPtr &inst);
+
+ /** Re-executes all rescheduled memory instructions. */
+ void replayMemInst(DynInstPtr &inst);
+
+ /** Completes memory instruction. */
+ void completeMemInst(DynInstPtr &inst);
+
+ void violation(DynInstPtr &inst, DynInstPtr &violation) { }
+
+ bool isFull() { return numInsts >= size; }
+
+ void dumpInsts();
+
+ private:
+ bool find(queue q, typename std::list<DynInstPtr>::iterator it);
+ BackEnd *be;
+ TimeBuffer<IssueToExec> *i2e;
+ typename TimeBuffer<IssueToExec>::wire numIssued;
+ typedef typename std::list<DynInstPtr> InstList;
+ typedef typename std::list<DynInstPtr>::iterator InstListIt;
+ typedef typename std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare> ReadyInstQueue;
+ // Not sure I need the IQ list; it just needs to be a count.
+ InstList iq;
+ InstList toBeScheduled;
+ InstList readyList;
+ InstList nonSpec;
+ InstList replayList;
+ ReadyInstQueue readyQueue;
+ public:
+ int size;
+ int numInsts;
+ int width;
+
+ Stats::VectorDistribution<> occ_dist;
+
+ Stats::Vector<> inst_count;
+ Stats::Vector<> peak_inst_count;
+ Stats::Scalar<> empty_count;
+ Stats::Scalar<> current_count;
+ Stats::Scalar<> fullCount;
+
+ Stats::Formula occ_rate;
+ Stats::Formula avg_residency;
+ Stats::Formula empty_rate;
+ Stats::Formula full_rate;
+ };
+
+ /** LdWriteback event for a load completion. */
+ class LdWritebackEvent : public Event {
+ private:
+ /** Instruction that is writing back data to the register file. */
+ DynInstPtr inst;
+ /** Pointer to IEW stage. */
+ BackEnd *be;
+
+ public:
+ /** Constructs a load writeback event. */
+ LdWritebackEvent(DynInstPtr &_inst, BackEnd *be);
+
+ /** Processes writeback event. */
+ virtual void process();
+ /** Returns the description of the writeback event. */
+ virtual const char *description();
+ };
+
+ BackEnd(Params *params);
+
+ std::string name() const;
+
+ void regStats();
+
+ void setCPU(FullCPU *cpu_ptr)
+ { cpu = cpu_ptr; }
+
+ void setFrontEnd(FrontEnd *front_end_ptr)
+ { frontEnd = front_end_ptr; }
+
+ void setXC(ExecContext *xc_ptr)
+ { xc = xc_ptr; }
+
+ void setThreadState(Thread *thread_ptr)
+ { thread = thread_ptr; }
+
+ void setCommBuffer(TimeBuffer<CommStruct> *_comm);
+
+ void tick();
+ void squash();
+ void squashFromXC();
+ bool xcSquash;
+
+ template <class T>
+ Fault read(MemReqPtr &req, T &data, int load_idx);
+
+ template <class T>
+ Fault write(MemReqPtr &req, T &data, int store_idx);
+
+ Addr readCommitPC() { return commitPC; }
+
+ Addr commitPC;
+
+ bool robEmpty() { return instList.empty(); }
+
+ bool isFull() { return numInsts >= numROBEntries; }
+ bool isBlocked() { return status == Blocked || dispatchStatus == Blocked; }
+
+ /** Tells memory dependence unit that a memory instruction needs to be
+ * rescheduled. It will re-execute once replayMemInst() is called.
+ */
+ void rescheduleMemInst(DynInstPtr &inst)
+ { IQ.rescheduleMemInst(inst); }
+
+ /** Re-executes all rescheduled memory instructions. */
+ void replayMemInst(DynInstPtr &inst)
+ { IQ.replayMemInst(inst); }
+
+ /** Completes memory instruction. */
+ void completeMemInst(DynInstPtr &inst)
+ { IQ.completeMemInst(inst); }
+
+ void fetchFault(Fault &fault);
+
+ private:
+ void updateStructures();
+ void dispatchInsts();
+ void dispatchStall();
+ void checkDispatchStatus();
+ void scheduleReadyInsts();
+ void executeInsts();
+ void commitInsts();
+ void addToIQ(DynInstPtr &inst);
+ void addToLSQ(DynInstPtr &inst);
+ void instToCommit(DynInstPtr &inst);
+ void writebackInsts();
+ bool commitInst(int inst_num);
+ void squash(const InstSeqNum &sn);
+ void squashDueToBranch(DynInstPtr &inst);
+ void squashDueToMemBlocked(DynInstPtr &inst);
+ void updateExeInstStats(DynInstPtr &inst);
+ void updateComInstStats(DynInstPtr &inst);
+
+ public:
+ FullCPU *cpu;
+
+ FrontEnd *frontEnd;
+
+ ExecContext *xc;
+
+ Thread *thread;
+
+ enum Status {
+ Running,
+ Idle,
+ DcacheMissStall,
+ DcacheMissComplete,
+ Blocked
+ };
+
+ Status status;
+
+ Status dispatchStatus;
+
+ Counter funcExeInst;
+
+ private:
+// typedef typename Impl::InstQueue InstQueue;
+
+ InstQueue IQ;
+
+ typedef typename Impl::LdstQueue LdstQueue;
+
+ LdstQueue LSQ;
+ public:
+ RenameTable<Impl> commitRenameTable;
+
+ RenameTable<Impl> renameTable;
+ private:
+ class DCacheCompletionEvent : public Event
+ {
+ private:
+ BackEnd *be;
+
+ public:
+ DCacheCompletionEvent(BackEnd *_be);
+
+ virtual void process();
+ virtual const char *description();
+ };
+
+ friend class DCacheCompletionEvent;
+
+ DCacheCompletionEvent cacheCompletionEvent;
+
+ MemInterface *dcacheInterface;
+
+ MemReqPtr memReq;
+
+ // General back end width. Used if the more specific isn't given.
+ int width;
+
+ // Dispatch width.
+ int dispatchWidth;
+ int numDispatchEntries;
+ int dispatchSize;
+
+ int issueWidth;
+
+ // Writeback width
+ int wbWidth;
+
+ // Commit width
+ int commitWidth;
+
+ /** Index into queue of instructions being written back. */
+ unsigned wbNumInst;
+
+ /** Cycle number within the queue of instructions being written
+ * back. Used in case there are too many instructions writing
+ * back at the current cycle and writesbacks need to be scheduled
+ * for the future. See comments in instToCommit().
+ */
+ unsigned wbCycle;
+
+ int numROBEntries;
+ int numInsts;
+
+ bool squashPending;
+ InstSeqNum squashSeqNum;
+ Addr squashNextPC;
+
+ Fault faultFromFetch;
+
+ private:
+ typedef typename std::list<DynInstPtr>::iterator InstListIt;
+
+ std::list<DynInstPtr> instList;
+ std::list<DynInstPtr> dispatch;
+ std::list<DynInstPtr> writeback;
+
+ int latency;
+
+ int squashLatency;
+
+ bool exactFullStall;
+
+ bool fetchRedirect[Impl::MaxThreads];
+
+ // number of cycles stalled for D-cache misses
+/* Stats::Scalar<> dcacheStallCycles;
+ Counter lastDcacheStall;
+*/
+ Stats::Vector<> rob_cap_events;
+ Stats::Vector<> rob_cap_inst_count;
+ Stats::Vector<> iq_cap_events;
+ Stats::Vector<> iq_cap_inst_count;
+ // total number of instructions executed
+ Stats::Vector<> exe_inst;
+ Stats::Vector<> exe_swp;
+ Stats::Vector<> exe_nop;
+ Stats::Vector<> exe_refs;
+ Stats::Vector<> exe_loads;
+ Stats::Vector<> exe_branches;
+
+ Stats::Vector<> issued_ops;
+
+ // total number of loads forwaded from LSQ stores
+ Stats::Vector<> lsq_forw_loads;
+
+ // total number of loads ignored due to invalid addresses
+ Stats::Vector<> inv_addr_loads;
+
+ // total number of software prefetches ignored due to invalid addresses
+ Stats::Vector<> inv_addr_swpfs;
+ // ready loads blocked due to memory disambiguation
+ Stats::Vector<> lsq_blocked_loads;
+
+ Stats::Scalar<> lsqInversion;
+
+ Stats::Vector<> n_issued_dist;
+ Stats::VectorDistribution<> issue_delay_dist;
+
+ Stats::VectorDistribution<> queue_res_dist;
+/*
+ Stats::Vector<> stat_fu_busy;
+ Stats::Vector2d<> stat_fuBusy;
+ Stats::Vector<> dist_unissued;
+ Stats::Vector2d<> stat_issued_inst_type;
+
+ Stats::Formula misspec_cnt;
+ Stats::Formula misspec_ipc;
+ Stats::Formula issue_rate;
+ Stats::Formula issue_stores;
+ Stats::Formula issue_op_rate;
+ Stats::Formula fu_busy_rate;
+ Stats::Formula commit_stores;
+ Stats::Formula commit_ipc;
+ Stats::Formula commit_ipb;
+ Stats::Formula lsq_inv_rate;
+*/
+ Stats::Vector<> writeback_count;
+ Stats::Vector<> producer_inst;
+ Stats::Vector<> consumer_inst;
+ Stats::Vector<> wb_penalized;
+
+ Stats::Formula wb_rate;
+ Stats::Formula wb_fanout;
+ Stats::Formula wb_penalized_rate;
+
+ // total number of instructions committed
+ Stats::Vector<> stat_com_inst;
+ Stats::Vector<> stat_com_swp;
+ Stats::Vector<> stat_com_refs;
+ Stats::Vector<> stat_com_loads;
+ Stats::Vector<> stat_com_membars;
+ Stats::Vector<> stat_com_branches;
+
+ Stats::Distribution<> n_committed_dist;
+
+ Stats::Scalar<> commit_eligible_samples;
+ Stats::Vector<> commit_eligible;
+
+ Stats::Scalar<> ROB_fcount;
+ Stats::Formula ROB_full_rate;
+
+ Stats::Vector<> ROB_count; // cumulative ROB occupancy
+ Stats::Formula ROB_occ_rate;
+ Stats::VectorDistribution<> ROB_occ_dist;
+ public:
+ void dumpInsts();
+};
+
+template <class Impl>
+template <class T>
+Fault
+BackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
+{
+/* memReq->reset(addr, sizeof(T), flags);
+
+ // translate to physical address
+ Fault fault = cpu->translateDataReadReq(memReq);
+
+ // if we have a cache, do cache access too
+ if (fault == NoFault && dcacheInterface) {
+ memReq->cmd = Read;
+ memReq->completionEvent = NULL;
+ memReq->time = curTick;
+ memReq->flags &= ~INST_READ;
+ MemAccessResult result = dcacheInterface->access(memReq);
+
+ // Ugly hack to get an event scheduled *only* if the access is
+ // a miss. We really should add first-class support for this
+ // at some point.
+ if (result != MA_HIT && dcacheInterface->doEvents()) {
+ // Fix this hack for keeping funcExeInst correct with loads that
+ // are executed twice.
+ --funcExeInst;
+
+ memReq->completionEvent = &cacheCompletionEvent;
+ lastDcacheStall = curTick;
+// unscheduleTickEvent();
+// status = DcacheMissStall;
+ DPRINTF(OzoneCPU, "Dcache miss stall!\n");
+ } else {
+ // do functional access
+ fault = thread->mem->read(memReq, data);
+
+ }
+ }
+*/
+/*
+ if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
+ recordEvent("Uncached Read");
+*/
+ return LSQ.read(req, data, load_idx);
+}
+
+template <class Impl>
+template <class T>
+Fault
+BackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
+{
+/*
+ memReq->reset(addr, sizeof(T), flags);
+
+ // translate to physical address
+ Fault fault = cpu->translateDataWriteReq(memReq);
+
+ if (fault == NoFault && dcacheInterface) {
+ memReq->cmd = Write;
+ memcpy(memReq->data,(uint8_t *)&data,memReq->size);
+ memReq->completionEvent = NULL;
+ memReq->time = curTick;
+ memReq->flags &= ~INST_READ;
+ MemAccessResult result = dcacheInterface->access(memReq);
+
+ // Ugly hack to get an event scheduled *only* if the access is
+ // a miss. We really should add first-class support for this
+ // at some point.
+ if (result != MA_HIT && dcacheInterface->doEvents()) {
+ memReq->completionEvent = &cacheCompletionEvent;
+ lastDcacheStall = curTick;
+// unscheduleTickEvent();
+// status = DcacheMissStall;
+ DPRINTF(OzoneCPU, "Dcache miss stall!\n");
+ }
+ }
+
+ if (res && (fault == NoFault))
+ *res = memReq->result;
+ */
+/*
+ if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
+ recordEvent("Uncached Write");
+*/
+ return LSQ.write(req, data, store_idx);
+}
+
+#endif // __CPU_OZONE_BACK_END_HH__
diff --git a/cpu/ozone/back_end_impl.hh b/cpu/ozone/back_end_impl.hh
new file mode 100644
index 000000000..36770d65c
--- /dev/null
+++ b/cpu/ozone/back_end_impl.hh
@@ -0,0 +1,1904 @@
+
+#include "encumbered/cpu/full/op_class.hh"
+#include "cpu/ozone/back_end.hh"
+
+template <class Impl>
+BackEnd<Impl>::InstQueue::InstQueue(Params *params)
+ : size(params->numIQEntries), numInsts(0), width(params->issueWidth)
+{
+}
+
+template <class Impl>
+std::string
+BackEnd<Impl>::InstQueue::name() const
+{
+ return be->name() + ".iq";
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::InstQueue::regStats()
+{
+ using namespace Stats;
+
+ occ_dist
+ .init(1, 0, size, 2)
+ .name(name() + "occ_dist")
+ .desc("IQ Occupancy per cycle")
+ .flags(total | cdf)
+ ;
+
+ inst_count
+ .init(1)
+ .name(name() + "cum_num_insts")
+ .desc("Total occupancy")
+ .flags(total)
+ ;
+
+ peak_inst_count
+ .init(1)
+ .name(name() + "peak_occupancy")
+ .desc("Peak IQ occupancy")
+ .flags(total)
+ ;
+
+ current_count
+ .name(name() + "current_count")
+ .desc("Occupancy this cycle")
+ ;
+
+ empty_count
+ .name(name() + "empty_count")
+ .desc("Number of empty cycles")
+ ;
+
+ fullCount
+ .name(name() + "full_count")
+ .desc("Number of full cycles")
+ ;
+
+
+ occ_rate
+ .name(name() + "occ_rate")
+ .desc("Average occupancy")
+ .flags(total)
+ ;
+ occ_rate = inst_count / be->cpu->numCycles;
+
+ avg_residency
+ .name(name() + "avg_residency")
+ .desc("Average IQ residency")
+ .flags(total)
+ ;
+ avg_residency = occ_rate / be->cpu->numCycles;
+
+ empty_rate
+ .name(name() + "empty_rate")
+ .desc("Fraction of cycles empty")
+ ;
+ empty_rate = 100 * empty_count / be->cpu->numCycles;
+
+ full_rate
+ .name(name() + "full_rate")
+ .desc("Fraction of cycles full")
+ ;
+ full_rate = 100 * fullCount / be->cpu->numCycles;
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::InstQueue::setIssueExecQueue(TimeBuffer<IssueToExec> *i2e_queue)
+{
+ i2e = i2e_queue;
+ numIssued = i2e->getWire(0);
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::InstQueue::insert(DynInstPtr &inst)
+{
+ numInsts++;
+ inst_count[0]++;
+ if (!inst->isNonSpeculative()) {
+ DPRINTF(BE, "Instruction [sn:%lli] added to IQ\n", inst->seqNum);
+ if (inst->readyToIssue()) {
+ toBeScheduled.push_front(inst);
+ inst->iqIt = toBeScheduled.begin();
+ inst->iqItValid = true;
+ } else {
+ iq.push_front(inst);
+ inst->iqIt = iq.begin();
+ inst->iqItValid = true;
+ }
+ } else {
+ DPRINTF(BE, "Nonspeculative instruction [sn:%lli] added to IQ\n", inst->seqNum);
+ nonSpec.push_front(inst);
+ inst->iqIt = nonSpec.begin();
+ inst->iqItValid = true;
+ }
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::InstQueue::scheduleReadyInsts()
+{
+ int scheduled = numIssued->size;
+ InstListIt iq_it = --toBeScheduled.end();
+ InstListIt iq_end_it = toBeScheduled.end();
+
+ while (iq_it != iq_end_it && scheduled < width) {
+// if ((*iq_it)->readyToIssue()) {
+ DPRINTF(BE, "Instruction [sn:%lli] PC:%#x is ready\n",
+ (*iq_it)->seqNum, (*iq_it)->readPC());
+ readyQueue.push(*iq_it);
+ readyList.push_front(*iq_it);
+
+ (*iq_it)->iqIt = readyList.begin();
+
+ toBeScheduled.erase(iq_it--);
+
+ ++scheduled;
+// } else {
+// iq_it++;
+// }
+ }
+
+ numIssued->size+= scheduled;
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::InstQueue::scheduleNonSpec(const InstSeqNum &sn)
+{
+/*
+ InstListIt non_spec_it = nonSpec.begin();
+ InstListIt non_spec_end_it = nonSpec.end();
+
+ while ((*non_spec_it)->seqNum != sn) {
+ non_spec_it++;
+ assert(non_spec_it != non_spec_end_it);
+ }
+*/
+ DynInstPtr inst = nonSpec.back();
+
+ DPRINTF(BE, "Nonspeculative instruction [sn:%lli] scheduled\n", inst->seqNum);
+
+ assert(inst->seqNum == sn);
+
+ assert(find(NonSpec, inst->iqIt));
+ nonSpec.erase(inst->iqIt);
+ readyList.push_front(inst);
+ inst->iqIt = readyList.begin();
+ readyQueue.push(inst);
+ numIssued->size++;
+}
+
+template <class Impl>
+typename Impl::DynInstPtr
+BackEnd<Impl>::InstQueue::getReadyInst()
+{
+ assert(!readyList.empty());
+
+ DynInstPtr inst = readyQueue.top();
+ readyQueue.pop();
+ assert(find(ReadyList, inst->iqIt));
+ readyList.erase(inst->iqIt);
+ inst->iqItValid = false;
+// if (!inst->isMemRef())
+ --numInsts;
+ return inst;
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::InstQueue::squash(const InstSeqNum &sn)
+{
+ InstListIt iq_it = iq.begin();
+ InstListIt iq_end_it = iq.end();
+
+ while (iq_it != iq_end_it && (*iq_it)->seqNum > sn) {
+ DPRINTF(BE, "Instruction [sn:%lli] removed from IQ\n", (*iq_it)->seqNum);
+ (*iq_it)->iqItValid = false;
+ iq.erase(iq_it++);
+ --numInsts;
+ }
+
+ iq_it = nonSpec.begin();
+ iq_end_it = nonSpec.end();
+
+ while (iq_it != iq_end_it && (*iq_it)->seqNum > sn) {
+ DPRINTF(BE, "Instruction [sn:%lli] removed from IQ\n", (*iq_it)->seqNum);
+ (*iq_it)->iqItValid = false;
+ nonSpec.erase(iq_it++);
+ --numInsts;
+ }
+
+ iq_it = replayList.begin();
+ iq_end_it = replayList.end();
+
+ while (iq_it != iq_end_it) {
+ if ((*iq_it)->seqNum > sn) {
+ DPRINTF(BE, "Instruction [sn:%lli] removed from IQ\n", (*iq_it)->seqNum);
+ (*iq_it)->iqItValid = false;
+ replayList.erase(iq_it++);
+ --numInsts;
+ } else {
+ iq_it++;
+ }
+ }
+
+ assert(numInsts >= 0);
+/*
+ InstListIt ready_it = readyList.begin();
+ InstListIt ready_end_it = readyList.end();
+
+ while (ready_it != ready_end_it) {
+ if ((*ready_it)->seqNum > sn) {
+ readyList.erase(ready_it++);
+ } else {
+ ready_it++;
+ }
+ }
+*/
+}
+
+template <class Impl>
+int
+BackEnd<Impl>::InstQueue::wakeDependents(DynInstPtr &inst)
+{
+ assert(!inst->isSquashed());
+ std::vector<DynInstPtr> &dependents = inst->getDependents();
+ int num_outputs = dependents.size();
+
+ DPRINTF(BE, "Waking instruction [sn:%lli] dependents in IQ\n", inst->seqNum);
+
+ for (int i = 0; i < num_outputs; i++) {
+ DynInstPtr dep_inst = dependents[i];
+ dep_inst->markSrcRegReady();
+ DPRINTF(BE, "Marking source reg ready [sn:%lli] in IQ\n", dep_inst->seqNum);
+
+ if (dep_inst->readyToIssue() && dep_inst->iqItValid) {
+ if (dep_inst->isNonSpeculative()) {
+ assert(find(NonSpec, dep_inst->iqIt));
+ nonSpec.erase(dep_inst->iqIt);
+ } else {
+ assert(find(IQ, dep_inst->iqIt));
+ iq.erase(dep_inst->iqIt);
+ }
+
+ toBeScheduled.push_front(dep_inst);
+ dep_inst->iqIt = toBeScheduled.begin();
+ }
+ }
+ return num_outputs;
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::InstQueue::rescheduleMemInst(DynInstPtr &inst)
+{
+ DPRINTF(BE, "Rescheduling memory instruction [sn:%lli]\n", inst->seqNum);
+ assert(!inst->iqItValid);
+ replayList.push_front(inst);
+ inst->iqIt = replayList.begin();
+ inst->iqItValid = true;
+ ++numInsts;
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::InstQueue::replayMemInst(DynInstPtr &inst)
+{
+ DPRINTF(BE, "Replaying memory instruction [sn:%lli]\n", inst->seqNum);
+ assert(find(ReplayList, inst->iqIt));
+ InstListIt iq_it = --replayList.end();
+ InstListIt iq_end_it = replayList.end();
+ while (iq_it != iq_end_it) {
+ DynInstPtr rescheduled_inst = (*iq_it);
+
+ DPRINTF(BE, "Memory instruction [sn:%lli] also replayed\n", inst->seqNum);
+ replayList.erase(iq_it--);
+ toBeScheduled.push_front(rescheduled_inst);
+ rescheduled_inst->iqIt = toBeScheduled.begin();
+ }
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::InstQueue::completeMemInst(DynInstPtr &inst)
+{
+ panic("Not implemented.");
+}
+
+template <class Impl>
+bool
+BackEnd<Impl>::InstQueue::find(queue q, InstListIt it)
+{
+ InstListIt iq_it, iq_end_it;
+ switch(q) {
+ case NonSpec:
+ iq_it = nonSpec.begin();
+ iq_end_it = nonSpec.end();
+ break;
+ case IQ:
+ iq_it = iq.begin();
+ iq_end_it = iq.end();
+ break;
+ case ToBeScheduled:
+ iq_it = toBeScheduled.begin();
+ iq_end_it = toBeScheduled.end();
+ break;
+ case ReadyList:
+ iq_it = readyList.begin();
+ iq_end_it = readyList.end();
+ break;
+ case ReplayList:
+ iq_it = replayList.begin();
+ iq_end_it = replayList.end();
+ }
+
+ while (iq_it != it && iq_it != iq_end_it) {
+ iq_it++;
+ }
+ if (iq_it == it) {
+ return true;
+ } else {
+ return false;
+ }
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::InstQueue::dumpInsts()
+{
+ cprintf("IQ size: %i\n", iq.size());
+
+ InstListIt inst_list_it = --iq.end();
+
+ int num = 0;
+ int valid_num = 0;
+ while (inst_list_it != iq.end())
+ {
+ cprintf("Instruction:%i\n",
+ num);
+ if (!(*inst_list_it)->isSquashed()) {
+ if (!(*inst_list_it)->isIssued()) {
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ } else if ((*inst_list_it)->isMemRef() &&
+ !(*inst_list_it)->memOpDone) {
+ // Loads that have not been marked as executed still count
+ // towards the total instructions.
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ }
+ }
+
+ cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
+ "Issued:%i\nSquashed:%i\n",
+ (*inst_list_it)->readPC(),
+ (*inst_list_it)->seqNum,
+ (*inst_list_it)->threadNumber,
+ (*inst_list_it)->isIssued(),
+ (*inst_list_it)->isSquashed());
+
+ if ((*inst_list_it)->isMemRef()) {
+ cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
+ }
+
+ cprintf("\n");
+
+ inst_list_it--;
+ ++num;
+ }
+
+ cprintf("nonSpec size: %i\n", nonSpec.size());
+
+ inst_list_it = --nonSpec.end();
+
+ while (inst_list_it != nonSpec.end())
+ {
+ cprintf("Instruction:%i\n",
+ num);
+ if (!(*inst_list_it)->isSquashed()) {
+ if (!(*inst_list_it)->isIssued()) {
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ } else if ((*inst_list_it)->isMemRef() &&
+ !(*inst_list_it)->memOpDone) {
+ // Loads that have not been marked as executed still count
+ // towards the total instructions.
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ }
+ }
+
+ cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
+ "Issued:%i\nSquashed:%i\n",
+ (*inst_list_it)->readPC(),
+ (*inst_list_it)->seqNum,
+ (*inst_list_it)->threadNumber,
+ (*inst_list_it)->isIssued(),
+ (*inst_list_it)->isSquashed());
+
+ if ((*inst_list_it)->isMemRef()) {
+ cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
+ }
+
+ cprintf("\n");
+
+ inst_list_it--;
+ ++num;
+ }
+
+ cprintf("toBeScheduled size: %i\n", toBeScheduled.size());
+
+ inst_list_it = --toBeScheduled.end();
+
+ while (inst_list_it != toBeScheduled.end())
+ {
+ cprintf("Instruction:%i\n",
+ num);
+ if (!(*inst_list_it)->isSquashed()) {
+ if (!(*inst_list_it)->isIssued()) {
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ } else if ((*inst_list_it)->isMemRef() &&
+ !(*inst_list_it)->memOpDone) {
+ // Loads that have not been marked as executed still count
+ // towards the total instructions.
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ }
+ }
+
+ cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
+ "Issued:%i\nSquashed:%i\n",
+ (*inst_list_it)->readPC(),
+ (*inst_list_it)->seqNum,
+ (*inst_list_it)->threadNumber,
+ (*inst_list_it)->isIssued(),
+ (*inst_list_it)->isSquashed());
+
+ if ((*inst_list_it)->isMemRef()) {
+ cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
+ }
+
+ cprintf("\n");
+
+ inst_list_it--;
+ ++num;
+ }
+
+ cprintf("readyList size: %i\n", readyList.size());
+
+ inst_list_it = --readyList.end();
+
+ while (inst_list_it != readyList.end())
+ {
+ cprintf("Instruction:%i\n",
+ num);
+ if (!(*inst_list_it)->isSquashed()) {
+ if (!(*inst_list_it)->isIssued()) {
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ } else if ((*inst_list_it)->isMemRef() &&
+ !(*inst_list_it)->memOpDone) {
+ // Loads that have not been marked as executed still count
+ // towards the total instructions.
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ }
+ }
+
+ cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
+ "Issued:%i\nSquashed:%i\n",
+ (*inst_list_it)->readPC(),
+ (*inst_list_it)->seqNum,
+ (*inst_list_it)->threadNumber,
+ (*inst_list_it)->isIssued(),
+ (*inst_list_it)->isSquashed());
+
+ if ((*inst_list_it)->isMemRef()) {
+ cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
+ }
+
+ cprintf("\n");
+
+ inst_list_it--;
+ ++num;
+ }
+}
+
+template<class Impl>
+BackEnd<Impl>::LdWritebackEvent::LdWritebackEvent(DynInstPtr &_inst,
+ BackEnd<Impl> *_be)
+ : Event(&mainEventQueue), inst(_inst), be(_be)
+{
+ this->setFlags(Event::AutoDelete);
+}
+
+template<class Impl>
+void
+BackEnd<Impl>::LdWritebackEvent::process()
+{
+ DPRINTF(BE, "Load writeback event [sn:%lli]\n", inst->seqNum);
+// DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum);
+
+ //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
+
+// iewStage->wakeCPU();
+
+ if (inst->isSquashed()) {
+ inst = NULL;
+ return;
+ }
+
+ if (!inst->isExecuted()) {
+ inst->setExecuted();
+
+ // Execute again to copy data to proper place.
+ inst->completeAcc();
+ }
+
+ // Need to insert instruction into queue to commit
+ be->instToCommit(inst);
+
+ //wroteToTimeBuffer = true;
+// iewStage->activityThisCycle();
+
+ inst = NULL;
+}
+
+template<class Impl>
+const char *
+BackEnd<Impl>::LdWritebackEvent::description()
+{
+ return "Load writeback event";
+}
+
+
+template <class Impl>
+BackEnd<Impl>::DCacheCompletionEvent::DCacheCompletionEvent(BackEnd *_be)
+ : Event(&mainEventQueue, CPU_Tick_Pri), be(_be)
+{
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::DCacheCompletionEvent::process()
+{
+}
+
+template <class Impl>
+const char *
+BackEnd<Impl>::DCacheCompletionEvent::description()
+{
+ return "Cache completion event";
+}
+
+template <class Impl>
+BackEnd<Impl>::BackEnd(Params *params)
+ : d2i(5, 5), i2e(5, 5), e2c(5, 5), numInstsToWB(5, 5),
+ xcSquash(false), IQ(params),
+ cacheCompletionEvent(this), width(params->backEndWidth),
+ exactFullStall(true)
+{
+ numROBEntries = params->numROBEntries;
+ numInsts = 0;
+ numDispatchEntries = 32;
+ IQ.setBE(this);
+ LSQ.setBE(this);
+
+ // Setup IQ and LSQ with their parameters here.
+ instsToDispatch = d2i.getWire(-1);
+
+ instsToExecute = i2e.getWire(-1);
+
+ IQ.setIssueExecQueue(&i2e);
+
+ dispatchWidth = params->dispatchWidth ? params->dispatchWidth : width;
+ issueWidth = params->issueWidth ? params->issueWidth : width;
+ wbWidth = params->wbWidth ? params->wbWidth : width;
+ commitWidth = params->commitWidth ? params->commitWidth : width;
+
+ LSQ.init(params, params->LQEntries, params->SQEntries, 0);
+
+ dispatchStatus = Running;
+}
+
+template <class Impl>
+std::string
+BackEnd<Impl>::name() const
+{
+ return cpu->name() + ".backend";
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::regStats()
+{
+ using namespace Stats;
+ rob_cap_events
+ .init(cpu->number_of_threads)
+ .name(name() + ".ROB:cap_events")
+ .desc("number of cycles where ROB cap was active")
+ .flags(total)
+ ;
+
+ rob_cap_inst_count
+ .init(cpu->number_of_threads)
+ .name(name() + ".ROB:cap_inst")
+ .desc("number of instructions held up by ROB cap")
+ .flags(total)
+ ;
+
+ iq_cap_events
+ .init(cpu->number_of_threads)
+ .name(name() +".IQ:cap_events" )
+ .desc("number of cycles where IQ cap was active")
+ .flags(total)
+ ;
+
+ iq_cap_inst_count
+ .init(cpu->number_of_threads)
+ .name(name() + ".IQ:cap_inst")
+ .desc("number of instructions held up by IQ cap")
+ .flags(total)
+ ;
+
+
+ exe_inst
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:count")
+ .desc("number of insts issued")
+ .flags(total)
+ ;
+
+ exe_swp
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:swp")
+ .desc("number of swp insts issued")
+ .flags(total)
+ ;
+
+ exe_nop
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:nop")
+ .desc("number of nop insts issued")
+ .flags(total)
+ ;
+
+ exe_refs
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:refs")
+ .desc("number of memory reference insts issued")
+ .flags(total)
+ ;
+
+ exe_loads
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:loads")
+ .desc("number of load insts issued")
+ .flags(total)
+ ;
+
+ exe_branches
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:branches")
+ .desc("Number of branches issued")
+ .flags(total)
+ ;
+
+ issued_ops
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:op_count")
+ .desc("number of insts issued")
+ .flags(total)
+ ;
+
+/*
+ for (int i=0; i<Num_OpClasses; ++i) {
+ stringstream subname;
+ subname << opClassStrings[i] << "_delay";
+ issue_delay_dist.subname(i, subname.str());
+ }
+*/
+ //
+ // Other stats
+ //
+ lsq_forw_loads
+ .init(cpu->number_of_threads)
+ .name(name() + ".LSQ:forw_loads")
+ .desc("number of loads forwarded via LSQ")
+ .flags(total)
+ ;
+
+ inv_addr_loads
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:addr_loads")
+ .desc("number of invalid-address loads")
+ .flags(total)
+ ;
+
+ inv_addr_swpfs
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:addr_swpfs")
+ .desc("number of invalid-address SW prefetches")
+ .flags(total)
+ ;
+
+ lsq_blocked_loads
+ .init(cpu->number_of_threads)
+ .name(name() + ".LSQ:blocked_loads")
+ .desc("number of ready loads not issued due to memory disambiguation")
+ .flags(total)
+ ;
+
+ lsqInversion
+ .name(name() + ".ISSUE:lsq_invert")
+ .desc("Number of times LSQ instruction issued early")
+ ;
+
+ n_issued_dist
+ .init(issueWidth + 1)
+ .name(name() + ".ISSUE:issued_per_cycle")
+ .desc("Number of insts issued each cycle")
+ .flags(total | pdf | dist)
+ ;
+ issue_delay_dist
+ .init(Num_OpClasses,0,99,2)
+ .name(name() + ".ISSUE:")
+ .desc("cycles from operands ready to issue")
+ .flags(pdf | cdf)
+ ;
+
+ queue_res_dist
+ .init(Num_OpClasses, 0, 99, 2)
+ .name(name() + ".IQ:residence:")
+ .desc("cycles from dispatch to issue")
+ .flags(total | pdf | cdf )
+ ;
+ for (int i = 0; i < Num_OpClasses; ++i) {
+ queue_res_dist.subname(i, opClassStrings[i]);
+ }
+
+ writeback_count
+ .init(cpu->number_of_threads)
+ .name(name() + ".WB:count")
+ .desc("cumulative count of insts written-back")
+ .flags(total)
+ ;
+
+ producer_inst
+ .init(cpu->number_of_threads)
+ .name(name() + ".WB:producers")
+ .desc("num instructions producing a value")
+ .flags(total)
+ ;
+
+ consumer_inst
+ .init(cpu->number_of_threads)
+ .name(name() + ".WB:consumers")
+ .desc("num instructions consuming a value")
+ .flags(total)
+ ;
+
+ wb_penalized
+ .init(cpu->number_of_threads)
+ .name(name() + ".WB:penalized")
+ .desc("number of instrctions required to write to 'other' IQ")
+ .flags(total)
+ ;
+
+
+ wb_penalized_rate
+ .name(name() + ".WB:penalized_rate")
+ .desc ("fraction of instructions written-back that wrote to 'other' IQ")
+ .flags(total)
+ ;
+
+ wb_penalized_rate = wb_penalized / writeback_count;
+
+ wb_fanout
+ .name(name() + ".WB:fanout")
+ .desc("average fanout of values written-back")
+ .flags(total)
+ ;
+
+ wb_fanout = producer_inst / consumer_inst;
+
+ wb_rate
+ .name(name() + ".WB:rate")
+ .desc("insts written-back per cycle")
+ .flags(total)
+ ;
+ wb_rate = writeback_count / cpu->numCycles;
+
+ stat_com_inst
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:count")
+ .desc("Number of instructions committed")
+ .flags(total)
+ ;
+
+ stat_com_swp
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:swp_count")
+ .desc("Number of s/w prefetches committed")
+ .flags(total)
+ ;
+
+ stat_com_refs
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:refs")
+ .desc("Number of memory references committed")
+ .flags(total)
+ ;
+
+ stat_com_loads
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:loads")
+ .desc("Number of loads committed")
+ .flags(total)
+ ;
+
+ stat_com_membars
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:membars")
+ .desc("Number of memory barriers committed")
+ .flags(total)
+ ;
+
+ stat_com_branches
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:branches")
+ .desc("Number of branches committed")
+ .flags(total)
+ ;
+ n_committed_dist
+ .init(0,commitWidth,1)
+ .name(name() + ".COM:committed_per_cycle")
+ .desc("Number of insts commited each cycle")
+ .flags(pdf)
+ ;
+
+ //
+ // Commit-Eligible instructions...
+ //
+ // -> The number of instructions eligible to commit in those
+ // cycles where we reached our commit BW limit (less the number
+ // actually committed)
+ //
+ // -> The average value is computed over ALL CYCLES... not just
+ // the BW limited cycles
+ //
+ // -> The standard deviation is computed only over cycles where
+ // we reached the BW limit
+ //
+ commit_eligible
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:bw_limited")
+ .desc("number of insts not committed due to BW limits")
+ .flags(total)
+ ;
+
+ commit_eligible_samples
+ .name(name() + ".COM:bw_lim_events")
+ .desc("number cycles where commit BW limit reached")
+ ;
+
+ ROB_fcount
+ .name(name() + ".ROB:full_count")
+ .desc("number of cycles where ROB was full")
+ ;
+
+ ROB_count
+ .init(cpu->number_of_threads)
+ .name(name() + ".ROB:occupancy")
+ .desc(name() + ".ROB occupancy (cumulative)")
+ .flags(total)
+ ;
+
+ ROB_full_rate
+ .name(name() + ".ROB:full_rate")
+ .desc("ROB full per cycle")
+ ;
+ ROB_full_rate = ROB_fcount / cpu->numCycles;
+
+ ROB_occ_rate
+ .name(name() + ".ROB:occ_rate")
+ .desc("ROB occupancy rate")
+ .flags(total)
+ ;
+ ROB_occ_rate = ROB_count / cpu->numCycles;
+
+ ROB_occ_dist
+ .init(cpu->number_of_threads,0,numROBEntries,2)
+ .name(name() + ".ROB:occ_dist")
+ .desc("ROB Occupancy per cycle")
+ .flags(total | cdf)
+ ;
+
+ IQ.regStats();
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
+{
+ comm = _comm;
+ toIEW = comm->getWire(0);
+ fromCommit = comm->getWire(-1);
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::tick()
+{
+ DPRINTF(BE, "Ticking back end\n");
+
+ ROB_count[0]+= numInsts;
+
+ wbCycle = 0;
+
+ if (xcSquash) {
+ squashFromXC();
+ }
+
+ // Read in any done instruction information and update the IQ or LSQ.
+ updateStructures();
+
+ if (dispatchStatus != Blocked) {
+ d2i.advance();
+ dispatchInsts();
+ } else {
+ checkDispatchStatus();
+ }
+
+ i2e.advance();
+ scheduleReadyInsts();
+
+ e2c.advance();
+ executeInsts();
+
+ numInstsToWB.advance();
+ writebackInsts();
+
+ commitInsts();
+
+ DPRINTF(BE, "IQ entries in use: %i, ROB entries in use: %i, LSQ loads: %i, LSQ stores: %i\n",
+ IQ.numInsts, numInsts, LSQ.numLoads(), LSQ.numStores());
+
+ assert(numInsts == instList.size());
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::updateStructures()
+{
+ if (fromCommit->doneSeqNum) {
+ IQ.commit(fromCommit->doneSeqNum);
+ LSQ.commitLoads(fromCommit->doneSeqNum);
+ LSQ.commitStores(fromCommit->doneSeqNum);
+ }
+
+ if (fromCommit->nonSpecSeqNum) {
+ if (fromCommit->uncached) {
+ LSQ.executeLoad(fromCommit->lqIdx);
+ } else {
+ IQ.scheduleNonSpec(
+ fromCommit->nonSpecSeqNum);
+ }
+ }
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::addToIQ(DynInstPtr &inst)
+{
+ // Do anything IQ specific here?
+ IQ.insert(inst);
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::addToLSQ(DynInstPtr &inst)
+{
+ // Do anything LSQ specific here?
+ LSQ.insert(inst);
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::dispatchInsts()
+{
+ DPRINTF(BE, "Trying to dispatch instructions.\n");
+
+ // Pull instructions out of the front end.
+ int disp_width = dispatchWidth ? dispatchWidth : width;
+
+ // Could model dispatching time, but in general 1 cycle is probably
+ // good enough.
+
+ if (dispatchSize < numDispatchEntries) {
+ for (int i = 0; i < disp_width; i++) {
+ // Get instructions
+ DynInstPtr inst = frontEnd->getInst();
+
+ if (!inst) {
+ // No more instructions to get
+ break;
+ }
+
+ DPRINTF(BE, "Processing instruction [sn:%lli] PC:%#x\n",
+ inst->seqNum, inst->readPC());
+
+ for (int i = 0; i < inst->numDestRegs(); ++i)
+ renameTable[inst->destRegIdx(i)] = inst;
+
+ // Add to queue to be dispatched.
+ dispatch.push_back(inst);
+
+ d2i[0].size++;
+ ++dispatchSize;
+ }
+ }
+
+ assert(dispatch.size() < 64);
+
+ for (int i = 0; i < instsToDispatch->size; ++i) {
+ assert(!dispatch.empty());
+ // Get instruction from front of time buffer
+ DynInstPtr inst = dispatch.front();
+ dispatch.pop_front();
+ --dispatchSize;
+
+ if (inst->isSquashed())
+ continue;
+
+ ++numInsts;
+ instList.push_back(inst);
+
+ DPRINTF(BE, "Dispatching instruction [sn:%lli] PC:%#x\n",
+ inst->seqNum, inst->readPC());
+
+ addToIQ(inst);
+
+ if (inst->isMemRef()) {
+ addToLSQ(inst);
+ }
+
+ if (inst->isNonSpeculative()) {
+ inst->setCanCommit();
+ }
+
+ // Check if IQ or LSQ is full. If so we'll need to break and stop
+ // removing instructions. Also update the number of insts to remove
+ // from the queue.
+ if (exactFullStall) {
+ bool stall = false;
+ if (IQ.isFull()) {
+ DPRINTF(BE, "IQ is full!\n");
+ stall = true;
+ } else if (LSQ.isFull()) {
+ DPRINTF(BE, "LSQ is full!\n");
+ stall = true;
+ } else if (isFull()) {
+ DPRINTF(BE, "ROB is full!\n");
+ stall = true;
+ ROB_fcount++;
+ }
+ if (stall) {
+ instsToDispatch->size-= i+1;
+ dispatchStall();
+ return;
+ }
+ }
+ }
+
+ // Check if IQ or LSQ is full. If so we'll need to break and stop
+ // removing instructions. Also update the number of insts to remove
+ // from the queue. Check here if we don't care about exact stall
+ // conditions.
+
+ bool stall = false;
+ if (IQ.isFull()) {
+ DPRINTF(BE, "IQ is full!\n");
+ stall = true;
+ } else if (LSQ.isFull()) {
+ DPRINTF(BE, "LSQ is full!\n");
+ stall = true;
+ } else if (isFull()) {
+ DPRINTF(BE, "ROB is full!\n");
+ stall = true;
+ ROB_fcount++;
+ }
+ if (stall) {
+ d2i.advance();
+ dispatchStall();
+ return;
+ }
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::dispatchStall()
+{
+ dispatchStatus = Blocked;
+ if (!cpu->decoupledFrontEnd) {
+ // Tell front end to stall here through a timebuffer, or just tell
+ // it directly.
+ }
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::checkDispatchStatus()
+{
+ DPRINTF(BE, "Checking dispatch status\n");
+ assert(dispatchStatus == Blocked);
+ if (!IQ.isFull() && !LSQ.isFull() && !isFull()) {
+ DPRINTF(BE, "Dispatch no longer blocked\n");
+ dispatchStatus = Running;
+ dispatchInsts();
+ }
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::scheduleReadyInsts()
+{
+ // Tell IQ to put any ready instructions into the instruction list.
+ // Probably want to have a list of DynInstPtrs returned here. Then I
+ // can choose to either put them into a time buffer to simulate
+ // IQ scheduling time, or hand them directly off to the next stage.
+ // Do you ever want to directly hand it off to the next stage?
+ DPRINTF(BE, "Trying to schedule ready instructions\n");
+ IQ.scheduleReadyInsts();
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::executeInsts()
+{
+ int insts_to_execute = instsToExecute->size;
+
+ issued_ops[0]+= insts_to_execute;
+ n_issued_dist[insts_to_execute]++;
+
+ DPRINTF(BE, "Trying to execute %i instructions\n", insts_to_execute);
+
+ fetchRedirect[0] = false;
+
+ while (insts_to_execute > 0) {
+ // Get ready instruction from the IQ (or queue coming out of IQ)
+ // Execute the ready instruction.
+ // Wakeup any dependents if it's done.
+ DynInstPtr inst = IQ.getReadyInst();
+
+ DPRINTF(BE, "Executing inst [sn:%lli] PC: %#x\n",
+ inst->seqNum, inst->readPC());
+
+ ++funcExeInst;
+
+ // Check if the instruction is squashed; if so then skip it
+ // and don't count it towards the FU usage.
+ if (inst->isSquashed()) {
+ DPRINTF(BE, "Execute: Instruction was squashed.\n");
+
+ // Not sure how to handle this plus the method of sending # of
+ // instructions to use. Probably will just have to count it
+ // towards the bandwidth usage, but not the FU usage.
+ --insts_to_execute;
+
+ // Consider this instruction executed so that commit can go
+ // ahead and retire the instruction.
+ inst->setExecuted();
+
+ // Not sure if I should set this here or just let commit try to
+ // commit any squashed instructions. I like the latter a bit more.
+ inst->setCanCommit();
+
+// ++iewExecSquashedInsts;
+
+ continue;
+ }
+
+ Fault fault = NoFault;
+
+ // Execute instruction.
+ // Note that if the instruction faults, it will be handled
+ // at the commit stage.
+ if (inst->isMemRef() &&
+ (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
+ DPRINTF(BE, "Execute: Initiating access for memory "
+ "reference.\n");
+
+ // Tell the LDSTQ to execute this instruction (if it is a load).
+ if (inst->isLoad()) {
+ // Loads will mark themselves as executed, and their writeback
+ // event adds the instruction to the queue to commit
+ fault = LSQ.executeLoad(inst);
+
+// ++iewExecLoadInsts;
+ } else if (inst->isStore()) {
+ LSQ.executeStore(inst);
+
+// ++iewExecStoreInsts;
+
+ if (!(inst->req->flags & LOCKED)) {
+ inst->setExecuted();
+
+ instToCommit(inst);
+ }
+ // Store conditionals will mark themselves as executed, and
+ // their writeback event will add the instruction to the queue
+ // to commit.
+ } else {
+ panic("Unexpected memory type!\n");
+ }
+
+ } else {
+ inst->execute();
+
+// ++iewExecutedInsts;
+
+ inst->setExecuted();
+
+ instToCommit(inst);
+ }
+
+ updateExeInstStats(inst);
+
+ // Probably should have some sort of function for this.
+ // More general question of how to handle squashes? Have some sort of
+ // squash unit that controls it? Probably...
+ // Check if branch was correct. This check happens after the
+ // instruction is added to the queue because even if the branch
+ // is mispredicted, the branch instruction itself is still valid.
+ // Only handle this if there hasn't already been something that
+ // redirects fetch in this group of instructions.
+
+ // This probably needs to prioritize the redirects if a different
+ // scheduler is used. Currently the scheduler schedules the oldest
+ // instruction first, so the branch resolution order will be correct.
+ unsigned tid = inst->threadNumber;
+
+ if (!fetchRedirect[tid]) {
+
+ if (inst->mispredicted()) {
+ fetchRedirect[tid] = true;
+
+ DPRINTF(BE, "Execute: Branch mispredict detected.\n");
+ DPRINTF(BE, "Execute: Redirecting fetch to PC: %#x.\n",
+ inst->nextPC);
+
+ // If incorrect, then signal the ROB that it must be squashed.
+ squashDueToBranch(inst);
+
+ if (inst->predTaken()) {
+// predictedTakenIncorrect++;
+ } else {
+// predictedNotTakenIncorrect++;
+ }
+ } else if (LSQ.violation()) {
+ fetchRedirect[tid] = true;
+
+ // Get the DynInst that caused the violation. Note that this
+ // clears the violation signal.
+ DynInstPtr violator;
+ violator = LSQ.getMemDepViolator();
+
+ DPRINTF(BE, "LDSTQ detected a violation. Violator PC: "
+ "%#x, inst PC: %#x. Addr is: %#x.\n",
+ violator->readPC(), inst->readPC(), inst->physEffAddr);
+
+ // Tell the instruction queue that a violation has occured.
+// IQ.violation(inst, violator);
+
+ // Squash.
+// squashDueToMemOrder(inst,tid);
+ squashDueToBranch(inst);
+
+// ++memOrderViolationEvents;
+ } else if (LSQ.loadBlocked()) {
+ fetchRedirect[tid] = true;
+
+ DPRINTF(BE, "Load operation couldn't execute because the "
+ "memory system is blocked. PC: %#x [sn:%lli]\n",
+ inst->readPC(), inst->seqNum);
+
+ squashDueToMemBlocked(inst);
+ }
+ }
+
+// instList.pop_front();
+
+ --insts_to_execute;
+
+ // keep an instruction count
+ thread->numInst++;
+ thread->numInsts++;
+ }
+
+ assert(insts_to_execute >= 0);
+}
+
+template<class Impl>
+void
+BackEnd<Impl>::instToCommit(DynInstPtr &inst)
+{
+ int wb_width = wbWidth;
+ // First check the time slot that this instruction will write
+ // to. If there are free write ports at the time, then go ahead
+ // and write the instruction to that time. If there are not,
+ // keep looking back to see where's the first time there's a
+ // free slot. What happens if you run out of free spaces?
+ // For now naively assume that all instructions take one cycle.
+ // Otherwise would have to look into the time buffer based on the
+ // latency of the instruction.
+
+ DPRINTF(BE, "Sending instructions to commit [sn:%lli] PC %#x.\n",
+ inst->seqNum, inst->readPC());
+
+ while (numInstsToWB[wbCycle].size >= wb_width) {
+ ++wbCycle;
+
+ assert(wbCycle < 5);
+ }
+
+ // Add finished instruction to queue to commit.
+ writeback.push_back(inst);
+ numInstsToWB[wbCycle].size++;
+
+ if (wbCycle)
+ wb_penalized[0]++;
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::writebackInsts()
+{
+ int wb_width = wbWidth;
+ // Using this method I'm not quite sure how to prevent an
+ // instruction from waking its own dependents multiple times,
+ // without the guarantee that commit always has enough bandwidth
+ // to accept all instructions being written back. This guarantee
+ // might not be too unrealistic.
+ InstListIt wb_inst_it = writeback.begin();
+ InstListIt wb_end_it = writeback.end();
+ int inst_num = 0;
+ int consumer_insts = 0;
+
+ for (; inst_num < wb_width &&
+ wb_inst_it != wb_end_it; inst_num++) {
+ DynInstPtr inst = (*wb_inst_it);
+
+ // Some instructions will be sent to commit without having
+ // executed because they need commit to handle them.
+ // E.g. Uncached loads have not actually executed when they
+ // are first sent to commit. Instead commit must tell the LSQ
+ // when it's ready to execute the uncached load.
+ if (!inst->isSquashed()) {
+ DPRINTF(BE, "Writing back instruction [sn:%lli] PC %#x.\n",
+ inst->seqNum, inst->readPC());
+
+ inst->setCanCommit();
+ inst->setResultReady();
+
+ if (inst->isExecuted()) {
+ int dependents = IQ.wakeDependents(inst);
+ if (dependents) {
+ producer_inst[0]++;
+ consumer_insts+= dependents;
+ }
+ }
+ }
+
+ writeback.erase(wb_inst_it++);
+ }
+ LSQ.writebackStores();
+ consumer_inst[0]+= consumer_insts;
+ writeback_count[0]+= inst_num;
+}
+
+template <class Impl>
+bool
+BackEnd<Impl>::commitInst(int inst_num)
+{
+ // Read instruction from the head of the ROB
+ DynInstPtr inst = instList.front();
+
+ // Make sure instruction is valid
+ assert(inst);
+
+ if (!inst->readyToCommit())
+ return false;
+
+ DPRINTF(BE, "Trying to commit instruction [sn:%lli] PC:%#x\n",
+ inst->seqNum, inst->readPC());
+
+ // If the instruction is not executed yet, then it is a non-speculative
+ // or store inst. Signal backwards that it should be executed.
+ if (!inst->isExecuted()) {
+ // Keep this number correct. We have not yet actually executed
+ // and committed this instruction.
+// thread->funcExeInst--;
+
+ if (inst->isNonSpeculative()) {
+#if !FULL_SYSTEM
+ // Hack to make sure syscalls aren't executed until all stores
+ // write back their data. This direct communication shouldn't
+ // be used for anything other than this.
+ if (inst_num > 0 || LSQ.hasStoresToWB()) {
+ DPRINTF(BE, "Waiting for all stores to writeback.\n");
+ return false;
+ }
+#endif
+
+ DPRINTF(BE, "Encountered a store or non-speculative "
+ "instruction at the head of the ROB, PC %#x.\n",
+ inst->readPC());
+
+ // Send back the non-speculative instruction's sequence number.
+ toIEW->nonSpecSeqNum = inst->seqNum;
+
+ // Change the instruction so it won't try to commit again until
+ // it is executed.
+ inst->clearCanCommit();
+
+// ++commitNonSpecStalls;
+
+ return false;
+ } else if (inst->isLoad()) {
+ DPRINTF(BE, "[sn:%lli]: Uncached load, PC %#x.\n",
+ inst->seqNum, inst->readPC());
+
+ // Send back the non-speculative instruction's sequence
+ // number. Maybe just tell the lsq to re-execute the load.
+ toIEW->nonSpecSeqNum = inst->seqNum;
+ toIEW->uncached = true;
+ toIEW->lqIdx = inst->lqIdx;
+
+ inst->clearCanCommit();
+
+ return false;
+ } else {
+ panic("Trying to commit un-executed instruction "
+ "of unknown type!\n");
+ }
+ }
+
+ // Now check if it's one of the special trap or barrier or
+ // serializing instructions.
+ if (inst->isThreadSync())
+ {
+ // Not handled for now.
+ panic("Barrier instructions are not handled yet.\n");
+ }
+
+ // Check if the instruction caused a fault. If so, trap.
+ Fault inst_fault = inst->getFault();
+
+ if (inst_fault != NoFault) {
+ if (!inst->isNop()) {
+#if FULL_SYSTEM
+ DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n",
+ inst->seqNum, inst->readPC());
+
+// assert(!thread->inSyscall);
+
+// thread->inSyscall = true;
+
+ // Consider holding onto the trap and waiting until the trap event
+ // happens for this to be executed.
+ inst_fault->invoke(thread->getXCProxy());
+
+ // Exit state update mode to avoid accidental updating.
+// thread->inSyscall = false;
+
+// commitStatus = TrapPending;
+
+ // Generate trap squash event.
+// generateTrapEvent();
+
+ return false;
+#else // !FULL_SYSTEM
+ panic("fault (%d) detected @ PC %08p", inst_fault,
+ inst->PC);
+#endif // FULL_SYSTEM
+ }
+ }
+
+ if (inst->isControl()) {
+// ++commitCommittedBranches;
+ }
+
+ int freed_regs = 0;
+
+ for (int i = 0; i < inst->numDestRegs(); ++i) {
+ DPRINTF(BE, "Commit rename map setting register %i to [sn:%lli]\n",
+ (int)inst->destRegIdx(i), inst->seqNum);
+ thread->renameTable[inst->destRegIdx(i)] = inst;
+ ++freed_regs;
+ }
+
+ if (inst->traceData) {
+ inst->traceData->finalize();
+ inst->traceData = NULL;
+ }
+
+ inst->clearDependents();
+
+ frontEnd->addFreeRegs(freed_regs);
+
+ instList.pop_front();
+
+ --numInsts;
+ cpu->numInst++;
+ thread->numInsts++;
+ ++thread->funcExeInst;
+ thread->PC = inst->readNextPC();
+ updateComInstStats(inst);
+
+ // Write the done sequence number here.
+ toIEW->doneSeqNum = inst->seqNum;
+
+#if FULL_SYSTEM
+ int count = 0;
+ Addr oldpc;
+ do {
+ if (count == 0)
+ assert(!thread->inSyscall && !thread->trapPending);
+ oldpc = thread->readPC();
+ cpu->system->pcEventQueue.service(
+ thread->getXCProxy());
+ count++;
+ } while (oldpc != thread->readPC());
+ if (count > 1) {
+ DPRINTF(BE, "PC skip function event, stopping commit\n");
+// completed_last_inst = false;
+// squashPending = true;
+ return false;
+ }
+#endif
+ return true;
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::commitInsts()
+{
+ int commit_width = commitWidth ? commitWidth : width;
+
+ // Not sure this should be a loop or not.
+ int inst_num = 0;
+ while (!instList.empty() && inst_num < commit_width) {
+ if (instList.front()->isSquashed()) {
+ panic("No squashed insts should still be on the list!");
+ instList.front()->clearDependents();
+ instList.pop_front();
+ continue;
+ }
+
+ if (!commitInst(inst_num++)) {
+ break;
+ }
+ }
+ n_committed_dist.sample(inst_num);
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::squash(const InstSeqNum &sn)
+{
+ IQ.squash(sn);
+ LSQ.squash(sn);
+
+ int freed_regs = 0;
+ InstListIt dispatch_end = dispatch.end();
+ InstListIt insts_it = dispatch.end();
+ insts_it--;
+
+ while (insts_it != dispatch_end && (*insts_it)->seqNum > sn)
+ {
+ if ((*insts_it)->isSquashed()) {
+ --insts_it;
+ continue;
+ }
+ DPRINTF(BE, "Squashing instruction on dispatch list PC %#x, [sn:%lli].\n",
+ (*insts_it)->readPC(),
+ (*insts_it)->seqNum);
+
+ // Mark the instruction as squashed, and ready to commit so that
+ // it can drain out of the pipeline.
+ (*insts_it)->setSquashed();
+
+ (*insts_it)->setCanCommit();
+
+ // Be careful with IPRs and such here
+ for (int i = 0; i < (*insts_it)->numDestRegs(); ++i) {
+ DynInstPtr prev_dest = (*insts_it)->getPrevDestInst(i);
+ DPRINTF(BE, "Commit rename map setting register %i to [sn:%lli]\n",
+ (int)(*insts_it)->destRegIdx(i), prev_dest);
+ renameTable[(*insts_it)->destRegIdx(i)] = prev_dest;
+ ++freed_regs;
+ }
+
+ (*insts_it)->clearDependents();
+
+ --insts_it;
+ }
+
+ insts_it = instList.end();
+ insts_it--;
+
+ while (!instList.empty() && (*insts_it)->seqNum > sn)
+ {
+ if ((*insts_it)->isSquashed()) {
+ --insts_it;
+ continue;
+ }
+ DPRINTF(BE, "Squashing instruction on inst list PC %#x, [sn:%lli].\n",
+ (*insts_it)->readPC(),
+ (*insts_it)->seqNum);
+
+ // Mark the instruction as squashed, and ready to commit so that
+ // it can drain out of the pipeline.
+ (*insts_it)->setSquashed();
+
+ (*insts_it)->setCanCommit();
+
+ for (int i = 0; i < (*insts_it)->numDestRegs(); ++i) {
+ DynInstPtr prev_dest = (*insts_it)->getPrevDestInst(i);
+ DPRINTF(BE, "Commit rename map setting register %i to [sn:%lli]\n",
+ (int)(*insts_it)->destRegIdx(i), prev_dest);
+ renameTable[(*insts_it)->destRegIdx(i)] = prev_dest;
+ ++freed_regs;
+ }
+
+ (*insts_it)->clearDependents();
+
+ instList.erase(insts_it--);
+ --numInsts;
+ }
+
+ frontEnd->addFreeRegs(freed_regs);
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::squashFromXC()
+{
+ xcSquash = true;
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::squashDueToBranch(DynInstPtr &inst)
+{
+ // Update the branch predictor state I guess
+ squash(inst->seqNum);
+ frontEnd->squash(inst->seqNum, inst->readNextPC(),
+ true, inst->mispredicted());
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::squashDueToMemBlocked(DynInstPtr &inst)
+{
+ DPRINTF(IEW, "Memory blocked, squashing load and younger insts, "
+ "PC: %#x [sn:%i].\n", inst->readPC(), inst->seqNum);
+
+ squash(inst->seqNum - 1);
+ frontEnd->squash(inst->seqNum - 1, inst->readPC());
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::fetchFault(Fault &fault)
+{
+ faultFromFetch = fault;
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::updateExeInstStats(DynInstPtr &inst)
+{
+ int thread_number = inst->threadNumber;
+
+ //
+ // Pick off the software prefetches
+ //
+#ifdef TARGET_ALPHA
+ if (inst->isDataPrefetch())
+ exe_swp[thread_number]++;
+ else
+ exe_inst[thread_number]++;
+#else
+ exe_inst[thread_number]++;
+#endif
+
+ //
+ // Control operations
+ //
+ if (inst->isControl())
+ exe_branches[thread_number]++;
+
+ //
+ // Memory operations
+ //
+ if (inst->isMemRef()) {
+ exe_refs[thread_number]++;
+
+ if (inst->isLoad())
+ exe_loads[thread_number]++;
+ }
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::updateComInstStats(DynInstPtr &inst)
+{
+ unsigned thread = inst->threadNumber;
+
+ //
+ // Pick off the software prefetches
+ //
+#ifdef TARGET_ALPHA
+ if (inst->isDataPrefetch()) {
+ stat_com_swp[thread]++;
+ } else {
+ stat_com_inst[thread]++;
+ }
+#else
+ stat_com_inst[thread]++;
+#endif
+
+ //
+ // Control Instructions
+ //
+ if (inst->isControl())
+ stat_com_branches[thread]++;
+
+ //
+ // Memory references
+ //
+ if (inst->isMemRef()) {
+ stat_com_refs[thread]++;
+
+ if (inst->isLoad()) {
+ stat_com_loads[thread]++;
+ }
+ }
+
+ if (inst->isMemBarrier()) {
+ stat_com_membars[thread]++;
+ }
+}
+
+template <class Impl>
+void
+BackEnd<Impl>::dumpInsts()
+{
+ int num = 0;
+ int valid_num = 0;
+
+ InstListIt inst_list_it = instList.begin();
+
+ cprintf("Inst list size: %i\n", instList.size());
+
+ while (inst_list_it != instList.end())
+ {
+ cprintf("Instruction:%i\n",
+ num);
+ if (!(*inst_list_it)->isSquashed()) {
+ if (!(*inst_list_it)->isIssued()) {
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ } else if ((*inst_list_it)->isMemRef() &&
+ !(*inst_list_it)->memOpDone) {
+ // Loads that have not been marked as executed still count
+ // towards the total instructions.
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ }
+ }
+
+ cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
+ "Issued:%i\nSquashed:%i\n",
+ (*inst_list_it)->readPC(),
+ (*inst_list_it)->seqNum,
+ (*inst_list_it)->threadNumber,
+ (*inst_list_it)->isIssued(),
+ (*inst_list_it)->isSquashed());
+
+ if ((*inst_list_it)->isMemRef()) {
+ cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
+ }
+
+ cprintf("\n");
+
+ inst_list_it++;
+ ++num;
+ }
+
+ cprintf("Dispatch list size: %i\n", dispatch.size());
+
+ inst_list_it = dispatch.begin();
+
+ while (inst_list_it != dispatch.end())
+ {
+ cprintf("Instruction:%i\n",
+ num);
+ if (!(*inst_list_it)->isSquashed()) {
+ if (!(*inst_list_it)->isIssued()) {
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ } else if ((*inst_list_it)->isMemRef() &&
+ !(*inst_list_it)->memOpDone) {
+ // Loads that have not been marked as executed still count
+ // towards the total instructions.
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ }
+ }
+
+ cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
+ "Issued:%i\nSquashed:%i\n",
+ (*inst_list_it)->readPC(),
+ (*inst_list_it)->seqNum,
+ (*inst_list_it)->threadNumber,
+ (*inst_list_it)->isIssued(),
+ (*inst_list_it)->isSquashed());
+
+ if ((*inst_list_it)->isMemRef()) {
+ cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
+ }
+
+ cprintf("\n");
+
+ inst_list_it++;
+ ++num;
+ }
+
+ cprintf("Writeback list size: %i\n", writeback.size());
+
+ inst_list_it = writeback.begin();
+
+ while (inst_list_it != writeback.end())
+ {
+ cprintf("Instruction:%i\n",
+ num);
+ if (!(*inst_list_it)->isSquashed()) {
+ if (!(*inst_list_it)->isIssued()) {
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ } else if ((*inst_list_it)->isMemRef() &&
+ !(*inst_list_it)->memOpDone) {
+ // Loads that have not been marked as executed still count
+ // towards the total instructions.
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ }
+ }
+
+ cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
+ "Issued:%i\nSquashed:%i\n",
+ (*inst_list_it)->readPC(),
+ (*inst_list_it)->seqNum,
+ (*inst_list_it)->threadNumber,
+ (*inst_list_it)->isIssued(),
+ (*inst_list_it)->isSquashed());
+
+ if ((*inst_list_it)->isMemRef()) {
+ cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
+ }
+
+ cprintf("\n");
+
+ inst_list_it++;
+ ++num;
+ }
+}
diff --git a/cpu/ozone/cpu_builder.cc b/cpu/ozone/cpu_builder.cc
new file mode 100644
index 000000000..64aa49c71
--- /dev/null
+++ b/cpu/ozone/cpu_builder.cc
@@ -0,0 +1,830 @@
+
+#include <string>
+
+#include "cpu/checker/cpu.hh"
+#include "cpu/inst_seq.hh"
+#include "cpu/ozone/cpu.hh"
+#include "cpu/ozone/ozone_impl.hh"
+#include "cpu/ozone/simple_impl.hh"
+#include "cpu/ozone/simple_params.hh"
+#include "mem/cache/base_cache.hh"
+#include "sim/builder.hh"
+#include "sim/process.hh"
+#include "sim/sim_object.hh"
+
+class DerivOzoneCPU : public OzoneCPU<OzoneImpl>
+{
+ public:
+ DerivOzoneCPU(SimpleParams *p)
+ : OzoneCPU<OzoneImpl>(p)
+ { }
+};
+
+class SimpleOzoneCPU : public OzoneCPU<SimpleImpl>
+{
+ public:
+ SimpleOzoneCPU(SimpleParams *p)
+ : OzoneCPU<SimpleImpl>(p)
+ { }
+};
+
+
+////////////////////////////////////////////////////////////////////////
+//
+// OzoneCPU Simulation Object
+//
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
+
+ Param<int> clock;
+ Param<int> numThreads;
+
+#if FULL_SYSTEM
+SimObjectParam<System *> system;
+Param<int> cpu_id;
+SimObjectParam<AlphaITB *> itb;
+SimObjectParam<AlphaDTB *> dtb;
+#else
+SimObjectVectorParam<Process *> workload;
+//SimObjectParam<PageTable *> page_table;
+#endif // FULL_SYSTEM
+
+SimObjectParam<FunctionalMemory *> mem;
+
+SimObjectParam<BaseCPU *> checker;
+
+Param<Counter> max_insts_any_thread;
+Param<Counter> max_insts_all_threads;
+Param<Counter> max_loads_any_thread;
+Param<Counter> max_loads_all_threads;
+
+SimObjectParam<BaseCache *> icache;
+SimObjectParam<BaseCache *> dcache;
+
+Param<unsigned> cachePorts;
+Param<unsigned> width;
+Param<unsigned> frontEndWidth;
+Param<unsigned> backEndWidth;
+Param<unsigned> backEndSquashLatency;
+Param<unsigned> backEndLatency;
+Param<unsigned> maxInstBufferSize;
+Param<unsigned> numPhysicalRegs;
+Param<unsigned> maxOutstandingMemOps;
+
+Param<unsigned> decodeToFetchDelay;
+Param<unsigned> renameToFetchDelay;
+Param<unsigned> iewToFetchDelay;
+Param<unsigned> commitToFetchDelay;
+Param<unsigned> fetchWidth;
+
+Param<unsigned> renameToDecodeDelay;
+Param<unsigned> iewToDecodeDelay;
+Param<unsigned> commitToDecodeDelay;
+Param<unsigned> fetchToDecodeDelay;
+Param<unsigned> decodeWidth;
+
+Param<unsigned> iewToRenameDelay;
+Param<unsigned> commitToRenameDelay;
+Param<unsigned> decodeToRenameDelay;
+Param<unsigned> renameWidth;
+
+Param<unsigned> commitToIEWDelay;
+Param<unsigned> renameToIEWDelay;
+Param<unsigned> issueToExecuteDelay;
+Param<unsigned> issueWidth;
+Param<unsigned> executeWidth;
+Param<unsigned> executeIntWidth;
+Param<unsigned> executeFloatWidth;
+Param<unsigned> executeBranchWidth;
+Param<unsigned> executeMemoryWidth;
+
+Param<unsigned> iewToCommitDelay;
+Param<unsigned> renameToROBDelay;
+Param<unsigned> commitWidth;
+Param<unsigned> squashWidth;
+
+Param<unsigned> localPredictorSize;
+Param<unsigned> localCtrBits;
+Param<unsigned> localHistoryTableSize;
+Param<unsigned> localHistoryBits;
+Param<unsigned> globalPredictorSize;
+Param<unsigned> globalCtrBits;
+Param<unsigned> globalHistoryBits;
+Param<unsigned> choicePredictorSize;
+Param<unsigned> choiceCtrBits;
+
+Param<unsigned> BTBEntries;
+Param<unsigned> BTBTagSize;
+
+Param<unsigned> RASSize;
+
+Param<unsigned> LQEntries;
+Param<unsigned> SQEntries;
+Param<unsigned> LFSTSize;
+Param<unsigned> SSITSize;
+
+Param<unsigned> numPhysIntRegs;
+Param<unsigned> numPhysFloatRegs;
+Param<unsigned> numIQEntries;
+Param<unsigned> numROBEntries;
+
+Param<bool> decoupledFrontEnd;
+Param<int> dispatchWidth;
+Param<int> wbWidth;
+
+Param<unsigned> smtNumFetchingThreads;
+Param<std::string> smtFetchPolicy;
+Param<std::string> smtLSQPolicy;
+Param<unsigned> smtLSQThreshold;
+Param<std::string> smtIQPolicy;
+Param<unsigned> smtIQThreshold;
+Param<std::string> smtROBPolicy;
+Param<unsigned> smtROBThreshold;
+Param<std::string> smtCommitPolicy;
+
+Param<unsigned> instShiftAmt;
+
+Param<bool> defer_registration;
+
+Param<bool> function_trace;
+Param<Tick> function_trace_start;
+
+END_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
+
+ INIT_PARAM(clock, "clock speed"),
+ INIT_PARAM(numThreads, "number of HW thread contexts"),
+
+#if FULL_SYSTEM
+ INIT_PARAM(system, "System object"),
+ INIT_PARAM(cpu_id, "processor ID"),
+ INIT_PARAM(itb, "Instruction translation buffer"),
+ INIT_PARAM(dtb, "Data translation buffer"),
+#else
+ INIT_PARAM(workload, "Processes to run"),
+// INIT_PARAM(page_table, "Page table"),
+#endif // FULL_SYSTEM
+
+ INIT_PARAM_DFLT(mem, "Memory", NULL),
+
+ INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
+
+ INIT_PARAM_DFLT(max_insts_any_thread,
+ "Terminate when any thread reaches this inst count",
+ 0),
+ INIT_PARAM_DFLT(max_insts_all_threads,
+ "Terminate when all threads have reached"
+ "this inst count",
+ 0),
+ INIT_PARAM_DFLT(max_loads_any_thread,
+ "Terminate when any thread reaches this load count",
+ 0),
+ INIT_PARAM_DFLT(max_loads_all_threads,
+ "Terminate when all threads have reached this load"
+ "count",
+ 0),
+
+ INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
+ INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
+
+ INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
+ INIT_PARAM_DFLT(width, "Width", 1),
+ INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
+ INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
+ INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
+ INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
+ INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
+ INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
+ INIT_PARAM_DFLT(maxOutstandingMemOps, "Maximum outstanding memory operations", 4),
+
+ INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
+ INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
+ INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
+ "delay"),
+ INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
+ INIT_PARAM(fetchWidth, "Fetch width"),
+ INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
+ INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
+ "delay"),
+ INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
+ INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
+ INIT_PARAM(decodeWidth, "Decode width"),
+
+ INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
+ "delay"),
+ INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
+ INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
+ INIT_PARAM(renameWidth, "Rename width"),
+
+ INIT_PARAM(commitToIEWDelay, "Commit to "
+ "Issue/Execute/Writeback delay"),
+ INIT_PARAM(renameToIEWDelay, "Rename to "
+ "Issue/Execute/Writeback delay"),
+ INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
+ "to the IEW stage)"),
+ INIT_PARAM(issueWidth, "Issue width"),
+ INIT_PARAM(executeWidth, "Execute width"),
+ INIT_PARAM(executeIntWidth, "Integer execute width"),
+ INIT_PARAM(executeFloatWidth, "Floating point execute width"),
+ INIT_PARAM(executeBranchWidth, "Branch execute width"),
+ INIT_PARAM(executeMemoryWidth, "Memory execute width"),
+
+ INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
+ "delay"),
+ INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
+ INIT_PARAM(commitWidth, "Commit width"),
+ INIT_PARAM(squashWidth, "Squash width"),
+
+ INIT_PARAM(localPredictorSize, "Size of local predictor"),
+ INIT_PARAM(localCtrBits, "Bits per counter"),
+ INIT_PARAM(localHistoryTableSize, "Size of local history table"),
+ INIT_PARAM(localHistoryBits, "Bits for the local history"),
+ INIT_PARAM(globalPredictorSize, "Size of global predictor"),
+ INIT_PARAM(globalCtrBits, "Bits per counter"),
+ INIT_PARAM(globalHistoryBits, "Bits of history"),
+ INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
+ INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
+
+ INIT_PARAM(BTBEntries, "Number of BTB entries"),
+ INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
+
+ INIT_PARAM(RASSize, "RAS size"),
+
+ INIT_PARAM(LQEntries, "Number of load queue entries"),
+ INIT_PARAM(SQEntries, "Number of store queue entries"),
+ INIT_PARAM(LFSTSize, "Last fetched store table size"),
+ INIT_PARAM(SSITSize, "Store set ID table size"),
+
+ INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
+ INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
+ "registers"),
+ INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
+ INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
+
+ INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
+ INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
+ INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
+
+ INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
+ INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
+ INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
+ INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
+ INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
+ INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
+ INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
+ INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
+ INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
+
+ INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
+ INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
+
+ INIT_PARAM(function_trace, "Enable function trace"),
+ INIT_PARAM(function_trace_start, "Cycle to start function trace")
+
+END_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
+
+CREATE_SIM_OBJECT(DerivOzoneCPU)
+{
+ DerivOzoneCPU *cpu;
+
+#if FULL_SYSTEM
+ // Full-system only supports a single thread for the moment.
+ int actual_num_threads = 1;
+#else
+ // In non-full-system mode, we infer the number of threads from
+ // the workload if it's not explicitly specified.
+ int actual_num_threads =
+ numThreads.isValid() ? numThreads : workload.size();
+
+ if (workload.size() == 0) {
+ fatal("Must specify at least one workload!");
+ }
+
+#endif
+
+ SimpleParams *params = new SimpleParams;
+
+ params->clock = clock;
+
+ params->name = getInstanceName();
+ params->numberOfThreads = actual_num_threads;
+
+#if FULL_SYSTEM
+ params->system = system;
+ params->cpu_id = cpu_id;
+ params->itb = itb;
+ params->dtb = dtb;
+#else
+ params->workload = workload;
+// params->pTable = page_table;
+#endif // FULL_SYSTEM
+
+ params->mem = mem;
+ params->checker = checker;
+ params->max_insts_any_thread = max_insts_any_thread;
+ params->max_insts_all_threads = max_insts_all_threads;
+ params->max_loads_any_thread = max_loads_any_thread;
+ params->max_loads_all_threads = max_loads_all_threads;
+
+ //
+ // Caches
+ //
+ params->icacheInterface = icache ? icache->getInterface() : NULL;
+ params->dcacheInterface = dcache ? dcache->getInterface() : NULL;
+ params->cachePorts = cachePorts;
+
+ params->width = width;
+ params->frontEndWidth = frontEndWidth;
+ params->backEndWidth = backEndWidth;
+ params->backEndSquashLatency = backEndSquashLatency;
+ params->backEndLatency = backEndLatency;
+ params->maxInstBufferSize = maxInstBufferSize;
+ params->numPhysicalRegs = numPhysIntRegs + numPhysFloatRegs;
+ params->maxOutstandingMemOps = maxOutstandingMemOps;
+
+ params->decodeToFetchDelay = decodeToFetchDelay;
+ params->renameToFetchDelay = renameToFetchDelay;
+ params->iewToFetchDelay = iewToFetchDelay;
+ params->commitToFetchDelay = commitToFetchDelay;
+ params->fetchWidth = fetchWidth;
+
+ params->renameToDecodeDelay = renameToDecodeDelay;
+ params->iewToDecodeDelay = iewToDecodeDelay;
+ params->commitToDecodeDelay = commitToDecodeDelay;
+ params->fetchToDecodeDelay = fetchToDecodeDelay;
+ params->decodeWidth = decodeWidth;
+
+ params->iewToRenameDelay = iewToRenameDelay;
+ params->commitToRenameDelay = commitToRenameDelay;
+ params->decodeToRenameDelay = decodeToRenameDelay;
+ params->renameWidth = renameWidth;
+
+ params->commitToIEWDelay = commitToIEWDelay;
+ params->renameToIEWDelay = renameToIEWDelay;
+ params->issueToExecuteDelay = issueToExecuteDelay;
+ params->issueWidth = issueWidth;
+ params->executeWidth = executeWidth;
+ params->executeIntWidth = executeIntWidth;
+ params->executeFloatWidth = executeFloatWidth;
+ params->executeBranchWidth = executeBranchWidth;
+ params->executeMemoryWidth = executeMemoryWidth;
+
+ params->iewToCommitDelay = iewToCommitDelay;
+ params->renameToROBDelay = renameToROBDelay;
+ params->commitWidth = commitWidth;
+ params->squashWidth = squashWidth;
+
+
+ params->localPredictorSize = localPredictorSize;
+ params->localCtrBits = localCtrBits;
+ params->localHistoryTableSize = localHistoryTableSize;
+ params->localHistoryBits = localHistoryBits;
+ params->globalPredictorSize = globalPredictorSize;
+ params->globalCtrBits = globalCtrBits;
+ params->globalHistoryBits = globalHistoryBits;
+ params->choicePredictorSize = choicePredictorSize;
+ params->choiceCtrBits = choiceCtrBits;
+
+ params->BTBEntries = BTBEntries;
+ params->BTBTagSize = BTBTagSize;
+
+ params->RASSize = RASSize;
+
+ params->LQEntries = LQEntries;
+ params->SQEntries = SQEntries;
+
+ params->SSITSize = SSITSize;
+ params->LFSTSize = LFSTSize;
+
+ params->numPhysIntRegs = numPhysIntRegs;
+ params->numPhysFloatRegs = numPhysFloatRegs;
+ params->numIQEntries = numIQEntries;
+ params->numROBEntries = numROBEntries;
+
+ params->decoupledFrontEnd = decoupledFrontEnd;
+ params->dispatchWidth = dispatchWidth;
+ params->wbWidth = wbWidth;
+
+ params->smtNumFetchingThreads = smtNumFetchingThreads;
+ params->smtFetchPolicy = smtFetchPolicy;
+ params->smtIQPolicy = smtIQPolicy;
+ params->smtLSQPolicy = smtLSQPolicy;
+ params->smtLSQThreshold = smtLSQThreshold;
+ params->smtROBPolicy = smtROBPolicy;
+ params->smtROBThreshold = smtROBThreshold;
+ params->smtCommitPolicy = smtCommitPolicy;
+
+ params->instShiftAmt = 2;
+
+ params->deferRegistration = defer_registration;
+
+ params->functionTrace = function_trace;
+ params->functionTraceStart = function_trace_start;
+
+ cpu = new DerivOzoneCPU(params);
+
+ return cpu;
+}
+
+REGISTER_SIM_OBJECT("DerivOzoneCPU", DerivOzoneCPU)
+
+
+
+////////////////////////////////////////////////////////////////////////
+//
+// OzoneCPU Simulation Object
+//
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
+
+ Param<int> clock;
+ Param<int> numThreads;
+
+#if FULL_SYSTEM
+SimObjectParam<System *> system;
+Param<int> cpu_id;
+SimObjectParam<AlphaITB *> itb;
+SimObjectParam<AlphaDTB *> dtb;
+#else
+SimObjectVectorParam<Process *> workload;
+//SimObjectParam<PageTable *> page_table;
+#endif // FULL_SYSTEM
+
+SimObjectParam<FunctionalMemory *> mem;
+
+SimObjectParam<BaseCPU *> checker;
+
+Param<Counter> max_insts_any_thread;
+Param<Counter> max_insts_all_threads;
+Param<Counter> max_loads_any_thread;
+Param<Counter> max_loads_all_threads;
+
+SimObjectParam<BaseCache *> icache;
+SimObjectParam<BaseCache *> dcache;
+
+Param<unsigned> cachePorts;
+Param<unsigned> width;
+Param<unsigned> frontEndWidth;
+Param<unsigned> backEndWidth;
+Param<unsigned> backEndSquashLatency;
+Param<unsigned> backEndLatency;
+Param<unsigned> maxInstBufferSize;
+Param<unsigned> numPhysicalRegs;
+
+Param<unsigned> decodeToFetchDelay;
+Param<unsigned> renameToFetchDelay;
+Param<unsigned> iewToFetchDelay;
+Param<unsigned> commitToFetchDelay;
+Param<unsigned> fetchWidth;
+
+Param<unsigned> renameToDecodeDelay;
+Param<unsigned> iewToDecodeDelay;
+Param<unsigned> commitToDecodeDelay;
+Param<unsigned> fetchToDecodeDelay;
+Param<unsigned> decodeWidth;
+
+Param<unsigned> iewToRenameDelay;
+Param<unsigned> commitToRenameDelay;
+Param<unsigned> decodeToRenameDelay;
+Param<unsigned> renameWidth;
+
+Param<unsigned> commitToIEWDelay;
+Param<unsigned> renameToIEWDelay;
+Param<unsigned> issueToExecuteDelay;
+Param<unsigned> issueWidth;
+Param<unsigned> executeWidth;
+Param<unsigned> executeIntWidth;
+Param<unsigned> executeFloatWidth;
+Param<unsigned> executeBranchWidth;
+Param<unsigned> executeMemoryWidth;
+
+Param<unsigned> iewToCommitDelay;
+Param<unsigned> renameToROBDelay;
+Param<unsigned> commitWidth;
+Param<unsigned> squashWidth;
+
+Param<unsigned> localPredictorSize;
+Param<unsigned> localCtrBits;
+Param<unsigned> localHistoryTableSize;
+Param<unsigned> localHistoryBits;
+Param<unsigned> globalPredictorSize;
+Param<unsigned> globalCtrBits;
+Param<unsigned> globalHistoryBits;
+Param<unsigned> choicePredictorSize;
+Param<unsigned> choiceCtrBits;
+
+Param<unsigned> BTBEntries;
+Param<unsigned> BTBTagSize;
+
+Param<unsigned> RASSize;
+
+Param<unsigned> LQEntries;
+Param<unsigned> SQEntries;
+Param<unsigned> LFSTSize;
+Param<unsigned> SSITSize;
+
+Param<unsigned> numPhysIntRegs;
+Param<unsigned> numPhysFloatRegs;
+Param<unsigned> numIQEntries;
+Param<unsigned> numROBEntries;
+
+Param<bool> decoupledFrontEnd;
+Param<int> dispatchWidth;
+Param<int> wbWidth;
+
+Param<unsigned> smtNumFetchingThreads;
+Param<std::string> smtFetchPolicy;
+Param<std::string> smtLSQPolicy;
+Param<unsigned> smtLSQThreshold;
+Param<std::string> smtIQPolicy;
+Param<unsigned> smtIQThreshold;
+Param<std::string> smtROBPolicy;
+Param<unsigned> smtROBThreshold;
+Param<std::string> smtCommitPolicy;
+
+Param<unsigned> instShiftAmt;
+
+Param<bool> defer_registration;
+
+Param<bool> function_trace;
+Param<Tick> function_trace_start;
+
+END_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
+
+ INIT_PARAM(clock, "clock speed"),
+ INIT_PARAM(numThreads, "number of HW thread contexts"),
+
+#if FULL_SYSTEM
+ INIT_PARAM(system, "System object"),
+ INIT_PARAM(cpu_id, "processor ID"),
+ INIT_PARAM(itb, "Instruction translation buffer"),
+ INIT_PARAM(dtb, "Data translation buffer"),
+#else
+ INIT_PARAM(workload, "Processes to run"),
+// INIT_PARAM(page_table, "Page table"),
+#endif // FULL_SYSTEM
+
+ INIT_PARAM_DFLT(mem, "Memory", NULL),
+
+ INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
+
+ INIT_PARAM_DFLT(max_insts_any_thread,
+ "Terminate when any thread reaches this inst count",
+ 0),
+ INIT_PARAM_DFLT(max_insts_all_threads,
+ "Terminate when all threads have reached"
+ "this inst count",
+ 0),
+ INIT_PARAM_DFLT(max_loads_any_thread,
+ "Terminate when any thread reaches this load count",
+ 0),
+ INIT_PARAM_DFLT(max_loads_all_threads,
+ "Terminate when all threads have reached this load"
+ "count",
+ 0),
+
+ INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
+ INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
+
+ INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
+ INIT_PARAM_DFLT(width, "Width", 1),
+ INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
+ INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
+ INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
+ INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
+ INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
+ INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
+
+ INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
+ INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
+ INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
+ "delay"),
+ INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
+ INIT_PARAM(fetchWidth, "Fetch width"),
+ INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
+ INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
+ "delay"),
+ INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
+ INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
+ INIT_PARAM(decodeWidth, "Decode width"),
+
+ INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
+ "delay"),
+ INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
+ INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
+ INIT_PARAM(renameWidth, "Rename width"),
+
+ INIT_PARAM(commitToIEWDelay, "Commit to "
+ "Issue/Execute/Writeback delay"),
+ INIT_PARAM(renameToIEWDelay, "Rename to "
+ "Issue/Execute/Writeback delay"),
+ INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
+ "to the IEW stage)"),
+ INIT_PARAM(issueWidth, "Issue width"),
+ INIT_PARAM(executeWidth, "Execute width"),
+ INIT_PARAM(executeIntWidth, "Integer execute width"),
+ INIT_PARAM(executeFloatWidth, "Floating point execute width"),
+ INIT_PARAM(executeBranchWidth, "Branch execute width"),
+ INIT_PARAM(executeMemoryWidth, "Memory execute width"),
+
+ INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
+ "delay"),
+ INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
+ INIT_PARAM(commitWidth, "Commit width"),
+ INIT_PARAM(squashWidth, "Squash width"),
+
+ INIT_PARAM(localPredictorSize, "Size of local predictor"),
+ INIT_PARAM(localCtrBits, "Bits per counter"),
+ INIT_PARAM(localHistoryTableSize, "Size of local history table"),
+ INIT_PARAM(localHistoryBits, "Bits for the local history"),
+ INIT_PARAM(globalPredictorSize, "Size of global predictor"),
+ INIT_PARAM(globalCtrBits, "Bits per counter"),
+ INIT_PARAM(globalHistoryBits, "Bits of history"),
+ INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
+ INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
+
+ INIT_PARAM(BTBEntries, "Number of BTB entries"),
+ INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
+
+ INIT_PARAM(RASSize, "RAS size"),
+
+ INIT_PARAM(LQEntries, "Number of load queue entries"),
+ INIT_PARAM(SQEntries, "Number of store queue entries"),
+ INIT_PARAM(LFSTSize, "Last fetched store table size"),
+ INIT_PARAM(SSITSize, "Store set ID table size"),
+
+ INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
+ INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
+ "registers"),
+ INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
+ INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
+
+ INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
+ INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
+ INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
+
+ INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
+ INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
+ INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
+ INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
+ INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
+ INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
+ INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
+ INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
+ INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
+
+ INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
+ INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
+
+ INIT_PARAM(function_trace, "Enable function trace"),
+ INIT_PARAM(function_trace_start, "Cycle to start function trace")
+
+END_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
+
+CREATE_SIM_OBJECT(SimpleOzoneCPU)
+{
+ SimpleOzoneCPU *cpu;
+
+#if FULL_SYSTEM
+ // Full-system only supports a single thread for the moment.
+ int actual_num_threads = 1;
+#else
+ // In non-full-system mode, we infer the number of threads from
+ // the workload if it's not explicitly specified.
+ int actual_num_threads =
+ numThreads.isValid() ? numThreads : workload.size();
+
+ if (workload.size() == 0) {
+ fatal("Must specify at least one workload!");
+ }
+
+#endif
+
+ SimpleParams *params = new SimpleParams;
+
+ params->clock = clock;
+
+ params->name = getInstanceName();
+ params->numberOfThreads = actual_num_threads;
+
+#if FULL_SYSTEM
+ params->system = system;
+ params->cpu_id = cpu_id;
+ params->itb = itb;
+ params->dtb = dtb;
+#else
+ params->workload = workload;
+// params->pTable = page_table;
+#endif // FULL_SYSTEM
+
+ params->mem = mem;
+ params->checker = checker;
+ params->max_insts_any_thread = max_insts_any_thread;
+ params->max_insts_all_threads = max_insts_all_threads;
+ params->max_loads_any_thread = max_loads_any_thread;
+ params->max_loads_all_threads = max_loads_all_threads;
+
+ //
+ // Caches
+ //
+ params->icacheInterface = icache ? icache->getInterface() : NULL;
+ params->dcacheInterface = dcache ? dcache->getInterface() : NULL;
+ params->cachePorts = cachePorts;
+
+ params->width = width;
+ params->frontEndWidth = frontEndWidth;
+ params->backEndWidth = backEndWidth;
+ params->backEndSquashLatency = backEndSquashLatency;
+ params->backEndLatency = backEndLatency;
+ params->maxInstBufferSize = maxInstBufferSize;
+ params->numPhysicalRegs = numPhysIntRegs + numPhysFloatRegs;
+
+ params->decodeToFetchDelay = decodeToFetchDelay;
+ params->renameToFetchDelay = renameToFetchDelay;
+ params->iewToFetchDelay = iewToFetchDelay;
+ params->commitToFetchDelay = commitToFetchDelay;
+ params->fetchWidth = fetchWidth;
+
+ params->renameToDecodeDelay = renameToDecodeDelay;
+ params->iewToDecodeDelay = iewToDecodeDelay;
+ params->commitToDecodeDelay = commitToDecodeDelay;
+ params->fetchToDecodeDelay = fetchToDecodeDelay;
+ params->decodeWidth = decodeWidth;
+
+ params->iewToRenameDelay = iewToRenameDelay;
+ params->commitToRenameDelay = commitToRenameDelay;
+ params->decodeToRenameDelay = decodeToRenameDelay;
+ params->renameWidth = renameWidth;
+
+ params->commitToIEWDelay = commitToIEWDelay;
+ params->renameToIEWDelay = renameToIEWDelay;
+ params->issueToExecuteDelay = issueToExecuteDelay;
+ params->issueWidth = issueWidth;
+ params->executeWidth = executeWidth;
+ params->executeIntWidth = executeIntWidth;
+ params->executeFloatWidth = executeFloatWidth;
+ params->executeBranchWidth = executeBranchWidth;
+ params->executeMemoryWidth = executeMemoryWidth;
+
+ params->iewToCommitDelay = iewToCommitDelay;
+ params->renameToROBDelay = renameToROBDelay;
+ params->commitWidth = commitWidth;
+ params->squashWidth = squashWidth;
+
+
+ params->localPredictorSize = localPredictorSize;
+ params->localCtrBits = localCtrBits;
+ params->localHistoryTableSize = localHistoryTableSize;
+ params->localHistoryBits = localHistoryBits;
+ params->globalPredictorSize = globalPredictorSize;
+ params->globalCtrBits = globalCtrBits;
+ params->globalHistoryBits = globalHistoryBits;
+ params->choicePredictorSize = choicePredictorSize;
+ params->choiceCtrBits = choiceCtrBits;
+
+ params->BTBEntries = BTBEntries;
+ params->BTBTagSize = BTBTagSize;
+
+ params->RASSize = RASSize;
+
+ params->LQEntries = LQEntries;
+ params->SQEntries = SQEntries;
+
+ params->SSITSize = SSITSize;
+ params->LFSTSize = LFSTSize;
+
+ params->numPhysIntRegs = numPhysIntRegs;
+ params->numPhysFloatRegs = numPhysFloatRegs;
+ params->numIQEntries = numIQEntries;
+ params->numROBEntries = numROBEntries;
+
+ params->decoupledFrontEnd = decoupledFrontEnd;
+ params->dispatchWidth = dispatchWidth;
+ params->wbWidth = wbWidth;
+
+ params->smtNumFetchingThreads = smtNumFetchingThreads;
+ params->smtFetchPolicy = smtFetchPolicy;
+ params->smtIQPolicy = smtIQPolicy;
+ params->smtLSQPolicy = smtLSQPolicy;
+ params->smtLSQThreshold = smtLSQThreshold;
+ params->smtROBPolicy = smtROBPolicy;
+ params->smtROBThreshold = smtROBThreshold;
+ params->smtCommitPolicy = smtCommitPolicy;
+
+ params->instShiftAmt = 2;
+
+ params->deferRegistration = defer_registration;
+
+ params->functionTrace = function_trace;
+ params->functionTraceStart = function_trace_start;
+
+ cpu = new SimpleOzoneCPU(params);
+
+ return cpu;
+}
+
+REGISTER_SIM_OBJECT("SimpleOzoneCPU", SimpleOzoneCPU)
+
diff --git a/cpu/ozone/dyn_inst.cc b/cpu/ozone/dyn_inst.cc
new file mode 100644
index 000000000..3bf8b03ca
--- /dev/null
+++ b/cpu/ozone/dyn_inst.cc
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu/ozone/dyn_inst_impl.hh"
+#include "cpu/ozone/ozone_impl.hh"
+#include "cpu/ozone/simple_impl.hh"
+
+template class OzoneDynInst<OzoneImpl>;
+template class OzoneDynInst<SimpleImpl>;
+
diff --git a/cpu/ozone/dyn_inst.hh b/cpu/ozone/dyn_inst.hh
new file mode 100644
index 000000000..5d48bb361
--- /dev/null
+++ b/cpu/ozone/dyn_inst.hh
@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2005-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_OZONE_DYN_INST_HH__
+#define __CPU_OZONE_DYN_INST_HH__
+
+#include "arch/isa_traits.hh"
+#include "config/full_system.hh"
+#include "cpu/base_dyn_inst.hh"
+#include "cpu/ozone/cpu.hh" // MUST include this
+#include "cpu/inst_seq.hh"
+#include "cpu/ozone/simple_impl.hh" // Would be nice to not have to include this
+#include "cpu/ozone/ozone_impl.hh"
+
+#include <list>
+#include <vector>
+
+template <class Impl>
+class OzoneDynInst : public BaseDynInst<Impl>
+{
+ public:
+ // Typedefs
+ typedef typename Impl::FullCPU FullCPU;
+
+ typedef typename FullCPU::ImplState ImplState;
+
+ // Typedef for DynInstPtr. This is really just a RefCountingPtr<OoODynInst>.
+ typedef typename Impl::DynInstPtr DynInstPtr;
+
+ typedef TheISA::ExtMachInst ExtMachInst;
+ typedef TheISA::MachInst MachInst;
+ typedef TheISA::MiscReg MiscReg;
+ typedef typename std::list<DynInstPtr>::iterator ListIt;
+
+ // Note that this is duplicated from the BaseDynInst class; I'm
+ // simply not sure the enum would carry through so I could use it
+ // in array declarations in this class.
+ enum {
+ MaxInstSrcRegs = TheISA::MaxInstSrcRegs,
+ MaxInstDestRegs = TheISA::MaxInstDestRegs
+ };
+
+ OzoneDynInst(FullCPU *cpu);
+
+ OzoneDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
+ InstSeqNum seq_num, FullCPU *cpu);
+
+ OzoneDynInst(StaticInstPtr inst);
+
+ ~OzoneDynInst();
+
+ void setSrcInst(DynInstPtr &newSrcInst, int regIdx)
+ { srcInsts[regIdx] = newSrcInst; }
+
+ bool srcInstReady(int regIdx);
+
+ void setPrevDestInst(DynInstPtr &oldDestInst, int regIdx)
+ { prevDestInst[regIdx] = oldDestInst; }
+
+ DynInstPtr &getPrevDestInst(int regIdx)
+ { return prevDestInst[regIdx]; }
+
+ void addDependent(DynInstPtr &dependent_inst);
+
+ std::vector<DynInstPtr> &getDependents() { return dependents; }
+ std::vector<DynInstPtr> &getMemDeps() { return memDependents; }
+ std::list<DynInstPtr> &getMemSrcs() { return srcMemInsts; }
+
+ void wakeDependents();
+
+ void wakeMemDependents();
+
+ void addMemDependent(DynInstPtr &inst) { memDependents.push_back(inst); }
+
+ void addSrcMemInst(DynInstPtr &inst) { srcMemInsts.push_back(inst); }
+
+ void markMemInstReady(OzoneDynInst<Impl> *inst);
+
+ // For now I will remove instructions from the list when they wake
+ // up. In the future, you only really need a counter.
+ bool memDepReady() { return srcMemInsts.empty(); }
+
+ private:
+ void initInstPtrs();
+
+ std::vector<DynInstPtr> dependents;
+
+ std::vector<DynInstPtr> memDependents;
+
+ std::list<DynInstPtr> srcMemInsts;
+
+ /** The instruction that produces the value of the source
+ * registers. These may be NULL if the value has already been
+ * read from the source instruction.
+ */
+ DynInstPtr srcInsts[MaxInstSrcRegs];
+
+ /**
+ * Previous rename instruction for this destination.
+ */
+ DynInstPtr prevDestInst[MaxInstSrcRegs];
+
+ public:
+
+ Fault initiateAcc();
+
+ Fault completeAcc();
+
+ // The register accessor methods provide the index of the
+ // instruction's operand (e.g., 0 or 1), not the architectural
+ // register index, to simplify the implementation of register
+ // renaming. We find the architectural register index by indexing
+ // into the instruction's own operand index table. Note that a
+ // raw pointer to the StaticInst is provided instead of a
+ // ref-counted StaticInstPtr to redice overhead. This is fine as
+ // long as these methods don't copy the pointer into any long-term
+ // storage (which is pretty hard to imagine they would have reason
+ // to do).
+
+ uint64_t readIntReg(const StaticInst *si, int idx)
+ {
+ return srcInsts[idx]->readIntResult();
+ }
+
+ float readFloatRegSingle(const StaticInst *si, int idx)
+ {
+ return srcInsts[idx]->readFloatResult();
+ }
+
+ double readFloatRegDouble(const StaticInst *si, int idx)
+ {
+ return srcInsts[idx]->readDoubleResult();
+ }
+
+ uint64_t readFloatRegInt(const StaticInst *si, int idx)
+ {
+ return srcInsts[idx]->readIntResult();
+ }
+
+ /** @todo: Make results into arrays so they can handle multiple dest
+ * registers.
+ */
+ void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ {
+ BaseDynInst<Impl>::setIntReg(si, idx, val);
+ }
+
+ void setFloatRegSingle(const StaticInst *si, int idx, float val)
+ {
+ BaseDynInst<Impl>::setFloatRegSingle(si, idx, val);
+ }
+
+ void setFloatRegDouble(const StaticInst *si, int idx, double val)
+ {
+ BaseDynInst<Impl>::setFloatRegDouble(si, idx, val);
+ }
+
+ void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
+ {
+ BaseDynInst<Impl>::setFloatRegInt(si, idx, val);
+ }
+
+ void setIntResult(uint64_t result) { this->instResult.integer = result; }
+ void setDoubleResult(double result) { this->instResult.dbl = result; }
+
+ bool srcsReady();
+ bool eaSrcsReady();
+
+ Fault execute();
+
+ Fault executeEAComp()
+ { return NoFault; }
+
+ Fault executeMemAcc()
+ { return this->staticInst->memAccInst()->execute(this, this->traceData); }
+
+ void clearDependents();
+
+ void clearMemDependents();
+
+ public:
+ // ISA stuff
+ MiscReg readMiscReg(int misc_reg);
+
+ MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
+
+ Fault setMiscReg(int misc_reg, const MiscReg &val);
+
+ Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+
+#if FULL_SYSTEM
+ Fault hwrei();
+ int readIntrFlag();
+ void setIntrFlag(int val);
+ bool inPalMode();
+ void trap(Fault fault);
+ bool simPalCheck(int palFunc);
+#else
+ void syscall();
+#endif
+
+ ListIt iqIt;
+ bool iqItValid;
+};
+
+#endif // __CPU_OZONE_DYN_INST_HH__
diff --git a/cpu/ozone/dyn_inst_impl.hh b/cpu/ozone/dyn_inst_impl.hh
new file mode 100644
index 000000000..f891ec515
--- /dev/null
+++ b/cpu/ozone/dyn_inst_impl.hh
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2005-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/faults.hh"
+#include "arch/isa_traits.hh"
+#include "config/full_system.hh"
+#include "cpu/ozone/dyn_inst.hh"
+#include "kern/kernel_stats.hh"
+
+using namespace TheISA;
+
+template <class Impl>
+OzoneDynInst<Impl>::OzoneDynInst(FullCPU *cpu)
+ : BaseDynInst<Impl>(0, 0, 0, 0, cpu)
+{
+ this->setResultReady();
+
+ initInstPtrs();
+}
+
+template <class Impl>
+OzoneDynInst<Impl>::OzoneDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
+ InstSeqNum seq_num, FullCPU *cpu)
+ : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
+{
+ initInstPtrs();
+}
+
+template <class Impl>
+OzoneDynInst<Impl>::OzoneDynInst(StaticInstPtr _staticInst)
+ : BaseDynInst<Impl>(_staticInst)
+{
+ initInstPtrs();
+}
+
+template <class Impl>
+OzoneDynInst<Impl>::~OzoneDynInst()
+{
+ DPRINTF(BE, "[sn:%lli] destructor called\n", this->seqNum);
+ for (int i = 0; i < this->numSrcRegs(); ++i) {
+ srcInsts[i] = NULL;
+ }
+
+ for (int i = 0; i < this->numDestRegs(); ++i) {
+ prevDestInst[i] = NULL;
+ }
+
+ dependents.clear();
+}
+
+template <class Impl>
+Fault
+OzoneDynInst<Impl>::execute()
+{
+ // @todo: Pretty convoluted way to avoid squashing from happening when using
+ // the XC during an instruction's execution (specifically for instructions
+ // that have sideeffects that use the XC). Fix this.
+ bool in_syscall = this->thread->inSyscall;
+ this->thread->inSyscall = true;
+
+ this->fault = this->staticInst->execute(this, this->traceData);
+
+ this->thread->inSyscall = in_syscall;
+
+ return this->fault;
+}
+
+template <class Impl>
+Fault
+OzoneDynInst<Impl>::initiateAcc()
+{
+ // @todo: Pretty convoluted way to avoid squashing from happening when using
+ // the XC during an instruction's execution (specifically for instructions
+ // that have sideeffects that use the XC). Fix this.
+ bool in_syscall = this->thread->inSyscall;
+ this->thread->inSyscall = true;
+
+ this->fault = this->staticInst->initiateAcc(this, this->traceData);
+
+ this->thread->inSyscall = in_syscall;
+
+ return this->fault;
+}
+
+template <class Impl>
+Fault
+OzoneDynInst<Impl>::completeAcc()
+{
+ if (this->isLoad()) {
+ this->fault = this->staticInst->completeAcc(this->req->data,
+ this,
+ this->traceData);
+ } else if (this->isStore()) {
+ this->fault = this->staticInst->completeAcc((uint8_t*)&this->req->result,
+ this,
+ this->traceData);
+ } else {
+ panic("Unknown type!");
+ }
+
+ return this->fault;
+}
+
+template <class Impl>
+bool
+OzoneDynInst<Impl>::srcInstReady(int regIdx)
+{
+ return srcInsts[regIdx]->isResultReady();
+}
+
+template <class Impl>
+void
+OzoneDynInst<Impl>::addDependent(DynInstPtr &dependent_inst)
+{
+ dependents.push_back(dependent_inst);
+}
+
+template <class Impl>
+void
+OzoneDynInst<Impl>::wakeDependents()
+{
+ for (int i = 0; i < dependents.size(); ++i) {
+ dependents[i]->markSrcRegReady();
+ }
+}
+
+template <class Impl>
+void
+OzoneDynInst<Impl>::wakeMemDependents()
+{
+ for (int i = 0; i < memDependents.size(); ++i) {
+ memDependents[i]->markMemInstReady(this);
+ }
+}
+
+template <class Impl>
+void
+OzoneDynInst<Impl>::markMemInstReady(OzoneDynInst<Impl> *inst)
+{
+ ListIt mem_it = srcMemInsts.begin();
+ while ((*mem_it) != inst && mem_it != srcMemInsts.end()) {
+ mem_it++;
+ }
+ assert(mem_it != srcMemInsts.end());
+
+ srcMemInsts.erase(mem_it);
+}
+
+template <class Impl>
+void
+OzoneDynInst<Impl>::initInstPtrs()
+{
+ for (int i = 0; i < MaxInstSrcRegs; ++i) {
+ srcInsts[i] = NULL;
+ }
+ iqItValid = false;
+}
+
+template <class Impl>
+bool
+OzoneDynInst<Impl>::srcsReady()
+{
+ for (int i = 0; i < this->numSrcRegs(); ++i) {
+ if (!srcInsts[i]->isResultReady())
+ return false;
+ }
+
+ return true;
+}
+
+template <class Impl>
+bool
+OzoneDynInst<Impl>::eaSrcsReady()
+{
+ for (int i = 1; i < this->numSrcRegs(); ++i) {
+ if (!srcInsts[i]->isResultReady())
+ return false;
+ }
+
+ return true;
+}
+
+template <class Impl>
+void
+OzoneDynInst<Impl>::clearDependents()
+{
+ dependents.clear();
+ for (int i = 0; i < this->numSrcRegs(); ++i) {
+ srcInsts[i] = NULL;
+ }
+ for (int i = 0; i < this->numDestRegs(); ++i) {
+ prevDestInst[i] = NULL;
+ }
+}
+
+template <class Impl>
+void
+OzoneDynInst<Impl>::clearMemDependents()
+{
+ memDependents.clear();
+}
+
+template <class Impl>
+MiscReg
+OzoneDynInst<Impl>::readMiscReg(int misc_reg)
+{
+ return this->thread->readMiscReg(misc_reg);
+}
+
+template <class Impl>
+MiscReg
+OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault)
+{
+ return this->thread->readMiscRegWithEffect(misc_reg, fault);
+}
+
+template <class Impl>
+Fault
+OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
+{
+ this->setIntResult(val);
+ return this->thread->setMiscReg(misc_reg, val);
+}
+
+template <class Impl>
+Fault
+OzoneDynInst<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+{
+ return this->thread->setMiscRegWithEffect(misc_reg, val);
+}
+
+#if FULL_SYSTEM
+
+template <class Impl>
+Fault
+OzoneDynInst<Impl>::hwrei()
+{
+ if (!this->cpu->inPalMode(this->readPC()))
+ return new AlphaISA::UnimplementedOpcodeFault;
+
+ this->setNextPC(this->thread->readMiscReg(AlphaISA::IPR_EXC_ADDR));
+
+ this->cpu->hwrei();
+
+ // FIXME: XXX check for interrupts? XXX
+ return NoFault;
+}
+
+template <class Impl>
+int
+OzoneDynInst<Impl>::readIntrFlag()
+{
+return this->cpu->readIntrFlag();
+}
+
+template <class Impl>
+void
+OzoneDynInst<Impl>::setIntrFlag(int val)
+{
+ this->cpu->setIntrFlag(val);
+}
+
+template <class Impl>
+bool
+OzoneDynInst<Impl>::inPalMode()
+{
+ return this->cpu->inPalMode();
+}
+
+template <class Impl>
+void
+OzoneDynInst<Impl>::trap(Fault fault)
+{
+ fault->invoke(this->thread->getXCProxy());
+}
+
+template <class Impl>
+bool
+OzoneDynInst<Impl>::simPalCheck(int palFunc)
+{
+ return this->cpu->simPalCheck(palFunc);
+}
+#else
+template <class Impl>
+void
+OzoneDynInst<Impl>::syscall()
+{
+ this->cpu->syscall();
+}
+#endif
diff --git a/cpu/ozone/front_end.cc b/cpu/ozone/front_end.cc
new file mode 100644
index 000000000..a974d43cb
--- /dev/null
+++ b/cpu/ozone/front_end.cc
@@ -0,0 +1,7 @@
+
+#include "cpu/ozone/front_end_impl.hh"
+#include "cpu/ozone/ozone_impl.hh"
+#include "cpu/ozone/simple_impl.hh"
+
+template class FrontEnd<OzoneImpl>;
+template class FrontEnd<SimpleImpl>;
diff --git a/cpu/ozone/front_end.hh b/cpu/ozone/front_end.hh
new file mode 100644
index 000000000..dd382491f
--- /dev/null
+++ b/cpu/ozone/front_end.hh
@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_OZONE_FRONT_END_HH__
+#define __CPU_OZONE_FRONT_END_HH__
+
+#include <deque>
+
+#include "cpu/inst_seq.hh"
+#include "cpu/o3/bpred_unit.hh"
+#include "cpu/ozone/rename_table.hh"
+#include "mem/mem_req.hh"
+#include "sim/eventq.hh"
+#include "sim/stats.hh"
+
+class ExecContext;
+class MemInterface;
+template <class>
+class OzoneThreadState;
+class PageTable;
+template <class>
+class TimeBuffer;
+
+template <class Impl>
+class FrontEnd
+{
+ public:
+ typedef typename Impl::Params Params;
+ typedef typename Impl::DynInst DynInst;
+ typedef typename Impl::DynInstPtr DynInstPtr;
+ typedef typename Impl::FullCPU FullCPU;
+ typedef typename Impl::BackEnd BackEnd;
+
+ typedef typename Impl::FullCPU::OzoneXC OzoneXC;
+ typedef typename Impl::FullCPU::CommStruct CommStruct;
+
+ FrontEnd(Params *params);
+
+ std::string name() const;
+
+ void setCPU(FullCPU *cpu_ptr)
+ { cpu = cpu_ptr; }
+
+ void setBackEnd(BackEnd *back_end_ptr)
+ { backEnd = back_end_ptr; }
+
+ void setCommBuffer(TimeBuffer<CommStruct> *_comm);
+
+ void setXC(ExecContext *xc_ptr);
+
+ void setThreadState(OzoneThreadState<Impl> *thread_ptr)
+ { thread = thread_ptr; }
+
+ void regStats();
+
+ void tick();
+ Fault fetchCacheLine();
+ void processInst(DynInstPtr &inst);
+ void squash(const InstSeqNum &squash_num, const Addr &next_PC,
+ const bool is_branch = false, const bool branch_taken = false);
+ DynInstPtr getInst();
+
+ void processCacheCompletion(MemReqPtr &req);
+
+ void addFreeRegs(int num_freed);
+
+ bool isEmpty() { return instBuffer.empty(); }
+
+ void switchOut();
+
+ void doSwitchOut();
+
+ void takeOverFrom(ExecContext *old_xc = NULL);
+
+ bool isSwitchedOut() { return switchedOut; }
+
+ bool switchedOut;
+
+ private:
+ bool updateStatus();
+
+ void checkBE();
+ DynInstPtr getInstFromCacheline();
+ void renameInst(DynInstPtr &inst);
+ // Returns true if we need to stop the front end this cycle
+ bool processBarriers(DynInstPtr &inst);
+
+ void handleFault(Fault &fault);
+ public:
+ Fault getFault() { return fetchFault; }
+ private:
+ Fault fetchFault;
+
+ // Align an address (typically a PC) to the start of an I-cache block.
+ // We fold in the PISA 64- to 32-bit conversion here as well.
+ Addr icacheBlockAlignPC(Addr addr)
+ {
+ addr = TheISA::realPCToFetchPC(addr);
+ return (addr & ~(cacheBlkMask));
+ }
+
+ InstSeqNum getAndIncrementInstSeq()
+ { return cpu->globalSeqNum++; }
+
+ public:
+ FullCPU *cpu;
+
+ BackEnd *backEnd;
+
+ ExecContext *xc;
+
+ OzoneThreadState<Impl> *thread;
+
+ enum Status {
+ Running,
+ Idle,
+ IcacheMissStall,
+ IcacheMissComplete,
+ SerializeBlocked,
+ SerializeComplete,
+ RenameBlocked,
+ QuiescePending,
+ TrapPending,
+ BEBlocked
+ };
+
+ Status status;
+
+ private:
+ TimeBuffer<CommStruct> *comm;
+ typename TimeBuffer<CommStruct>::wire fromCommit;
+
+ typedef typename Impl::BranchPred BranchPred;
+
+ BranchPred branchPred;
+
+ class ICacheCompletionEvent : public Event
+ {
+ private:
+ MemReqPtr req;
+ FrontEnd *frontEnd;
+
+ public:
+ ICacheCompletionEvent(MemReqPtr &_req, FrontEnd *_fe);
+
+ virtual void process();
+ virtual const char *description();
+ };
+
+ MemInterface *icacheInterface;
+
+#if !FULL_SYSTEM
+ PageTable *pTable;
+#endif
+
+ MemReqPtr memReq;
+
+ /** Mask to get a cache block's address. */
+ Addr cacheBlkMask;
+
+ unsigned cacheBlkSize;
+
+ Addr cacheBlkPC;
+
+ /** The cache line being fetched. */
+ uint8_t *cacheData;
+
+ bool fetchCacheLineNextCycle;
+
+ bool cacheBlkValid;
+
+ public:
+ RenameTable<Impl> renameTable;
+
+ private:
+ Addr PC;
+ Addr nextPC;
+
+ public:
+ void setPC(Addr val) { PC = val; }
+ void setNextPC(Addr val) { nextPC = val; }
+
+ void wakeFromQuiesce();
+
+ void dumpInsts();
+
+ private:
+ typedef typename std::deque<DynInstPtr> InstBuff;
+ typedef typename InstBuff::iterator InstBuffIt;
+
+ InstBuff instBuffer;
+
+ int instBufferSize;
+
+ int maxInstBufferSize;
+
+ int width;
+
+ int freeRegs;
+
+ int numPhysRegs;
+
+ bool serializeNext;
+
+ DynInstPtr barrierInst;
+
+ public:
+ bool interruptPending;
+ private:
+ // number of idle cycles
+/*
+ Stats::Average<> notIdleFraction;
+ Stats::Formula idleFraction;
+*/
+ // @todo: Consider making these vectors and tracking on a per thread basis.
+ /** Stat for total number of cycles stalled due to an icache miss. */
+ Stats::Scalar<> icacheStallCycles;
+ /** Stat for total number of fetched instructions. */
+ Stats::Scalar<> fetchedInsts;
+ Stats::Scalar<> fetchedBranches;
+ /** Stat for total number of predicted branches. */
+ Stats::Scalar<> predictedBranches;
+ /** Stat for total number of cycles spent fetching. */
+ Stats::Scalar<> fetchCycles;
+
+ Stats::Scalar<> fetchIdleCycles;
+ /** Stat for total number of cycles spent squashing. */
+ Stats::Scalar<> fetchSquashCycles;
+ /** Stat for total number of cycles spent blocked due to other stages in
+ * the pipeline.
+ */
+ Stats::Scalar<> fetchBlockedCycles;
+ /** Stat for total number of fetched cache lines. */
+ Stats::Scalar<> fetchedCacheLines;
+
+ Stats::Scalar<> fetchIcacheSquashes;
+ /** Distribution of number of instructions fetched each cycle. */
+ Stats::Distribution<> fetchNisnDist;
+// Stats::Vector<> qfull_iq_occupancy;
+// Stats::VectorDistribution<> qfull_iq_occ_dist_;
+ Stats::Formula idleRate;
+ Stats::Formula branchRate;
+ Stats::Formula fetchRate;
+ Stats::Scalar<> IFQCount; // cumulative IFQ occupancy
+ Stats::Formula IFQOccupancy;
+ Stats::Formula IFQLatency;
+ Stats::Scalar<> IFQFcount; // cumulative IFQ full count
+ Stats::Formula IFQFullRate;
+
+ Stats::Scalar<> dispatchCountStat;
+ Stats::Scalar<> dispatchedSerializing;
+ Stats::Scalar<> dispatchedTempSerializing;
+ Stats::Scalar<> dispatchSerializeStallCycles;
+ Stats::Formula dispatchRate;
+ Stats::Formula regIntFull;
+ Stats::Formula regFpFull;
+};
+
+#endif // __CPU_OZONE_FRONT_END_HH__
diff --git a/cpu/ozone/front_end_impl.hh b/cpu/ozone/front_end_impl.hh
new file mode 100644
index 000000000..ffbcf3340
--- /dev/null
+++ b/cpu/ozone/front_end_impl.hh
@@ -0,0 +1,920 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/faults.hh"
+#include "arch/isa_traits.hh"
+#include "base/statistics.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/exetrace.hh"
+#include "cpu/ozone/front_end.hh"
+#include "mem/mem_interface.hh"
+#include "sim/byte_swap.hh"
+
+using namespace TheISA;
+
+template <class Impl>
+FrontEnd<Impl>::FrontEnd(Params *params)
+ : branchPred(params),
+ icacheInterface(params->icacheInterface),
+ instBufferSize(0),
+ maxInstBufferSize(params->maxInstBufferSize),
+ width(params->frontEndWidth),
+ freeRegs(params->numPhysicalRegs),
+ numPhysRegs(params->numPhysicalRegs),
+ serializeNext(false),
+ interruptPending(false)
+{
+ switchedOut = false;
+
+ status = Idle;
+
+ memReq = NULL;
+ // Size of cache block.
+ cacheBlkSize = icacheInterface ? icacheInterface->getBlockSize() : 64;
+
+ assert(isPowerOf2(cacheBlkSize));
+
+ // Create mask to get rid of offset bits.
+ cacheBlkMask = (cacheBlkSize - 1);
+
+ // Create space to store a cache line.
+ cacheData = new uint8_t[cacheBlkSize];
+
+ fetchCacheLineNextCycle = true;
+
+ cacheBlkValid = false;
+
+#if !FULL_SYSTEM
+// pTable = params->pTable;
+#endif
+ fetchFault = NoFault;
+}
+
+template <class Impl>
+std::string
+FrontEnd<Impl>::name() const
+{
+ return cpu->name() + ".frontend";
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
+{
+ comm = _comm;
+ // @todo: Hardcoded for now. Allow this to be set by a latency.
+ fromCommit = comm->getWire(-1);
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::setXC(ExecContext *xc_ptr)
+{
+ xc = xc_ptr;
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::regStats()
+{
+ icacheStallCycles
+ .name(name() + ".icacheStallCycles")
+ .desc("Number of cycles fetch is stalled on an Icache miss")
+ .prereq(icacheStallCycles);
+
+ fetchedInsts
+ .name(name() + ".fetchedInsts")
+ .desc("Number of instructions fetch has processed")
+ .prereq(fetchedInsts);
+
+ fetchedBranches
+ .name(name() + ".fetchedBranches")
+ .desc("Number of fetched branches")
+ .prereq(fetchedBranches);
+
+ predictedBranches
+ .name(name() + ".predictedBranches")
+ .desc("Number of branches that fetch has predicted taken")
+ .prereq(predictedBranches);
+
+ fetchCycles
+ .name(name() + ".fetchCycles")
+ .desc("Number of cycles fetch has run and was not squashing or"
+ " blocked")
+ .prereq(fetchCycles);
+
+ fetchIdleCycles
+ .name(name() + ".fetchIdleCycles")
+ .desc("Number of cycles fetch was idle")
+ .prereq(fetchIdleCycles);
+
+ fetchSquashCycles
+ .name(name() + ".fetchSquashCycles")
+ .desc("Number of cycles fetch has spent squashing")
+ .prereq(fetchSquashCycles);
+
+ fetchBlockedCycles
+ .name(name() + ".fetchBlockedCycles")
+ .desc("Number of cycles fetch has spent blocked")
+ .prereq(fetchBlockedCycles);
+
+ fetchedCacheLines
+ .name(name() + ".fetchedCacheLines")
+ .desc("Number of cache lines fetched")
+ .prereq(fetchedCacheLines);
+
+ fetchIcacheSquashes
+ .name(name() + ".fetchIcacheSquashes")
+ .desc("Number of outstanding Icache misses that were squashed")
+ .prereq(fetchIcacheSquashes);
+
+ fetchNisnDist
+ .init(/* base value */ 0,
+ /* last value */ width,
+ /* bucket size */ 1)
+ .name(name() + ".rateDist")
+ .desc("Number of instructions fetched each cycle (Total)")
+ .flags(Stats::pdf);
+
+ idleRate
+ .name(name() + ".idleRate")
+ .desc("Percent of cycles fetch was idle")
+ .prereq(idleRate);
+ idleRate = fetchIdleCycles * 100 / cpu->numCycles;
+
+ branchRate
+ .name(name() + ".branchRate")
+ .desc("Number of branch fetches per cycle")
+ .flags(Stats::total);
+ branchRate = fetchedBranches / cpu->numCycles;
+
+ fetchRate
+ .name(name() + ".rate")
+ .desc("Number of inst fetches per cycle")
+ .flags(Stats::total);
+ fetchRate = fetchedInsts / cpu->numCycles;
+
+ IFQCount
+ .name(name() + ".IFQ:count")
+ .desc("cumulative IFQ occupancy")
+ ;
+
+ IFQFcount
+ .name(name() + ".IFQ:fullCount")
+ .desc("cumulative IFQ full count")
+ .flags(Stats::total)
+ ;
+
+ IFQOccupancy
+ .name(name() + ".IFQ:occupancy")
+ .desc("avg IFQ occupancy (inst's)")
+ ;
+ IFQOccupancy = IFQCount / cpu->numCycles;
+
+ IFQLatency
+ .name(name() + ".IFQ:latency")
+ .desc("avg IFQ occupant latency (cycle's)")
+ .flags(Stats::total)
+ ;
+
+ IFQFullRate
+ .name(name() + ".IFQ:fullRate")
+ .desc("fraction of time (cycles) IFQ was full")
+ .flags(Stats::total);
+ ;
+ IFQFullRate = IFQFcount * Stats::constant(100) / cpu->numCycles;
+
+ dispatchCountStat
+ .name(name() + ".DIS:count")
+ .desc("cumulative count of dispatched insts")
+ .flags(Stats::total)
+ ;
+
+ dispatchedSerializing
+ .name(name() + ".DIS:serializingInsts")
+ .desc("count of serializing insts dispatched")
+ .flags(Stats::total)
+ ;
+
+ dispatchedTempSerializing
+ .name(name() + ".DIS:tempSerializingInsts")
+ .desc("count of temporary serializing insts dispatched")
+ .flags(Stats::total)
+ ;
+
+ dispatchSerializeStallCycles
+ .name(name() + ".DIS:serializeStallCycles")
+ .desc("count of cycles dispatch stalled for serializing inst")
+ .flags(Stats::total)
+ ;
+
+ dispatchRate
+ .name(name() + ".DIS:rate")
+ .desc("dispatched insts per cycle")
+ .flags(Stats::total)
+ ;
+ dispatchRate = dispatchCountStat / cpu->numCycles;
+
+ regIntFull
+ .name(name() + ".REG:int:full")
+ .desc("number of cycles where there were no INT registers")
+ ;
+
+ regFpFull
+ .name(name() + ".REG:fp:full")
+ .desc("number of cycles where there were no FP registers")
+ ;
+ IFQLatency = IFQOccupancy / dispatchRate;
+
+ branchPred.regStats();
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::tick()
+{
+ if (switchedOut)
+ return;
+
+ // @todo: Maybe I want to just have direct communication...
+ if (fromCommit->doneSeqNum) {
+ branchPred.update(fromCommit->doneSeqNum, 0);
+ }
+
+ IFQCount += instBufferSize;
+ IFQFcount += instBufferSize == maxInstBufferSize;
+
+ // Fetch cache line
+ if (status == IcacheMissComplete) {
+ cacheBlkValid = true;
+
+ status = Running;
+ if (barrierInst)
+ status = SerializeBlocked;
+ if (freeRegs <= 0)
+ status = RenameBlocked;
+ checkBE();
+ } else if (status == IcacheMissStall) {
+ DPRINTF(FE, "Still in Icache miss stall.\n");
+ icacheStallCycles++;
+ return;
+ }
+
+ if (status == RenameBlocked || status == SerializeBlocked ||
+ status == TrapPending || status == BEBlocked) {
+ // Will cause a one cycle bubble between changing state and
+ // restarting.
+ DPRINTF(FE, "In blocked status.\n");
+
+ fetchBlockedCycles++;
+
+ if (status == SerializeBlocked) {
+ dispatchSerializeStallCycles++;
+ }
+ updateStatus();
+ return;
+ } else if (status == QuiescePending) {
+ DPRINTF(FE, "Waiting for quiesce to execute or get squashed.\n");
+ return;
+ } else if (status != IcacheMissComplete) {
+ if (fetchCacheLineNextCycle) {
+ Fault fault = fetchCacheLine();
+ if (fault != NoFault) {
+ handleFault(fault);
+ fetchFault = fault;
+ return;
+ }
+ fetchCacheLineNextCycle = false;
+ }
+ // If miss, stall until it returns.
+ if (status == IcacheMissStall) {
+ // Tell CPU to not tick me for now.
+ return;
+ }
+ }
+
+ fetchCycles++;
+
+ int num_inst = 0;
+
+ // Otherwise loop and process instructions.
+ // One way to hack infinite width is to set width and maxInstBufferSize
+ // both really high. Inelegant, but probably will work.
+ while (num_inst < width &&
+ instBufferSize < maxInstBufferSize) {
+ // Get instruction from cache line.
+ DynInstPtr inst = getInstFromCacheline();
+
+ if (!inst) {
+ // PC is no longer in the cache line, end fetch.
+ // Might want to check this at the end of the cycle so that
+ // there's no cycle lost to checking for a new cache line.
+ DPRINTF(FE, "Need to get new cache line\n");
+ fetchCacheLineNextCycle = true;
+ break;
+ }
+
+ processInst(inst);
+
+ if (status == SerializeBlocked) {
+ break;
+ }
+
+ // Possibly push into a time buffer that estimates the front end
+ // latency
+ instBuffer.push_back(inst);
+ ++instBufferSize;
+ ++num_inst;
+
+#if FULL_SYSTEM
+ if (inst->isQuiesce()) {
+ warn("%lli: Quiesce instruction encountered, halting fetch!", curTick);
+ status = QuiescePending;
+ break;
+ }
+#endif
+
+ if (inst->predTaken()) {
+ // Start over with tick?
+ break;
+ } else if (freeRegs <= 0) {
+ DPRINTF(FE, "Ran out of free registers to rename to!\n");
+ status = RenameBlocked;
+ break;
+ } else if (serializeNext) {
+ break;
+ }
+ }
+
+ fetchNisnDist.sample(num_inst);
+ checkBE();
+
+ DPRINTF(FE, "Num insts processed: %i, Inst Buffer size: %i, Free "
+ "Regs %i\n", num_inst, instBufferSize, freeRegs);
+}
+
+template <class Impl>
+Fault
+FrontEnd<Impl>::fetchCacheLine()
+{
+ // Read a cache line, based on the current PC.
+#if FULL_SYSTEM
+ // Flag to say whether or not address is physical addr.
+ unsigned flags = cpu->inPalMode(PC) ? PHYSICAL : 0;
+#else
+ unsigned flags = 0;
+#endif // FULL_SYSTEM
+ Fault fault = NoFault;
+
+ if (interruptPending && flags == 0) {
+ return fault;
+ }
+
+ // Align the fetch PC so it's at the start of a cache block.
+ Addr fetch_PC = icacheBlockAlignPC(PC);
+
+ DPRINTF(FE, "Fetching cache line starting at %#x.\n", fetch_PC);
+
+ // Setup the memReq to do a read of the first isntruction's address.
+ // Set the appropriate read size and flags as well.
+ memReq = new MemReq();
+
+ memReq->asid = 0;
+ memReq->thread_num = 0;
+ memReq->data = new uint8_t[64];
+ memReq->xc = xc;
+ memReq->cmd = Read;
+ memReq->reset(fetch_PC, cacheBlkSize, flags);
+
+ // Translate the instruction request.
+ fault = cpu->translateInstReq(memReq);
+
+ // Now do the timing access to see whether or not the instruction
+ // exists within the cache.
+ if (icacheInterface && fault == NoFault) {
+#if FULL_SYSTEM
+ if (cpu->system->memctrl->badaddr(memReq->paddr) ||
+ memReq->flags & UNCACHEABLE) {
+ DPRINTF(FE, "Fetch: Bad address %#x (hopefully on a "
+ "misspeculating path!",
+ memReq->paddr);
+ return TheISA::genMachineCheckFault();
+ }
+#endif
+
+ memReq->completionEvent = NULL;
+
+ memReq->time = curTick;
+ fault = cpu->mem->read(memReq, cacheData);
+
+ MemAccessResult res = icacheInterface->access(memReq);
+
+ // If the cache missed then schedule an event to wake
+ // up this stage once the cache miss completes.
+ if (icacheInterface->doEvents() && res != MA_HIT) {
+ memReq->completionEvent = new ICacheCompletionEvent(memReq, this);
+
+ status = IcacheMissStall;
+
+ cacheBlkValid = false;
+
+ DPRINTF(FE, "Cache miss.\n");
+ } else {
+ DPRINTF(FE, "Cache hit.\n");
+
+ cacheBlkValid = true;
+
+// memcpy(cacheData, memReq->data, memReq->size);
+ }
+ }
+
+ // Note that this will set the cache block PC a bit earlier than it should
+ // be set.
+ cacheBlkPC = fetch_PC;
+
+ ++fetchedCacheLines;
+
+ DPRINTF(FE, "Done fetching cache line.\n");
+
+ return fault;
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::processInst(DynInstPtr &inst)
+{
+ if (processBarriers(inst)) {
+ return;
+ }
+
+ Addr inst_PC = inst->readPC();
+
+ if (!inst->isControl()) {
+ inst->setPredTarg(inst->readNextPC());
+ } else {
+ fetchedBranches++;
+ if (branchPred.predict(inst, inst_PC, inst->threadNumber)) {
+ predictedBranches++;
+ }
+ }
+
+ Addr next_PC = inst->readPredTarg();
+
+ DPRINTF(FE, "[sn:%lli] Predicted and processed inst PC %#x, next PC "
+ "%#x\n", inst->seqNum, inst_PC, next_PC);
+
+// inst->setNextPC(next_PC);
+
+ // Not sure where I should set this
+ PC = next_PC;
+
+ renameInst(inst);
+}
+
+template <class Impl>
+bool
+FrontEnd<Impl>::processBarriers(DynInstPtr &inst)
+{
+ if (serializeNext) {
+ inst->setSerializeBefore();
+ serializeNext = false;
+ } else if (!inst->isSerializing() &&
+ !inst->isIprAccess() &&
+ !inst->isStoreConditional()) {
+ return false;
+ }
+
+ if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
+ !inst->isSerializeHandled()) {
+ DPRINTF(FE, "Serialize before instruction encountered.\n");
+
+ if (!inst->isTempSerializeBefore()) {
+ dispatchedSerializing++;
+ inst->setSerializeHandled();
+ } else {
+ dispatchedTempSerializing++;
+ }
+
+ // Change status over to SerializeBlocked so that other stages know
+ // what this is blocked on.
+ status = SerializeBlocked;
+
+ barrierInst = inst;
+ return true;
+ } else if ((inst->isStoreConditional() || inst->isSerializeAfter())
+ && !inst->isSerializeHandled()) {
+ DPRINTF(FE, "Serialize after instruction encountered.\n");
+
+ inst->setSerializeHandled();
+
+ dispatchedSerializing++;
+
+ serializeNext = true;
+ return false;
+ }
+ return false;
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::handleFault(Fault &fault)
+{
+ DPRINTF(FE, "Fault at fetch, telling commit\n");
+
+ // We're blocked on the back end until it handles this fault.
+ status = TrapPending;
+
+ // Get a sequence number.
+ InstSeqNum inst_seq = getAndIncrementInstSeq();
+ // We will use a nop in order to carry the fault.
+ ExtMachInst ext_inst = TheISA::NoopMachInst;
+
+ // Create a new DynInst from the dummy nop.
+ DynInstPtr instruction = new DynInst(ext_inst, PC,
+ PC+sizeof(MachInst),
+ inst_seq, cpu);
+ instruction->setPredTarg(instruction->readNextPC());
+// instruction->setThread(tid);
+
+// instruction->setASID(tid);
+
+ instruction->setState(thread);
+
+ instruction->traceData = NULL;
+
+ instruction->fault = fault;
+ instruction->setCanIssue();
+ instBuffer.push_back(instruction);
+ ++instBufferSize;
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::squash(const InstSeqNum &squash_num, const Addr &next_PC,
+ const bool is_branch, const bool branch_taken)
+{
+ DPRINTF(FE, "Squashing from [sn:%lli], setting PC to %#x\n",
+ squash_num, next_PC);
+
+ if (fetchFault != NoFault)
+ fetchFault = NoFault;
+
+ while (!instBuffer.empty() &&
+ instBuffer.back()->seqNum > squash_num) {
+ DynInstPtr inst = instBuffer.back();
+
+ DPRINTF(FE, "Squashing instruction [sn:%lli] PC %#x\n",
+ inst->seqNum, inst->readPC());
+
+ inst->clearDependents();
+
+ instBuffer.pop_back();
+ --instBufferSize;
+
+ freeRegs+= inst->numDestRegs();
+ }
+
+ // Copy over rename table from the back end.
+ renameTable.copyFrom(backEnd->renameTable);
+
+ PC = next_PC;
+
+ // Update BP with proper information.
+ if (is_branch) {
+ branchPred.squash(squash_num, next_PC, branch_taken, 0);
+ } else {
+ branchPred.squash(squash_num, 0);
+ }
+
+ // Clear the icache miss if it's outstanding.
+ if (status == IcacheMissStall && icacheInterface) {
+ DPRINTF(FE, "Squashing outstanding Icache miss.\n");
+ memReq = NULL;
+ }
+
+ if (status == SerializeBlocked) {
+ assert(barrierInst->seqNum > squash_num);
+ barrierInst = NULL;
+ }
+
+ // Unless this squash originated from the front end, we're probably
+ // in running mode now.
+ // Actually might want to make this latency dependent.
+ status = Running;
+ fetchCacheLineNextCycle = true;
+}
+
+template <class Impl>
+typename Impl::DynInstPtr
+FrontEnd<Impl>::getInst()
+{
+ if (instBufferSize == 0) {
+ return NULL;
+ }
+
+ DynInstPtr inst = instBuffer.front();
+
+ instBuffer.pop_front();
+
+ --instBufferSize;
+
+ dispatchCountStat++;
+
+ return inst;
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::processCacheCompletion(MemReqPtr &req)
+{
+ DPRINTF(FE, "Processing cache completion\n");
+
+ // Do something here.
+ if (status != IcacheMissStall ||
+ req != memReq ||
+ switchedOut) {
+ DPRINTF(FE, "Previous fetch was squashed.\n");
+ fetchIcacheSquashes++;
+ return;
+ }
+
+ status = IcacheMissComplete;
+
+/* if (checkStall(tid)) {
+ fetchStatus[tid] = Blocked;
+ } else {
+ fetchStatus[tid] = IcacheMissComplete;
+ }
+*/
+// memcpy(cacheData, memReq->data, memReq->size);
+
+ // Reset the completion event to NULL.
+// memReq->completionEvent = NULL;
+ memReq = NULL;
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::addFreeRegs(int num_freed)
+{
+ if (status == RenameBlocked && freeRegs + num_freed > 0) {
+ status = Running;
+ }
+
+ DPRINTF(FE, "Adding %i freed registers\n", num_freed);
+
+ freeRegs+= num_freed;
+
+// assert(freeRegs <= numPhysRegs);
+ if (freeRegs > numPhysRegs)
+ freeRegs = numPhysRegs;
+}
+
+template <class Impl>
+bool
+FrontEnd<Impl>::updateStatus()
+{
+ bool serialize_block = !backEnd->robEmpty() || instBufferSize;
+ bool be_block = cpu->decoupledFrontEnd ? false : backEnd->isBlocked();
+ bool ret_val = false;
+
+ if (status == SerializeBlocked && !serialize_block) {
+ status = SerializeComplete;
+ ret_val = true;
+ }
+
+ if (status == BEBlocked && !be_block) {
+ if (barrierInst) {
+ status = SerializeBlocked;
+ } else {
+ status = Running;
+ }
+ ret_val = true;
+ }
+ return ret_val;
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::checkBE()
+{
+ bool be_block = cpu->decoupledFrontEnd ? false : backEnd->isBlocked();
+ if (be_block) {
+ if (status == Running || status == Idle) {
+ status = BEBlocked;
+ }
+ }
+}
+
+template <class Impl>
+typename Impl::DynInstPtr
+FrontEnd<Impl>::getInstFromCacheline()
+{
+ if (status == SerializeComplete) {
+ DynInstPtr inst = barrierInst;
+ status = Running;
+ barrierInst = NULL;
+ inst->clearSerializeBefore();
+ return inst;
+ }
+
+ InstSeqNum inst_seq;
+ MachInst inst;
+ // @todo: Fix this magic number used here to handle word offset (and
+ // getting rid of PAL bit)
+ unsigned offset = (PC & cacheBlkMask) & ~3;
+
+ // PC of inst is not in this cache block
+ if (PC >= (cacheBlkPC + cacheBlkSize) || PC < cacheBlkPC || !cacheBlkValid) {
+ return NULL;
+ }
+
+ //////////////////////////
+ // Fetch one instruction
+ //////////////////////////
+
+ // Get a sequence number.
+ inst_seq = getAndIncrementInstSeq();
+
+ // Make sure this is a valid index.
+ assert(offset <= cacheBlkSize - sizeof(MachInst));
+
+ // Get the instruction from the array of the cache line.
+ inst = htog(*reinterpret_cast<MachInst *>(&cacheData[offset]));
+
+ ExtMachInst decode_inst = TheISA::makeExtMI(inst, PC);
+
+ // Create a new DynInst from the instruction fetched.
+ DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst),
+ inst_seq, cpu);
+
+ instruction->setState(thread);
+
+ DPRINTF(FE, "Instruction [sn:%lli] created, with PC %#x\n%s\n",
+ inst_seq, instruction->readPC(),
+ instruction->staticInst->disassemble(PC));
+
+ instruction->traceData =
+ Trace::getInstRecord(curTick, xc, cpu,
+ instruction->staticInst,
+ instruction->readPC(), 0);
+
+ // Increment stat of fetched instructions.
+ ++fetchedInsts;
+
+ return instruction;
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::renameInst(DynInstPtr &inst)
+{
+ DynInstPtr src_inst = NULL;
+ int num_src_regs = inst->numSrcRegs();
+ if (num_src_regs == 0) {
+ inst->setCanIssue();
+ } else {
+ for (int i = 0; i < num_src_regs; ++i) {
+ src_inst = renameTable[inst->srcRegIdx(i)];
+
+ inst->setSrcInst(src_inst, i);
+
+ DPRINTF(FE, "[sn:%lli]: Src reg %i is inst [sn:%lli]\n",
+ inst->seqNum, (int)inst->srcRegIdx(i), src_inst->seqNum);
+
+ if (src_inst->isResultReady()) {
+ DPRINTF(FE, "Reg ready.\n");
+ inst->markSrcRegReady(i);
+ } else {
+ DPRINTF(FE, "Adding to dependent list.\n");
+ src_inst->addDependent(inst);
+ }
+ }
+ }
+
+ for (int i = 0; i < inst->numDestRegs(); ++i) {
+ RegIndex idx = inst->destRegIdx(i);
+
+ DPRINTF(FE, "Dest reg %i is now inst [sn:%lli], was previously "
+ "[sn:%lli]\n",
+ (int)inst->destRegIdx(i), inst->seqNum,
+ renameTable[idx]->seqNum);
+
+ inst->setPrevDestInst(renameTable[idx], i);
+
+ renameTable[idx] = inst;
+ --freeRegs;
+ }
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::wakeFromQuiesce()
+{
+ DPRINTF(FE, "Waking up from quiesce\n");
+ // Hopefully this is safe
+ status = Running;
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::switchOut()
+{
+ switchedOut = true;
+ cpu->signalSwitched();
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::doSwitchOut()
+{
+ memReq = NULL;
+ squash(0, 0);
+ instBuffer.clear();
+ instBufferSize = 0;
+ status = Idle;
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::takeOverFrom(ExecContext *old_xc)
+{
+ assert(freeRegs == numPhysRegs);
+ fetchCacheLineNextCycle = true;
+
+ cacheBlkValid = false;
+
+#if !FULL_SYSTEM
+// pTable = params->pTable;
+#endif
+ fetchFault = NoFault;
+ serializeNext = false;
+ barrierInst = NULL;
+ status = Running;
+ switchedOut = false;
+ interruptPending = false;
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::dumpInsts()
+{
+ cprintf("instBuffer size: %i\n", instBuffer.size());
+
+ InstBuffIt buff_it = instBuffer.begin();
+
+ for (int num = 0; buff_it != instBuffer.end(); num++) {
+ cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
+ "Squashed:%i\n\n",
+ num, (*buff_it)->readPC(), (*buff_it)->threadNumber,
+ (*buff_it)->seqNum, (*buff_it)->isIssued(),
+ (*buff_it)->isSquashed());
+ buff_it++;
+ }
+}
+
+template <class Impl>
+FrontEnd<Impl>::ICacheCompletionEvent::ICacheCompletionEvent(MemReqPtr &_req, FrontEnd *fe)
+ : Event(&mainEventQueue, Delayed_Writeback_Pri), req(_req), frontEnd(fe)
+{
+ this->setFlags(Event::AutoDelete);
+}
+
+template <class Impl>
+void
+FrontEnd<Impl>::ICacheCompletionEvent::process()
+{
+ frontEnd->processCacheCompletion(req);
+}
+
+template <class Impl>
+const char *
+FrontEnd<Impl>::ICacheCompletionEvent::description()
+{
+ return "ICache completion event";
+}
diff --git a/cpu/ozone/inorder_back_end.cc b/cpu/ozone/inorder_back_end.cc
new file mode 100644
index 000000000..14db610d2
--- /dev/null
+++ b/cpu/ozone/inorder_back_end.cc
@@ -0,0 +1,5 @@
+
+#include "cpu/ozone/inorder_back_end_impl.hh"
+#include "cpu/ozone/simple_impl.hh"
+
+template class InorderBackEnd<SimpleImpl>;
diff --git a/cpu/ozone/inorder_back_end.hh b/cpu/ozone/inorder_back_end.hh
new file mode 100644
index 000000000..4039d8384
--- /dev/null
+++ b/cpu/ozone/inorder_back_end.hh
@@ -0,0 +1,450 @@
+
+#ifndef __CPU_OZONE_INORDER_BACK_END_HH__
+#define __CPU_OZONE_INORDER_BACK_END_HH__
+
+#include <list>
+
+#include "arch/faults.hh"
+#include "base/timebuf.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/inst_seq.hh"
+#include "cpu/ozone/rename_table.hh"
+#include "cpu/ozone/thread_state.hh"
+#include "mem/mem_interface.hh"
+#include "mem/mem_req.hh"
+#include "sim/eventq.hh"
+
+template <class Impl>
+class InorderBackEnd
+{
+ public:
+ typedef typename Impl::Params Params;
+ typedef typename Impl::DynInstPtr DynInstPtr;
+ typedef typename Impl::FullCPU FullCPU;
+ typedef typename Impl::FrontEnd FrontEnd;
+
+ typedef typename FullCPU::OzoneXC OzoneXC;
+ typedef typename Impl::FullCPU::CommStruct CommStruct;
+
+ InorderBackEnd(Params *params);
+
+ std::string name() const;
+
+ void setCPU(FullCPU *cpu_ptr)
+ { cpu = cpu_ptr; }
+
+ void setFrontEnd(FrontEnd *front_end_ptr)
+ { frontEnd = front_end_ptr; }
+
+ void setCommBuffer(TimeBuffer<CommStruct> *_comm)
+ { comm = _comm; }
+
+ void setXC(ExecContext *xc_ptr);
+
+ void setThreadState(OzoneThreadState<Impl> *thread_ptr);
+
+ void regStats() { }
+
+#if FULL_SYSTEM
+ void checkInterrupts();
+#endif
+
+ void tick();
+ void executeInsts();
+ void squash(const InstSeqNum &squash_num, const Addr &next_PC);
+
+ void squashFromXC();
+ void generateXCEvent() { }
+
+ bool robEmpty() { return instList.empty(); }
+
+ bool isFull() { return false; }
+ bool isBlocked() { return status == DcacheMissStoreStall ||
+ status == DcacheMissLoadStall ||
+ interruptBlocked; }
+
+ void fetchFault(Fault &fault);
+
+ void dumpInsts();
+
+ private:
+ void handleFault();
+
+ void setSquashInfoFromXC();
+
+ bool squashPending;
+ InstSeqNum squashSeqNum;
+ Addr squashNextPC;
+
+ Fault faultFromFetch;
+
+ bool interruptBlocked;
+
+ public:
+ template <class T>
+ Fault read(Addr addr, T &data, unsigned flags);
+
+ template <class T>
+ Fault read(MemReqPtr &req, T &data, int load_idx);
+
+ template <class T>
+ Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
+
+ template <class T>
+ Fault write(MemReqPtr &req, T &data, int store_idx);
+
+ Addr readCommitPC() { return commitPC; }
+
+ Addr commitPC;
+
+ void switchOut() { panic("Not implemented!"); }
+ void doSwitchOut() { panic("Not implemented!"); }
+ void takeOverFrom(ExecContext *old_xc = NULL) { panic("Not implemented!"); }
+
+ public:
+ FullCPU *cpu;
+
+ FrontEnd *frontEnd;
+
+ ExecContext *xc;
+
+ OzoneThreadState<Impl> *thread;
+
+ RenameTable<Impl> renameTable;
+
+ protected:
+ enum Status {
+ Running,
+ Idle,
+ DcacheMissLoadStall,
+ DcacheMissStoreStall,
+ DcacheMissComplete,
+ Blocked
+ };
+
+ Status status;
+
+ class DCacheCompletionEvent : public Event
+ {
+ private:
+ InorderBackEnd *be;
+
+ public:
+ DCacheCompletionEvent(InorderBackEnd *_be);
+
+ virtual void process();
+ virtual const char *description();
+
+ DynInstPtr inst;
+ };
+
+ friend class DCacheCompletionEvent;
+
+ DCacheCompletionEvent cacheCompletionEvent;
+
+ MemInterface *dcacheInterface;
+
+ MemReqPtr memReq;
+
+ private:
+ typedef typename std::list<DynInstPtr>::iterator InstListIt;
+
+ std::list<DynInstPtr> instList;
+
+ // General back end width. Used if the more specific isn't given.
+ int width;
+
+ int latency;
+
+ int squashLatency;
+
+ TimeBuffer<int> numInstsToWB;
+ TimeBuffer<int>::wire instsAdded;
+ TimeBuffer<int>::wire instsToExecute;
+
+ TimeBuffer<CommStruct> *comm;
+ // number of cycles stalled for D-cache misses
+ Stats::Scalar<> dcacheStallCycles;
+ Counter lastDcacheStall;
+};
+
+template <class Impl>
+template <class T>
+Fault
+InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
+{
+ memReq->reset(addr, sizeof(T), flags);
+
+ // translate to physical address
+ Fault fault = cpu->translateDataReadReq(memReq);
+
+ // if we have a cache, do cache access too
+ if (fault == NoFault && dcacheInterface) {
+ memReq->cmd = Read;
+ memReq->completionEvent = NULL;
+ memReq->time = curTick;
+ memReq->flags &= ~INST_READ;
+ MemAccessResult result = dcacheInterface->access(memReq);
+
+ // Ugly hack to get an event scheduled *only* if the access is
+ // a miss. We really should add first-class support for this
+ // at some point.
+ if (result != MA_HIT) {
+ // Fix this hack for keeping funcExeInst correct with loads that
+ // are executed twice.
+ memReq->completionEvent = &cacheCompletionEvent;
+ lastDcacheStall = curTick;
+// unscheduleTickEvent();
+ status = DcacheMissLoadStall;
+ DPRINTF(IBE, "Dcache miss stall!\n");
+ } else {
+ // do functional access
+ DPRINTF(IBE, "Dcache hit!\n");
+ }
+ }
+/*
+ if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
+ recordEvent("Uncached Read");
+*/
+ return fault;
+}
+#if 0
+template <class Impl>
+template <class T>
+Fault
+InorderBackEnd<Impl>::read(MemReqPtr &req, T &data)
+{
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
+ if (req->flags & LOCKED) {
+ req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
+ req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
+ }
+#endif
+
+ Fault error;
+ error = thread->mem->read(req, data);
+ data = LittleEndianGuest::gtoh(data);
+ return error;
+}
+#endif
+
+template <class Impl>
+template <class T>
+Fault
+InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
+{
+ memReq->reset(addr, sizeof(T), flags);
+
+ // translate to physical address
+ Fault fault = cpu->translateDataWriteReq(memReq);
+
+ if (fault == NoFault && dcacheInterface) {
+ memReq->cmd = Write;
+// memcpy(memReq->data,(uint8_t *)&data,memReq->size);
+ memReq->completionEvent = NULL;
+ memReq->time = curTick;
+ memReq->flags &= ~INST_READ;
+ MemAccessResult result = dcacheInterface->access(memReq);
+
+ // Ugly hack to get an event scheduled *only* if the access is
+ // a miss. We really should add first-class support for this
+ // at some point.
+ if (result != MA_HIT) {
+ memReq->completionEvent = &cacheCompletionEvent;
+ lastDcacheStall = curTick;
+// unscheduleTickEvent();
+ status = DcacheMissStoreStall;
+ DPRINTF(IBE, "Dcache miss stall!\n");
+ } else {
+ DPRINTF(IBE, "Dcache hit!\n");
+ }
+ }
+
+ if (res && (fault == NoFault))
+ *res = memReq->result;
+/*
+ if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
+ recordEvent("Uncached Write");
+*/
+ return fault;
+}
+#if 0
+template <class Impl>
+template <class T>
+Fault
+InorderBackEnd<Impl>::write(MemReqPtr &req, T &data)
+{
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
+ ExecContext *xc;
+
+ // If this is a store conditional, act appropriately
+ if (req->flags & LOCKED) {
+ xc = req->xc;
+
+ if (req->flags & UNCACHEABLE) {
+ // Don't update result register (see stq_c in isa_desc)
+ req->result = 2;
+ xc->setStCondFailures(0);//Needed? [RGD]
+ } else {
+ bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
+ Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
+ req->result = lock_flag;
+ if (!lock_flag ||
+ ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
+ xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
+ xc->setStCondFailures(xc->readStCondFailures() + 1);
+ if (((xc->readStCondFailures()) % 100000) == 0) {
+ std::cerr << "Warning: "
+ << xc->readStCondFailures()
+ << " consecutive store conditional failures "
+ << "on cpu " << req->xc->readCpuId()
+ << std::endl;
+ }
+ return NoFault;
+ }
+ else xc->setStCondFailures(0);
+ }
+ }
+
+ // Need to clear any locked flags on other proccessors for
+ // this address. Only do this for succsful Store Conditionals
+ // and all other stores (WH64?). Unsuccessful Store
+ // Conditionals would have returned above, and wouldn't fall
+ // through.
+ for (int i = 0; i < cpu->system->execContexts.size(); i++){
+ xc = cpu->system->execContexts[i];
+ if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
+ (req->paddr & ~0xf)) {
+ xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
+ }
+ }
+
+#endif
+ return thread->mem->write(req, (T)LittleEndianGuest::htog(data));
+}
+#endif
+
+template <class Impl>
+template <class T>
+Fault
+InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
+{
+// panic("Unimplemented!");
+// memReq->reset(addr, sizeof(T), flags);
+
+ // translate to physical address
+// Fault fault = cpu->translateDataReadReq(req);
+ req->cmd = Read;
+ req->completionEvent = NULL;
+ req->time = curTick;
+ assert(!req->data);
+ req->data = new uint8_t[64];
+ req->flags &= ~INST_READ;
+ Fault fault = cpu->read(req, data);
+ memcpy(req->data, &data, sizeof(T));
+
+ // if we have a cache, do cache access too
+ if (dcacheInterface) {
+ MemAccessResult result = dcacheInterface->access(req);
+
+ // Ugly hack to get an event scheduled *only* if the access is
+ // a miss. We really should add first-class support for this
+ // at some point.
+ if (result != MA_HIT) {
+ req->completionEvent = &cacheCompletionEvent;
+ lastDcacheStall = curTick;
+// unscheduleTickEvent();
+ status = DcacheMissLoadStall;
+ DPRINTF(IBE, "Dcache miss load stall!\n");
+ } else {
+ DPRINTF(IBE, "Dcache hit!\n");
+
+ }
+ }
+
+/*
+ if (!dcacheInterface && (req->flags & UNCACHEABLE))
+ recordEvent("Uncached Read");
+*/
+ return NoFault;
+}
+
+template <class Impl>
+template <class T>
+Fault
+InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
+{
+// req->reset(addr, sizeof(T), flags);
+
+ // translate to physical address
+// Fault fault = cpu->translateDataWriteReq(req);
+
+ req->cmd = Write;
+ req->completionEvent = NULL;
+ req->time = curTick;
+ assert(!req->data);
+ req->data = new uint8_t[64];
+ memcpy(req->data, (uint8_t *)&data, req->size);
+
+ switch(req->size) {
+ case 1:
+ cpu->write(req, (uint8_t &)data);
+ break;
+ case 2:
+ cpu->write(req, (uint16_t &)data);
+ break;
+ case 4:
+ cpu->write(req, (uint32_t &)data);
+ break;
+ case 8:
+ cpu->write(req, (uint64_t &)data);
+ break;
+ default:
+ panic("Unexpected store size!\n");
+ }
+
+ if (dcacheInterface) {
+ req->cmd = Write;
+ req->data = new uint8_t[64];
+ memcpy(req->data,(uint8_t *)&data,req->size);
+ req->completionEvent = NULL;
+ req->time = curTick;
+ req->flags &= ~INST_READ;
+ MemAccessResult result = dcacheInterface->access(req);
+
+ // Ugly hack to get an event scheduled *only* if the access is
+ // a miss. We really should add first-class support for this
+ // at some point.
+ if (result != MA_HIT) {
+ req->completionEvent = &cacheCompletionEvent;
+ lastDcacheStall = curTick;
+// unscheduleTickEvent();
+ status = DcacheMissStoreStall;
+ DPRINTF(IBE, "Dcache miss store stall!\n");
+ } else {
+ DPRINTF(IBE, "Dcache hit!\n");
+
+ }
+ }
+/*
+ if (req->flags & LOCKED) {
+ if (req->flags & UNCACHEABLE) {
+ // Don't update result register (see stq_c in isa_desc)
+ req->result = 2;
+ } else {
+ req->result = 1;
+ }
+ }
+*/
+/*
+ if (res && (fault == NoFault))
+ *res = req->result;
+ */
+/*
+ if (!dcacheInterface && (req->flags & UNCACHEABLE))
+ recordEvent("Uncached Write");
+*/
+ return NoFault;
+}
+
+#endif // __CPU_OZONE_INORDER_BACK_END_HH__
diff --git a/cpu/ozone/inorder_back_end_impl.hh b/cpu/ozone/inorder_back_end_impl.hh
new file mode 100644
index 000000000..5a378ec76
--- /dev/null
+++ b/cpu/ozone/inorder_back_end_impl.hh
@@ -0,0 +1,519 @@
+
+#include "arch/faults.hh"
+#include "arch/isa_traits.hh"
+#include "cpu/ozone/inorder_back_end.hh"
+#include "cpu/ozone/thread_state.hh"
+
+using namespace TheISA;
+
+template <class Impl>
+InorderBackEnd<Impl>::InorderBackEnd(Params *params)
+ : squashPending(false),
+ squashSeqNum(0),
+ squashNextPC(0),
+ faultFromFetch(NoFault),
+ interruptBlocked(false),
+ cacheCompletionEvent(this),
+ dcacheInterface(params->dcacheInterface),
+ width(params->backEndWidth),
+ latency(params->backEndLatency),
+ squashLatency(params->backEndSquashLatency),
+ numInstsToWB(0, latency + 1)
+{
+ instsAdded = numInstsToWB.getWire(latency);
+ instsToExecute = numInstsToWB.getWire(0);
+
+ memReq = new MemReq;
+ memReq->data = new uint8_t[64];
+ status = Running;
+}
+
+template <class Impl>
+std::string
+InorderBackEnd<Impl>::name() const
+{
+ return cpu->name() + ".inorderbackend";
+}
+
+template <class Impl>
+void
+InorderBackEnd<Impl>::setXC(ExecContext *xc_ptr)
+{
+ xc = xc_ptr;
+ memReq->xc = xc;
+}
+
+template <class Impl>
+void
+InorderBackEnd<Impl>::setThreadState(OzoneThreadState<Impl> *thread_ptr)
+{
+ thread = thread_ptr;
+ thread->setFuncExeInst(0);
+}
+
+#if FULL_SYSTEM
+template <class Impl>
+void
+InorderBackEnd<Impl>::checkInterrupts()
+{
+ //Check if there are any outstanding interrupts
+ //Handle the interrupts
+ int ipl = 0;
+ int summary = 0;
+
+ cpu->checkInterrupts = false;
+
+ if (thread->readMiscReg(IPR_ASTRR))
+ panic("asynchronous traps not implemented\n");
+
+ if (thread->readMiscReg(IPR_SIRR)) {
+ for (int i = INTLEVEL_SOFTWARE_MIN;
+ i < INTLEVEL_SOFTWARE_MAX; i++) {
+ if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+ // See table 4-19 of the 21164 hardware reference
+ ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
+ summary |= (ULL(1) << i);
+ }
+ }
+ }
+
+ uint64_t interrupts = cpu->intr_status();
+
+ if (interrupts) {
+ for (int i = INTLEVEL_EXTERNAL_MIN;
+ i < INTLEVEL_EXTERNAL_MAX; i++) {
+ if (interrupts & (ULL(1) << i)) {
+ // See table 4-19 of the 21164 hardware reference
+ ipl = i;
+ summary |= (ULL(1) << i);
+ }
+ }
+ }
+
+ if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) {
+ thread->inSyscall = true;
+
+ thread->setMiscReg(IPR_ISR, summary);
+ thread->setMiscReg(IPR_INTID, ipl);
+ Fault(new InterruptFault)->invoke(xc);
+ DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
+ thread->readMiscReg(IPR_IPLR), ipl, summary);
+
+ // May need to go 1 inst prior
+ squashPending = true;
+
+ thread->inSyscall = false;
+
+ setSquashInfoFromXC();
+ }
+}
+#endif
+
+template <class Impl>
+void
+InorderBackEnd<Impl>::tick()
+{
+ // Squash due to an external source
+ // Not sure if this or an interrupt has higher priority
+ if (squashPending) {
+ squash(squashSeqNum, squashNextPC);
+ return;
+ }
+
+ // if (interrupt) then set thread PC, stall front end, record that
+ // I'm waiting for it to drain. (for now just squash)
+#if FULL_SYSTEM
+ if (interruptBlocked ||
+ (cpu->checkInterrupts &&
+ cpu->check_interrupts() &&
+ !cpu->inPalMode())) {
+ if (!robEmpty()) {
+ interruptBlocked = true;
+ } else if (robEmpty() && cpu->inPalMode()) {
+ // Will need to let the front end continue a bit until
+ // we're out of pal mode. Hopefully we never get into an
+ // infinite loop...
+ interruptBlocked = false;
+ } else {
+ interruptBlocked = false;
+ checkInterrupts();
+ return;
+ }
+ }
+#endif
+
+ if (status != DcacheMissLoadStall &&
+ status != DcacheMissStoreStall) {
+ for (int i = 0; i < width && (*instsAdded) < width; ++i) {
+ DynInstPtr inst = frontEnd->getInst();
+
+ if (!inst)
+ break;
+
+ instList.push_back(inst);
+
+ (*instsAdded)++;
+ }
+
+#if FULL_SYSTEM
+ if (faultFromFetch && robEmpty() && frontEnd->isEmpty()) {
+ handleFault();
+ } else {
+ executeInsts();
+ }
+#else
+ executeInsts();
+#endif
+ }
+}
+
+template <class Impl>
+void
+InorderBackEnd<Impl>::executeInsts()
+{
+ bool completed_last_inst = true;
+ int insts_to_execute = *instsToExecute;
+ int freed_regs = 0;
+
+ while (insts_to_execute > 0) {
+ assert(!instList.empty());
+ DynInstPtr inst = instList.front();
+
+ commitPC = inst->readPC();
+
+ thread->setPC(commitPC);
+ thread->setNextPC(inst->readNextPC());
+
+#if FULL_SYSTEM
+ int count = 0;
+ Addr oldpc;
+ do {
+ if (count == 0)
+ assert(!thread->inSyscall && !thread->trapPending);
+ oldpc = thread->readPC();
+ cpu->system->pcEventQueue.service(
+ thread->getXCProxy());
+ count++;
+ } while (oldpc != thread->readPC());
+ if (count > 1) {
+ DPRINTF(IBE, "PC skip function event, stopping commit\n");
+ completed_last_inst = false;
+ squashPending = true;
+ break;
+ }
+#endif
+
+ Fault inst_fault = NoFault;
+
+ if (status == DcacheMissComplete) {
+ DPRINTF(IBE, "Completing inst [sn:%lli]\n", inst->seqNum);
+ status = Running;
+ } else if (inst->isMemRef() && status != DcacheMissComplete &&
+ (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
+ DPRINTF(IBE, "Initiating mem op inst [sn:%lli] PC: %#x\n",
+ inst->seqNum, inst->readPC());
+
+ cacheCompletionEvent.inst = inst;
+ inst_fault = inst->initiateAcc();
+ if (inst_fault == NoFault &&
+ status != DcacheMissLoadStall &&
+ status != DcacheMissStoreStall) {
+ inst_fault = inst->completeAcc();
+ }
+ ++thread->funcExeInst;
+ } else {
+ DPRINTF(IBE, "Executing inst [sn:%lli] PC: %#x\n",
+ inst->seqNum, inst->readPC());
+ inst_fault = inst->execute();
+ ++thread->funcExeInst;
+ }
+
+ // Will need to be able to break this loop in case the load
+ // misses. Split access/complete ops would be useful here
+ // with writeback events.
+ if (status == DcacheMissLoadStall) {
+ *instsToExecute = insts_to_execute;
+
+ completed_last_inst = false;
+ break;
+ } else if (status == DcacheMissStoreStall) {
+ // Figure out how to fix this hack. Probably have DcacheMissLoad
+ // vs DcacheMissStore.
+ *instsToExecute = insts_to_execute;
+ completed_last_inst = false;
+/*
+ instList.pop_front();
+ --insts_to_execute;
+ if (inst->traceData) {
+ inst->traceData->finalize();
+ }
+*/
+
+ // Don't really need to stop for a store stall as long as
+ // the memory system is able to handle store forwarding
+ // and such. Breaking out might help avoid the cache
+ // interface becoming blocked.
+ break;
+ }
+
+ inst->setExecuted();
+ inst->setCompleted();
+ inst->setCanCommit();
+
+ instList.pop_front();
+
+ --insts_to_execute;
+ --(*instsToExecute);
+
+ if (inst->traceData) {
+ inst->traceData->finalize();
+ inst->traceData = NULL;
+ }
+
+ if (inst_fault != NoFault) {
+#if FULL_SYSTEM
+ DPRINTF(IBE, "Inst [sn:%lli] PC %#x has a fault\n",
+ inst->seqNum, inst->readPC());
+
+ assert(!thread->inSyscall);
+
+ thread->inSyscall = true;
+
+ // Hack for now; DTB will sometimes need the machine instruction
+ // for when faults happen. So we will set it here, prior to the
+ // DTB possibly needing it for this translation.
+ thread->setInst(
+ static_cast<TheISA::MachInst>(inst->staticInst->machInst));
+
+ // Consider holding onto the trap and waiting until the trap event
+ // happens for this to be executed.
+ inst_fault->invoke(xc);
+
+ // Exit state update mode to avoid accidental updating.
+ thread->inSyscall = false;
+
+ squashPending = true;
+
+ // Generate trap squash event.
+// generateTrapEvent(tid);
+ completed_last_inst = false;
+ break;
+#else // !FULL_SYSTEM
+ panic("fault (%d) detected @ PC %08p", inst_fault,
+ inst->PC);
+#endif // FULL_SYSTEM
+ }
+
+ for (int i = 0; i < inst->numDestRegs(); ++i) {
+ renameTable[inst->destRegIdx(i)] = inst;
+ thread->renameTable[inst->destRegIdx(i)] = inst;
+ ++freed_regs;
+ }
+
+ inst->clearDependents();
+
+ comm->access(0)->doneSeqNum = inst->seqNum;
+
+ if (inst->mispredicted()) {
+ squash(inst->seqNum, inst->readNextPC());
+
+ thread->setNextPC(inst->readNextPC());
+
+ break;
+ } else if (squashPending) {
+ // Something external happened that caused the CPU to squash.
+ // Break out of commit and handle the squash next cycle.
+ break;
+ }
+ // If it didn't mispredict, then it executed fine. Send back its
+ // registers and BP info? What about insts that may still have
+ // latency, like loads? Probably can send back the information after
+ // it is completed.
+
+ // keep an instruction count
+ cpu->numInst++;
+ thread->numInsts++;
+ }
+
+ frontEnd->addFreeRegs(freed_regs);
+
+ assert(insts_to_execute >= 0);
+
+ // Should only advance this if I have executed all instructions.
+ if (insts_to_execute == 0) {
+ numInstsToWB.advance();
+ }
+
+ // Should I set the PC to the next PC here? What do I set next PC to?
+ if (completed_last_inst) {
+ thread->setPC(thread->readNextPC());
+ thread->setNextPC(thread->readPC() + sizeof(MachInst));
+ }
+
+ if (squashPending) {
+ setSquashInfoFromXC();
+ }
+}
+
+template <class Impl>
+void
+InorderBackEnd<Impl>::handleFault()
+{
+ DPRINTF(Commit, "Handling fault from fetch\n");
+
+ assert(!thread->inSyscall);
+
+ thread->inSyscall = true;
+
+ // Consider holding onto the trap and waiting until the trap event
+ // happens for this to be executed.
+ faultFromFetch->invoke(xc);
+
+ // Exit state update mode to avoid accidental updating.
+ thread->inSyscall = false;
+
+ squashPending = true;
+
+ setSquashInfoFromXC();
+}
+
+template <class Impl>
+void
+InorderBackEnd<Impl>::squash(const InstSeqNum &squash_num, const Addr &next_PC)
+{
+ DPRINTF(IBE, "Squashing from [sn:%lli], setting PC to %#x\n",
+ squash_num, next_PC);
+
+ InstListIt squash_it = --(instList.end());
+
+ int freed_regs = 0;
+
+ while (!instList.empty() && (*squash_it)->seqNum > squash_num) {
+ DynInstPtr inst = *squash_it;
+
+ DPRINTF(IBE, "Squashing instruction PC %#x, [sn:%lli].\n",
+ inst->readPC(),
+ inst->seqNum);
+
+ // May cause problems with misc regs
+ freed_regs+= inst->numDestRegs();
+ inst->clearDependents();
+ squash_it--;
+ instList.pop_back();
+ }
+
+ frontEnd->addFreeRegs(freed_regs);
+
+ for (int i = 0; i < latency+1; ++i) {
+ numInstsToWB.advance();
+ }
+
+ squashPending = false;
+
+ // Probably want to make sure that this squash is the one that set the
+ // thread into inSyscall mode.
+ thread->inSyscall = false;
+
+ // Tell front end to squash, reset PC to new one.
+ frontEnd->squash(squash_num, next_PC);
+
+ faultFromFetch = NULL;
+}
+
+template <class Impl>
+void
+InorderBackEnd<Impl>::squashFromXC()
+{
+ // Record that I need to squash
+ squashPending = true;
+
+ thread->inSyscall = true;
+}
+
+template <class Impl>
+void
+InorderBackEnd<Impl>::setSquashInfoFromXC()
+{
+ // Need to handle the case of the instList being empty. In that case
+ // probably any number works, except maybe with stores in the store buffer.
+ squashSeqNum = instList.empty() ? 0 : instList.front()->seqNum - 1;
+
+ squashNextPC = thread->PC;
+}
+
+template <class Impl>
+void
+InorderBackEnd<Impl>::fetchFault(Fault &fault)
+{
+ faultFromFetch = fault;
+}
+
+template <class Impl>
+void
+InorderBackEnd<Impl>::dumpInsts()
+{
+ int num = 0;
+ int valid_num = 0;
+
+ InstListIt inst_list_it = instList.begin();
+
+ cprintf("Inst list size: %i\n", instList.size());
+
+ while (inst_list_it != instList.end())
+ {
+ cprintf("Instruction:%i\n",
+ num);
+ if (!(*inst_list_it)->isSquashed()) {
+ if (!(*inst_list_it)->isIssued()) {
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ } else if ((*inst_list_it)->isMemRef() &&
+ !(*inst_list_it)->memOpDone) {
+ // Loads that have not been marked as executed still count
+ // towards the total instructions.
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ }
+ }
+
+ cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
+ "Issued:%i\nSquashed:%i\n",
+ (*inst_list_it)->readPC(),
+ (*inst_list_it)->seqNum,
+ (*inst_list_it)->threadNumber,
+ (*inst_list_it)->isIssued(),
+ (*inst_list_it)->isSquashed());
+
+ if ((*inst_list_it)->isMemRef()) {
+ cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
+ }
+
+ cprintf("\n");
+
+ inst_list_it++;
+ ++num;
+ }
+}
+
+template <class Impl>
+InorderBackEnd<Impl>::DCacheCompletionEvent::DCacheCompletionEvent(
+ InorderBackEnd *_be)
+ : Event(&mainEventQueue, CPU_Tick_Pri), be(_be)
+{
+// this->setFlags(Event::AutoDelete);
+}
+
+template <class Impl>
+void
+InorderBackEnd<Impl>::DCacheCompletionEvent::process()
+{
+ inst->completeAcc();
+ be->status = DcacheMissComplete;
+}
+
+template <class Impl>
+const char *
+InorderBackEnd<Impl>::DCacheCompletionEvent::description()
+{
+ return "DCache completion event";
+}
diff --git a/cpu/ozone/inst_queue.cc b/cpu/ozone/inst_queue.cc
new file mode 100644
index 000000000..9c61602d9
--- /dev/null
+++ b/cpu/ozone/inst_queue.cc
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu/ozone/dyn_inst.hh"
+#include "cpu/ozone/ozone_impl.hh"
+#include "cpu/ozone/simple_impl.hh"
+#include "cpu/ozone/inst_queue_impl.hh"
+
+// Force instantiation of InstructionQueue.
+template class InstQueue<SimpleImpl>;
+template class InstQueue<OzoneImpl>;
diff --git a/cpu/ozone/inst_queue.hh b/cpu/ozone/inst_queue.hh
new file mode 100644
index 000000000..2cbbb7987
--- /dev/null
+++ b/cpu/ozone/inst_queue.hh
@@ -0,0 +1,506 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_OZONE_INST_QUEUE_HH__
+#define __CPU_OZONE_INST_QUEUE_HH__
+
+#include <list>
+#include <map>
+#include <queue>
+#include <vector>
+
+#include "base/statistics.hh"
+#include "base/timebuf.hh"
+#include "cpu/inst_seq.hh"
+#include "sim/host.hh"
+
+class FUPool;
+class MemInterface;
+
+/**
+ * A standard instruction queue class. It holds ready instructions, in
+ * order, in seperate priority queues to facilitate the scheduling of
+ * instructions. The IQ uses a separate linked list to track dependencies.
+ * Similar to the rename map and the free list, it expects that
+ * floating point registers have their indices start after the integer
+ * registers (ie with 96 int and 96 fp registers, regs 0-95 are integer
+ * and 96-191 are fp). This remains true even for both logical and
+ * physical register indices. The IQ depends on the memory dependence unit to
+ * track when memory operations are ready in terms of ordering; register
+ * dependencies are tracked normally. Right now the IQ also handles the
+ * execution timing; this is mainly to allow back-to-back scheduling without
+ * requiring IEW to be able to peek into the IQ. At the end of the execution
+ * latency, the instruction is put into the queue to execute, where it will
+ * have the execute() function called on it.
+ * @todo: Make IQ able to handle multiple FU pools.
+ */
+template <class Impl>
+class InstQueue
+{
+ public:
+ //Typedefs from the Impl.
+ typedef typename Impl::FullCPU FullCPU;
+ typedef typename Impl::DynInstPtr DynInstPtr;
+ typedef typename Impl::Params Params;
+ typedef typename Impl::IssueStruct IssueStruct;
+/*
+ typedef typename Impl::CPUPol::IEW IEW;
+ typedef typename Impl::CPUPol::MemDepUnit MemDepUnit;
+ typedef typename Impl::CPUPol::IssueStruct IssueStruct;
+ typedef typename Impl::CPUPol::TimeStruct TimeStruct;
+*/
+ // Typedef of iterator through the list of instructions.
+ typedef typename std::list<DynInstPtr>::iterator ListIt;
+
+ friend class Impl::FullCPU;
+#if 0
+ /** FU completion event class. */
+ class FUCompletion : public Event {
+ private:
+ /** Executing instruction. */
+ DynInstPtr inst;
+
+ /** Index of the FU used for executing. */
+ int fuIdx;
+
+ /** Pointer back to the instruction queue. */
+ InstQueue<Impl> *iqPtr;
+
+ public:
+ /** Construct a FU completion event. */
+ FUCompletion(DynInstPtr &_inst, int fu_idx,
+ InstQueue<Impl> *iq_ptr);
+
+ virtual void process();
+ virtual const char *description();
+ };
+#endif
+ /** Constructs an IQ. */
+ InstQueue(Params *params);
+
+ /** Destructs the IQ. */
+ ~InstQueue();
+
+ /** Returns the name of the IQ. */
+ std::string name() const;
+
+ /** Registers statistics. */
+ void regStats();
+
+ /** Sets CPU pointer. */
+ void setCPU(FullCPU *_cpu) { cpu = _cpu; }
+#if 0
+ /** Sets active threads list. */
+ void setActiveThreads(list<unsigned> *at_ptr);
+
+ /** Sets the IEW pointer. */
+ void setIEW(IEW *iew_ptr) { iewStage = iew_ptr; }
+#endif
+ /** Sets the timer buffer between issue and execute. */
+ void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
+#if 0
+ /** Sets the global time buffer. */
+ void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
+
+ /** Number of entries needed for given amount of threads. */
+ int entryAmount(int num_threads);
+
+ /** Resets max entries for all threads. */
+ void resetEntries();
+#endif
+ /** Returns total number of free entries. */
+ unsigned numFreeEntries();
+
+ /** Returns number of free entries for a thread. */
+ unsigned numFreeEntries(unsigned tid);
+
+ /** Returns whether or not the IQ is full. */
+ bool isFull();
+
+ /** Returns whether or not the IQ is full for a specific thread. */
+ bool isFull(unsigned tid);
+
+ /** Returns if there are any ready instructions in the IQ. */
+ bool hasReadyInsts();
+
+ /** Inserts a new instruction into the IQ. */
+ void insert(DynInstPtr &new_inst);
+
+ /** Inserts a new, non-speculative instruction into the IQ. */
+ void insertNonSpec(DynInstPtr &new_inst);
+#if 0
+ /**
+ * Advances the tail of the IQ, used if an instruction is not added to the
+ * IQ for scheduling.
+ * @todo: Rename this function.
+ */
+ void advanceTail(DynInstPtr &inst);
+
+ /** Process FU completion event. */
+ void processFUCompletion(DynInstPtr &inst, int fu_idx);
+#endif
+ /**
+ * Schedules ready instructions, adding the ready ones (oldest first) to
+ * the queue to execute.
+ */
+ void scheduleReadyInsts();
+
+ /** Schedules a single specific non-speculative instruction. */
+ void scheduleNonSpec(const InstSeqNum &inst);
+
+ /**
+ * Commits all instructions up to and including the given sequence number,
+ * for a specific thread.
+ */
+ void commit(const InstSeqNum &inst, unsigned tid = 0);
+
+ /** Wakes all dependents of a completed instruction. */
+ void wakeDependents(DynInstPtr &completed_inst);
+
+ /** Adds a ready memory instruction to the ready list. */
+ void addReadyMemInst(DynInstPtr &ready_inst);
+#if 0
+ /**
+ * Reschedules a memory instruction. It will be ready to issue once
+ * replayMemInst() is called.
+ */
+ void rescheduleMemInst(DynInstPtr &resched_inst);
+
+ /** Replays a memory instruction. It must be rescheduled first. */
+ void replayMemInst(DynInstPtr &replay_inst);
+#endif
+ /** Completes a memory operation. */
+ void completeMemInst(DynInstPtr &completed_inst);
+#if 0
+ /** Indicates an ordering violation between a store and a load. */
+ void violation(DynInstPtr &store, DynInstPtr &faulting_load);
+#endif
+ /**
+ * Squashes instructions for a thread. Squashing information is obtained
+ * from the time buffer.
+ */
+ void squash(unsigned tid); // Probably want the ISN
+
+ /** Returns the number of used entries for a thread. */
+ unsigned getCount(unsigned tid) { return count[tid]; };
+
+ /** Updates the number of free entries. */
+ void updateFreeEntries(int num) { freeEntries += num; }
+
+ /** Debug function to print all instructions. */
+ void printInsts();
+
+ private:
+ /** Does the actual squashing. */
+ void doSquash(unsigned tid);
+
+ /////////////////////////
+ // Various pointers
+ /////////////////////////
+
+ /** Pointer to the CPU. */
+ FullCPU *cpu;
+
+ /** Cache interface. */
+ MemInterface *dcacheInterface;
+#if 0
+ /** Pointer to IEW stage. */
+ IEW *iewStage;
+
+ /** The memory dependence unit, which tracks/predicts memory dependences
+ * between instructions.
+ */
+ MemDepUnit memDepUnit[Impl::MaxThreads];
+#endif
+ /** The queue to the execute stage. Issued instructions will be written
+ * into it.
+ */
+ TimeBuffer<IssueStruct> *issueToExecuteQueue;
+#if 0
+ /** The backwards time buffer. */
+ TimeBuffer<TimeStruct> *timeBuffer;
+
+ /** Wire to read information from timebuffer. */
+ typename TimeBuffer<TimeStruct>::wire fromCommit;
+
+ /** Function unit pool. */
+ FUPool *fuPool;
+#endif
+ //////////////////////////////////////
+ // Instruction lists, ready queues, and ordering
+ //////////////////////////////////////
+
+ /** List of all the instructions in the IQ (some of which may be issued). */
+ std::list<DynInstPtr> instList[Impl::MaxThreads];
+
+ /**
+ * Struct for comparing entries to be added to the priority queue. This
+ * gives reverse ordering to the instructions in terms of sequence
+ * numbers: the instructions with smaller sequence numbers (and hence
+ * are older) will be at the top of the priority queue.
+ */
+ struct pqCompare {
+ bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
+ {
+ return lhs->seqNum > rhs->seqNum;
+ }
+ };
+
+ /**
+ * Struct for an IQ entry. It includes the instruction and an iterator
+ * to the instruction's spot in the IQ.
+ */
+ struct IQEntry {
+ DynInstPtr inst;
+ ListIt iqIt;
+ };
+
+ typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare>
+ ReadyInstQueue;
+
+ typedef std::map<DynInstPtr, pqCompare> ReadyInstMap;
+ typedef typename std::map<DynInstPtr, pqCompare>::iterator ReadyMapIt;
+
+ /** List of ready instructions.
+ */
+ ReadyInstQueue readyInsts;
+
+ /** List of non-speculative instructions that will be scheduled
+ * once the IQ gets a signal from commit. While it's redundant to
+ * have the key be a part of the value (the sequence number is stored
+ * inside of DynInst), when these instructions are woken up only
+ * the sequence number will be available. Thus it is most efficient to be
+ * able to search by the sequence number alone.
+ */
+ std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
+
+ typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
+#if 0
+ /** Entry for the list age ordering by op class. */
+ struct ListOrderEntry {
+ OpClass queueType;
+ InstSeqNum oldestInst;
+ };
+
+ /** List that contains the age order of the oldest instruction of each
+ * ready queue. Used to select the oldest instruction available
+ * among op classes.
+ */
+ std::list<ListOrderEntry> listOrder;
+
+ typedef typename std::list<ListOrderEntry>::iterator ListOrderIt;
+
+ /** Tracks if each ready queue is on the age order list. */
+ bool queueOnList[Num_OpClasses];
+
+ /** Iterators of each ready queue. Points to their spot in the age order
+ * list.
+ */
+ ListOrderIt readyIt[Num_OpClasses];
+
+ /** Add an op class to the age order list. */
+ void addToOrderList(OpClass op_class);
+
+ /**
+ * Called when the oldest instruction has been removed from a ready queue;
+ * this places that ready queue into the proper spot in the age order list.
+ */
+ void moveToYoungerInst(ListOrderIt age_order_it);
+#endif
+ //////////////////////////////////////
+ // Various parameters
+ //////////////////////////////////////
+#if 0
+ /** IQ Resource Sharing Policy */
+ enum IQPolicy {
+ Dynamic,
+ Partitioned,
+ Threshold
+ };
+
+ /** IQ sharing policy for SMT. */
+ IQPolicy iqPolicy;
+#endif
+ /** Number of Total Threads*/
+ unsigned numThreads;
+#if 0
+ /** Pointer to list of active threads. */
+ list<unsigned> *activeThreads;
+#endif
+ /** Per Thread IQ count */
+ unsigned count[Impl::MaxThreads];
+
+ /** Max IQ Entries Per Thread */
+ unsigned maxEntries[Impl::MaxThreads];
+
+ /** Number of free IQ entries left. */
+ unsigned freeEntries;
+
+ /** The number of entries in the instruction queue. */
+ unsigned numEntries;
+
+ /** The total number of instructions that can be issued in one cycle. */
+ unsigned totalWidth;
+#if 0
+ /** The number of physical registers in the CPU. */
+ unsigned numPhysRegs;
+
+ /** The number of physical integer registers in the CPU. */
+ unsigned numPhysIntRegs;
+
+ /** The number of floating point registers in the CPU. */
+ unsigned numPhysFloatRegs;
+#endif
+ /** Delay between commit stage and the IQ.
+ * @todo: Make there be a distinction between the delays within IEW.
+ */
+ unsigned commitToIEWDelay;
+
+ //////////////////////////////////
+ // Variables needed for squashing
+ //////////////////////////////////
+
+ /** The sequence number of the squashed instruction. */
+ InstSeqNum squashedSeqNum[Impl::MaxThreads];
+
+ /** Iterator that points to the last instruction that has been squashed.
+ * This will not be valid unless the IQ is in the process of squashing.
+ */
+ ListIt squashIt[Impl::MaxThreads];
+#if 0
+ ///////////////////////////////////
+ // Dependency graph stuff
+ ///////////////////////////////////
+
+ class DependencyEntry
+ {
+ public:
+ DependencyEntry()
+ : inst(NULL), next(NULL)
+ { }
+
+ DynInstPtr inst;
+ //Might want to include data about what arch. register the
+ //dependence is waiting on.
+ DependencyEntry *next;
+
+ //This function, and perhaps this whole class, stand out a little
+ //bit as they don't fit a classification well. I want access
+ //to the underlying structure of the linked list, yet at
+ //the same time it feels like this should be something abstracted
+ //away. So for now it will sit here, within the IQ, until
+ //a better implementation is decided upon.
+ // This function probably shouldn't be within the entry...
+ void insert(DynInstPtr &new_inst);
+
+ void remove(DynInstPtr &inst_to_remove);
+
+ // Debug variable, remove when done testing.
+ static unsigned mem_alloc_counter;
+ };
+
+ /** Array of linked lists. Each linked list is a list of all the
+ * instructions that depend upon a given register. The actual
+ * register's index is used to index into the graph; ie all
+ * instructions in flight that are dependent upon r34 will be
+ * in the linked list of dependGraph[34].
+ */
+ DependencyEntry *dependGraph;
+
+ /** A cache of the recently woken registers. It is 1 if the register
+ * has been woken up recently, and 0 if the register has been added
+ * to the dependency graph and has not yet received its value. It
+ * is basically a secondary scoreboard, and should pretty much mirror
+ * the scoreboard that exists in the rename map.
+ */
+ vector<bool> regScoreboard;
+
+ /** Adds an instruction to the dependency graph, as a producer. */
+ bool addToDependents(DynInstPtr &new_inst);
+
+ /** Adds an instruction to the dependency graph, as a consumer. */
+ void createDependency(DynInstPtr &new_inst);
+#endif
+ /** Moves an instruction to the ready queue if it is ready. */
+ void addIfReady(DynInstPtr &inst);
+
+ /** Debugging function to count how many entries are in the IQ. It does
+ * a linear walk through the instructions, so do not call this function
+ * during normal execution.
+ */
+ int countInsts();
+#if 0
+ /** Debugging function to dump out the dependency graph.
+ */
+ void dumpDependGraph();
+#endif
+ /** Debugging function to dump all the list sizes, as well as print
+ * out the list of nonspeculative instructions. Should not be used
+ * in any other capacity, but it has no harmful sideaffects.
+ */
+ void dumpLists();
+
+ /** Debugging function to dump out all instructions that are in the
+ * IQ.
+ */
+ void dumpInsts();
+
+ /** Stat for number of instructions added. */
+ Stats::Scalar<> iqInstsAdded;
+ /** Stat for number of non-speculative instructions added. */
+ Stats::Scalar<> iqNonSpecInstsAdded;
+// Stats::Scalar<> iqIntInstsAdded;
+ /** Stat for number of integer instructions issued. */
+ Stats::Scalar<> iqIntInstsIssued;
+// Stats::Scalar<> iqFloatInstsAdded;
+ /** Stat for number of floating point instructions issued. */
+ Stats::Scalar<> iqFloatInstsIssued;
+// Stats::Scalar<> iqBranchInstsAdded;
+ /** Stat for number of branch instructions issued. */
+ Stats::Scalar<> iqBranchInstsIssued;
+// Stats::Scalar<> iqMemInstsAdded;
+ /** Stat for number of memory instructions issued. */
+ Stats::Scalar<> iqMemInstsIssued;
+// Stats::Scalar<> iqMiscInstsAdded;
+ /** Stat for number of miscellaneous instructions issued. */
+ Stats::Scalar<> iqMiscInstsIssued;
+ /** Stat for number of squashed instructions that were ready to issue. */
+ Stats::Scalar<> iqSquashedInstsIssued;
+ /** Stat for number of squashed instructions examined when squashing. */
+ Stats::Scalar<> iqSquashedInstsExamined;
+ /** Stat for number of squashed instruction operands examined when
+ * squashing.
+ */
+ Stats::Scalar<> iqSquashedOperandsExamined;
+ /** Stat for number of non-speculative instructions removed due to a squash.
+ */
+ Stats::Scalar<> iqSquashedNonSpecRemoved;
+
+};
+
+#endif //__CPU_OZONE_INST_QUEUE_HH__
diff --git a/cpu/ozone/inst_queue_impl.hh b/cpu/ozone/inst_queue_impl.hh
new file mode 100644
index 000000000..0523c68d6
--- /dev/null
+++ b/cpu/ozone/inst_queue_impl.hh
@@ -0,0 +1,1341 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// Todo:
+// Current ordering allows for 0 cycle added-to-scheduled. Could maybe fake
+// it; either do in reverse order, or have added instructions put into a
+// different ready queue that, in scheduleRreadyInsts(), gets put onto the
+// normal ready queue. This would however give only a one cycle delay,
+// but probably is more flexible to actually add in a delay parameter than
+// just running it backwards.
+
+#include <vector>
+
+#include "sim/root.hh"
+
+#include "cpu/ozone/inst_queue.hh"
+#if 0
+template <class Impl>
+InstQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
+ int fu_idx,
+ InstQueue<Impl> *iq_ptr)
+ : Event(&mainEventQueue, Stat_Event_Pri),
+ inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr)
+{
+ this->setFlags(Event::AutoDelete);
+}
+
+template <class Impl>
+void
+InstQueue<Impl>::FUCompletion::process()
+{
+ iqPtr->processFUCompletion(inst, fuIdx);
+}
+
+
+template <class Impl>
+const char *
+InstQueue<Impl>::FUCompletion::description()
+{
+ return "Functional unit completion event";
+}
+#endif
+template <class Impl>
+InstQueue<Impl>::InstQueue(Params *params)
+ : dcacheInterface(params->dcacheInterface),
+// fuPool(params->fuPool),
+ numEntries(params->numIQEntries),
+ totalWidth(params->issueWidth),
+// numPhysIntRegs(params->numPhysIntRegs),
+// numPhysFloatRegs(params->numPhysFloatRegs),
+ commitToIEWDelay(params->commitToIEWDelay)
+{
+// assert(fuPool);
+
+// numThreads = params->numberOfThreads;
+ numThreads = 1;
+
+ //Initialize thread IQ counts
+ for (int i = 0; i <numThreads; i++) {
+ count[i] = 0;
+ }
+
+ // Initialize the number of free IQ entries.
+ freeEntries = numEntries;
+
+ // Set the number of physical registers as the number of int + float
+// numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
+
+// DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs);
+
+ //Create an entry for each physical register within the
+ //dependency graph.
+// dependGraph = new DependencyEntry[numPhysRegs];
+
+ // Resize the register scoreboard.
+// regScoreboard.resize(numPhysRegs);
+/*
+ //Initialize Mem Dependence Units
+ for (int i = 0; i < numThreads; i++) {
+ memDepUnit[i].init(params,i);
+ memDepUnit[i].setIQ(this);
+ }
+
+ // Initialize all the head pointers to point to NULL, and all the
+ // entries as unready.
+ // Note that in actuality, the registers corresponding to the logical
+ // registers start off as ready. However this doesn't matter for the
+ // IQ as the instruction should have been correctly told if those
+ // registers are ready in rename. Thus it can all be initialized as
+ // unready.
+ for (int i = 0; i < numPhysRegs; ++i) {
+ dependGraph[i].next = NULL;
+ dependGraph[i].inst = NULL;
+ regScoreboard[i] = false;
+ }
+*/
+ for (int i = 0; i < numThreads; ++i) {
+ squashedSeqNum[i] = 0;
+ }
+/*
+ for (int i = 0; i < Num_OpClasses; ++i) {
+ queueOnList[i] = false;
+ readyIt[i] = listOrder.end();
+ }
+
+ string policy = params->smtIQPolicy;
+
+ //Convert string to lowercase
+ std::transform(policy.begin(), policy.end(), policy.begin(),
+ (int(*)(int)) tolower);
+
+ //Figure out resource sharing policy
+ if (policy == "dynamic") {
+ iqPolicy = Dynamic;
+
+ //Set Max Entries to Total ROB Capacity
+ for (int i = 0; i < numThreads; i++) {
+ maxEntries[i] = numEntries;
+ }
+
+ } else if (policy == "partitioned") {
+ iqPolicy = Partitioned;
+
+ //@todo:make work if part_amt doesnt divide evenly.
+ int part_amt = numEntries / numThreads;
+
+ //Divide ROB up evenly
+ for (int i = 0; i < numThreads; i++) {
+ maxEntries[i] = part_amt;
+ }
+
+ DPRINTF(Fetch, "IQ sharing policy set to Partitioned:"
+ "%i entries per thread.\n",part_amt);
+
+ } else if (policy == "threshold") {
+ iqPolicy = Threshold;
+
+ double threshold = (double)params->smtIQThreshold / 100;
+
+ int thresholdIQ = (int)((double)threshold * numEntries);
+
+ //Divide up by threshold amount
+ for (int i = 0; i < numThreads; i++) {
+ maxEntries[i] = thresholdIQ;
+ }
+
+ DPRINTF(Fetch, "IQ sharing policy set to Threshold:"
+ "%i entries per thread.\n",thresholdIQ);
+ } else {
+ assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
+ "Partitioned, Threshold}");
+ }
+*/
+}
+
+template <class Impl>
+InstQueue<Impl>::~InstQueue()
+{
+ // Clear the dependency graph
+/*
+ DependencyEntry *curr;
+ DependencyEntry *prev;
+
+ for (int i = 0; i < numPhysRegs; ++i) {
+ curr = dependGraph[i].next;
+
+ while (curr) {
+ DependencyEntry::mem_alloc_counter--;
+
+ prev = curr;
+ curr = prev->next;
+ prev->inst = NULL;
+
+ delete prev;
+ }
+
+ if (dependGraph[i].inst) {
+ dependGraph[i].inst = NULL;
+ }
+
+ dependGraph[i].next = NULL;
+ }
+
+ assert(DependencyEntry::mem_alloc_counter == 0);
+
+ delete [] dependGraph;
+*/
+}
+
+template <class Impl>
+std::string
+InstQueue<Impl>::name() const
+{
+ return cpu->name() + ".iq";
+}
+
+template <class Impl>
+void
+InstQueue<Impl>::regStats()
+{
+ iqInstsAdded
+ .name(name() + ".iqInstsAdded")
+ .desc("Number of instructions added to the IQ (excludes non-spec)")
+ .prereq(iqInstsAdded);
+
+ iqNonSpecInstsAdded
+ .name(name() + ".iqNonSpecInstsAdded")
+ .desc("Number of non-speculative instructions added to the IQ")
+ .prereq(iqNonSpecInstsAdded);
+
+// iqIntInstsAdded;
+
+ iqIntInstsIssued
+ .name(name() + ".iqIntInstsIssued")
+ .desc("Number of integer instructions issued")
+ .prereq(iqIntInstsIssued);
+
+// iqFloatInstsAdded;
+
+ iqFloatInstsIssued
+ .name(name() + ".iqFloatInstsIssued")
+ .desc("Number of float instructions issued")
+ .prereq(iqFloatInstsIssued);
+
+// iqBranchInstsAdded;
+
+ iqBranchInstsIssued
+ .name(name() + ".iqBranchInstsIssued")
+ .desc("Number of branch instructions issued")
+ .prereq(iqBranchInstsIssued);
+
+// iqMemInstsAdded;
+
+ iqMemInstsIssued
+ .name(name() + ".iqMemInstsIssued")
+ .desc("Number of memory instructions issued")
+ .prereq(iqMemInstsIssued);
+
+// iqMiscInstsAdded;
+
+ iqMiscInstsIssued
+ .name(name() + ".iqMiscInstsIssued")
+ .desc("Number of miscellaneous instructions issued")
+ .prereq(iqMiscInstsIssued);
+
+ iqSquashedInstsIssued
+ .name(name() + ".iqSquashedInstsIssued")
+ .desc("Number of squashed instructions issued")
+ .prereq(iqSquashedInstsIssued);
+
+ iqSquashedInstsExamined
+ .name(name() + ".iqSquashedInstsExamined")
+ .desc("Number of squashed instructions iterated over during squash;"
+ " mainly for profiling")
+ .prereq(iqSquashedInstsExamined);
+
+ iqSquashedOperandsExamined
+ .name(name() + ".iqSquashedOperandsExamined")
+ .desc("Number of squashed operands that are examined and possibly "
+ "removed from graph")
+ .prereq(iqSquashedOperandsExamined);
+
+ iqSquashedNonSpecRemoved
+ .name(name() + ".iqSquashedNonSpecRemoved")
+ .desc("Number of squashed non-spec instructions that were removed")
+ .prereq(iqSquashedNonSpecRemoved);
+/*
+ for ( int i=0; i < numThreads; i++) {
+ // Tell mem dependence unit to reg stats as well.
+ memDepUnit[i].regStats();
+ }
+*/
+}
+/*
+template <class Impl>
+void
+InstQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+{
+ DPRINTF(IQ, "Setting active threads list pointer.\n");
+ activeThreads = at_ptr;
+}
+*/
+template <class Impl>
+void
+InstQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
+{
+ DPRINTF(IQ, "Set the issue to execute queue.\n");
+ issueToExecuteQueue = i2e_ptr;
+}
+/*
+template <class Impl>
+void
+InstQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
+{
+ DPRINTF(IQ, "Set the time buffer.\n");
+ timeBuffer = tb_ptr;
+
+ fromCommit = timeBuffer->getWire(-commitToIEWDelay);
+}
+
+template <class Impl>
+int
+InstQueue<Impl>::entryAmount(int num_threads)
+{
+ if (iqPolicy == Partitioned) {
+ return numEntries / num_threads;
+ } else {
+ return 0;
+ }
+}
+
+
+template <class Impl>
+void
+InstQueue<Impl>::resetEntries()
+{
+ if (iqPolicy != Dynamic || numThreads > 1) {
+ int active_threads = (*activeThreads).size();
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+ list<unsigned>::iterator list_end = (*activeThreads).end();
+
+ while (threads != list_end) {
+ if (iqPolicy == Partitioned) {
+ maxEntries[*threads++] = numEntries / active_threads;
+ } else if(iqPolicy == Threshold && active_threads == 1) {
+ maxEntries[*threads++] = numEntries;
+ }
+ }
+ }
+}
+*/
+template <class Impl>
+unsigned
+InstQueue<Impl>::numFreeEntries()
+{
+ return freeEntries;
+}
+
+template <class Impl>
+unsigned
+InstQueue<Impl>::numFreeEntries(unsigned tid)
+{
+ return maxEntries[tid] - count[tid];
+}
+
+// Might want to do something more complex if it knows how many instructions
+// will be issued this cycle.
+template <class Impl>
+bool
+InstQueue<Impl>::isFull()
+{
+ if (freeEntries == 0) {
+ return(true);
+ } else {
+ return(false);
+ }
+}
+
+template <class Impl>
+bool
+InstQueue<Impl>::isFull(unsigned tid)
+{
+ if (numFreeEntries(tid) == 0) {
+ return(true);
+ } else {
+ return(false);
+ }
+}
+
+template <class Impl>
+bool
+InstQueue<Impl>::hasReadyInsts()
+{
+/*
+ if (!listOrder.empty()) {
+ return true;
+ }
+
+ for (int i = 0; i < Num_OpClasses; ++i) {
+ if (!readyInsts[i].empty()) {
+ return true;
+ }
+ }
+
+ return false;
+*/
+ return readyInsts.empty();
+}
+
+template <class Impl>
+void
+InstQueue<Impl>::insert(DynInstPtr &new_inst)
+{
+ // Make sure the instruction is valid
+ assert(new_inst);
+
+ DPRINTF(IQ, "Adding instruction PC %#x to the IQ.\n",
+ new_inst->readPC());
+
+ // Check if there are any free entries. Panic if there are none.
+ // Might want to have this return a fault in the future instead of
+ // panicing.
+ assert(freeEntries != 0);
+
+ instList[new_inst->threadNumber].push_back(new_inst);
+
+ // Decrease the number of free entries.
+ --freeEntries;
+
+ //Mark Instruction as in IQ
+// new_inst->setInIQ();
+/*
+ // Look through its source registers (physical regs), and mark any
+ // dependencies.
+ addToDependents(new_inst);
+
+ // Have this instruction set itself as the producer of its destination
+ // register(s).
+ createDependency(new_inst);
+*/
+ // If it's a memory instruction, add it to the memory dependency
+ // unit.
+// if (new_inst->isMemRef()) {
+// memDepUnit[new_inst->threadNumber].insert(new_inst);
+// } else {
+ // If the instruction is ready then add it to the ready list.
+ addIfReady(new_inst);
+// }
+
+ ++iqInstsAdded;
+
+
+ //Update Thread IQ Count
+ count[new_inst->threadNumber]++;
+
+ assert(freeEntries == (numEntries - countInsts()));
+}
+
+template <class Impl>
+void
+InstQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
+{
+ nonSpecInsts[new_inst->seqNum] = new_inst;
+
+ // @todo: Clean up this code; can do it by setting inst as unable
+ // to issue, then calling normal insert on the inst.
+
+ // Make sure the instruction is valid
+ assert(new_inst);
+
+ DPRINTF(IQ, "Adding instruction PC %#x to the IQ.\n",
+ new_inst->readPC());
+
+ // Check if there are any free entries. Panic if there are none.
+ // Might want to have this return a fault in the future instead of
+ // panicing.
+ assert(freeEntries != 0);
+
+ instList[new_inst->threadNumber].push_back(new_inst);
+
+ // Decrease the number of free entries.
+ --freeEntries;
+
+ //Mark Instruction as in IQ
+// new_inst->setInIQ();
+/*
+ // Have this instruction set itself as the producer of its destination
+ // register(s).
+ createDependency(new_inst);
+
+ // If it's a memory instruction, add it to the memory dependency
+ // unit.
+ if (new_inst->isMemRef()) {
+ memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
+ }
+*/
+ ++iqNonSpecInstsAdded;
+
+ //Update Thread IQ Count
+ count[new_inst->threadNumber]++;
+
+ assert(freeEntries == (numEntries - countInsts()));
+}
+/*
+template <class Impl>
+void
+InstQueue<Impl>::advanceTail(DynInstPtr &inst)
+{
+ // Have this instruction set itself as the producer of its destination
+ // register(s).
+ createDependency(inst);
+}
+
+template <class Impl>
+void
+InstQueue<Impl>::addToOrderList(OpClass op_class)
+{
+ assert(!readyInsts[op_class].empty());
+
+ ListOrderEntry queue_entry;
+
+ queue_entry.queueType = op_class;
+
+ queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
+
+ ListOrderIt list_it = listOrder.begin();
+ ListOrderIt list_end_it = listOrder.end();
+
+ while (list_it != list_end_it) {
+ if ((*list_it).oldestInst > queue_entry.oldestInst) {
+ break;
+ }
+
+ list_it++;
+ }
+
+ readyIt[op_class] = listOrder.insert(list_it, queue_entry);
+ queueOnList[op_class] = true;
+}
+
+template <class Impl>
+void
+InstQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
+{
+ // Get iterator of next item on the list
+ // Delete the original iterator
+ // Determine if the next item is either the end of the list or younger
+ // than the new instruction. If so, then add in a new iterator right here.
+ // If not, then move along.
+ ListOrderEntry queue_entry;
+ OpClass op_class = (*list_order_it).queueType;
+ ListOrderIt next_it = list_order_it;
+
+ ++next_it;
+
+ queue_entry.queueType = op_class;
+ queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
+
+ while (next_it != listOrder.end() &&
+ (*next_it).oldestInst < queue_entry.oldestInst) {
+ ++next_it;
+ }
+
+ readyIt[op_class] = listOrder.insert(next_it, queue_entry);
+}
+
+template <class Impl>
+void
+InstQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
+{
+ // The CPU could have been sleeping until this op completed (*extremely*
+ // long latency op). Wake it if it was. This may be overkill.
+ iewStage->wakeCPU();
+
+ fuPool->freeUnit(fu_idx);
+
+ int &size = issueToExecuteQueue->access(0)->size;
+
+ issueToExecuteQueue->access(0)->insts[size++] = inst;
+}
+*/
+// @todo: Figure out a better way to remove the squashed items from the
+// lists. Checking the top item of each list to see if it's squashed
+// wastes time and forces jumps.
+template <class Impl>
+void
+InstQueue<Impl>::scheduleReadyInsts()
+{
+ DPRINTF(IQ, "Attempting to schedule ready instructions from "
+ "the IQ.\n");
+
+// IssueStruct *i2e_info = issueToExecuteQueue->access(0);
+/*
+ // Will need to reorder the list if either a queue is not on the list,
+ // or it has an older instruction than last time.
+ for (int i = 0; i < Num_OpClasses; ++i) {
+ if (!readyInsts[i].empty()) {
+ if (!queueOnList[i]) {
+ addToOrderList(OpClass(i));
+ } else if (readyInsts[i].top()->seqNum <
+ (*readyIt[i]).oldestInst) {
+ listOrder.erase(readyIt[i]);
+ addToOrderList(OpClass(i));
+ }
+ }
+ }
+
+ // Have iterator to head of the list
+ // While I haven't exceeded bandwidth or reached the end of the list,
+ // Try to get a FU that can do what this op needs.
+ // If successful, change the oldestInst to the new top of the list, put
+ // the queue in the proper place in the list.
+ // Increment the iterator.
+ // This will avoid trying to schedule a certain op class if there are no
+ // FUs that handle it.
+ ListOrderIt order_it = listOrder.begin();
+ ListOrderIt order_end_it = listOrder.end();
+ int total_issued = 0;
+ int exec_queue_slot = i2e_info->size;
+
+ while (exec_queue_slot < totalWidth && order_it != order_end_it) {
+ OpClass op_class = (*order_it).queueType;
+
+ assert(!readyInsts[op_class].empty());
+
+ DynInstPtr issuing_inst = readyInsts[op_class].top();
+
+ assert(issuing_inst->seqNum == (*order_it).oldestInst);
+
+ if (issuing_inst->isSquashed()) {
+ readyInsts[op_class].pop();
+
+ if (!readyInsts[op_class].empty()) {
+ moveToYoungerInst(order_it);
+ } else {
+ readyIt[op_class] = listOrder.end();
+ queueOnList[op_class] = false;
+ }
+
+ listOrder.erase(order_it++);
+
+ ++iqSquashedInstsIssued;
+
+ continue;
+ }
+
+ int idx = fuPool->getUnit(op_class);
+
+ if (idx != -1) {
+ int op_latency = fuPool->getOpLatency(op_class);
+
+ if (op_latency == 1) {
+ i2e_info->insts[exec_queue_slot++] = issuing_inst;
+ i2e_info->size++;
+
+ // Add the FU onto the list of FU's to be freed next cycle.
+ fuPool->freeUnit(idx);
+ } else {
+ int issue_latency = fuPool->getIssueLatency(op_class);
+
+ if (issue_latency > 1) {
+ // Generate completion event for the FU
+ FUCompletion *execution = new FUCompletion(issuing_inst,
+ idx, this);
+
+ execution->schedule(curTick + issue_latency - 1);
+ } else {
+ i2e_info->insts[exec_queue_slot++] = issuing_inst;
+ i2e_info->size++;
+
+ // Add the FU onto the list of FU's to be freed next cycle.
+ fuPool->freeUnit(idx);
+ }
+ }
+
+ DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x "
+ "[sn:%lli]\n",
+ issuing_inst->threadNumber, issuing_inst->readPC(),
+ issuing_inst->seqNum);
+
+ readyInsts[op_class].pop();
+
+ if (!readyInsts[op_class].empty()) {
+ moveToYoungerInst(order_it);
+ } else {
+ readyIt[op_class] = listOrder.end();
+ queueOnList[op_class] = false;
+ }
+
+ issuing_inst->setIssued();
+ ++total_issued;
+
+ if (!issuing_inst->isMemRef()) {
+ // Memory instructions can not be freed from the IQ until they
+ // complete.
+ ++freeEntries;
+ count[issuing_inst->threadNumber]--;
+ issuing_inst->removeInIQ();
+ } else {
+ memDepUnit[issuing_inst->threadNumber].issue(issuing_inst);
+ }
+
+ listOrder.erase(order_it++);
+ } else {
+ ++order_it;
+ }
+ }
+
+ if (total_issued) {
+ cpu->activityThisCycle();
+ } else {
+ DPRINTF(IQ, "Not able to schedule any instructions.\n");
+ }
+*/
+}
+
+template <class Impl>
+void
+InstQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
+{
+ DPRINTF(IQ, "Marking nonspeculative instruction with sequence "
+ "number %i as ready to execute.\n", inst);
+
+ NonSpecMapIt inst_it = nonSpecInsts.find(inst);
+
+ assert(inst_it != nonSpecInsts.end());
+
+// unsigned tid = (*inst_it).second->threadNumber;
+
+ // Mark this instruction as ready to issue.
+ (*inst_it).second->setCanIssue();
+
+ // Now schedule the instruction.
+// if (!(*inst_it).second->isMemRef()) {
+ addIfReady((*inst_it).second);
+// } else {
+// memDepUnit[tid].nonSpecInstReady((*inst_it).second);
+// }
+
+ nonSpecInsts.erase(inst_it);
+}
+
+template <class Impl>
+void
+InstQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid)
+{
+ /*Need to go through each thread??*/
+ DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
+ tid,inst);
+
+ ListIt iq_it = instList[tid].begin();
+
+ while (iq_it != instList[tid].end() &&
+ (*iq_it)->seqNum <= inst) {
+ ++iq_it;
+ instList[tid].pop_front();
+ }
+
+ assert(freeEntries == (numEntries - countInsts()));
+}
+
+template <class Impl>
+void
+InstQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
+{
+ DPRINTF(IQ, "Waking dependents of completed instruction.\n");
+ // Look at the physical destination register of the DynInst
+ // and look it up on the dependency graph. Then mark as ready
+ // any instructions within the instruction queue.
+/*
+ DependencyEntry *curr;
+ DependencyEntry *prev;
+*/
+ // Tell the memory dependence unit to wake any dependents on this
+ // instruction if it is a memory instruction. Also complete the memory
+ // instruction at this point since we know it executed fine.
+ // @todo: Might want to rename "completeMemInst" to
+ // something that indicates that it won't need to be replayed, and call
+ // this earlier. Might not be a big deal.
+ if (completed_inst->isMemRef()) {
+// memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
+ completeMemInst(completed_inst);
+ }
+ completed_inst->wakeDependents();
+/*
+ for (int dest_reg_idx = 0;
+ dest_reg_idx < completed_inst->numDestRegs();
+ dest_reg_idx++)
+ {
+ PhysRegIndex dest_reg =
+ completed_inst->renamedDestRegIdx(dest_reg_idx);
+
+ // Special case of uniq or control registers. They are not
+ // handled by the IQ and thus have no dependency graph entry.
+ // @todo Figure out a cleaner way to handle this.
+ if (dest_reg >= numPhysRegs) {
+ continue;
+ }
+
+ DPRINTF(IQ, "Waking any dependents on register %i.\n",
+ (int) dest_reg);
+
+ //Maybe abstract this part into a function.
+ //Go through the dependency chain, marking the registers as ready
+ //within the waiting instructions.
+
+ curr = dependGraph[dest_reg].next;
+
+ while (curr) {
+ DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
+ curr->inst->readPC());
+
+ // Might want to give more information to the instruction
+ // so that it knows which of its source registers is ready.
+ // However that would mean that the dependency graph entries
+ // would need to hold the src_reg_idx.
+ curr->inst->markSrcRegReady();
+
+ addIfReady(curr->inst);
+
+ DependencyEntry::mem_alloc_counter--;
+
+ prev = curr;
+ curr = prev->next;
+ prev->inst = NULL;
+
+ delete prev;
+ }
+
+ // Reset the head node now that all of its dependents have been woken
+ // up.
+ dependGraph[dest_reg].next = NULL;
+ dependGraph[dest_reg].inst = NULL;
+
+ // Mark the scoreboard as having that register ready.
+ regScoreboard[dest_reg] = true;
+ }
+*/
+}
+
+template <class Impl>
+void
+InstQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
+{
+ OpClass op_class = ready_inst->opClass();
+
+ readyInsts.push(ready_inst);
+
+ DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
+ "the ready list, PC %#x opclass:%i [sn:%lli].\n",
+ ready_inst->readPC(), op_class, ready_inst->seqNum);
+}
+/*
+template <class Impl>
+void
+InstQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
+{
+ memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
+}
+
+template <class Impl>
+void
+InstQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
+{
+ memDepUnit[replay_inst->threadNumber].replay(replay_inst);
+}
+*/
+template <class Impl>
+void
+InstQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
+{
+ int tid = completed_inst->threadNumber;
+
+ DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
+ completed_inst->readPC(), completed_inst->seqNum);
+
+ ++freeEntries;
+
+// completed_inst->memOpDone = true;
+
+// memDepUnit[tid].completed(completed_inst);
+
+ count[tid]--;
+}
+/*
+template <class Impl>
+void
+InstQueue<Impl>::violation(DynInstPtr &store,
+ DynInstPtr &faulting_load)
+{
+ memDepUnit[store->threadNumber].violation(store, faulting_load);
+}
+*/
+template <class Impl>
+void
+InstQueue<Impl>::squash(unsigned tid)
+{
+ DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
+ "the IQ.\n", tid);
+
+ // Read instruction sequence number of last instruction out of the
+ // time buffer.
+// squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
+
+ // Setup the squash iterator to point to the tail.
+ squashIt[tid] = instList[tid].end();
+ --squashIt[tid];
+
+ // Call doSquash if there are insts in the IQ
+ if (count[tid] > 0) {
+ doSquash(tid);
+ }
+
+ // Also tell the memory dependence unit to squash.
+// memDepUnit[tid].squash(squashedSeqNum[tid], tid);
+}
+
+template <class Impl>
+void
+InstQueue<Impl>::doSquash(unsigned tid)
+{
+ // Make sure the squashed sequence number is valid.
+ assert(squashedSeqNum[tid] != 0);
+
+ DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
+ tid, squashedSeqNum[tid]);
+
+ // Squash any instructions younger than the squashed sequence number
+ // given.
+ while (squashIt[tid] != instList[tid].end() &&
+ (*squashIt[tid])->seqNum > squashedSeqNum[tid]) {
+
+ DynInstPtr squashed_inst = (*squashIt[tid]);
+
+ // Only handle the instruction if it actually is in the IQ and
+ // hasn't already been squashed in the IQ.
+ if (squashed_inst->threadNumber != tid ||
+ squashed_inst->isSquashedInIQ()) {
+ --squashIt[tid];
+ continue;
+ }
+
+ if (!squashed_inst->isIssued() ||
+ (squashed_inst->isMemRef()/* &&
+ !squashed_inst->memOpDone*/)) {
+
+ // Remove the instruction from the dependency list.
+ if (!squashed_inst->isNonSpeculative()) {
+/*
+ for (int src_reg_idx = 0;
+ src_reg_idx < squashed_inst->numSrcRegs();
+ src_reg_idx++)
+ {
+ PhysRegIndex src_reg =
+ squashed_inst->renamedSrcRegIdx(src_reg_idx);
+
+ // Only remove it from the dependency graph if it was
+ // placed there in the first place.
+ // HACK: This assumes that instructions woken up from the
+ // dependency chain aren't informed that a specific src
+ // register has become ready. This may not always be true
+ // in the future.
+ // Instead of doing a linked list traversal, we can just
+ // remove these squashed instructions either at issue time,
+ // or when the register is overwritten. The only downside
+ // to this is it leaves more room for error.
+
+ if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
+ src_reg < numPhysRegs) {
+ dependGraph[src_reg].remove(squashed_inst);
+ }
+
+
+ ++iqSquashedOperandsExamined;
+ }
+*/
+ // Might want to remove producers as well.
+ } else {
+ nonSpecInsts[squashed_inst->seqNum] = NULL;
+
+ nonSpecInsts.erase(squashed_inst->seqNum);
+
+ ++iqSquashedNonSpecRemoved;
+ }
+
+ // Might want to also clear out the head of the dependency graph.
+
+ // Mark it as squashed within the IQ.
+ squashed_inst->setSquashedInIQ();
+
+ // @todo: Remove this hack where several statuses are set so the
+ // inst will flow through the rest of the pipeline.
+ squashed_inst->setIssued();
+ squashed_inst->setCanCommit();
+// squashed_inst->removeInIQ();
+
+ //Update Thread IQ Count
+ count[squashed_inst->threadNumber]--;
+
+ ++freeEntries;
+
+ if (numThreads > 1) {
+ DPRINTF(IQ, "[tid:%i]: Instruction PC %#x squashed.\n",
+ tid, squashed_inst->readPC());
+ } else {
+ DPRINTF(IQ, "Instruction PC %#x squashed.\n",
+ squashed_inst->readPC());
+ }
+ }
+
+ --squashIt[tid];
+ ++iqSquashedInstsExamined;
+ }
+}
+/*
+template <class Impl>
+void
+InstQueue<Impl>::DependencyEntry::insert(DynInstPtr &new_inst)
+{
+ //Add this new, dependent instruction at the head of the dependency
+ //chain.
+
+ // First create the entry that will be added to the head of the
+ // dependency chain.
+ DependencyEntry *new_entry = new DependencyEntry;
+ new_entry->next = this->next;
+ new_entry->inst = new_inst;
+
+ // Then actually add it to the chain.
+ this->next = new_entry;
+
+ ++mem_alloc_counter;
+}
+
+template <class Impl>
+void
+InstQueue<Impl>::DependencyEntry::remove(DynInstPtr &inst_to_remove)
+{
+ DependencyEntry *prev = this;
+ DependencyEntry *curr = this->next;
+
+ // Make sure curr isn't NULL. Because this instruction is being
+ // removed from a dependency list, it must have been placed there at
+ // an earlier time. The dependency chain should not be empty,
+ // unless the instruction dependent upon it is already ready.
+ if (curr == NULL) {
+ return;
+ }
+
+ // Find the instruction to remove within the dependency linked list.
+ while (curr->inst != inst_to_remove) {
+ prev = curr;
+ curr = curr->next;
+
+ assert(curr != NULL);
+ }
+
+ // Now remove this instruction from the list.
+ prev->next = curr->next;
+
+ --mem_alloc_counter;
+
+ // Could push this off to the destructor of DependencyEntry
+ curr->inst = NULL;
+
+ delete curr;
+}
+
+template <class Impl>
+bool
+InstQueue<Impl>::addToDependents(DynInstPtr &new_inst)
+{
+ // Loop through the instruction's source registers, adding
+ // them to the dependency list if they are not ready.
+ int8_t total_src_regs = new_inst->numSrcRegs();
+ bool return_val = false;
+
+ for (int src_reg_idx = 0;
+ src_reg_idx < total_src_regs;
+ src_reg_idx++)
+ {
+ // Only add it to the dependency graph if it's not ready.
+ if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
+ PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
+
+ // Check the IQ's scoreboard to make sure the register
+ // hasn't become ready while the instruction was in flight
+ // between stages. Only if it really isn't ready should
+ // it be added to the dependency graph.
+ if (src_reg >= numPhysRegs) {
+ continue;
+ } else if (regScoreboard[src_reg] == false) {
+ DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
+ "is being added to the dependency chain.\n",
+ new_inst->readPC(), src_reg);
+
+ dependGraph[src_reg].insert(new_inst);
+
+ // Change the return value to indicate that something
+ // was added to the dependency graph.
+ return_val = true;
+ } else {
+ DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
+ "became ready before it reached the IQ.\n",
+ new_inst->readPC(), src_reg);
+ // Mark a register ready within the instruction.
+ new_inst->markSrcRegReady();
+ }
+ }
+ }
+
+ return return_val;
+}
+
+template <class Impl>
+void
+InstQueue<Impl>::createDependency(DynInstPtr &new_inst)
+{
+ //Actually nothing really needs to be marked when an
+ //instruction becomes the producer of a register's value,
+ //but for convenience a ptr to the producing instruction will
+ //be placed in the head node of the dependency links.
+ int8_t total_dest_regs = new_inst->numDestRegs();
+
+ for (int dest_reg_idx = 0;
+ dest_reg_idx < total_dest_regs;
+ dest_reg_idx++)
+ {
+ PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
+
+ // Instructions that use the misc regs will have a reg number
+ // higher than the normal physical registers. In this case these
+ // registers are not renamed, and there is no need to track
+ // dependencies as these instructions must be executed at commit.
+ if (dest_reg >= numPhysRegs) {
+ continue;
+ }
+
+ if (dependGraph[dest_reg].next) {
+ dumpDependGraph();
+ panic("Dependency graph %i not empty!", dest_reg);
+ }
+
+ dependGraph[dest_reg].inst = new_inst;
+
+ // Mark the scoreboard to say it's not yet ready.
+ regScoreboard[dest_reg] = false;
+ }
+}
+*/
+template <class Impl>
+void
+InstQueue<Impl>::addIfReady(DynInstPtr &inst)
+{
+ //If the instruction now has all of its source registers
+ // available, then add it to the list of ready instructions.
+ if (inst->readyToIssue()) {
+
+ //Add the instruction to the proper ready list.
+ if (inst->isMemRef()) {
+
+ DPRINTF(IQ, "Checking if memory instruction can issue.\n");
+
+ // Message to the mem dependence unit that this instruction has
+ // its registers ready.
+
+// memDepUnit[inst->threadNumber].regsReady(inst);
+
+ return;
+ }
+
+ OpClass op_class = inst->opClass();
+
+ DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
+ "the ready list, PC %#x opclass:%i [sn:%lli].\n",
+ inst->readPC(), op_class, inst->seqNum);
+
+ readyInsts.push(inst);
+ }
+}
+
+template <class Impl>
+int
+InstQueue<Impl>::countInsts()
+{
+ //ksewell:This works but definitely could use a cleaner write
+ //with a more intuitive way of counting. Right now it's
+ //just brute force ....
+
+#if 0
+ int total_insts = 0;
+
+ for (int i = 0; i < numThreads; ++i) {
+ ListIt count_it = instList[i].begin();
+
+ while (count_it != instList[i].end()) {
+ if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
+ if (!(*count_it)->isIssued()) {
+ ++total_insts;
+ } else if ((*count_it)->isMemRef() &&
+ !(*count_it)->memOpDone) {
+ // Loads that have not been marked as executed still count
+ // towards the total instructions.
+ ++total_insts;
+ }
+ }
+
+ ++count_it;
+ }
+ }
+
+ return total_insts;
+#else
+ return numEntries - freeEntries;
+#endif
+}
+/*
+template <class Impl>
+void
+InstQueue<Impl>::dumpDependGraph()
+{
+ DependencyEntry *curr;
+
+ for (int i = 0; i < numPhysRegs; ++i)
+ {
+ curr = &dependGraph[i];
+
+ if (curr->inst) {
+ cprintf("dependGraph[%i]: producer: %#x [sn:%lli] consumer: ",
+ i, curr->inst->readPC(), curr->inst->seqNum);
+ } else {
+ cprintf("dependGraph[%i]: No producer. consumer: ", i);
+ }
+
+ while (curr->next != NULL) {
+ curr = curr->next;
+
+ cprintf("%#x [sn:%lli] ",
+ curr->inst->readPC(), curr->inst->seqNum);
+ }
+
+ cprintf("\n");
+ }
+}
+*/
+template <class Impl>
+void
+InstQueue<Impl>::dumpLists()
+{
+ for (int i = 0; i < Num_OpClasses; ++i) {
+ cprintf("Ready list %i size: %i\n", i, readyInsts.size());
+
+ cprintf("\n");
+ }
+
+ cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
+
+ NonSpecMapIt non_spec_it = nonSpecInsts.begin();
+ NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
+
+ cprintf("Non speculative list: ");
+
+ while (non_spec_it != non_spec_end_it) {
+ cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(),
+ (*non_spec_it).second->seqNum);
+ ++non_spec_it;
+ }
+
+ cprintf("\n");
+/*
+ ListOrderIt list_order_it = listOrder.begin();
+ ListOrderIt list_order_end_it = listOrder.end();
+ int i = 1;
+
+ cprintf("List order: ");
+
+ while (list_order_it != list_order_end_it) {
+ cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
+ (*list_order_it).oldestInst);
+
+ ++list_order_it;
+ ++i;
+ }
+*/
+ cprintf("\n");
+}
+
+
+template <class Impl>
+void
+InstQueue<Impl>::dumpInsts()
+{
+ for (int i = 0; i < numThreads; ++i) {
+// int num = 0;
+// int valid_num = 0;
+/*
+ ListIt inst_list_it = instList[i].begin();
+
+ while (inst_list_it != instList[i].end())
+ {
+ cprintf("Instruction:%i\n",
+ num);
+ if (!(*inst_list_it)->isSquashed()) {
+ if (!(*inst_list_it)->isIssued()) {
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ } else if ((*inst_list_it)->isMemRef() &&
+ !(*inst_list_it)->memOpDone) {
+ // Loads that have not been marked as executed still count
+ // towards the total instructions.
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ }
+ }
+
+ cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
+ "Issued:%i\nSquashed:%i\n",
+ (*inst_list_it)->readPC(),
+ (*inst_list_it)->seqNum,
+ (*inst_list_it)->threadNumber,
+ (*inst_list_it)->isIssued(),
+ (*inst_list_it)->isSquashed());
+
+ if ((*inst_list_it)->isMemRef()) {
+ cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
+ }
+
+ cprintf("\n");
+
+ inst_list_it++;
+ ++num;
+ }
+*/
+ }
+}
diff --git a/cpu/ozone/lsq_unit.cc b/cpu/ozone/lsq_unit.cc
new file mode 100644
index 000000000..3ac51b87d
--- /dev/null
+++ b/cpu/ozone/lsq_unit.cc
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu/ozone/ozone_impl.hh"
+#include "cpu/ozone/lsq_unit_impl.hh"
+
+// Force the instantiation of LDSTQ for all the implementations we care about.
+template class OzoneLSQ<OzoneImpl>;
+
diff --git a/cpu/ozone/lsq_unit.hh b/cpu/ozone/lsq_unit.hh
new file mode 100644
index 000000000..4b600af67
--- /dev/null
+++ b/cpu/ozone/lsq_unit.hh
@@ -0,0 +1,637 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_OZONE_LSQ_UNIT_HH__
+#define __CPU_OZONE_LSQ_UNIT_HH__
+
+#include <map>
+#include <queue>
+#include <algorithm>
+
+#include "arch/faults.hh"
+#include "arch/isa_traits.hh"
+#include "config/full_system.hh"
+#include "base/hashmap.hh"
+#include "cpu/inst_seq.hh"
+#include "mem/mem_interface.hh"
+//#include "mem/page_table.hh"
+#include "sim/sim_object.hh"
+
+class PageTable;
+
+/**
+ * Class that implements the actual LQ and SQ for each specific thread.
+ * Both are circular queues; load entries are freed upon committing, while
+ * store entries are freed once they writeback. The LSQUnit tracks if there
+ * are memory ordering violations, and also detects partial load to store
+ * forwarding cases (a store only has part of a load's data) that requires
+ * the load to wait until the store writes back. In the former case it
+ * holds onto the instruction until the dependence unit looks at it, and
+ * in the latter it stalls the LSQ until the store writes back. At that
+ * point the load is replayed.
+ */
+template <class Impl>
+class OzoneLSQ {
+ public:
+ typedef typename Impl::Params Params;
+ typedef typename Impl::FullCPU FullCPU;
+ typedef typename Impl::BackEnd BackEnd;
+ typedef typename Impl::DynInstPtr DynInstPtr;
+ typedef typename Impl::IssueStruct IssueStruct;
+
+ typedef TheISA::IntReg IntReg;
+
+ typedef typename std::map<InstSeqNum, DynInstPtr>::iterator LdMapIt;
+
+ private:
+ class StoreCompletionEvent : public Event {
+ public:
+ /** Constructs a store completion event. */
+ StoreCompletionEvent(int store_idx, Event *wb_event, OzoneLSQ *lsq_ptr);
+
+ /** Processes the store completion event. */
+ void process();
+
+ /** Returns the description of this event. */
+ const char *description();
+
+ private:
+ /** The store index of the store being written back. */
+ int storeIdx;
+ /** The writeback event for the store. Needed for store
+ * conditionals.
+ */
+ Event *wbEvent;
+ /** The pointer to the LSQ unit that issued the store. */
+ OzoneLSQ<Impl> *lsqPtr;
+ };
+
+ friend class StoreCompletionEvent;
+
+ public:
+ /** Constructs an LSQ unit. init() must be called prior to use. */
+ OzoneLSQ();
+
+ /** Initializes the LSQ unit with the specified number of entries. */
+ void init(Params *params, unsigned maxLQEntries,
+ unsigned maxSQEntries, unsigned id);
+
+ /** Returns the name of the LSQ unit. */
+ std::string name() const;
+
+ /** Sets the CPU pointer. */
+ void setCPU(FullCPU *cpu_ptr)
+ { cpu = cpu_ptr; }
+
+ /** Sets the back-end stage pointer. */
+ void setBE(BackEnd *be_ptr)
+ { be = be_ptr; }
+
+ /** Sets the page table pointer. */
+ void setPageTable(PageTable *pt_ptr);
+
+ /** Ticks the LSQ unit, which in this case only resets the number of
+ * used cache ports.
+ * @todo: Move the number of used ports up to the LSQ level so it can
+ * be shared by all LSQ units.
+ */
+ void tick() { usedPorts = 0; }
+
+ /** Inserts an instruction. */
+ void insert(DynInstPtr &inst);
+ /** Inserts a load instruction. */
+ void insertLoad(DynInstPtr &load_inst);
+ /** Inserts a store instruction. */
+ void insertStore(DynInstPtr &store_inst);
+
+ /** Executes a load instruction. */
+ Fault executeLoad(DynInstPtr &inst);
+
+ Fault executeLoad(int lq_idx);
+ /** Executes a store instruction. */
+ Fault executeStore(DynInstPtr &inst);
+
+ /** Commits the head load. */
+ void commitLoad();
+ /** Commits a specific load, given by the sequence number. */
+ void commitLoad(InstSeqNum &inst);
+ /** Commits loads older than a specific sequence number. */
+ void commitLoads(InstSeqNum &youngest_inst);
+
+ /** Commits stores older than a specific sequence number. */
+ void commitStores(InstSeqNum &youngest_inst);
+
+ /** Writes back stores. */
+ void writebackStores();
+
+ // @todo: Include stats in the LSQ unit.
+ //void regStats();
+
+ /** Clears all the entries in the LQ. */
+ void clearLQ();
+
+ /** Clears all the entries in the SQ. */
+ void clearSQ();
+
+ /** Resizes the LQ to a given size. */
+ void resizeLQ(unsigned size);
+
+ /** Resizes the SQ to a given size. */
+ void resizeSQ(unsigned size);
+
+ /** Squashes all instructions younger than a specific sequence number. */
+ void squash(const InstSeqNum &squashed_num);
+
+ /** Returns if there is a memory ordering violation. Value is reset upon
+ * call to getMemDepViolator().
+ */
+ bool violation() { return memDepViolator; }
+
+ /** Returns the memory ordering violator. */
+ DynInstPtr getMemDepViolator();
+
+ /** Returns if a load became blocked due to the memory system. It clears
+ * the bool's value upon this being called.
+ */
+ inline bool loadBlocked();
+
+ /** Returns the number of free entries (min of free LQ and SQ entries). */
+ unsigned numFreeEntries();
+
+ /** Returns the number of loads ready to execute. */
+ int numLoadsReady();
+
+ /** Returns the number of loads in the LQ. */
+ int numLoads() { return loads; }
+
+ /** Returns the number of stores in the SQ. */
+ int numStores() { return stores; }
+
+ /** Returns if either the LQ or SQ is full. */
+ bool isFull() { return lqFull() || sqFull(); }
+
+ /** Returns if the LQ is full. */
+ bool lqFull() { return loads >= (LQEntries - 1); }
+
+ /** Returns if the SQ is full. */
+ bool sqFull() { return stores >= (SQEntries - 1); }
+
+ /** Debugging function to dump instructions in the LSQ. */
+ void dumpInsts();
+
+ /** Returns the number of instructions in the LSQ. */
+ unsigned getCount() { return loads + stores; }
+
+ /** Returns if there are any stores to writeback. */
+ bool hasStoresToWB() { return storesToWB; }
+
+ /** Returns the number of stores to writeback. */
+ int numStoresToWB() { return storesToWB; }
+
+ /** Returns if the LSQ unit will writeback on this cycle. */
+ bool willWB() { return storeQueue[storeWBIdx].canWB &&
+ !storeQueue[storeWBIdx].completed &&
+ !dcacheInterface->isBlocked(); }
+
+ private:
+ /** Completes the store at the specified index. */
+ void completeStore(int store_idx);
+
+ /** Increments the given store index (circular queue). */
+ inline void incrStIdx(int &store_idx);
+ /** Decrements the given store index (circular queue). */
+ inline void decrStIdx(int &store_idx);
+ /** Increments the given load index (circular queue). */
+ inline void incrLdIdx(int &load_idx);
+ /** Decrements the given load index (circular queue). */
+ inline void decrLdIdx(int &load_idx);
+
+ private:
+ /** Pointer to the CPU. */
+ FullCPU *cpu;
+
+ /** Pointer to the back-end stage. */
+ BackEnd *be;
+
+ /** Pointer to the D-cache. */
+ MemInterface *dcacheInterface;
+
+ /** Pointer to the page table. */
+ PageTable *pTable;
+
+ public:
+ struct SQEntry {
+ /** Constructs an empty store queue entry. */
+ SQEntry()
+ : inst(NULL), req(NULL), size(0), data(0),
+ canWB(0), committed(0), completed(0)
+ { }
+
+ /** Constructs a store queue entry for a given instruction. */
+ SQEntry(DynInstPtr &_inst)
+ : inst(_inst), req(NULL), size(0), data(0),
+ canWB(0), committed(0), completed(0)
+ { }
+
+ /** The store instruction. */
+ DynInstPtr inst;
+ /** The memory request for the store. */
+ MemReqPtr req;
+ /** The size of the store. */
+ int size;
+ /** The store data. */
+ IntReg data;
+ /** Whether or not the store can writeback. */
+ bool canWB;
+ /** Whether or not the store is committed. */
+ bool committed;
+ /** Whether or not the store is completed. */
+ bool completed;
+ };
+
+ enum Status {
+ Running,
+ Idle,
+ DcacheMissStall,
+ DcacheMissSwitch
+ };
+
+ private:
+ /** The OzoneLSQ thread id. */
+ unsigned lsqID;
+
+ /** The status of the LSQ unit. */
+ Status _status;
+
+ /** The store queue. */
+ std::vector<SQEntry> storeQueue;
+
+ /** The load queue. */
+ std::vector<DynInstPtr> loadQueue;
+
+ // Consider making these 16 bits
+ /** The number of LQ entries. */
+ unsigned LQEntries;
+ /** The number of SQ entries. */
+ unsigned SQEntries;
+
+ /** The number of load instructions in the LQ. */
+ int loads;
+ /** The number of store instructions in the SQ (excludes those waiting to
+ * writeback).
+ */
+ int stores;
+ /** The number of store instructions in the SQ waiting to writeback. */
+ int storesToWB;
+
+ /** The index of the head instruction in the LQ. */
+ int loadHead;
+ /** The index of the tail instruction in the LQ. */
+ int loadTail;
+
+ /** The index of the head instruction in the SQ. */
+ int storeHead;
+ /** The index of the first instruction that is ready to be written back,
+ * and has not yet been written back.
+ */
+ int storeWBIdx;
+ /** The index of the tail instruction in the SQ. */
+ int storeTail;
+
+ /// @todo Consider moving to a more advanced model with write vs read ports
+ /** The number of cache ports available each cycle. */
+ int cachePorts;
+
+ /** The number of used cache ports in this cycle. */
+ int usedPorts;
+
+ //list<InstSeqNum> mshrSeqNums;
+
+ //Stats::Scalar<> dcacheStallCycles;
+ Counter lastDcacheStall;
+
+ /** Wire to read information from the issue stage time queue. */
+ typename TimeBuffer<IssueStruct>::wire fromIssue;
+
+ // Make these per thread?
+ /** Whether or not the LSQ is stalled. */
+ bool stalled;
+ /** The store that causes the stall due to partial store to load
+ * forwarding.
+ */
+ InstSeqNum stallingStoreIsn;
+ /** The index of the above store. */
+ int stallingLoadIdx;
+
+ /** Whether or not a load is blocked due to the memory system. It is
+ * cleared when this value is checked via loadBlocked().
+ */
+ bool isLoadBlocked;
+
+ /** The oldest faulting load instruction. */
+ DynInstPtr loadFaultInst;
+ /** The oldest faulting store instruction. */
+ DynInstPtr storeFaultInst;
+
+ /** The oldest load that caused a memory ordering violation. */
+ DynInstPtr memDepViolator;
+
+ // Will also need how many read/write ports the Dcache has. Or keep track
+ // of that in stage that is one level up, and only call executeLoad/Store
+ // the appropriate number of times.
+
+ public:
+ /** Executes the load at the given index. */
+ template <class T>
+ Fault read(MemReqPtr &req, T &data, int load_idx);
+
+ /** Executes the store at the given index. */
+ template <class T>
+ Fault write(MemReqPtr &req, T &data, int store_idx);
+
+ /** Returns the index of the head load instruction. */
+ int getLoadHead() { return loadHead; }
+ /** Returns the sequence number of the head load instruction. */
+ InstSeqNum getLoadHeadSeqNum()
+ {
+ if (loadQueue[loadHead]) {
+ return loadQueue[loadHead]->seqNum;
+ } else {
+ return 0;
+ }
+
+ }
+
+ /** Returns the index of the head store instruction. */
+ int getStoreHead() { return storeHead; }
+ /** Returns the sequence number of the head store instruction. */
+ InstSeqNum getStoreHeadSeqNum()
+ {
+ if (storeQueue[storeHead].inst) {
+ return storeQueue[storeHead].inst->seqNum;
+ } else {
+ return 0;
+ }
+
+ }
+
+ /** Returns whether or not the LSQ unit is stalled. */
+ bool isStalled() { return stalled; }
+};
+
+template <class Impl>
+template <class T>
+Fault
+OzoneLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx)
+{
+ //Depending on issue2execute delay a squashed load could
+ //execute if it is found to be squashed in the same
+ //cycle it is scheduled to execute
+ assert(loadQueue[load_idx]);
+
+ if (loadQueue[load_idx]->isExecuted()) {
+ panic("Should not reach this point with split ops!");
+
+ memcpy(&data,req->data,req->size);
+
+ return NoFault;
+ }
+
+ // Make sure this isn't an uncacheable access
+ // A bit of a hackish way to get uncached accesses to work only if they're
+ // at the head of the LSQ and are ready to commit (at the head of the ROB
+ // too).
+ // @todo: Fix uncached accesses.
+ if (req->flags & UNCACHEABLE &&
+ (load_idx != loadHead || !loadQueue[load_idx]->readyToCommit())) {
+
+ return TheISA::genMachineCheckFault();
+ }
+
+ // Check the SQ for any previous stores that might lead to forwarding
+ int store_idx = loadQueue[load_idx]->sqIdx;
+
+ int store_size = 0;
+
+ DPRINTF(OzoneLSQ, "Read called, load idx: %i, store idx: %i, "
+ "storeHead: %i addr: %#x\n",
+ load_idx, store_idx, storeHead, req->paddr);
+
+ while (store_idx != -1) {
+ // End once we've reached the top of the LSQ
+ if (store_idx == storeWBIdx) {
+ break;
+ }
+
+ // Move the index to one younger
+ if (--store_idx < 0)
+ store_idx += SQEntries;
+
+ assert(storeQueue[store_idx].inst);
+
+ store_size = storeQueue[store_idx].size;
+
+ if (store_size == 0)
+ continue;
+
+ // Check if the store data is within the lower and upper bounds of
+ // addresses that the request needs.
+ bool store_has_lower_limit =
+ req->vaddr >= storeQueue[store_idx].inst->effAddr;
+ bool store_has_upper_limit =
+ (req->vaddr + req->size) <= (storeQueue[store_idx].inst->effAddr +
+ store_size);
+ bool lower_load_has_store_part =
+ req->vaddr < (storeQueue[store_idx].inst->effAddr +
+ store_size);
+ bool upper_load_has_store_part =
+ (req->vaddr + req->size) > storeQueue[store_idx].inst->effAddr;
+
+ // If the store's data has all of the data needed, we can forward.
+ if (store_has_lower_limit && store_has_upper_limit) {
+
+ int shift_amt = req->vaddr & (store_size - 1);
+ // Assumes byte addressing
+ shift_amt = shift_amt << 3;
+
+ // Cast this to type T?
+ data = storeQueue[store_idx].data >> shift_amt;
+
+ req->cmd = Read;
+ assert(!req->completionEvent);
+ req->completionEvent = NULL;
+ req->time = curTick;
+ assert(!req->data);
+ req->data = new uint8_t[64];
+
+ memcpy(req->data, &data, req->size);
+
+ DPRINTF(OzoneLSQ, "Forwarding from store idx %i to load to "
+ "addr %#x, data %#x\n",
+ store_idx, req->vaddr, *(req->data));
+
+ typename BackEnd::LdWritebackEvent *wb =
+ new typename BackEnd::LdWritebackEvent(loadQueue[load_idx],
+ be);
+
+ // We'll say this has a 1 cycle load-store forwarding latency
+ // for now.
+ // FIXME - Need to make this a parameter.
+ wb->schedule(curTick);
+
+ // Should keep track of stat for forwarded data
+ return NoFault;
+ } else if ((store_has_lower_limit && lower_load_has_store_part) ||
+ (store_has_upper_limit && upper_load_has_store_part) ||
+ (lower_load_has_store_part && upper_load_has_store_part)) {
+ // This is the partial store-load forwarding case where a store
+ // has only part of the load's data.
+
+ // If it's already been written back, then don't worry about
+ // stalling on it.
+ if (storeQueue[store_idx].completed) {
+ continue;
+ }
+
+ // Must stall load and force it to retry, so long as it's the oldest
+ // load that needs to do so.
+ if (!stalled ||
+ (stalled &&
+ loadQueue[load_idx]->seqNum <
+ loadQueue[stallingLoadIdx]->seqNum)) {
+ stalled = true;
+ stallingStoreIsn = storeQueue[store_idx].inst->seqNum;
+ stallingLoadIdx = load_idx;
+ }
+
+ // Tell IQ/mem dep unit that this instruction will need to be
+ // rescheduled eventually
+ be->rescheduleMemInst(loadQueue[load_idx]);
+
+ DPRINTF(OzoneLSQ, "Load-store forwarding mis-match. "
+ "Store idx %i to load addr %#x\n",
+ store_idx, req->vaddr);
+
+ return NoFault;
+ }
+ }
+
+
+ // If there's no forwarding case, then go access memory
+ DynInstPtr inst = loadQueue[load_idx];
+
+ ++usedPorts;
+
+ // if we have a cache, do cache access too
+ if (dcacheInterface) {
+ if (dcacheInterface->isBlocked()) {
+ isLoadBlocked = true;
+ // No fault occurred, even though the interface is blocked.
+ return NoFault;
+ }
+
+ DPRINTF(OzoneLSQ, "D-cache: PC:%#x reading from paddr:%#x "
+ "vaddr:%#x flags:%i\n",
+ inst->readPC(), req->paddr, req->vaddr, req->flags);
+
+ // Setup MemReq pointer
+ req->cmd = Read;
+ req->completionEvent = NULL;
+ req->time = curTick;
+ assert(!req->data);
+ req->data = new uint8_t[64];
+
+ assert(!req->completionEvent);
+ typedef typename BackEnd::LdWritebackEvent LdWritebackEvent;
+
+ LdWritebackEvent *wb = new LdWritebackEvent(loadQueue[load_idx], be);
+
+ req->completionEvent = wb;
+
+ // Do Cache Access
+ MemAccessResult result = dcacheInterface->access(req);
+
+ // Ugly hack to get an event scheduled *only* if the access is
+ // a miss. We really should add first-class support for this
+ // at some point.
+ // @todo: Probably should support having no events
+ if (result != MA_HIT) {
+ DPRINTF(OzoneLSQ, "D-cache miss!\n");
+ DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
+ inst->seqNum);
+
+ lastDcacheStall = curTick;
+
+ _status = DcacheMissStall;
+
+ wb->setDcacheMiss();
+
+ } else {
+// DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n",
+// inst->seqNum);
+
+ DPRINTF(OzoneLSQ, "D-cache hit!\n");
+ }
+ } else {
+ fatal("Must use D-cache with new memory system");
+ }
+
+ return NoFault;
+}
+
+template <class Impl>
+template <class T>
+Fault
+OzoneLSQ<Impl>::write(MemReqPtr &req, T &data, int store_idx)
+{
+ assert(storeQueue[store_idx].inst);
+
+ DPRINTF(OzoneLSQ, "Doing write to store idx %i, addr %#x data %#x"
+ " | storeHead:%i [sn:%i]\n",
+ store_idx, req->paddr, data, storeHead,
+ storeQueue[store_idx].inst->seqNum);
+
+ storeQueue[store_idx].req = req;
+ storeQueue[store_idx].size = sizeof(T);
+ storeQueue[store_idx].data = data;
+
+ // This function only writes the data to the store queue, so no fault
+ // can happen here.
+ return NoFault;
+}
+
+template <class Impl>
+inline bool
+OzoneLSQ<Impl>::loadBlocked()
+{
+ bool ret_val = isLoadBlocked;
+ isLoadBlocked = false;
+ return ret_val;
+}
+
+#endif // __CPU_OZONE_LSQ_UNIT_HH__
diff --git a/cpu/ozone/lsq_unit_impl.hh b/cpu/ozone/lsq_unit_impl.hh
new file mode 100644
index 000000000..726348d76
--- /dev/null
+++ b/cpu/ozone/lsq_unit_impl.hh
@@ -0,0 +1,846 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/isa_traits.hh"
+#include "base/str.hh"
+#include "cpu/ozone/lsq_unit.hh"
+
+template <class Impl>
+OzoneLSQ<Impl>::StoreCompletionEvent::StoreCompletionEvent(int store_idx,
+ Event *wb_event,
+ OzoneLSQ<Impl> *lsq_ptr)
+ : Event(&mainEventQueue),
+ storeIdx(store_idx),
+ wbEvent(wb_event),
+ lsqPtr(lsq_ptr)
+{
+ this->setFlags(Event::AutoDelete);
+}
+
+template <class Impl>
+void
+OzoneLSQ<Impl>::StoreCompletionEvent::process()
+{
+ DPRINTF(OzoneLSQ, "Cache miss complete for store idx:%i\n", storeIdx);
+
+ //lsqPtr->removeMSHR(lsqPtr->storeQueue[storeIdx].inst->seqNum);
+
+// lsqPtr->cpu->wakeCPU();
+ if (wbEvent)
+ wbEvent->process();
+ lsqPtr->completeStore(storeIdx);
+}
+
+template <class Impl>
+const char *
+OzoneLSQ<Impl>::StoreCompletionEvent::description()
+{
+ return "LSQ store completion event";
+}
+
+template <class Impl>
+OzoneLSQ<Impl>::OzoneLSQ()
+ : loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false)
+{
+}
+
+template<class Impl>
+void
+OzoneLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
+ unsigned maxSQEntries, unsigned id)
+
+{
+ DPRINTF(OzoneLSQ, "Creating OzoneLSQ%i object.\n",id);
+
+ lsqID = id;
+
+ LQEntries = maxLQEntries;
+ SQEntries = maxSQEntries;
+
+ loadQueue.resize(LQEntries);
+ storeQueue.resize(SQEntries);
+
+
+ // May want to initialize these entries to NULL
+
+ loadHead = loadTail = 0;
+
+ storeHead = storeWBIdx = storeTail = 0;
+
+ usedPorts = 0;
+ cachePorts = params->cachePorts;
+
+ dcacheInterface = params->dcacheInterface;
+
+ loadFaultInst = storeFaultInst = memDepViolator = NULL;
+}
+
+template<class Impl>
+std::string
+OzoneLSQ<Impl>::name() const
+{
+ return "lsqunit";
+}
+
+template<class Impl>
+void
+OzoneLSQ<Impl>::clearLQ()
+{
+ loadQueue.clear();
+}
+
+template<class Impl>
+void
+OzoneLSQ<Impl>::clearSQ()
+{
+ storeQueue.clear();
+}
+
+template<class Impl>
+void
+OzoneLSQ<Impl>::setPageTable(PageTable *pt_ptr)
+{
+ DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
+ pTable = pt_ptr;
+}
+
+template<class Impl>
+void
+OzoneLSQ<Impl>::resizeLQ(unsigned size)
+{
+ assert( size >= LQEntries);
+
+ if (size > LQEntries) {
+ while (size > loadQueue.size()) {
+ DynInstPtr dummy;
+ loadQueue.push_back(dummy);
+ LQEntries++;
+ }
+ } else {
+ LQEntries = size;
+ }
+
+}
+
+template<class Impl>
+void
+OzoneLSQ<Impl>::resizeSQ(unsigned size)
+{
+ if (size > SQEntries) {
+ while (size > storeQueue.size()) {
+ SQEntry dummy;
+ storeQueue.push_back(dummy);
+ SQEntries++;
+ }
+ } else {
+ SQEntries = size;
+ }
+}
+
+template <class Impl>
+void
+OzoneLSQ<Impl>::insert(DynInstPtr &inst)
+{
+ // Make sure we really have a memory reference.
+ assert(inst->isMemRef());
+
+ // Make sure it's one of the two classes of memory references.
+ assert(inst->isLoad() || inst->isStore());
+
+ if (inst->isLoad()) {
+ insertLoad(inst);
+ } else {
+ insertStore(inst);
+ }
+
+// inst->setInLSQ();
+}
+
+template <class Impl>
+void
+OzoneLSQ<Impl>::insertLoad(DynInstPtr &load_inst)
+{
+ assert((loadTail + 1) % LQEntries != loadHead && loads < LQEntries);
+
+ DPRINTF(OzoneLSQ, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
+ load_inst->readPC(), loadTail, load_inst->seqNum);
+
+ load_inst->lqIdx = loadTail;
+
+ if (stores == 0) {
+ load_inst->sqIdx = -1;
+ } else {
+ load_inst->sqIdx = storeTail;
+ }
+
+ loadQueue[loadTail] = load_inst;
+
+ incrLdIdx(loadTail);
+
+ ++loads;
+}
+
+template <class Impl>
+void
+OzoneLSQ<Impl>::insertStore(DynInstPtr &store_inst)
+{
+ // Make sure it is not full before inserting an instruction.
+ assert((storeTail + 1) % SQEntries != storeHead);
+ assert(stores < SQEntries);
+
+ DPRINTF(OzoneLSQ, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
+ store_inst->readPC(), storeTail, store_inst->seqNum);
+
+ store_inst->sqIdx = storeTail;
+ store_inst->lqIdx = loadTail;
+
+ storeQueue[storeTail] = SQEntry(store_inst);
+
+ incrStIdx(storeTail);
+
+ ++stores;
+
+}
+
+template <class Impl>
+typename Impl::DynInstPtr
+OzoneLSQ<Impl>::getMemDepViolator()
+{
+ DynInstPtr temp = memDepViolator;
+
+ memDepViolator = NULL;
+
+ return temp;
+}
+
+template <class Impl>
+unsigned
+OzoneLSQ<Impl>::numFreeEntries()
+{
+ unsigned free_lq_entries = LQEntries - loads;
+ unsigned free_sq_entries = SQEntries - stores;
+
+ // Both the LQ and SQ entries have an extra dummy entry to differentiate
+ // empty/full conditions. Subtract 1 from the free entries.
+ if (free_lq_entries < free_sq_entries) {
+ return free_lq_entries - 1;
+ } else {
+ return free_sq_entries - 1;
+ }
+}
+
+template <class Impl>
+int
+OzoneLSQ<Impl>::numLoadsReady()
+{
+ int load_idx = loadHead;
+ int retval = 0;
+
+ while (load_idx != loadTail) {
+ assert(loadQueue[load_idx]);
+
+ if (loadQueue[load_idx]->readyToIssue()) {
+ ++retval;
+ }
+ }
+
+ return retval;
+}
+
+#if 0
+template <class Impl>
+Fault
+OzoneLSQ<Impl>::executeLoad()
+{
+ Fault load_fault = NoFault;
+ DynInstPtr load_inst;
+
+ assert(readyLoads.size() != 0);
+
+ // Execute a ready load.
+ LdMapIt ready_it = readyLoads.begin();
+
+ load_inst = (*ready_it).second;
+
+ // Execute the instruction, which is held in the data portion of the
+ // iterator.
+ load_fault = load_inst->execute();
+
+ // If it executed successfully, then switch it over to the executed
+ // loads list.
+ if (load_fault == NoFault) {
+ executedLoads[load_inst->seqNum] = load_inst;
+
+ readyLoads.erase(ready_it);
+ } else {
+ loadFaultInst = load_inst;
+ }
+
+ return load_fault;
+}
+#endif
+
+template <class Impl>
+Fault
+OzoneLSQ<Impl>::executeLoad(DynInstPtr &inst)
+{
+ // Execute a specific load.
+ Fault load_fault = NoFault;
+
+ DPRINTF(OzoneLSQ, "Executing load PC %#x, [sn:%lli]\n",
+ inst->readPC(),inst->seqNum);
+
+ // Make sure it's really in the list.
+ // Normally it should always be in the list. However,
+ /* due to a syscall it may not be the list.
+#ifdef DEBUG
+ int i = loadHead;
+ while (1) {
+ if (i == loadTail && !find(inst)) {
+ assert(0 && "Load not in the queue!");
+ } else if (loadQueue[i] == inst) {
+ break;
+ }
+
+ i = i + 1;
+ if (i >= LQEntries) {
+ i = 0;
+ }
+ }
+#endif // DEBUG*/
+
+ load_fault = inst->initiateAcc();
+
+ // Might want to make sure that I'm not overwriting a previously faulting
+ // instruction that hasn't been checked yet.
+ // Actually probably want the oldest faulting load
+ if (load_fault != NoFault) {
+ // Maybe just set it as can commit here, although that might cause
+ // some other problems with sending traps to the ROB too quickly.
+// iewStage->instToCommit(inst);
+// iewStage->activityThisCycle();
+ }
+
+ return load_fault;
+}
+
+template <class Impl>
+Fault
+OzoneLSQ<Impl>::executeLoad(int lq_idx)
+{
+ // Very hackish. Not sure the best way to check that this
+ // instruction is at the head of the ROB. I should have some sort
+ // of extra information here so that I'm not overloading the
+ // canCommit signal for 15 different things.
+ loadQueue[lq_idx]->setCanCommit();
+ Fault ret_fault = executeLoad(loadQueue[lq_idx]);
+ loadQueue[lq_idx]->clearCanCommit();
+ return ret_fault;
+}
+
+template <class Impl>
+Fault
+OzoneLSQ<Impl>::executeStore(DynInstPtr &store_inst)
+{
+ // Make sure that a store exists.
+ assert(stores != 0);
+
+ int store_idx = store_inst->sqIdx;
+
+ DPRINTF(OzoneLSQ, "Executing store PC %#x [sn:%lli]\n",
+ store_inst->readPC(), store_inst->seqNum);
+
+ // Check the recently completed loads to see if any match this store's
+ // address. If so, then we have a memory ordering violation.
+ int load_idx = store_inst->lqIdx;
+
+ Fault store_fault = store_inst->initiateAcc();
+
+ // Store size should now be available. Use it to get proper offset for
+ // addr comparisons.
+ int size = storeQueue[store_idx].size;
+
+ if (size == 0) {
+ DPRINTF(OzoneLSQ,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
+ store_inst->readPC(),store_inst->seqNum);
+
+ return store_fault;
+ }
+
+ assert(store_fault == NoFault);
+
+ if (!storeFaultInst) {
+ if (store_fault != NoFault) {
+ panic("Fault in a store instruction!");
+ storeFaultInst = store_inst;
+ } else if (store_inst->isNonSpeculative()) {
+ // Nonspeculative accesses (namely store conditionals)
+ // need to set themselves as able to writeback if we
+ // haven't had a fault by here.
+ storeQueue[store_idx].canWB = true;
+
+ ++storesToWB;
+ }
+ }
+
+ if (!memDepViolator) {
+ while (load_idx != loadTail) {
+ // Actually should only check loads that have actually executed
+ // Might be safe because effAddr is set to InvalAddr when the
+ // dyn inst is created.
+
+ // Must actually check all addrs in the proper size range
+ // Which is more correct than needs to be. What if for now we just
+ // assume all loads are quad-word loads, and do the addr based
+ // on that.
+ // @todo: Fix this, magic number being used here
+ if ((loadQueue[load_idx]->effAddr >> 8) ==
+ (store_inst->effAddr >> 8)) {
+ // A load incorrectly passed this store. Squash and refetch.
+ // For now return a fault to show that it was unsuccessful.
+ memDepViolator = loadQueue[load_idx];
+
+ return TheISA::genMachineCheckFault();
+ }
+
+ incrLdIdx(load_idx);
+ }
+
+ // If we've reached this point, there was no violation.
+ memDepViolator = NULL;
+ }
+
+ return store_fault;
+}
+
+template <class Impl>
+void
+OzoneLSQ<Impl>::commitLoad()
+{
+ assert(loadQueue[loadHead]);
+
+ DPRINTF(OzoneLSQ, "[sn:%lli] Committing head load instruction, PC %#x\n",
+ loadQueue[loadHead]->seqNum, loadQueue[loadHead]->readPC());
+
+
+ loadQueue[loadHead] = NULL;
+
+ incrLdIdx(loadHead);
+
+ --loads;
+}
+
+template <class Impl>
+void
+OzoneLSQ<Impl>::commitLoad(InstSeqNum &inst)
+{
+ // Hopefully I don't use this function too much
+ panic("Don't use this function!");
+
+ int i = loadHead;
+ while (1) {
+ if (i == loadTail) {
+ assert(0 && "Load not in the queue!");
+ } else if (loadQueue[i]->seqNum == inst) {
+ break;
+ }
+
+ ++i;
+ if (i >= LQEntries) {
+ i = 0;
+ }
+ }
+
+// loadQueue[i]->removeInLSQ();
+ loadQueue[i] = NULL;
+ --loads;
+}
+
+template <class Impl>
+void
+OzoneLSQ<Impl>::commitLoads(InstSeqNum &youngest_inst)
+{
+ assert(loads == 0 || loadQueue[loadHead]);
+
+ while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
+ commitLoad();
+ }
+}
+
+template <class Impl>
+void
+OzoneLSQ<Impl>::commitStores(InstSeqNum &youngest_inst)
+{
+ assert(stores == 0 || storeQueue[storeHead].inst);
+
+ int store_idx = storeHead;
+
+ while (store_idx != storeTail) {
+ assert(storeQueue[store_idx].inst);
+ if (!storeQueue[store_idx].canWB) {
+ if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
+ break;
+ }
+ DPRINTF(OzoneLSQ, "Marking store as able to write back, PC "
+ "%#x [sn:%lli]\n",
+ storeQueue[store_idx].inst->readPC(),
+ storeQueue[store_idx].inst->seqNum);
+
+ storeQueue[store_idx].canWB = true;
+
+// --stores;
+ ++storesToWB;
+ }
+
+ incrStIdx(store_idx);
+ }
+}
+
+template <class Impl>
+void
+OzoneLSQ<Impl>::writebackStores()
+{
+ while (storesToWB > 0 &&
+ storeWBIdx != storeTail &&
+ storeQueue[storeWBIdx].inst &&
+ storeQueue[storeWBIdx].canWB &&
+ usedPorts < cachePorts) {
+
+ if (storeQueue[storeWBIdx].size == 0) {
+ completeStore(storeWBIdx);
+
+ incrStIdx(storeWBIdx);
+
+ continue;
+ }
+
+ if (dcacheInterface && dcacheInterface->isBlocked()) {
+ DPRINTF(OzoneLSQ, "Unable to write back any more stores, cache"
+ " is blocked!\n");
+ break;
+ }
+
+ ++usedPorts;
+
+ if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
+ incrStIdx(storeWBIdx);
+
+ continue;
+ }
+
+ assert(storeQueue[storeWBIdx].req);
+ assert(!storeQueue[storeWBIdx].committed);
+
+ MemReqPtr req = storeQueue[storeWBIdx].req;
+ storeQueue[storeWBIdx].committed = true;
+
+// Fault fault = cpu->translateDataReadReq(req);
+ req->cmd = Write;
+ req->completionEvent = NULL;
+ req->time = curTick;
+ assert(!req->data);
+ req->data = new uint8_t[64];
+ memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size);
+
+ DPRINTF(OzoneLSQ, "D-Cache: Writing back store idx:%i PC:%#x "
+ "to Addr:%#x, data:%#x [sn:%lli]\n",
+ storeWBIdx,storeQueue[storeWBIdx].inst->readPC(),
+ req->paddr, *(req->data),
+ storeQueue[storeWBIdx].inst->seqNum);
+
+// if (fault != NoFault) {
+ //What should we do if there is a fault???
+ //for now panic
+// panic("Page Table Fault!!!!!\n");
+// }
+
+ if (dcacheInterface) {
+ MemAccessResult result = dcacheInterface->access(req);
+
+ //@todo temp fix for LL/SC (works fine for 1 CPU)
+ if (req->flags & LOCKED) {
+ req->result=1;
+ panic("LL/SC! oh no no support!!!");
+ }
+
+ if (isStalled() &&
+ storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
+ DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
+ "load idx:%i\n",
+ stallingStoreIsn, stallingLoadIdx);
+ stalled = false;
+ stallingStoreIsn = 0;
+ be->replayMemInst(loadQueue[stallingLoadIdx]);
+ }
+
+ if (result != MA_HIT && dcacheInterface->doEvents()) {
+ Event *wb = NULL;
+/*
+ typename IEW::LdWritebackEvent *wb = NULL;
+ if (req->flags & LOCKED) {
+ // Stx_C does not generate a system port transaction.
+ req->result=0;
+ wb = new typename IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
+ iewStage);
+ }
+*/
+ DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
+
+// DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
+// storeQueue[storeWBIdx].inst->seqNum);
+
+ // Will stores need their own kind of writeback events?
+ // Do stores even need writeback events?
+ assert(!req->completionEvent);
+ req->completionEvent = new
+ StoreCompletionEvent(storeWBIdx, wb, this);
+
+ lastDcacheStall = curTick;
+
+ _status = DcacheMissStall;
+
+ //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
+
+ //DPRINTF(OzoneLSQ, "Added MSHR. count = %i\n",mshrSeqNums.size());
+
+ // Increment stat here or something
+ } else {
+ DPRINTF(OzoneLSQ,"D-Cache: Write Hit on idx:%i !\n",
+ storeWBIdx);
+
+// DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
+// storeQueue[storeWBIdx].inst->seqNum);
+
+ if (req->flags & LOCKED) {
+ // Stx_C does not generate a system port transaction.
+ req->result=1;
+ typename BackEnd::LdWritebackEvent *wb =
+ new typename BackEnd::LdWritebackEvent(storeQueue[storeWBIdx].inst,
+ be);
+ wb->schedule(curTick);
+ }
+
+ completeStore(storeWBIdx);
+ }
+
+ incrStIdx(storeWBIdx);
+ } else {
+ panic("Must HAVE DCACHE!!!!!\n");
+ }
+ }
+
+ // Not sure this should set it to 0.
+ usedPorts = 0;
+
+ assert(stores >= 0 && storesToWB >= 0);
+}
+
+/*template <class Impl>
+void
+OzoneLSQ<Impl>::removeMSHR(InstSeqNum seqNum)
+{
+ list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
+ mshrSeqNums.end(),
+ seqNum);
+
+ if (mshr_it != mshrSeqNums.end()) {
+ mshrSeqNums.erase(mshr_it);
+ DPRINTF(OzoneLSQ, "Removing MSHR. count = %i\n",mshrSeqNums.size());
+ }
+}*/
+
+template <class Impl>
+void
+OzoneLSQ<Impl>::squash(const InstSeqNum &squashed_num)
+{
+ DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
+ "(Loads:%i Stores:%i)\n",squashed_num,loads,stores);
+
+ int load_idx = loadTail;
+ decrLdIdx(load_idx);
+
+ while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
+
+ // Clear the smart pointer to make sure it is decremented.
+ DPRINTF(OzoneLSQ,"Load Instruction PC %#x squashed, "
+ "[sn:%lli]\n",
+ loadQueue[load_idx]->readPC(),
+ loadQueue[load_idx]->seqNum);
+
+ if (isStalled() && load_idx == stallingLoadIdx) {
+ stalled = false;
+ stallingStoreIsn = 0;
+ stallingLoadIdx = 0;
+ }
+
+// loadQueue[load_idx]->squashed = true;
+ loadQueue[load_idx] = NULL;
+ --loads;
+
+ // Inefficient!
+ loadTail = load_idx;
+
+ decrLdIdx(load_idx);
+ }
+
+ int store_idx = storeTail;
+ decrStIdx(store_idx);
+
+ while (stores != 0 && storeQueue[store_idx].inst->seqNum > squashed_num) {
+
+ // Clear the smart pointer to make sure it is decremented.
+ DPRINTF(OzoneLSQ,"Store Instruction PC %#x squashed, "
+ "idx:%i [sn:%lli]\n",
+ storeQueue[store_idx].inst->readPC(),
+ store_idx, storeQueue[store_idx].inst->seqNum);
+
+ // I don't think this can happen. It should have been cleared by the
+ // stalling load.
+ if (isStalled() &&
+ storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
+ panic("Is stalled should have been cleared by stalling load!\n");
+ stalled = false;
+ stallingStoreIsn = 0;
+ }
+
+// storeQueue[store_idx].inst->squashed = true;
+ storeQueue[store_idx].inst = NULL;
+ storeQueue[store_idx].canWB = 0;
+
+ if (storeQueue[store_idx].req) {
+ assert(!storeQueue[store_idx].req->completionEvent);
+ }
+ storeQueue[store_idx].req = NULL;
+ --stores;
+
+ // Inefficient!
+ storeTail = store_idx;
+
+ decrStIdx(store_idx);
+ }
+}
+
+template <class Impl>
+void
+OzoneLSQ<Impl>::dumpInsts()
+{
+ cprintf("Load store queue: Dumping instructions.\n");
+ cprintf("Load queue size: %i\n", loads);
+ cprintf("Load queue: ");
+
+ int load_idx = loadHead;
+
+ while (load_idx != loadTail && loadQueue[load_idx]) {
+ cprintf("[sn:%lli] %#x ", loadQueue[load_idx]->seqNum,
+ loadQueue[load_idx]->readPC());
+
+ incrLdIdx(load_idx);
+ }
+
+ cprintf("\nStore queue size: %i\n", stores);
+ cprintf("Store queue: ");
+
+ int store_idx = storeHead;
+
+ while (store_idx != storeTail && storeQueue[store_idx].inst) {
+ cprintf("[sn:%lli] %#x ", storeQueue[store_idx].inst->seqNum,
+ storeQueue[store_idx].inst->readPC());
+
+ incrStIdx(store_idx);
+ }
+
+ cprintf("\n");
+}
+
+template <class Impl>
+void
+OzoneLSQ<Impl>::completeStore(int store_idx)
+{
+ assert(storeQueue[store_idx].inst);
+ storeQueue[store_idx].completed = true;
+ --storesToWB;
+ // A bit conservative because a store completion may not free up entries,
+ // but hopefully avoids two store completions in one cycle from making
+ // the CPU tick twice.
+// cpu->activityThisCycle();
+
+ if (store_idx == storeHead) {
+ do {
+ incrStIdx(storeHead);
+
+ --stores;
+ } while (storeQueue[storeHead].completed &&
+ storeHead != storeTail);
+
+// be->updateLSQNextCycle = true;
+ }
+
+ DPRINTF(OzoneLSQ, "Store head idx:%i\n", storeHead);
+
+ if (isStalled() &&
+ storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
+ DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
+ "load idx:%i\n",
+ stallingStoreIsn, stallingLoadIdx);
+ stalled = false;
+ stallingStoreIsn = 0;
+ be->replayMemInst(loadQueue[stallingLoadIdx]);
+ }
+}
+
+template <class Impl>
+inline void
+OzoneLSQ<Impl>::incrStIdx(int &store_idx)
+{
+ if (++store_idx >= SQEntries)
+ store_idx = 0;
+}
+
+template <class Impl>
+inline void
+OzoneLSQ<Impl>::decrStIdx(int &store_idx)
+{
+ if (--store_idx < 0)
+ store_idx += SQEntries;
+}
+
+template <class Impl>
+inline void
+OzoneLSQ<Impl>::incrLdIdx(int &load_idx)
+{
+ if (++load_idx >= LQEntries)
+ load_idx = 0;
+}
+
+template <class Impl>
+inline void
+OzoneLSQ<Impl>::decrLdIdx(int &load_idx)
+{
+ if (--load_idx < 0)
+ load_idx += LQEntries;
+}
diff --git a/cpu/ozone/lw_back_end.cc b/cpu/ozone/lw_back_end.cc
new file mode 100644
index 000000000..8e9a56ef5
--- /dev/null
+++ b/cpu/ozone/lw_back_end.cc
@@ -0,0 +1,5 @@
+
+#include "cpu/ozone/lw_back_end_impl.hh"
+#include "cpu/ozone/ozone_impl.hh"
+
+template class LWBackEnd<OzoneImpl>;
diff --git a/cpu/ozone/lw_back_end.hh b/cpu/ozone/lw_back_end.hh
new file mode 100644
index 000000000..1c03ffb73
--- /dev/null
+++ b/cpu/ozone/lw_back_end.hh
@@ -0,0 +1,473 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_OZONE_LW_BACK_END_HH__
+#define __CPU_OZONE_LW_BACK_END_HH__
+
+#include <list>
+#include <queue>
+#include <set>
+#include <string>
+
+#include "arch/faults.hh"
+#include "base/timebuf.hh"
+#include "cpu/inst_seq.hh"
+#include "cpu/ozone/rename_table.hh"
+#include "cpu/ozone/thread_state.hh"
+#include "mem/functional/functional.hh"
+#include "mem/mem_interface.hh"
+#include "mem/mem_req.hh"
+#include "sim/eventq.hh"
+
+template <class>
+class Checker;
+class ExecContext;
+
+template <class Impl>
+class OzoneThreadState;
+
+template <class Impl>
+class LWBackEnd
+{
+ public:
+ typedef OzoneThreadState<Impl> Thread;
+
+ typedef typename Impl::Params Params;
+ typedef typename Impl::DynInst DynInst;
+ typedef typename Impl::DynInstPtr DynInstPtr;
+ typedef typename Impl::FullCPU FullCPU;
+ typedef typename Impl::FrontEnd FrontEnd;
+ typedef typename Impl::FullCPU::CommStruct CommStruct;
+
+ struct SizeStruct {
+ int size;
+ };
+
+ typedef SizeStruct DispatchToIssue;
+ typedef SizeStruct IssueToExec;
+ typedef SizeStruct ExecToCommit;
+ typedef SizeStruct Writeback;
+
+ TimeBuffer<DispatchToIssue> d2i;
+ typename TimeBuffer<DispatchToIssue>::wire instsToDispatch;
+ TimeBuffer<IssueToExec> i2e;
+ typename TimeBuffer<IssueToExec>::wire instsToExecute;
+ TimeBuffer<ExecToCommit> e2c;
+ TimeBuffer<Writeback> numInstsToWB;
+
+ TimeBuffer<CommStruct> *comm;
+ typename TimeBuffer<CommStruct>::wire toIEW;
+ typename TimeBuffer<CommStruct>::wire fromCommit;
+
+ class TrapEvent : public Event {
+ private:
+ LWBackEnd<Impl> *be;
+
+ public:
+ TrapEvent(LWBackEnd<Impl> *_be);
+
+ void process();
+ const char *description();
+ };
+
+ /** LdWriteback event for a load completion. */
+ class LdWritebackEvent : public Event {
+ private:
+ /** Instruction that is writing back data to the register file. */
+ DynInstPtr inst;
+ /** Pointer to IEW stage. */
+ LWBackEnd *be;
+
+ bool dcacheMiss;
+
+ public:
+ /** Constructs a load writeback event. */
+ LdWritebackEvent(DynInstPtr &_inst, LWBackEnd *be);
+
+ /** Processes writeback event. */
+ virtual void process();
+ /** Returns the description of the writeback event. */
+ virtual const char *description();
+
+ void setDcacheMiss() { dcacheMiss = true; be->addDcacheMiss(inst); }
+ };
+
+ LWBackEnd(Params *params);
+
+ std::string name() const;
+
+ void regStats();
+
+ void setCPU(FullCPU *cpu_ptr);
+
+ void setFrontEnd(FrontEnd *front_end_ptr)
+ { frontEnd = front_end_ptr; }
+
+ void setXC(ExecContext *xc_ptr)
+ { xc = xc_ptr; }
+
+ void setThreadState(Thread *thread_ptr)
+ { thread = thread_ptr; }
+
+ void setCommBuffer(TimeBuffer<CommStruct> *_comm);
+
+ void tick();
+ void squash();
+ void generateXCEvent() { xcSquash = true; }
+ void squashFromXC();
+ void squashFromTrap();
+ void checkInterrupts();
+ bool trapSquash;
+ bool xcSquash;
+
+ template <class T>
+ Fault read(MemReqPtr &req, T &data, int load_idx);
+
+ template <class T>
+ Fault write(MemReqPtr &req, T &data, int store_idx);
+
+ Addr readCommitPC() { return commitPC; }
+
+ Addr commitPC;
+
+ Tick lastCommitCycle;
+
+ bool robEmpty() { return instList.empty(); }
+
+ bool isFull() { return numInsts >= numROBEntries; }
+ bool isBlocked() { return status == Blocked || dispatchStatus == Blocked; }
+
+ void fetchFault(Fault &fault);
+
+ int wakeDependents(DynInstPtr &inst, bool memory_deps = false);
+
+ /** Tells memory dependence unit that a memory instruction needs to be
+ * rescheduled. It will re-execute once replayMemInst() is called.
+ */
+ void rescheduleMemInst(DynInstPtr &inst);
+
+ /** Re-executes all rescheduled memory instructions. */
+ void replayMemInst(DynInstPtr &inst);
+
+ /** Completes memory instruction. */
+ void completeMemInst(DynInstPtr &inst) { }
+
+ void addDcacheMiss(DynInstPtr &inst)
+ {
+ waitingMemOps.insert(inst->seqNum);
+ numWaitingMemOps++;
+ DPRINTF(BE, "Adding a Dcache miss mem op [sn:%lli], total %i\n",
+ inst->seqNum, numWaitingMemOps);
+ }
+
+ void removeDcacheMiss(DynInstPtr &inst)
+ {
+ assert(waitingMemOps.find(inst->seqNum) != waitingMemOps.end());
+ waitingMemOps.erase(inst->seqNum);
+ numWaitingMemOps--;
+ DPRINTF(BE, "Removing a Dcache miss mem op [sn:%lli], total %i\n",
+ inst->seqNum, numWaitingMemOps);
+ }
+
+ void addWaitingMemOp(DynInstPtr &inst)
+ {
+ waitingMemOps.insert(inst->seqNum);
+ numWaitingMemOps++;
+ DPRINTF(BE, "Adding a waiting mem op [sn:%lli], total %i\n",
+ inst->seqNum, numWaitingMemOps);
+ }
+
+ void removeWaitingMemOp(DynInstPtr &inst)
+ {
+ assert(waitingMemOps.find(inst->seqNum) != waitingMemOps.end());
+ waitingMemOps.erase(inst->seqNum);
+ numWaitingMemOps--;
+ DPRINTF(BE, "Removing a waiting mem op [sn:%lli], total %i\n",
+ inst->seqNum, numWaitingMemOps);
+ }
+
+ void instToCommit(DynInstPtr &inst);
+
+ void switchOut();
+ void doSwitchOut();
+ void takeOverFrom(ExecContext *old_xc = NULL);
+
+ bool isSwitchedOut() { return switchedOut; }
+
+ private:
+ void generateTrapEvent(Tick latency = 0);
+ void handleFault(Fault &fault, Tick latency = 0);
+ void updateStructures();
+ void dispatchInsts();
+ void dispatchStall();
+ void checkDispatchStatus();
+ void executeInsts();
+ void commitInsts();
+ void addToLSQ(DynInstPtr &inst);
+ void writebackInsts();
+ bool commitInst(int inst_num);
+ void squash(const InstSeqNum &sn);
+ void squashDueToBranch(DynInstPtr &inst);
+ void squashDueToMemViolation(DynInstPtr &inst);
+ void squashDueToMemBlocked(DynInstPtr &inst);
+ void updateExeInstStats(DynInstPtr &inst);
+ void updateComInstStats(DynInstPtr &inst);
+
+ public:
+ FullCPU *cpu;
+
+ FrontEnd *frontEnd;
+
+ ExecContext *xc;
+
+ Thread *thread;
+
+ enum Status {
+ Running,
+ Idle,
+ DcacheMissStall,
+ DcacheMissComplete,
+ Blocked,
+ TrapPending
+ };
+
+ Status status;
+
+ Status dispatchStatus;
+
+ Status commitStatus;
+
+ Counter funcExeInst;
+
+ private:
+ typedef typename Impl::LdstQueue LdstQueue;
+
+ LdstQueue LSQ;
+ public:
+ RenameTable<Impl> commitRenameTable;
+
+ RenameTable<Impl> renameTable;
+ private:
+ class DCacheCompletionEvent : public Event
+ {
+ private:
+ LWBackEnd *be;
+
+ public:
+ DCacheCompletionEvent(LWBackEnd *_be);
+
+ virtual void process();
+ virtual const char *description();
+ };
+
+ friend class DCacheCompletionEvent;
+
+ DCacheCompletionEvent cacheCompletionEvent;
+
+ MemInterface *dcacheInterface;
+
+ MemReqPtr memReq;
+
+ // General back end width. Used if the more specific isn't given.
+ int width;
+
+ // Dispatch width.
+ int dispatchWidth;
+ int numDispatchEntries;
+ int dispatchSize;
+
+ int waitingInsts;
+
+ int issueWidth;
+
+ // Writeback width
+ int wbWidth;
+
+ // Commit width
+ int commitWidth;
+
+ /** Index into queue of instructions being written back. */
+ unsigned wbNumInst;
+
+ /** Cycle number within the queue of instructions being written
+ * back. Used in case there are too many instructions writing
+ * back at the current cycle and writesbacks need to be scheduled
+ * for the future. See comments in instToCommit().
+ */
+ unsigned wbCycle;
+
+ int numROBEntries;
+ int numInsts;
+
+ std::set<InstSeqNum> waitingMemOps;
+ typedef std::set<InstSeqNum>::iterator MemIt;
+ int numWaitingMemOps;
+ unsigned maxOutstandingMemOps;
+
+ bool squashPending;
+ InstSeqNum squashSeqNum;
+ Addr squashNextPC;
+
+ Fault faultFromFetch;
+ bool fetchHasFault;
+
+ bool switchedOut;
+ bool switchPending;
+
+ DynInstPtr memBarrier;
+
+ private:
+ struct pqCompare {
+ bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
+ {
+ return lhs->seqNum > rhs->seqNum;
+ }
+ };
+
+ typedef typename std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare> ReadyInstQueue;
+ ReadyInstQueue exeList;
+
+ typedef typename std::list<DynInstPtr>::iterator InstListIt;
+
+ std::list<DynInstPtr> instList;
+ std::list<DynInstPtr> waitingList;
+ std::list<DynInstPtr> replayList;
+ std::list<DynInstPtr> writeback;
+
+ int latency;
+
+ int squashLatency;
+
+ bool exactFullStall;
+
+ // number of cycles stalled for D-cache misses
+/* Stats::Scalar<> dcacheStallCycles;
+ Counter lastDcacheStall;
+*/
+ Stats::Vector<> rob_cap_events;
+ Stats::Vector<> rob_cap_inst_count;
+ Stats::Vector<> iq_cap_events;
+ Stats::Vector<> iq_cap_inst_count;
+ // total number of instructions executed
+ Stats::Vector<> exe_inst;
+ Stats::Vector<> exe_swp;
+ Stats::Vector<> exe_nop;
+ Stats::Vector<> exe_refs;
+ Stats::Vector<> exe_loads;
+ Stats::Vector<> exe_branches;
+
+ Stats::Vector<> issued_ops;
+
+ // total number of loads forwaded from LSQ stores
+ Stats::Vector<> lsq_forw_loads;
+
+ // total number of loads ignored due to invalid addresses
+ Stats::Vector<> inv_addr_loads;
+
+ // total number of software prefetches ignored due to invalid addresses
+ Stats::Vector<> inv_addr_swpfs;
+ // ready loads blocked due to memory disambiguation
+ Stats::Vector<> lsq_blocked_loads;
+
+ Stats::Scalar<> lsqInversion;
+
+ Stats::Vector<> n_issued_dist;
+ Stats::VectorDistribution<> issue_delay_dist;
+
+ Stats::VectorDistribution<> queue_res_dist;
+/*
+ Stats::Vector<> stat_fu_busy;
+ Stats::Vector2d<> stat_fuBusy;
+ Stats::Vector<> dist_unissued;
+ Stats::Vector2d<> stat_issued_inst_type;
+
+ Stats::Formula misspec_cnt;
+ Stats::Formula misspec_ipc;
+ Stats::Formula issue_rate;
+ Stats::Formula issue_stores;
+ Stats::Formula issue_op_rate;
+ Stats::Formula fu_busy_rate;
+ Stats::Formula commit_stores;
+ Stats::Formula commit_ipc;
+ Stats::Formula commit_ipb;
+ Stats::Formula lsq_inv_rate;
+*/
+ Stats::Vector<> writeback_count;
+ Stats::Vector<> producer_inst;
+ Stats::Vector<> consumer_inst;
+ Stats::Vector<> wb_penalized;
+
+ Stats::Formula wb_rate;
+ Stats::Formula wb_fanout;
+ Stats::Formula wb_penalized_rate;
+
+ // total number of instructions committed
+ Stats::Vector<> stat_com_inst;
+ Stats::Vector<> stat_com_swp;
+ Stats::Vector<> stat_com_refs;
+ Stats::Vector<> stat_com_loads;
+ Stats::Vector<> stat_com_membars;
+ Stats::Vector<> stat_com_branches;
+
+ Stats::Distribution<> n_committed_dist;
+
+ Stats::Scalar<> commit_eligible_samples;
+ Stats::Vector<> commit_eligible;
+
+ Stats::Vector<> squashedInsts;
+ Stats::Vector<> ROBSquashedInsts;
+
+ Stats::Scalar<> ROB_fcount;
+ Stats::Formula ROB_full_rate;
+
+ Stats::Vector<> ROB_count; // cumulative ROB occupancy
+ Stats::Formula ROB_occ_rate;
+ Stats::VectorDistribution<> ROB_occ_dist;
+ public:
+ void dumpInsts();
+
+ Checker<DynInstPtr> *checker;
+};
+
+template <class Impl>
+template <class T>
+Fault
+LWBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
+{
+ return LSQ.read(req, data, load_idx);
+}
+
+template <class Impl>
+template <class T>
+Fault
+LWBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
+{
+ return LSQ.write(req, data, store_idx);
+}
+
+#endif // __CPU_OZONE_LW_BACK_END_HH__
diff --git a/cpu/ozone/lw_back_end_impl.hh b/cpu/ozone/lw_back_end_impl.hh
new file mode 100644
index 000000000..41b4ea24b
--- /dev/null
+++ b/cpu/ozone/lw_back_end_impl.hh
@@ -0,0 +1,1693 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu/checker/cpu.hh"
+#include "cpu/ozone/lw_back_end.hh"
+#include "encumbered/cpu/full/op_class.hh"
+
+template <class Impl>
+void
+LWBackEnd<Impl>::generateTrapEvent(Tick latency)
+{
+ DPRINTF(BE, "Generating trap event\n");
+
+ TrapEvent *trap = new TrapEvent(this);
+
+ trap->schedule(curTick + cpu->cycles(latency));
+
+ thread->trapPending = true;
+}
+
+template <class Impl>
+int
+LWBackEnd<Impl>::wakeDependents(DynInstPtr &inst, bool memory_deps)
+{
+ assert(!inst->isSquashed());
+ std::vector<DynInstPtr> &dependents = memory_deps ? inst->getMemDeps() :
+ inst->getDependents();
+ int num_outputs = dependents.size();
+
+ DPRINTF(BE, "Waking instruction [sn:%lli] dependents in IQ\n", inst->seqNum);
+
+ for (int i = 0; i < num_outputs; i++) {
+ DynInstPtr dep_inst = dependents[i];
+ if (!memory_deps) {
+ dep_inst->markSrcRegReady();
+ } else {
+ if (!dep_inst->isSquashed())
+ dep_inst->markMemInstReady(inst.get());
+ }
+
+ DPRINTF(BE, "Marking source reg ready [sn:%lli] in IQ\n", dep_inst->seqNum);
+
+ if (dep_inst->readyToIssue() && dep_inst->isInROB() &&
+ !dep_inst->isNonSpeculative() && !dep_inst->isStoreConditional() &&
+ dep_inst->memDepReady() && !dep_inst->isMemBarrier() &&
+ !dep_inst->isWriteBarrier()) {
+ DPRINTF(BE, "Adding instruction to exeList [sn:%lli]\n",
+ dep_inst->seqNum);
+ exeList.push(dep_inst);
+ if (dep_inst->iqItValid) {
+ DPRINTF(BE, "Removing instruction from waiting list\n");
+ waitingList.erase(dep_inst->iqIt);
+ waitingInsts--;
+ dep_inst->iqItValid = false;
+ assert(waitingInsts >= 0);
+ }
+ if (dep_inst->isMemRef()) {
+ removeWaitingMemOp(dep_inst);
+ DPRINTF(BE, "Issued a waiting mem op [sn:%lli]\n",
+ dep_inst->seqNum);
+ }
+ }
+ }
+ return num_outputs;
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::rescheduleMemInst(DynInstPtr &inst)
+{
+ replayList.push_front(inst);
+}
+
+template <class Impl>
+LWBackEnd<Impl>::TrapEvent::TrapEvent(LWBackEnd<Impl> *_be)
+ : Event(&mainEventQueue, CPU_Tick_Pri), be(_be)
+{
+ this->setFlags(Event::AutoDelete);
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::TrapEvent::process()
+{
+ be->trapSquash = true;
+}
+
+template <class Impl>
+const char *
+LWBackEnd<Impl>::TrapEvent::description()
+{
+ return "Trap event";
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::replayMemInst(DynInstPtr &inst)
+{
+ bool found_inst = false;
+ while (!replayList.empty()) {
+ exeList.push(replayList.front());
+ if (replayList.front() == inst) {
+ found_inst = true;
+ }
+ replayList.pop_front();
+ }
+ assert(found_inst);
+}
+
+template<class Impl>
+LWBackEnd<Impl>::LdWritebackEvent::LdWritebackEvent(DynInstPtr &_inst,
+ LWBackEnd<Impl> *_be)
+ : Event(&mainEventQueue), inst(_inst), be(_be), dcacheMiss(false)
+{
+ this->setFlags(Event::AutoDelete);
+}
+
+template<class Impl>
+void
+LWBackEnd<Impl>::LdWritebackEvent::process()
+{
+ DPRINTF(BE, "Load writeback event [sn:%lli]\n", inst->seqNum);
+// DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum);
+
+ //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
+
+// iewStage->wakeCPU();
+
+ if (be->isSwitchedOut())
+ return;
+
+ if (dcacheMiss) {
+ be->removeDcacheMiss(inst);
+ }
+
+ if (inst->isSquashed()) {
+ inst = NULL;
+ return;
+ }
+
+ if (!inst->isExecuted()) {
+ inst->setExecuted();
+
+ // Execute again to copy data to proper place.
+ inst->completeAcc();
+ }
+
+ // Need to insert instruction into queue to commit
+ be->instToCommit(inst);
+
+ //wroteToTimeBuffer = true;
+// iewStage->activityThisCycle();
+
+ inst = NULL;
+}
+
+template<class Impl>
+const char *
+LWBackEnd<Impl>::LdWritebackEvent::description()
+{
+ return "Load writeback event";
+}
+
+
+template <class Impl>
+LWBackEnd<Impl>::DCacheCompletionEvent::DCacheCompletionEvent(LWBackEnd *_be)
+ : Event(&mainEventQueue, CPU_Tick_Pri), be(_be)
+{
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::DCacheCompletionEvent::process()
+{
+}
+
+template <class Impl>
+const char *
+LWBackEnd<Impl>::DCacheCompletionEvent::description()
+{
+ return "Cache completion event";
+}
+
+template <class Impl>
+LWBackEnd<Impl>::LWBackEnd(Params *params)
+ : d2i(5, 5), i2e(5, 5), e2c(5, 5), numInstsToWB(5, 5),
+ trapSquash(false), xcSquash(false), cacheCompletionEvent(this),
+ dcacheInterface(params->dcacheInterface), width(params->backEndWidth),
+ exactFullStall(true)
+{
+ numROBEntries = params->numROBEntries;
+ numInsts = 0;
+ numDispatchEntries = 32;
+ maxOutstandingMemOps = params->maxOutstandingMemOps;
+ numWaitingMemOps = 0;
+ waitingInsts = 0;
+ switchedOut = false;
+ switchPending = false;
+
+ LSQ.setBE(this);
+
+ // Setup IQ and LSQ with their parameters here.
+ instsToDispatch = d2i.getWire(-1);
+
+ instsToExecute = i2e.getWire(-1);
+
+ dispatchWidth = params->dispatchWidth ? params->dispatchWidth : width;
+ issueWidth = params->issueWidth ? params->issueWidth : width;
+ wbWidth = params->wbWidth ? params->wbWidth : width;
+ commitWidth = params->commitWidth ? params->commitWidth : width;
+
+ LSQ.init(params, params->LQEntries, params->SQEntries, 0);
+
+ dispatchStatus = Running;
+}
+
+template <class Impl>
+std::string
+LWBackEnd<Impl>::name() const
+{
+ return cpu->name() + ".backend";
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::regStats()
+{
+ using namespace Stats;
+ rob_cap_events
+ .init(cpu->number_of_threads)
+ .name(name() + ".ROB:cap_events")
+ .desc("number of cycles where ROB cap was active")
+ .flags(total)
+ ;
+
+ rob_cap_inst_count
+ .init(cpu->number_of_threads)
+ .name(name() + ".ROB:cap_inst")
+ .desc("number of instructions held up by ROB cap")
+ .flags(total)
+ ;
+
+ iq_cap_events
+ .init(cpu->number_of_threads)
+ .name(name() +".IQ:cap_events" )
+ .desc("number of cycles where IQ cap was active")
+ .flags(total)
+ ;
+
+ iq_cap_inst_count
+ .init(cpu->number_of_threads)
+ .name(name() + ".IQ:cap_inst")
+ .desc("number of instructions held up by IQ cap")
+ .flags(total)
+ ;
+
+
+ exe_inst
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:count")
+ .desc("number of insts issued")
+ .flags(total)
+ ;
+
+ exe_swp
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:swp")
+ .desc("number of swp insts issued")
+ .flags(total)
+ ;
+
+ exe_nop
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:nop")
+ .desc("number of nop insts issued")
+ .flags(total)
+ ;
+
+ exe_refs
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:refs")
+ .desc("number of memory reference insts issued")
+ .flags(total)
+ ;
+
+ exe_loads
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:loads")
+ .desc("number of load insts issued")
+ .flags(total)
+ ;
+
+ exe_branches
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:branches")
+ .desc("Number of branches issued")
+ .flags(total)
+ ;
+
+ issued_ops
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:op_count")
+ .desc("number of insts issued")
+ .flags(total)
+ ;
+
+/*
+ for (int i=0; i<Num_OpClasses; ++i) {
+ stringstream subname;
+ subname << opClassStrings[i] << "_delay";
+ issue_delay_dist.subname(i, subname.str());
+ }
+*/
+ //
+ // Other stats
+ //
+ lsq_forw_loads
+ .init(cpu->number_of_threads)
+ .name(name() + ".LSQ:forw_loads")
+ .desc("number of loads forwarded via LSQ")
+ .flags(total)
+ ;
+
+ inv_addr_loads
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:addr_loads")
+ .desc("number of invalid-address loads")
+ .flags(total)
+ ;
+
+ inv_addr_swpfs
+ .init(cpu->number_of_threads)
+ .name(name() + ".ISSUE:addr_swpfs")
+ .desc("number of invalid-address SW prefetches")
+ .flags(total)
+ ;
+
+ lsq_blocked_loads
+ .init(cpu->number_of_threads)
+ .name(name() + ".LSQ:blocked_loads")
+ .desc("number of ready loads not issued due to memory disambiguation")
+ .flags(total)
+ ;
+
+ lsqInversion
+ .name(name() + ".ISSUE:lsq_invert")
+ .desc("Number of times LSQ instruction issued early")
+ ;
+
+ n_issued_dist
+ .init(issueWidth + 1)
+ .name(name() + ".ISSUE:issued_per_cycle")
+ .desc("Number of insts issued each cycle")
+ .flags(total | pdf | dist)
+ ;
+ issue_delay_dist
+ .init(Num_OpClasses,0,99,2)
+ .name(name() + ".ISSUE:")
+ .desc("cycles from operands ready to issue")
+ .flags(pdf | cdf)
+ ;
+
+ queue_res_dist
+ .init(Num_OpClasses, 0, 99, 2)
+ .name(name() + ".IQ:residence:")
+ .desc("cycles from dispatch to issue")
+ .flags(total | pdf | cdf )
+ ;
+ for (int i = 0; i < Num_OpClasses; ++i) {
+ queue_res_dist.subname(i, opClassStrings[i]);
+ }
+
+ writeback_count
+ .init(cpu->number_of_threads)
+ .name(name() + ".WB:count")
+ .desc("cumulative count of insts written-back")
+ .flags(total)
+ ;
+
+ producer_inst
+ .init(cpu->number_of_threads)
+ .name(name() + ".WB:producers")
+ .desc("num instructions producing a value")
+ .flags(total)
+ ;
+
+ consumer_inst
+ .init(cpu->number_of_threads)
+ .name(name() + ".WB:consumers")
+ .desc("num instructions consuming a value")
+ .flags(total)
+ ;
+
+ wb_penalized
+ .init(cpu->number_of_threads)
+ .name(name() + ".WB:penalized")
+ .desc("number of instrctions required to write to 'other' IQ")
+ .flags(total)
+ ;
+
+
+ wb_penalized_rate
+ .name(name() + ".WB:penalized_rate")
+ .desc ("fraction of instructions written-back that wrote to 'other' IQ")
+ .flags(total)
+ ;
+
+ wb_penalized_rate = wb_penalized / writeback_count;
+
+ wb_fanout
+ .name(name() + ".WB:fanout")
+ .desc("average fanout of values written-back")
+ .flags(total)
+ ;
+
+ wb_fanout = producer_inst / consumer_inst;
+
+ wb_rate
+ .name(name() + ".WB:rate")
+ .desc("insts written-back per cycle")
+ .flags(total)
+ ;
+ wb_rate = writeback_count / cpu->numCycles;
+
+ stat_com_inst
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:count")
+ .desc("Number of instructions committed")
+ .flags(total)
+ ;
+
+ stat_com_swp
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:swp_count")
+ .desc("Number of s/w prefetches committed")
+ .flags(total)
+ ;
+
+ stat_com_refs
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:refs")
+ .desc("Number of memory references committed")
+ .flags(total)
+ ;
+
+ stat_com_loads
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:loads")
+ .desc("Number of loads committed")
+ .flags(total)
+ ;
+
+ stat_com_membars
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:membars")
+ .desc("Number of memory barriers committed")
+ .flags(total)
+ ;
+
+ stat_com_branches
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:branches")
+ .desc("Number of branches committed")
+ .flags(total)
+ ;
+ n_committed_dist
+ .init(0,commitWidth,1)
+ .name(name() + ".COM:committed_per_cycle")
+ .desc("Number of insts commited each cycle")
+ .flags(pdf)
+ ;
+
+ //
+ // Commit-Eligible instructions...
+ //
+ // -> The number of instructions eligible to commit in those
+ // cycles where we reached our commit BW limit (less the number
+ // actually committed)
+ //
+ // -> The average value is computed over ALL CYCLES... not just
+ // the BW limited cycles
+ //
+ // -> The standard deviation is computed only over cycles where
+ // we reached the BW limit
+ //
+ commit_eligible
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:bw_limited")
+ .desc("number of insts not committed due to BW limits")
+ .flags(total)
+ ;
+
+ commit_eligible_samples
+ .name(name() + ".COM:bw_lim_events")
+ .desc("number cycles where commit BW limit reached")
+ ;
+
+ squashedInsts
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:squashed_insts")
+ .desc("Number of instructions removed from inst list")
+ ;
+
+ ROBSquashedInsts
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:rob_squashed_insts")
+ .desc("Number of instructions removed from inst list when they reached the head of the ROB")
+ ;
+
+ ROB_fcount
+ .name(name() + ".ROB:full_count")
+ .desc("number of cycles where ROB was full")
+ ;
+
+ ROB_count
+ .init(cpu->number_of_threads)
+ .name(name() + ".ROB:occupancy")
+ .desc(name() + ".ROB occupancy (cumulative)")
+ .flags(total)
+ ;
+
+ ROB_full_rate
+ .name(name() + ".ROB:full_rate")
+ .desc("ROB full per cycle")
+ ;
+ ROB_full_rate = ROB_fcount / cpu->numCycles;
+
+ ROB_occ_rate
+ .name(name() + ".ROB:occ_rate")
+ .desc("ROB occupancy rate")
+ .flags(total)
+ ;
+ ROB_occ_rate = ROB_count / cpu->numCycles;
+
+ ROB_occ_dist
+ .init(cpu->number_of_threads,0,numROBEntries,2)
+ .name(name() + ".ROB:occ_dist")
+ .desc("ROB Occupancy per cycle")
+ .flags(total | cdf)
+ ;
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::setCPU(FullCPU *cpu_ptr)
+{
+ cpu = cpu_ptr;
+ LSQ.setCPU(cpu_ptr);
+ checker = cpu->checker;
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
+{
+ comm = _comm;
+ toIEW = comm->getWire(0);
+ fromCommit = comm->getWire(-1);
+}
+
+#if FULL_SYSTEM
+template <class Impl>
+void
+LWBackEnd<Impl>::checkInterrupts()
+{
+ if (cpu->checkInterrupts &&
+ cpu->check_interrupts() &&
+ !cpu->inPalMode(thread->readPC()) &&
+ !trapSquash &&
+ !xcSquash) {
+ frontEnd->interruptPending = true;
+ if (robEmpty() && !LSQ.hasStoresToWB()) {
+ // Will need to squash all instructions currently in flight and have
+ // the interrupt handler restart at the last non-committed inst.
+ // Most of that can be handled through the trap() function. The
+ // processInterrupts() function really just checks for interrupts
+ // and then calls trap() if there is an interrupt present.
+
+ // Not sure which thread should be the one to interrupt. For now
+ // always do thread 0.
+ assert(!thread->inSyscall);
+ thread->inSyscall = true;
+
+ // CPU will handle implementation of the interrupt.
+ cpu->processInterrupts();
+
+ // Now squash or record that I need to squash this cycle.
+ commitStatus = TrapPending;
+
+ // Exit state update mode to avoid accidental updating.
+ thread->inSyscall = false;
+
+ // Generate trap squash event.
+ generateTrapEvent();
+
+ DPRINTF(BE, "Interrupt detected.\n");
+ } else {
+ DPRINTF(BE, "Interrupt must wait for ROB to drain.\n");
+ }
+ }
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::handleFault(Fault &fault, Tick latency)
+{
+ DPRINTF(BE, "Handling fault!\n");
+
+ assert(!thread->inSyscall);
+
+ thread->inSyscall = true;
+
+ // Consider holding onto the trap and waiting until the trap event
+ // happens for this to be executed.
+ fault->invoke(thread->getXCProxy());
+
+ // Exit state update mode to avoid accidental updating.
+ thread->inSyscall = false;
+
+ commitStatus = TrapPending;
+
+ // Generate trap squash event.
+ generateTrapEvent(latency);
+}
+#endif
+
+template <class Impl>
+void
+LWBackEnd<Impl>::tick()
+{
+ DPRINTF(BE, "Ticking back end\n");
+
+ if (switchPending && robEmpty() && !LSQ.hasStoresToWB()) {
+ cpu->signalSwitched();
+ return;
+ }
+
+ ROB_count[0]+= numInsts;
+
+ wbCycle = 0;
+
+ // Read in any done instruction information and update the IQ or LSQ.
+ updateStructures();
+
+#if FULL_SYSTEM
+ checkInterrupts();
+
+ if (trapSquash) {
+ assert(!xcSquash);
+ squashFromTrap();
+ } else if (xcSquash) {
+ squashFromXC();
+ }
+#endif
+
+ if (dispatchStatus != Blocked) {
+ dispatchInsts();
+ } else {
+ checkDispatchStatus();
+ }
+
+ if (commitStatus != TrapPending) {
+ executeInsts();
+
+ commitInsts();
+ }
+
+ LSQ.writebackStores();
+
+ DPRINTF(BE, "Waiting insts: %i, mem ops: %i, ROB entries in use: %i, "
+ "LSQ loads: %i, LSQ stores: %i\n",
+ waitingInsts, numWaitingMemOps, numInsts,
+ LSQ.numLoads(), LSQ.numStores());
+
+#ifdef DEBUG
+ assert(numInsts == instList.size());
+ assert(waitingInsts == waitingList.size());
+ assert(numWaitingMemOps == waitingMemOps.size());
+ assert(!switchedOut);
+#endif
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::updateStructures()
+{
+ if (fromCommit->doneSeqNum) {
+ LSQ.commitLoads(fromCommit->doneSeqNum);
+ LSQ.commitStores(fromCommit->doneSeqNum);
+ }
+
+ if (fromCommit->nonSpecSeqNum) {
+ if (fromCommit->uncached) {
+// LSQ.executeLoad(fromCommit->lqIdx);
+ } else {
+// IQ.scheduleNonSpec(
+// fromCommit->nonSpecSeqNum);
+ }
+ }
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::addToLSQ(DynInstPtr &inst)
+{
+ // Do anything LSQ specific here?
+ LSQ.insert(inst);
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::dispatchInsts()
+{
+ DPRINTF(BE, "Trying to dispatch instructions.\n");
+
+ while (numInsts < numROBEntries &&
+ numWaitingMemOps < maxOutstandingMemOps) {
+ // Get instruction from front of time buffer
+ DynInstPtr inst = frontEnd->getInst();
+ if (!inst) {
+ break;
+ } else if (inst->isSquashed()) {
+ continue;
+ }
+
+ ++numInsts;
+ instList.push_front(inst);
+
+ inst->setInROB();
+
+ DPRINTF(BE, "Dispatching instruction [sn:%lli] PC:%#x\n",
+ inst->seqNum, inst->readPC());
+
+ for (int i = 0; i < inst->numDestRegs(); ++i)
+ renameTable[inst->destRegIdx(i)] = inst;
+
+ if (inst->isMemBarrier() || inst->isWriteBarrier()) {
+ if (memBarrier) {
+ DPRINTF(BE, "Instruction [sn:%lli] is waiting on "
+ "barrier [sn:%lli].\n",
+ inst->seqNum, memBarrier->seqNum);
+ memBarrier->addMemDependent(inst);
+ inst->addSrcMemInst(memBarrier);
+ }
+ memBarrier = inst;
+ inst->setCanCommit();
+ } else if (inst->readyToIssue() &&
+ !inst->isNonSpeculative() &&
+ !inst->isStoreConditional()) {
+ if (inst->isMemRef()) {
+
+ LSQ.insert(inst);
+ if (memBarrier) {
+ DPRINTF(BE, "Instruction [sn:%lli] is waiting on "
+ "barrier [sn:%lli].\n",
+ inst->seqNum, memBarrier->seqNum);
+ memBarrier->addMemDependent(inst);
+ inst->addSrcMemInst(memBarrier);
+ addWaitingMemOp(inst);
+
+ waitingList.push_front(inst);
+ inst->iqIt = waitingList.begin();
+ inst->iqItValid = true;
+ waitingInsts++;
+ } else {
+ DPRINTF(BE, "Instruction [sn:%lli] ready, addding to "
+ "exeList.\n",
+ inst->seqNum);
+ exeList.push(inst);
+ }
+ } else if (inst->isNop()) {
+ DPRINTF(BE, "Nop encountered [sn:%lli], skipping exeList.\n",
+ inst->seqNum);
+ inst->setIssued();
+ inst->setExecuted();
+ inst->setCanCommit();
+ } else {
+ DPRINTF(BE, "Instruction [sn:%lli] ready, addding to "
+ "exeList.\n",
+ inst->seqNum);
+ exeList.push(inst);
+ }
+ } else {
+ if (inst->isNonSpeculative() || inst->isStoreConditional()) {
+ inst->setCanCommit();
+ DPRINTF(BE, "Adding non speculative instruction\n");
+ }
+
+ if (inst->isMemRef()) {
+ addWaitingMemOp(inst);
+ LSQ.insert(inst);
+ if (memBarrier) {
+ memBarrier->addMemDependent(inst);
+ inst->addSrcMemInst(memBarrier);
+
+ DPRINTF(BE, "Instruction [sn:%lli] is waiting on "
+ "barrier [sn:%lli].\n",
+ inst->seqNum, memBarrier->seqNum);
+ }
+ }
+
+ DPRINTF(BE, "Instruction [sn:%lli] not ready, addding to "
+ "waitingList.\n",
+ inst->seqNum);
+ waitingList.push_front(inst);
+ inst->iqIt = waitingList.begin();
+ inst->iqItValid = true;
+ waitingInsts++;
+ }
+ }
+
+ // Check if IQ or LSQ is full. If so we'll need to break and stop
+ // removing instructions. Also update the number of insts to remove
+ // from the queue. Check here if we don't care about exact stall
+ // conditions.
+/*
+ bool stall = false;
+ if (IQ.isFull()) {
+ DPRINTF(BE, "IQ is full!\n");
+ stall = true;
+ } else if (LSQ.isFull()) {
+ DPRINTF(BE, "LSQ is full!\n");
+ stall = true;
+ } else if (isFull()) {
+ DPRINTF(BE, "ROB is full!\n");
+ stall = true;
+ ROB_fcount++;
+ }
+ if (stall) {
+ d2i.advance();
+ dispatchStall();
+ return;
+ }
+*/
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::dispatchStall()
+{
+ dispatchStatus = Blocked;
+ if (!cpu->decoupledFrontEnd) {
+ // Tell front end to stall here through a timebuffer, or just tell
+ // it directly.
+ }
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::checkDispatchStatus()
+{
+ DPRINTF(BE, "Checking dispatch status\n");
+ assert(dispatchStatus == Blocked);
+ if (!LSQ.isFull() && !isFull()) {
+ DPRINTF(BE, "Dispatch no longer blocked\n");
+ dispatchStatus = Running;
+ dispatchInsts();
+ }
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::executeInsts()
+{
+ DPRINTF(BE, "Trying to execute instructions\n");
+
+ int num_executed = 0;
+ while (!exeList.empty() && num_executed < issueWidth) {
+ DynInstPtr inst = exeList.top();
+
+ DPRINTF(BE, "Executing inst [sn:%lli] PC: %#x\n",
+ inst->seqNum, inst->readPC());
+
+ // Check if the instruction is squashed; if so then skip it
+ // and don't count it towards the FU usage.
+ if (inst->isSquashed()) {
+ DPRINTF(BE, "Execute: Instruction was squashed.\n");
+
+ // Not sure how to handle this plus the method of sending # of
+ // instructions to use. Probably will just have to count it
+ // towards the bandwidth usage, but not the FU usage.
+ ++num_executed;
+
+ // Consider this instruction executed so that commit can go
+ // ahead and retire the instruction.
+ inst->setExecuted();
+
+ // Not sure if I should set this here or just let commit try to
+ // commit any squashed instructions. I like the latter a bit more.
+ inst->setCanCommit();
+
+// ++iewExecSquashedInsts;
+ exeList.pop();
+
+ continue;
+ }
+
+ Fault fault = NoFault;
+
+ // Execute instruction.
+ // Note that if the instruction faults, it will be handled
+ // at the commit stage.
+ if (inst->isMemRef() &&
+ (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
+ if (dcacheInterface->isBlocked()) {
+ // Should I move the instruction aside?
+ DPRINTF(BE, "Execute: dcache is blocked\n");
+ break;
+ }
+ DPRINTF(BE, "Execute: Initiating access for memory "
+ "reference.\n");
+
+ if (inst->isLoad()) {
+ LSQ.executeLoad(inst);
+ } else if (inst->isStore()) {
+ LSQ.executeStore(inst);
+ if (inst->req && !(inst->req->flags & LOCKED)) {
+ inst->setExecuted();
+
+ instToCommit(inst);
+ }
+ } else {
+ panic("Unknown mem type!");
+ }
+ } else {
+ inst->execute();
+
+ inst->setExecuted();
+
+ instToCommit(inst);
+ }
+
+ updateExeInstStats(inst);
+
+ ++funcExeInst;
+ ++num_executed;
+
+ exeList.pop();
+
+ if (inst->mispredicted()) {
+ squashDueToBranch(inst);
+ break;
+ } else if (LSQ.violation()) {
+ // Get the DynInst that caused the violation. Note that this
+ // clears the violation signal.
+ DynInstPtr violator;
+ violator = LSQ.getMemDepViolator();
+
+ DPRINTF(BE, "LDSTQ detected a violation. Violator PC: "
+ "%#x, inst PC: %#x. Addr is: %#x.\n",
+ violator->readPC(), inst->readPC(), inst->physEffAddr);
+
+ // Squash.
+ squashDueToMemViolation(inst);
+ }
+ }
+
+ issued_ops[0]+= num_executed;
+ n_issued_dist[num_executed]++;
+}
+
+template<class Impl>
+void
+LWBackEnd<Impl>::instToCommit(DynInstPtr &inst)
+{
+
+ DPRINTF(BE, "Sending instructions to commit [sn:%lli] PC %#x.\n",
+ inst->seqNum, inst->readPC());
+
+ if (!inst->isSquashed()) {
+ DPRINTF(BE, "Writing back instruction [sn:%lli] PC %#x.\n",
+ inst->seqNum, inst->readPC());
+
+ inst->setCanCommit();
+
+ if (inst->isExecuted()) {
+ inst->setResultReady();
+ int dependents = wakeDependents(inst);
+ if (dependents) {
+ producer_inst[0]++;
+ consumer_inst[0]+= dependents;
+ }
+ }
+ }
+
+ writeback_count[0]++;
+}
+#if 0
+template <class Impl>
+void
+LWBackEnd<Impl>::writebackInsts()
+{
+ int wb_width = wbWidth;
+ // Using this method I'm not quite sure how to prevent an
+ // instruction from waking its own dependents multiple times,
+ // without the guarantee that commit always has enough bandwidth
+ // to accept all instructions being written back. This guarantee
+ // might not be too unrealistic.
+ InstListIt wb_inst_it = writeback.begin();
+ InstListIt wb_end_it = writeback.end();
+ int inst_num = 0;
+ int consumer_insts = 0;
+
+ for (; inst_num < wb_width &&
+ wb_inst_it != wb_end_it; inst_num++) {
+ DynInstPtr inst = (*wb_inst_it);
+
+ // Some instructions will be sent to commit without having
+ // executed because they need commit to handle them.
+ // E.g. Uncached loads have not actually executed when they
+ // are first sent to commit. Instead commit must tell the LSQ
+ // when it's ready to execute the uncached load.
+ if (!inst->isSquashed()) {
+ DPRINTF(BE, "Writing back instruction [sn:%lli] PC %#x.\n",
+ inst->seqNum, inst->readPC());
+
+ inst->setCanCommit();
+ inst->setResultReady();
+
+ if (inst->isExecuted()) {
+ int dependents = wakeDependents(inst);
+ if (dependents) {
+ producer_inst[0]++;
+ consumer_insts+= dependents;
+ }
+ }
+ }
+
+ writeback.erase(wb_inst_it++);
+ }
+ LSQ.writebackStores();
+ consumer_inst[0]+= consumer_insts;
+ writeback_count[0]+= inst_num;
+}
+#endif
+template <class Impl>
+bool
+LWBackEnd<Impl>::commitInst(int inst_num)
+{
+ // Read instruction from the head of the ROB
+ DynInstPtr inst = instList.back();
+
+ // Make sure instruction is valid
+ assert(inst);
+
+ if (!inst->readyToCommit())
+ return false;
+
+ DPRINTF(BE, "Trying to commit instruction [sn:%lli] PC:%#x\n",
+ inst->seqNum, inst->readPC());
+
+ thread->setPC(inst->readPC());
+ thread->setNextPC(inst->readNextPC());
+ inst->reachedCommit = true;
+
+ // If the instruction is not executed yet, then it is a non-speculative
+ // or store inst. Signal backwards that it should be executed.
+ if (!inst->isExecuted()) {
+ if (inst->isNonSpeculative() ||
+ inst->isStoreConditional() ||
+ inst->isMemBarrier() ||
+ inst->isWriteBarrier()) {
+#if !FULL_SYSTEM
+ // Hack to make sure syscalls aren't executed until all stores
+ // write back their data. This direct communication shouldn't
+ // be used for anything other than this.
+ if (inst_num > 0 || LSQ.hasStoresToWB())
+#else
+ if ((inst->isMemBarrier() || inst->isWriteBarrier() ||
+ inst->isQuiesce()) &&
+ LSQ.hasStoresToWB())
+#endif
+ {
+ DPRINTF(BE, "Waiting for all stores to writeback.\n");
+ return false;
+ }
+
+ DPRINTF(BE, "Encountered a store or non-speculative "
+ "instruction at the head of the ROB, PC %#x.\n",
+ inst->readPC());
+
+ if (inst->isMemBarrier() || inst->isWriteBarrier()) {
+ DPRINTF(BE, "Waking dependents on barrier [sn:%lli]\n",
+ inst->seqNum);
+ assert(memBarrier);
+ wakeDependents(inst, true);
+ if (memBarrier == inst)
+ memBarrier = NULL;
+ inst->clearMemDependents();
+ }
+
+ // Send back the non-speculative instruction's sequence number.
+ if (inst->iqItValid) {
+ DPRINTF(BE, "Removing instruction from waiting list\n");
+ waitingList.erase(inst->iqIt);
+ inst->iqItValid = false;
+ waitingInsts--;
+ assert(waitingInsts >= 0);
+ if (inst->isStore())
+ removeWaitingMemOp(inst);
+ }
+
+ exeList.push(inst);
+
+ // Change the instruction so it won't try to commit again until
+ // it is executed.
+ inst->clearCanCommit();
+
+// ++commitNonSpecStalls;
+
+ return false;
+ } else if (inst->isLoad()) {
+ DPRINTF(BE, "[sn:%lli]: Uncached load, PC %#x.\n",
+ inst->seqNum, inst->readPC());
+
+ // Send back the non-speculative instruction's sequence
+ // number. Maybe just tell the lsq to re-execute the load.
+
+ // Send back the non-speculative instruction's sequence number.
+ if (inst->iqItValid) {
+ DPRINTF(BE, "Removing instruction from waiting list\n");
+ waitingList.erase(inst->iqIt);
+ inst->iqItValid = false;
+ waitingInsts--;
+ assert(waitingInsts >= 0);
+ removeWaitingMemOp(inst);
+ }
+ replayMemInst(inst);
+
+ inst->clearCanCommit();
+
+ return false;
+ } else {
+ panic("Trying to commit un-executed instruction "
+ "of unknown type!\n");
+ }
+ }
+
+ // Not handled for now.
+ assert(!inst->isThreadSync());
+ assert(inst->memDepReady());
+ // Stores will mark themselves as totally completed as they need
+ // to wait to writeback to memory. @todo: Hack...attempt to fix
+ // having the checker be forced to wait until a store completes in
+ // order to check all of the instructions. If the store at the
+ // head of the check list misses, but a later store hits, then
+ // loads in the checker may see the younger store values instead
+ // of the store they should see. Either the checker needs its own
+ // memory (annoying to update), its own store buffer (how to tell
+ // which value is correct?), or something else...
+ if (!inst->isStore()) {
+ inst->setCompleted();
+ }
+ // Check if the instruction caused a fault. If so, trap.
+ Fault inst_fault = inst->getFault();
+
+ // Use checker prior to updating anything due to traps or PC
+ // based events.
+ if (checker) {
+ checker->tick(inst);
+ }
+
+ if (inst_fault != NoFault) {
+ DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n",
+ inst->seqNum, inst->readPC());
+
+ // Instruction is completed as it has a fault.
+ inst->setCompleted();
+
+ if (LSQ.hasStoresToWB()) {
+ DPRINTF(BE, "Stores still in flight, will wait until drained.\n");
+ return false;
+ } else if (inst_num != 0) {
+ DPRINTF(BE, "Will wait until instruction is head of commit group.\n");
+ return false;
+ } else if (checker && inst->isStore()) {
+ checker->tick(inst);
+ }
+
+ thread->setInst(
+ static_cast<TheISA::MachInst>(inst->staticInst->machInst));
+#if FULL_SYSTEM
+ handleFault(inst_fault);
+ return false;
+#else // !FULL_SYSTEM
+ panic("fault (%d) detected @ PC %08p", inst_fault,
+ inst->PC);
+#endif // FULL_SYSTEM
+ }
+
+ int freed_regs = 0;
+
+ for (int i = 0; i < inst->numDestRegs(); ++i) {
+ DPRINTF(BE, "Commit rename map setting reg %i to [sn:%lli]\n",
+ (int)inst->destRegIdx(i), inst->seqNum);
+ thread->renameTable[inst->destRegIdx(i)] = inst;
+ ++freed_regs;
+ }
+
+ if (inst->traceData) {
+ inst->traceData->setFetchSeq(inst->seqNum);
+ inst->traceData->setCPSeq(thread->numInst);
+ inst->traceData->finalize();
+ inst->traceData = NULL;
+ }
+
+ inst->clearDependents();
+
+ frontEnd->addFreeRegs(freed_regs);
+
+ instList.pop_back();
+
+ --numInsts;
+ ++thread->funcExeInst;
+ // Maybe move this to where the fault is handled; if the fault is
+ // handled, don't try to set this myself as the fault will set it.
+ // If not, then I set thread->PC = thread->nextPC and
+ // thread->nextPC = thread->nextPC + 4.
+ thread->setPC(thread->readNextPC());
+ thread->setNextPC(thread->readNextPC() + sizeof(TheISA::MachInst));
+ updateComInstStats(inst);
+
+ // Write the done sequence number here.
+ toIEW->doneSeqNum = inst->seqNum;
+ lastCommitCycle = curTick;
+
+#if FULL_SYSTEM
+ int count = 0;
+ Addr oldpc;
+ do {
+ if (count == 0)
+ assert(!thread->inSyscall && !thread->trapPending);
+ oldpc = thread->readPC();
+ cpu->system->pcEventQueue.service(
+ thread->getXCProxy());
+ count++;
+ } while (oldpc != thread->readPC());
+ if (count > 1) {
+ DPRINTF(BE, "PC skip function event, stopping commit\n");
+ xcSquash = true;
+ return false;
+ }
+#endif
+ return true;
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::commitInsts()
+{
+ // Not sure this should be a loop or not.
+ int inst_num = 0;
+ while (!instList.empty() && inst_num < commitWidth) {
+ if (instList.back()->isSquashed()) {
+ instList.back()->clearDependents();
+ instList.pop_back();
+ --numInsts;
+ ROBSquashedInsts[instList.back()->threadNumber]++;
+ continue;
+ }
+
+ if (!commitInst(inst_num++)) {
+ DPRINTF(BE, "Can't commit, Instruction [sn:%lli] PC "
+ "%#x is head of ROB and not ready\n",
+ instList.back()->seqNum, instList.back()->readPC());
+ --inst_num;
+ break;
+ }
+ }
+ n_committed_dist.sample(inst_num);
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::squash(const InstSeqNum &sn)
+{
+ LSQ.squash(sn);
+
+ int freed_regs = 0;
+ InstListIt waiting_list_end = waitingList.end();
+ InstListIt insts_it = waitingList.begin();
+
+ while (insts_it != waiting_list_end && (*insts_it)->seqNum > sn)
+ {
+ if ((*insts_it)->isSquashed()) {
+ ++insts_it;
+ continue;
+ }
+ DPRINTF(BE, "Squashing instruction on waitingList PC %#x, [sn:%lli].\n",
+ (*insts_it)->readPC(),
+ (*insts_it)->seqNum);
+
+ if ((*insts_it)->isMemRef()) {
+ DPRINTF(BE, "Squashing a waiting mem op [sn:%lli]\n",
+ (*insts_it)->seqNum);
+ removeWaitingMemOp((*insts_it));
+ }
+
+ waitingList.erase(insts_it++);
+ waitingInsts--;
+ }
+ assert(waitingInsts >= 0);
+
+ insts_it = instList.begin();
+
+ while (!instList.empty() && (*insts_it)->seqNum > sn)
+ {
+ if ((*insts_it)->isSquashed()) {
+ ++insts_it;
+ continue;
+ }
+ DPRINTF(BE, "Squashing instruction on inst list PC %#x, [sn:%lli].\n",
+ (*insts_it)->readPC(),
+ (*insts_it)->seqNum);
+
+ // Mark the instruction as squashed, and ready to commit so that
+ // it can drain out of the pipeline.
+ (*insts_it)->setSquashed();
+
+ (*insts_it)->setCanCommit();
+
+ (*insts_it)->removeInROB();
+
+ for (int i = 0; i < (*insts_it)->numDestRegs(); ++i) {
+ DynInstPtr prev_dest = (*insts_it)->getPrevDestInst(i);
+ DPRINTF(BE, "Commit rename map setting reg %i to [sn:%lli]\n",
+ (int)(*insts_it)->destRegIdx(i), prev_dest->seqNum);
+ renameTable[(*insts_it)->destRegIdx(i)] = prev_dest;
+ ++freed_regs;
+ }
+
+ (*insts_it)->clearDependents();
+
+ squashedInsts[(*insts_it)->threadNumber]++;
+
+ instList.erase(insts_it++);
+ --numInsts;
+ }
+
+ insts_it = waitingList.begin();
+ while (!waitingList.empty() && insts_it != waitingList.end()) {
+ if ((*insts_it)->seqNum < sn) {
+ ++insts_it;
+ continue;
+ }
+ assert((*insts_it)->isSquashed());
+
+ waitingList.erase(insts_it++);
+ waitingInsts--;
+ }
+
+ while (memBarrier && memBarrier->seqNum > sn) {
+ DPRINTF(BE, "[sn:%lli] Memory barrier squashed (or previously "
+ "squashed)\n", memBarrier->seqNum);
+ memBarrier->clearMemDependents();
+ if (memBarrier->memDepReady()) {
+ DPRINTF(BE, "No previous barrier\n");
+ memBarrier = NULL;
+ } else {
+ std::list<DynInstPtr> &srcs = memBarrier->getMemSrcs();
+ memBarrier = srcs.front();
+ srcs.pop_front();
+ assert(srcs.empty());
+ DPRINTF(BE, "Previous barrier: [sn:%lli]\n",
+ memBarrier->seqNum);
+ }
+ }
+
+ frontEnd->addFreeRegs(freed_regs);
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::squashFromXC()
+{
+ InstSeqNum squashed_inst = robEmpty() ? 0 : instList.back()->seqNum - 1;
+ squash(squashed_inst);
+ frontEnd->squash(squashed_inst, thread->readPC(),
+ false, false);
+ frontEnd->interruptPending = false;
+
+ thread->trapPending = false;
+ thread->inSyscall = false;
+ xcSquash = false;
+ commitStatus = Running;
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::squashFromTrap()
+{
+ InstSeqNum squashed_inst = robEmpty() ? 0 : instList.back()->seqNum - 1;
+ squash(squashed_inst);
+ frontEnd->squash(squashed_inst, thread->readPC(),
+ false, false);
+ frontEnd->interruptPending = false;
+
+ thread->trapPending = false;
+ thread->inSyscall = false;
+ trapSquash = false;
+ commitStatus = Running;
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::squashDueToBranch(DynInstPtr &inst)
+{
+ // Update the branch predictor state I guess
+ DPRINTF(BE, "Squashing due to branch [sn:%lli], will restart at PC %#x\n",
+ inst->seqNum, inst->readNextPC());
+ squash(inst->seqNum);
+ frontEnd->squash(inst->seqNum, inst->readNextPC(),
+ true, inst->mispredicted());
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::squashDueToMemViolation(DynInstPtr &inst)
+{
+ // Update the branch predictor state I guess
+ DPRINTF(BE, "Squashing due to violation [sn:%lli], will restart at PC %#x\n",
+ inst->seqNum, inst->readNextPC());
+ squash(inst->seqNum);
+ frontEnd->squash(inst->seqNum, inst->readNextPC(),
+ false, inst->mispredicted());
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::squashDueToMemBlocked(DynInstPtr &inst)
+{
+ DPRINTF(IEW, "Memory blocked, squashing load and younger insts, "
+ "PC: %#x [sn:%i].\n", inst->readPC(), inst->seqNum);
+
+ squash(inst->seqNum - 1);
+ frontEnd->squash(inst->seqNum - 1, inst->readPC());
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::fetchFault(Fault &fault)
+{
+ faultFromFetch = fault;
+ fetchHasFault = true;
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::switchOut()
+{
+ switchPending = true;
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::doSwitchOut()
+{
+ switchedOut = true;
+ switchPending = false;
+ // Need to get rid of all committed, non-speculative state and write it
+ // to memory/XC. In this case this is stores that have committed and not
+ // yet written back.
+ assert(robEmpty());
+ assert(!LSQ.hasStoresToWB());
+
+ LSQ.switchOut();
+
+ squash(0);
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::takeOverFrom(ExecContext *old_xc)
+{
+ switchedOut = false;
+ xcSquash = false;
+ trapSquash = false;
+
+ numInsts = 0;
+ numWaitingMemOps = 0;
+ waitingMemOps.clear();
+ waitingInsts = 0;
+ switchedOut = false;
+ dispatchStatus = Running;
+ commitStatus = Running;
+ LSQ.takeOverFrom(old_xc);
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::updateExeInstStats(DynInstPtr &inst)
+{
+ int thread_number = inst->threadNumber;
+
+ //
+ // Pick off the software prefetches
+ //
+#ifdef TARGET_ALPHA
+ if (inst->isDataPrefetch())
+ exe_swp[thread_number]++;
+ else
+ exe_inst[thread_number]++;
+#else
+ exe_inst[thread_number]++;
+#endif
+
+ //
+ // Control operations
+ //
+ if (inst->isControl())
+ exe_branches[thread_number]++;
+
+ //
+ // Memory operations
+ //
+ if (inst->isMemRef()) {
+ exe_refs[thread_number]++;
+
+ if (inst->isLoad())
+ exe_loads[thread_number]++;
+ }
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::updateComInstStats(DynInstPtr &inst)
+{
+ unsigned tid = inst->threadNumber;
+
+ // keep an instruction count
+ thread->numInst++;
+ thread->numInsts++;
+
+ cpu->numInst++;
+ //
+ // Pick off the software prefetches
+ //
+#ifdef TARGET_ALPHA
+ if (inst->isDataPrefetch()) {
+ stat_com_swp[tid]++;
+ } else {
+ stat_com_inst[tid]++;
+ }
+#else
+ stat_com_inst[tid]++;
+#endif
+
+ //
+ // Control Instructions
+ //
+ if (inst->isControl())
+ stat_com_branches[tid]++;
+
+ //
+ // Memory references
+ //
+ if (inst->isMemRef()) {
+ stat_com_refs[tid]++;
+
+ if (inst->isLoad()) {
+ stat_com_loads[tid]++;
+ }
+ }
+
+ if (inst->isMemBarrier()) {
+ stat_com_membars[tid]++;
+ }
+}
+
+template <class Impl>
+void
+LWBackEnd<Impl>::dumpInsts()
+{
+ int num = 0;
+ int valid_num = 0;
+
+ InstListIt inst_list_it = --(instList.end());
+
+ cprintf("ExeList size: %i\n", exeList.size());
+
+ cprintf("Inst list size: %i\n", instList.size());
+
+ while (inst_list_it != instList.end())
+ {
+ cprintf("Instruction:%i\n",
+ num);
+ if (!(*inst_list_it)->isSquashed()) {
+ if (!(*inst_list_it)->isIssued()) {
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ } else if ((*inst_list_it)->isMemRef() &&
+ !(*inst_list_it)->memOpDone) {
+ // Loads that have not been marked as executed still count
+ // towards the total instructions.
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ }
+ }
+
+ cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
+ "Issued:%i\nSquashed:%i\n",
+ (*inst_list_it)->readPC(),
+ (*inst_list_it)->seqNum,
+ (*inst_list_it)->threadNumber,
+ (*inst_list_it)->isIssued(),
+ (*inst_list_it)->isSquashed());
+
+ if ((*inst_list_it)->isMemRef()) {
+ cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
+ }
+
+ cprintf("\n");
+
+ inst_list_it--;
+ ++num;
+ }
+
+ cprintf("Waiting list size: %i\n", waitingList.size());
+
+ inst_list_it = --(waitingList.end());
+
+ while (inst_list_it != waitingList.end())
+ {
+ cprintf("Instruction:%i\n",
+ num);
+ if (!(*inst_list_it)->isSquashed()) {
+ if (!(*inst_list_it)->isIssued()) {
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ } else if ((*inst_list_it)->isMemRef() &&
+ !(*inst_list_it)->memOpDone) {
+ // Loads that have not been marked as executed still count
+ // towards the total instructions.
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ }
+ }
+
+ cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
+ "Issued:%i\nSquashed:%i\n",
+ (*inst_list_it)->readPC(),
+ (*inst_list_it)->seqNum,
+ (*inst_list_it)->threadNumber,
+ (*inst_list_it)->isIssued(),
+ (*inst_list_it)->isSquashed());
+
+ if ((*inst_list_it)->isMemRef()) {
+ cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
+ }
+
+ cprintf("\n");
+
+ inst_list_it--;
+ ++num;
+ }
+
+ cprintf("waitingMemOps list size: %i\n", waitingMemOps.size());
+
+ MemIt waiting_it = waitingMemOps.begin();
+
+ while (waiting_it != waitingMemOps.end())
+ {
+ cprintf("[sn:%lli] ", (*waiting_it));
+ waiting_it++;
+ ++num;
+ }
+ cprintf("\n");
+}
diff --git a/cpu/ozone/lw_lsq.cc b/cpu/ozone/lw_lsq.cc
new file mode 100644
index 000000000..922228b09
--- /dev/null
+++ b/cpu/ozone/lw_lsq.cc
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu/ozone/ozone_impl.hh"
+#include "cpu/ozone/lw_lsq_impl.hh"
+
+// Force the instantiation of LDSTQ for all the implementations we care about.
+template class OzoneLWLSQ<OzoneImpl>;
+
diff --git a/cpu/ozone/lw_lsq.hh b/cpu/ozone/lw_lsq.hh
new file mode 100644
index 000000000..6fe343b42
--- /dev/null
+++ b/cpu/ozone/lw_lsq.hh
@@ -0,0 +1,657 @@
+/*
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_OZONE_LW_LSQ_HH__
+#define __CPU_OZONE_LW_LSQ_HH__
+
+#include <list>
+#include <map>
+#include <queue>
+#include <algorithm>
+
+#include "arch/faults.hh"
+#include "arch/isa_traits.hh"
+#include "config/full_system.hh"
+#include "base/hashmap.hh"
+#include "cpu/inst_seq.hh"
+#include "mem/mem_interface.hh"
+//#include "mem/page_table.hh"
+#include "sim/debug.hh"
+#include "sim/sim_object.hh"
+
+//class PageTable;
+
+/**
+ * Class that implements the actual LQ and SQ for each specific thread.
+ * Both are circular queues; load entries are freed upon committing, while
+ * store entries are freed once they writeback. The LSQUnit tracks if there
+ * are memory ordering violations, and also detects partial load to store
+ * forwarding cases (a store only has part of a load's data) that requires
+ * the load to wait until the store writes back. In the former case it
+ * holds onto the instruction until the dependence unit looks at it, and
+ * in the latter it stalls the LSQ until the store writes back. At that
+ * point the load is replayed.
+ */
+template <class Impl>
+class OzoneLWLSQ {
+ public:
+ typedef typename Impl::Params Params;
+ typedef typename Impl::FullCPU FullCPU;
+ typedef typename Impl::BackEnd BackEnd;
+ typedef typename Impl::DynInstPtr DynInstPtr;
+ typedef typename Impl::IssueStruct IssueStruct;
+
+ typedef TheISA::IntReg IntReg;
+
+ typedef typename std::map<InstSeqNum, DynInstPtr>::iterator LdMapIt;
+
+ private:
+ class StoreCompletionEvent : public Event {
+ public:
+ /** Constructs a store completion event. */
+ StoreCompletionEvent(DynInstPtr &inst, BackEnd *be,
+ Event *wb_event, OzoneLWLSQ *lsq_ptr);
+
+ /** Processes the store completion event. */
+ void process();
+
+ /** Returns the description of this event. */
+ const char *description();
+
+ private:
+ /** The store index of the store being written back. */
+ DynInstPtr inst;
+
+ BackEnd *be;
+ /** The writeback event for the store. Needed for store
+ * conditionals.
+ */
+ public:
+ Event *wbEvent;
+ bool miss;
+ private:
+ /** The pointer to the LSQ unit that issued the store. */
+ OzoneLWLSQ<Impl> *lsqPtr;
+ };
+
+ public:
+ /** Constructs an LSQ unit. init() must be called prior to use. */
+ OzoneLWLSQ();
+
+ /** Initializes the LSQ unit with the specified number of entries. */
+ void init(Params *params, unsigned maxLQEntries,
+ unsigned maxSQEntries, unsigned id);
+
+ /** Returns the name of the LSQ unit. */
+ std::string name() const;
+
+ /** Sets the CPU pointer. */
+ void setCPU(FullCPU *cpu_ptr)
+ { cpu = cpu_ptr; }
+
+ /** Sets the back-end stage pointer. */
+ void setBE(BackEnd *be_ptr)
+ { be = be_ptr; }
+
+ /** Sets the page table pointer. */
+// void setPageTable(PageTable *pt_ptr);
+
+ /** Ticks the LSQ unit, which in this case only resets the number of
+ * used cache ports.
+ * @todo: Move the number of used ports up to the LSQ level so it can
+ * be shared by all LSQ units.
+ */
+ void tick() { usedPorts = 0; }
+
+ /** Inserts an instruction. */
+ void insert(DynInstPtr &inst);
+ /** Inserts a load instruction. */
+ void insertLoad(DynInstPtr &load_inst);
+ /** Inserts a store instruction. */
+ void insertStore(DynInstPtr &store_inst);
+
+ /** Executes a load instruction. */
+ Fault executeLoad(DynInstPtr &inst);
+
+ /** Executes a store instruction. */
+ Fault executeStore(DynInstPtr &inst);
+
+ /** Commits the head load. */
+ void commitLoad();
+ /** Commits loads older than a specific sequence number. */
+ void commitLoads(InstSeqNum &youngest_inst);
+
+ /** Commits stores older than a specific sequence number. */
+ void commitStores(InstSeqNum &youngest_inst);
+
+ /** Writes back stores. */
+ void writebackStores();
+
+ // @todo: Include stats in the LSQ unit.
+ //void regStats();
+
+ /** Clears all the entries in the LQ. */
+ void clearLQ();
+
+ /** Clears all the entries in the SQ. */
+ void clearSQ();
+
+ /** Resizes the LQ to a given size. */
+ void resizeLQ(unsigned size);
+
+ /** Resizes the SQ to a given size. */
+ void resizeSQ(unsigned size);
+
+ /** Squashes all instructions younger than a specific sequence number. */
+ void squash(const InstSeqNum &squashed_num);
+
+ /** Returns if there is a memory ordering violation. Value is reset upon
+ * call to getMemDepViolator().
+ */
+ bool violation() { return memDepViolator; }
+
+ /** Returns the memory ordering violator. */
+ DynInstPtr getMemDepViolator();
+
+ /** Returns if a load became blocked due to the memory system. It clears
+ * the bool's value upon this being called.
+ */
+ bool loadBlocked()
+ { return isLoadBlocked; }
+
+ void clearLoadBlocked()
+ { isLoadBlocked = false; }
+
+ bool isLoadBlockedHandled()
+ { return loadBlockedHandled; }
+
+ void setLoadBlockedHandled()
+ { loadBlockedHandled = true; }
+
+ /** Returns the number of free entries (min of free LQ and SQ entries). */
+ unsigned numFreeEntries();
+
+ /** Returns the number of loads ready to execute. */
+ int numLoadsReady();
+
+ /** Returns the number of loads in the LQ. */
+ int numLoads() { return loads; }
+
+ /** Returns the number of stores in the SQ. */
+ int numStores() { return stores; }
+
+ /** Returns if either the LQ or SQ is full. */
+ bool isFull() { return lqFull() || sqFull(); }
+
+ /** Returns if the LQ is full. */
+ bool lqFull() { return loads >= (LQEntries - 1); }
+
+ /** Returns if the SQ is full. */
+ bool sqFull() { return stores >= (SQEntries - 1); }
+
+ /** Debugging function to dump instructions in the LSQ. */
+ void dumpInsts();
+
+ /** Returns the number of instructions in the LSQ. */
+ unsigned getCount() { return loads + stores; }
+
+ /** Returns if there are any stores to writeback. */
+ bool hasStoresToWB() { return storesToWB; }
+
+ /** Returns the number of stores to writeback. */
+ int numStoresToWB() { return storesToWB; }
+
+ /** Returns if the LSQ unit will writeback on this cycle. */
+ bool willWB() { return storeQueue.back().canWB &&
+ !storeQueue.back().completed &&
+ !dcacheInterface->isBlocked(); }
+
+ void switchOut();
+
+ void takeOverFrom(ExecContext *old_xc = NULL);
+
+ bool isSwitchedOut() { return switchedOut; }
+
+ bool switchedOut;
+
+ private:
+ /** Completes the store at the specified index. */
+ void completeStore(int store_idx);
+
+ private:
+ /** Pointer to the CPU. */
+ FullCPU *cpu;
+
+ /** Pointer to the back-end stage. */
+ BackEnd *be;
+
+ /** Pointer to the D-cache. */
+ MemInterface *dcacheInterface;
+
+ /** Pointer to the page table. */
+// PageTable *pTable;
+
+ public:
+ struct SQEntry {
+ /** Constructs an empty store queue entry. */
+ SQEntry()
+ : inst(NULL), req(NULL), size(0), data(0),
+ canWB(0), committed(0), completed(0), lqIt(NULL)
+ { }
+
+ /** Constructs a store queue entry for a given instruction. */
+ SQEntry(DynInstPtr &_inst)
+ : inst(_inst), req(NULL), size(0), data(0),
+ canWB(0), committed(0), completed(0), lqIt(NULL)
+ { }
+
+ /** The store instruction. */
+ DynInstPtr inst;
+ /** The memory request for the store. */
+ MemReqPtr req;
+ /** The size of the store. */
+ int size;
+ /** The store data. */
+ IntReg data;
+ /** Whether or not the store can writeback. */
+ bool canWB;
+ /** Whether or not the store is committed. */
+ bool committed;
+ /** Whether or not the store is completed. */
+ bool completed;
+
+ typename std::list<DynInstPtr>::iterator lqIt;
+ };
+
+ enum Status {
+ Running,
+ Idle,
+ DcacheMissStall,
+ DcacheMissSwitch
+ };
+
+ private:
+ /** The OzoneLWLSQ thread id. */
+ unsigned lsqID;
+
+ /** The status of the LSQ unit. */
+ Status _status;
+
+ /** The store queue. */
+ std::list<SQEntry> storeQueue;
+ /** The load queue. */
+ std::list<DynInstPtr> loadQueue;
+
+ typedef typename std::list<SQEntry>::iterator SQIt;
+ typedef typename std::list<DynInstPtr>::iterator LQIt;
+
+
+ struct HashFn {
+ size_t operator() (const int a) const
+ {
+ unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
+
+ return hash;
+ }
+ };
+
+ m5::hash_map<int, SQIt, HashFn> SQItHash;
+ std::queue<int> SQIndices;
+ m5::hash_map<int, LQIt, HashFn> LQItHash;
+ std::queue<int> LQIndices;
+
+ typedef typename m5::hash_map<int, LQIt, HashFn>::iterator LQHashIt;
+ typedef typename m5::hash_map<int, SQIt, HashFn>::iterator SQHashIt;
+ // Consider making these 16 bits
+ /** The number of LQ entries. */
+ unsigned LQEntries;
+ /** The number of SQ entries. */
+ unsigned SQEntries;
+
+ /** The number of load instructions in the LQ. */
+ int loads;
+ /** The number of store instructions in the SQ (excludes those waiting to
+ * writeback).
+ */
+ int stores;
+
+ int storesToWB;
+
+ /// @todo Consider moving to a more advanced model with write vs read ports
+ /** The number of cache ports available each cycle. */
+ int cachePorts;
+
+ /** The number of used cache ports in this cycle. */
+ int usedPorts;
+
+ //list<InstSeqNum> mshrSeqNums;
+
+ //Stats::Scalar<> dcacheStallCycles;
+ Counter lastDcacheStall;
+
+ // Make these per thread?
+ /** Whether or not the LSQ is stalled. */
+ bool stalled;
+ /** The store that causes the stall due to partial store to load
+ * forwarding.
+ */
+ InstSeqNum stallingStoreIsn;
+ /** The index of the above store. */
+ LQIt stallingLoad;
+
+ /** Whether or not a load is blocked due to the memory system. It is
+ * cleared when this value is checked via loadBlocked().
+ */
+ bool isLoadBlocked;
+
+ bool loadBlockedHandled;
+
+ InstSeqNum blockedLoadSeqNum;
+
+ /** The oldest faulting load instruction. */
+ DynInstPtr loadFaultInst;
+ /** The oldest faulting store instruction. */
+ DynInstPtr storeFaultInst;
+
+ /** The oldest load that caused a memory ordering violation. */
+ DynInstPtr memDepViolator;
+
+ // Will also need how many read/write ports the Dcache has. Or keep track
+ // of that in stage that is one level up, and only call executeLoad/Store
+ // the appropriate number of times.
+
+ public:
+ /** Executes the load at the given index. */
+ template <class T>
+ Fault read(MemReqPtr &req, T &data, int load_idx);
+
+ /** Executes the store at the given index. */
+ template <class T>
+ Fault write(MemReqPtr &req, T &data, int store_idx);
+
+ /** Returns the sequence number of the head load instruction. */
+ InstSeqNum getLoadHeadSeqNum()
+ {
+ if (!loadQueue.empty()) {
+ return loadQueue.back()->seqNum;
+ } else {
+ return 0;
+ }
+
+ }
+
+ /** Returns the sequence number of the head store instruction. */
+ InstSeqNum getStoreHeadSeqNum()
+ {
+ if (!storeQueue.empty()) {
+ return storeQueue.back().inst->seqNum;
+ } else {
+ return 0;
+ }
+
+ }
+
+ /** Returns whether or not the LSQ unit is stalled. */
+ bool isStalled() { return stalled; }
+};
+
+template <class Impl>
+template <class T>
+Fault
+OzoneLWLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx)
+{
+ //Depending on issue2execute delay a squashed load could
+ //execute if it is found to be squashed in the same
+ //cycle it is scheduled to execute
+ typename m5::hash_map<int, LQIt, HashFn>::iterator
+ lq_hash_it = LQItHash.find(load_idx);
+ assert(lq_hash_it != LQItHash.end());
+ DynInstPtr inst = (*(*lq_hash_it).second);
+
+ if (inst->isExecuted()) {
+ panic("Should not reach this point with split ops!");
+
+ memcpy(&data,req->data,req->size);
+
+ return NoFault;
+ }
+
+ // Make sure this isn't an uncacheable access
+ // A bit of a hackish way to get uncached accesses to work only if they're
+ // at the head of the LSQ and are ready to commit (at the head of the ROB
+ // too).
+ // @todo: Fix uncached accesses.
+ if (req->flags & UNCACHEABLE &&
+ (inst != loadQueue.back() || !inst->reachedCommit)) {
+ DPRINTF(OzoneLSQ, "[sn:%lli] Uncached load and not head of "
+ "commit/LSQ!\n",
+ inst->seqNum);
+ be->rescheduleMemInst(inst);
+ return TheISA::genMachineCheckFault();
+ }
+
+ // Check the SQ for any previous stores that might lead to forwarding
+ SQIt sq_it = storeQueue.begin();
+ int store_size = 0;
+
+ DPRINTF(OzoneLSQ, "Read called, load idx: %i addr: %#x\n",
+ load_idx, req->paddr);
+
+ while (sq_it != storeQueue.end() && (*sq_it).inst->seqNum > inst->seqNum)
+ ++sq_it;
+
+ while (1) {
+ // End once we've reached the top of the LSQ
+ if (sq_it == storeQueue.end()) {
+ break;
+ }
+
+ assert((*sq_it).inst);
+
+ store_size = (*sq_it).size;
+
+ if (store_size == 0) {
+ sq_it++;
+ continue;
+ }
+
+ // Check if the store data is within the lower and upper bounds of
+ // addresses that the request needs.
+ bool store_has_lower_limit =
+ req->vaddr >= (*sq_it).inst->effAddr;
+ bool store_has_upper_limit =
+ (req->vaddr + req->size) <= ((*sq_it).inst->effAddr +
+ store_size);
+ bool lower_load_has_store_part =
+ req->vaddr < ((*sq_it).inst->effAddr +
+ store_size);
+ bool upper_load_has_store_part =
+ (req->vaddr + req->size) > (*sq_it).inst->effAddr;
+
+ // If the store's data has all of the data needed, we can forward.
+ if (store_has_lower_limit && store_has_upper_limit) {
+
+ int shift_amt = req->vaddr & (store_size - 1);
+ // Assumes byte addressing
+ shift_amt = shift_amt << 3;
+
+ // Cast this to type T?
+ data = (*sq_it).data >> shift_amt;
+
+ req->cmd = Read;
+ assert(!req->completionEvent);
+ req->completionEvent = NULL;
+ req->time = curTick;
+ assert(!req->data);
+ req->data = new uint8_t[64];
+
+ memcpy(req->data, &data, req->size);
+
+ DPRINTF(OzoneLSQ, "Forwarding from store [sn:%lli] to load to "
+ "[sn:%lli] addr %#x, data %#x\n",
+ (*sq_it).inst->seqNum, inst->seqNum, req->vaddr, *(req->data));
+
+ typename BackEnd::LdWritebackEvent *wb =
+ new typename BackEnd::LdWritebackEvent(inst,
+ be);
+
+ // We'll say this has a 1 cycle load-store forwarding latency
+ // for now.
+ // FIXME - Need to make this a parameter.
+ wb->schedule(curTick);
+
+ // Should keep track of stat for forwarded data
+ return NoFault;
+ } else if ((store_has_lower_limit && lower_load_has_store_part) ||
+ (store_has_upper_limit && upper_load_has_store_part) ||
+ (lower_load_has_store_part && upper_load_has_store_part)) {
+ // This is the partial store-load forwarding case where a store
+ // has only part of the load's data.
+
+ // If it's already been written back, then don't worry about
+ // stalling on it.
+ if ((*sq_it).completed) {
+ sq_it++;
+ break;
+ }
+
+ // Must stall load and force it to retry, so long as it's the oldest
+ // load that needs to do so.
+ if (!stalled ||
+ (stalled &&
+ inst->seqNum <
+ (*stallingLoad)->seqNum)) {
+ stalled = true;
+ stallingStoreIsn = (*sq_it).inst->seqNum;
+ stallingLoad = (*lq_hash_it).second;
+ }
+
+ // Tell IQ/mem dep unit that this instruction will need to be
+ // rescheduled eventually
+ be->rescheduleMemInst(inst);
+
+ DPRINTF(OzoneLSQ, "Load-store forwarding mis-match. "
+ "Store [sn:%lli] to load addr %#x\n",
+ (*sq_it).inst->seqNum, req->vaddr);
+
+ return NoFault;
+ }
+ sq_it++;
+ }
+
+ // If there's no forwarding case, then go access memory
+ DPRINTF(OzoneLSQ, "Doing functional access for inst PC %#x\n",
+ inst->readPC());
+
+ // Setup MemReq pointer
+ req->cmd = Read;
+ req->completionEvent = NULL;
+ req->time = curTick;
+ assert(!req->data);
+ req->data = new uint8_t[64];
+ Fault fault = cpu->read(req, data);
+ memcpy(req->data, &data, sizeof(T));
+
+ ++usedPorts;
+
+ // if we have a cache, do cache access too
+ if (dcacheInterface) {
+ if (dcacheInterface->isBlocked()) {
+ // There's an older load that's already going to squash.
+ if (isLoadBlocked && blockedLoadSeqNum < inst->seqNum)
+ return NoFault;
+
+ isLoadBlocked = true;
+ loadBlockedHandled = false;
+ blockedLoadSeqNum = inst->seqNum;
+ // No fault occurred, even though the interface is blocked.
+ return NoFault;
+ }
+
+ DPRINTF(OzoneLSQ, "D-cache: PC:%#x reading from paddr:%#x "
+ "vaddr:%#x flags:%i\n",
+ inst->readPC(), req->paddr, req->vaddr, req->flags);
+
+ assert(!req->completionEvent);
+ req->completionEvent =
+ new typename BackEnd::LdWritebackEvent(inst, be);
+
+ // Do Cache Access
+ MemAccessResult result = dcacheInterface->access(req);
+
+ // Ugly hack to get an event scheduled *only* if the access is
+ // a miss. We really should add first-class support for this
+ // at some point.
+ // @todo: Probably should support having no events
+ if (result != MA_HIT) {
+ DPRINTF(OzoneLSQ, "D-cache miss!\n");
+ DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
+ inst->seqNum);
+
+ lastDcacheStall = curTick;
+
+ _status = DcacheMissStall;
+
+ } else {
+ DPRINTF(OzoneLSQ, "D-cache hit!\n");
+ }
+ } else {
+ fatal("Must use D-cache with new memory system");
+ }
+
+ return NoFault;
+}
+
+template <class Impl>
+template <class T>
+Fault
+OzoneLWLSQ<Impl>::write(MemReqPtr &req, T &data, int store_idx)
+{
+ SQHashIt sq_hash_it = SQItHash.find(store_idx);
+ assert(sq_hash_it != SQItHash.end());
+
+ SQIt sq_it = (*sq_hash_it).second;
+ assert((*sq_it).inst);
+
+ DPRINTF(OzoneLSQ, "Doing write to store idx %i, addr %#x data %#x"
+ " | [sn:%lli]\n",
+ store_idx, req->paddr, data, (*sq_it).inst->seqNum);
+
+ (*sq_it).req = req;
+ (*sq_it).size = sizeof(T);
+ (*sq_it).data = data;
+ assert(!req->data);
+ req->data = new uint8_t[64];
+ memcpy(req->data, (uint8_t *)&(*sq_it).data, req->size);
+
+ // This function only writes the data to the store queue, so no fault
+ // can happen here.
+ return NoFault;
+}
+
+#endif // __CPU_OZONE_LW_LSQ_HH__
diff --git a/cpu/ozone/lw_lsq_impl.hh b/cpu/ozone/lw_lsq_impl.hh
new file mode 100644
index 000000000..f72bbb1cc
--- /dev/null
+++ b/cpu/ozone/lw_lsq_impl.hh
@@ -0,0 +1,874 @@
+/*
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/isa_traits.hh"
+#include "base/str.hh"
+#include "cpu/ozone/lw_lsq.hh"
+#include "cpu/checker/cpu.hh"
+
+template <class Impl>
+OzoneLWLSQ<Impl>::StoreCompletionEvent::StoreCompletionEvent(DynInstPtr &_inst,
+ BackEnd *_be,
+ Event *wb_event,
+ OzoneLWLSQ<Impl> *lsq_ptr)
+ : Event(&mainEventQueue),
+ inst(_inst),
+ be(_be),
+ wbEvent(wb_event),
+ miss(false),
+ lsqPtr(lsq_ptr)
+{
+ this->setFlags(Event::AutoDelete);
+}
+
+template <class Impl>
+void
+OzoneLWLSQ<Impl>::StoreCompletionEvent::process()
+{
+ DPRINTF(OzoneLSQ, "Cache miss complete for store [sn:%lli]\n",
+ inst->seqNum);
+
+ //lsqPtr->removeMSHR(lsqPtr->storeQueue[storeIdx].inst->seqNum);
+
+// lsqPtr->cpu->wakeCPU();
+ if (lsqPtr->isSwitchedOut()) {
+ if (wbEvent)
+ delete wbEvent;
+
+ return;
+ }
+
+ if (wbEvent) {
+ wbEvent->process();
+ delete wbEvent;
+ }
+
+ lsqPtr->completeStore(inst->sqIdx);
+ if (miss)
+ be->removeDcacheMiss(inst);
+}
+
+template <class Impl>
+const char *
+OzoneLWLSQ<Impl>::StoreCompletionEvent::description()
+{
+ return "LSQ store completion event";
+}
+
+template <class Impl>
+OzoneLWLSQ<Impl>::OzoneLWLSQ()
+ : loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false),
+ loadBlockedHandled(false)
+{
+}
+
+template<class Impl>
+void
+OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
+ unsigned maxSQEntries, unsigned id)
+{
+ DPRINTF(OzoneLSQ, "Creating OzoneLWLSQ%i object.\n",id);
+
+ lsqID = id;
+
+ LQEntries = maxLQEntries;
+ SQEntries = maxSQEntries;
+
+ for (int i = 0; i < LQEntries * 2; i++) {
+ LQIndices.push(i);
+ SQIndices.push(i);
+ }
+
+ usedPorts = 0;
+ cachePorts = params->cachePorts;
+
+ dcacheInterface = params->dcacheInterface;
+
+ loadFaultInst = storeFaultInst = memDepViolator = NULL;
+
+ blockedLoadSeqNum = 0;
+}
+
+template<class Impl>
+std::string
+OzoneLWLSQ<Impl>::name() const
+{
+ return "lsqunit";
+}
+
+template<class Impl>
+void
+OzoneLWLSQ<Impl>::clearLQ()
+{
+ loadQueue.clear();
+}
+
+template<class Impl>
+void
+OzoneLWLSQ<Impl>::clearSQ()
+{
+ storeQueue.clear();
+}
+/*
+template<class Impl>
+void
+OzoneLWLSQ<Impl>::setPageTable(PageTable *pt_ptr)
+{
+ DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
+ pTable = pt_ptr;
+}
+*/
+template<class Impl>
+void
+OzoneLWLSQ<Impl>::resizeLQ(unsigned size)
+{
+ assert( size >= LQEntries);
+
+ if (size > LQEntries) {
+ while (size > loadQueue.size()) {
+ DynInstPtr dummy;
+ loadQueue.push_back(dummy);
+ LQEntries++;
+ }
+ } else {
+ LQEntries = size;
+ }
+
+}
+
+template<class Impl>
+void
+OzoneLWLSQ<Impl>::resizeSQ(unsigned size)
+{
+ if (size > SQEntries) {
+ while (size > storeQueue.size()) {
+ SQEntry dummy;
+ storeQueue.push_back(dummy);
+ SQEntries++;
+ }
+ } else {
+ SQEntries = size;
+ }
+}
+
+template <class Impl>
+void
+OzoneLWLSQ<Impl>::insert(DynInstPtr &inst)
+{
+ // Make sure we really have a memory reference.
+ assert(inst->isMemRef());
+
+ // Make sure it's one of the two classes of memory references.
+ assert(inst->isLoad() || inst->isStore());
+
+ if (inst->isLoad()) {
+ insertLoad(inst);
+ } else {
+ insertStore(inst);
+ }
+}
+
+template <class Impl>
+void
+OzoneLWLSQ<Impl>::insertLoad(DynInstPtr &load_inst)
+{
+ assert(loads < LQEntries * 2);
+ assert(!LQIndices.empty());
+ int load_index = LQIndices.front();
+ LQIndices.pop();
+
+ DPRINTF(OzoneLSQ, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
+ load_inst->readPC(), load_index, load_inst->seqNum);
+
+ load_inst->lqIdx = load_index;
+
+ loadQueue.push_front(load_inst);
+ LQItHash[load_index] = loadQueue.begin();
+
+ ++loads;
+}
+
+template <class Impl>
+void
+OzoneLWLSQ<Impl>::insertStore(DynInstPtr &store_inst)
+{
+ // Make sure it is not full before inserting an instruction.
+ assert(stores - storesToWB < SQEntries);
+
+ assert(!SQIndices.empty());
+ int store_index = SQIndices.front();
+ SQIndices.pop();
+
+ DPRINTF(OzoneLSQ, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
+ store_inst->readPC(), store_index, store_inst->seqNum);
+
+ store_inst->sqIdx = store_index;
+ SQEntry entry(store_inst);
+ if (loadQueue.empty()) {
+ entry.lqIt = loadQueue.end();
+ } else {
+ entry.lqIt = loadQueue.begin();
+ }
+ storeQueue.push_front(entry);
+
+ SQItHash[store_index] = storeQueue.begin();
+
+ ++stores;
+}
+
+template <class Impl>
+typename Impl::DynInstPtr
+OzoneLWLSQ<Impl>::getMemDepViolator()
+{
+ DynInstPtr temp = memDepViolator;
+
+ memDepViolator = NULL;
+
+ return temp;
+}
+
+template <class Impl>
+unsigned
+OzoneLWLSQ<Impl>::numFreeEntries()
+{
+ unsigned free_lq_entries = LQEntries - loads;
+ unsigned free_sq_entries = SQEntries - stores;
+
+ // Both the LQ and SQ entries have an extra dummy entry to differentiate
+ // empty/full conditions. Subtract 1 from the free entries.
+ if (free_lq_entries < free_sq_entries) {
+ return free_lq_entries - 1;
+ } else {
+ return free_sq_entries - 1;
+ }
+}
+
+template <class Impl>
+int
+OzoneLWLSQ<Impl>::numLoadsReady()
+{
+ int retval = 0;
+ LQIt lq_it = loadQueue.begin();
+ LQIt end_it = loadQueue.end();
+
+ while (lq_it != end_it) {
+ if ((*lq_it)->readyToIssue()) {
+ ++retval;
+ }
+ }
+
+ return retval;
+}
+
+template <class Impl>
+Fault
+OzoneLWLSQ<Impl>::executeLoad(DynInstPtr &inst)
+{
+ // Execute a specific load.
+ Fault load_fault = NoFault;
+
+ DPRINTF(OzoneLSQ, "Executing load PC %#x, [sn:%lli]\n",
+ inst->readPC(),inst->seqNum);
+
+ // Make sure it's really in the list.
+ // Normally it should always be in the list. However,
+ /* due to a syscall it may not be the list.
+#ifdef DEBUG
+ int i = loadHead;
+ while (1) {
+ if (i == loadTail && !find(inst)) {
+ assert(0 && "Load not in the queue!");
+ } else if (loadQueue[i] == inst) {
+ break;
+ }
+
+ i = i + 1;
+ if (i >= LQEntries) {
+ i = 0;
+ }
+ }
+#endif // DEBUG*/
+
+ load_fault = inst->initiateAcc();
+
+ // Might want to make sure that I'm not overwriting a previously faulting
+ // instruction that hasn't been checked yet.
+ // Actually probably want the oldest faulting load
+ if (load_fault != NoFault) {
+ DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum);
+ // Maybe just set it as can commit here, although that might cause
+ // some other problems with sending traps to the ROB too quickly.
+ be->instToCommit(inst);
+// iewStage->activityThisCycle();
+ }
+
+ return load_fault;
+}
+
+template <class Impl>
+Fault
+OzoneLWLSQ<Impl>::executeStore(DynInstPtr &store_inst)
+{
+ // Make sure that a store exists.
+ assert(stores != 0);
+
+ int store_idx = store_inst->sqIdx;
+ SQHashIt sq_hash_it = SQItHash.find(store_idx);
+ assert(sq_hash_it != SQItHash.end());
+ DPRINTF(OzoneLSQ, "Executing store PC %#x [sn:%lli]\n",
+ store_inst->readPC(), store_inst->seqNum);
+
+ SQIt sq_it = (*sq_hash_it).second;
+
+ Fault store_fault = store_inst->initiateAcc();
+
+ // Store size should now be available. Use it to get proper offset for
+ // addr comparisons.
+ int size = (*sq_it).size;
+
+ if (size == 0) {
+ DPRINTF(OzoneLSQ,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
+ store_inst->readPC(),store_inst->seqNum);
+
+ return store_fault;
+ }
+
+ assert(store_fault == NoFault);
+
+ if (!storeFaultInst) {
+ if (store_fault != NoFault) {
+ panic("Fault in a store instruction!");
+ storeFaultInst = store_inst;
+ } else if (store_inst->isStoreConditional()) {
+ // Store conditionals need to set themselves as able to
+ // writeback if we haven't had a fault by here.
+ (*sq_it).canWB = true;
+
+ ++storesToWB;
+ DPRINTF(OzoneLSQ, "Nonspeculative store! storesToWB:%i\n",
+ storesToWB);
+ }
+ }
+
+ LQIt lq_it = --(loadQueue.end());
+
+ if (!memDepViolator) {
+ while (lq_it != loadQueue.end()) {
+ if ((*lq_it)->seqNum < store_inst->seqNum) {
+ lq_it--;
+ continue;
+ }
+ // Actually should only check loads that have actually executed
+ // Might be safe because effAddr is set to InvalAddr when the
+ // dyn inst is created.
+
+ // Must actually check all addrs in the proper size range
+ // Which is more correct than needs to be. What if for now we just
+ // assume all loads are quad-word loads, and do the addr based
+ // on that.
+ // @todo: Fix this, magic number being used here
+ if (((*lq_it)->effAddr >> 8) ==
+ (store_inst->effAddr >> 8)) {
+ // A load incorrectly passed this store. Squash and refetch.
+ // For now return a fault to show that it was unsuccessful.
+ memDepViolator = (*lq_it);
+
+ return TheISA::genMachineCheckFault();
+ }
+
+ lq_it--;
+ }
+
+ // If we've reached this point, there was no violation.
+ memDepViolator = NULL;
+ }
+
+ return store_fault;
+}
+
+template <class Impl>
+void
+OzoneLWLSQ<Impl>::commitLoad()
+{
+ assert(!loadQueue.empty());
+
+ DPRINTF(OzoneLSQ, "[sn:%lli] Committing head load instruction, PC %#x\n",
+ loadQueue.back()->seqNum, loadQueue.back()->readPC());
+
+ LQIndices.push(loadQueue.back()->lqIdx);
+ LQItHash.erase(loadQueue.back()->lqIdx);
+
+ loadQueue.pop_back();
+
+ --loads;
+}
+
+template <class Impl>
+void
+OzoneLWLSQ<Impl>::commitLoads(InstSeqNum &youngest_inst)
+{
+ assert(loads == 0 || !loadQueue.empty());
+
+ while (loads != 0 &&
+ loadQueue.back()->seqNum <= youngest_inst) {
+ commitLoad();
+ }
+}
+
+template <class Impl>
+void
+OzoneLWLSQ<Impl>::commitStores(InstSeqNum &youngest_inst)
+{
+ assert(stores == 0 || !storeQueue.empty());
+
+ SQIt sq_it = --(storeQueue.end());
+ while (!storeQueue.empty() && sq_it != storeQueue.end()) {
+ assert((*sq_it).inst);
+ if (!(*sq_it).canWB) {
+ if ((*sq_it).inst->seqNum > youngest_inst) {
+ break;
+ }
+ ++storesToWB;
+
+ DPRINTF(OzoneLSQ, "Marking store as able to write back, PC "
+ "%#x [sn:%lli], storesToWB:%i\n",
+ (*sq_it).inst->readPC(),
+ (*sq_it).inst->seqNum,
+ storesToWB);
+
+ (*sq_it).canWB = true;
+ }
+
+ sq_it--;
+ }
+}
+
+template <class Impl>
+void
+OzoneLWLSQ<Impl>::writebackStores()
+{
+ SQIt sq_it = --(storeQueue.end());
+ while (storesToWB > 0 &&
+ sq_it != storeQueue.end() &&
+ (*sq_it).inst &&
+ (*sq_it).canWB &&
+ usedPorts < cachePorts) {
+
+ DynInstPtr inst = (*sq_it).inst;
+
+ if ((*sq_it).size == 0 && !(*sq_it).completed) {
+ sq_it--;
+ completeStore(inst->sqIdx);
+
+ continue;
+ }
+
+ if (inst->isDataPrefetch() || (*sq_it).committed) {
+ sq_it--;
+ continue;
+ }
+
+ if (dcacheInterface && dcacheInterface->isBlocked()) {
+ DPRINTF(OzoneLSQ, "Unable to write back any more stores, cache"
+ " is blocked!\n");
+ break;
+ }
+
+ ++usedPorts;
+
+ assert((*sq_it).req);
+ assert(!(*sq_it).committed);
+
+ (*sq_it).committed = true;
+
+ MemReqPtr req = (*sq_it).req;
+
+ req->cmd = Write;
+ req->completionEvent = NULL;
+ req->time = curTick;
+
+ switch((*sq_it).size) {
+ case 1:
+ cpu->write(req, (uint8_t &)(*sq_it).data);
+ break;
+ case 2:
+ cpu->write(req, (uint16_t &)(*sq_it).data);
+ break;
+ case 4:
+ cpu->write(req, (uint32_t &)(*sq_it).data);
+ break;
+ case 8:
+ cpu->write(req, (uint64_t &)(*sq_it).data);
+ break;
+ default:
+ panic("Unexpected store size!\n");
+ }
+ if (!(req->flags & LOCKED)) {
+ (*sq_it).inst->setCompleted();
+ if (cpu->checker) {
+ cpu->checker->tick((*sq_it).inst);
+ }
+ }
+
+ DPRINTF(OzoneLSQ, "D-Cache: Writing back store idx:%i PC:%#x "
+ "to Addr:%#x, data:%#x [sn:%lli]\n",
+ inst->sqIdx,inst->readPC(),
+ req->paddr, *(req->data),
+ inst->seqNum);
+
+ if (dcacheInterface) {
+ assert(!req->completionEvent);
+ StoreCompletionEvent *store_event = new
+ StoreCompletionEvent(inst, be, NULL, this);
+ req->completionEvent = store_event;
+
+ MemAccessResult result = dcacheInterface->access(req);
+
+ if (isStalled() &&
+ inst->seqNum == stallingStoreIsn) {
+ DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
+ "load [sn:%lli]\n",
+ stallingStoreIsn, (*stallingLoad)->seqNum);
+ stalled = false;
+ stallingStoreIsn = 0;
+ be->replayMemInst((*stallingLoad));
+ }
+
+ if (result != MA_HIT && dcacheInterface->doEvents()) {
+ store_event->miss = true;
+ typename BackEnd::LdWritebackEvent *wb = NULL;
+ if (req->flags & LOCKED) {
+ wb = new typename BackEnd::LdWritebackEvent(inst,
+ be);
+ store_event->wbEvent = wb;
+ }
+
+ DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
+
+// DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
+// inst->seqNum);
+
+ be->addDcacheMiss(inst);
+
+ lastDcacheStall = curTick;
+
+ _status = DcacheMissStall;
+
+ // Increment stat here or something
+
+ sq_it--;
+ } else {
+ DPRINTF(OzoneLSQ,"D-Cache: Write Hit on idx:%i !\n",
+ inst->sqIdx);
+
+// DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
+// inst->seqNum);
+
+ if (req->flags & LOCKED) {
+ // Stx_C does not generate a system port
+ // transaction in the 21264, but that might be
+ // hard to accomplish in this model.
+
+ typename BackEnd::LdWritebackEvent *wb =
+ new typename BackEnd::LdWritebackEvent(inst,
+ be);
+ store_event->wbEvent = wb;
+ }
+ sq_it--;
+ }
+ } else {
+ panic("Must HAVE DCACHE!!!!!\n");
+ }
+ }
+
+ // Not sure this should set it to 0.
+ usedPorts = 0;
+
+ assert(stores >= 0 && storesToWB >= 0);
+}
+
+template <class Impl>
+void
+OzoneLWLSQ<Impl>::squash(const InstSeqNum &squashed_num)
+{
+ DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
+ "(Loads:%i Stores:%i)\n",squashed_num,loads,stores);
+
+
+ LQIt lq_it = loadQueue.begin();
+
+ while (loads != 0 && (*lq_it)->seqNum > squashed_num) {
+ assert(!loadQueue.empty());
+ // Clear the smart pointer to make sure it is decremented.
+ DPRINTF(OzoneLSQ,"Load Instruction PC %#x squashed, "
+ "[sn:%lli]\n",
+ (*lq_it)->readPC(),
+ (*lq_it)->seqNum);
+
+ if (isStalled() && lq_it == stallingLoad) {
+ stalled = false;
+ stallingStoreIsn = 0;
+ stallingLoad = NULL;
+ }
+
+ --loads;
+
+ // Inefficient!
+ LQHashIt lq_hash_it = LQItHash.find((*lq_it)->lqIdx);
+ assert(lq_hash_it != LQItHash.end());
+ LQItHash.erase(lq_hash_it);
+ LQIndices.push((*lq_it)->lqIdx);
+ loadQueue.erase(lq_it++);
+ }
+
+ if (isLoadBlocked) {
+ if (squashed_num < blockedLoadSeqNum) {
+ isLoadBlocked = false;
+ loadBlockedHandled = false;
+ blockedLoadSeqNum = 0;
+ }
+ }
+
+ SQIt sq_it = storeQueue.begin();
+
+ while (stores != 0 && (*sq_it).inst->seqNum > squashed_num) {
+ assert(!storeQueue.empty());
+
+ if ((*sq_it).canWB) {
+ break;
+ }
+
+ // Clear the smart pointer to make sure it is decremented.
+ DPRINTF(OzoneLSQ,"Store Instruction PC %#x idx:%i squashed [sn:%lli]\n",
+ (*sq_it).inst->readPC(), (*sq_it).inst->sqIdx,
+ (*sq_it).inst->seqNum);
+
+ // I don't think this can happen. It should have been cleared by the
+ // stalling load.
+ if (isStalled() &&
+ (*sq_it).inst->seqNum == stallingStoreIsn) {
+ panic("Is stalled should have been cleared by stalling load!\n");
+ stalled = false;
+ stallingStoreIsn = 0;
+ }
+
+ SQHashIt sq_hash_it = SQItHash.find((*sq_it).inst->sqIdx);
+ assert(sq_hash_it != SQItHash.end());
+ SQItHash.erase(sq_hash_it);
+ SQIndices.push((*sq_it).inst->sqIdx);
+ (*sq_it).inst = NULL;
+ (*sq_it).canWB = 0;
+
+ if ((*sq_it).req) {
+ assert(!(*sq_it).req->completionEvent);
+ }
+ (*sq_it).req = NULL;
+ --stores;
+ storeQueue.erase(sq_it++);
+ }
+}
+
+template <class Impl>
+void
+OzoneLWLSQ<Impl>::dumpInsts()
+{
+ cprintf("Load store queue: Dumping instructions.\n");
+ cprintf("Load queue size: %i\n", loads);
+ cprintf("Load queue: ");
+
+ LQIt lq_it = --(loadQueue.end());
+
+ while (lq_it != loadQueue.end() && (*lq_it)) {
+ cprintf("[sn:%lli] %#x ", (*lq_it)->seqNum,
+ (*lq_it)->readPC());
+
+ lq_it--;
+ }
+
+ cprintf("\nStore queue size: %i\n", stores);
+ cprintf("Store queue: ");
+
+ SQIt sq_it = --(storeQueue.end());
+
+ while (sq_it != storeQueue.end() && (*sq_it).inst) {
+ cprintf("[sn:%lli]\nPC:%#x\nSize:%i\nCommitted:%i\nCompleted:%i\ncanWB:%i\n",
+ (*sq_it).inst->seqNum,
+ (*sq_it).inst->readPC(),
+ (*sq_it).size,
+ (*sq_it).committed,
+ (*sq_it).completed,
+ (*sq_it).canWB);
+
+ sq_it--;
+ }
+
+ cprintf("\n");
+}
+
+template <class Impl>
+void
+OzoneLWLSQ<Impl>::completeStore(int store_idx)
+{
+ SQHashIt sq_hash_it = SQItHash.find(store_idx);
+ assert(sq_hash_it != SQItHash.end());
+ SQIt sq_it = (*sq_hash_it).second;
+
+ assert((*sq_it).inst);
+ (*sq_it).completed = true;
+ DynInstPtr inst = (*sq_it).inst;
+
+ --storesToWB;
+
+ if (isStalled() &&
+ inst->seqNum == stallingStoreIsn) {
+ DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
+ "load [sn:%lli]\n",
+ stallingStoreIsn, (*stallingLoad)->seqNum);
+ stalled = false;
+ stallingStoreIsn = 0;
+ be->replayMemInst((*stallingLoad));
+ }
+
+ DPRINTF(OzoneLSQ, "Completing store idx:%i [sn:%lli], storesToWB:%i\n",
+ inst->sqIdx, inst->seqNum, storesToWB);
+
+ assert(!storeQueue.empty());
+ SQItHash.erase(sq_hash_it);
+ SQIndices.push(inst->sqIdx);
+ storeQueue.erase(sq_it);
+ --stores;
+
+ inst->setCompleted();
+ if (cpu->checker) {
+ cpu->checker->tick(inst);
+ }
+}
+
+template <class Impl>
+void
+OzoneLWLSQ<Impl>::switchOut()
+{
+ assert(storesToWB == 0);
+ switchedOut = true;
+ SQIt sq_it = --(storeQueue.end());
+ while (storesToWB > 0 &&
+ sq_it != storeQueue.end() &&
+ (*sq_it).inst &&
+ (*sq_it).canWB) {
+
+ DynInstPtr inst = (*sq_it).inst;
+
+ if ((*sq_it).size == 0 && !(*sq_it).completed) {
+ sq_it--;
+ continue;
+ }
+
+ // Store conditionals don't complete until *after* they have written
+ // back. If it's here and not yet sent to memory, then don't bother
+ // as it's not part of committed state.
+ if (inst->isDataPrefetch() || (*sq_it).committed) {
+ sq_it--;
+ continue;
+ } else if ((*sq_it).req->flags & LOCKED) {
+ sq_it--;
+ assert(!(*sq_it).canWB ||
+ ((*sq_it).canWB && (*sq_it).req->flags & LOCKED));
+ continue;
+ }
+
+ assert((*sq_it).req);
+ assert(!(*sq_it).committed);
+
+ MemReqPtr req = (*sq_it).req;
+ (*sq_it).committed = true;
+
+ req->cmd = Write;
+ req->completionEvent = NULL;
+ req->time = curTick;
+ assert(!req->data);
+ req->data = new uint8_t[64];
+ memcpy(req->data, (uint8_t *)&(*sq_it).data, req->size);
+
+ DPRINTF(OzoneLSQ, "Switching out : Writing back store idx:%i PC:%#x "
+ "to Addr:%#x, data:%#x directly to memory [sn:%lli]\n",
+ inst->sqIdx,inst->readPC(),
+ req->paddr, *(req->data),
+ inst->seqNum);
+
+ switch((*sq_it).size) {
+ case 1:
+ cpu->write(req, (uint8_t &)(*sq_it).data);
+ break;
+ case 2:
+ cpu->write(req, (uint16_t &)(*sq_it).data);
+ break;
+ case 4:
+ cpu->write(req, (uint32_t &)(*sq_it).data);
+ break;
+ case 8:
+ cpu->write(req, (uint64_t &)(*sq_it).data);
+ break;
+ default:
+ panic("Unexpected store size!\n");
+ }
+ }
+
+ // Clear the queue to free up resources
+ storeQueue.clear();
+ loadQueue.clear();
+ loads = stores = storesToWB = 0;
+}
+
+template <class Impl>
+void
+OzoneLWLSQ<Impl>::takeOverFrom(ExecContext *old_xc)
+{
+ // Clear out any old state. May be redundant if this is the first time
+ // the CPU is being used.
+ stalled = false;
+ isLoadBlocked = false;
+ loadBlockedHandled = false;
+ switchedOut = false;
+
+ // Could do simple checks here to see if indices are on twice
+ while (!LQIndices.empty())
+ LQIndices.pop();
+ while (!SQIndices.empty())
+ SQIndices.pop();
+
+ for (int i = 0; i < LQEntries * 2; i++) {
+ LQIndices.push(i);
+ SQIndices.push(i);
+ }
+
+ usedPorts = 0;
+
+ loadFaultInst = storeFaultInst = memDepViolator = NULL;
+
+ blockedLoadSeqNum = 0;
+}
diff --git a/cpu/ozone/null_predictor.hh b/cpu/ozone/null_predictor.hh
new file mode 100644
index 000000000..d19e2cd1c
--- /dev/null
+++ b/cpu/ozone/null_predictor.hh
@@ -0,0 +1,76 @@
+
+#ifndef __CPU_OZONE_NULL_PREDICTOR_HH__
+#define __CPU_OZONE_NULL_PREDICTOR_HH__
+
+#include "arch/isa_traits.hh"
+#include "cpu/inst_seq.hh"
+
+template <class Impl>
+class NullPredictor
+{
+ public:
+ typedef typename Impl::Params Params;
+ typedef typename Impl::DynInstPtr DynInstPtr;
+
+ NullPredictor(Params *p) { }
+
+ struct BPredInfo {
+ BPredInfo()
+ : PC(0), nextPC(0)
+ { }
+
+ BPredInfo(const Addr &pc, const Addr &next_pc)
+ : PC(pc), nextPC(next_pc)
+ { }
+
+ Addr PC;
+ Addr nextPC;
+ };
+
+ BPredInfo lookup(Addr &PC) { return BPredInfo(PC, PC+4); }
+
+ void undo(BPredInfo &bp_info) { return; }
+
+ /**
+ * Predicts whether or not the instruction is a taken branch, and the
+ * target of the branch if it is taken.
+ * @param inst The branch instruction.
+ * @param PC The predicted PC is passed back through this parameter.
+ * @param tid The thread id.
+ * @return Returns if the branch is taken or not.
+ */
+ bool predict(DynInstPtr &inst, Addr &PC, unsigned tid)
+ { return false; }
+
+ /**
+ * Tells the branch predictor to commit any updates until the given
+ * sequence number.
+ * @param done_sn The sequence number to commit any older updates up until.
+ * @param tid The thread id.
+ */
+ void update(const InstSeqNum &done_sn, unsigned tid) { }
+
+ /**
+ * Squashes all outstanding updates until a given sequence number.
+ * @param squashed_sn The sequence number to squash any younger updates up
+ * until.
+ * @param tid The thread id.
+ */
+ void squash(const InstSeqNum &squashed_sn, unsigned tid) { }
+
+ /**
+ * Squashes all outstanding updates until a given sequence number, and
+ * corrects that sn's update with the proper address and taken/not taken.
+ * @param squashed_sn The sequence number to squash any younger updates up
+ * until.
+ * @param corr_target The correct branch target.
+ * @param actually_taken The correct branch direction.
+ * @param tid The thread id.
+ */
+ void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
+ bool actually_taken, unsigned tid)
+ { }
+
+};
+
+#endif // __CPU_OZONE_NULL_PREDICTOR_HH__
diff --git a/cpu/ozone/ozone_impl.hh b/cpu/ozone/ozone_impl.hh
new file mode 100644
index 000000000..1f543ec6e
--- /dev/null
+++ b/cpu/ozone/ozone_impl.hh
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_OZONE_OZONE_IMPL_HH__
+#define __CPU_OZONE_OZONE_IMPL_HH__
+
+#include "arch/alpha/isa_traits.hh"
+#include "cpu/o3/bpred_unit.hh"
+#include "cpu/ozone/back_end.hh"
+#include "cpu/ozone/front_end.hh"
+#include "cpu/ozone/inst_queue.hh"
+#include "cpu/ozone/lsq_unit.hh"
+#include "cpu/ozone/lw_lsq.hh"
+#include "cpu/ozone/lw_back_end.hh"
+#include "cpu/ozone/null_predictor.hh"
+#include "cpu/ozone/dyn_inst.hh"
+#include "cpu/ozone/simple_params.hh"
+
+template <class Impl>
+class OzoneCPU;
+
+template <class Impl>
+class OzoneDynInst;
+
+struct OzoneImpl {
+ typedef SimpleParams Params;
+ typedef OzoneCPU<OzoneImpl> OzoneCPU;
+ typedef OzoneCPU FullCPU;
+
+ // Would like to put these into their own area.
+// typedef NullPredictor BranchPred;
+ typedef TwobitBPredUnit<OzoneImpl> BranchPred;
+ typedef FrontEnd<OzoneImpl> FrontEnd;
+ // Will need IQ, LSQ eventually
+ typedef LWBackEnd<OzoneImpl> BackEnd;
+
+ typedef InstQueue<OzoneImpl> InstQueue;
+ typedef OzoneLWLSQ<OzoneImpl> LdstQueue;
+
+ typedef OzoneDynInst<OzoneImpl> DynInst;
+ typedef RefCountingPtr<DynInst> DynInstPtr;
+
+ typedef uint64_t IssueStruct;
+
+ enum {
+ MaxThreads = 1
+ };
+};
+
+#endif // __CPU_OZONE_OZONE_IMPL_HH__
diff --git a/cpu/ozone/rename_table.cc b/cpu/ozone/rename_table.cc
new file mode 100644
index 000000000..fff41903e
--- /dev/null
+++ b/cpu/ozone/rename_table.cc
@@ -0,0 +1,7 @@
+
+#include "cpu/ozone/rename_table_impl.hh"
+#include "cpu/ozone/ozone_impl.hh"
+#include "cpu/ozone/simple_impl.hh"
+
+template class RenameTable<OzoneImpl>;
+template class RenameTable<SimpleImpl>;
diff --git a/cpu/ozone/rename_table.hh b/cpu/ozone/rename_table.hh
new file mode 100644
index 000000000..6ee23b21b
--- /dev/null
+++ b/cpu/ozone/rename_table.hh
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_OZONE_RENAME_TABLE_HH__
+#define __CPU_OZONE_RENAME_TABLE_HH__
+
+#include "arch/isa_traits.hh"
+
+/** Rename table that holds the rename of each architectural register to
+ * producing DynInst. Needs to support copying from one table to another.
+ */
+
+template <class Impl>
+class RenameTable {
+ public:
+ typedef typename Impl::DynInstPtr DynInstPtr;
+
+ RenameTable();
+
+ void copyFrom(const RenameTable<Impl> &table_to_copy);
+
+ DynInstPtr &operator [] (int index)
+ { return table[index]; }
+
+ DynInstPtr table[TheISA::TotalNumRegs];
+};
+
+#endif // __CPU_OZONE_RENAME_TABLE_HH__
diff --git a/cpu/ozone/rename_table_impl.hh b/cpu/ozone/rename_table_impl.hh
new file mode 100644
index 000000000..86fc1cc55
--- /dev/null
+++ b/cpu/ozone/rename_table_impl.hh
@@ -0,0 +1,23 @@
+
+#include <cstdlib> // Not really sure what to include to get NULL
+#include "cpu/ozone/rename_table.hh"
+
+template <class Impl>
+RenameTable<Impl>::RenameTable()
+{
+ // Actually should set these to dummy dyn insts that have the initial value
+ // and force their values to be initialized. This keeps everything the
+ // same.
+ for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
+ table[i] = NULL;
+ }
+}
+
+template <class Impl>
+void
+RenameTable<Impl>::copyFrom(const RenameTable<Impl> &table_to_copy)
+{
+ for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
+ table[i] = table_to_copy.table[i];
+ }
+}
diff --git a/cpu/ozone/simple_impl.hh b/cpu/ozone/simple_impl.hh
new file mode 100644
index 000000000..961bf2ea9
--- /dev/null
+++ b/cpu/ozone/simple_impl.hh
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_OZONE_SIMPLE_IMPL_HH__
+#define __CPU_OZONE_SIMPLE_IMPL_HH__
+
+#include "arch/isa_traits.hh"
+#include "cpu/o3/bpred_unit.hh"
+#include "cpu/ozone/cpu.hh"
+#include "cpu/ozone/front_end.hh"
+#include "cpu/ozone/inorder_back_end.hh"
+#include "cpu/ozone/null_predictor.hh"
+#include "cpu/ozone/dyn_inst.hh"
+#include "cpu/ozone/simple_params.hh"
+
+//template <class Impl>
+//class OzoneCPU;
+
+template <class Impl>
+class OzoneDynInst;
+
+struct SimpleImpl {
+ typedef SimpleParams Params;
+ typedef OzoneCPU<SimpleImpl> OzoneCPU;
+ typedef OzoneCPU FullCPU;
+
+ // Would like to put these into their own area.
+// typedef NullPredictor BranchPred;
+ typedef TwobitBPredUnit<SimpleImpl> BranchPred;
+ typedef FrontEnd<SimpleImpl> FrontEnd;
+ // Will need IQ, LSQ eventually
+ typedef InorderBackEnd<SimpleImpl> BackEnd;
+
+ typedef OzoneDynInst<SimpleImpl> DynInst;
+ typedef RefCountingPtr<DynInst> DynInstPtr;
+
+ typedef uint64_t IssueStruct;
+
+ enum {
+ MaxThreads = 1
+ };
+};
+
+#endif // __CPU_OZONE_SIMPLE_IMPL_HH__
diff --git a/cpu/ozone/simple_params.hh b/cpu/ozone/simple_params.hh
new file mode 100644
index 000000000..647da1781
--- /dev/null
+++ b/cpu/ozone/simple_params.hh
@@ -0,0 +1,165 @@
+
+
+#ifndef __CPU_OZONE_SIMPLE_PARAMS_HH__
+#define __CPU_OZONE_SIMPLE_PARAMS_HH__
+
+#include "cpu/ozone/cpu.hh"
+
+//Forward declarations
+class AlphaDTB;
+class AlphaITB;
+class FUPool;
+class FunctionalMemory;
+class MemInterface;
+class PageTable;
+class Process;
+class System;
+
+/**
+ * This file defines the parameters that will be used for the OzoneCPU.
+ * This must be defined externally so that the Impl can have a params class
+ * defined that it can pass to all of the individual stages.
+ */
+
+class SimpleParams : public BaseCPU::Params
+{
+ public:
+
+#if FULL_SYSTEM
+ AlphaITB *itb; AlphaDTB *dtb;
+#else
+ std::vector<Process *> workload;
+// Process *process;
+#endif // FULL_SYSTEM
+
+ //Page Table
+ PageTable *pTable;
+
+ FunctionalMemory *mem;
+
+ //
+ // Caches
+ //
+ MemInterface *icacheInterface;
+ MemInterface *dcacheInterface;
+
+ unsigned cachePorts;
+ unsigned width;
+ unsigned frontEndWidth;
+ unsigned backEndWidth;
+ unsigned backEndSquashLatency;
+ unsigned backEndLatency;
+ unsigned maxInstBufferSize;
+ unsigned numPhysicalRegs;
+ unsigned maxOutstandingMemOps;
+ //
+ // Fetch
+ //
+ unsigned decodeToFetchDelay;
+ unsigned renameToFetchDelay;
+ unsigned iewToFetchDelay;
+ unsigned commitToFetchDelay;
+ unsigned fetchWidth;
+
+ //
+ // Decode
+ //
+ unsigned renameToDecodeDelay;
+ unsigned iewToDecodeDelay;
+ unsigned commitToDecodeDelay;
+ unsigned fetchToDecodeDelay;
+ unsigned decodeWidth;
+
+ //
+ // Rename
+ //
+ unsigned iewToRenameDelay;
+ unsigned commitToRenameDelay;
+ unsigned decodeToRenameDelay;
+ unsigned renameWidth;
+
+ //
+ // IEW
+ //
+ unsigned commitToIEWDelay;
+ unsigned renameToIEWDelay;
+ unsigned issueToExecuteDelay;
+ unsigned issueWidth;
+ unsigned executeWidth;
+ unsigned executeIntWidth;
+ unsigned executeFloatWidth;
+ unsigned executeBranchWidth;
+ unsigned executeMemoryWidth;
+ FUPool *fuPool;
+
+ //
+ // Commit
+ //
+ unsigned iewToCommitDelay;
+ unsigned renameToROBDelay;
+ unsigned commitWidth;
+ unsigned squashWidth;
+
+ //
+ // Branch predictor (BP & BTB)
+ //
+ unsigned localPredictorSize;
+ unsigned localCtrBits;
+ unsigned localHistoryTableSize;
+ unsigned localHistoryBits;
+ unsigned globalPredictorSize;
+ unsigned globalCtrBits;
+ unsigned globalHistoryBits;
+ unsigned choicePredictorSize;
+ unsigned choiceCtrBits;
+
+ unsigned BTBEntries;
+ unsigned BTBTagSize;
+
+ unsigned RASSize;
+
+ //
+ // Load store queue
+ //
+ unsigned LQEntries;
+ unsigned SQEntries;
+
+ //
+ // Memory dependence
+ //
+ unsigned SSITSize;
+ unsigned LFSTSize;
+
+ //
+ // Miscellaneous
+ //
+ unsigned numPhysIntRegs;
+ unsigned numPhysFloatRegs;
+ unsigned numIQEntries;
+ unsigned numROBEntries;
+
+ bool decoupledFrontEnd;
+ int dispatchWidth;
+ int wbWidth;
+
+ //SMT Parameters
+ unsigned smtNumFetchingThreads;
+
+ std::string smtFetchPolicy;
+
+ std::string smtIQPolicy;
+ unsigned smtIQThreshold;
+
+ std::string smtLSQPolicy;
+ unsigned smtLSQThreshold;
+
+ std::string smtCommitPolicy;
+
+ std::string smtROBPolicy;
+ unsigned smtROBThreshold;
+
+ // Probably can get this from somewhere.
+ unsigned instShiftAmt;
+};
+
+#endif // __CPU_OZONE_SIMPLE_PARAMS_HH__
diff --git a/cpu/ozone/thread_state.hh b/cpu/ozone/thread_state.hh
new file mode 100644
index 000000000..c86c3a720
--- /dev/null
+++ b/cpu/ozone/thread_state.hh
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_OZONE_THREAD_STATE_HH__
+#define __CPU_OZONE_THREAD_STATE_HH__
+
+#include "arch/faults.hh"
+#include "arch/isa_traits.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/thread_state.hh"
+#include "sim/process.hh"
+
+class Event;
+//class Process;
+
+#if FULL_SYSTEM
+class EndQuiesceEvent;
+class FunctionProfile;
+class ProfileNode;
+#else
+class Process;
+class FunctionalMemory;
+#endif
+
+// Maybe this ozone thread state should only really have committed state?
+// I need to think about why I'm using this and what it's useful for. Clearly
+// has benefits for SMT; basically serves same use as CPUExecContext.
+// Makes the ExecContext proxy easier. Gives organization/central access point
+// to state of a thread that can be accessed normally (i.e. not in-flight
+// stuff within a OoO processor). Does this need an XC proxy within it?
+template <class Impl>
+struct OzoneThreadState : public ThreadState {
+ typedef typename ExecContext::Status Status;
+ typedef typename Impl::FullCPU FullCPU;
+ typedef TheISA::MiscReg MiscReg;
+
+#if FULL_SYSTEM
+ OzoneThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem)
+ : ThreadState(-1, _thread_num, _mem),
+ inSyscall(0), trapPending(0)
+ {
+ memset(&regs, 0, sizeof(TheISA::RegFile));
+ }
+#else
+ OzoneThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid)
+ : ThreadState(-1, _thread_num, _process->getMemory(), _process, _asid),
+ cpu(_cpu), inSyscall(0), trapPending(0)
+ {
+ memset(&regs, 0, sizeof(TheISA::RegFile));
+ }
+
+ OzoneThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
+ int _asid)
+ : ThreadState(-1, _thread_num, _mem, NULL, _asid),
+ cpu(_cpu), inSyscall(0), trapPending(0)
+ {
+ memset(&regs, 0, sizeof(TheISA::RegFile));
+ }
+#endif
+
+ Status _status;
+
+ Status status() const { return _status; }
+
+ void setStatus(Status new_status) { _status = new_status; }
+
+ RenameTable<Impl> renameTable;
+ Addr PC;
+ Addr nextPC;
+
+ // Current instruction
+ TheISA::MachInst inst;
+
+ TheISA::RegFile regs;
+
+ typename Impl::FullCPU *cpu;
+
+ bool inSyscall;
+
+ bool trapPending;
+
+ ExecContext *xcProxy;
+
+ ExecContext *getXCProxy() { return xcProxy; }
+
+#if !FULL_SYSTEM
+
+ Fault dummyTranslation(MemReqPtr &req)
+ {
+#if 0
+ assert((req->vaddr >> 48 & 0xffff) == 0);
+#endif
+
+ // put the asid in the upper 16 bits of the paddr
+ req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
+ req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
+ return NoFault;
+ }
+ Fault translateInstReq(MemReqPtr &req)
+ {
+ return dummyTranslation(req);
+ }
+ Fault translateDataReadReq(MemReqPtr &req)
+ {
+ return dummyTranslation(req);
+ }
+ Fault translateDataWriteReq(MemReqPtr &req)
+ {
+ return dummyTranslation(req);
+ }
+#else
+ Fault translateInstReq(MemReqPtr &req)
+ {
+ return cpu->itb->translate(req);
+ }
+
+ Fault translateDataReadReq(MemReqPtr &req)
+ {
+ return cpu->dtb->translate(req, false);
+ }
+
+ Fault translateDataWriteReq(MemReqPtr &req)
+ {
+ return cpu->dtb->translate(req, true);
+ }
+#endif
+
+ MiscReg readMiscReg(int misc_reg)
+ {
+ return regs.miscRegs.readReg(misc_reg);
+ }
+
+ MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+ {
+ return regs.miscRegs.readRegWithEffect(misc_reg, fault, xcProxy);
+ }
+
+ Fault setMiscReg(int misc_reg, const MiscReg &val)
+ {
+ return regs.miscRegs.setReg(misc_reg, val);
+ }
+
+ Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+ {
+ return regs.miscRegs.setRegWithEffect(misc_reg, val, xcProxy);
+ }
+
+ uint64_t readPC()
+ { return PC; }
+
+ void setPC(uint64_t val)
+ { PC = val; }
+
+ uint64_t readNextPC()
+ { return nextPC; }
+
+ void setNextPC(uint64_t val)
+ { nextPC = val; }
+
+ bool misspeculating() { return false; }
+
+ void setInst(TheISA::MachInst _inst) { inst = _inst; }
+
+ Counter readFuncExeInst() { return funcExeInst; }
+
+ void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
+};
+
+#endif // __CPU_OZONE_THREAD_STATE_HH__
diff --git a/cpu/quiesce_event.cc b/cpu/quiesce_event.cc
new file mode 100644
index 000000000..37814ae09
--- /dev/null
+++ b/cpu/quiesce_event.cc
@@ -0,0 +1,20 @@
+
+#include "cpu/exec_context.hh"
+#include "cpu/quiesce_event.hh"
+
+EndQuiesceEvent::EndQuiesceEvent(ExecContext *_xc)
+ : Event(&mainEventQueue), xc(_xc)
+{
+}
+
+void
+EndQuiesceEvent::process()
+{
+ xc->activate();
+}
+
+const char*
+EndQuiesceEvent::description()
+{
+ return "End Quiesce Event.";
+}
diff --git a/cpu/quiesce_event.hh b/cpu/quiesce_event.hh
new file mode 100644
index 000000000..18e88ecce
--- /dev/null
+++ b/cpu/quiesce_event.hh
@@ -0,0 +1,23 @@
+#ifndef __CPU_QUIESCE_EVENT_HH__
+#define __CPU_QUIESCE_EVENT_HH__
+
+#include "sim/eventq.hh"
+
+class ExecContext;
+
+/** Event for timing out quiesce instruction */
+struct EndQuiesceEvent : public Event
+{
+ /** A pointer to the execution context that is quiesced */
+ ExecContext *xc;
+
+ EndQuiesceEvent(ExecContext *_xc);
+
+ /** Event process to occur at interrupt*/
+ virtual void process();
+
+ /** Event description */
+ virtual const char *description();
+};
+
+#endif // __CPU_QUIESCE_EVENT_HH__
diff --git a/cpu/thread_state.hh b/cpu/thread_state.hh
new file mode 100644
index 000000000..e09cb12fd
--- /dev/null
+++ b/cpu/thread_state.hh
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_THREAD_STATE_HH__
+#define __CPU_THREAD_STATE_HH__
+
+#include "cpu/exec_context.hh"
+
+#if FULL_SYSTEM
+class EndQuiesceEvent;
+class FunctionProfile;
+class ProfileNode;
+namespace Kernel {
+ class Statistics;
+};
+#else
+class FunctionalMemory;
+class Process;
+#endif
+
+/**
+ * Struct for holding general thread state that is needed across CPU
+ * models. This includes things such as pointers to the process,
+ * memory, quiesce events, and certain stats. This can be expanded
+ * to hold more thread-specific stats within it.
+ */
+struct ThreadState {
+#if FULL_SYSTEM
+ ThreadState(int _cpuId, int _tid, FunctionalMemory *_mem)
+ : cpuId(_cpuId), tid(_tid), mem(_mem), lastActivate(0), lastSuspend(0),
+ profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL)
+#else
+ ThreadState(int _cpuId, int _tid, FunctionalMemory *_mem,
+ Process *_process, short _asid)
+ : cpuId(_cpuId), tid(_tid), mem(_mem), process(_process), asid(_asid)
+#endif
+ {
+ funcExeInst = 0;
+ storeCondFailures = 0;
+ }
+
+ ExecContext::Status status;
+
+ int cpuId;
+
+ // Index of hardware thread context on the CPU that this represents.
+ int tid;
+
+ Counter numInst;
+ Stats::Scalar<> numInsts;
+ Stats::Scalar<> numMemRefs;
+
+ // number of simulated loads
+ Counter numLoad;
+ Counter startNumLoad;
+
+ FunctionalMemory *mem; // functional storage for process address space
+
+#if FULL_SYSTEM
+ Tick lastActivate;
+ Tick lastSuspend;
+
+ FunctionProfile *profile;
+ ProfileNode *profileNode;
+ Addr profilePC;
+
+ EndQuiesceEvent *quiesceEvent;
+
+ Kernel::Statistics *kernelStats;
+#else
+ Process *process;
+
+ // Address space ID. Note that this is used for TIMING cache
+ // simulation only; all functional memory accesses should use
+ // one of the FunctionalMemory pointers above.
+ short asid;
+
+#endif
+
+ /**
+ * Temporary storage to pass the source address from copy_load to
+ * copy_store.
+ * @todo Remove this temporary when we have a better way to do it.
+ */
+ Addr copySrcAddr;
+ /**
+ * Temp storage for the physical source address of a copy.
+ * @todo Remove this temporary when we have a better way to do it.
+ */
+ Addr copySrcPhysAddr;
+
+ /*
+ * number of executed instructions, for matching with syscall trace
+ * points in EIO files.
+ */
+ Counter funcExeInst;
+
+ //
+ // Count failed store conditionals so we can warn of apparent
+ // application deadlock situations.
+ unsigned storeCondFailures;
+};
+
+#endif // __CPU_THREAD_STATE_HH__
diff --git a/python/m5/objects/FUPool.py b/python/m5/objects/FUPool.py
new file mode 100644
index 000000000..5eecfd12f
--- /dev/null
+++ b/python/m5/objects/FUPool.py
@@ -0,0 +1,8 @@
+from m5 import *
+from FullCPU import OpType
+from FullCPU import OpDesc
+from FullCPU import FUDesc
+
+class FUPool(SimObject):
+ type = 'FUPool'
+ FUList = VectorParam.FUDesc("list of FU's for this pool")
diff --git a/python/m5/objects/OzoneCPU.py b/python/m5/objects/OzoneCPU.py
new file mode 100644
index 000000000..3fca61e28
--- /dev/null
+++ b/python/m5/objects/OzoneCPU.py
@@ -0,0 +1,89 @@
+from m5 import *
+from BaseCPU import BaseCPU
+
+class DerivOzoneCPU(BaseCPU):
+ type = 'DerivOzoneCPU'
+
+ numThreads = Param.Unsigned("number of HW thread contexts")
+
+ if not build_env['FULL_SYSTEM']:
+ mem = Param.FunctionalMemory(NULL, "memory")
+
+ checker = Param.BaseCPU("Checker CPU")
+
+ width = Param.Unsigned("Width")
+ frontEndWidth = Param.Unsigned("Front end width")
+ backEndWidth = Param.Unsigned("Back end width")
+ backEndSquashLatency = Param.Unsigned("Back end squash latency")
+ backEndLatency = Param.Unsigned("Back end latency")
+ maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size")
+ maxOutstandingMemOps = Param.Unsigned("Maximum number of outstanding memory operations")
+ decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
+ renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
+ iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
+ "delay")
+ commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
+ fetchWidth = Param.Unsigned("Fetch width")
+
+ renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
+ iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
+ "delay")
+ commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
+ fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
+ decodeWidth = Param.Unsigned("Decode width")
+
+ iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
+ "delay")
+ commitToRenameDelay = Param.Unsigned("Commit to rename delay")
+ decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
+ renameWidth = Param.Unsigned("Rename width")
+
+ commitToIEWDelay = Param.Unsigned("Commit to "
+ "Issue/Execute/Writeback delay")
+ renameToIEWDelay = Param.Unsigned("Rename to "
+ "Issue/Execute/Writeback delay")
+ issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
+ "to the IEW stage)")
+ issueWidth = Param.Unsigned("Issue width")
+ executeWidth = Param.Unsigned("Execute width")
+ executeIntWidth = Param.Unsigned("Integer execute width")
+ executeFloatWidth = Param.Unsigned("Floating point execute width")
+ executeBranchWidth = Param.Unsigned("Branch execute width")
+ executeMemoryWidth = Param.Unsigned("Memory execute width")
+
+ iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
+ "delay")
+ renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
+ commitWidth = Param.Unsigned("Commit width")
+ squashWidth = Param.Unsigned("Squash width")
+
+ localPredictorSize = Param.Unsigned("Size of local predictor")
+ localCtrBits = Param.Unsigned("Bits per counter")
+ localHistoryTableSize = Param.Unsigned("Size of local history table")
+ localHistoryBits = Param.Unsigned("Bits for the local history")
+ globalPredictorSize = Param.Unsigned("Size of global predictor")
+ globalCtrBits = Param.Unsigned("Bits per counter")
+ globalHistoryBits = Param.Unsigned("Bits of history")
+ choicePredictorSize = Param.Unsigned("Size of choice predictor")
+ choiceCtrBits = Param.Unsigned("Bits of choice counters")
+
+ BTBEntries = Param.Unsigned("Number of BTB entries")
+ BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
+
+ RASSize = Param.Unsigned("RAS size")
+
+ LQEntries = Param.Unsigned("Number of load queue entries")
+ SQEntries = Param.Unsigned("Number of store queue entries")
+ LFSTSize = Param.Unsigned("Last fetched store table size")
+ SSITSize = Param.Unsigned("Store set ID table size")
+
+ numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
+ numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
+ "registers")
+ numIQEntries = Param.Unsigned("Number of instruction queue entries")
+ numROBEntries = Param.Unsigned("Number of reorder buffer entries")
+
+ instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
+
+ function_trace = Param.Bool(False, "Enable function trace")
+ function_trace_start = Param.Tick(0, "Cycle to start function trace")
diff --git a/python/m5/objects/SimpleOzoneCPU.py b/python/m5/objects/SimpleOzoneCPU.py
new file mode 100644
index 000000000..0d6403383
--- /dev/null
+++ b/python/m5/objects/SimpleOzoneCPU.py
@@ -0,0 +1,86 @@
+from m5 import *
+from BaseCPU import BaseCPU
+
+class SimpleOzoneCPU(BaseCPU):
+ type = 'SimpleOzoneCPU'
+
+ numThreads = Param.Unsigned("number of HW thread contexts")
+
+ if not build_env['FULL_SYSTEM']:
+ mem = Param.FunctionalMemory(NULL, "memory")
+
+ width = Param.Unsigned("Width")
+ frontEndWidth = Param.Unsigned("Front end width")
+ backEndWidth = Param.Unsigned("Back end width")
+ backEndSquashLatency = Param.Unsigned("Back end squash latency")
+ backEndLatency = Param.Unsigned("Back end latency")
+ maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size")
+ decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
+ renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
+ iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
+ "delay")
+ commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
+ fetchWidth = Param.Unsigned("Fetch width")
+
+ renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
+ iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
+ "delay")
+ commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
+ fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
+ decodeWidth = Param.Unsigned("Decode width")
+
+ iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
+ "delay")
+ commitToRenameDelay = Param.Unsigned("Commit to rename delay")
+ decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
+ renameWidth = Param.Unsigned("Rename width")
+
+ commitToIEWDelay = Param.Unsigned("Commit to "
+ "Issue/Execute/Writeback delay")
+ renameToIEWDelay = Param.Unsigned("Rename to "
+ "Issue/Execute/Writeback delay")
+ issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
+ "to the IEW stage)")
+ issueWidth = Param.Unsigned("Issue width")
+ executeWidth = Param.Unsigned("Execute width")
+ executeIntWidth = Param.Unsigned("Integer execute width")
+ executeFloatWidth = Param.Unsigned("Floating point execute width")
+ executeBranchWidth = Param.Unsigned("Branch execute width")
+ executeMemoryWidth = Param.Unsigned("Memory execute width")
+
+ iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
+ "delay")
+ renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
+ commitWidth = Param.Unsigned("Commit width")
+ squashWidth = Param.Unsigned("Squash width")
+
+ localPredictorSize = Param.Unsigned("Size of local predictor")
+ localCtrBits = Param.Unsigned("Bits per counter")
+ localHistoryTableSize = Param.Unsigned("Size of local history table")
+ localHistoryBits = Param.Unsigned("Bits for the local history")
+ globalPredictorSize = Param.Unsigned("Size of global predictor")
+ globalCtrBits = Param.Unsigned("Bits per counter")
+ globalHistoryBits = Param.Unsigned("Bits of history")
+ choicePredictorSize = Param.Unsigned("Size of choice predictor")
+ choiceCtrBits = Param.Unsigned("Bits of choice counters")
+
+ BTBEntries = Param.Unsigned("Number of BTB entries")
+ BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
+
+ RASSize = Param.Unsigned("RAS size")
+
+ LQEntries = Param.Unsigned("Number of load queue entries")
+ SQEntries = Param.Unsigned("Number of store queue entries")
+ LFSTSize = Param.Unsigned("Last fetched store table size")
+ SSITSize = Param.Unsigned("Store set ID table size")
+
+ numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
+ numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
+ "registers")
+ numIQEntries = Param.Unsigned("Number of instruction queue entries")
+ numROBEntries = Param.Unsigned("Number of reorder buffer entries")
+
+ instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
+
+ function_trace = Param.Bool(False, "Enable function trace")
+ function_trace_start = Param.Tick(0, "Cycle to start function trace")
diff --git a/src/SConscript b/src/SConscript
index 78db4e453..184c7ccc1 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -79,12 +79,14 @@ base_sources = Split('''
base/stats/visit.cc
base/stats/text.cc
+ cpu/activity.cc
cpu/base.cc
cpu/cpu_exec_context.cc
cpu/cpuevent.cc
cpu/exetrace.cc
cpu/op_class.cc
cpu/pc_event.cc
+ cpu/quiesce_event.cc
cpu/static_inst.cc
cpu/sampler/sampler.cc
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 12f7659e6..a242282ec 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -145,7 +145,8 @@ CPUExecContext::hwrei()
setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
if (!misspeculating()) {
- cpu->kernelStats->hwrei();
+ if (kernelStats)
+ kernelStats->hwrei();
cpu->checkInterrupts = true;
}
@@ -335,7 +336,8 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
// write entire quad w/ no side-effect
old = ipr[idx];
ipr[idx] = val;
- xc->getCpuPtr()->kernelStats->context(old, val, xc);
+ if (xc->getKernelStats())
+ xc->getKernelStats()->context(old, val, xc);
break;
case AlphaISA::IPR_DTB_PTE:
@@ -362,14 +364,18 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
- xc->getCpuPtr()->kernelStats->swpipl(ipr[idx]);
+ if (xc->getKernelStats())
+ xc->getKernelStats()->swpipl(ipr[idx]);
break;
case AlphaISA::IPR_DTB_CM:
- if (val & 0x18)
- xc->getCpuPtr()->kernelStats->mode(Kernel::user, xc);
- else
- xc->getCpuPtr()->kernelStats->mode(Kernel::kernel, xc);
+ if (val & 0x18) {
+ if (xc->getKernelStats())
+ xc->getKernelStats()->mode(Kernel::user, xc);
+ } else {
+ if (xc->getKernelStats())
+ xc->getKernelStats()->mode(Kernel::kernel, xc);
+ }
case AlphaISA::IPR_ICM:
// only write two mode bits - processor mode
@@ -555,7 +561,8 @@ AlphaISA::copyIprs(ExecContext *src, ExecContext *dest)
bool
CPUExecContext::simPalCheck(int palFunc)
{
- cpu->kernelStats->callpal(palFunc, proxy);
+ if (kernelStats)
+ kernelStats->callpal(palFunc, proxy);
switch (palFunc) {
case PAL::halt:
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index f41c46ac1..e6b4c234f 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -78,7 +78,7 @@ decode OPCODE default Unknown::unknown() {
uint64_t tmp = write_result;
// see stq_c
Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
- }}, mem_flags = LOCKED);
+ }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
0x2f: stq_c({{ Mem.uq = Ra; }},
{{
uint64_t tmp = write_result;
@@ -90,7 +90,7 @@ decode OPCODE default Unknown::unknown() {
// mailbox access, and we don't update the
// result register at all.
Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
- }}, mem_flags = LOCKED);
+ }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
}
format IntegerOperate {
@@ -596,8 +596,8 @@ decode OPCODE default Unknown::unknown() {
0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
- 0x024: mt_fpcr({{ FPCR = Fa.uq; }});
- 0x025: mf_fpcr({{ Fa.uq = FPCR; }});
+ 0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
+ 0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
}
}
@@ -628,7 +628,7 @@ decode OPCODE default Unknown::unknown() {
#else
Ra = curTick;
#endif
- }});
+ }}, IsUnverifiable);
// All of the barrier instructions below do nothing in
// their execute() methods (hence the empty code blocks).
@@ -646,8 +646,8 @@ decode OPCODE default Unknown::unknown() {
// a barrier on integer and FP traps. "EXCB is thus a
// superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
// them the same though.
- 0x0000: trapb({{ }}, IsSerializing, No_OpClass);
- 0x0400: excb({{ }}, IsSerializing, No_OpClass);
+ 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
+ 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
}
@@ -701,9 +701,9 @@ decode OPCODE default Unknown::unknown() {
xc->syscall(R0);
}}, IsNonSpeculative);
// Read uniq reg into ABI return value register (r0)
- 0x9e: rduniq({{ R0 = Runiq; }});
+ 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
// Write uniq reg with value from ABI arg register (r16)
- 0x9f: wruniq({{ Runiq = R16; }});
+ 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
}
}
#endif
@@ -740,7 +740,7 @@ decode OPCODE default Unknown::unknown() {
format HwMoveIPR {
1: hw_mfpr({{
Ra = xc->readMiscRegWithEffect(ipr_index, fault);
- }});
+ }}, IsIprAccess);
}
}
@@ -750,14 +750,14 @@ decode OPCODE default Unknown::unknown() {
1: hw_mtpr({{
xc->setMiscRegWithEffect(ipr_index, Ra);
if (traceData) { traceData->setData(Ra); }
- }});
+ }}, IsIprAccess);
}
}
format BasicOperate {
0x1e: decode PALMODE {
0: OpcdecFault::hw_rei();
- 1:hw_rei({{ xc->hwrei(); }}, IsSerializing);
+ 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
}
// M5 special opcodes use the reserved 0x01 opcode space
@@ -767,13 +767,13 @@ decode OPCODE default Unknown::unknown() {
}}, IsNonSpeculative);
0x01: quiesce({{
AlphaPseudo::quiesce(xc->xcBase());
- }}, IsNonSpeculative);
+ }}, IsNonSpeculative, IsQuiesce);
0x02: quiesceNs({{
AlphaPseudo::quiesceNs(xc->xcBase(), R16);
- }}, IsNonSpeculative);
+ }}, IsNonSpeculative, IsQuiesce);
0x03: quiesceCycles({{
AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
- }}, IsNonSpeculative);
+ }}, IsNonSpeculative, IsQuiesce);
0x04: quiesceTime({{
R0 = AlphaPseudo::quiesceTime(xc->xcBase());
}}, IsNonSpeculative);
diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa
index 93640f274..37de20617 100644
--- a/src/arch/alpha/isa/pal.isa
+++ b/src/arch/alpha/isa/pal.isa
@@ -264,9 +264,11 @@ output decoder {{
}
}};
-def format HwMoveIPR(code) {{
+def format HwMoveIPR(code, *flags) {{
+ all_flags = ['IprAccessOp']
+ all_flags += flags
iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code),
- ['IprAccessOp'])
+ all_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
diff --git a/src/base/traceflags.py b/src/base/traceflags.py
index 3b7dd0f81..9797e4cb7 100644
--- a/src/base/traceflags.py
+++ b/src/base/traceflags.py
@@ -103,49 +103,19 @@ baseFlags = [
'IdeDisk',
'InstExec',
'Interrupt',
- 'LDSTQ',
+ 'LSQ',
+ 'LSQUnit',
'Loader',
'MC146818',
'MMU',
'MSHR',
'Mbox',
'MemDepUnit',
- 'OoOCPU',
- 'PCEvent',
- 'PCIA',
- 'PCIDEV',
- 'PciConfigAll',
- 'Pipeline',
- 'Printf',
- 'ROB',
- 'Regs',
- 'Rename',
- 'RenameMap',
- 'SQL',
- 'Sampler',
- 'ScsiCtrl',
- 'ScsiDisk',
- 'ScsiNone',
- 'Serialize',
- 'SimpleCPU',
- 'SimpleDisk',
- 'SimpleDiskData',
- 'Sparc',
- 'Split',
- 'Stack',
- 'StatEvents',
- 'Stats',
- 'StoreSet',
- 'Syscall',
- 'SyscallVerbose',
- 'TCPIP',
- 'TLB',
- 'Thread',
- 'Timer',
- 'Tsunami',
- 'Uart',
- 'VtoPhys',
- 'WriteBarrier',
+ 'OzoneCPU',
+ 'FE',
+ 'IBE',
+ 'BE',
+ 'OzoneLSQ',
]
#
@@ -163,7 +133,8 @@ compoundFlagMap = {
'EthernetAll' : [ 'Ethernet', 'EthernetPIO', 'EthernetDMA', 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ],
'EthernetNoData' : [ 'Ethernet', 'EthernetPIO', 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ],
'IdeAll' : [ 'IdeCtrl', 'IdeDisk' ],
- 'FullCPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LDSTQ', 'StoreSet', 'MemDepUnit', 'DynInst', 'FullCPU']
+ 'FullCPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'FullCPU', 'Activity','Scoreboard','Writeback'],
+ 'OzoneCPUAll' : [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU']
}
#############################################################
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 34fb6df78..a4cbe2aa6 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -58,6 +58,14 @@ virtual Fault completeAcc(Packet *pkt, %s *xc,
{ panic("completeAcc not defined!"); };
'''
+mem_ini_sig_template = '''
+virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); };
+'''
+
+mem_comp_sig_template = '''
+virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; };
+'''
+
# Generate header.
def gen_cpu_exec_signatures(target, source, env):
f = open(str(target[0]), 'w')
@@ -118,20 +126,48 @@ if 'AlphaFullCPU' in env['CPU_MODELS']:
o3/decode.cc
o3/fetch.cc
o3/free_list.cc
+ o3/fu_pool.cc
o3/cpu.cc
o3/iew.cc
o3/inst_queue.cc
- o3/ldstq.cc
+ o3/lsq_unit.cc
+ o3/lsq.cc
o3/mem_dep_unit.cc
o3/ras.cc
o3/rename.cc
o3/rename_map.cc
o3/rob.cc
- o3/sat_counter.cc
+ o3/scoreboard.cc
o3/store_set.cc
o3/tournament_pred.cc
''')
+if 'OzoneSimpleCPU' in env['CPU_MODELS']:
+ sources += Split('''
+ ozone/cpu.cc
+ ozone/cpu_builder.cc
+ ozone/dyn_inst.cc
+ ozone/front_end.cc
+ ozone/inorder_back_end.cc
+ ozone/inst_queue.cc
+ ozone/rename_table.cc
+ ''')
+
+if 'OzoneCPU' in env['CPU_MODELS']:
+ sources += Split('''
+ ozone/back_end.cc
+ ozone/lsq_unit.cc
+ ozone/lw_back_end.cc
+ ozone/lw_lsq.cc
+ ''')
+
+if 'CheckerCPU' in env['CPU_MODELS']:
+ sources += Split('''
+ checker/cpu.cc
+ checker/cpu_builder.cc
+ checker/o3_cpu_builder.cc
+ ''')
+
# FullCPU sources are included from m5/SConscript since they're not
# below this point in the file hierarchy.
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index fb6116fd4..8641d987d 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -46,10 +46,6 @@
#include "base/trace.hh"
-#if FULL_SYSTEM
-#include "kern/kernel_stats.hh"
-#endif
-
using namespace std;
vector<BaseCPU *> BaseCPU::cpuList;
@@ -154,8 +150,6 @@ BaseCPU::BaseCPU(Params *p)
profileEvent = NULL;
if (params->profile)
profileEvent = new ProfileEvent(this, params->profile);
-
- kernelStats = new Kernel::Statistics(system);
#endif
}
@@ -165,6 +159,7 @@ BaseCPU::Params::Params()
#if FULL_SYSTEM
profile = false;
#endif
+ checker = NULL;
}
void
@@ -175,10 +170,6 @@ BaseCPU::enableFunctionTrace()
BaseCPU::~BaseCPU()
{
-#if FULL_SYSTEM
- if (kernelStats)
- delete kernelStats;
-#endif
}
void
@@ -219,8 +210,6 @@ BaseCPU::regStats()
execContexts[0]->regStats(name());
#if FULL_SYSTEM
- if (kernelStats)
- kernelStats->regStats(name() + ".kern");
#endif
}
@@ -240,6 +229,7 @@ BaseCPU::registerExecContexts()
#else
xc->setCpuId(xc->getProcessPtr()->registerExecContext(xc));
#endif
+ }
}
}
@@ -349,12 +339,6 @@ BaseCPU::serialize(std::ostream &os)
{
SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
SERIALIZE_SCALAR(intstatus);
-
-#if FULL_SYSTEM
- if (kernelStats)
- kernelStats->serialize(os);
-#endif
-
}
void
@@ -362,11 +346,6 @@ BaseCPU::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
UNSERIALIZE_SCALAR(intstatus);
-
-#if FULL_SYSTEM
- if (kernelStats)
- kernelStats->unserialize(cp, section);
-#endif
}
#endif // FULL_SYSTEM
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 79700c117..f14ace750 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -38,10 +38,10 @@
#include "sim/sim_object.hh"
#include "arch/isa_traits.hh"
-class System;
-namespace Kernel { class Statistics; }
class BranchPred;
+class CheckerCPU;
class ExecContext;
+class System;
class BaseCPU : public SimObject
{
@@ -125,6 +125,7 @@ class BaseCPU : public SimObject
int cpu_id;
Tick profile;
#endif
+ BaseCPU *checker;
Params();
};
@@ -232,10 +233,6 @@ class BaseCPU : public SimObject
public:
// Number of CPU cycles simulated
Stats::Scalar<> numCycles;
-
-#if FULL_SYSTEM
- Kernel::Statistics *kernelStats;
-#endif
};
#endif // __CPU_BASE_HH__
diff --git a/src/cpu/base_dyn_inst.cc b/src/cpu/base_dyn_inst.cc
index bf7c35cad..7ab760ae3 100644
--- a/src/cpu/base_dyn_inst.cc
+++ b/src/cpu/base_dyn_inst.cc
@@ -26,10 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_BASE_DYN_INST_CC__
-#define __CPU_BASE_DYN_INST_CC__
-
#include <iostream>
+#include <set>
#include <string>
#include <sstream>
@@ -43,6 +41,8 @@
#include "cpu/base_dyn_inst.hh"
#include "cpu/o3/alpha_impl.hh"
#include "cpu/o3/alpha_cpu.hh"
+#include "cpu/ozone/simple_impl.hh"
+#include "cpu/ozone/ozone_impl.hh"
using namespace std;
using namespace TheISA;
@@ -54,21 +54,23 @@ using namespace TheISA;
unsigned int MyHashFunc(const BaseDynInst *addr)
{
- unsigned a = (unsigned)addr;
- unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
+ unsigned a = (unsigned)addr;
+ unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
- return hash;
+ return hash;
}
-typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc> my_hash_t;
+typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
+my_hash_t;
+
my_hash_t thishash;
#endif
template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(MachInst machInst, Addr inst_PC,
+BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC,
Addr pred_PC, InstSeqNum seq_num,
FullCPU *cpu)
- : staticInst(machInst), traceData(NULL), cpu(cpu), cpuXC(cpu->cpuXCBase())
+ : staticInst(machInst), traceData(NULL), cpu(cpu)/*, xc(cpu->xcBase())*/
{
seqNum = seq_num;
@@ -83,6 +85,7 @@ template <class Impl>
BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
: staticInst(_staticInst), traceData(NULL)
{
+ seqNum = 0;
initVars();
}
@@ -90,23 +93,40 @@ template <class Impl>
void
BaseDynInst<Impl>::initVars()
{
+ req = NULL;
effAddr = MemReq::inval_addr;
physEffAddr = MemReq::inval_addr;
+ storeSize = 0;
readyRegs = 0;
completed = false;
+ resultReady = false;
canIssue = false;
issued = false;
executed = false;
canCommit = false;
+ committed = false;
squashed = false;
squashedInIQ = false;
+ squashedInLSQ = false;
+ squashedInROB = false;
eaCalcDone = false;
+ memOpDone = false;
+ lqIdx = -1;
+ sqIdx = -1;
+ reachedCommit = false;
blockingInst = false;
recoverInst = false;
+ iqEntry = false;
+ robEntry = false;
+
+ serializeBefore = false;
+ serializeAfter = false;
+ serializeHandled = false;
+
// Eventually make this a parameter.
threadNumber = 0;
@@ -114,22 +134,63 @@ BaseDynInst<Impl>::initVars()
asid = 0;
// Initialize the fault to be unimplemented opcode.
- fault = new UnimplementedOpcodeFault;
+// fault = new UnimplementedOpcodeFault;
+ fault = NoFault;
++instcount;
- DPRINTF(FullCPU, "DynInst: Instruction created. Instcount=%i\n",
- instcount);
+ if (instcount > 1500) {
+ cpu->dumpInsts();
+#ifdef DEBUG
+ dumpSNList();
+#endif
+ assert(instcount <= 1500);
+ }
+
+ DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n",
+ seqNum, instcount);
+
+#ifdef DEBUG
+ cpu->snList.insert(seqNum);
+#endif
}
template <class Impl>
BaseDynInst<Impl>::~BaseDynInst()
{
+ if (req) {
+ req = NULL;
+ }
+
+ if (traceData) {
+ delete traceData;
+ }
+
--instcount;
- DPRINTF(FullCPU, "DynInst: Instruction destroyed. Instcount=%i\n",
- instcount);
+
+ DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n",
+ seqNum, instcount);
+#ifdef DEBUG
+ cpu->snList.erase(seqNum);
+#endif
}
+#ifdef DEBUG
+template <class Impl>
+void
+BaseDynInst<Impl>::dumpSNList()
+{
+ std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
+
+ int count = 0;
+ while (sn_it != cpu->snList.end()) {
+ cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
+ count++;
+ sn_it++;
+ }
+}
+#endif
+
template <class Impl>
void
BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
@@ -139,14 +200,14 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
// state.
// Generate a MemReq so we can translate the effective address.
- MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), 1, flags);
+ MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
req->asid = asid;
// Prefetches never cause faults.
fault = NoFault;
// note this is a local, not BaseDynInst::fault
- Fault trans_fault = cpuXC->translateDataReadReq(req);
+ Fault trans_fault = cpu->translateDataReadReq(req);
if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
// It's a valid address to cacheable space. Record key MemReq
@@ -162,15 +223,6 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
effAddr = physEffAddr = MemReq::inval_addr;
}
- /**
- * @todo
- * Replace the disjoint functional memory with a unified one and remove
- * this hack.
- */
-#if !FULL_SYSTEM
- req->paddr = req->vaddr;
-#endif
-
if (traceData) {
traceData->setAddr(addr);
}
@@ -184,10 +236,10 @@ BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
// will casue a TLB miss trap if necessary... not sure whether
// that's the best thing to do or not. We don't really need the
// MemReq otherwise, since wh64 has no functional effect.
- MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), size, flags);
+ MemReqPtr req = new MemReq(addr, thread->getXCProxy(), size, flags);
req->asid = asid;
- fault = cpuXC->translateDataWriteReq(req);
+ fault = cpu->translateDataWriteReq(req);
if (fault == NoFault && !(req->flags & UNCACHEABLE)) {
// Record key MemReq parameters so we can generate another one
@@ -212,18 +264,18 @@ template <class Impl>
Fault
BaseDynInst<Impl>::copySrcTranslate(Addr src)
{
- MemReqPtr req = new MemReq(src, cpuXC->getProxy(), 64);
+ MemReqPtr req = new MemReq(src, thread->getXCProxy(), 64);
req->asid = asid;
// translate to physical address
- Fault fault = cpuXC->translateDataReadReq(req);
+ Fault fault = cpu->translateDataReadReq(req);
if (fault == NoFault) {
- cpuXC->copySrcAddr = src;
- cpuXC->copySrcPhysAddr = req->paddr;
+ thread->copySrcAddr = src;
+ thread->copySrcPhysAddr = req->paddr;
} else {
- cpuXC->copySrcAddr = 0;
- cpuXC->copySrcPhysAddr = 0;
+ thread->copySrcAddr = 0;
+ thread->copySrcPhysAddr = 0;
}
return fault;
}
@@ -236,18 +288,18 @@ Fault
BaseDynInst<Impl>::copy(Addr dest)
{
uint8_t data[64];
- FunctionalMemory *mem = cpuXC->mem;
- assert(cpuXC->copySrcPhysAddr || cpuXC->misspeculating());
- MemReqPtr req = new MemReq(dest, cpuXC->getProxy(), 64);
+ FunctionalMemory *mem = thread->mem;
+ assert(thread->copySrcPhysAddr || thread->misspeculating());
+ MemReqPtr req = new MemReq(dest, thread->getXCProxy(), 64);
req->asid = asid;
// translate to physical address
- Fault fault = cpuXC->translateDataWriteReq(req);
+ Fault fault = cpu->translateDataWriteReq(req);
if (fault == NoFault) {
Addr dest_addr = req->paddr;
// Need to read straight from memory since we have more than 8 bytes.
- req->paddr = cpuXC->copySrcPhysAddr;
+ req->paddr = thread->copySrcPhysAddr;
mem->read(req, data);
req->paddr = dest_addr;
mem->write(req, data);
@@ -275,7 +327,6 @@ BaseDynInst<Impl>::dump(std::string &outstring)
outstring = s.str();
}
-
#if 0
template <class Impl>
Fault
@@ -338,6 +389,28 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
#endif
template <class Impl>
+void
+BaseDynInst<Impl>::markSrcRegReady()
+{
+ if (++readyRegs == numSrcRegs()) {
+ canIssue = true;
+ }
+}
+
+template <class Impl>
+void
+BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
+{
+ ++readyRegs;
+
+ _readySrcRegIdx[src_idx] = true;
+
+ if (readyRegs == numSrcRegs()) {
+ canIssue = true;
+ }
+}
+
+template <class Impl>
bool
BaseDynInst<Impl>::eaSrcsReady()
{
@@ -345,8 +418,7 @@ BaseDynInst<Impl>::eaSrcsReady()
// EA calc depends on. (i.e. src reg 0 is the source of the data to be
// stored)
- for (int i = 1; i < numSrcRegs(); ++i)
- {
+ for (int i = 1; i < numSrcRegs(); ++i) {
if (!_readySrcRegIdx[i])
return false;
}
@@ -361,4 +433,16 @@ template <>
int
BaseDynInst<AlphaSimpleImpl>::instcount = 0;
-#endif // __CPU_BASE_DYN_INST_CC__
+// Forward declaration
+template class BaseDynInst<SimpleImpl>;
+
+template <>
+int
+BaseDynInst<SimpleImpl>::instcount = 0;
+
+// Forward declaration
+template class BaseDynInst<OzoneImpl>;
+
+template <>
+int
+BaseDynInst<OzoneImpl>::instcount = 0;
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 3a7852f79..388ea4a8d 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -29,21 +29,24 @@
#ifndef __CPU_BASE_DYN_INST_HH__
#define __CPU_BASE_DYN_INST_HH__
+#include <list>
#include <string>
-#include <vector>
#include "base/fast_alloc.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/exetrace.hh"
#include "cpu/inst_seq.hh"
-#include "cpu/o3/comm.hh"
#include "cpu/static_inst.hh"
-#include "encumbered/cpu/full/bpred_update.hh"
#include "encumbered/cpu/full/op_class.hh"
+#include "mem/functional/memory_control.hh"
+#include "sim/system.hh"
+/*
+#include "encumbered/cpu/full/bpred_update.hh"
#include "encumbered/cpu/full/spec_memory.hh"
#include "encumbered/cpu/full/spec_state.hh"
#include "encumbered/mem/functional/main.hh"
+*/
/**
* @file
@@ -59,20 +62,29 @@ class BaseDynInst : public FastAlloc, public RefCounted
public:
// Typedef for the CPU.
typedef typename Impl::FullCPU FullCPU;
+ typedef typename FullCPU::ImplState ImplState;
- /// Binary machine instruction type.
+ // Binary machine instruction type.
typedef TheISA::MachInst MachInst;
- /// Logical register index type.
+ // Extended machine instruction type
+ typedef TheISA::ExtMachInst ExtMachInst;
+ // Logical register index type.
typedef TheISA::RegIndex RegIndex;
- /// Integer register index type.
+ // Integer register index type.
typedef TheISA::IntReg IntReg;
+ // The DynInstPtr type.
+ typedef typename Impl::DynInstPtr DynInstPtr;
+
+ // The list of instructions iterator type.
+ typedef typename std::list<DynInstPtr>::iterator ListIt;
+
enum {
- MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
- MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
+ MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
+ MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
};
- /** The static inst used by this dyn inst. */
+ /** The StaticInst used by this BaseDynInst. */
StaticInstPtr staticInst;
////////////////////////////////////////////
@@ -80,11 +92,27 @@ class BaseDynInst : public FastAlloc, public RefCounted
// INSTRUCTION EXECUTION
//
////////////////////////////////////////////
+ /** InstRecord that tracks this instructions. */
Trace::InstRecord *traceData;
+ /**
+ * Does a read to a given address.
+ * @param addr The address to read.
+ * @param data The read's data is written into this parameter.
+ * @param flags The request's flags.
+ * @return Returns any fault due to the read.
+ */
template <class T>
Fault read(Addr addr, T &data, unsigned flags);
+ /**
+ * Does a write to a given address.
+ * @param data The data to be written.
+ * @param addr The address to write to.
+ * @param flags The request's flags.
+ * @param res The result of the write (for load locked/store conditionals).
+ * @return Returns any fault due to the write.
+ */
template <class T>
Fault write(T data, Addr addr, unsigned flags,
uint64_t *res);
@@ -96,18 +124,24 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** @todo: Consider making this private. */
public:
- /** Is this instruction valid. */
- bool valid;
-
/** The sequence number of the instruction. */
InstSeqNum seqNum;
- /** How many source registers are ready. */
- unsigned readyRegs;
+ /** Is the instruction in the IQ */
+ bool iqEntry;
+
+ /** Is the instruction in the ROB */
+ bool robEntry;
+
+ /** Is the instruction in the LSQ */
+ bool lsqEntry;
/** Is the instruction completed. */
bool completed;
+ /** Is the instruction's result ready. */
+ bool resultReady;
+
/** Can this instruction issue. */
bool canIssue;
@@ -120,12 +154,21 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Can this instruction commit. */
bool canCommit;
+ /** Is this instruction committed. */
+ bool committed;
+
/** Is this instruction squashed. */
bool squashed;
/** Is this instruction squashed in the instruction queue. */
bool squashedInIQ;
+ /** Is this instruction squashed in the instruction queue. */
+ bool squashedInLSQ;
+
+ /** Is this instruction squashed in the instruction queue. */
+ bool squashedInROB;
+
/** Is this a recover instruction. */
bool recoverInst;
@@ -141,15 +184,21 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** data address space ID, for loads & stores. */
short asid;
+ /** How many source registers are ready. */
+ unsigned readyRegs;
+
/** Pointer to the FullCPU object. */
FullCPU *cpu;
- /** Pointer to the exec context. Will not exist in the final version. */
- CPUExecContext *cpuXC;
+ /** Pointer to the exec context. */
+ ImplState *thread;
/** The kind of fault this instruction has generated. */
Fault fault;
+ /** The memory request. */
+ MemReqPtr req;
+
/** The effective virtual address (lds & stores only). */
Addr effAddr;
@@ -197,17 +246,29 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Count of total number of dynamic instructions. */
static int instcount;
- /** Whether or not the source register is ready. Not sure this should be
- * here vs. the derived class.
+#ifdef DEBUG
+ void dumpSNList();
+#endif
+
+ /** Whether or not the source register is ready.
+ * @todo: Not sure this should be here vs the derived class.
*/
bool _readySrcRegIdx[MaxInstSrcRegs];
public:
- /** BaseDynInst constructor given a binary instruction. */
- BaseDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
+ /** BaseDynInst constructor given a binary instruction.
+ * @param inst The binary instruction.
+ * @param PC The PC of the instruction.
+ * @param pred_PC The predicted next PC.
+ * @param seq_num The sequence number of the instruction.
+ * @param cpu Pointer to the instruction's CPU.
+ */
+ BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
FullCPU *cpu);
- /** BaseDynInst constructor given a static inst pointer. */
+ /** BaseDynInst constructor given a StaticInst pointer.
+ * @param _staticInst The StaticInst for this BaseDynInst.
+ */
BaseDynInst(StaticInstPtr &_staticInst);
/** BaseDynInst destructor. */
@@ -218,12 +279,20 @@ class BaseDynInst : public FastAlloc, public RefCounted
void initVars();
public:
+ /**
+ * @todo: Make this function work; currently it is a dummy function.
+ * @param fault Last fault.
+ * @param cmd Last command.
+ * @param addr Virtual address of access.
+ * @param p Memory accessed.
+ * @param nbytes Access size.
+ */
void
- trace_mem(Fault fault, // last fault
- MemCmd cmd, // last command
- Addr addr, // virtual address of access
- void *p, // memory accessed
- int nbytes); // access size
+ trace_mem(Fault fault,
+ MemCmd cmd,
+ Addr addr,
+ void *p,
+ int nbytes);
/** Dumps out contents of this BaseDynInst. */
void dump();
@@ -237,6 +306,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Checks whether or not this instruction has had its branch target
* calculated yet. For now it is not utilized and is hacked to be
* always false.
+ * @todo: Actually use this instruction.
*/
bool doneTargCalc() { return false; }
@@ -252,12 +322,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
Addr readPredTarg() { return predPC; }
/** Returns whether the instruction was predicted taken or not. */
- bool predTaken() {
- return( predPC != (PC + sizeof(MachInst) ) );
- }
+ bool predTaken() { return predPC != (PC + sizeof(MachInst)); }
/** Returns whether the instruction mispredicted. */
- bool mispredicted() { return (predPC != nextPC); }
+ bool mispredicted() { return predPC != nextPC; }
//
// Instruction types. Forward checks to StaticInst object.
@@ -266,6 +334,8 @@ class BaseDynInst : public FastAlloc, public RefCounted
bool isMemRef() const { return staticInst->isMemRef(); }
bool isLoad() const { return staticInst->isLoad(); }
bool isStore() const { return staticInst->isStore(); }
+ bool isStoreConditional() const
+ { return staticInst->isStoreConditional(); }
bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
bool isCopy() const { return staticInst->isCopy(); }
@@ -280,9 +350,53 @@ class BaseDynInst : public FastAlloc, public RefCounted
bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
bool isThreadSync() const { return staticInst->isThreadSync(); }
bool isSerializing() const { return staticInst->isSerializing(); }
+ bool isSerializeBefore() const
+ { return staticInst->isSerializeBefore() || serializeBefore; }
+ bool isSerializeAfter() const
+ { return staticInst->isSerializeAfter() || serializeAfter; }
bool isMemBarrier() const { return staticInst->isMemBarrier(); }
bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
+ bool isQuiesce() const { return staticInst->isQuiesce(); }
+ bool isIprAccess() const { return staticInst->isIprAccess(); }
+ bool isUnverifiable() const { return staticInst->isUnverifiable(); }
+
+ /** Temporarily sets this instruction as a serialize before instruction. */
+ void setSerializeBefore() { serializeBefore = true; }
+
+ /** Clears the serializeBefore part of this instruction. */
+ void clearSerializeBefore() { serializeBefore = false; }
+
+ /** Checks if this serializeBefore is only temporarily set. */
+ bool isTempSerializeBefore() { return serializeBefore; }
+
+ /** Tracks if instruction has been externally set as serializeBefore. */
+ bool serializeBefore;
+
+ /** Temporarily sets this instruction as a serialize after instruction. */
+ void setSerializeAfter() { serializeAfter = true; }
+
+ /** Clears the serializeAfter part of this instruction.*/
+ void clearSerializeAfter() { serializeAfter = false; }
+
+ /** Checks if this serializeAfter is only temporarily set. */
+ bool isTempSerializeAfter() { return serializeAfter; }
+
+ /** Tracks if instruction has been externally set as serializeAfter. */
+ bool serializeAfter;
+
+ /** Checks if the serialization part of this instruction has been
+ * handled. This does not apply to the temporary serializing
+ * state; it only applies to this instruction's own permanent
+ * serializing state.
+ */
+ bool isSerializeHandled() { return serializeHandled; }
+
+ /** Sets the serialization part of this instruction as handled. */
+ void setSerializeHandled() { serializeHandled = true; }
+
+ /** Whether or not the serialization of this instruction has been handled. */
+ bool serializeHandled;
/** Returns the opclass of this instruction. */
OpClass opClass() const { return staticInst->opClass(); }
@@ -290,10 +404,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Returns the branch target address. */
Addr branchTarget() const { return staticInst->branchTarget(PC); }
- /** Number of source registers. */
- int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
+ /** Returns the number of source registers. */
+ int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
- /** Number of destination registers. */
+ /** Returns the number of destination registers. */
int8_t numDestRegs() const { return staticInst->numDestRegs(); }
// the following are used to track physical register usage
@@ -302,16 +416,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
/** Returns the logical register index of the i'th destination register. */
- RegIndex destRegIdx(int i) const
- {
- return staticInst->destRegIdx(i);
- }
+ RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
/** Returns the logical register index of the i'th source register. */
- RegIndex srcRegIdx(int i) const
- {
- return staticInst->srcRegIdx(i);
- }
+ RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
/** Returns the result of an integer instruction. */
uint64_t readIntResult() { return instResult.integer; }
@@ -322,30 +430,32 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Returns the result of a floating point (double) instruction. */
double readDoubleResult() { return instResult.dbl; }
- //Push to .cc file.
- /** Records that one of the source registers is ready. */
- void markSrcRegReady()
+ void setIntReg(const StaticInst *si, int idx, uint64_t val)
{
- ++readyRegs;
- if(readyRegs == numSrcRegs()) {
- canIssue = true;
- }
+ instResult.integer = val;
}
- /** Marks a specific register as ready.
- * @todo: Move this to .cc file.
- */
- void markSrcRegReady(RegIndex src_idx)
+ void setFloatRegSingle(const StaticInst *si, int idx, float val)
{
- ++readyRegs;
+ instResult.fp = val;
+ }
- _readySrcRegIdx[src_idx] = 1;
+ void setFloatRegDouble(const StaticInst *si, int idx, double val)
+ {
+ instResult.dbl = val;
+ }
- if(readyRegs == numSrcRegs()) {
- canIssue = true;
- }
+ void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
+ {
+ instResult.integer = val;
}
+ /** Records that one of the source registers is ready. */
+ void markSrcRegReady();
+
+ /** Marks a specific register as ready. */
+ void markSrcRegReady(RegIndex src_idx);
+
/** Returns if a source register is ready. */
bool isReadySrcRegIdx(int idx) const
{
@@ -355,9 +465,13 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Sets this instruction as completed. */
void setCompleted() { completed = true; }
- /** Returns whethe or not this instruction is completed. */
+ /** Returns whether or not this instruction is completed. */
bool isCompleted() const { return completed; }
+ void setResultReady() { resultReady = true; }
+
+ bool isResultReady() const { return resultReady; }
+
/** Sets this instruction as ready to issue. */
void setCanIssue() { canIssue = true; }
@@ -385,34 +499,98 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Returns whether or not this instruction is ready to commit. */
bool readyToCommit() const { return canCommit; }
+ /** Sets this instruction as committed. */
+ void setCommitted() { committed = true; }
+
+ /** Returns whether or not this instruction is committed. */
+ bool isCommitted() const { return committed; }
+
/** Sets this instruction as squashed. */
void setSquashed() { squashed = true; }
/** Returns whether or not this instruction is squashed. */
bool isSquashed() const { return squashed; }
+ //Instruction Queue Entry
+ //-----------------------
+ /** Sets this instruction as a entry the IQ. */
+ void setInIQ() { iqEntry = true; }
+
+ /** Sets this instruction as a entry the IQ. */
+ void removeInIQ() { iqEntry = false; }
+
/** Sets this instruction as squashed in the IQ. */
- void setSquashedInIQ() { squashedInIQ = true; }
+ void setSquashedInIQ() { squashedInIQ = true; squashed = true;}
/** Returns whether or not this instruction is squashed in the IQ. */
bool isSquashedInIQ() const { return squashedInIQ; }
+ /** Returns whether or not this instruction has issued. */
+ bool isInIQ() const { return iqEntry; }
+
+
+ //Load / Store Queue Functions
+ //-----------------------
+ /** Sets this instruction as a entry the LSQ. */
+ void setInLSQ() { lsqEntry = true; }
+
+ /** Sets this instruction as a entry the LSQ. */
+ void removeInLSQ() { lsqEntry = false; }
+
+ /** Sets this instruction as squashed in the LSQ. */
+ void setSquashedInLSQ() { squashedInLSQ = true;}
+
+ /** Returns whether or not this instruction is squashed in the LSQ. */
+ bool isSquashedInLSQ() const { return squashedInLSQ; }
+
+ /** Returns whether or not this instruction is in the LSQ. */
+ bool isInLSQ() const { return lsqEntry; }
+
+
+ //Reorder Buffer Functions
+ //-----------------------
+ /** Sets this instruction as a entry the ROB. */
+ void setInROB() { robEntry = true; }
+
+ /** Sets this instruction as a entry the ROB. */
+ void removeInROB() { robEntry = false; }
+
+ /** Sets this instruction as squashed in the ROB. */
+ void setSquashedInROB() { squashedInROB = true; }
+
+ /** Returns whether or not this instruction is squashed in the ROB. */
+ bool isSquashedInROB() const { return squashedInROB; }
+
+ /** Returns whether or not this instruction is in the ROB. */
+ bool isInROB() const { return robEntry; }
+
/** Read the PC of this instruction. */
const Addr readPC() const { return PC; }
/** Set the next PC of this instruction (its actual target). */
- void setNextPC(uint64_t val) { nextPC = val; }
+ void setNextPC(uint64_t val)
+ {
+ nextPC = val;
+// instResult.integer = val;
+ }
+
+ void setASID(short addr_space_id) { asid = addr_space_id; }
+
+ void setThread(unsigned tid) { threadNumber = tid; }
+
+ void setState(ImplState *state) { thread = state; }
/** Returns the exec context.
* @todo: Remove this once the ExecContext is no longer used.
*/
- ExecContext *xcBase() { return cpuXC->getProxy(); }
+ ExecContext *xcBase() { return thread->getXCProxy(); }
private:
/** Instruction effective address.
* @todo: Consider if this is necessary or not.
*/
Addr instEffAddr;
+
/** Whether or not the effective address calculation is completed.
* @todo: Consider if this is necessary or not.
*/
@@ -423,7 +601,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
/** Returns the effective address. */
- const Addr &getEA() const { return instEffAddr; }
+ const Addr &getEA() const { return req->vaddr; }
/** Returns whether or not the eff. addr. calculation has been completed. */
bool doneEACalc() { return eaCalcDone; }
@@ -431,12 +609,26 @@ class BaseDynInst : public FastAlloc, public RefCounted
/** Returns whether or not the eff. addr. source registers are ready. */
bool eaSrcsReady();
+ /** Whether or not the memory operation is done. */
+ bool memOpDone;
+
public:
/** Load queue index. */
int16_t lqIdx;
/** Store queue index. */
int16_t sqIdx;
+
+ bool reachedCommit;
+
+ /** Iterator pointing to this BaseDynInst in the list of all insts. */
+ ListIt instListIt;
+
+ /** Returns iterator to this instruction in the list of all insts. */
+ ListIt &getInstListIt() { return instListIt; }
+
+ /** Sets iterator for this instruction in the list of all insts. */
+ void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
};
template<class Impl>
@@ -444,34 +636,47 @@ template<class T>
inline Fault
BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
{
- MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags);
+ if (executed) {
+ fault = cpu->read(req, data, lqIdx);
+ return fault;
+ }
+
+ req = new MemReq(addr, thread->getXCProxy(), sizeof(T), flags);
req->asid = asid;
+ req->thread_num = threadNumber;
+ req->pc = this->PC;
+
+ if ((req->vaddr & (TheISA::VMPageSize - 1)) + req->size >
+ TheISA::VMPageSize) {
+ return TheISA::genAlignmentFault();
+ }
fault = cpu->translateDataReadReq(req);
- // Record key MemReq parameters so we can generate another one
- // just like it for the timing access without calling translate()
- // again (which might mess up the TLB).
- // Do I ever really need this? -KTL 3/05
effAddr = req->vaddr;
physEffAddr = req->paddr;
memReqFlags = req->flags;
- /**
- * @todo
- * Replace the disjoint functional memory with a unified one and remove
- * this hack.
- */
-#if !FULL_SYSTEM
- req->paddr = req->vaddr;
-#endif
-
if (fault == NoFault) {
+#if FULL_SYSTEM
+ if (cpu->system->memctrl->badaddr(physEffAddr)) {
+ fault = TheISA::genMachineCheckFault();
+ data = (T)-1;
+ this->setExecuted();
+ } else {
+ fault = cpu->read(req, data, lqIdx);
+ }
+#else
fault = cpu->read(req, data, lqIdx);
+#endif
} else {
// Return a fixed value to keep simulation deterministic even
// along misspeculated paths.
data = (T)-1;
+
+ // Commit will have to clean up whatever happened. Set this
+ // instruction as executed.
+ this->setExecuted();
}
if (traceData) {
@@ -492,30 +697,33 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
traceData->setData(data);
}
- MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags);
+ req = new MemReq(addr, thread->getXCProxy(), sizeof(T), flags);
req->asid = asid;
+ req->thread_num = threadNumber;
+ req->pc = this->PC;
+
+ if ((req->vaddr & (TheISA::VMPageSize - 1)) + req->size >
+ TheISA::VMPageSize) {
+ return TheISA::genAlignmentFault();
+ }
fault = cpu->translateDataWriteReq(req);
- // Record key MemReq parameters so we can generate another one
- // just like it for the timing access without calling translate()
- // again (which might mess up the TLB).
effAddr = req->vaddr;
physEffAddr = req->paddr;
memReqFlags = req->flags;
- /**
- * @todo
- * Replace the disjoint functional memory with a unified one and remove
- * this hack.
- */
-#if !FULL_SYSTEM
- req->paddr = req->vaddr;
-#endif
-
if (fault == NoFault) {
+#if FULL_SYSTEM
+ if (cpu->system->memctrl->badaddr(physEffAddr)) {
+ fault = TheISA::genMachineCheckFault();
+ } else {
+ fault = cpu->write(req, data, sqIdx);
+ }
+#else
fault = cpu->write(req, data, sqIdx);
+#endif
}
if (res) {
diff --git a/src/cpu/cpu_exec_context.cc b/src/cpu/cpu_exec_context.cc
index b8aa9a67e..7c2b32a93 100644
--- a/src/cpu/cpu_exec_context.cc
+++ b/src/cpu/cpu_exec_context.cc
@@ -39,6 +39,7 @@
#include "base/output.hh"
#include "base/trace.hh"
#include "cpu/profile.hh"
+#include "cpu/quiesce_event.hh"
#include "kern/kernel_stats.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
@@ -54,15 +55,17 @@ using namespace std;
// constructor
#if FULL_SYSTEM
CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
- AlphaITB *_itb, AlphaDTB *_dtb)
+ AlphaITB *_itb, AlphaDTB *_dtb,
+ bool use_kernel_stats)
: _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
cpu_id(-1), lastActivate(0), lastSuspend(0), system(_sys), itb(_itb),
- dtb(_dtb), profile(NULL), quiesceEvent(this), func_exe_inst(0),
- storeCondFailures(0)
+ dtb(_dtb), profile(NULL), func_exe_inst(0), storeCondFailures(0)
{
proxy = new ProxyExecContext<CPUExecContext>(this);
+ quiesceEvent = new EndQuiesceEvent(proxy);
+
regs.clear();
if (cpu->params->profile) {
@@ -79,6 +82,12 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
profileNode = &dummyNode;
profilePC = 3;
+
+ if (use_kernel_stats) {
+ kernelStats = new Kernel::Statistics(system);
+ } else {
+ kernelStats = NULL;
+ }
Port *mem_port;
physPort = new FunctionalPort(csprintf("%s-%d-funcport",
cpu->name(), thread_num));
@@ -136,23 +145,6 @@ CPUExecContext::dumpFuncProfile()
profile->dump(proxy, *os);
}
-CPUExecContext::EndQuiesceEvent::EndQuiesceEvent(CPUExecContext *_cpuXC)
- : Event(&mainEventQueue), cpuXC(_cpuXC)
-{
-}
-
-void
-CPUExecContext::EndQuiesceEvent::process()
-{
- cpuXC->activate();
-}
-
-const char*
-CPUExecContext::EndQuiesceEvent::description()
-{
- return "End Quiesce Event.";
-}
-
void
CPUExecContext::profileClear()
{
@@ -185,6 +177,16 @@ CPUExecContext::takeOverFrom(ExecContext *oldContext)
cpu_id = oldContext->readCpuId();
#if !FULL_SYSTEM
func_exe_inst = oldContext->readFuncExeInst();
+#else
+ EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
+ if (quiesce) {
+ // Point the quiesce event's XC at this XC so that it wakes up
+ // the proper CPU.
+ quiesce->xc = proxy;
+ }
+ if (quiesceEvent) {
+ quiesceEvent->xc = proxy;
+ }
#endif
storeCondFailures = 0;
@@ -203,10 +205,11 @@ CPUExecContext::serialize(ostream &os)
#if FULL_SYSTEM
Tick quiesceEndTick = 0;
- if (quiesceEvent.scheduled())
- quiesceEndTick = quiesceEvent.when();
+ if (quiesceEvent->scheduled())
+ quiesceEndTick = quiesceEvent->when();
SERIALIZE_SCALAR(quiesceEndTick);
-
+ if (kernelStats)
+ kernelStats->serialize(os);
#endif
}
@@ -224,7 +227,9 @@ CPUExecContext::unserialize(Checkpoint *cp, const std::string &section)
Tick quiesceEndTick;
UNSERIALIZE_SCALAR(quiesceEndTick);
if (quiesceEndTick)
- quiesceEvent.schedule(quiesceEndTick);
+ quiesceEvent->schedule(quiesceEndTick);
+ if (kernelStats)
+ kernelStats->unserialize(cp, section);
#endif
}
@@ -237,7 +242,14 @@ CPUExecContext::activate(int delay)
lastActivate = curTick;
+ if (status() == ExecContext::Unallocated) {
+ cpu->activateWhenReady(thread_num);
+ return;
+ }
+
_status = ExecContext::Active;
+
+ // status() == Suspended
cpu->activateContext(thread_num, delay);
}
@@ -286,6 +298,10 @@ CPUExecContext::halt()
void
CPUExecContext::regStats(const string &name)
{
+#if FULL_SYSTEM
+ if (kernelStats)
+ kernelStats->regStats(name + ".kern");
+#endif
}
void
diff --git a/src/cpu/cpu_exec_context.hh b/src/cpu/cpu_exec_context.hh
index 2c06a7b3b..61e6550af 100644
--- a/src/cpu/cpu_exec_context.hh
+++ b/src/cpu/cpu_exec_context.hh
@@ -52,6 +52,10 @@ class FunctionalPort;
class PhysicalPort;
+namespace Kernel {
+ class Statistics;
+};
+
#else // !FULL_SYSTEM
#include "sim/process.hh"
@@ -142,23 +146,9 @@ class CPUExecContext
Addr profilePC;
void dumpFuncProfile();
- /** Event for timing out quiesce instruction */
- struct EndQuiesceEvent : public Event
- {
- /** A pointer to the execution context that is quiesced */
- CPUExecContext *cpuXC;
-
- EndQuiesceEvent(CPUExecContext *_cpuXC);
+ EndQuiesceEvent *quiesceEvent;
- /** Event process to occur at interrupt*/
- virtual void process();
-
- /** Event description */
- virtual const char *description();
- };
- EndQuiesceEvent quiesceEvent;
-
- Event *getQuiesceEvent() { return &quiesceEvent; }
+ EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
Tick readLastActivate() { return lastActivate; }
@@ -168,6 +158,9 @@ class CPUExecContext
void profileSample();
+ Kernel::Statistics *getKernelStats() { return kernelStats; }
+
+ Kernel::Statistics *kernelStats;
#else
/// Port that syscalls can use to access memory (provides translation step).
TranslatingPort *port;
@@ -208,7 +201,8 @@ class CPUExecContext
// constructor: initialize context from given process structure
#if FULL_SYSTEM
CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
- AlphaITB *_itb, AlphaDTB *_dtb);
+ AlphaITB *_itb, AlphaDTB *_dtb,
+ bool use_kernel_stats = true);
#else
CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid,
MemObject *memobj);
diff --git a/src/cpu/cpu_models.py b/src/cpu/cpu_models.py
index 8d0a15f61..c3de03948 100644
--- a/src/cpu/cpu_models.py
+++ b/src/cpu/cpu_models.py
@@ -68,4 +68,13 @@ CpuModel('FullCPU', 'full_cpu_exec.cc',
CpuModel('AlphaFullCPU', 'alpha_o3_exec.cc',
'#include "cpu/o3/alpha_dyn_inst.hh"',
{ 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
+CpuModel('OzoneSimpleCPU', 'ozone_simple_exec.cc',
+ '#include "cpu/ozone/dyn_inst.hh"',
+ { 'CPU_exec_context': 'OzoneDynInst<SimpleImpl>' })
+CpuModel('OzoneCPU', 'ozone_exec.cc',
+ '#include "cpu/ozone/dyn_inst.hh"',
+ { 'CPU_exec_context': 'OzoneDynInst<OzoneImpl>' })
+CpuModel('CheckerCPU', 'checker_cpu_exec.cc',
+ '#include "cpu/checker/cpu.hh"',
+ { 'CPU_exec_context': 'CheckerCPU' })
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 1f26183ab..5b601bb30 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -41,12 +41,16 @@
class AlphaDTB;
class AlphaITB;
class BaseCPU;
+class EndQuiesceEvent;
class Event;
class TranslatingPort;
class FunctionalPort;
class VirtualPort;
class Process;
class System;
+namespace Kernel {
+ class Statistics;
+};
class ExecContext
{
@@ -96,6 +100,8 @@ class ExecContext
virtual AlphaDTB * getDTBPtr() = 0;
+ virtual Kernel::Statistics *getKernelStats() = 0;
+
virtual FunctionalPort *getPhysPort() = 0;
virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0;
@@ -136,7 +142,7 @@ class ExecContext
virtual void unserialize(Checkpoint *cp, const std::string &section) = 0;
#if FULL_SYSTEM
- virtual Event *getQuiesceEvent() = 0;
+ virtual EndQuiesceEvent *getQuiesceEvent() = 0;
// Not necessarily the best location for these...
// Having an extra function just to read these is obnoxious
@@ -149,15 +155,6 @@ class ExecContext
virtual int getThreadNum() = 0;
- virtual int getInstAsid() = 0;
- virtual int getDataAsid() = 0;
-
- virtual Fault translateInstReq(RequestPtr &req) = 0;
-
- virtual Fault translateDataReadReq(RequestPtr &req) = 0;
-
- virtual Fault translateDataWriteReq(RequestPtr &req) = 0;
-
// Also somewhat obnoxious. Really only used for the TLB fault.
// However, may be quite useful in SPARC.
virtual TheISA::MachInst getInst() = 0;
@@ -216,11 +213,7 @@ class ExecContext
virtual void setStCondFailures(unsigned sc_failures) = 0;
#if FULL_SYSTEM
- virtual int readIntrFlag() = 0;
- virtual void setIntrFlag(int val) = 0;
- virtual Fault hwrei() = 0;
virtual bool inPalMode() = 0;
- virtual bool simPalCheck(int palFunc) = 0;
#endif
// Only really makes sense for old CPU model. Still could be useful though.
@@ -234,12 +227,9 @@ class ExecContext
virtual void setSyscallReturn(SyscallReturn return_value) = 0;
- virtual void syscall(int64_t callnum) = 0;
// Same with st cond failures.
virtual Counter readFuncExeInst() = 0;
-
- virtual void setFuncExeInst(Counter new_val) = 0;
#endif
virtual void changeRegFileContext(RegFile::ContextParam param,
@@ -271,6 +261,8 @@ class ProxyExecContext : public ExecContext
AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
+ Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); }
+
FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); }
VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); }
@@ -313,7 +305,7 @@ class ProxyExecContext : public ExecContext
{ actualXC->unserialize(cp, section); }
#if FULL_SYSTEM
- Event *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
+ EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
Tick readLastActivate() { return actualXC->readLastActivate(); }
Tick readLastSuspend() { return actualXC->readLastSuspend(); }
@@ -324,18 +316,6 @@ class ProxyExecContext : public ExecContext
int getThreadNum() { return actualXC->getThreadNum(); }
- int getInstAsid() { return actualXC->getInstAsid(); }
- int getDataAsid() { return actualXC->getDataAsid(); }
-
- Fault translateInstReq(RequestPtr &req)
- { return actualXC->translateInstReq(req); }
-
- Fault translateDataReadReq(RequestPtr &req)
- { return actualXC->translateDataReadReq(req); }
-
- Fault translateDataWriteReq(RequestPtr &req)
- { return actualXC->translateDataWriteReq(req); }
-
// @todo: Do I need this?
MachInst getInst() { return actualXC->getInst(); }
@@ -406,17 +386,8 @@ class ProxyExecContext : public ExecContext
void setStCondFailures(unsigned sc_failures)
{ actualXC->setStCondFailures(sc_failures); }
-
#if FULL_SYSTEM
- int readIntrFlag() { return actualXC->readIntrFlag(); }
-
- void setIntrFlag(int val) { actualXC->setIntrFlag(val); }
-
- Fault hwrei() { return actualXC->hwrei(); }
-
bool inPalMode() { return actualXC->inPalMode(); }
-
- bool simPalCheck(int palFunc) { return actualXC->simPalCheck(palFunc); }
#endif
// @todo: Fix this!
@@ -432,12 +403,8 @@ class ProxyExecContext : public ExecContext
void setSyscallReturn(SyscallReturn return_value)
{ actualXC->setSyscallReturn(return_value); }
- void syscall(int64_t callnum) { actualXC->syscall(callnum); }
Counter readFuncExeInst() { return actualXC->readFuncExeInst(); }
-
- void setFuncExeInst(Counter new_val)
- { return actualXC->setFuncExeInst(new_val); }
#endif
void changeRegFileContext(RegFile::ContextParam param,
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 0ed3b43c4..5ec05ea72 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -82,7 +82,8 @@ Trace::InstRecord::dump(ostream &outs)
std::string sym_str;
Addr sym_addr;
if (debugSymbolTable
- && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)) {
+ && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)
+ && flags[PC_SYMBOL]) {
if (PC != sym_addr)
sym_str += csprintf("+%d", PC - sym_addr);
outs << "@" << sym_str << " : ";
@@ -190,6 +191,8 @@ Param<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq",
"print fetch sequence number", false);
Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
"print correct-path sequence number", false);
+Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol",
+ "Use symbols for the PC if available", true);
Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
"print trace in intel compatible format", false);
Param<string> exe_trace_system(&exeTraceParams, "trace_system",
@@ -214,6 +217,7 @@ Trace::InstRecord::setParams()
flags[PRINT_INT_REGS] = exe_trace_print_iregs;
flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq;
flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq;
+ flags[PC_SYMBOL] = exe_trace_pc_symbol;
flags[INTEL_FORMAT] = exe_trace_intel_format;
trace_system = exe_trace_system;
}
diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index a26cdc517..7b86a9344 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -144,6 +144,7 @@ class InstRecord : public Record
PRINT_INT_REGS,
PRINT_FETCH_SEQ,
PRINT_CP_SEQ,
+ PC_SYMBOL,
INTEL_FORMAT,
NUM_BITS
};
diff --git a/src/cpu/inst_seq.hh b/src/cpu/inst_seq.hh
index 8de047af7..356d19df0 100644
--- a/src/cpu/inst_seq.hh
+++ b/src/cpu/inst_seq.hh
@@ -29,6 +29,8 @@
#ifndef __STD_TYPES_HH__
#define __STD_TYPES_HH__
+#include <stdint.h>
+
// inst sequence type, used to order instructions in the ready list,
// if this rolls over the ready list order temporarily will get messed
// up, but execution will continue and complete correctly
diff --git a/src/cpu/o3/2bit_local_pred.cc b/src/cpu/o3/2bit_local_pred.cc
index d9744eec7..c3fb2fdb8 100644
--- a/src/cpu/o3/2bit_local_pred.cc
+++ b/src/cpu/o3/2bit_local_pred.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "base/intmath.hh"
#include "base/trace.hh"
#include "cpu/o3/2bit_local_pred.hh"
@@ -36,17 +37,25 @@ DefaultBP::DefaultBP(unsigned _localPredictorSize,
localCtrBits(_localCtrBits),
instShiftAmt(_instShiftAmt)
{
- // Should do checks here to make sure sizes are correct (powers of 2).
+ if (!isPowerOf2(localPredictorSize)) {
+ fatal("Invalid local predictor size!\n");
+ }
+
+ localPredictorSets = localPredictorSize / localCtrBits;
+
+ if (!isPowerOf2(localPredictorSets)) {
+ fatal("Invalid number of local predictor sets! Check localCtrBits.\n");
+ }
// Setup the index mask.
- indexMask = localPredictorSize - 1;
+ indexMask = localPredictorSets - 1;
DPRINTF(Fetch, "Branch predictor: index mask: %#x\n", indexMask);
// Setup the array of counters for the local predictor.
- localCtrs = new SatCounter[localPredictorSize];
+ localCtrs.resize(localPredictorSets);
- for (int i = 0; i < localPredictorSize; ++i)
+ for (int i = 0; i < localPredictorSets; ++i)
localCtrs[i].setBits(_localCtrBits);
DPRINTF(Fetch, "Branch predictor: local predictor size: %i\n",
@@ -58,6 +67,14 @@ DefaultBP::DefaultBP(unsigned _localPredictorSize,
instShiftAmt);
}
+void
+DefaultBP::reset()
+{
+ for (int i = 0; i < localPredictorSets; ++i) {
+ localCtrs[i].reset();
+ }
+}
+
bool
DefaultBP::lookup(Addr &branch_addr)
{
@@ -68,8 +85,6 @@ DefaultBP::lookup(Addr &branch_addr)
DPRINTF(Fetch, "Branch predictor: Looking up index %#x\n",
local_predictor_idx);
- assert(local_predictor_idx < localPredictorSize);
-
local_prediction = localCtrs[local_predictor_idx].read();
DPRINTF(Fetch, "Branch predictor: prediction is %i.\n",
@@ -102,8 +117,6 @@ DefaultBP::update(Addr &branch_addr, bool taken)
DPRINTF(Fetch, "Branch predictor: Looking up index %#x\n",
local_predictor_idx);
- assert(local_predictor_idx < localPredictorSize);
-
if (taken) {
DPRINTF(Fetch, "Branch predictor: Branch updated as taken.\n");
localCtrs[local_predictor_idx].increment();
diff --git a/src/cpu/o3/2bit_local_pred.hh b/src/cpu/o3/2bit_local_pred.hh
index 97433e542..cd65978ca 100644
--- a/src/cpu/o3/2bit_local_pred.hh
+++ b/src/cpu/o3/2bit_local_pred.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,18 +26,23 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
-#define __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
+#ifndef __CPU_O3_2BIT_LOCAL_PRED_HH__
+#define __CPU_O3_2BIT_LOCAL_PRED_HH__
// For Addr type.
#include "arch/isa_traits.hh"
#include "cpu/o3/sat_counter.hh"
+#include <vector>
+
class DefaultBP
{
public:
/**
* Default branch predictor constructor.
+ * @param localPredictorSize Size of the local predictor.
+ * @param localCtrBits Number of bits per counter.
+ * @param instShiftAmt Offset amount for instructions to ignore alignment.
*/
DefaultBP(unsigned localPredictorSize, unsigned localCtrBits,
unsigned instShiftAmt);
@@ -57,10 +62,15 @@ class DefaultBP
*/
void update(Addr &branch_addr, bool taken);
+ void reset();
+
private:
- /** Returns the taken/not taken prediction given the value of the
+ /**
+ * Returns the taken/not taken prediction given the value of the
* counter.
+ * @param count The value of the counter.
+ * @return The prediction based on the counter value.
*/
inline bool getPrediction(uint8_t &count);
@@ -68,11 +78,14 @@ class DefaultBP
inline unsigned getLocalIndex(Addr &PC);
/** Array of counters that make up the local predictor. */
- SatCounter *localCtrs;
+ std::vector<SatCounter> localCtrs;
/** Size of the local predictor. */
unsigned localPredictorSize;
+ /** Number of sets. */
+ unsigned localPredictorSets;
+
/** Number of bits of the local predictor's counters. */
unsigned localCtrBits;
@@ -83,4 +96,4 @@ class DefaultBP
unsigned indexMask;
};
-#endif // __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
+#endif // __CPU_O3_2BIT_LOCAL_PRED_HH__
diff --git a/src/cpu/o3/alpha_cpu.hh b/src/cpu/o3/alpha_cpu.hh
index 8e1e0f42a..1bab0703e 100644
--- a/src/cpu/o3/alpha_cpu.hh
+++ b/src/cpu/o3/alpha_cpu.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,16 +26,19 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-// Todo: Find all the stuff in ExecContext and ev5 that needs to be
-// specifically designed for this CPU.
+#ifndef __CPU_O3_ALPHA_FULL_CPU_HH__
+#define __CPU_O3_ALPHA_FULL_CPU_HH__
-#ifndef __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
-#define __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
-
-#include "cpu/o3/cpu.hh"
#include "arch/isa_traits.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/o3/cpu.hh"
#include "sim/byteswap.hh"
+class EndQuiesceEvent;
+namespace Kernel {
+ class Statistics;
+};
+
template <class Impl>
class AlphaFullCPU : public FullO3CPU<Impl>
{
@@ -46,37 +49,180 @@ class AlphaFullCPU : public FullO3CPU<Impl>
typedef TheISA::MiscRegFile MiscRegFile;
public:
+ typedef O3ThreadState<Impl> ImplState;
+ typedef O3ThreadState<Impl> Thread;
typedef typename Impl::Params Params;
- public:
- AlphaFullCPU(Params &params);
+ /** Constructs an AlphaFullCPU with the given parameters. */
+ AlphaFullCPU(Params *params);
+
+ class AlphaXC : public ExecContext
+ {
+ public:
+ AlphaFullCPU<Impl> *cpu;
+
+ O3ThreadState<Impl> *thread;
+
+ virtual BaseCPU *getCpuPtr() { return cpu; }
+
+ virtual void setCpuId(int id) { cpu->cpu_id = id; }
+
+ virtual int readCpuId() { return cpu->cpu_id; }
+
+ virtual FunctionalMemory *getMemPtr() { return thread->mem; }
+
+#if FULL_SYSTEM
+ virtual System *getSystemPtr() { return cpu->system; }
+
+ virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
+
+ virtual AlphaITB *getITBPtr() { return cpu->itb; }
+
+ virtual AlphaDTB * getDTBPtr() { return cpu->dtb; }
+
+ virtual Kernel::Statistics *getKernelStats()
+ { return thread->kernelStats; }
+#else
+ virtual Process *getProcessPtr() { return thread->process; }
+#endif
+
+ virtual Status status() const { return thread->status(); }
+
+ virtual void setStatus(Status new_status)
+ { thread->setStatus(new_status); }
+
+ /// Set the status to Active. Optional delay indicates number of
+ /// cycles to wait before beginning execution.
+ virtual void activate(int delay = 1);
+
+ /// Set the status to Suspended.
+ virtual void suspend();
+
+ /// Set the status to Unallocated.
+ virtual void deallocate();
+
+ /// Set the status to Halted.
+ virtual void halt();
+
+#if FULL_SYSTEM
+ virtual void dumpFuncProfile();
+#endif
+
+ virtual void takeOverFrom(ExecContext *old_context);
+
+ virtual void regStats(const std::string &name);
+
+ virtual void serialize(std::ostream &os);
+ virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+#if FULL_SYSTEM
+ virtual EndQuiesceEvent *getQuiesceEvent();
+
+ virtual Tick readLastActivate();
+ virtual Tick readLastSuspend();
+
+ virtual void profileClear();
+ virtual void profileSample();
+#endif
+
+ virtual int getThreadNum() { return thread->tid; }
+
+ virtual TheISA::MachInst getInst();
+
+ virtual void copyArchRegs(ExecContext *xc);
+
+ virtual void clearArchRegs();
+
+ virtual uint64_t readIntReg(int reg_idx);
+
+ virtual float readFloatRegSingle(int reg_idx);
+
+ virtual double readFloatRegDouble(int reg_idx);
+
+ virtual uint64_t readFloatRegInt(int reg_idx);
+
+ virtual void setIntReg(int reg_idx, uint64_t val);
+
+ virtual void setFloatRegSingle(int reg_idx, float val);
+
+ virtual void setFloatRegDouble(int reg_idx, double val);
+
+ virtual void setFloatRegInt(int reg_idx, uint64_t val);
+
+ virtual uint64_t readPC()
+ { return cpu->readPC(thread->tid); }
+
+ virtual void setPC(uint64_t val);
+
+ virtual uint64_t readNextPC()
+ { return cpu->readNextPC(thread->tid); }
+
+ virtual void setNextPC(uint64_t val);
+
+ virtual MiscReg readMiscReg(int misc_reg)
+ { return cpu->readMiscReg(misc_reg, thread->tid); }
+
+ virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+ { return cpu->readMiscRegWithEffect(misc_reg, fault, thread->tid); }
+
+ virtual Fault setMiscReg(int misc_reg, const MiscReg &val);
+
+ virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+
+ // @todo: Figure out where these store cond failures should go.
+ virtual unsigned readStCondFailures()
+ { return thread->storeCondFailures; }
+
+ virtual void setStCondFailures(unsigned sc_failures)
+ { thread->storeCondFailures = sc_failures; }
+
+#if FULL_SYSTEM
+ virtual bool inPalMode()
+ { return TheISA::PcPAL(cpu->readPC(thread->tid)); }
+#endif
+
+ // Only really makes sense for old CPU model. Lots of code
+ // outside the CPU still checks this function, so it will
+ // always return false to keep everything working.
+ virtual bool misspeculating() { return false; }
+
+#if !FULL_SYSTEM
+ virtual IntReg getSyscallArg(int i);
+
+ virtual void setSyscallArg(int i, IntReg val);
+
+ virtual void setSyscallReturn(SyscallReturn return_value);
+
+ virtual void syscall() { return cpu->syscall(thread->tid); }
+
+ virtual Counter readFuncExeInst() { return thread->funcExeInst; }
+#endif
+ };
#if FULL_SYSTEM
+ /** ITB pointer. */
AlphaITB *itb;
+ /** DTB pointer. */
AlphaDTB *dtb;
#endif
- public:
+ /** Registers statistics. */
void regStats();
#if FULL_SYSTEM
- //Note that the interrupt stuff from the base CPU might be somewhat
- //ISA specific (ie NumInterruptLevels). These functions might not
- //be needed in FullCPU though.
-// void post_interrupt(int int_num, int index);
-// void clear_interrupt(int int_num, int index);
-// void clear_interrupts();
-
+ /** Translates instruction requestion. */
Fault translateInstReq(MemReqPtr &req)
{
return itb->translate(req);
}
+ /** Translates data read request. */
Fault translateDataReadReq(MemReqPtr &req)
{
return dtb->translate(req, false);
}
+ /** Translates data write request. */
Fault translateDataWriteReq(MemReqPtr &req)
{
return dtb->translate(req, true);
@@ -95,141 +241,113 @@ class AlphaFullCPU : public FullO3CPU<Impl>
return NoFault;
}
+ /** Translates instruction requestion in syscall emulation mode. */
Fault translateInstReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
+ /** Translates data read request in syscall emulation mode. */
Fault translateDataReadReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
+ /** Translates data write request in syscall emulation mode. */
Fault translateDataWriteReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
#endif
+ MiscReg readMiscReg(int misc_reg, unsigned tid);
- // Later on may want to remove this misc stuff from the regfile and
- // have it handled at this level. Might prove to be an issue when
- // trying to rename source/destination registers...
- MiscReg readMiscReg(int misc_reg)
- {
- // Dummy function for now.
- // @todo: Fix this once reg file gets fixed.
- return 0;
- }
+ MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid);
- Fault setMiscReg(int misc_reg, const MiscReg &val)
- {
- // Dummy function for now.
- // @todo: Fix this once reg file gets fixed.
- return NoFault;
- }
+ Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
+
+ Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
+
+ void squashFromXC(unsigned tid);
- // Most of the full system code and syscall emulation is not yet
- // implemented. These functions do show what the final interface will
- // look like.
#if FULL_SYSTEM
+ void post_interrupt(int int_num, int index);
+
int readIntrFlag();
+ /** Sets the interrupt flags. */
void setIntrFlag(int val);
- Fault hwrei();
- bool inPalMode() { return AlphaISA::PcPAL(this->regFile.readPC()); }
+ /** HW return from error interrupt. */
+ Fault hwrei(unsigned tid);
+ /** Returns if a specific PC is a PAL mode PC. */
bool inPalMode(uint64_t PC)
{ return AlphaISA::PcPAL(PC); }
- void trap(Fault fault);
- bool simPalCheck(int palFunc);
+ /** Traps to handle given fault. */
+ void trap(Fault fault, unsigned tid);
+ bool simPalCheck(int palFunc, unsigned tid);
+ /** Processes any interrupts. */
void processInterrupts();
-#endif
-
-
-#if !FULL_SYSTEM
- // Need to change these into regfile calls that directly set a certain
- // register. Actually, these functions should handle most of this
- // functionality by themselves; should look up the rename and then
- // set the register.
- IntReg getSyscallArg(int i)
- {
- return this->cpuXC->readIntReg(AlphaISA::ArgumentReg0 + i);
- }
-
- // used to shift args for indirect syscall
- void setSyscallArg(int i, IntReg val)
- {
- this->cpuXC->setIntReg(AlphaISA::ArgumentReg0 + i, val);
- }
-
- void setSyscallReturn(int64_t return_value)
- {
- // check for error condition. Alpha syscall convention is to
- // indicate success/failure in reg a3 (r19) and put the
- // return value itself in the standard return value reg (v0).
- const int RegA3 = 19; // only place this is used
- if (return_value >= 0) {
- // no error
- this->cpuXC->setIntReg(RegA3, 0);
- this->cpuXC->setIntReg(AlphaISA::ReturnValueReg, return_value);
- } else {
- // got an error, return details
- this->cpuXC->setIntReg(RegA3, (IntReg) -1);
- this->cpuXC->setIntReg(AlphaISA::ReturnValueReg, -return_value);
- }
- }
-
- void syscall(short thread_num);
- void squashStages();
+ /** Halts the CPU. */
+ void halt() { panic("Halt not implemented!\n"); }
#endif
- void copyToXC();
- void copyFromXC();
-
- public:
-#if FULL_SYSTEM
- bool palShadowEnabled;
-
- // Not sure this is used anywhere.
- void intr_post(RegFile *regs, Fault fault, Addr pc);
- // Actually used within exec files. Implement properly.
- void swapPALShadow(bool use_shadow);
- // Called by CPU constructor. Can implement as I please.
- void initCPU(RegFile *regs);
- // Called by initCPU. Implement as I please.
- void initIPRs(RegFile *regs);
- void halt() { panic("Halt not implemented!\n"); }
+#if !FULL_SYSTEM
+ /** Executes a syscall.
+ * @todo: Determine if this needs to be virtual.
+ */
+ void syscall(int thread_num);
+ /** Gets a syscall argument. */
+ IntReg getSyscallArg(int i, int tid);
+
+ /** Used to shift args for indirect syscall. */
+ void setSyscallArg(int i, IntReg val, int tid);
+
+ /** Sets the return value of a syscall. */
+ void setSyscallReturn(SyscallReturn return_value, int tid);
#endif
-
+ /** Read from memory function. */
template <class T>
Fault read(MemReqPtr &req, T &data)
{
+#if 0
#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
if (req->flags & LOCKED) {
req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
}
#endif
-
+#endif
Fault error;
+
+#if FULL_SYSTEM
+ // @todo: Fix this LL/SC hack.
+ if (req->flags & LOCKED) {
+ lockAddr = req->paddr;
+ lockFlag = true;
+ }
+#endif
+
error = this->mem->read(req, data);
data = gtoh(data);
return error;
}
+ /** CPU read function, forwards read to LSQ. */
template <class T>
Fault read(MemReqPtr &req, T &data, int load_idx)
{
return this->iew.ldstQueue.read(req, data, load_idx);
}
+ /** Write to memory function. */
template <class T>
Fault write(MemReqPtr &req, T &data)
{
+#if 0
#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
ExecContext *xc;
@@ -276,16 +394,37 @@ class AlphaFullCPU : public FullO3CPU<Impl>
}
#endif
+#endif
+
+#if FULL_SYSTEM
+ // @todo: Fix this LL/SC hack.
+ if (req->flags & LOCKED) {
+ if (req->flags & UNCACHEABLE) {
+ req->result = 2;
+ } else {
+ if (this->lockFlag) {
+ req->result = 1;
+ } else {
+ req->result = 0;
+ return NoFault;
+ }
+ }
+ }
+#endif
return this->mem->write(req, (T)htog(data));
}
+ /** CPU write function, forwards write to LSQ. */
template <class T>
Fault write(MemReqPtr &req, T &data, int store_idx)
{
return this->iew.ldstQueue.write(req, data, store_idx);
}
+ Addr lockAddr;
+
+ bool lockFlag;
};
-#endif // __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
+#endif // __CPU_O3_ALPHA_FULL_CPU_HH__
diff --git a/src/cpu/o3/alpha_cpu_builder.cc b/src/cpu/o3/alpha_cpu_builder.cc
index 6025b8ef2..b0d812edc 100644
--- a/src/cpu/o3/alpha_cpu_builder.cc
+++ b/src/cpu/o3/alpha_cpu_builder.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,39 +26,20 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "base/inifile.hh"
-#include "base/loader/symtab.hh"
-#include "base/misc.hh"
+#include <string>
+
#include "cpu/base.hh"
-#include "cpu/exetrace.hh"
#include "cpu/o3/alpha_cpu.hh"
#include "cpu/o3/alpha_impl.hh"
-#include "mem/base_mem.hh"
+#include "cpu/o3/alpha_params.hh"
+#include "cpu/o3/fu_pool.hh"
#include "mem/cache/base_cache.hh"
-#include "mem/mem_interface.hh"
#include "sim/builder.hh"
-#include "sim/debug.hh"
-#include "sim/host.hh"
-#include "sim/process.hh"
-#include "sim/sim_events.hh"
-#include "sim/sim_object.hh"
-#include "sim/stats.hh"
-
-#if FULL_SYSTEM
-#include "base/remote_gdb.hh"
-#include "mem/functional/memory_control.hh"
-#include "mem/functional/physical.hh"
-#include "sim/system.hh"
-#include "arch/tlb.hh"
-#include "arch/vtophys.hh"
-#else // !FULL_SYSTEM
-#include "mem/functional/functional.hh"
-#endif // FULL_SYSTEM
class DerivAlphaFullCPU : public AlphaFullCPU<AlphaSimpleImpl>
{
public:
- DerivAlphaFullCPU(AlphaSimpleParams p)
+ DerivAlphaFullCPU(AlphaSimpleParams *p)
: AlphaFullCPU<AlphaSimpleImpl>(p)
{ }
};
@@ -67,6 +48,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
Param<int> clock;
Param<int> numThreads;
+Param<int> activity;
#if FULL_SYSTEM
SimObjectParam<System *> system;
@@ -75,9 +57,13 @@ SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
#else
SimObjectVectorParam<Process *> workload;
+//SimObjectParam<PageTable *> page_table;
#endif // FULL_SYSTEM
+
SimObjectParam<FunctionalMemory *> mem;
+SimObjectParam<BaseCPU *> checker;
+
Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
@@ -86,6 +72,8 @@ Param<Counter> max_loads_all_threads;
SimObjectParam<BaseCache *> icache;
SimObjectParam<BaseCache *> dcache;
+Param<unsigned> cachePorts;
+
Param<unsigned> decodeToFetchDelay;
Param<unsigned> renameToFetchDelay;
Param<unsigned> iewToFetchDelay;
@@ -112,25 +100,24 @@ Param<unsigned> executeIntWidth;
Param<unsigned> executeFloatWidth;
Param<unsigned> executeBranchWidth;
Param<unsigned> executeMemoryWidth;
+SimObjectParam<FUPool *> fuPool;
Param<unsigned> iewToCommitDelay;
Param<unsigned> renameToROBDelay;
Param<unsigned> commitWidth;
Param<unsigned> squashWidth;
+Param<Tick> trapLatency;
+Param<Tick> fetchTrapLatency;
-#if 0
Param<unsigned> localPredictorSize;
-Param<unsigned> localPredictorCtrBits;
-#endif
-Param<unsigned> local_predictor_size;
-Param<unsigned> local_ctr_bits;
-Param<unsigned> local_history_table_size;
-Param<unsigned> local_history_bits;
-Param<unsigned> global_predictor_size;
-Param<unsigned> global_ctr_bits;
-Param<unsigned> global_history_bits;
-Param<unsigned> choice_predictor_size;
-Param<unsigned> choice_ctr_bits;
+Param<unsigned> localCtrBits;
+Param<unsigned> localHistoryTableSize;
+Param<unsigned> localHistoryBits;
+Param<unsigned> globalPredictorSize;
+Param<unsigned> globalCtrBits;
+Param<unsigned> globalHistoryBits;
+Param<unsigned> choicePredictorSize;
+Param<unsigned> choiceCtrBits;
Param<unsigned> BTBEntries;
Param<unsigned> BTBTagSize;
@@ -147,6 +134,16 @@ Param<unsigned> numPhysFloatRegs;
Param<unsigned> numIQEntries;
Param<unsigned> numROBEntries;
+Param<unsigned> smtNumFetchingThreads;
+Param<std::string> smtFetchPolicy;
+Param<std::string> smtLSQPolicy;
+Param<unsigned> smtLSQThreshold;
+Param<std::string> smtIQPolicy;
+Param<unsigned> smtIQThreshold;
+Param<std::string> smtROBPolicy;
+Param<unsigned> smtROBThreshold;
+Param<std::string> smtCommitPolicy;
+
Param<unsigned> instShiftAmt;
Param<bool> defer_registration;
@@ -160,6 +157,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
INIT_PARAM(clock, "clock speed"),
INIT_PARAM(numThreads, "number of HW thread contexts"),
+ INIT_PARAM_DFLT(activity, "Initial activity count", 0),
#if FULL_SYSTEM
INIT_PARAM(system, "System object"),
@@ -168,10 +166,13 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
INIT_PARAM(dtb, "Data translation buffer"),
#else
INIT_PARAM(workload, "Processes to run"),
+// INIT_PARAM(page_table, "Page table"),
#endif // FULL_SYSTEM
INIT_PARAM_DFLT(mem, "Memory", NULL),
+ INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
+
INIT_PARAM_DFLT(max_insts_any_thread,
"Terminate when any thread reaches this inst count",
0),
@@ -190,13 +191,14 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
+ INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
+
INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
"delay"),
INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
INIT_PARAM(fetchWidth, "Fetch width"),
-
INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
"delay"),
@@ -222,27 +224,25 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
INIT_PARAM(executeFloatWidth, "Floating point execute width"),
INIT_PARAM(executeBranchWidth, "Branch execute width"),
INIT_PARAM(executeMemoryWidth, "Memory execute width"),
+ INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
"delay"),
INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
INIT_PARAM(commitWidth, "Commit width"),
INIT_PARAM(squashWidth, "Squash width"),
-
-#if 0
- INIT_PARAM(localPredictorSize, "Size of the local predictor in entries. "
- "Must be a power of 2."),
- INIT_PARAM(localPredictorCtrBits, "Number of bits per counter for bpred"),
-#endif
- INIT_PARAM(local_predictor_size, "Size of local predictor"),
- INIT_PARAM(local_ctr_bits, "Bits per counter"),
- INIT_PARAM(local_history_table_size, "Size of local history table"),
- INIT_PARAM(local_history_bits, "Bits for the local history"),
- INIT_PARAM(global_predictor_size, "Size of global predictor"),
- INIT_PARAM(global_ctr_bits, "Bits per counter"),
- INIT_PARAM(global_history_bits, "Bits of history"),
- INIT_PARAM(choice_predictor_size, "Size of choice predictor"),
- INIT_PARAM(choice_ctr_bits, "Bits of choice counters"),
+ INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
+ INIT_PARAM_DFLT(fetchTrapLatency, "Number of cycles before the fetch trap is handled", 12),
+
+ INIT_PARAM(localPredictorSize, "Size of local predictor"),
+ INIT_PARAM(localCtrBits, "Bits per counter"),
+ INIT_PARAM(localHistoryTableSize, "Size of local history table"),
+ INIT_PARAM(localHistoryBits, "Bits for the local history"),
+ INIT_PARAM(globalPredictorSize, "Size of global predictor"),
+ INIT_PARAM(globalCtrBits, "Bits per counter"),
+ INIT_PARAM(globalHistoryBits, "Bits of history"),
+ INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
+ INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
INIT_PARAM(BTBEntries, "Number of BTB entries"),
INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
@@ -260,6 +260,16 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
+ INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
+ INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
+ INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
+ INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
+ INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
+ INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
+ INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
+ INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
+ INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
+
INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
@@ -287,101 +297,116 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
#endif
- AlphaSimpleParams params;
+ AlphaSimpleParams *params = new AlphaSimpleParams;
- params.clock = clock;
+ params->clock = clock;
- params.name = getInstanceName();
- params.numberOfThreads = actual_num_threads;
+ params->name = getInstanceName();
+ params->numberOfThreads = actual_num_threads;
+ params->activity = activity;
#if FULL_SYSTEM
- params.system = system;
- params.cpu_id = cpu_id;
- params.itb = itb;
- params.dtb = dtb;
+ params->system = system;
+ params->cpu_id = cpu_id;
+ params->itb = itb;
+ params->dtb = dtb;
#else
- params.workload = workload;
+ params->workload = workload;
+// params->pTable = page_table;
#endif // FULL_SYSTEM
- params.mem = mem;
+ params->mem = mem;
- params.max_insts_any_thread = max_insts_any_thread;
- params.max_insts_all_threads = max_insts_all_threads;
- params.max_loads_any_thread = max_loads_any_thread;
- params.max_loads_all_threads = max_loads_all_threads;
+ params->checker = checker;
+
+ params->max_insts_any_thread = max_insts_any_thread;
+ params->max_insts_all_threads = max_insts_all_threads;
+ params->max_loads_any_thread = max_loads_any_thread;
+ params->max_loads_all_threads = max_loads_all_threads;
//
// Caches
//
- params.icacheInterface = icache ? icache->getInterface() : NULL;
- params.dcacheInterface = dcache ? dcache->getInterface() : NULL;
-
- params.decodeToFetchDelay = decodeToFetchDelay;
- params.renameToFetchDelay = renameToFetchDelay;
- params.iewToFetchDelay = iewToFetchDelay;
- params.commitToFetchDelay = commitToFetchDelay;
- params.fetchWidth = fetchWidth;
-
- params.renameToDecodeDelay = renameToDecodeDelay;
- params.iewToDecodeDelay = iewToDecodeDelay;
- params.commitToDecodeDelay = commitToDecodeDelay;
- params.fetchToDecodeDelay = fetchToDecodeDelay;
- params.decodeWidth = decodeWidth;
-
- params.iewToRenameDelay = iewToRenameDelay;
- params.commitToRenameDelay = commitToRenameDelay;
- params.decodeToRenameDelay = decodeToRenameDelay;
- params.renameWidth = renameWidth;
-
- params.commitToIEWDelay = commitToIEWDelay;
- params.renameToIEWDelay = renameToIEWDelay;
- params.issueToExecuteDelay = issueToExecuteDelay;
- params.issueWidth = issueWidth;
- params.executeWidth = executeWidth;
- params.executeIntWidth = executeIntWidth;
- params.executeFloatWidth = executeFloatWidth;
- params.executeBranchWidth = executeBranchWidth;
- params.executeMemoryWidth = executeMemoryWidth;
-
- params.iewToCommitDelay = iewToCommitDelay;
- params.renameToROBDelay = renameToROBDelay;
- params.commitWidth = commitWidth;
- params.squashWidth = squashWidth;
-#if 0
- params.localPredictorSize = localPredictorSize;
- params.localPredictorCtrBits = localPredictorCtrBits;
-#endif
- params.local_predictor_size = local_predictor_size;
- params.local_ctr_bits = local_ctr_bits;
- params.local_history_table_size = local_history_table_size;
- params.local_history_bits = local_history_bits;
- params.global_predictor_size = global_predictor_size;
- params.global_ctr_bits = global_ctr_bits;
- params.global_history_bits = global_history_bits;
- params.choice_predictor_size = choice_predictor_size;
- params.choice_ctr_bits = choice_ctr_bits;
-
- params.BTBEntries = BTBEntries;
- params.BTBTagSize = BTBTagSize;
-
- params.RASSize = RASSize;
-
- params.LQEntries = LQEntries;
- params.SQEntries = SQEntries;
- params.SSITSize = SSITSize;
- params.LFSTSize = LFSTSize;
-
- params.numPhysIntRegs = numPhysIntRegs;
- params.numPhysFloatRegs = numPhysFloatRegs;
- params.numIQEntries = numIQEntries;
- params.numROBEntries = numROBEntries;
-
- params.instShiftAmt = 2;
-
- params.defReg = defer_registration;
-
- params.functionTrace = function_trace;
- params.functionTraceStart = function_trace_start;
+ params->icacheInterface = icache ? icache->getInterface() : NULL;
+ params->dcacheInterface = dcache ? dcache->getInterface() : NULL;
+ params->cachePorts = cachePorts;
+
+ params->decodeToFetchDelay = decodeToFetchDelay;
+ params->renameToFetchDelay = renameToFetchDelay;
+ params->iewToFetchDelay = iewToFetchDelay;
+ params->commitToFetchDelay = commitToFetchDelay;
+ params->fetchWidth = fetchWidth;
+
+ params->renameToDecodeDelay = renameToDecodeDelay;
+ params->iewToDecodeDelay = iewToDecodeDelay;
+ params->commitToDecodeDelay = commitToDecodeDelay;
+ params->fetchToDecodeDelay = fetchToDecodeDelay;
+ params->decodeWidth = decodeWidth;
+
+ params->iewToRenameDelay = iewToRenameDelay;
+ params->commitToRenameDelay = commitToRenameDelay;
+ params->decodeToRenameDelay = decodeToRenameDelay;
+ params->renameWidth = renameWidth;
+
+ params->commitToIEWDelay = commitToIEWDelay;
+ params->renameToIEWDelay = renameToIEWDelay;
+ params->issueToExecuteDelay = issueToExecuteDelay;
+ params->issueWidth = issueWidth;
+ params->executeWidth = executeWidth;
+ params->executeIntWidth = executeIntWidth;
+ params->executeFloatWidth = executeFloatWidth;
+ params->executeBranchWidth = executeBranchWidth;
+ params->executeMemoryWidth = executeMemoryWidth;
+ params->fuPool = fuPool;
+
+ params->iewToCommitDelay = iewToCommitDelay;
+ params->renameToROBDelay = renameToROBDelay;
+ params->commitWidth = commitWidth;
+ params->squashWidth = squashWidth;
+ params->trapLatency = trapLatency;
+ params->fetchTrapLatency = fetchTrapLatency;
+
+ params->localPredictorSize = localPredictorSize;
+ params->localCtrBits = localCtrBits;
+ params->localHistoryTableSize = localHistoryTableSize;
+ params->localHistoryBits = localHistoryBits;
+ params->globalPredictorSize = globalPredictorSize;
+ params->globalCtrBits = globalCtrBits;
+ params->globalHistoryBits = globalHistoryBits;
+ params->choicePredictorSize = choicePredictorSize;
+ params->choiceCtrBits = choiceCtrBits;
+
+ params->BTBEntries = BTBEntries;
+ params->BTBTagSize = BTBTagSize;
+
+ params->RASSize = RASSize;
+
+ params->LQEntries = LQEntries;
+ params->SQEntries = SQEntries;
+
+ params->SSITSize = SSITSize;
+ params->LFSTSize = LFSTSize;
+
+ params->numPhysIntRegs = numPhysIntRegs;
+ params->numPhysFloatRegs = numPhysFloatRegs;
+ params->numIQEntries = numIQEntries;
+ params->numROBEntries = numROBEntries;
+
+ params->smtNumFetchingThreads = smtNumFetchingThreads;
+ params->smtFetchPolicy = smtFetchPolicy;
+ params->smtIQPolicy = smtIQPolicy;
+ params->smtLSQPolicy = smtLSQPolicy;
+ params->smtLSQThreshold = smtLSQThreshold;
+ params->smtROBPolicy = smtROBPolicy;
+ params->smtROBThreshold = smtROBThreshold;
+ params->smtCommitPolicy = smtCommitPolicy;
+
+ params->instShiftAmt = 2;
+
+ params->deferRegistration = defer_registration;
+
+ params->functionTrace = function_trace;
+ params->functionTraceStart = function_trace_start;
cpu = new DerivAlphaFullCPU(params);
diff --git a/src/cpu/o3/alpha_cpu_impl.hh b/src/cpu/o3/alpha_cpu_impl.hh
index 7c4c2b969..f7f0a3842 100644
--- a/src/cpu/o3/alpha_cpu_impl.hh
+++ b/src/cpu/o3/alpha_cpu_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,27 +30,96 @@
#include "base/cprintf.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
-#include "mem/cache/cache.hh" // for dynamic cast
+#include "cpu/checker/exec_context.hh"
#include "mem/mem_interface.hh"
-#include "sim/builder.hh"
#include "sim/sim_events.hh"
#include "sim/stats.hh"
#include "cpu/o3/alpha_cpu.hh"
#include "cpu/o3/alpha_params.hh"
#include "cpu/o3/comm.hh"
+#include "cpu/o3/thread_state.hh"
#if FULL_SYSTEM
#include "arch/alpha/osfpal.hh"
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
+#include "cpu/quiesce_event.hh"
+#include "kern/kernel_stats.hh"
#endif
+using namespace TheISA;
+
template <class Impl>
-AlphaFullCPU<Impl>::AlphaFullCPU(Params &params)
+AlphaFullCPU<Impl>::AlphaFullCPU(Params *params)
+#if FULL_SYSTEM
+ : FullO3CPU<Impl>(params), itb(params->itb), dtb(params->dtb)
+#else
: FullO3CPU<Impl>(params)
+#endif
{
DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n");
+ this->thread.resize(this->numThreads);
+
+ for (int i = 0; i < this->numThreads; ++i) {
+#if FULL_SYSTEM
+ assert(this->numThreads == 1);
+ this->thread[i] = new Thread(this, 0, params->mem);
+ this->thread[i]->setStatus(ExecContext::Suspended);
+#else
+ if (i < params->workload.size()) {
+ DPRINTF(FullCPU, "FullCPU: Workload[%i]'s starting PC is %#x, "
+ "process is %#x",
+ i, params->workload[i]->prog_entry, this->thread[i]);
+ this->thread[i] = new Thread(this, i, params->workload[i], i);
+ assert(params->workload[i]->getMemory() != NULL);
+
+ this->thread[i]->setStatus(ExecContext::Suspended);
+ //usedTids[i] = true;
+ //threadMap[i] = i;
+ } else {
+ //Allocate Empty execution context so M5 can use later
+ //when scheduling threads to CPU
+ Process* dummy_proc = NULL;
+
+ this->thread[i] = new Thread(this, i, dummy_proc, i);
+ //usedTids[i] = false;
+ }
+#endif // !FULL_SYSTEM
+
+ this->thread[i]->numInst = 0;
+
+ ExecContext *xc_proxy;
+
+ AlphaXC *alpha_xc_proxy = new AlphaXC;
+
+ if (params->checker) {
+ xc_proxy = new CheckerExecContext<AlphaXC>(alpha_xc_proxy, this->checker);
+ } else {
+ xc_proxy = alpha_xc_proxy;
+ }
+
+ alpha_xc_proxy->cpu = this;
+ alpha_xc_proxy->thread = this->thread[i];
+
+#if FULL_SYSTEM
+ this->thread[i]->quiesceEvent =
+ new EndQuiesceEvent(xc_proxy);
+ this->thread[i]->lastActivate = 0;
+ this->thread[i]->lastSuspend = 0;
+#endif
+ this->thread[i]->xcProxy = xc_proxy;
+
+ this->execContexts.push_back(xc_proxy);
+ }
+
+
+ for (int i=0; i < this->numThreads; i++) {
+ this->thread[i]->funcExeInst = 0;
+ }
+
+ // Sets CPU pointers. These must be set at this level because the CPU
+ // pointers are defined to be the highest level of CPU class.
this->fetch.setCPU(this);
this->decode.setCPU(this);
this->rename.setCPU(this);
@@ -58,6 +127,10 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params &params)
this->commit.setCPU(this);
this->rob.setCPU(this);
+ this->regFile.setCPU(this);
+
+ lockAddr = 0;
+ lockFlag = false;
}
template <class Impl>
@@ -73,179 +146,460 @@ AlphaFullCPU<Impl>::regStats()
this->commit.regStats();
}
-#if !FULL_SYSTEM
+#if FULL_SYSTEM
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::dumpFuncProfile()
+{
+ // Currently not supported
+}
+#endif
-// Will probably need to know which thread is calling syscall
-// Will need to pass that information in to the DynInst when it is constructed,
-// so that this call can be made with the proper thread number.
template <class Impl>
void
-AlphaFullCPU<Impl>::syscall(short thread_num)
+AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context)
{
- DPRINTF(FullCPU, "AlphaFullCPU: Syscall() called.\n\n");
+ // some things should already be set up
+ assert(getMemPtr() == old_context->getMemPtr());
+#if FULL_SYSTEM
+ assert(getSystemPtr() == old_context->getSystemPtr());
+#else
+ assert(getProcessPtr() == old_context->getProcessPtr());
+#endif
- // Commit stage needs to run as well.
- this->commit.tick();
+ // copy over functional state
+ setStatus(old_context->status());
+ copyArchRegs(old_context);
+ setCpuId(old_context->readCpuId());
+#if !FULL_SYSTEM
+ thread->funcExeInst = old_context->readFuncExeInst();
+#else
+ EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
+ if (other_quiesce) {
+ // Point the quiesce event's XC at this XC so that it wakes up
+ // the proper CPU.
+ other_quiesce->xc = this;
+ }
+ if (thread->quiesceEvent) {
+ thread->quiesceEvent->xc = this;
+ }
- squashStages();
+ // Transfer kernel stats from one CPU to the other.
+ thread->kernelStats = old_context->getKernelStats();
+// storeCondFailures = 0;
+ cpu->lockFlag = false;
+#endif
- // Temporarily increase this by one to account for the syscall
- // instruction.
- ++(this->funcExeInst);
+ old_context->setStatus(ExecContext::Unallocated);
+
+ thread->inSyscall = false;
+ thread->trapPending = false;
+}
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::activate(int delay)
+{
+ DPRINTF(FullCPU, "Calling activate on AlphaXC\n");
- // Copy over all important state to xc once all the unrolling is done.
- copyToXC();
+ if (thread->status() == ExecContext::Active)
+ return;
- // This is hardcoded to thread 0 while the CPU is only single threaded.
- this->thread[0]->syscall();
+#if FULL_SYSTEM
+ thread->lastActivate = curTick;
+#endif
- // Copy over all important state back to CPU.
- copyFromXC();
+ if (thread->status() == ExecContext::Unallocated) {
+ cpu->activateWhenReady(thread->tid);
+ return;
+ }
- // Decrease funcExeInst by one as the normal commit will handle
- // incrememnting it.
- --(this->funcExeInst);
+ thread->setStatus(ExecContext::Active);
+
+ // status() == Suspended
+ cpu->activateContext(thread->tid, delay);
}
-// This is not a pretty function, and should only be used if it is necessary
-// to fake having everything squash all at once (ie for non-full system
-// syscalls). Maybe put this at the FullCPU level?
template <class Impl>
void
-AlphaFullCPU<Impl>::squashStages()
+AlphaFullCPU<Impl>::AlphaXC::suspend()
{
- InstSeqNum rob_head = this->rob.readHeadSeqNum();
+ DPRINTF(FullCPU, "Calling suspend on AlphaXC\n");
- // Now hack the time buffer to put this sequence number in the places
- // where the stages might read it.
- for (int i = 0; i < 5; ++i)
- {
- this->timeBuffer.access(-i)->commitInfo.doneSeqNum = rob_head;
+ if (thread->status() == ExecContext::Suspended)
+ return;
+
+#if FULL_SYSTEM
+ thread->lastActivate = curTick;
+ thread->lastSuspend = curTick;
+#endif
+/*
+#if FULL_SYSTEM
+ // Don't change the status from active if there are pending interrupts
+ if (cpu->check_interrupts()) {
+ assert(status() == ExecContext::Active);
+ return;
}
+#endif
+*/
+ thread->setStatus(ExecContext::Suspended);
+ cpu->suspendContext(thread->tid);
+}
- this->fetch.squash(this->rob.readHeadNextPC());
- this->fetchQueue.advance();
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::deallocate()
+{
+ DPRINTF(FullCPU, "Calling deallocate on AlphaXC\n");
- this->decode.squash();
- this->decodeQueue.advance();
+ if (thread->status() == ExecContext::Unallocated)
+ return;
- this->rename.squash();
- this->renameQueue.advance();
- this->renameQueue.advance();
+ thread->setStatus(ExecContext::Unallocated);
+ cpu->deallocateContext(thread->tid);
+}
- // Be sure to advance the IEW queues so that the commit stage doesn't
- // try to set an instruction as completed at the same time that it
- // might be deleting it.
- this->iew.squash();
- this->iewQueue.advance();
- this->iewQueue.advance();
- // Needs to tell the LSQ to write back all of its data
- this->iew.lsqWriteback();
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::halt()
+{
+ DPRINTF(FullCPU, "Calling halt on AlphaXC\n");
- this->rob.squash(rob_head);
- this->commit.setSquashing();
+ if (thread->status() == ExecContext::Halted)
+ return;
- // Now hack the time buffer to clear the sequence numbers in the places
- // where the stages might read it.?
- for (int i = 0; i < 5; ++i)
- {
- this->timeBuffer.access(-i)->commitInfo.doneSeqNum = 0;
- }
+ thread->setStatus(ExecContext::Halted);
+ cpu->haltContext(thread->tid);
+}
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::regStats(const std::string &name)
+{
+#if FULL_SYSTEM
+ thread->kernelStats = new Kernel::Statistics(cpu->system);
+ thread->kernelStats->regStats(name + ".kern");
+#endif
}
-#endif // FULL_SYSTEM
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::serialize(std::ostream &os)
+{
+#if FULL_SYSTEM
+ if (thread->kernelStats)
+ thread->kernelStats->serialize(os);
+#endif
+
+}
template <class Impl>
void
-AlphaFullCPU<Impl>::copyToXC()
+AlphaFullCPU<Impl>::AlphaXC::unserialize(Checkpoint *cp, const std::string &section)
{
- PhysRegIndex renamed_reg;
+#if FULL_SYSTEM
+ if (thread->kernelStats)
+ thread->kernelStats->unserialize(cp, section);
+#endif
- // First loop through the integer registers.
- for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
- {
- renamed_reg = this->renameMap.lookup(i);
- this->cpuXC->setIntReg(i, this->regFile.readIntReg(renamed_reg));
- DPRINTF(FullCPU, "FullCPU: Copying register %i, has data %lli.\n",
- renamed_reg, this->regFile.intRegFile[renamed_reg]);
- }
+}
- // Then loop through the floating point registers.
- for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
- {
- renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
- this->cpuXC->setFloatRegBits(i,
- this->regFile.readFloatRegBits(renamed_reg));
- }
+#if FULL_SYSTEM
+template <class Impl>
+EndQuiesceEvent *
+AlphaFullCPU<Impl>::AlphaXC::getQuiesceEvent()
+{
+ return thread->quiesceEvent;
+}
- this->cpuXC->setMiscReg(AlphaISA::Fpcr_DepTag,
- this->regFile.readMiscReg(AlphaISA::Fpcr_DepTag));
- this->cpuXC->setMiscReg(AlphaISA::Uniq_DepTag,
- this->regFile.readMiscReg(AlphaISA::Uniq_DepTag));
- this->cpuXC->setMiscReg(AlphaISA::Lock_Flag_DepTag,
- this->regFile.readMiscReg(AlphaISA::Lock_Flag_DepTag));
- this->cpuXC->setMiscReg(AlphaISA::Lock_Addr_DepTag,
- this->regFile.readMiscReg(AlphaISA::Lock_Addr_DepTag));
+template <class Impl>
+Tick
+AlphaFullCPU<Impl>::AlphaXC::readLastActivate()
+{
+ return thread->lastActivate;
+}
- this->cpuXC->setPC(this->rob.readHeadPC());
- this->cpuXC->setNextPC(this->cpuXC->readPC()+4);
+template <class Impl>
+Tick
+AlphaFullCPU<Impl>::AlphaXC::readLastSuspend()
+{
+ return thread->lastSuspend;
+}
-#if !FULL_SYSTEM
- this->cpuXC->setFuncExeInst(this->funcExeInst);
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::profileClear()
+{}
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::profileSample()
+{}
#endif
+
+template <class Impl>
+TheISA::MachInst
+AlphaFullCPU<Impl>::AlphaXC:: getInst()
+{
+ return thread->inst;
}
-// This function will probably mess things up unless the ROB is empty and
-// there are no instructions in the pipeline.
template <class Impl>
void
-AlphaFullCPU<Impl>::copyFromXC()
+AlphaFullCPU<Impl>::AlphaXC::copyArchRegs(ExecContext *xc)
{
+ // This function will mess things up unless the ROB is empty and
+ // there are no instructions in the pipeline.
+ unsigned tid = thread->tid;
PhysRegIndex renamed_reg;
// First loop through the integer registers.
- for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
- {
- renamed_reg = this->renameMap.lookup(i);
+ for (int i = 0; i < AlphaISA::NumIntRegs; ++i) {
+ renamed_reg = cpu->renameMap[tid].lookup(i);
DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, "
"now has data %lli.\n",
- renamed_reg, this->regFile.intRegFile[renamed_reg],
- this->cpuXC->readIntReg(i));
+ renamed_reg, cpu->readIntReg(renamed_reg),
+ xc->readIntReg(i));
- this->regFile.setIntReg(renamed_reg, this->cpuXC->readIntReg(i));
+ cpu->setIntReg(renamed_reg, xc->readIntReg(i));
}
// Then loop through the floating point registers.
for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
{
renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
- this->regFile.setFloatRegBits(renamed_reg,
- this->cpuXC->readFloatRegBits(i));
+ this->cpuXC->setFloatRegBits(i,
+ this->regFile.readFloatRegBits(renamed_reg));
}
- // Then loop through the misc registers.
- this->regFile.setMiscReg(AlphaISA::Fpcr_DepTag,
- this->cpuXC->readMiscReg(AlphaISA::Fpcr_DepTag));
- this->regFile.setMiscReg(AlphaISA::Uniq_DepTag,
- this->cpuXC->readMiscReg(AlphaISA::Uniq_DepTag));
- this->regFile.setMiscReg(AlphaISA::Lock_Flag_DepTag,
- this->cpuXC->readMiscReg(AlphaISA::Lock_Flag_DepTag));
- this->regFile.setMiscReg(AlphaISA::Lock_Addr_DepTag,
- this->cpuXC->readMiscReg(AlphaISA::Lock_Addr_DepTag));
+ // Copy the misc regs.
+ cpu->regFile.miscRegs[tid].copyMiscRegs(xc);
// Then finally set the PC and the next PC.
-// regFile.pc = cpuXC->regs.pc;
-// regFile.npc = cpuXC->regs.npc;
+ cpu->setPC(xc->readPC(), tid);
+ cpu->setNextPC(xc->readNextPC(), tid);
#if !FULL_SYSTEM
- this->funcExeInst = this->cpuXC->readFuncExeInst();
+ this->thread->funcExeInst = xc->readFuncExeInst();
#endif
}
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::clearArchRegs()
+{}
+
+template <class Impl>
+uint64_t
+AlphaFullCPU<Impl>::AlphaXC::readIntReg(int reg_idx)
+{
+ DPRINTF(Fault, "Reading int register through the XC!\n");
+ return cpu->readArchIntReg(reg_idx, thread->tid);
+}
+
+template <class Impl>
+float
+AlphaFullCPU<Impl>::AlphaXC::readFloatRegSingle(int reg_idx)
+{
+ DPRINTF(Fault, "Reading float register through the XC!\n");
+ return cpu->readArchFloatRegSingle(reg_idx, thread->tid);
+}
+
+template <class Impl>
+double
+AlphaFullCPU<Impl>::AlphaXC::readFloatRegDouble(int reg_idx)
+{
+ DPRINTF(Fault, "Reading float register through the XC!\n");
+ return cpu->readArchFloatRegDouble(reg_idx, thread->tid);
+}
+
+template <class Impl>
+uint64_t
+AlphaFullCPU<Impl>::AlphaXC::readFloatRegInt(int reg_idx)
+{
+ DPRINTF(Fault, "Reading floatint register through the XC!\n");
+ return cpu->readArchFloatRegInt(reg_idx, thread->tid);
+}
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::setIntReg(int reg_idx, uint64_t val)
+{
+ DPRINTF(Fault, "Setting int register through the XC!\n");
+ cpu->setArchIntReg(reg_idx, val, thread->tid);
+
+ if (!thread->trapPending && !thread->inSyscall) {
+ cpu->squashFromXC(thread->tid);
+ }
+}
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::setFloatRegSingle(int reg_idx, float val)
+{
+ DPRINTF(Fault, "Setting float register through the XC!\n");
+ cpu->setArchFloatRegSingle(reg_idx, val, thread->tid);
+
+ if (!thread->trapPending && !thread->inSyscall) {
+ cpu->squashFromXC(thread->tid);
+ }
+}
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::setFloatRegDouble(int reg_idx, double val)
+{
+ DPRINTF(Fault, "Setting float register through the XC!\n");
+ cpu->setArchFloatRegDouble(reg_idx, val, thread->tid);
+
+ if (!thread->trapPending && !thread->inSyscall) {
+ cpu->squashFromXC(thread->tid);
+ }
+}
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::setFloatRegInt(int reg_idx, uint64_t val)
+{
+ DPRINTF(Fault, "Setting floatint register through the XC!\n");
+ cpu->setArchFloatRegInt(reg_idx, val, thread->tid);
+
+ if (!thread->trapPending && !thread->inSyscall) {
+ cpu->squashFromXC(thread->tid);
+ }
+}
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::setPC(uint64_t val)
+{
+ cpu->setPC(val, thread->tid);
+
+ if (!thread->trapPending && !thread->inSyscall) {
+ cpu->squashFromXC(thread->tid);
+ }
+}
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::setNextPC(uint64_t val)
+{
+ cpu->setNextPC(val, thread->tid);
+
+ if (!thread->trapPending && !thread->inSyscall) {
+ cpu->squashFromXC(thread->tid);
+ }
+}
+
+template <class Impl>
+Fault
+AlphaFullCPU<Impl>::AlphaXC::setMiscReg(int misc_reg, const MiscReg &val)
+{
+ DPRINTF(Fault, "Setting misc register through the XC!\n");
+
+ Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->tid);
+
+ if (!thread->trapPending && !thread->inSyscall) {
+ cpu->squashFromXC(thread->tid);
+ }
+
+ return ret_fault;
+}
+
+template <class Impl>
+Fault
+AlphaFullCPU<Impl>::AlphaXC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+{
+ DPRINTF(Fault, "Setting misc register through the XC!\n");
+
+ Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, thread->tid);
+
+ if (!thread->trapPending && !thread->inSyscall) {
+ cpu->squashFromXC(thread->tid);
+ }
+
+ return ret_fault;
+}
+
+#if !FULL_SYSTEM
+
+template <class Impl>
+TheISA::IntReg
+AlphaFullCPU<Impl>::AlphaXC::getSyscallArg(int i)
+{
+ return cpu->getSyscallArg(i, thread->tid);
+}
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::setSyscallArg(int i, IntReg val)
+{
+ cpu->setSyscallArg(i, val, thread->tid);
+}
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::AlphaXC::setSyscallReturn(SyscallReturn return_value)
+{
+ cpu->setSyscallReturn(return_value, thread->tid);
+}
+
+#endif // FULL_SYSTEM
+
+template <class Impl>
+MiscReg
+AlphaFullCPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
+{
+ return this->regFile.readMiscReg(misc_reg, tid);
+}
+
+template <class Impl>
+MiscReg
+AlphaFullCPU<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault,
+ unsigned tid)
+{
+ return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid);
+}
+
+template <class Impl>
+Fault
+AlphaFullCPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
+{
+ return this->regFile.setMiscReg(misc_reg, val, tid);
+}
+
+template <class Impl>
+Fault
+AlphaFullCPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
+ unsigned tid)
+{
+ return this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
+}
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::squashFromXC(unsigned tid)
+{
+ this->thread[tid]->inSyscall = true;
+ this->commit.generateXCEvent(tid);
+}
+
#if FULL_SYSTEM
template <class Impl>
+void
+AlphaFullCPU<Impl>::post_interrupt(int int_num, int index)
+{
+ BaseCPU::post_interrupt(int_num, index);
+
+ if (this->thread[0]->status() == ExecContext::Suspended) {
+ DPRINTF(IPI,"Suspended Processor awoke\n");
+// xcProxies[0]->activate();
+ this->execContexts[0]->activate();
+ }
+}
+
+template <class Impl>
int
AlphaFullCPU<Impl>::readIntrFlag()
{
@@ -259,20 +613,14 @@ AlphaFullCPU<Impl>::setIntrFlag(int val)
this->regFile.setIntrFlag(val);
}
-// Can force commit stage to squash and stuff.
template <class Impl>
Fault
-AlphaFullCPU<Impl>::hwrei()
+AlphaFullCPU<Impl>::hwrei(unsigned tid)
{
- if (!inPalMode())
- return new AlphaISA::UnimplementedOpcodeFault;
-
- this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR));
+ // Need to clear the lock flag upon returning from an interrupt.
+ this->lockFlag = false;
-// kernelStats.hwrei();
-
- if ((this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
-// AlphaISA::swap_palshadow(&regs, false);
+ this->thread[tid]->kernelStats->hwrei();
this->checkInterrupts = true;
@@ -282,9 +630,11 @@ AlphaFullCPU<Impl>::hwrei()
template <class Impl>
bool
-AlphaFullCPU<Impl>::simPalCheck(int palFunc)
+AlphaFullCPU<Impl>::simPalCheck(int palFunc, unsigned tid)
{
-// kernelStats.callpal(palFunc);
+ if (this->thread[tid]->kernelStats)
+ this->thread[tid]->kernelStats->callpal(palFunc,
+ this->execContexts[tid]);
switch (palFunc) {
case PAL::halt:
@@ -303,69 +653,123 @@ AlphaFullCPU<Impl>::simPalCheck(int palFunc)
return true;
}
-// Probably shouldn't be able to switch to the trap handler as quickly as
-// this. Also needs to get the exception restart address from the commit
-// stage.
template <class Impl>
void
-AlphaFullCPU<Impl>::trap(Fault fault)
+AlphaFullCPU<Impl>::trap(Fault fault, unsigned tid)
{
-/* // Keep in mind that a trap may be initiated by fetch if there's a TLB
- // miss
- uint64_t PC = this->commit.readCommitPC();
+ fault->invoke(this->execContexts[tid]);
+}
- DPRINTF(Fault, "Fault %s\n", fault->name());
- this->recordEvent(csprintf("Fault %s", fault->name()));
+template <class Impl>
+void
+AlphaFullCPU<Impl>::processInterrupts()
+{
+ // Check for interrupts here. For now can copy the code that
+ // exists within isa_fullsys_traits.hh. Also assume that thread 0
+ // is the one that handles the interrupts.
+ // @todo: Possibly consolidate the interrupt checking code.
+ // @todo: Allow other threads to handle interrupts.
+
+ // Check if there are any outstanding interrupts
+ //Handle the interrupts
+ int ipl = 0;
+ int summary = 0;
+
+ this->checkInterrupts = false;
+
+ if (this->readMiscReg(IPR_ASTRR, 0))
+ panic("asynchronous traps not implemented\n");
+
+ if (this->readMiscReg(IPR_SIRR, 0)) {
+ for (int i = INTLEVEL_SOFTWARE_MIN;
+ i < INTLEVEL_SOFTWARE_MAX; i++) {
+ if (this->readMiscReg(IPR_SIRR, 0) & (ULL(1) << i)) {
+ // See table 4-19 of the 21164 hardware reference
+ ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
+ summary |= (ULL(1) << i);
+ }
+ }
+ }
- //kernelStats.fault(fault);
+ uint64_t interrupts = this->intr_status();
+
+ if (interrupts) {
+ for (int i = INTLEVEL_EXTERNAL_MIN;
+ i < INTLEVEL_EXTERNAL_MAX; i++) {
+ if (interrupts & (ULL(1) << i)) {
+ // See table 4-19 of the 21164 hardware reference
+ ipl = i;
+ summary |= (ULL(1) << i);
+ }
+ }
+ }
- if (fault->isA<ArithmeticFault>())
- panic("Arithmetic traps are unimplemented!");
+ if (ipl && ipl > this->readMiscReg(IPR_IPLR, 0)) {
+ this->setMiscReg(IPR_ISR, summary, 0);
+ this->setMiscReg(IPR_INTID, ipl, 0);
+ if (this->checker) {
+ this->checker->cpuXCBase()->setMiscReg(IPR_ISR, summary);
+ this->checker->cpuXCBase()->setMiscReg(IPR_INTID, ipl);
+ }
+ this->trap(Fault(new InterruptFault), 0);
+ DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
+ this->readMiscReg(IPR_IPLR, 0), ipl, summary);
+ }
+}
- // exception restart address - Get the commit PC
- if (!fault->isA<InterruptFault>() || !inPalMode(PC))
- this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC);
+#endif // FULL_SYSTEM
- if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>())
- // || fault == InterruptFault && !PC_PAL(regs.pc)
- {
- // traps... skip faulting instruction
- AlphaISA::MiscReg ipr_exc_addr =
- this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR);
- this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR,
- ipr_exc_addr + 4);
- }
+#if !FULL_SYSTEM
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::syscall(int tid)
+{
+ DPRINTF(FullCPU, "AlphaFullCPU: [tid:%i] Executing syscall().\n\n", tid);
- if (!inPalMode(PC))
- swapPALShadow(true);
+ DPRINTF(Activity,"Activity: syscall() called.\n");
- this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) +
- (dynamic_cast<AlphaFault *>(fault.get()))->vect());
- this->regFile.setNextPC(PC + sizeof(MachInst));*/
+ // Temporarily increase this by one to account for the syscall
+ // instruction.
+ ++(this->thread[tid]->funcExeInst);
+
+ // Execute the actual syscall.
+ this->thread[tid]->syscall();
+
+ // Decrease funcExeInst by one as the normal commit will handle
+ // incrementing it.
+ --(this->thread[tid]->funcExeInst);
}
template <class Impl>
-void
-AlphaFullCPU<Impl>::processInterrupts()
+TheISA::IntReg
+AlphaFullCPU<Impl>::getSyscallArg(int i, int tid)
{
- // Check for interrupts here. For now can copy the code that exists
- // within isa_fullsys_traits.hh.
+ return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid);
}
-// swap_palshadow swaps in the values of the shadow registers and
-// swaps them with the values of the physical registers that map to the
-// same logical index.
template <class Impl>
void
-AlphaFullCPU<Impl>::swapPALShadow(bool use_shadow)
+AlphaFullCPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
{
- if (palShadowEnabled == use_shadow)
- panic("swap_palshadow: wrong PAL shadow state");
-
- palShadowEnabled = use_shadow;
-
- // Will have to lookup in rename map to get physical registers, then
- // swap.
+ this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid);
}
-#endif // FULL_SYSTEM
+template <class Impl>
+void
+AlphaFullCPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
+{
+ // check for error condition. Alpha syscall convention is to
+ // indicate success/failure in reg a3 (r19) and put the
+ // return value itself in the standard return value reg (v0).
+ if (return_value.successful()) {
+ // no error
+ this->setArchIntReg(SyscallSuccessReg, 0, tid);
+ this->setArchIntReg(ReturnValueReg, return_value.value(), tid);
+ } else {
+ // got an error, return details
+ this->setArchIntReg(SyscallSuccessReg, (IntReg) -1, tid);
+ this->setArchIntReg(ReturnValueReg, -return_value.value(), tid);
+ }
+}
+#endif
diff --git a/src/cpu/o3/alpha_dyn_inst.hh b/src/cpu/o3/alpha_dyn_inst.hh
index 5b8a05e5c..b03c8c337 100644
--- a/src/cpu/o3/alpha_dyn_inst.hh
+++ b/src/cpu/o3/alpha_dyn_inst.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,21 +26,21 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_ALPHA_DYN_INST_HH__
-#define __CPU_O3_CPU_ALPHA_DYN_INST_HH__
+#ifndef __CPU_O3_ALPHA_DYN_INST_HH__
+#define __CPU_O3_ALPHA_DYN_INST_HH__
#include "cpu/base_dyn_inst.hh"
+#include "cpu/inst_seq.hh"
#include "cpu/o3/alpha_cpu.hh"
#include "cpu/o3/alpha_impl.hh"
-#include "cpu/inst_seq.hh"
/**
- * Mostly implementation specific AlphaDynInst. It is templated in case there
- * are other implementations that are similar enough to be able to use this
- * class without changes. This is mainly useful if there are multiple similar
- * CPU implementations of the same ISA.
+ * Mostly implementation & ISA specific AlphaDynInst. As with most
+ * other classes in the new CPU model, it is templated on the Impl to
+ * allow for passing in of all types, such as the CPU type and the ISA
+ * type. The AlphaDynInst serves as the primary interface to the CPU
+ * for instructions that are executing.
*/
-
template <class Impl>
class AlphaDynInst : public BaseDynInst<Impl>
{
@@ -50,6 +50,8 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** Binary machine instruction type. */
typedef TheISA::MachInst MachInst;
+ /** Extended machine instruction type. */
+ typedef TheISA::ExtMachInst ExtMachInst;
/** Logical register index type. */
typedef TheISA::RegIndex RegIndex;
/** Integer register index type. */
@@ -64,60 +66,66 @@ class AlphaDynInst : public BaseDynInst<Impl>
public:
/** BaseDynInst constructor given a binary instruction. */
- AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
+ AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
FullCPU *cpu);
/** BaseDynInst constructor given a static inst pointer. */
AlphaDynInst(StaticInstPtr &_staticInst);
/** Executes the instruction.*/
- Fault execute()
- {
- return this->fault = this->staticInst->execute(this, this->traceData);
- }
+ Fault execute();
+
+ /** Initiates the access. Only valid for memory operations. */
+ Fault initiateAcc();
+
+ /** Completes the access. Only valid for memory operations. */
+ Fault completeAcc();
+
+ private:
+ /** Initializes variables. */
+ void initVars();
public:
MiscReg readMiscReg(int misc_reg)
{
- // Dummy function for now.
- // @todo: Fix this once reg file gets fixed.
- return 0;
+ return this->cpu->readMiscReg(misc_reg, this->threadNumber);
}
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
{
- // Dummy function for now.
- // @todo: Fix this once reg file gets fixed.
- return 0;
+ return this->cpu->readMiscRegWithEffect(misc_reg, fault,
+ this->threadNumber);
}
Fault setMiscReg(int misc_reg, const MiscReg &val)
{
- // Dummy function for now.
- // @todo: Fix this once reg file gets fixed.
- return NoFault;
+ this->instResult.integer = val;
+ return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
}
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
- // Dummy function for now.
- // @todo: Fix this once reg file gets fixed.
- return NoFault;
+ return this->cpu->setMiscRegWithEffect(misc_reg, val,
+ this->threadNumber);
}
#if FULL_SYSTEM
+ /** Calls hardware return from error interrupt. */
Fault hwrei();
+ /** Reads interrupt flag. */
int readIntrFlag();
+ /** Sets interrupt flag. */
void setIntrFlag(int val);
+ /** Checks if system is in PAL mode. */
bool inPalMode();
+ /** Traps to handle specified fault. */
void trap(Fault fault);
bool simPalCheck(int palFunc);
#else
+ /** Calls a syscall. */
void syscall();
#endif
-
-
private:
/** Physical register index of the destination registers of this
* instruction.
@@ -178,19 +186,19 @@ class AlphaDynInst : public BaseDynInst<Impl>
void setIntReg(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setIntReg(_destRegIdx[idx], val);
- this->instResult.integer = val;
+ BaseDynInst<Impl>::setIntReg(si, idx, val);
}
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
{
this->cpu->setFloatReg(_destRegIdx[idx], val, width);
- this->instResult.fp = val;
+ BaseDynInst<Impl>::setFloatRegSingle(si, idx, val);
}
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
{
this->cpu->setFloatReg(_destRegIdx[idx], val);
- this->instResult.dbl = val;
+ BaseDynInst<Impl>::setFloatRegDouble(si, idx, val);
}
void setFloatRegBits(const StaticInst *si, int idx,
@@ -203,7 +211,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
{
this->cpu->setFloatRegBits(_destRegIdx[idx], val);
- this->instResult.integer = val;
+ BaseDynInst<Impl>::setFloatRegInt(si, idx, val);
}
/** Returns the physical register index of the i'th destination
@@ -249,16 +257,24 @@ class AlphaDynInst : public BaseDynInst<Impl>
}
public:
+ /** Calculates EA part of a memory instruction. Currently unused,
+ * though it may be useful in the future if we want to split
+ * memory operations into EA calculation and memory access parts.
+ */
Fault calcEA()
{
return this->staticInst->eaCompInst()->execute(this, this->traceData);
}
+ /** Does the memory access part of a memory instruction. Currently unused,
+ * though it may be useful in the future if we want to split
+ * memory operations into EA calculation and memory access parts.
+ */
Fault memAccess()
{
return this->staticInst->memAccInst()->execute(this, this->traceData);
}
};
-#endif // __CPU_O3_CPU_ALPHA_DYN_INST_HH__
+#endif // __CPU_O3_ALPHA_DYN_INST_HH__
diff --git a/src/cpu/o3/alpha_dyn_inst_impl.hh b/src/cpu/o3/alpha_dyn_inst_impl.hh
index 96b7d3430..541d5ab82 100644
--- a/src/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/src/cpu/o3/alpha_dyn_inst_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,42 +29,88 @@
#include "cpu/o3/alpha_dyn_inst.hh"
template <class Impl>
-AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
+AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
InstSeqNum seq_num, FullCPU *cpu)
: BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
{
+ initVars();
+}
+
+template <class Impl>
+AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
+ : BaseDynInst<Impl>(_staticInst)
+{
+ initVars();
+}
+
+template <class Impl>
+void
+AlphaDynInst<Impl>::initVars()
+{
// Make sure to have the renamed register entries set to the same
// as the normal register entries. It will allow the IQ to work
// without any modifications.
- for (int i = 0; i < this->staticInst->numDestRegs(); i++)
- {
+ for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
_destRegIdx[i] = this->staticInst->destRegIdx(i);
}
- for (int i = 0; i < this->staticInst->numSrcRegs(); i++)
- {
+ for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
this->_readySrcRegIdx[i] = 0;
}
+}
+
+template <class Impl>
+Fault
+AlphaDynInst<Impl>::execute()
+{
+ // @todo: Pretty convoluted way to avoid squashing from happening when using
+ // the XC during an instruction's execution (specifically for instructions
+ // that have sideeffects that use the XC). Fix this.
+ bool in_syscall = this->thread->inSyscall;
+ this->thread->inSyscall = true;
+
+ this->fault = this->staticInst->execute(this, this->traceData);
+
+ this->thread->inSyscall = in_syscall;
+ return this->fault;
}
template <class Impl>
-AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
- : BaseDynInst<Impl>(_staticInst)
+Fault
+AlphaDynInst<Impl>::initiateAcc()
{
- // Make sure to have the renamed register entries set to the same
- // as the normal register entries. It will allow the IQ to work
- // without any modifications.
- for (int i = 0; i < _staticInst->numDestRegs(); i++)
- {
- _destRegIdx[i] = _staticInst->destRegIdx(i);
- }
+ // @todo: Pretty convoluted way to avoid squashing from happening when using
+ // the XC during an instruction's execution (specifically for instructions
+ // that have sideeffects that use the XC). Fix this.
+ bool in_syscall = this->thread->inSyscall;
+ this->thread->inSyscall = true;
+
+ this->fault = this->staticInst->initiateAcc(this, this->traceData);
+
+ this->thread->inSyscall = in_syscall;
- for (int i = 0; i < _staticInst->numSrcRegs(); i++)
- {
- _srcRegIdx[i] = _staticInst->srcRegIdx(i);
+ return this->fault;
+}
+
+template <class Impl>
+Fault
+AlphaDynInst<Impl>::completeAcc()
+{
+ if (this->isLoad()) {
+ this->fault = this->staticInst->completeAcc(this->req->data,
+ this,
+ this->traceData);
+ } else if (this->isStore()) {
+ this->fault = this->staticInst->completeAcc((uint8_t*)&this->req->result,
+ this,
+ this->traceData);
+ } else {
+ panic("Unknown type!");
}
+
+ return this->fault;
}
#if FULL_SYSTEM
@@ -72,14 +118,24 @@ template <class Impl>
Fault
AlphaDynInst<Impl>::hwrei()
{
- return this->cpu->hwrei();
+ if (!this->cpu->inPalMode(this->readPC()))
+ return new AlphaISA::UnimplementedOpcodeFault;
+
+ this->setNextPC(this->cpu->readMiscReg(AlphaISA::IPR_EXC_ADDR,
+ this->threadNumber));
+
+ // Tell CPU to clear any state it needs to if a hwrei is taken.
+ this->cpu->hwrei(this->threadNumber);
+
+ // FIXME: XXX check for interrupts? XXX
+ return NoFault;
}
template <class Impl>
int
AlphaDynInst<Impl>::readIntrFlag()
{
-return this->cpu->readIntrFlag();
+ return this->cpu->readIntrFlag();
}
template <class Impl>
@@ -93,21 +149,21 @@ template <class Impl>
bool
AlphaDynInst<Impl>::inPalMode()
{
- return this->cpu->inPalMode();
+ return this->cpu->inPalMode(this->PC);
}
template <class Impl>
void
AlphaDynInst<Impl>::trap(Fault fault)
{
- this->cpu->trap(fault);
+ this->cpu->trap(fault, this->threadNumber);
}
template <class Impl>
bool
AlphaDynInst<Impl>::simPalCheck(int palFunc)
{
- return this->cpu->simPalCheck(palFunc);
+ return this->cpu->simPalCheck(palFunc, this->threadNumber);
}
#else
template <class Impl>
diff --git a/src/cpu/o3/alpha_impl.hh b/src/cpu/o3/alpha_impl.hh
index 5e39fcb37..f404bd3ec 100644
--- a/src/cpu/o3/alpha_impl.hh
+++ b/src/cpu/o3/alpha_impl.hh
@@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_ALPHA_IMPL_HH__
-#define __CPU_O3_CPU_ALPHA_IMPL_HH__
+#ifndef __CPU_O3_ALPHA_IMPL_HH__
+#define __CPU_O3_ALPHA_IMPL_HH__
#include "arch/alpha/isa_traits.hh"
@@ -41,7 +41,7 @@ class AlphaDynInst;
template <class Impl>
class AlphaFullCPU;
-/** Implementation specific struct that defines several key things to the
+/** Implementation specific struct that defines several key types to the
* CPU, the stages within the CPU, the time buffers, and the DynInst.
* The struct defines the ISA, the CPU policy, the specific DynInst, the
* specific FullCPU, and all of the structs from the time buffers to do
@@ -54,10 +54,10 @@ struct AlphaSimpleImpl
/** The type of MachInst. */
typedef TheISA::MachInst MachInst;
- /** The CPU policy to be used (ie fetch, decode, etc.). */
+ /** The CPU policy to be used, which defines all of the CPU stages. */
typedef SimpleCPUPolicy<AlphaSimpleImpl> CPUPol;
- /** The DynInst to be used. */
+ /** The DynInst type to be used. */
typedef AlphaDynInst<AlphaSimpleImpl> DynInst;
/** The refcounted DynInst pointer to be used. In most cases this is
@@ -65,15 +65,16 @@ struct AlphaSimpleImpl
*/
typedef RefCountingPtr<DynInst> DynInstPtr;
- /** The FullCPU to be used. */
+ /** The FullCPU type to be used. */
typedef AlphaFullCPU<AlphaSimpleImpl> FullCPU;
/** The Params to be passed to each stage. */
typedef AlphaSimpleParams Params;
enum {
- MaxWidth = 8
+ MaxWidth = 8,
+ MaxThreads = 4
};
};
-#endif // __CPU_O3_CPU_ALPHA_IMPL_HH__
+#endif // __CPU_O3_ALPHA_IMPL_HH__
diff --git a/src/cpu/o3/alpha_params.hh b/src/cpu/o3/alpha_params.hh
index 79b0937e3..e3acf2c05 100644
--- a/src/cpu/o3/alpha_params.hh
+++ b/src/cpu/o3/alpha_params.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,18 +26,19 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_ALPHA_SIMPLE_PARAMS_HH__
-#define __CPU_O3_CPU_ALPHA_SIMPLE_PARAMS_HH__
+#ifndef __CPU_O3_ALPHA_PARAMS_HH__
+#define __CPU_O3_ALPHA_PARAMS_HH__
#include "cpu/o3/cpu.hh"
//Forward declarations
-class System;
-class AlphaITB;
class AlphaDTB;
+class AlphaITB;
+class FUPool;
class FunctionalMemory;
-class Process;
class MemInterface;
+class Process;
+class System;
/**
* This file defines the parameters that will be used for the AlphaFullCPU.
@@ -56,14 +57,23 @@ class AlphaSimpleParams : public BaseFullCPU::Params
Process *process;
#endif // FULL_SYSTEM
+ //Page Table
+// PageTable *pTable;
+
FunctionalMemory *mem;
+ BaseCPU *checker;
+
+ unsigned activity;
+
//
// Caches
//
MemInterface *icacheInterface;
MemInterface *dcacheInterface;
+ unsigned cachePorts;
+
//
// Fetch
//
@@ -102,6 +112,7 @@ class AlphaSimpleParams : public BaseFullCPU::Params
unsigned executeFloatWidth;
unsigned executeBranchWidth;
unsigned executeMemoryWidth;
+ FUPool *fuPool;
//
// Commit
@@ -110,24 +121,21 @@ class AlphaSimpleParams : public BaseFullCPU::Params
unsigned renameToROBDelay;
unsigned commitWidth;
unsigned squashWidth;
+ Tick trapLatency;
+ Tick fetchTrapLatency;
//
// Branch predictor (BP & BTB)
//
-/*
unsigned localPredictorSize;
- unsigned localPredictorCtrBits;
-*/
-
- unsigned local_predictor_size;
- unsigned local_ctr_bits;
- unsigned local_history_table_size;
- unsigned local_history_bits;
- unsigned global_predictor_size;
- unsigned global_ctr_bits;
- unsigned global_history_bits;
- unsigned choice_predictor_size;
- unsigned choice_ctr_bits;
+ unsigned localCtrBits;
+ unsigned localHistoryTableSize;
+ unsigned localHistoryBits;
+ unsigned globalPredictorSize;
+ unsigned globalCtrBits;
+ unsigned globalHistoryBits;
+ unsigned choicePredictorSize;
+ unsigned choiceCtrBits;
unsigned BTBEntries;
unsigned BTBTagSize;
@@ -154,10 +162,24 @@ class AlphaSimpleParams : public BaseFullCPU::Params
unsigned numIQEntries;
unsigned numROBEntries;
+ //SMT Parameters
+ unsigned smtNumFetchingThreads;
+
+ std::string smtFetchPolicy;
+
+ std::string smtIQPolicy;
+ unsigned smtIQThreshold;
+
+ std::string smtLSQPolicy;
+ unsigned smtLSQThreshold;
+
+ std::string smtCommitPolicy;
+
+ std::string smtROBPolicy;
+ unsigned smtROBThreshold;
+
// Probably can get this from somewhere.
unsigned instShiftAmt;
-
- bool defReg;
};
-#endif // __CPU_O3_CPU_ALPHA_PARAMS_HH__
+#endif // __CPU_O3_ALPHA_PARAMS_HH__
diff --git a/src/cpu/o3/bpred_unit.cc b/src/cpu/o3/bpred_unit.cc
index 85bd6f0a6..92344111f 100644
--- a/src/cpu/o3/bpred_unit.cc
+++ b/src/cpu/o3/bpred_unit.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,5 +29,9 @@
#include "cpu/o3/bpred_unit_impl.hh"
#include "cpu/o3/alpha_impl.hh"
#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/ozone/ozone_impl.hh"
+#include "cpu/ozone/simple_impl.hh"
template class TwobitBPredUnit<AlphaSimpleImpl>;
+template class TwobitBPredUnit<OzoneImpl>;
+template class TwobitBPredUnit<SimpleImpl>;
diff --git a/src/cpu/o3/bpred_unit.hh b/src/cpu/o3/bpred_unit.hh
index 2725684f7..b7814b2e9 100644
--- a/src/cpu/o3/bpred_unit.hh
+++ b/src/cpu/o3/bpred_unit.hh
@@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __BPRED_UNIT_HH__
-#define __BPRED_UNIT_HH__
+#ifndef __CPU_O3_BPRED_UNIT_HH__
+#define __CPU_O3_BPRED_UNIT_HH__
// For Addr type.
#include "arch/isa_traits.hh"
@@ -35,20 +35,15 @@
#include "cpu/inst_seq.hh"
#include "cpu/o3/2bit_local_pred.hh"
-#include "cpu/o3/tournament_pred.hh"
#include "cpu/o3/btb.hh"
#include "cpu/o3/ras.hh"
+#include "cpu/o3/tournament_pred.hh"
#include <list>
/**
* Basically a wrapper class to hold both the branch predictor
- * and the BTB. Right now I'm unsure of the implementation; it would
- * be nicer to have something closer to the CPUPolicy or the Impl where
- * this is just typedefs, but it forces the upper level stages to be
- * aware of the constructors of the BP and the BTB. The nicer thing
- * to do is have this templated on the Impl, accept the usual Params
- * object, and be able to call the constructors on the BP and BTB.
+ * and the BTB.
*/
template<class Impl>
class TwobitBPredUnit
@@ -57,77 +52,175 @@ class TwobitBPredUnit
typedef typename Impl::Params Params;
typedef typename Impl::DynInstPtr DynInstPtr;
- TwobitBPredUnit(Params &params);
+ /**
+ * @param params The params object, that has the size of the BP and BTB.
+ */
+ TwobitBPredUnit(Params *params);
+ /**
+ * Registers statistics.
+ */
void regStats();
- bool predict(DynInstPtr &inst, Addr &PC);
-
- void update(const InstSeqNum &done_sn);
-
- void squash(const InstSeqNum &squashed_sn);
-
+ void switchOut();
+
+ void takeOverFrom();
+
+ /**
+ * Predicts whether or not the instruction is a taken branch, and the
+ * target of the branch if it is taken.
+ * @param inst The branch instruction.
+ * @param PC The predicted PC is passed back through this parameter.
+ * @param tid The thread id.
+ * @return Returns if the branch is taken or not.
+ */
+ bool predict(DynInstPtr &inst, Addr &PC, unsigned tid);
+
+ /**
+ * Tells the branch predictor to commit any updates until the given
+ * sequence number.
+ * @param done_sn The sequence number to commit any older updates up until.
+ * @param tid The thread id.
+ */
+ void update(const InstSeqNum &done_sn, unsigned tid);
+
+ /**
+ * Squashes all outstanding updates until a given sequence number.
+ * @param squashed_sn The sequence number to squash any younger updates up
+ * until.
+ * @param tid The thread id.
+ */
+ void squash(const InstSeqNum &squashed_sn, unsigned tid);
+
+ /**
+ * Squashes all outstanding updates until a given sequence number, and
+ * corrects that sn's update with the proper address and taken/not taken.
+ * @param squashed_sn The sequence number to squash any younger updates up
+ * until.
+ * @param corr_target The correct branch target.
+ * @param actually_taken The correct branch direction.
+ * @param tid The thread id.
+ */
void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
- bool actually_taken);
+ bool actually_taken, unsigned tid);
+ /**
+ * Looks up a given PC in the BP to see if it is taken or not taken.
+ * @param inst_PC The PC to look up.
+ * @return Whether the branch is taken or not taken.
+ */
bool BPLookup(Addr &inst_PC)
{ return BP.lookup(inst_PC); }
+ /**
+ * Looks up a given PC in the BTB to see if a matching entry exists.
+ * @param inst_PC The PC to look up.
+ * @return Whether the BTB contains the given PC.
+ */
bool BTBValid(Addr &inst_PC)
- { return BTB.valid(inst_PC); }
+ { return BTB.valid(inst_PC, 0); }
+ /**
+ * Looks up a given PC in the BTB to get the predicted target.
+ * @param inst_PC The PC to look up.
+ * @return The address of the target of the branch.
+ */
Addr BTBLookup(Addr &inst_PC)
- { return BTB.lookup(inst_PC); }
-
- // Will want to include global history.
+ { return BTB.lookup(inst_PC, 0); }
+
+ /**
+ * Updates the BP with taken/not taken information.
+ * @param inst_PC The branch's PC that will be updated.
+ * @param taken Whether the branch was taken or not taken.
+ * @todo Make this update flexible enough to handle a global predictor.
+ */
void BPUpdate(Addr &inst_PC, bool taken)
{ BP.update(inst_PC, taken); }
+ /**
+ * Updates the BTB with the target of a branch.
+ * @param inst_PC The branch's PC that will be updated.
+ * @param target_PC The branch's target that will be added to the BTB.
+ */
void BTBUpdate(Addr &inst_PC, Addr &target_PC)
- { BTB.update(inst_PC, target_PC); }
+ { BTB.update(inst_PC, target_PC,0); }
private:
struct PredictorHistory {
+ /**
+ * Makes a predictor history struct that contains a sequence number,
+ * the PC of its instruction, and whether or not it was predicted
+ * taken.
+ */
PredictorHistory(const InstSeqNum &seq_num, const Addr &inst_PC,
- const bool pred_taken)
- : seqNum(seq_num), PC(inst_PC), predTaken(pred_taken),
- globalHistory(0), usedRAS(0), wasCall(0), RASIndex(0),
- RASTarget(0)
+ const bool pred_taken, const unsigned _tid)
+ : seqNum(seq_num), PC(inst_PC), RASTarget(0), globalHistory(0),
+ RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0),
+ wasCall(0)
{ }
+ /** The sequence number for the predictor history entry. */
InstSeqNum seqNum;
+ /** The PC associated with the sequence number. */
Addr PC;
- bool predTaken;
+ /** The RAS target (only valid if a return). */
+ Addr RASTarget;
+ /** The global history at the time this entry was created. */
unsigned globalHistory;
- bool usedRAS;
+ /** The RAS index of the instruction (only valid if a call). */
+ unsigned RASIndex;
- bool wasCall;
+ /** The thread id. */
+ unsigned tid;
- unsigned RASIndex;
+ /** Whether or not it was predicted taken. */
+ bool predTaken;
- Addr RASTarget;
+ /** Whether or not the RAS was used. */
+ bool usedRAS;
+
+ /** Whether or not the instruction was a call. */
+ bool wasCall;
};
- std::list<PredictorHistory> predHist;
+ typedef std::list<PredictorHistory> History;
+
+ /**
+ * The per-thread predictor history. This is used to update the predictor
+ * as instructions are committed, or restore it to the proper state after
+ * a squash.
+ */
+ History predHist[Impl::MaxThreads];
+ /** The branch predictor. */
DefaultBP BP;
+ /** The BTB. */
DefaultBTB BTB;
- ReturnAddrStack RAS;
+ /** The per-thread return address stack. */
+ ReturnAddrStack RAS[Impl::MaxThreads];
+ /** Stat for number of BP lookups. */
Stats::Scalar<> lookups;
+ /** Stat for number of conditional branches predicted. */
Stats::Scalar<> condPredicted;
+ /** Stat for number of conditional branches predicted incorrectly. */
Stats::Scalar<> condIncorrect;
+ /** Stat for number of BTB lookups. */
Stats::Scalar<> BTBLookups;
+ /** Stat for number of BTB hits. */
Stats::Scalar<> BTBHits;
+ /** Stat for number of times the BTB is correct. */
Stats::Scalar<> BTBCorrect;
+ /** Stat for number of times the RAS is used to get a target. */
Stats::Scalar<> usedRAS;
+ /** Stat for number of times the RAS is incorrect. */
Stats::Scalar<> RASIncorrect;
};
-#endif // __BPRED_UNIT_HH__
+#endif // __CPU_O3_BPRED_UNIT_HH__
diff --git a/src/cpu/o3/bpred_unit_impl.hh b/src/cpu/o3/bpred_unit_impl.hh
index 8d16a0cdf..c37df606b 100644
--- a/src/cpu/o3/bpred_unit_impl.hh
+++ b/src/cpu/o3/bpred_unit_impl.hh
@@ -26,20 +26,26 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include <list>
+#include <vector>
+
#include "base/trace.hh"
#include "base/traceflags.hh"
#include "cpu/o3/bpred_unit.hh"
+using namespace std;
+
template<class Impl>
-TwobitBPredUnit<Impl>::TwobitBPredUnit(Params &params)
- : BP(params.local_predictor_size,
- params.local_ctr_bits,
- params.instShiftAmt),
- BTB(params.BTBEntries,
- params.BTBTagSize,
- params.instShiftAmt),
- RAS(params.RASSize)
+TwobitBPredUnit<Impl>::TwobitBPredUnit(Params *params)
+ : BP(params->localPredictorSize,
+ params->localCtrBits,
+ params->instShiftAmt),
+ BTB(params->BTBEntries,
+ params->BTBTagSize,
+ params->instShiftAmt)
{
+ for (int i=0; i < Impl::MaxThreads; i++)
+ RAS[i].init(params->RASSize);
}
template <class Impl>
@@ -79,7 +85,7 @@ TwobitBPredUnit<Impl>::regStats()
usedRAS
.name(name() + ".BPredUnit.usedRAS")
- .desc("Number of times the RAS was used.")
+ .desc("Number of times the RAS was used to get a target.")
;
RASIncorrect
@@ -89,8 +95,30 @@ TwobitBPredUnit<Impl>::regStats()
}
template <class Impl>
+void
+TwobitBPredUnit<Impl>::switchOut()
+{
+ for (int i = 0; i < Impl::MaxThreads; ++i) {
+ predHist[i].clear();
+ }
+}
+
+template <class Impl>
+void
+TwobitBPredUnit<Impl>::takeOverFrom()
+{
+/*
+ for (int i = 0; i < Impl::MaxThreads; ++i)
+ RAS[i].reset();
+
+ BP.reset();
+ BTB.reset();
+*/
+}
+
+template <class Impl>
bool
-TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC)
+TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
{
// See if branch predictor predicts taken.
// If so, get its target addr either from the BTB or the RAS.
@@ -106,18 +134,19 @@ TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC)
++lookups;
if (inst->isUncondCtrl()) {
- DPRINTF(Fetch, "BranchPred: Unconditional control.\n");
+ DPRINTF(Fetch, "BranchPred: [tid:%i] Unconditional control.\n", tid);
pred_taken = true;
} else {
++condPredicted;
pred_taken = BPLookup(PC);
- DPRINTF(Fetch, "BranchPred: Branch predictor predicted %i for PC %#x"
- "\n", pred_taken, inst->readPC());
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: Branch predictor predicted %i "
+ "for PC %#x\n",
+ tid, pred_taken, inst->readPC());
}
- PredictorHistory predict_record(inst->seqNum, PC, pred_taken);
+ PredictorHistory predict_record(inst->seqNum, PC, pred_taken, tid);
// Now lookup in the BTB or RAS.
if (pred_taken) {
@@ -126,45 +155,48 @@ TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC)
// If it's a function return call, then look up the address
// in the RAS.
- target = RAS.top();
+ target = RAS[tid].top();
// Record the top entry of the RAS, and its index.
predict_record.usedRAS = true;
- predict_record.RASIndex = RAS.topIdx();
+ predict_record.RASIndex = RAS[tid].topIdx();
predict_record.RASTarget = target;
- RAS.pop();
+ assert(predict_record.RASIndex < 16);
- DPRINTF(Fetch, "BranchPred: Instruction %#x is a return, RAS "
- "predicted target: %#x, RAS index: %i.\n",
- inst->readPC(), target, predict_record.RASIndex);
+ RAS[tid].pop();
+
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x is a return, "
+ "RAS predicted target: %#x, RAS index: %i.\n",
+ tid, inst->readPC(), target, predict_record.RASIndex);
} else {
++BTBLookups;
if (inst->isCall()) {
- RAS.push(PC+sizeof(MachInst));
+ RAS[tid].push(PC + sizeof(MachInst));
// Record that it was a call so that the top RAS entry can
// be popped off if the speculation is incorrect.
predict_record.wasCall = true;
- DPRINTF(Fetch, "BranchPred: Instruction %#x was a call, "
- "adding %#x to the RAS.\n",
- inst->readPC(), PC+sizeof(MachInst));
+ DPRINTF(Fetch, "BranchPred: [tid:%i] Instruction %#x was a call"
+ ", adding %#x to the RAS.\n",
+ tid, inst->readPC(), PC + sizeof(MachInst));
}
- if (BTB.valid(PC)) {
+ if (BTB.valid(PC, tid)) {
++BTBHits;
//If it's anything else, use the BTB to get the target addr.
- target = BTB.lookup(PC);
+ target = BTB.lookup(PC, tid);
- DPRINTF(Fetch, "BranchPred: Instruction %#x predicted target "
- "is %#x.\n", inst->readPC(), target);
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: Instruction %#x predicted"
+ " target is %#x.\n",
+ tid, inst->readPC(), target);
} else {
- DPRINTF(Fetch, "BranchPred: BTB doesn't have a valid entry."
- "\n");
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: BTB doesn't have a "
+ "valid entry.\n",tid);
pred_taken = false;
}
@@ -180,97 +212,113 @@ TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC)
inst->setPredTarg(PC);
}
- predHist.push_front(predict_record);
+ predHist[tid].push_front(predict_record);
- assert(!predHist.empty());
+ DPRINTF(Fetch, "[tid:%i] predHist.size(): %i\n", tid, predHist[tid].size());
return pred_taken;
}
template <class Impl>
void
-TwobitBPredUnit<Impl>::update(const InstSeqNum &done_sn)
+TwobitBPredUnit<Impl>::update(const InstSeqNum &done_sn, unsigned tid)
{
- DPRINTF(Fetch, "BranchPred: Commiting branches until sequence number "
- "%i.\n", done_sn);
-
- while (!predHist.empty() && predHist.back().seqNum <= done_sn) {
- assert(!predHist.empty());
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: Commiting branches until sequence"
+ "number %lli.\n", tid, done_sn);
- // Update the branch predictor with the correct results of branches.
- BP.update(predHist.back().PC, predHist.back().predTaken);
+ while (!predHist[tid].empty() &&
+ predHist[tid].back().seqNum <= done_sn) {
+ // Update the branch predictor with the correct results.
+ BP.update(predHist[tid].back().PC,
+ predHist[tid].back().predTaken);
- predHist.pop_back();
+ predHist[tid].pop_back();
}
}
template <class Impl>
void
-TwobitBPredUnit<Impl>::squash(const InstSeqNum &squashed_sn)
+TwobitBPredUnit<Impl>::squash(const InstSeqNum &squashed_sn, unsigned tid)
{
- while (!predHist.empty() && predHist.front().seqNum > squashed_sn) {
- if (predHist.front().usedRAS) {
- DPRINTF(Fetch, "BranchPred: Restoring top of RAS to: %i, "
- "target: %#x.\n",
- predHist.front().RASIndex,
- predHist.front().RASTarget);
+ History &pred_hist = predHist[tid];
+
+ while (!pred_hist.empty() &&
+ pred_hist.front().seqNum > squashed_sn) {
+ if (pred_hist.front().usedRAS) {
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: Restoring top of RAS to: %i,"
+ " target: %#x.\n",
+ tid,
+ pred_hist.front().RASIndex,
+ pred_hist.front().RASTarget);
+
+ RAS[tid].restore(pred_hist.front().RASIndex,
+ pred_hist.front().RASTarget);
- RAS.restore(predHist.front().RASIndex,
- predHist.front().RASTarget);
- } else if (predHist.front().wasCall) {
- DPRINTF(Fetch, "BranchPred: Removing speculative entry added "
- "to the RAS.\n");
+ } else if (pred_hist.front().wasCall) {
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing speculative entry added "
+ "to the RAS.\n",tid);
- RAS.pop();
+ RAS[tid].pop();
}
- predHist.pop_front();
+ pred_hist.pop_front();
}
+
}
template <class Impl>
void
TwobitBPredUnit<Impl>::squash(const InstSeqNum &squashed_sn,
const Addr &corr_target,
- const bool actually_taken)
+ const bool actually_taken,
+ unsigned tid)
{
// Now that we know that a branch was mispredicted, we need to undo
// all the branches that have been seen up until this branch and
// fix up everything.
+ History &pred_hist = predHist[tid];
+
++condIncorrect;
- DPRINTF(Fetch, "BranchPred: Squashing from sequence number %i, "
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: Squashing from sequence number %i, "
"setting target to %#x.\n",
- squashed_sn, corr_target);
-
- while (!predHist.empty() && predHist.front().seqNum > squashed_sn) {
+ tid, squashed_sn, corr_target);
- if (predHist.front().usedRAS) {
- DPRINTF(Fetch, "BranchPred: Restoring top of RAS to: %i, "
+ while (!pred_hist.empty() &&
+ pred_hist.front().seqNum > squashed_sn) {
+ if (pred_hist.front().usedRAS) {
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: Restoring top of RAS to: %i, "
"target: %#x.\n",
- predHist.front().RASIndex,
- predHist.front().RASTarget);
+ tid,
+ pred_hist.front().RASIndex,
+ pred_hist.front().RASTarget);
- RAS.restore(predHist.front().RASIndex,
- predHist.front().RASTarget);
- } else if (predHist.front().wasCall) {
- DPRINTF(Fetch, "BranchPred: Removing speculative entry added "
- "to the RAS.\n");
+ RAS[tid].restore(pred_hist.front().RASIndex,
+ pred_hist.front().RASTarget);
+ } else if (pred_hist.front().wasCall) {
+ DPRINTF(Fetch, "BranchPred: [tid:%i]: Removing speculative entry"
+ " added to the RAS.\n", tid);
- RAS.pop();
+ RAS[tid].pop();
}
- predHist.pop_front();
+ pred_hist.pop_front();
}
- predHist.front().predTaken = actually_taken;
+ // If there's a squash due to a syscall, there may not be an entry
+ // corresponding to the squash. In that case, don't bother trying to
+ // fix up the entry.
+ if (!pred_hist.empty()) {
+ pred_hist.front().predTaken = actually_taken;
- if (predHist.front().usedRAS) {
- ++RASIncorrect;
- }
+ if (pred_hist.front().usedRAS) {
+ ++RASIncorrect;
+ }
- BP.update(predHist.front().PC, actually_taken);
+ BP.update(pred_hist.front().PC, actually_taken);
- BTB.update(predHist.front().PC, corr_target);
+ BTB.update(pred_hist.front().PC, corr_target, tid);
+ pred_hist.pop_front();
+ }
}
diff --git a/src/cpu/o3/btb.cc b/src/cpu/o3/btb.cc
index 2d39c3856..e5f69043a 100644
--- a/src/cpu/o3/btb.cc
+++ b/src/cpu/o3/btb.cc
@@ -39,14 +39,15 @@ DefaultBTB::DefaultBTB(unsigned _numEntries,
tagBits(_tagBits),
instShiftAmt(_instShiftAmt)
{
- // @todo Check to make sure num_entries is valid (a power of 2)
-
DPRINTF(Fetch, "BTB: Creating BTB object.\n");
- btb = new BTBEntry[numEntries];
+ if (!isPowerOf2(numEntries)) {
+ fatal("BTB entries is not a power of 2!");
+ }
+
+ btb.resize(numEntries);
- for (int i = 0; i < numEntries; ++i)
- {
+ for (int i = 0; i < numEntries; ++i) {
btb[i].valid = false;
}
@@ -57,6 +58,14 @@ DefaultBTB::DefaultBTB(unsigned _numEntries,
tagShiftAmt = instShiftAmt + floorLog2(numEntries);
}
+void
+DefaultBTB::reset()
+{
+ for (int i = 0; i < numEntries; ++i) {
+ btb[i].valid = false;
+ }
+}
+
inline
unsigned
DefaultBTB::getIndex(const Addr &inst_PC)
@@ -73,7 +82,7 @@ DefaultBTB::getTag(const Addr &inst_PC)
}
bool
-DefaultBTB::valid(const Addr &inst_PC)
+DefaultBTB::valid(const Addr &inst_PC, unsigned tid)
{
unsigned btb_idx = getIndex(inst_PC);
@@ -81,7 +90,9 @@ DefaultBTB::valid(const Addr &inst_PC)
assert(btb_idx < numEntries);
- if (btb[btb_idx].valid && inst_tag == btb[btb_idx].tag) {
+ if (btb[btb_idx].valid
+ && inst_tag == btb[btb_idx].tag
+ && btb[btb_idx].tid == tid) {
return true;
} else {
return false;
@@ -92,7 +103,7 @@ DefaultBTB::valid(const Addr &inst_PC)
// address is valid, and also the address. For now will just use addr = 0 to
// represent invalid entry.
Addr
-DefaultBTB::lookup(const Addr &inst_PC)
+DefaultBTB::lookup(const Addr &inst_PC, unsigned tid)
{
unsigned btb_idx = getIndex(inst_PC);
@@ -100,7 +111,9 @@ DefaultBTB::lookup(const Addr &inst_PC)
assert(btb_idx < numEntries);
- if (btb[btb_idx].valid && inst_tag == btb[btb_idx].tag) {
+ if (btb[btb_idx].valid
+ && inst_tag == btb[btb_idx].tag
+ && btb[btb_idx].tid == tid) {
return btb[btb_idx].target;
} else {
return 0;
@@ -108,12 +121,13 @@ DefaultBTB::lookup(const Addr &inst_PC)
}
void
-DefaultBTB::update(const Addr &inst_PC, const Addr &target)
+DefaultBTB::update(const Addr &inst_PC, const Addr &target, unsigned tid)
{
unsigned btb_idx = getIndex(inst_PC);
assert(btb_idx < numEntries);
+ btb[btb_idx].tid = tid;
btb[btb_idx].valid = true;
btb[btb_idx].target = target;
btb[btb_idx].tag = getTag(inst_PC);
diff --git a/src/cpu/o3/btb.hh b/src/cpu/o3/btb.hh
index 77bdc32ea..b9ff42573 100644
--- a/src/cpu/o3/btb.hh
+++ b/src/cpu/o3/btb.hh
@@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_BTB_HH__
-#define __CPU_O3_CPU_BTB_HH__
+#ifndef __CPU_O3_BTB_HH__
+#define __CPU_O3_BTB_HH__
// For Addr type.
#include "arch/isa_traits.hh"
@@ -42,39 +42,86 @@ class DefaultBTB
{
}
+ /** The entry's tag. */
Addr tag;
+
+ /** The entry's target. */
Addr target;
+
+ /** The entry's thread id. */
+ unsigned tid;
+
+ /** Whether or not the entry is valid. */
bool valid;
};
public:
+ /** Creates a BTB with the given number of entries, number of bits per
+ * tag, and instruction offset amount.
+ * @param numEntries Number of entries for the BTB.
+ * @param tagBits Number of bits for each tag in the BTB.
+ * @param instShiftAmt Offset amount for instructions to ignore alignment.
+ */
DefaultBTB(unsigned numEntries, unsigned tagBits,
unsigned instShiftAmt);
- Addr lookup(const Addr &inst_PC);
-
- bool valid(const Addr &inst_PC);
-
- void update(const Addr &inst_PC, const Addr &target_PC);
+ void reset();
+
+ /** Looks up an address in the BTB. Must call valid() first on the address.
+ * @param inst_PC The address of the branch to look up.
+ * @param tid The thread id.
+ * @return Returns the target of the branch.
+ */
+ Addr lookup(const Addr &inst_PC, unsigned tid);
+
+ /** Checks if a branch is in the BTB.
+ * @param inst_PC The address of the branch to look up.
+ * @param tid The thread id.
+ * @return Whether or not the branch exists in the BTB.
+ */
+ bool valid(const Addr &inst_PC, unsigned tid);
+
+ /** Updates the BTB with the target of a branch.
+ * @param inst_PC The address of the branch being updated.
+ * @param target_PC The target address of the branch.
+ * @param tid The thread id.
+ */
+ void update(const Addr &inst_PC, const Addr &target_PC,
+ unsigned tid);
private:
+ /** Returns the index into the BTB, based on the branch's PC.
+ * @param inst_PC The branch to look up.
+ * @return Returns the index into the BTB.
+ */
inline unsigned getIndex(const Addr &inst_PC);
+ /** Returns the tag bits of a given address.
+ * @param inst_PC The branch's address.
+ * @return Returns the tag bits.
+ */
inline Addr getTag(const Addr &inst_PC);
- BTBEntry *btb;
+ /** The actual BTB. */
+ std::vector<BTBEntry> btb;
+ /** The number of entries in the BTB. */
unsigned numEntries;
+ /** The index mask. */
unsigned idxMask;
+ /** The number of tag bits per entry. */
unsigned tagBits;
+ /** The tag mask. */
unsigned tagMask;
+ /** Number of bits to shift PC when calculating index. */
unsigned instShiftAmt;
+ /** Number of bits to shift PC when calculating tag. */
unsigned tagShiftAmt;
};
-#endif // __CPU_O3_CPU_BTB_HH__
+#endif // __CPU_O3_BTB_HH__
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index c74c77ddf..c36c58d3d 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,30 +26,35 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_COMM_HH__
-#define __CPU_O3_CPU_COMM_HH__
+#ifndef __CPU_O3_COMM_HH__
+#define __CPU_O3_COMM_HH__
#include <vector>
+#include "arch/faults.hh"
#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
#include "sim/host.hh"
-// Find better place to put this typedef.
-// The impl might be the best place for this.
+// Typedef for physical register index type. Although the Impl would be the
+// most likely location for this, there are a few classes that need this
+// typedef yet are not templated on the Impl. For now it will be defined here.
typedef short int PhysRegIndex;
template<class Impl>
-struct SimpleFetchSimpleDecode {
+struct DefaultFetchDefaultDecode {
typedef typename Impl::DynInstPtr DynInstPtr;
int size;
DynInstPtr insts[Impl::MaxWidth];
+ Fault fetchFault;
+ InstSeqNum fetchFaultSN;
+ bool clearFetchFault;
};
template<class Impl>
-struct SimpleDecodeSimpleRename {
+struct DefaultDecodeDefaultRename {
typedef typename Impl::DynInstPtr DynInstPtr;
int size;
@@ -58,7 +63,7 @@ struct SimpleDecodeSimpleRename {
};
template<class Impl>
-struct SimpleRenameSimpleIEW {
+struct DefaultRenameDefaultIEW {
typedef typename Impl::DynInstPtr DynInstPtr;
int size;
@@ -67,19 +72,21 @@ struct SimpleRenameSimpleIEW {
};
template<class Impl>
-struct SimpleIEWSimpleCommit {
+struct DefaultIEWDefaultCommit {
typedef typename Impl::DynInstPtr DynInstPtr;
int size;
DynInstPtr insts[Impl::MaxWidth];
- bool squash;
- bool branchMispredict;
- bool branchTaken;
- uint64_t mispredPC;
- uint64_t nextPC;
- InstSeqNum squashedSeqNum;
+ bool squash[Impl::MaxThreads];
+ bool branchMispredict[Impl::MaxThreads];
+ bool branchTaken[Impl::MaxThreads];
+ uint64_t mispredPC[Impl::MaxThreads];
+ uint64_t nextPC[Impl::MaxThreads];
+ InstSeqNum squashedSeqNum[Impl::MaxThreads];
+
+ bool includeSquashInst[Impl::MaxThreads];
};
template<class Impl>
@@ -91,73 +98,100 @@ struct IssueStruct {
DynInstPtr insts[Impl::MaxWidth];
};
+template<class Impl>
struct TimeBufStruct {
struct decodeComm {
bool squash;
- bool stall;
bool predIncorrect;
uint64_t branchAddr;
InstSeqNum doneSeqNum;
- // Might want to package this kind of branch stuff into a single
+ // @todo: Might want to package this kind of branch stuff into a single
// struct as it is used pretty frequently.
bool branchMispredict;
bool branchTaken;
uint64_t mispredPC;
uint64_t nextPC;
+
+ unsigned branchCount;
};
- decodeComm decodeInfo;
+ decodeComm decodeInfo[Impl::MaxThreads];
// Rename can't actually tell anything to squash or send a new PC back
// because it doesn't do anything along those lines. But maybe leave
// these fields in here to keep the stages mostly orthagonal.
struct renameComm {
bool squash;
- bool stall;
uint64_t nextPC;
};
- renameComm renameInfo;
+ renameComm renameInfo[Impl::MaxThreads];
struct iewComm {
- bool stall;
-
// Also eventually include skid buffer space.
+ bool usedIQ;
unsigned freeIQEntries;
+ bool usedLSQ;
+ unsigned freeLSQEntries;
+
+ unsigned iqCount;
+ unsigned ldstqCount;
+
+ unsigned dispatched;
+ unsigned dispatchedToLSQ;
};
- iewComm iewInfo;
+ iewComm iewInfo[Impl::MaxThreads];
struct commitComm {
- bool squash;
- bool stall;
+ bool usedROB;
unsigned freeROBEntries;
+ bool emptyROB;
+
+ bool squash;
+ bool robSquashing;
bool branchMispredict;
bool branchTaken;
uint64_t mispredPC;
uint64_t nextPC;
- bool robSquashing;
-
// Represents the instruction that has either been retired or
// squashed. Similar to having a single bus that broadcasts the
// retired or squashed sequence number.
InstSeqNum doneSeqNum;
- // Extra bit of information so that the LDSTQ only updates when it
- // needs to.
- bool commitIsLoad;
+ //Just in case we want to do a commit/squash on a cycle
+ //(necessary for multiple ROBs?)
+ bool commitInsts;
+ InstSeqNum squashSeqNum;
// Communication specifically to the IQ to tell the IQ that it can
// schedule a non-speculative instruction.
InstSeqNum nonSpecSeqNum;
+
+ // Hack for now to send back an uncached access to the IEW stage.
+ typedef typename Impl::DynInstPtr DynInstPtr;
+ bool uncached;
+ DynInstPtr uncachedLoad;
+
+ bool interruptPending;
+ bool clearInterrupt;
};
- commitComm commitInfo;
+ commitComm commitInfo[Impl::MaxThreads];
+
+ bool decodeBlock[Impl::MaxThreads];
+ bool decodeUnblock[Impl::MaxThreads];
+ bool renameBlock[Impl::MaxThreads];
+ bool renameUnblock[Impl::MaxThreads];
+ bool iewBlock[Impl::MaxThreads];
+ bool iewUnblock[Impl::MaxThreads];
+ bool commitBlock[Impl::MaxThreads];
+ bool commitUnblock[Impl::MaxThreads];
};
-#endif //__CPU_O3_CPU_COMM_HH__
+#endif //__CPU_O3_COMM_HH__
diff --git a/src/cpu/o3/commit.cc b/src/cpu/o3/commit.cc
index cf33d7f8b..fe5e9c1de 100644
--- a/src/cpu/o3/commit.cc
+++ b/src/cpu/o3/commit.cc
@@ -30,4 +30,4 @@
#include "cpu/o3/alpha_impl.hh"
#include "cpu/o3/commit_impl.hh"
-template class SimpleCommit<AlphaSimpleImpl>;
+template class DefaultCommit<AlphaSimpleImpl>;
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 580c1a316..66abf8dc6 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,29 +26,43 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-// Todo: Maybe have a special method for handling interrupts/traps.
-//
-// Traps: Have IEW send a signal to commit saying that there's a trap to
-// be handled. Have commit send the PC back to the fetch stage, along
-// with the current commit PC. Fetch will directly access the IPR and save
-// off all the proper stuff. Commit can send out a squash, or something
-// close to it.
-// Do the same for hwrei(). However, requires that commit be specifically
-// built to support that kind of stuff. Probably not horrible to have
-// commit support having the CPU tell it to squash the other stages and
-// restart at a given address. The IPR register does become an issue.
-// Probably not a big deal if the IPR stuff isn't cycle accurate. Can just
-// have the original function handle writing to the IPR register.
-
-#ifndef __CPU_O3_CPU_SIMPLE_COMMIT_HH__
-#define __CPU_O3_CPU_SIMPLE_COMMIT_HH__
+#ifndef __CPU_O3_COMMIT_HH__
+#define __CPU_O3_COMMIT_HH__
+#include "arch/faults.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
+#include "cpu/exetrace.hh"
+#include "cpu/inst_seq.hh"
#include "mem/memory_interface.hh"
+template <class>
+class O3ThreadState;
+
+/**
+ * DefaultCommit handles single threaded and SMT commit. Its width is
+ * specified by the parameters; each cycle it tries to commit that
+ * many instructions. The SMT policy decides which thread it tries to
+ * commit instructions from. Non- speculative instructions must reach
+ * the head of the ROB before they are ready to execute; once they
+ * reach the head, commit will broadcast the instruction's sequence
+ * number to the previous stages so that they can issue/ execute the
+ * instruction. Only one non-speculative instruction is handled per
+ * cycle. Commit is responsible for handling all back-end initiated
+ * redirects. It receives the redirect, and then broadcasts it to all
+ * stages, indicating the sequence number they should squash until,
+ * and any necessary branch misprediction information as well. It
+ * priortizes redirects by instruction's age, only broadcasting a
+ * redirect if it corresponds to an instruction that should currently
+ * be in the ROB. This is done by tracking the sequence number of the
+ * youngest instruction in the ROB, which gets updated to any
+ * squashing instruction's sequence number, and only broadcasting a
+ * redirect if it corresponds to an older instruction. Commit also
+ * supports multiple cycle squashing, to model a ROB that can only
+ * remove a certain number of instructions per cycle.
+ */
template<class Impl>
-class SimpleCommit
+class DefaultCommit
{
public:
// Typedefs from the Impl.
@@ -57,62 +71,201 @@ class SimpleCommit
typedef typename Impl::Params Params;
typedef typename Impl::CPUPol CPUPol;
+ typedef typename CPUPol::RenameMap RenameMap;
typedef typename CPUPol::ROB ROB;
typedef typename CPUPol::TimeStruct TimeStruct;
+ typedef typename CPUPol::FetchStruct FetchStruct;
typedef typename CPUPol::IEWStruct IEWStruct;
typedef typename CPUPol::RenameStruct RenameStruct;
- public:
- // I don't believe commit can block, so it will only have two
- // statuses for now.
- // Actually if there's a cache access that needs to block (ie
- // uncachable load or just a mem access in commit) then the stage
- // may have to wait.
- enum Status {
+ typedef typename CPUPol::Fetch Fetch;
+ typedef typename CPUPol::IEW IEW;
+
+ typedef O3ThreadState<Impl> Thread;
+
+ class TrapEvent : public Event {
+ private:
+ DefaultCommit<Impl> *commit;
+ unsigned tid;
+
+ public:
+ TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid);
+
+ void process();
+ const char *description();
+ };
+
+ /** Overall commit status. Used to determine if the CPU can deschedule
+ * itself due to a lack of activity.
+ */
+ enum CommitStatus{
+ Active,
+ Inactive
+ };
+
+ /** Individual thread status. */
+ enum ThreadStatus {
Running,
Idle,
ROBSquashing,
- DcacheMissStall,
- DcacheMissComplete
+ TrapPending,
+ FetchTrapPending
+ };
+
+ /** Commit policy for SMT mode. */
+ enum CommitPolicy {
+ Aggressive,
+ RoundRobin,
+ OldestReady
};
private:
- Status _status;
+ /** Overall commit status. */
+ CommitStatus _status;
+ /** Next commit status, to be set at the end of the cycle. */
+ CommitStatus _nextStatus;
+ /** Per-thread status. */
+ ThreadStatus commitStatus[Impl::MaxThreads];
+ /** Commit policy used in SMT mode. */
+ CommitPolicy commitPolicy;
public:
- SimpleCommit(Params &params);
+ /** Construct a DefaultCommit with the given parameters. */
+ DefaultCommit(Params *params);
+
+ /** Returns the name of the DefaultCommit. */
+ std::string name() const;
+ /** Registers statistics. */
void regStats();
+ /** Sets the CPU pointer. */
void setCPU(FullCPU *cpu_ptr);
+ /** Sets the list of threads. */
+ void setThreads(std::vector<Thread *> &threads);
+
+ /** Sets the main time buffer pointer, used for backwards communication. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
+ void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
+
+ /** Sets the pointer to the queue coming from rename. */
void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
+ /** Sets the pointer to the queue coming from IEW. */
void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
+ void setFetchStage(Fetch *fetch_stage);
+
+ Fetch *fetchStage;
+
+ /** Sets the poitner to the IEW stage. */
+ void setIEWStage(IEW *iew_stage);
+
+ /** The pointer to the IEW stage. Used solely to ensure that
+ * various events (traps, interrupts, syscalls) do not occur until
+ * all stores have written back.
+ */
+ IEW *iewStage;
+
+ /** Sets pointer to list of active threads. */
+ void setActiveThreads(std::list<unsigned> *at_ptr);
+
+ /** Sets pointer to the commited state rename map. */
+ void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
+
+ /** Sets pointer to the ROB. */
void setROB(ROB *rob_ptr);
+ /** Initializes stage by sending back the number of free entries. */
+ void initStage();
+
+ void switchOut();
+
+ void doSwitchOut();
+
+ void takeOverFrom();
+
+ /** Ticks the commit stage, which tries to commit instructions. */
void tick();
+ /** Handles any squashes that are sent from IEW, and adds instructions
+ * to the ROB and tries to commit instructions.
+ */
void commit();
+ /** Returns the number of free ROB entries for a specific thread. */
+ unsigned numROBFreeEntries(unsigned tid);
+
+ void generateXCEvent(unsigned tid);
+
private:
+ /** Updates the overall status of commit with the nextStatus, and
+ * tell the CPU if commit is active/inactive. */
+ void updateStatus();
+
+ /** Sets the next status based on threads' statuses, which becomes the
+ * current status at the end of the cycle.
+ */
+ void setNextStatus();
+
+ /** Checks if the ROB is completed with squashing. This is for the case
+ * where the ROB can take multiple cycles to complete squashing.
+ */
+ bool robDoneSquashing();
+
+ /** Returns if any of the threads have the number of ROB entries changed
+ * on this cycle. Used to determine if the number of free ROB entries needs
+ * to be sent back to previous stages.
+ */
+ bool changedROBEntries();
+ void squashAll(unsigned tid);
+
+ void squashFromTrap(unsigned tid);
+
+ void squashFromXC(unsigned tid);
+
+ /** Commits as many instructions as possible. */
void commitInsts();
+ /** Tries to commit the head ROB instruction passed in.
+ * @param head_inst The instruction to be committed.
+ */
bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
+ void generateTrapEvent(unsigned tid);
+
+ /** Gets instructions from rename and inserts them into the ROB. */
void getInsts();
+ /** Marks completed instructions using information sent from IEW. */
void markCompletedInsts();
+ /** Gets the thread to commit, based on the SMT policy. */
+ int getCommittingThread();
+
+ /** Returns the thread ID to use based on a round robin policy. */
+ int roundRobin();
+
+ /** Returns the thread ID to use based on an oldest instruction policy. */
+ int oldestReady();
+
public:
- uint64_t readCommitPC();
+ /** Returns the PC of the head instruction of the ROB.
+ * @todo: Probably remove this function as it returns only thread 0.
+ */
+ uint64_t readPC() { return PC[0]; }
+
+ uint64_t readPC(unsigned tid) { return PC[tid]; }
+
+ void setPC(uint64_t val, unsigned tid) { PC[tid] = val; }
- void setSquashing() { _status = ROBSquashing; }
+ uint64_t readNextPC(unsigned tid) { return nextPC[tid]; }
+
+ void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; }
private:
/** Time buffer interface. */
@@ -124,6 +277,10 @@ class SimpleCommit
/** Wire to read information from IEW (for ROB). */
typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
+ TimeBuffer<FetchStruct> *fetchQueue;
+
+ typename TimeBuffer<FetchStruct>::wire fromFetch;
+
/** IEW instruction queue interface. */
TimeBuffer<IEWStruct> *iewQueue;
@@ -136,22 +293,56 @@ class SimpleCommit
/** Wire to read information from rename queue. */
typename TimeBuffer<RenameStruct>::wire fromRename;
+ public:
/** ROB interface. */
ROB *rob;
+ private:
/** Pointer to FullCPU. */
FullCPU *cpu;
/** Memory interface. Used for d-cache accesses. */
MemInterface *dcacheInterface;
- private:
+ std::vector<Thread *> thread;
+
+ Fault fetchFault;
+
+ int fetchTrapWait;
+
+ /** Records that commit has written to the time buffer this cycle. Used for
+ * the CPU to determine if it can deschedule itself if there is no activity.
+ */
+ bool wroteToTimeBuffer;
+
+ /** Records if the number of ROB entries has changed this cycle. If it has,
+ * then the number of free entries must be re-broadcast.
+ */
+ bool changedROBNumEntries[Impl::MaxThreads];
+
+ /** A counter of how many threads are currently squashing. */
+ int squashCounter;
+
+ /** Records if a thread has to squash this cycle due to a trap. */
+ bool trapSquash[Impl::MaxThreads];
+
+ /** Records if a thread has to squash this cycle due to an XC write. */
+ bool xcSquash[Impl::MaxThreads];
+
+ /** Priority List used for Commit Policy */
+ std::list<unsigned> priority_list;
+
/** IEW to Commit delay, in ticks. */
unsigned iewToCommitDelay;
+ /** Commit to IEW delay, in ticks. */
+ unsigned commitToIEWDelay;
+
/** Rename to ROB delay, in ticks. */
unsigned renameToROBDelay;
+ unsigned fetchToCommitDelay;
+
/** Rename width, in instructions. Used so ROB knows how many
* instructions to get from the rename instruction queue.
*/
@@ -165,16 +356,69 @@ class SimpleCommit
/** Commit width, in instructions. */
unsigned commitWidth;
+ /** Number of Reorder Buffers */
+ unsigned numRobs;
+
+ /** Number of Active Threads */
+ unsigned numThreads;
+
+ bool switchPending;
+ bool switchedOut;
+
+ Tick trapLatency;
+
+ Tick fetchTrapLatency;
+
+ Tick fetchFaultTick;
+
+ Addr PC[Impl::MaxThreads];
+
+ Addr nextPC[Impl::MaxThreads];
+
+ /** The sequence number of the youngest valid instruction in the ROB. */
+ InstSeqNum youngestSeqNum[Impl::MaxThreads];
+
+ /** Pointer to the list of active threads. */
+ std::list<unsigned> *activeThreads;
+
+ /** Rename map interface. */
+ RenameMap *renameMap[Impl::MaxThreads];
+
+ void updateComInstStats(DynInstPtr &inst);
+
+ /** Stat for the total number of committed instructions. */
Stats::Scalar<> commitCommittedInsts;
+ /** Stat for the total number of squashed instructions discarded by commit.
+ */
Stats::Scalar<> commitSquashedInsts;
+ /** Stat for the total number of times commit is told to squash.
+ * @todo: Actually increment this stat.
+ */
Stats::Scalar<> commitSquashEvents;
+ /** Stat for the total number of times commit has had to stall due to a non-
+ * speculative instruction reaching the head of the ROB.
+ */
Stats::Scalar<> commitNonSpecStalls;
- Stats::Scalar<> commitCommittedBranches;
- Stats::Scalar<> commitCommittedLoads;
- Stats::Scalar<> commitCommittedMemRefs;
+ /** Stat for the total number of branch mispredicts that caused a squash. */
Stats::Scalar<> branchMispredicts;
-
- Stats::Distribution<> n_committed_dist;
+ /** Distribution of the number of committed instructions each cycle. */
+ Stats::Distribution<> numCommittedDist;
+
+ /** Total number of instructions committed. */
+ Stats::Vector<> statComInst;
+ /** Total number of software prefetches committed. */
+ Stats::Vector<> statComSwp;
+ /** Stat for the total number of committed memory references. */
+ Stats::Vector<> statComRefs;
+ /** Stat for the total number of committed loads. */
+ Stats::Vector<> statComLoads;
+ /** Total number of committed memory barriers. */
+ Stats::Vector<> statComMembars;
+ /** Total number of committed branches. */
+ Stats::Vector<> statComBranches;
+
+ Stats::Scalar<> commitEligibleSamples;
+ Stats::Vector<> commitEligible;
};
-#endif // __CPU_O3_CPU_SIMPLE_COMMIT_HH__
+#endif // __CPU_O3_COMMIT_HH__
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index e289bc0c0..346a8bc1c 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,26 +26,112 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include <algorithm>
+#include <string>
+
+#include "base/loader/symtab.hh"
#include "base/timebuf.hh"
-#include "cpu/o3/commit.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/exetrace.hh"
+#include "cpu/o3/commit.hh"
+#include "cpu/o3/thread_state.hh"
+
+using namespace std;
template <class Impl>
-SimpleCommit<Impl>::SimpleCommit(Params &params)
- : dcacheInterface(params.dcacheInterface),
- iewToCommitDelay(params.iewToCommitDelay),
- renameToROBDelay(params.renameToROBDelay),
- renameWidth(params.renameWidth),
- iewWidth(params.executeWidth),
- commitWidth(params.commitWidth)
+DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
+ unsigned _tid)
+ : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
{
- _status = Idle;
+ this->setFlags(Event::AutoDelete);
}
template <class Impl>
void
-SimpleCommit<Impl>::regStats()
+DefaultCommit<Impl>::TrapEvent::process()
+{
+ // This will get reset by commit if it was switched out at the
+ // time of this event processing.
+ commit->trapSquash[tid] = true;
+}
+
+template <class Impl>
+const char *
+DefaultCommit<Impl>::TrapEvent::description()
+{
+ return "Trap event";
+}
+
+template <class Impl>
+DefaultCommit<Impl>::DefaultCommit(Params *params)
+ : dcacheInterface(params->dcacheInterface),
+ squashCounter(0),
+ iewToCommitDelay(params->iewToCommitDelay),
+ commitToIEWDelay(params->commitToIEWDelay),
+ renameToROBDelay(params->renameToROBDelay),
+ fetchToCommitDelay(params->commitToFetchDelay),
+ renameWidth(params->renameWidth),
+ iewWidth(params->executeWidth),
+ commitWidth(params->commitWidth),
+ numThreads(params->numberOfThreads),
+ switchedOut(false),
+ trapLatency(params->trapLatency),
+ fetchTrapLatency(params->fetchTrapLatency)
{
+ _status = Active;
+ _nextStatus = Inactive;
+ string policy = params->smtCommitPolicy;
+
+ //Convert string to lowercase
+ std::transform(policy.begin(), policy.end(), policy.begin(),
+ (int(*)(int)) tolower);
+
+ //Assign commit policy
+ if (policy == "aggressive"){
+ commitPolicy = Aggressive;
+
+ DPRINTF(Commit,"Commit Policy set to Aggressive.");
+ } else if (policy == "roundrobin"){
+ commitPolicy = RoundRobin;
+
+ //Set-Up Priority List
+ for (int tid=0; tid < numThreads; tid++) {
+ priority_list.push_back(tid);
+ }
+
+ DPRINTF(Commit,"Commit Policy set to Round Robin.");
+ } else if (policy == "oldestready"){
+ commitPolicy = OldestReady;
+
+ DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
+ } else {
+ assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
+ "RoundRobin,OldestReady}");
+ }
+
+ for (int i=0; i < numThreads; i++) {
+ commitStatus[i] = Idle;
+ changedROBNumEntries[i] = false;
+ trapSquash[i] = false;
+ xcSquash[i] = false;
+ }
+
+ fetchFaultTick = 0;
+ fetchTrapWait = 0;
+}
+
+template <class Impl>
+std::string
+DefaultCommit<Impl>::name() const
+{
+ return cpu->name() + ".commit";
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::regStats()
+{
+ using namespace Stats;
commitCommittedInsts
.name(name() + ".commitCommittedInsts")
.desc("The number of committed instructions")
@@ -63,41 +149,110 @@ SimpleCommit<Impl>::regStats()
.desc("The number of times commit has been forced to stall to "
"communicate backwards")
.prereq(commitNonSpecStalls);
- commitCommittedBranches
- .name(name() + ".commitCommittedBranches")
- .desc("The number of committed branches")
- .prereq(commitCommittedBranches);
- commitCommittedLoads
- .name(name() + ".commitCommittedLoads")
- .desc("The number of committed loads")
- .prereq(commitCommittedLoads);
- commitCommittedMemRefs
- .name(name() + ".commitCommittedMemRefs")
- .desc("The number of committed memory references")
- .prereq(commitCommittedMemRefs);
branchMispredicts
.name(name() + ".branchMispredicts")
.desc("The number of times a branch was mispredicted")
.prereq(branchMispredicts);
- n_committed_dist
+ numCommittedDist
.init(0,commitWidth,1)
.name(name() + ".COM:committed_per_cycle")
.desc("Number of insts commited each cycle")
.flags(Stats::pdf)
;
+
+ statComInst
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:count")
+ .desc("Number of instructions committed")
+ .flags(total)
+ ;
+
+ statComSwp
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:swp_count")
+ .desc("Number of s/w prefetches committed")
+ .flags(total)
+ ;
+
+ statComRefs
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:refs")
+ .desc("Number of memory references committed")
+ .flags(total)
+ ;
+
+ statComLoads
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:loads")
+ .desc("Number of loads committed")
+ .flags(total)
+ ;
+
+ statComMembars
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:membars")
+ .desc("Number of memory barriers committed")
+ .flags(total)
+ ;
+
+ statComBranches
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:branches")
+ .desc("Number of branches committed")
+ .flags(total)
+ ;
+
+ //
+ // Commit-Eligible instructions...
+ //
+ // -> The number of instructions eligible to commit in those
+ // cycles where we reached our commit BW limit (less the number
+ // actually committed)
+ //
+ // -> The average value is computed over ALL CYCLES... not just
+ // the BW limited cycles
+ //
+ // -> The standard deviation is computed only over cycles where
+ // we reached the BW limit
+ //
+ commitEligible
+ .init(cpu->number_of_threads)
+ .name(name() + ".COM:bw_limited")
+ .desc("number of insts not committed due to BW limits")
+ .flags(total)
+ ;
+
+ commitEligibleSamples
+ .name(name() + ".COM:bw_lim_events")
+ .desc("number cycles where commit BW limit reached")
+ ;
}
template <class Impl>
void
-SimpleCommit<Impl>::setCPU(FullCPU *cpu_ptr)
+DefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr)
{
DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
cpu = cpu_ptr;
+
+ // Commit must broadcast the number of free entries it has at the start of
+ // the simulation, so it starts as active.
+ cpu->activateStage(FullCPU::CommitIdx);
+
+ trapLatency = cpu->cycles(trapLatency);
+ fetchTrapLatency = cpu->cycles(fetchTrapLatency);
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
+{
+ thread = threads;
}
template <class Impl>
void
-SimpleCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
+DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
{
DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
timeBuffer = tb_ptr;
@@ -111,7 +266,18 @@ SimpleCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
template <class Impl>
void
-SimpleCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
+DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
+{
+ DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
+ fetchQueue = fq_ptr;
+
+ // Setup wire to get instructions from rename (for the ROB).
+ fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
{
DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
renameQueue = rq_ptr;
@@ -122,7 +288,7 @@ SimpleCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
template <class Impl>
void
-SimpleCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
+DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
{
DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
iewQueue = iq_ptr;
@@ -133,7 +299,40 @@ SimpleCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
template <class Impl>
void
-SimpleCommit<Impl>::setROB(ROB *rob_ptr)
+DefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage)
+{
+ fetchStage = fetch_stage;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
+{
+ iewStage = iew_stage;
+}
+
+template<class Impl>
+void
+DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+{
+ DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
+ activeThreads = at_ptr;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
+{
+ DPRINTF(Commit, "Setting rename map pointers.\n");
+
+ for (int i=0; i < numThreads; i++) {
+ renameMap[i] = &rm_ptr[i];
+ }
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::setROB(ROB *rob_ptr)
{
DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
rob = rob_ptr;
@@ -141,107 +340,451 @@ SimpleCommit<Impl>::setROB(ROB *rob_ptr)
template <class Impl>
void
-SimpleCommit<Impl>::tick()
-{
- // If the ROB is currently in its squash sequence, then continue
- // to squash. In this case, commit does not do anything. Otherwise
- // run commit.
- if (_status == ROBSquashing) {
- if (rob->isDoneSquashing()) {
- _status = Running;
- } else {
- rob->doSquash();
-
- // Send back sequence number of tail of ROB, so other stages
- // can squash younger instructions. Note that really the only
- // stage that this is important for is the IEW stage; other
- // stages can just clear all their state as long as selective
- // replay isn't used.
- toIEW->commitInfo.doneSeqNum = rob->readTailSeqNum();
- toIEW->commitInfo.robSquashing = true;
+DefaultCommit<Impl>::initStage()
+{
+ rob->setActiveThreads(activeThreads);
+ rob->resetEntries();
+
+ // Broadcast the number of free entries.
+ for (int i=0; i < numThreads; i++) {
+ toIEW->commitInfo[i].usedROB = true;
+ toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
+ }
+
+ cpu->activityThisCycle();
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::switchOut()
+{
+ switchPending = true;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::doSwitchOut()
+{
+ switchedOut = true;
+ switchPending = false;
+ rob->switchOut();
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::takeOverFrom()
+{
+ switchedOut = false;
+ _status = Active;
+ _nextStatus = Inactive;
+ for (int i=0; i < numThreads; i++) {
+ commitStatus[i] = Idle;
+ changedROBNumEntries[i] = false;
+ trapSquash[i] = false;
+ xcSquash[i] = false;
+ }
+ squashCounter = 0;
+ rob->takeOverFrom();
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::updateStatus()
+{
+ // reset ROB changed variable
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+ changedROBNumEntries[tid] = false;
+
+ // Also check if any of the threads has a trap pending
+ if (commitStatus[tid] == TrapPending ||
+ commitStatus[tid] == FetchTrapPending) {
+ _nextStatus = Active;
}
- } else {
- commit();
}
+ if (_nextStatus == Inactive && _status == Active) {
+ DPRINTF(Activity, "Deactivating stage.\n");
+ cpu->deactivateStage(FullCPU::CommitIdx);
+ } else if (_nextStatus == Active && _status == Inactive) {
+ DPRINTF(Activity, "Activating stage.\n");
+ cpu->activateStage(FullCPU::CommitIdx);
+ }
+
+ _status = _nextStatus;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::setNextStatus()
+{
+ int squashes = 0;
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ if (commitStatus[tid] == ROBSquashing) {
+ squashes++;
+ }
+ }
+
+ assert(squashes == squashCounter);
+
+ // If commit is currently squashing, then it will have activity for the
+ // next cycle. Set its next status as active.
+ if (squashCounter) {
+ _nextStatus = Active;
+ }
+}
+
+template <class Impl>
+bool
+DefaultCommit<Impl>::changedROBEntries()
+{
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ if (changedROBNumEntries[tid]) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+template <class Impl>
+unsigned
+DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
+{
+ return rob->numFreeEntries(tid);
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
+{
+ DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
+
+ TrapEvent *trap = new TrapEvent(this, tid);
+
+ trap->schedule(curTick + trapLatency);
+
+ thread[tid]->trapPending = true;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::generateXCEvent(unsigned tid)
+{
+ DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid);
+
+ xcSquash[tid] = true;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::squashAll(unsigned tid)
+{
+ // If we want to include the squashing instruction in the squash,
+ // then use one older sequence number.
+ // Hopefully this doesn't mess things up. Basically I want to squash
+ // all instructions of this thread.
+ InstSeqNum squashed_inst = rob->isEmpty() ?
+ 0 : rob->readHeadInst(tid)->seqNum - 1;;
+
+ // All younger instructions will be squashed. Set the sequence
+ // number as the youngest instruction in the ROB (0 in this case.
+ // Hopefully nothing breaks.)
+ youngestSeqNum[tid] = 0;
+
+ rob->squash(squashed_inst, tid);
+ changedROBNumEntries[tid] = true;
+
+ // Send back the sequence number of the squashed instruction.
+ toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
+
+ // Send back the squash signal to tell stages that they should
+ // squash.
+ toIEW->commitInfo[tid].squash = true;
+
+ // Send back the rob squashing signal so other stages know that
+ // the ROB is in the process of squashing.
+ toIEW->commitInfo[tid].robSquashing = true;
+
+ toIEW->commitInfo[tid].branchMispredict = false;
+
+ toIEW->commitInfo[tid].nextPC = PC[tid];
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::squashFromTrap(unsigned tid)
+{
+ squashAll(tid);
+
+ DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
+
+ thread[tid]->trapPending = false;
+ thread[tid]->inSyscall = false;
+
+ trapSquash[tid] = false;
+
+ commitStatus[tid] = ROBSquashing;
+ cpu->activityThisCycle();
+
+ ++squashCounter;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::squashFromXC(unsigned tid)
+{
+ squashAll(tid);
+
+ DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]);
+
+ thread[tid]->inSyscall = false;
+ assert(!thread[tid]->trapPending);
+
+ commitStatus[tid] = ROBSquashing;
+ cpu->activityThisCycle();
+
+ xcSquash[tid] = false;
+
+ ++squashCounter;
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::tick()
+{
+ wroteToTimeBuffer = false;
+ _nextStatus = Inactive;
+
+ if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
+ cpu->signalSwitched();
+ return;
+ }
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ // Check if any of the threads are done squashing. Change the
+ // status if they are done.
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ if (commitStatus[tid] == ROBSquashing) {
+
+ if (rob->isDoneSquashing(tid)) {
+ commitStatus[tid] = Running;
+ --squashCounter;
+ } else {
+ DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
+ "insts this cycle.\n", tid);
+ }
+ }
+ }
+
+ commit();
+
markCompletedInsts();
- // Writeback number of free ROB entries here.
- DPRINTF(Commit, "Commit: ROB has %d free entries.\n",
- rob->numFreeEntries());
- toIEW->commitInfo.freeROBEntries = rob->numFreeEntries();
+ threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
+ // The ROB has more instructions it can commit. Its next status
+ // will be active.
+ _nextStatus = Active;
+
+ DynInstPtr inst = rob->readHeadInst(tid);
+
+ DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
+ " ROB and ready to commit\n",
+ tid, inst->seqNum, inst->readPC());
+
+ } else if (!rob->isEmpty(tid)) {
+ DynInstPtr inst = rob->readHeadInst(tid);
+
+ DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
+ "%#x is head of ROB and not ready\n",
+ tid, inst->seqNum, inst->readPC());
+ }
+
+ DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
+ tid, rob->countInsts(tid), rob->numFreeEntries(tid));
+ }
+
+
+ if (wroteToTimeBuffer) {
+ DPRINTF(Activity, "Activity This Cycle.\n");
+ cpu->activityThisCycle();
+ }
+
+ updateStatus();
}
template <class Impl>
void
-SimpleCommit<Impl>::commit()
+DefaultCommit<Impl>::commit()
{
+
//////////////////////////////////////
// Check for interrupts
//////////////////////////////////////
- // Process interrupts if interrupts are enabled and not in PAL mode.
- // Take the PC from commit and write it to the IPR, then squash. The
- // interrupt completing will take care of restoring the PC from that value
- // in the IPR. Look at IPR[EXC_ADDR];
- // hwrei() is what resets the PC to the place where instruction execution
- // beings again.
#if FULL_SYSTEM
- if (//checkInterrupts &&
+ // Process interrupts if interrupts are enabled, not in PAL mode,
+ // and no other traps or external squashes are currently pending.
+ // @todo: Allow other threads to handle interrupts.
+ if (cpu->checkInterrupts &&
cpu->check_interrupts() &&
- !cpu->inPalMode(readCommitPC())) {
- // Will need to squash all instructions currently in flight and have
- // the interrupt handler restart at the last non-committed inst.
- // Most of that can be handled through the trap() function. The
- // processInterrupts() function really just checks for interrupts
- // and then calls trap() if there is an interrupt present.
+ !cpu->inPalMode(readPC()) &&
+ !trapSquash[0] &&
+ !xcSquash[0]) {
+ // Tell fetch that there is an interrupt pending. This will
+ // make fetch wait until it sees a non PAL-mode PC, at which
+ // point it stops fetching instructions.
+ toIEW->commitInfo[0].interruptPending = true;
+
+ // Wait until the ROB is empty and all stores have drained in
+ // order to enter the interrupt.
+ if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
+ // Not sure which thread should be the one to interrupt. For now
+ // always do thread 0.
+ assert(!thread[0]->inSyscall);
+ thread[0]->inSyscall = true;
+
+ // CPU will handle implementation of the interrupt.
+ cpu->processInterrupts();
+
+ // Now squash or record that I need to squash this cycle.
+ commitStatus[0] = TrapPending;
+
+ // Exit state update mode to avoid accidental updating.
+ thread[0]->inSyscall = false;
+
+ // Generate trap squash event.
+ generateTrapEvent(0);
- // CPU will handle implementation of the interrupt.
- cpu->processInterrupts();
+ toIEW->commitInfo[0].clearInterrupt = true;
+
+ DPRINTF(Commit, "Interrupt detected.\n");
+ } else {
+ DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
+ }
}
#endif // FULL_SYSTEM
////////////////////////////////////
- // Check for squash signal, handle that first
+ // Check for any possible squashes, handle them first
////////////////////////////////////
- // Want to mainly check if the IEW stage is telling the ROB to squash.
- // Should I also check if the commit stage is telling the ROB to squah?
- // This might be necessary to keep the same timing between the IQ and
- // the ROB...
- if (fromIEW->squash) {
- DPRINTF(Commit, "Commit: Squashing instructions in the ROB.\n");
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ if (fromFetch->fetchFault && commitStatus[0] != TrapPending) {
+ // Record the fault. Wait until it's empty in the ROB.
+ // Then handle the trap. Ignore it if there's already a
+ // trap pending as fetch will be redirected.
+ fetchFault = fromFetch->fetchFault;
+ fetchFaultTick = curTick + fetchTrapLatency;
+ commitStatus[0] = FetchTrapPending;
+ DPRINTF(Commit, "Fault from fetch recorded. Will trap if the "
+ "ROB empties without squashing the fault.\n");
+ fetchTrapWait = 0;
+ }
+
+ // Fetch may tell commit to clear the trap if it's been squashed.
+ if (fromFetch->clearFetchFault) {
+ DPRINTF(Commit, "Received clear fetch fault signal\n");
+ fetchTrapWait = 0;
+ if (commitStatus[0] == FetchTrapPending) {
+ DPRINTF(Commit, "Clearing fault from fetch\n");
+ commitStatus[0] = Running;
+ }
+ }
+
+ // Not sure which one takes priority. I think if we have
+ // both, that's a bad sign.
+ if (trapSquash[tid] == true) {
+ assert(!xcSquash[tid]);
+ squashFromTrap(tid);
+ } else if (xcSquash[tid] == true) {
+ squashFromXC(tid);
+ }
+
+ // Squashed sequence number must be older than youngest valid
+ // instruction in the ROB. This prevents squashes from younger
+ // instructions overriding squashes from older instructions.
+ if (fromIEW->squash[tid] &&
+ commitStatus[tid] != TrapPending &&
+ fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
+
+ DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
+ tid,
+ fromIEW->mispredPC[tid],
+ fromIEW->squashedSeqNum[tid]);
- _status = ROBSquashing;
+ DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
+ tid,
+ fromIEW->nextPC[tid]);
- InstSeqNum squashed_inst = fromIEW->squashedSeqNum;
+ commitStatus[tid] = ROBSquashing;
- rob->squash(squashed_inst);
+ ++squashCounter;
- // Send back the sequence number of the squashed instruction.
- toIEW->commitInfo.doneSeqNum = squashed_inst;
+ // If we want to include the squashing instruction in the squash,
+ // then use one older sequence number.
+ InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
- // Send back the squash signal to tell stages that they should squash.
- toIEW->commitInfo.squash = true;
+ if (fromIEW->includeSquashInst[tid] == true)
+ squashed_inst--;
- // Send back the rob squashing signal so other stages know that the
- // ROB is in the process of squashing.
- toIEW->commitInfo.robSquashing = true;
+ // All younger instructions will be squashed. Set the sequence
+ // number as the youngest instruction in the ROB.
+ youngestSeqNum[tid] = squashed_inst;
- toIEW->commitInfo.branchMispredict = fromIEW->branchMispredict;
+ rob->squash(squashed_inst, tid);
+ changedROBNumEntries[tid] = true;
- toIEW->commitInfo.branchTaken = fromIEW->branchTaken;
+ toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
- toIEW->commitInfo.nextPC = fromIEW->nextPC;
+ toIEW->commitInfo[tid].squash = true;
- toIEW->commitInfo.mispredPC = fromIEW->mispredPC;
+ // Send back the rob squashing signal so other stages know that
+ // the ROB is in the process of squashing.
+ toIEW->commitInfo[tid].robSquashing = true;
- if (toIEW->commitInfo.branchMispredict) {
- ++branchMispredicts;
+ toIEW->commitInfo[tid].branchMispredict =
+ fromIEW->branchMispredict[tid];
+
+ toIEW->commitInfo[tid].branchTaken =
+ fromIEW->branchTaken[tid];
+
+ toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
+
+ toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
+
+ if (toIEW->commitInfo[tid].branchMispredict) {
+ ++branchMispredicts;
+ }
}
+
}
- if (_status != ROBSquashing) {
+ setNextStatus();
+
+ if (squashCounter != numThreads) {
// If we're not currently squashing, then get instructions.
getInsts();
@@ -249,121 +792,185 @@ SimpleCommit<Impl>::commit()
commitInsts();
}
- // If the ROB is empty, we can set this stage to idle. Use this
- // in the future when the Idle status will actually be utilized.
-#if 0
- if (rob->isEmpty()) {
- DPRINTF(Commit, "Commit: ROB is empty. Status changed to idle.\n");
- _status = Idle;
- // Schedule an event so that commit will actually wake up
- // once something gets put in the ROB.
+ //Check for any activity
+ threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ if (changedROBNumEntries[tid]) {
+ toIEW->commitInfo[tid].usedROB = true;
+ toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
+
+ if (rob->isEmpty(tid)) {
+ toIEW->commitInfo[tid].emptyROB = true;
+ }
+
+ wroteToTimeBuffer = true;
+ changedROBNumEntries[tid] = false;
+ }
}
-#endif
}
-// Loop that goes through as many instructions in the ROB as possible and
-// tries to commit them. The actual work for committing is done by the
-// commitHead() function.
template <class Impl>
void
-SimpleCommit<Impl>::commitInsts()
+DefaultCommit<Impl>::commitInsts()
{
////////////////////////////////////
// Handle commit
- // Note that commit will be handled prior to the ROB so that the ROB
- // only tries to commit instructions it has in this current cycle, and
- // not instructions it is writing in during this cycle.
- // Can't commit and squash things at the same time...
+ // Note that commit will be handled prior to putting new
+ // instructions in the ROB so that the ROB only tries to commit
+ // instructions it has in this current cycle, and not instructions
+ // it is writing in during this cycle. Can't commit and squash
+ // things at the same time...
////////////////////////////////////
- if (rob->isEmpty())
- return;
-
- DynInstPtr head_inst = rob->readHeadInst();
+ DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
unsigned num_committed = 0;
+ DynInstPtr head_inst;
+
// Commit as many instructions as possible until the commit bandwidth
// limit is reached, or it becomes impossible to commit any more.
- while (!rob->isEmpty() &&
- head_inst->readyToCommit() &&
- num_committed < commitWidth)
- {
- DPRINTF(Commit, "Commit: Trying to commit head instruction.\n");
+ while (num_committed < commitWidth) {
+ int commit_thread = getCommittingThread();
+
+ if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
+ break;
+
+ head_inst = rob->readHeadInst(commit_thread);
+
+ int tid = head_inst->threadNumber;
+
+ assert(tid == commit_thread);
+
+ DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
+ head_inst->seqNum, tid);
- // If the head instruction is squashed, it is ready to retire at any
- // time. However, we need to avoid updating any other state
- // incorrectly if it's already been squashed.
+ // If the head instruction is squashed, it is ready to retire
+ // (be removed from the ROB) at any time.
if (head_inst->isSquashed()) {
- DPRINTF(Commit, "Commit: Retiring squashed instruction from "
+ DPRINTF(Commit, "Retiring squashed instruction from "
"ROB.\n");
- // Tell ROB to retire head instruction. This retires the head
- // inst in the ROB without affecting any other stages.
- rob->retireHead();
+ rob->retireHead(commit_thread);
++commitSquashedInsts;
+ // Record that the number of ROB entries has changed.
+ changedROBNumEntries[tid] = true;
} else {
+ PC[tid] = head_inst->readPC();
+ nextPC[tid] = head_inst->readNextPC();
+
// Increment the total number of non-speculative instructions
// executed.
// Hack for now: it really shouldn't happen until after the
// commit is deemed to be successful, but this count is needed
// for syscalls.
- cpu->funcExeInst++;
+ thread[tid]->funcExeInst++;
// Try to commit the head instruction.
bool commit_success = commitHead(head_inst, num_committed);
- // Update what instruction we are looking at if the commit worked.
if (commit_success) {
++num_committed;
- // Send back which instruction has been committed.
- // @todo: Update this later when a wider pipeline is used.
- // Hmm, can't really give a pointer here...perhaps the
- // sequence number instead (copy).
- toIEW->commitInfo.doneSeqNum = head_inst->seqNum;
+ changedROBNumEntries[tid] = true;
+
+ // Set the doneSeqNum to the youngest committed instruction.
+ toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
++commitCommittedInsts;
- if (!head_inst->isNop()) {
- cpu->instDone();
+ // To match the old model, don't count nops and instruction
+ // prefetches towards the total commit count.
+ if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
+ cpu->instDone(tid);
+ }
+
+ PC[tid] = nextPC[tid];
+ nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
+#if FULL_SYSTEM
+ int count = 0;
+ Addr oldpc;
+ do {
+ // Debug statement. Checks to make sure we're not
+ // currently updating state while handling PC events.
+ if (count == 0)
+ assert(!thread[tid]->inSyscall &&
+ !thread[tid]->trapPending);
+ oldpc = PC[tid];
+ cpu->system->pcEventQueue.service(
+ thread[tid]->getXCProxy());
+ count++;
+ } while (oldpc != PC[tid]);
+ if (count > 1) {
+ DPRINTF(Commit, "PC skip function event, stopping commit\n");
+ break;
}
+#endif
} else {
+ DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
+ "[tid:%i] [sn:%i].\n",
+ head_inst->readPC(), tid ,head_inst->seqNum);
break;
}
}
-
- // Update the pointer to read the next instruction in the ROB.
- head_inst = rob->readHeadInst();
}
DPRINTF(CommitRate, "%i\n", num_committed);
- n_committed_dist.sample(num_committed);
+ numCommittedDist.sample(num_committed);
+
+ if (num_committed == commitWidth) {
+ commitEligible[0]++;
+ }
}
template <class Impl>
bool
-SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
+DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
{
- // Make sure instruction is valid
assert(head_inst);
- // If the instruction is not executed yet, then it is a non-speculative
- // or store inst. Signal backwards that it should be executed.
+ int tid = head_inst->threadNumber;
+
+ // If the instruction is not executed yet, then it will need extra
+ // handling. Signal backwards that it should be executed.
if (!head_inst->isExecuted()) {
// Keep this number correct. We have not yet actually executed
// and committed this instruction.
- cpu->funcExeInst--;
-
- if (head_inst->isNonSpeculative()) {
- DPRINTF(Commit, "Commit: Encountered a store or non-speculative "
- "instruction at the head of the ROB, PC %#x.\n",
- head_inst->readPC());
+ thread[tid]->funcExeInst--;
+
+ head_inst->reachedCommit = true;
+
+ if (head_inst->isNonSpeculative() ||
+ head_inst->isMemBarrier() ||
+ head_inst->isWriteBarrier()) {
+
+ DPRINTF(Commit, "Encountered a barrier or non-speculative "
+ "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
+ head_inst->seqNum, head_inst->readPC());
+
+#if !FULL_SYSTEM
+ // Hack to make sure syscalls/memory barriers/quiesces
+ // aren't executed until all stores write back their data.
+ // This direct communication shouldn't be used for
+ // anything other than this.
+ if (inst_num > 0 || iewStage->hasStoresToWB())
+#else
+ if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
+ head_inst->isQuiesce()) &&
+ iewStage->hasStoresToWB())
+#endif
+ {
+ DPRINTF(Commit, "Waiting for all stores to writeback.\n");
+ return false;
+ }
- toIEW->commitInfo.nonSpecSeqNum = head_inst->seqNum;
+ toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
// Change the instruction so it won't try to commit again until
// it is executed.
@@ -372,74 +979,111 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
++commitNonSpecStalls;
return false;
+ } else if (head_inst->isLoad()) {
+ DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
+ head_inst->seqNum, head_inst->readPC());
+
+ // Send back the non-speculative instruction's sequence
+ // number. Tell the lsq to re-execute the load.
+ toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
+ toIEW->commitInfo[tid].uncached = true;
+ toIEW->commitInfo[tid].uncachedLoad = head_inst;
+
+ head_inst->clearCanCommit();
+
+ return false;
} else {
- panic("Commit: Trying to commit un-executed instruction "
+ panic("Trying to commit un-executed instruction "
"of unknown type!\n");
}
}
- // Now check if it's one of the special trap or barrier or
- // serializing instructions.
- if (head_inst->isThreadSync() ||
- head_inst->isSerializing() ||
- head_inst->isMemBarrier() ||
- head_inst->isWriteBarrier() )
- {
- // Not handled for now. Mem barriers and write barriers are safe
- // to simply let commit as memory accesses only happen once they
- // reach the head of commit. Not sure about the other two.
- panic("Serializing or barrier instructions"
- " are not handled yet.\n");
+ if (head_inst->isThreadSync()) {
+ // Not handled for now.
+ panic("Thread sync instructions are not handled yet.\n");
+ }
+
+ // Stores mark themselves as completed.
+ if (!head_inst->isStore()) {
+ head_inst->setCompleted();
+ }
+
+ // Use checker prior to updating anything due to traps or PC
+ // based events.
+ if (cpu->checker) {
+ cpu->checker->tick(head_inst);
}
// Check if the instruction caused a fault. If so, trap.
Fault inst_fault = head_inst->getFault();
if (inst_fault != NoFault) {
- if (!head_inst->isNop()) {
+ head_inst->setCompleted();
#if FULL_SYSTEM
- cpu->trap(inst_fault);
-#else // !FULL_SYSTEM
- panic("fault (%d) detected @ PC %08p", inst_fault,
- head_inst->PC);
-#endif // FULL_SYSTEM
+ DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
+ head_inst->seqNum, head_inst->readPC());
+
+ if (iewStage->hasStoresToWB() || inst_num > 0) {
+ DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
+ return false;
}
- }
- // Check if we're really ready to commit. If not then return false.
- // I'm pretty sure all instructions should be able to commit if they've
- // reached this far. For now leave this in as a check.
- if (!rob->isHeadReady()) {
- panic("Commit: Unable to commit head instruction!\n");
- return false;
- }
+ if (cpu->checker && head_inst->isStore()) {
+ cpu->checker->tick(head_inst);
+ }
- // If it's a branch, then send back branch prediction update info
- // to the fetch stage.
- // This should be handled in the iew stage if a mispredict happens...
+ assert(!thread[tid]->inSyscall);
- if (head_inst->isControl()) {
+ // Mark that we're in state update mode so that the trap's
+ // execution doesn't generate extra squashes.
+ thread[tid]->inSyscall = true;
-#if 0
- toIEW->nextPC = head_inst->readPC();
- //Maybe switch over to BTB incorrect.
- toIEW->btbMissed = head_inst->btbMiss();
- toIEW->target = head_inst->nextPC;
- //Maybe also include global history information.
- //This simple version will have no branch prediction however.
-#endif
+ // DTB will sometimes need the machine instruction for when
+ // faults happen. So we will set it here, prior to the DTB
+ // possibly needing it for its fault.
+ thread[tid]->setInst(
+ static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
+
+ // Execute the trap. Although it's slightly unrealistic in
+ // terms of timing (as it doesn't wait for the full timing of
+ // the trap event to complete before updating state), it's
+ // needed to update the state as soon as possible. This
+ // prevents external agents from changing any specific state
+ // that the trap need.
+ cpu->trap(inst_fault, tid);
+
+ // Exit state update mode to avoid accidental updating.
+ thread[tid]->inSyscall = false;
+
+ commitStatus[tid] = TrapPending;
- ++commitCommittedBranches;
+ // Generate trap squash event.
+ generateTrapEvent(tid);
+
+ return false;
+#else // !FULL_SYSTEM
+ panic("fault (%d) detected @ PC %08p", inst_fault,
+ head_inst->PC);
+#endif // FULL_SYSTEM
}
- // Now that the instruction is going to be committed, finalize its
- // trace data.
+ updateComInstStats(head_inst);
+
if (head_inst->traceData) {
+ head_inst->traceData->setFetchSeq(head_inst->seqNum);
+ head_inst->traceData->setCPSeq(thread[tid]->numInst);
head_inst->traceData->finalize();
+ head_inst->traceData = NULL;
+ }
+
+ // Update the commit rename map
+ for (int i = 0; i < head_inst->numDestRegs(); i++) {
+ renameMap[tid]->setEntry(head_inst->destRegIdx(i),
+ head_inst->renamedDestRegIdx(i));
}
- //Finally clear the head ROB entry.
- rob->retireHead();
+ // Finally clear the head ROB entry.
+ rob->retireHead(tid);
// Return true to indicate that we have committed an instruction.
return true;
@@ -447,37 +1091,39 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
template <class Impl>
void
-SimpleCommit<Impl>::getInsts()
+DefaultCommit<Impl>::getInsts()
{
- //////////////////////////////////////
- // Handle ROB functions
- //////////////////////////////////////
-
- // Read any issued instructions and place them into the ROB. Do this
- // prior to squashing to avoid having instructions in the ROB that
- // don't get squashed properly.
+ // Read any renamed instructions and place them into the ROB.
int insts_to_process = min((int)renameWidth, fromRename->size);
- for (int inst_num = 0;
- inst_num < insts_to_process;
- ++inst_num)
+ for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
{
- if (!fromRename->insts[inst_num]->isSquashed()) {
- DPRINTF(Commit, "Commit: Inserting PC %#x into ROB.\n",
- fromRename->insts[inst_num]->readPC());
- rob->insertInst(fromRename->insts[inst_num]);
+ DynInstPtr inst = fromRename->insts[inst_num];
+ int tid = inst->threadNumber;
+
+ if (!inst->isSquashed() &&
+ commitStatus[tid] != ROBSquashing) {
+ changedROBNumEntries[tid] = true;
+
+ DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
+ inst->readPC(), inst->seqNum, tid);
+
+ rob->insertInst(inst);
+
+ assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
+
+ youngestSeqNum[tid] = inst->seqNum;
} else {
- DPRINTF(Commit, "Commit: Instruction %i PC %#x was "
+ DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
"squashed, skipping.\n",
- fromRename->insts[inst_num]->seqNum,
- fromRename->insts[inst_num]->readPC());
+ inst->readPC(), inst->seqNum, tid);
}
}
}
template <class Impl>
void
-SimpleCommit<Impl>::markCompletedInsts()
+DefaultCommit<Impl>::markCompletedInsts()
{
// Grab completed insts out of the IEW instruction queue, and mark
// instructions completed within the ROB.
@@ -485,18 +1131,177 @@ SimpleCommit<Impl>::markCompletedInsts()
inst_num < fromIEW->size && fromIEW->insts[inst_num];
++inst_num)
{
- DPRINTF(Commit, "Commit: Marking PC %#x, SN %i ready within ROB.\n",
- fromIEW->insts[inst_num]->readPC(),
- fromIEW->insts[inst_num]->seqNum);
+ if (!fromIEW->insts[inst_num]->isSquashed()) {
+ DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
+ "within ROB.\n",
+ fromIEW->insts[inst_num]->threadNumber,
+ fromIEW->insts[inst_num]->readPC(),
+ fromIEW->insts[inst_num]->seqNum);
+
+ // Mark the instruction as ready to commit.
+ fromIEW->insts[inst_num]->setCanCommit();
+ }
+ }
+}
+
+template <class Impl>
+bool
+DefaultCommit<Impl>::robDoneSquashing()
+{
+ list<unsigned>::iterator threads = (*activeThreads).begin();
- // Mark the instruction as ready to commit.
- fromIEW->insts[inst_num]->setCanCommit();
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ if (!rob->isDoneSquashing(tid))
+ return false;
}
+
+ return true;
}
template <class Impl>
-uint64_t
-SimpleCommit<Impl>::readCommitPC()
+void
+DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
{
- return rob->readHeadPC();
+ unsigned thread = inst->threadNumber;
+
+ //
+ // Pick off the software prefetches
+ //
+#ifdef TARGET_ALPHA
+ if (inst->isDataPrefetch()) {
+ statComSwp[thread]++;
+ } else {
+ statComInst[thread]++;
+ }
+#else
+ statComInst[thread]++;
+#endif
+
+ //
+ // Control Instructions
+ //
+ if (inst->isControl())
+ statComBranches[thread]++;
+
+ //
+ // Memory references
+ //
+ if (inst->isMemRef()) {
+ statComRefs[thread]++;
+
+ if (inst->isLoad()) {
+ statComLoads[thread]++;
+ }
+ }
+
+ if (inst->isMemBarrier()) {
+ statComMembars[thread]++;
+ }
+}
+
+////////////////////////////////////////
+// //
+// SMT COMMIT POLICY MAINTAINED HERE //
+// //
+////////////////////////////////////////
+template <class Impl>
+int
+DefaultCommit<Impl>::getCommittingThread()
+{
+ if (numThreads > 1) {
+ switch (commitPolicy) {
+
+ case Aggressive:
+ //If Policy is Aggressive, commit will call
+ //this function multiple times per
+ //cycle
+ return oldestReady();
+
+ case RoundRobin:
+ return roundRobin();
+
+ case OldestReady:
+ return oldestReady();
+
+ default:
+ return -1;
+ }
+ } else {
+ int tid = (*activeThreads).front();
+
+ if (commitStatus[tid] == Running ||
+ commitStatus[tid] == Idle ||
+ commitStatus[tid] == FetchTrapPending) {
+ return tid;
+ } else {
+ return -1;
+ }
+ }
+}
+
+template<class Impl>
+int
+DefaultCommit<Impl>::roundRobin()
+{
+ list<unsigned>::iterator pri_iter = priority_list.begin();
+ list<unsigned>::iterator end = priority_list.end();
+
+ while (pri_iter != end) {
+ unsigned tid = *pri_iter;
+
+ if (commitStatus[tid] == Running ||
+ commitStatus[tid] == Idle) {
+
+ if (rob->isHeadReady(tid)) {
+ priority_list.erase(pri_iter);
+ priority_list.push_back(tid);
+
+ return tid;
+ }
+ }
+
+ pri_iter++;
+ }
+
+ return -1;
+}
+
+template<class Impl>
+int
+DefaultCommit<Impl>::oldestReady()
+{
+ unsigned oldest = 0;
+ bool first = true;
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ if (!rob->isEmpty(tid) &&
+ (commitStatus[tid] == Running ||
+ commitStatus[tid] == Idle ||
+ commitStatus[tid] == FetchTrapPending)) {
+
+ if (rob->isHeadReady(tid)) {
+
+ DynInstPtr head_inst = rob->readHeadInst(tid);
+
+ if (first) {
+ oldest = tid;
+ first = false;
+ } else if (head_inst->seqNum < oldest) {
+ oldest = tid;
+ }
+ }
+ }
+ }
+
+ if (!first) {
+ return oldest;
+ } else {
+ return -1;
+ }
}
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index a268dbc23..ed02a845b 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -33,19 +33,29 @@
#else
#include "sim/process.hh"
#endif
-#include "sim/root.hh"
+#include "cpu/activity.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/cpu_exec_context.hh"
#include "cpu/exec_context.hh"
#include "cpu/o3/alpha_dyn_inst.hh"
#include "cpu/o3/alpha_impl.hh"
#include "cpu/o3/cpu.hh"
+#include "sim/root.hh"
+#include "sim/stat_control.hh"
+
using namespace std;
-BaseFullCPU::BaseFullCPU(Params &params)
- : BaseCPU(&params), cpu_id(0)
+BaseFullCPU::BaseFullCPU(Params *params)
+ : BaseCPU(params), cpu_id(0)
+{
+}
+
+void
+BaseFullCPU::regStats()
{
+ BaseCPU::regStats();
}
template <class Impl>
@@ -68,97 +78,88 @@ FullO3CPU<Impl>::TickEvent::description()
return "FullO3CPU tick event";
}
-//Call constructor to all the pipeline stages here
template <class Impl>
-FullO3CPU<Impl>::FullO3CPU(Params &params)
-#if FULL_SYSTEM
- : BaseFullCPU(params),
-#else
+FullO3CPU<Impl>::FullO3CPU(Params *params)
: BaseFullCPU(params),
-#endif // FULL_SYSTEM
tickEvent(this),
+ removeInstsThisCycle(false),
fetch(params),
decode(params),
rename(params),
iew(params),
commit(params),
- regFile(params.numPhysIntRegs, params.numPhysFloatRegs),
+ regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
- freeList(TheISA::NumIntRegs, params.numPhysIntRegs,
- TheISA::NumFloatRegs, params.numPhysFloatRegs),
+ freeList(params->numberOfThreads,//number of activeThreads
+ TheISA::NumIntRegs, params->numPhysIntRegs,
+ TheISA::NumFloatRegs, params->numPhysFloatRegs),
- renameMap(TheISA::NumIntRegs, params.numPhysIntRegs,
- TheISA::NumFloatRegs, params.numPhysFloatRegs,
- TheISA::NumMiscRegs,
- TheISA::ZeroReg,
- TheISA::ZeroReg + TheISA::NumIntRegs),
+ rob(params->numROBEntries, params->squashWidth,
+ params->smtROBPolicy, params->smtROBThreshold,
+ params->numberOfThreads),
- rob(params.numROBEntries, params.squashWidth),
+ scoreboard(params->numberOfThreads,//number of activeThreads
+ TheISA::NumIntRegs, params->numPhysIntRegs,
+ TheISA::NumFloatRegs, params->numPhysFloatRegs,
+ TheISA::NumMiscRegs * number_of_threads,
+ TheISA::ZeroReg),
- // What to pass to these time buffers?
// For now just have these time buffers be pretty big.
+ // @todo: Make these time buffer sizes parameters or derived
+ // from latencies
timeBuffer(5, 5),
fetchQueue(5, 5),
decodeQueue(5, 5),
renameQueue(5, 5),
iewQueue(5, 5),
-
- cpuXC(NULL),
+ activityRec(NumStages, 10, params->activity),
globalSeqNum(1),
#if FULL_SYSTEM
- system(params.system),
+ system(params->system),
memCtrl(system->memctrl),
physmem(system->physmem),
- itb(params.itb),
- dtb(params.dtb),
- mem(params.mem),
+ mem(params->mem),
#else
- // Hardcoded for a single thread!!
- mem(params.workload[0]->getMemory()),
+// pTable(params->pTable),
+ mem(params->workload[0]->getMemory()),
#endif // FULL_SYSTEM
-
- icacheInterface(params.icacheInterface),
- dcacheInterface(params.dcacheInterface),
- deferRegistration(params.defReg),
- numInsts(0),
- funcExeInst(0)
+ switchCount(0),
+ icacheInterface(params->icacheInterface),
+ dcacheInterface(params->dcacheInterface),
+ deferRegistration(params->deferRegistration),
+ numThreads(number_of_threads)
{
_status = Idle;
-#if !FULL_SYSTEM
- thread.resize(this->number_of_threads);
-#endif
-
- for (int i = 0; i < this->number_of_threads; ++i) {
+ if (params->checker) {
+ BaseCPU *temp_checker = params->checker;
+ checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
+ checker->setMemory(mem);
#if FULL_SYSTEM
- assert(i == 0);
- thread[i] = new CPUExecContext(this, 0, system, itb, dtb, mem);
- system->execContexts[i] = thread[i]->getProxy();
-
- execContexts.push_back(system->execContexts[i]);
-#else
- if (i < params.workload.size()) {
- DPRINTF(FullCPU, "FullCPU: Workload[%i]'s starting PC is %#x, "
- "process is %#x",
- i, params.workload[i]->prog_entry, thread[i]);
- thread[i] = new CPUExecContext(this, i, params.workload[i], i);
- }
- assert(params.workload[i]->getMemory() != NULL);
- assert(mem != NULL);
- execContexts.push_back(thread[i]->getProxy());
-#endif // !FULL_SYSTEM
+ checker->setSystem(params->system);
+#endif
+ } else {
+ checker = NULL;
}
- // Note that this is a hack so that my code which still uses xc-> will
- // still work. I should remove this eventually
- cpuXC = thread[0];
+#if !FULL_SYSTEM
+ thread.resize(number_of_threads);
+ tids.resize(number_of_threads);
+#endif
- // The stages also need their CPU pointer setup. However this must be
- // done at the upper level CPU because they have pointers to the upper
- // level CPU, and not this FullO3CPU.
+ // The stages also need their CPU pointer setup. However this
+ // must be done at the upper level CPU because they have pointers
+ // to the upper level CPU, and not this FullO3CPU.
+
+ // Set up Pointers to the activeThreads list for each stage
+ fetch.setActiveThreads(&activeThreads);
+ decode.setActiveThreads(&activeThreads);
+ rename.setActiveThreads(&activeThreads);
+ iew.setActiveThreads(&activeThreads);
+ commit.setActiveThreads(&activeThreads);
// Give each of the stages the time buffer they will use.
fetch.setTimeBuffer(&timeBuffer);
@@ -170,6 +171,7 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
// Also setup each of the stages' queues.
fetch.setFetchQueue(&fetchQueue);
decode.setFetchQueue(&fetchQueue);
+ commit.setFetchQueue(&fetchQueue);
decode.setDecodeQueue(&decodeQueue);
rename.setDecodeQueue(&decodeQueue);
rename.setRenameQueue(&renameQueue);
@@ -178,16 +180,85 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
commit.setIEWQueue(&iewQueue);
commit.setRenameQueue(&renameQueue);
+ commit.setFetchStage(&fetch);
+ commit.setIEWStage(&iew);
+ rename.setIEWStage(&iew);
+ rename.setCommitStage(&commit);
+
+#if !FULL_SYSTEM
+ int active_threads = params->workload.size();
+#else
+ int active_threads = 1;
+#endif
+
+ //Make Sure That this a Valid Architeture
+ assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
+ assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
+
+ rename.setScoreboard(&scoreboard);
+ iew.setScoreboard(&scoreboard);
+
// Setup the rename map for whichever stages need it.
- rename.setRenameMap(&renameMap);
- iew.setRenameMap(&renameMap);
+ PhysRegIndex lreg_idx = 0;
+ PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
+
+ for (int tid=0; tid < numThreads; tid++) {
+ bool bindRegs = (tid <= active_threads - 1);
+
+ commitRenameMap[tid].init(TheISA::NumIntRegs,
+ params->numPhysIntRegs,
+ lreg_idx, //Index for Logical. Regs
+
+ TheISA::NumFloatRegs,
+ params->numPhysFloatRegs,
+ freg_idx, //Index for Float Regs
+
+ TheISA::NumMiscRegs,
+
+ TheISA::ZeroReg,
+ TheISA::ZeroReg,
+
+ tid,
+ false);
+
+ renameMap[tid].init(TheISA::NumIntRegs,
+ params->numPhysIntRegs,
+ lreg_idx, //Index for Logical. Regs
+
+ TheISA::NumFloatRegs,
+ params->numPhysFloatRegs,
+ freg_idx, //Index for Float Regs
- // Setup the free list for whichever stages need it.
+ TheISA::NumMiscRegs,
+
+ TheISA::ZeroReg,
+ TheISA::ZeroReg,
+
+ tid,
+ bindRegs);
+ }
+
+ rename.setRenameMap(renameMap);
+ commit.setRenameMap(commitRenameMap);
+
+ // Give renameMap & rename stage access to the freeList;
+ for (int i=0; i < numThreads; i++) {
+ renameMap[i].setFreeList(&freeList);
+ }
rename.setFreeList(&freeList);
- renameMap.setFreeList(&freeList);
+
+ // Setup the page table for whichever stages need it.
+#if !FULL_SYSTEM
+// fetch.setPageTable(pTable);
+// iew.setPageTable(pTable);
+#endif
// Setup the ROB for whichever stages need it.
commit.setROB(&rob);
+
+ lastRunningCycle = curTick;
+
+ contextSwitch = false;
}
template <class Impl>
@@ -199,7 +270,58 @@ template <class Impl>
void
FullO3CPU<Impl>::fullCPURegStats()
{
+ BaseFullCPU::regStats();
+
// Register any of the FullCPU's stats here.
+ timesIdled
+ .name(name() + ".timesIdled")
+ .desc("Number of times that the entire CPU went into an idle state and"
+ " unscheduled itself")
+ .prereq(timesIdled);
+
+ idleCycles
+ .name(name() + ".idleCycles")
+ .desc("Total number of cycles that the CPU has spent unscheduled due "
+ "to idling")
+ .prereq(idleCycles);
+
+ // Number of Instructions simulated
+ // --------------------------------
+ // Should probably be in Base CPU but need templated
+ // MaxThreads so put in here instead
+ committedInsts
+ .init(numThreads)
+ .name(name() + ".committedInsts")
+ .desc("Number of Instructions Simulated");
+
+ totalCommittedInsts
+ .name(name() + ".committedInsts_total")
+ .desc("Number of Instructions Simulated");
+
+ cpi
+ .name(name() + ".cpi")
+ .desc("CPI: Cycles Per Instruction")
+ .precision(6);
+ cpi = simTicks / committedInsts;
+
+ totalCpi
+ .name(name() + ".cpi_total")
+ .desc("CPI: Total CPI of All Threads")
+ .precision(6);
+ totalCpi = simTicks / totalCommittedInsts;
+
+ ipc
+ .name(name() + ".ipc")
+ .desc("IPC: Instructions Per Cycle")
+ .precision(6);
+ ipc = committedInsts / simTicks;
+
+ totalIpc
+ .name(name() + ".ipc_total")
+ .desc("IPC: Total IPC of All Threads")
+ .precision(6);
+ totalIpc = totalCommittedInsts / simTicks;
+
}
template <class Impl>
@@ -208,9 +330,11 @@ FullO3CPU<Impl>::tick()
{
DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n");
- //Tick each of the stages if they're actually running.
- //Will want to figure out a way to unschedule itself if they're all
- //going to be idle for a long time.
+ ++numCycles;
+
+// activity = false;
+
+ //Tick each of the stages
fetch.tick();
decode.tick();
@@ -221,7 +345,11 @@ FullO3CPU<Impl>::tick()
commit.tick();
- // Now advance the time buffers, unless the stage is stalled.
+#if !FULL_SYSTEM
+ doContextSwitch();
+#endif
+
+ // Now advance the time buffers
timeBuffer.advance();
fetchQueue.advance();
@@ -229,99 +357,396 @@ FullO3CPU<Impl>::tick()
renameQueue.advance();
iewQueue.advance();
- if (_status == Running && !tickEvent.scheduled())
- tickEvent.schedule(curTick + 1);
+ activityRec.advance();
+
+ if (removeInstsThisCycle) {
+ cleanUpRemovedInsts();
+ }
+
+ if (!tickEvent.scheduled()) {
+ if (_status == SwitchedOut) {
+ // increment stat
+ lastRunningCycle = curTick;
+ } else if (!activityRec.active()) {
+ lastRunningCycle = curTick;
+ timesIdled++;
+ } else {
+ tickEvent.schedule(curTick + cycles(1));
+ }
+ }
+
+#if !FULL_SYSTEM
+ updateThreadPriority();
+#endif
+
}
template <class Impl>
void
FullO3CPU<Impl>::init()
{
- if(!deferRegistration)
- {
- this->registerExecContexts();
+ if (!deferRegistration) {
+ registerExecContexts();
+ }
- // Need to do a copy of the xc->regs into the CPU's regfile so
- // that it can start properly.
+ // Set inSyscall so that the CPU doesn't squash when initially
+ // setting up registers.
+ for (int i = 0; i < number_of_threads; ++i)
+ thread[i]->inSyscall = true;
+
+ for (int tid=0; tid < number_of_threads; tid++) {
#if FULL_SYSTEM
- ExecContext *src_xc = system->execContexts[0];
- TheISA::initCPU(src_xc, src_xc->readCpuId());
+ ExecContext *src_xc = execContexts[tid];
#else
- ExecContext *src_xc = thread[0]->getProxy();
+ ExecContext *src_xc = thread[tid]->getXCProxy();
#endif
- // First loop through the integer registers.
- for (int i = 0; i < TheISA::NumIntRegs; ++i)
- {
- regFile.intRegFile[i] = src_xc->readIntReg(i);
+ // Threads start in the Suspended State
+ if (src_xc->status() != ExecContext::Suspended) {
+ continue;
}
- // Then loop through the floating point registers.
- for (int i = 0; i < TheISA::NumFloatRegs; ++i)
- {
- regFile.floatRegFile.setRegBits(i, src_xc->readRegBits(i))
- }
-/*
- // Then loop through the misc registers.
- regFile.miscRegs.fpcr = src_xc->regs.miscRegs.fpcr;
- regFile.miscRegs.uniq = src_xc->regs.miscRegs.uniq;
- regFile.miscRegs.lock_flag = src_xc->regs.miscRegs.lock_flag;
- regFile.miscRegs.lock_addr = src_xc->regs.miscRegs.lock_addr;
-*/
- // Then finally set the PC and the next PC.
- regFile.pc = src_xc->readPC();
- regFile.npc = src_xc->readNextPC();
+#if FULL_SYSTEM
+ TheISA::initCPU(src_xc, src_xc->readCpuId());
+#endif
+ }
+
+ // Clear inSyscall.
+ for (int i = 0; i < number_of_threads; ++i)
+ thread[i]->inSyscall = false;
+
+ // Initialize stages.
+ fetch.initStage();
+ iew.initStage();
+ rename.initStage();
+ commit.initStage();
+
+ commit.setThreads(thread);
+}
+
+template <class Impl>
+void
+FullO3CPU<Impl>::insertThread(unsigned tid)
+{
+ DPRINTF(FullCPU,"[tid:%i] Initializing thread data");
+ // Will change now that the PC and thread state is internal to the CPU
+ // and not in the CPUExecContext.
+#if 0
+#if FULL_SYSTEM
+ ExecContext *src_xc = system->execContexts[tid];
+#else
+ CPUExecContext *src_xc = thread[tid];
+#endif
+
+ //Bind Int Regs to Rename Map
+ for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
+ PhysRegIndex phys_reg = freeList.getIntReg();
+
+ renameMap[tid].setEntry(ireg,phys_reg);
+ scoreboard.setReg(phys_reg);
+ }
+
+ //Bind Float Regs to Rename Map
+ for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
+ PhysRegIndex phys_reg = freeList.getFloatReg();
+
+ renameMap[tid].setEntry(freg,phys_reg);
+ scoreboard.setReg(phys_reg);
+ }
+
+ //Copy Thread Data Into RegFile
+ this->copyFromXC(tid);
+
+ //Set PC/NPC
+ regFile.pc[tid] = src_xc->readPC();
+ regFile.npc[tid] = src_xc->readNextPC();
+
+ src_xc->setStatus(ExecContext::Active);
+
+ activateContext(tid,1);
+
+ //Reset ROB/IQ/LSQ Entries
+ commit.rob->resetEntries();
+ iew.resetEntries();
+#endif
+}
+
+template <class Impl>
+void
+FullO3CPU<Impl>::removeThread(unsigned tid)
+{
+ DPRINTF(FullCPU,"[tid:%i] Removing thread data");
+#if 0
+ //Unbind Int Regs from Rename Map
+ for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
+ PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
+
+ scoreboard.unsetReg(phys_reg);
+ freeList.addReg(phys_reg);
+ }
+
+ //Unbind Float Regs from Rename Map
+ for (int freg = 0; freg < TheISA::NumFloatRegs; freg++) {
+ PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
+
+ scoreboard.unsetReg(phys_reg);
+ freeList.addReg(phys_reg);
+ }
+
+ //Copy Thread Data From RegFile
+ /* Fix Me:
+ * Do we really need to do this if we are removing a thread
+ * in the sense that it's finished (exiting)? If the thread is just
+ * being suspended we might...
+ */
+// this->copyToXC(tid);
+
+ //Squash Throughout Pipeline
+ fetch.squash(0,tid);
+ decode.squash(tid);
+ rename.squash(tid);
+
+ assert(iew.ldstQueue.getCount(tid) == 0);
+
+ //Reset ROB/IQ/LSQ Entries
+ if (activeThreads.size() >= 1) {
+ commit.rob->resetEntries();
+ iew.resetEntries();
+ }
+#endif
+}
+
+
+template <class Impl>
+void
+FullO3CPU<Impl>::activateWhenReady(int tid)
+{
+ DPRINTF(FullCPU,"[tid:%i]: Checking if resources are available for incoming"
+ "(e.g. PhysRegs/ROB/IQ/LSQ) \n",
+ tid);
+
+ bool ready = true;
+
+ if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) {
+ DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
+ "Phys. Int. Regs.\n",
+ tid);
+ ready = false;
+ } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) {
+ DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
+ "Phys. Float. Regs.\n",
+ tid);
+ ready = false;
+ } else if (commit.rob->numFreeEntries() >=
+ commit.rob->entryAmount(activeThreads.size() + 1)) {
+ DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
+ "ROB entries.\n",
+ tid);
+ ready = false;
+ } else if (iew.instQueue.numFreeEntries() >=
+ iew.instQueue.entryAmount(activeThreads.size() + 1)) {
+ DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
+ "IQ entries.\n",
+ tid);
+ ready = false;
+ } else if (iew.ldstQueue.numFreeEntries() >=
+ iew.ldstQueue.entryAmount(activeThreads.size() + 1)) {
+ DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough "
+ "LSQ entries.\n",
+ tid);
+ ready = false;
+ }
+
+ if (ready) {
+ insertThread(tid);
+
+ contextSwitch = false;
+
+ cpuWaitList.remove(tid);
+ } else {
+ suspendContext(tid);
+
+ //blocks fetch
+ contextSwitch = true;
+
+ //do waitlist
+ cpuWaitList.push_back(tid);
}
}
template <class Impl>
void
-FullO3CPU<Impl>::activateContext(int thread_num, int delay)
+FullO3CPU<Impl>::activateContext(int tid, int delay)
{
// Needs to set each stage to running as well.
+ list<unsigned>::iterator isActive = find(
+ activeThreads.begin(), activeThreads.end(), tid);
+
+ if (isActive == activeThreads.end()) {
+ //May Need to Re-code this if the delay variable is the
+ //delay needed for thread to activate
+ DPRINTF(FullCPU, "Adding Thread %i to active threads list\n",
+ tid);
+
+ activeThreads.push_back(tid);
+ }
+
+ assert(_status == Idle || _status == SwitchedOut);
scheduleTickEvent(delay);
+ // Be sure to signal that there's some activity so the CPU doesn't
+ // deschedule itself.
+ activityRec.activity();
+ fetch.wakeFromQuiesce();
+
_status = Running;
}
template <class Impl>
void
-FullO3CPU<Impl>::suspendContext(int thread_num)
+FullO3CPU<Impl>::suspendContext(int tid)
+{
+ DPRINTF(FullCPU,"[tid: %i]: Suspended ...\n", tid);
+ unscheduleTickEvent();
+ _status = Idle;
+/*
+ //Remove From Active List, if Active
+ list<unsigned>::iterator isActive = find(
+ activeThreads.begin(), activeThreads.end(), tid);
+
+ if (isActive != activeThreads.end()) {
+ DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n",
+ tid);
+ activeThreads.erase(isActive);
+ }
+*/
+}
+
+template <class Impl>
+void
+FullO3CPU<Impl>::deallocateContext(int tid)
{
- panic("suspendContext unimplemented!");
+ DPRINTF(FullCPU,"[tid:%i]: Deallocating ...", tid);
+/*
+ //Remove From Active List, if Active
+ list<unsigned>::iterator isActive = find(
+ activeThreads.begin(), activeThreads.end(), tid);
+
+ if (isActive != activeThreads.end()) {
+ DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n",
+ tid);
+ activeThreads.erase(isActive);
+
+ removeThread(tid);
+ }
+*/
}
template <class Impl>
void
-FullO3CPU<Impl>::deallocateContext(int thread_num)
+FullO3CPU<Impl>::haltContext(int tid)
{
- panic("deallocateContext unimplemented!");
+ DPRINTF(FullCPU,"[tid:%i]: Halted ...", tid);
+/*
+ //Remove From Active List, if Active
+ list<unsigned>::iterator isActive = find(
+ activeThreads.begin(), activeThreads.end(), tid);
+
+ if (isActive != activeThreads.end()) {
+ DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n",
+ tid);
+ activeThreads.erase(isActive);
+
+ removeThread(tid);
+ }
+*/
}
template <class Impl>
void
-FullO3CPU<Impl>::haltContext(int thread_num)
+FullO3CPU<Impl>::switchOut(Sampler *_sampler)
{
- panic("haltContext unimplemented!");
+ sampler = _sampler;
+ switchCount = 0;
+ fetch.switchOut();
+ decode.switchOut();
+ rename.switchOut();
+ iew.switchOut();
+ commit.switchOut();
+
+ // Wake the CPU and record activity so everything can drain out if
+ // the CPU is currently idle.
+ wakeCPU();
+ activityRec.activity();
}
template <class Impl>
void
-FullO3CPU<Impl>::switchOut()
+FullO3CPU<Impl>::signalSwitched()
{
- panic("FullO3CPU does not have a switch out function.\n");
+ if (++switchCount == NumStages) {
+ fetch.doSwitchOut();
+ rename.doSwitchOut();
+ commit.doSwitchOut();
+ instList.clear();
+ while (!removeList.empty()) {
+ removeList.pop();
+ }
+
+ if (checker)
+ checker->switchOut(sampler);
+
+ if (tickEvent.scheduled())
+ tickEvent.squash();
+ sampler->signalSwitched();
+ _status = SwitchedOut;
+ }
+ assert(switchCount <= 5);
}
template <class Impl>
void
FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
{
+ // Flush out any old data from the time buffers.
+ for (int i = 0; i < 10; ++i) {
+ timeBuffer.advance();
+ fetchQueue.advance();
+ decodeQueue.advance();
+ renameQueue.advance();
+ iewQueue.advance();
+ }
+
+ activityRec.reset();
+
BaseCPU::takeOverFrom(oldCPU);
+ fetch.takeOverFrom();
+ decode.takeOverFrom();
+ rename.takeOverFrom();
+ iew.takeOverFrom();
+ commit.takeOverFrom();
+
assert(!tickEvent.scheduled());
- // Set all status's to active, schedule the
- // CPU's tick event.
+ // @todo: Figure out how to properly select the tid to put onto
+ // the active threads list.
+ int tid = 0;
+
+ list<unsigned>::iterator isActive = find(
+ activeThreads.begin(), activeThreads.end(), tid);
+
+ if (isActive == activeThreads.end()) {
+ //May Need to Re-code this if the delay variable is the delay
+ //needed for thread to activate
+ DPRINTF(FullCPU, "Adding Thread %i to active threads list\n",
+ tid);
+
+ activeThreads.push_back(tid);
+ }
+
+ // Set all statuses to active, schedule the CPU's tick event.
+ // @todo: Fix up statuses so this is handled properly
for (int i = 0; i < execContexts.size(); ++i) {
ExecContext *xc = execContexts[i];
if (xc->status() == ExecContext::Active && _status != Running) {
@@ -329,14 +754,8 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
tickEvent.schedule(curTick);
}
}
-}
-
-template <class Impl>
-InstSeqNum
-FullO3CPU<Impl>::getAndIncrementInstSeq()
-{
- // Hopefully this works right.
- return globalSeqNum++;
+ if (!tickEvent.scheduled())
+ tickEvent.schedule(curTick);
}
template <class Impl>
@@ -363,7 +782,6 @@ FullO3CPU<Impl>::readFloatReg(int reg_idx)
template <class Impl>
FloatRegBits
FullO3CPU<Impl>::readFloatRegBits(int reg_idx, int width)
-{
return regFile.readFloatRegBits(reg_idx, width);
}
@@ -411,156 +829,368 @@ FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
template <class Impl>
uint64_t
-FullO3CPU<Impl>::readPC()
+FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
+{
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
+
+ return regFile.readIntReg(phys_reg);
+}
+
+template <class Impl>
+float
+FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
+{
+ int idx = reg_idx + TheISA::FP_Base_DepTag;
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
+
+ return regFile.readFloatRegSingle(phys_reg);
+}
+
+template <class Impl>
+double
+FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
+{
+ int idx = reg_idx + TheISA::FP_Base_DepTag;
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
+
+ return regFile.readFloatRegDouble(phys_reg);
+}
+
+template <class Impl>
+uint64_t
+FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
{
- return regFile.readPC();
+ int idx = reg_idx + TheISA::FP_Base_DepTag;
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
+
+ return regFile.readFloatRegInt(phys_reg);
}
template <class Impl>
void
-FullO3CPU<Impl>::setNextPC(uint64_t val)
+FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
{
- regFile.setNextPC(val);
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
+
+ regFile.setIntReg(phys_reg, val);
}
template <class Impl>
void
-FullO3CPU<Impl>::setPC(Addr new_PC)
+FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
{
- regFile.setPC(new_PC);
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
+
+ regFile.setFloatRegSingle(phys_reg, val);
}
template <class Impl>
void
-FullO3CPU<Impl>::addInst(DynInstPtr &inst)
+FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
{
- instList.push_back(inst);
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
+
+ regFile.setFloatRegDouble(phys_reg, val);
}
template <class Impl>
void
-FullO3CPU<Impl>::instDone()
+FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
{
- // Keep an instruction count.
- numInsts++;
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
- // Check for instruction-count-based events.
- comInstEventQueue[0]->serviceEvents(numInsts);
+ regFile.setFloatRegInt(phys_reg, val);
+}
+
+template <class Impl>
+uint64_t
+FullO3CPU<Impl>::readPC(unsigned tid)
+{
+ return commit.readPC(tid);
}
template <class Impl>
void
-FullO3CPU<Impl>::removeBackInst(DynInstPtr &inst)
+FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
{
- DynInstPtr inst_to_delete;
+ commit.setPC(new_PC, tid);
+}
- // Walk through the instruction list, removing any instructions
- // that were inserted after the given instruction, inst.
- while (instList.back() != inst)
- {
- assert(!instList.empty());
+template <class Impl>
+uint64_t
+FullO3CPU<Impl>::readNextPC(unsigned tid)
+{
+ return commit.readNextPC(tid);
+}
+
+template <class Impl>
+void
+FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
+{
+ commit.setNextPC(val, tid);
+}
+
+template <class Impl>
+typename FullO3CPU<Impl>::ListIt
+FullO3CPU<Impl>::addInst(DynInstPtr &inst)
+{
+ instList.push_back(inst);
- // Obtain the pointer to the instruction.
- inst_to_delete = instList.back();
+ return --(instList.end());
+}
- DPRINTF(FullCPU, "FullCPU: Removing instruction %i, PC %#x\n",
- inst_to_delete->seqNum, inst_to_delete->readPC());
+template <class Impl>
+void
+FullO3CPU<Impl>::instDone(unsigned tid)
+{
+ // Keep an instruction count.
+ thread[tid]->numInst++;
+ thread[tid]->numInsts++;
+ committedInsts[tid]++;
+ totalCommittedInsts++;
- // Remove the instruction from the list.
- instList.pop_back();
+ // Check for instruction-count-based events.
+ comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
+}
- // Mark it as squashed.
- inst_to_delete->setSquashed();
- }
+template <class Impl>
+void
+FullO3CPU<Impl>::addToRemoveList(DynInstPtr &inst)
+{
+ removeInstsThisCycle = true;
+
+ removeList.push(inst->getInstListIt());
}
template <class Impl>
void
FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
{
- DynInstPtr inst_to_remove;
+ DPRINTF(FullCPU, "FullCPU: Removing committed instruction [tid:%i] PC %#x "
+ "[sn:%lli]\n",
+ inst->threadNumber, inst->readPC(), inst->seqNum);
- // The front instruction should be the same one being asked to be removed.
- assert(instList.front() == inst);
+ removeInstsThisCycle = true;
// Remove the front instruction.
- inst_to_remove = inst;
- instList.pop_front();
-
- DPRINTF(FullCPU, "FullCPU: Removing committed instruction %#x, PC %#x\n",
- inst_to_remove, inst_to_remove->readPC());
+ removeList.push(inst->getInstListIt());
}
template <class Impl>
void
-FullO3CPU<Impl>::removeInstsNotInROB()
+FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
{
- DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction "
- "list.\n");
+ DPRINTF(FullCPU, "FullCPU: Thread %i: Deleting instructions from instruction"
+ " list.\n", tid);
+
+ ListIt end_it;
+
+ bool rob_empty = false;
+
+ if (instList.empty()) {
+ return;
+ } else if (rob.isEmpty(/*tid*/)) {
+ DPRINTF(FullCPU, "FullCPU: ROB is empty, squashing all insts.\n");
+ end_it = instList.begin();
+ rob_empty = true;
+ } else {
+ end_it = (rob.readTailInst(tid))->getInstListIt();
+ DPRINTF(FullCPU, "FullCPU: ROB is not empty, squashing insts not in ROB.\n");
+ }
+
+ removeInstsThisCycle = true;
+
+ ListIt inst_it = instList.end();
+
+ inst_it--;
+
+ // Walk through the instruction list, removing any instructions
+ // that were inserted after the given instruction iterator, end_it.
+ while (inst_it != end_it) {
+ assert(!instList.empty());
- DynInstPtr rob_tail = rob.readTailInst();
+ squashInstIt(inst_it, tid);
- removeBackInst(rob_tail);
+ inst_it--;
+ }
+
+ // If the ROB was empty, then we actually need to remove the first
+ // instruction as well.
+ if (rob_empty) {
+ squashInstIt(inst_it, tid);
+ }
}
template <class Impl>
void
-FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num)
+FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
+ unsigned tid)
{
+ assert(!instList.empty());
+
+ removeInstsThisCycle = true;
+
+ ListIt inst_iter = instList.end();
+
+ inst_iter--;
+
DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction "
- "list.\n");
+ "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
+ tid, seq_num, (*inst_iter)->seqNum);
- DynInstPtr inst_to_delete;
+ while ((*inst_iter)->seqNum > seq_num) {
- while (instList.back()->seqNum > seq_num) {
- assert(!instList.empty());
+ bool break_loop = (inst_iter == instList.begin());
- // Obtain the pointer to the instruction.
- inst_to_delete = instList.back();
+ squashInstIt(inst_iter, tid);
- DPRINTF(FullCPU, "FullCPU: Removing instruction %i, PC %#x\n",
- inst_to_delete->seqNum, inst_to_delete->readPC());
+ inst_iter--;
- // Remove the instruction from the list.
- instList.back() = NULL;
- instList.pop_back();
+ if (break_loop)
+ break;
+ }
+}
+
+template <class Impl>
+inline void
+FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
+{
+ if ((*instIt)->threadNumber == tid) {
+ DPRINTF(FullCPU, "FullCPU: Squashing instruction, "
+ "[tid:%i] [sn:%lli] PC %#x\n",
+ (*instIt)->threadNumber,
+ (*instIt)->seqNum,
+ (*instIt)->readPC());
// Mark it as squashed.
- inst_to_delete->setSquashed();
- }
+ (*instIt)->setSquashed();
+ // @todo: Formulate a consistent method for deleting
+ // instructions from the instruction list
+ // Remove the instruction from the list.
+ removeList.push(instIt);
+ }
}
template <class Impl>
void
+FullO3CPU<Impl>::cleanUpRemovedInsts()
+{
+ while (!removeList.empty()) {
+ DPRINTF(FullCPU, "FullCPU: Removing instruction, "
+ "[tid:%i] [sn:%lli] PC %#x\n",
+ (*removeList.front())->threadNumber,
+ (*removeList.front())->seqNum,
+ (*removeList.front())->readPC());
+
+ instList.erase(removeList.front());
+
+ removeList.pop();
+ }
+
+ removeInstsThisCycle = false;
+}
+/*
+template <class Impl>
+void
FullO3CPU<Impl>::removeAllInsts()
{
instList.clear();
}
-
+*/
template <class Impl>
void
FullO3CPU<Impl>::dumpInsts()
{
int num = 0;
- typename list<DynInstPtr>::iterator inst_list_it = instList.begin();
- while (inst_list_it != instList.end())
- {
- cprintf("Instruction:%i\nPC:%#x\nSN:%lli\nIssued:%i\nSquashed:%i\n\n",
- num, (*inst_list_it)->readPC(), (*inst_list_it)->seqNum,
- (*inst_list_it)->isIssued(), (*inst_list_it)->isSquashed());
+ ListIt inst_list_it = instList.begin();
+
+ cprintf("Dumping Instruction List\n");
+
+ while (inst_list_it != instList.end()) {
+ cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
+ "Squashed:%i\n\n",
+ num, (*inst_list_it)->readPC(), (*inst_list_it)->threadNumber,
+ (*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
+ (*inst_list_it)->isSquashed());
inst_list_it++;
++num;
}
}
-
+/*
template <class Impl>
void
FullO3CPU<Impl>::wakeDependents(DynInstPtr &inst)
{
iew.wakeDependents(inst);
}
+*/
+template <class Impl>
+void
+FullO3CPU<Impl>::wakeCPU()
+{
+ if (activityRec.active() || tickEvent.scheduled()) {
+ DPRINTF(Activity, "CPU already running.\n");
+ return;
+ }
+
+ DPRINTF(Activity, "Waking up CPU\n");
+
+ idleCycles += (curTick - 1) - lastRunningCycle;
+
+ tickEvent.schedule(curTick);
+}
+
+template <class Impl>
+int
+FullO3CPU<Impl>::getFreeTid()
+{
+ for (int i=0; i < numThreads; i++) {
+ if (!tids[i]) {
+ tids[i] = true;
+ return i;
+ }
+ }
+
+ return -1;
+}
+
+template <class Impl>
+void
+FullO3CPU<Impl>::doContextSwitch()
+{
+ if (contextSwitch) {
+
+ //ADD CODE TO DEACTIVE THREAD HERE (???)
+
+ for (int tid=0; tid < cpuWaitList.size(); tid++) {
+ activateWhenReady(tid);
+ }
+
+ if (cpuWaitList.size() == 0)
+ contextSwitch = true;
+ }
+}
+
+template <class Impl>
+void
+FullO3CPU<Impl>::updateThreadPriority()
+{
+ if (activeThreads.size() > 1)
+ {
+ //DEFAULT TO ROUND ROBIN SCHEME
+ //e.g. Move highest priority to end of thread list
+ list<unsigned>::iterator list_begin = activeThreads.begin();
+ list<unsigned>::iterator list_end = activeThreads.end();
+
+ unsigned high_thread = *list_begin;
+
+ activeThreads.erase(list_begin);
+
+ activeThreads.push_back(high_thread);
+ }
+}
// Forward declaration of FullO3CPU.
template class FullO3CPU<AlphaSimpleImpl>;
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index f7c80e8a1..bed95ad54 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -26,31 +26,31 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-//Todo: Add in a lot of the functions that are ISA specific. Also define
-//the functions that currently exist within the base cpu class. Define
-//everything for the simobject stuff so it can be serialized and
-//instantiated, add in debugging statements everywhere. Have CPU schedule
-//itself properly. Threads!
-// Avoid running stages and advancing queues if idle/stalled.
-
-#ifndef __CPU_O3_CPU_FULL_CPU_HH__
-#define __CPU_O3_CPU_FULL_CPU_HH__
+#ifndef __CPU_O3_CPU_HH__
+#define __CPU_O3_CPU_HH__
#include <iostream>
#include <list>
+#include <queue>
+#include <set>
#include <vector>
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "config/full_system.hh"
+#include "cpu/activity.hh"
#include "cpu/base.hh"
#include "cpu/cpu_exec_context.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/cpu_policy.hh"
+#include "cpu/o3/scoreboard.hh"
+#include "cpu/o3/thread_state.hh"
#include "sim/process.hh"
+template <class>
+class Checker;
class ExecContext;
-class FunctionalMemory;
+class MemInterface;
class Process;
class BaseFullCPU : public BaseCPU
@@ -59,11 +59,9 @@ class BaseFullCPU : public BaseCPU
public:
typedef BaseCPU::Params Params;
-#if FULL_SYSTEM
- BaseFullCPU(Params &params);
-#else
- BaseFullCPU(Params &params);
-#endif // FULL_SYSTEM
+ BaseFullCPU(Params *params);
+
+ void regStats();
protected:
int cpu_id;
@@ -73,45 +71,57 @@ template <class Impl>
class FullO3CPU : public BaseFullCPU
{
public:
- //Put typedefs from the Impl here.
+ // Typedefs from the Impl here.
typedef typename Impl::CPUPol CPUPolicy;
typedef typename Impl::Params Params;
typedef typename Impl::DynInstPtr DynInstPtr;
+ typedef O3ThreadState<Impl> Thread;
+
+ typedef typename std::list<DynInstPtr>::iterator ListIt;
+
public:
enum Status {
Running,
Idle,
Halted,
- Blocked // ?
+ Blocked,
+ SwitchedOut
};
+ /** Overall CPU status. */
Status _status;
private:
class TickEvent : public Event
{
private:
+ /** Pointer to the CPU. */
FullO3CPU<Impl> *cpu;
public:
+ /** Constructs a tick event. */
TickEvent(FullO3CPU<Impl> *c);
+
+ /** Processes a tick event, calling tick() on the CPU. */
void process();
+ /** Returns the description of the tick event. */
const char *description();
};
+ /** The tick event used for scheduling CPU ticks. */
TickEvent tickEvent;
- /// Schedule tick event, regardless of its current state.
+ /** Schedule tick event, regardless of its current state. */
void scheduleTickEvent(int delay)
{
if (tickEvent.squashed())
- tickEvent.reschedule(curTick + delay);
+ tickEvent.reschedule(curTick + cycles(delay));
else if (!tickEvent.scheduled())
- tickEvent.schedule(curTick + delay);
+ tickEvent.schedule(curTick + cycles(delay));
}
- /// Unschedule tick event, regardless of its current state.
+ /** Unschedule tick event, regardless of its current state. */
void unscheduleTickEvent()
{
if (tickEvent.scheduled())
@@ -119,25 +129,87 @@ class FullO3CPU : public BaseFullCPU
}
public:
- FullO3CPU(Params &params);
+ /** Constructs a CPU with the given parameters. */
+ FullO3CPU(Params *params);
+ /** Destructor. */
~FullO3CPU();
+ /** Registers statistics. */
void fullCPURegStats();
+ /** Ticks CPU, calling tick() on each stage, and checking the overall
+ * activity to see if the CPU should deschedule itself.
+ */
void tick();
+ /** Initialize the CPU */
void init();
- void activateContext(int thread_num, int delay);
- void suspendContext(int thread_num);
- void deallocateContext(int thread_num);
- void haltContext(int thread_num);
+ /** Setup CPU to insert a thread's context */
+ void insertThread(unsigned tid);
+
+ /** Remove all of a thread's context from CPU */
+ void removeThread(unsigned tid);
+
+ /** Count the Total Instructions Committed in the CPU. */
+ virtual Counter totalInstructions() const
+ {
+ Counter total(0);
+
+ for (int i=0; i < thread.size(); i++)
+ total += thread[i]->numInst;
+
+ return total;
+ }
+
+ /** Add Thread to Active Threads List. */
+ void activateContext(int tid, int delay);
+
+ /** Remove Thread from Active Threads List */
+ void suspendContext(int tid);
+
+ /** Remove Thread from Active Threads List &&
+ * Remove Thread Context from CPU.
+ */
+ void deallocateContext(int tid);
+
+ /** Remove Thread from Active Threads List &&
+ * Remove Thread Context from CPU.
+ */
+ void haltContext(int tid);
+
+ /** Activate a Thread When CPU Resources are Available. */
+ void activateWhenReady(int tid);
- void switchOut();
+ /** Add or Remove a Thread Context in the CPU. */
+ void doContextSwitch();
+
+ /** Update The Order In Which We Process Threads. */
+ void updateThreadPriority();
+
+ /** Executes a syscall on this cycle.
+ * ---------------------------------------
+ * Note: this is a virtual function. CPU-Specific
+ * functionality defined in derived classes
+ */
+ virtual void syscall(int tid) { panic("Unimplemented!"); }
+
+ /** Check if there are any system calls pending. */
+ void checkSyscalls();
+
+ /** Switches out this CPU.
+ */
+ void switchOut(Sampler *sampler);
+
+ void signalSwitched();
+
+ /** Takes over from another CPU.
+ */
void takeOverFrom(BaseCPU *oldCPU);
/** Get the current instruction sequence number, and increment it. */
- InstSeqNum getAndIncrementInstSeq();
+ InstSeqNum getAndIncrementInstSeq()
+ { return globalSeqNum++; }
#if FULL_SYSTEM
/** Check if this address is a valid instruction address. */
@@ -147,21 +219,28 @@ class FullO3CPU : public BaseFullCPU
bool validDataAddr(Addr addr) { return true; }
/** Get instruction asid. */
- int getInstAsid()
- { return regFile.miscRegs.getInstAsid(); }
+ int getInstAsid(unsigned tid)
+ { return regFile.miscRegs[tid].getInstAsid(); }
/** Get data asid. */
- int getDataAsid()
- { return regFile.miscRegs.getDataAsid(); }
+ int getDataAsid(unsigned tid)
+ { return regFile.miscRegs[tid].getDataAsid(); }
#else
- bool validInstAddr(Addr addr)
- { return thread[0]->validInstAddr(addr); }
+ /** Check if this address is a valid instruction address. */
+ bool validInstAddr(Addr addr,unsigned tid)
+ { return thread[tid]->validInstAddr(addr); }
- bool validDataAddr(Addr addr)
- { return thread[0]->validDataAddr(addr); }
+ /** Check if this address is a valid data address. */
+ bool validDataAddr(Addr addr,unsigned tid)
+ { return thread[tid]->validDataAddr(addr); }
- int getInstAsid() { return thread[0]->getInstAsid(); }
- int getDataAsid() { return thread[0]->getDataAsid(); }
+ /** Get instruction asid. */
+ int getInstAsid(unsigned tid)
+ { return thread[tid]->asid; }
+
+ /** Get data asid. */
+ int getDataAsid(unsigned tid)
+ { return thread[tid]->asid; }
#endif
@@ -188,95 +267,101 @@ class FullO3CPU : public BaseFullCPU
void setFloatRegBits(int reg_idx, FloatRegBits val);
- uint64_t readPC();
+ uint64_t readArchIntReg(int reg_idx, unsigned tid);
+
+ float readArchFloatRegSingle(int reg_idx, unsigned tid);
+
+ double readArchFloatRegDouble(int reg_idx, unsigned tid);
+
+ uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
+
+ void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
+
+ void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
+
+ void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
+
+ void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
- void setNextPC(uint64_t val);
+ uint64_t readPC(unsigned tid);
- void setPC(Addr new_PC);
+ void setPC(Addr new_PC,unsigned tid);
+
+ uint64_t readNextPC(unsigned tid);
+
+ void setNextPC(uint64_t val,unsigned tid);
/** Function to add instruction onto the head of the list of the
* instructions. Used when new instructions are fetched.
*/
- void addInst(DynInstPtr &inst);
+ ListIt addInst(DynInstPtr &inst);
/** Function to tell the CPU that an instruction has completed. */
- void instDone();
-
- /** Remove all instructions in back of the given instruction, but leave
- * that instruction in the list. This is useful in a squash, when there
- * are instructions in this list that don't exist in structures such as
- * the ROB. The instruction doesn't have to be the last instruction in
- * the list, but will be once this function completes.
- * @todo: Remove only up until that inst? Squashed inst is most likely
- * valid.
- */
- void removeBackInst(DynInstPtr &inst);
-
- /** Remove an instruction from the front of the list. It is expected
- * that there are no instructions in front of it (that is, none are older
- * than the instruction being removed). Used when retiring instructions.
- * @todo: Remove the argument to this function, and just have it remove
- * last instruction once it's verified that commit has the same ordering
- * as the instruction list.
+ void instDone(unsigned tid);
+
+ /** Add Instructions to the CPU Remove List*/
+ void addToRemoveList(DynInstPtr &inst);
+
+ /** Remove an instruction from the front end of the list. There's
+ * no restriction on location of the instruction.
*/
void removeFrontInst(DynInstPtr &inst);
/** Remove all instructions that are not currently in the ROB. */
- void removeInstsNotInROB();
+ void removeInstsNotInROB(unsigned tid);
/** Remove all instructions younger than the given sequence number. */
- void removeInstsUntil(const InstSeqNum &seq_num);
+ void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
+
+ inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
+
+ void cleanUpRemovedInsts();
/** Remove all instructions from the list. */
- void removeAllInsts();
+// void removeAllInsts();
void dumpInsts();
/** Basically a wrapper function so that instructions executed at
- * commit can tell the instruction queue that they have completed.
- * Eventually this hack should be removed.
+ * commit can tell the instruction queue that they have
+ * completed. Eventually this hack should be removed.
*/
- void wakeDependents(DynInstPtr &inst);
+// void wakeDependents(DynInstPtr &inst);
public:
/** List of all the instructions in flight. */
- list<DynInstPtr> instList;
+ std::list<DynInstPtr> instList;
+
+ /** List of all the instructions that will be removed at the end of this
+ * cycle.
+ */
+ std::queue<ListIt> removeList;
+
+#ifdef DEBUG
+ std::set<InstSeqNum> snList;
+#endif
+
+ /** Records if instructions need to be removed this cycle due to
+ * being retired or squashed.
+ */
+ bool removeInstsThisCycle;
- //not sure these should be private.
protected:
/** The fetch stage. */
typename CPUPolicy::Fetch fetch;
- /** The fetch stage's status. */
- typename CPUPolicy::Fetch::Status fetchStatus;
-
/** The decode stage. */
typename CPUPolicy::Decode decode;
- /** The decode stage's status. */
- typename CPUPolicy::Decode::Status decodeStatus;
-
/** The dispatch stage. */
typename CPUPolicy::Rename rename;
- /** The dispatch stage's status. */
- typename CPUPolicy::Rename::Status renameStatus;
-
/** The issue/execute/writeback stages. */
typename CPUPolicy::IEW iew;
- /** The issue/execute/writeback stage's status. */
- typename CPUPolicy::IEW::Status iewStatus;
-
/** The commit stage. */
typename CPUPolicy::Commit commit;
- /** The fetch stage's status. */
- typename CPUPolicy::Commit::Status commitStatus;
-
- //Might want to just pass these objects in to the constructors of the
- //appropriate stage. regFile is in iew, freeList in dispatch, renameMap
- //in dispatch, and the rob in commit.
/** The register file. */
typename CPUPolicy::RegFile regFile;
@@ -284,12 +369,33 @@ class FullO3CPU : public BaseFullCPU
typename CPUPolicy::FreeList freeList;
/** The rename map. */
- typename CPUPolicy::RenameMap renameMap;
+ typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
+
+ /** The commit rename map. */
+ typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
/** The re-order buffer. */
typename CPUPolicy::ROB rob;
+ /** Active Threads List */
+ std::list<unsigned> activeThreads;
+
+ /** Integer Register Scoreboard */
+ Scoreboard scoreboard;
+
public:
+ /** Enum to give each stage a specific index, so when calling
+ * activateStage() or deactivateStage(), they can specify which stage
+ * is being activated/deactivated.
+ */
+ enum StageIdx {
+ FetchIdx,
+ DecodeIdx,
+ RenameIdx,
+ IEWIdx,
+ CommitIdx,
+ NumStages };
+
/** Typedefs from the Impl to get the structs that each of the
* time buffers should use.
*/
@@ -319,45 +425,101 @@ class FullO3CPU : public BaseFullCPU
TimeBuffer<IEWStruct> iewQueue;
public:
- /** The temporary exec context to support older accessors. */
- CPUExecContext *cpuXC;
+ ActivityRecorder activityRec;
- /** Temporary function to get pointer to exec context. */
- ExecContext *xcBase()
- {
- return thread[0]->getProxy();
- }
+ void activityThisCycle() { activityRec.activity(); }
+
+ void activateStage(const StageIdx idx)
+ { activityRec.activateStage(idx); }
- CPUExecContext *cpuXCBase()
+ void deactivateStage(const StageIdx idx)
+ { activityRec.deactivateStage(idx); }
+
+ /** Wakes the CPU, rescheduling the CPU if it's not already active. */
+ void wakeCPU();
+
+ /** Gets a free thread id. Use if thread ids change across system. */
+ int getFreeTid();
+
+ public:
+ /** Temporary function to get pointer to exec context. */
+ ExecContext *xcBase(unsigned tid)
{
- return thread[0];
+ return thread[tid]->getXCProxy();
}
+ /** The global sequence number counter. */
InstSeqNum globalSeqNum;
+ Checker<DynInstPtr> *checker;
+
#if FULL_SYSTEM
+ /** Pointer to the system. */
System *system;
+ /** Pointer to the memory controller. */
MemoryController *memCtrl;
+ /** Pointer to physical memory. */
PhysicalMemory *physmem;
-
- AlphaITB *itb;
- AlphaDTB *dtb;
-
-// SWContext *swCtx;
#endif
- std::vector<CPUExecContext *> thread;
+ /** Pointer to memory. */
FunctionalMemory *mem;
+ Sampler *sampler;
+
+ int switchCount;
+
+ // List of all ExecContexts.
+ std::vector<Thread *> thread;
+
+#if 0
+ /** Page table pointer. */
+ PageTable *pTable;
+#endif
+
+ /** Pointer to the icache interface. */
MemInterface *icacheInterface;
+ /** Pointer to the dcache interface. */
MemInterface *dcacheInterface;
+ /** Whether or not the CPU should defer its registration. */
bool deferRegistration;
- Counter numInsts;
-
- Counter funcExeInst;
+ /** Is there a context switch pending? */
+ bool contextSwitch;
+
+ /** Threads Scheduled to Enter CPU */
+ std::list<int> cpuWaitList;
+
+ /** The cycle that the CPU was last running, used for statistics. */
+ Tick lastRunningCycle;
+
+ /** Number of Threads CPU can process */
+ unsigned numThreads;
+
+ /** Mapping for system thread id to cpu id */
+ std::map<unsigned,unsigned> threadMap;
+
+ /** Available thread ids in the cpu*/
+ std::vector<unsigned> tids;
+
+ /** Stat for total number of times the CPU is descheduled. */
+ Stats::Scalar<> timesIdled;
+ /** Stat for total number of cycles the CPU spends descheduled. */
+ Stats::Scalar<> idleCycles;
+ /** Stat for the number of committed instructions per thread. */
+ Stats::Vector<> committedInsts;
+ /** Stat for the total number of committed instructions. */
+ Stats::Scalar<> totalCommittedInsts;
+ /** Stat for the CPI per thread. */
+ Stats::Formula cpi;
+ /** Stat for the total CPI. */
+ Stats::Formula totalCpi;
+ /** Stat for the IPC per thread. */
+ Stats::Formula ipc;
+ /** Stat for the total IPC. */
+ Stats::Formula totalIpc;
};
-#endif
+#endif // __CPU_O3_CPU_HH__
diff --git a/src/cpu/o3/cpu_policy.hh b/src/cpu/o3/cpu_policy.hh
index 41f06f81b..52227013e 100644
--- a/src/cpu/o3/cpu_policy.hh
+++ b/src/cpu/o3/cpu_policy.hh
@@ -26,13 +26,14 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_CPU_POLICY_HH__
-#define __CPU_O3_CPU_CPU_POLICY_HH__
+#ifndef __CPU_O3_CPU_POLICY_HH__
+#define __CPU_O3_CPU_POLICY_HH__
#include "cpu/o3/bpred_unit.hh"
#include "cpu/o3/free_list.hh"
#include "cpu/o3/inst_queue.hh"
-#include "cpu/o3/ldstq.hh"
+#include "cpu/o3/lsq.hh"
+#include "cpu/o3/lsq_unit.hh"
#include "cpu/o3/mem_dep_unit.hh"
#include "cpu/o3/regfile.hh"
#include "cpu/o3/rename_map.hh"
@@ -57,32 +58,34 @@ struct SimpleCPUPolicy
typedef ROB<Impl> ROB;
typedef InstructionQueue<Impl> IQ;
typedef MemDepUnit<StoreSet, Impl> MemDepUnit;
- typedef LDSTQ<Impl> LDSTQ;
+ typedef LSQ<Impl> LSQ;
+ typedef LSQUnit<Impl> LSQUnit;
- typedef SimpleFetch<Impl> Fetch;
- typedef SimpleDecode<Impl> Decode;
- typedef SimpleRename<Impl> Rename;
- typedef SimpleIEW<Impl> IEW;
- typedef SimpleCommit<Impl> Commit;
+
+ typedef DefaultFetch<Impl> Fetch;
+ typedef DefaultDecode<Impl> Decode;
+ typedef DefaultRename<Impl> Rename;
+ typedef DefaultIEW<Impl> IEW;
+ typedef DefaultCommit<Impl> Commit;
/** The struct for communication between fetch and decode. */
- typedef SimpleFetchSimpleDecode<Impl> FetchStruct;
+ typedef DefaultFetchDefaultDecode<Impl> FetchStruct;
/** The struct for communication between decode and rename. */
- typedef SimpleDecodeSimpleRename<Impl> DecodeStruct;
+ typedef DefaultDecodeDefaultRename<Impl> DecodeStruct;
/** The struct for communication between rename and IEW. */
- typedef SimpleRenameSimpleIEW<Impl> RenameStruct;
+ typedef DefaultRenameDefaultIEW<Impl> RenameStruct;
/** The struct for communication between IEW and commit. */
- typedef SimpleIEWSimpleCommit<Impl> IEWStruct;
+ typedef DefaultIEWDefaultCommit<Impl> IEWStruct;
/** The struct for communication within the IEW stage. */
typedef IssueStruct<Impl> IssueStruct;
/** The struct for all backwards communication. */
- typedef TimeBufStruct TimeStruct;
+ typedef TimeBufStruct<Impl> TimeStruct;
};
-#endif //__CPU_O3_CPU_CPU_POLICY_HH__
+#endif //__CPU_O3_CPU_POLICY_HH__
diff --git a/src/cpu/o3/decode.cc b/src/cpu/o3/decode.cc
index 290648318..b14fbb7a3 100644
--- a/src/cpu/o3/decode.cc
+++ b/src/cpu/o3/decode.cc
@@ -30,4 +30,4 @@
#include "cpu/o3/alpha_impl.hh"
#include "cpu/o3/decode_impl.hh"
-template class SimpleDecode<AlphaSimpleImpl>;
+template class DefaultDecode<AlphaSimpleImpl>;
diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh
index 5b9a0f822..3035b3387 100644
--- a/src/cpu/o3/decode.hh
+++ b/src/cpu/o3/decode.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,16 +26,23 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_SIMPLE_DECODE_HH__
-#define __CPU_O3_CPU_SIMPLE_DECODE_HH__
+#ifndef __CPU_O3_DECODE_HH__
+#define __CPU_O3_DECODE_HH__
#include <queue>
#include "base/statistics.hh"
#include "base/timebuf.hh"
+/**
+ * DefaultDecode class handles both single threaded and SMT
+ * decode. Its width is specified by the parameters; each cycles it
+ * tries to decode that many instructions. Because instructions are
+ * actually decoded when the StaticInst is created, this stage does
+ * not do much other than check any PC-relative branches.
+ */
template<class Impl>
-class SimpleDecode
+class DefaultDecode
{
private:
// Typedefs from the Impl.
@@ -50,49 +57,129 @@ class SimpleDecode
typedef typename CPUPol::TimeStruct TimeStruct;
public:
- // The only time decode will become blocked is if dispatch becomes
- // blocked, which means IQ or ROB is probably full.
- enum Status {
+ /** Overall decode stage status. Used to determine if the CPU can
+ * deschedule itself due to a lack of activity.
+ */
+ enum DecodeStatus {
+ Active,
+ Inactive
+ };
+
+ /** Individual thread status. */
+ enum ThreadStatus {
Running,
Idle,
+ StartSquash,
Squashing,
Blocked,
Unblocking
};
private:
- // May eventually need statuses on a per thread basis.
- Status _status;
+ /** Decode status. */
+ DecodeStatus _status;
+
+ /** Per-thread status. */
+ ThreadStatus decodeStatus[Impl::MaxThreads];
public:
- SimpleDecode(Params &params);
+ /** DefaultDecode constructor. */
+ DefaultDecode(Params *params);
+ /** Returns the name of decode. */
+ std::string name() const;
+
+ /** Registers statistics. */
void regStats();
+ /** Sets CPU pointer. */
void setCPU(FullCPU *cpu_ptr);
+ /** Sets the main backwards communication time buffer pointer. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
+ /** Sets pointer to time buffer used to communicate to the next stage. */
void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
+ /** Sets pointer to time buffer coming from fetch. */
void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
+ /** Sets pointer to list of active threads. */
+ void setActiveThreads(std::list<unsigned> *at_ptr);
+
+ void switchOut();
+
+ void takeOverFrom();
+ /** Ticks decode, processing all input signals and decoding as many
+ * instructions as possible.
+ */
void tick();
- void decode();
+ /** Determines what to do based on decode's current status.
+ * @param status_change decode() sets this variable if there was a status
+ * change (ie switching from from blocking to unblocking).
+ * @param tid Thread id to decode instructions from.
+ */
+ void decode(bool &status_change, unsigned tid);
+
+ /** Processes instructions from fetch and passes them on to rename.
+ * Decoding of instructions actually happens when they are created in
+ * fetch, so this function mostly checks if PC-relative branches are
+ * correct.
+ */
+ void decodeInsts(unsigned tid);
private:
+ /** Inserts a thread's instructions into the skid buffer, to be decoded
+ * once decode unblocks.
+ */
+ void skidInsert(unsigned tid);
+
+ /** Returns if all of the skid buffers are empty. */
+ bool skidsEmpty();
+
+ /** Updates overall decode status based on all of the threads' statuses. */
+ void updateStatus();
+
+ /** Separates instructions from fetch into individual lists of instructions
+ * sorted by thread.
+ */
+ void sortInsts();
+
+ /** Reads all stall signals from the backwards communication timebuffer. */
+ void readStallSignals(unsigned tid);
+
+ /** Checks all input signals and updates decode's status appropriately. */
+ bool checkSignalsAndUpdate(unsigned tid);
+
+ /** Checks all stall signals, and returns if any are true. */
+ bool checkStall(unsigned tid) const;
+
+ /** Returns if there any instructions from fetch on this cycle. */
inline bool fetchInstsValid();
- void block();
+ /** Switches decode to blocking, and signals back that decode has
+ * become blocked.
+ * @return Returns true if there is a status change.
+ */
+ bool block(unsigned tid);
- inline void unblock();
+ /** Switches decode to unblocking if the skid buffer is empty, and
+ * signals back that decode has unblocked.
+ * @return Returns true if there is a status change.
+ */
+ bool unblock(unsigned tid);
- void squash(DynInstPtr &inst);
+ /** Squashes if there is a PC-relative branch that was predicted
+ * incorrectly. Sends squash information back to fetch.
+ */
+ void squash(DynInstPtr &inst, unsigned tid);
public:
- // Might want to make squash a friend function.
- void squash();
+ /** Squashes due to commit signalling a squash. Changes status to
+ * squashing and clears block/unblock signals as needed.
+ */
+ unsigned squash(unsigned tid);
private:
// Interfaces to objects outside of decode.
@@ -127,10 +214,27 @@ class SimpleDecode
/** Wire to get fetch's output from fetch queue. */
typename TimeBuffer<FetchStruct>::wire fromFetch;
+ /** Queue of all instructions coming from fetch this cycle. */
+ std::queue<DynInstPtr> insts[Impl::MaxThreads];
+
/** Skid buffer between fetch and decode. */
- std::queue<FetchStruct> skidBuffer;
+ std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
+
+ /** Variable that tracks if decode has written to the time buffer this
+ * cycle. Used to tell CPU if there is activity this cycle.
+ */
+ bool wroteToTimeBuffer;
+
+ /** Source of possible stalls. */
+ struct Stalls {
+ bool rename;
+ bool iew;
+ bool commit;
+ };
+
+ /** Tracks which stages are telling decode to stall. */
+ Stalls stalls[Impl::MaxThreads];
- //Consider making these unsigned to avoid any confusion.
/** Rename to decode delay, in ticks. */
unsigned renameToDecodeDelay;
@@ -146,20 +250,43 @@ class SimpleDecode
/** The width of decode, in instructions. */
unsigned decodeWidth;
- /** The instruction that decode is currently on. It needs to have
- * persistent state so that when a stall occurs in the middle of a
- * group of instructions, it can restart at the proper instruction.
- */
- unsigned numInst;
+ /** Index of instructions being sent to rename. */
+ unsigned toRenameIndex;
+
+ /** number of Active Threads*/
+ unsigned numThreads;
+ /** List of active thread ids */
+ std::list<unsigned> *activeThreads;
+
+ /** Number of branches in flight. */
+ unsigned branchCount[Impl::MaxThreads];
+
+ /** Maximum size of the skid buffer. */
+ unsigned skidBufferMax;
+
+ /** Stat for total number of idle cycles. */
Stats::Scalar<> decodeIdleCycles;
+ /** Stat for total number of blocked cycles. */
Stats::Scalar<> decodeBlockedCycles;
+ /** Stat for total number of normal running cycles. */
+ Stats::Scalar<> decodeRunCycles;
+ /** Stat for total number of unblocking cycles. */
Stats::Scalar<> decodeUnblockCycles;
+ /** Stat for total number of squashing cycles. */
Stats::Scalar<> decodeSquashCycles;
+ /** Stat for number of times a branch is resolved at decode. */
+ Stats::Scalar<> decodeBranchResolved;
+ /** Stat for number of times a branch mispredict is detected. */
Stats::Scalar<> decodeBranchMispred;
+ /** Stat for number of times decode detected a non-control instruction
+ * incorrectly predicted as a branch.
+ */
Stats::Scalar<> decodeControlMispred;
+ /** Stat for total number of decoded instructions. */
Stats::Scalar<> decodeDecodedInsts;
+ /** Stat for total number of squashed instructions. */
Stats::Scalar<> decodeSquashedInsts;
};
-#endif // __CPU_O3_CPU_SIMPLE_DECODE_HH__
+#endif // __CPU_O3_DECODE_HH__
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 463f0ddac..2ed7ec6fc 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -28,71 +28,98 @@
#include "cpu/o3/decode.hh"
+using namespace std;
+
template<class Impl>
-SimpleDecode<Impl>::SimpleDecode(Params &params)
- : renameToDecodeDelay(params.renameToDecodeDelay),
- iewToDecodeDelay(params.iewToDecodeDelay),
- commitToDecodeDelay(params.commitToDecodeDelay),
- fetchToDecodeDelay(params.fetchToDecodeDelay),
- decodeWidth(params.decodeWidth),
- numInst(0)
+DefaultDecode<Impl>::DefaultDecode(Params *params)
+ : renameToDecodeDelay(params->renameToDecodeDelay),
+ iewToDecodeDelay(params->iewToDecodeDelay),
+ commitToDecodeDelay(params->commitToDecodeDelay),
+ fetchToDecodeDelay(params->fetchToDecodeDelay),
+ decodeWidth(params->decodeWidth),
+ numThreads(params->numberOfThreads)
{
- DPRINTF(Decode, "Decode: decodeWidth=%i.\n", decodeWidth);
- _status = Idle;
+ _status = Inactive;
+
+ for (int i = 0; i < numThreads; ++i) {
+ decodeStatus[i] = Idle;
+
+ stalls[i].rename = false;
+ stalls[i].iew = false;
+ stalls[i].commit = false;
+ }
+
+ // @todo: Make into a parameter
+ skidBufferMax = (fetchToDecodeDelay * params->fetchWidth) + decodeWidth;
+}
+
+template <class Impl>
+std::string
+DefaultDecode<Impl>::name() const
+{
+ return cpu->name() + ".decode";
}
template <class Impl>
void
-SimpleDecode<Impl>::regStats()
+DefaultDecode<Impl>::regStats()
{
decodeIdleCycles
- .name(name() + ".decodeIdleCycles")
+ .name(name() + ".DECODE:IdleCycles")
.desc("Number of cycles decode is idle")
.prereq(decodeIdleCycles);
decodeBlockedCycles
- .name(name() + ".decodeBlockedCycles")
+ .name(name() + ".DECODE:BlockedCycles")
.desc("Number of cycles decode is blocked")
.prereq(decodeBlockedCycles);
+ decodeRunCycles
+ .name(name() + ".DECODE:RunCycles")
+ .desc("Number of cycles decode is running")
+ .prereq(decodeRunCycles);
decodeUnblockCycles
- .name(name() + ".decodeUnblockCycles")
+ .name(name() + ".DECODE:UnblockCycles")
.desc("Number of cycles decode is unblocking")
.prereq(decodeUnblockCycles);
decodeSquashCycles
- .name(name() + ".decodeSquashCycles")
+ .name(name() + ".DECODE:SquashCycles")
.desc("Number of cycles decode is squashing")
.prereq(decodeSquashCycles);
+ decodeBranchResolved
+ .name(name() + ".DECODE:BranchResolved")
+ .desc("Number of times decode resolved a branch")
+ .prereq(decodeBranchResolved);
decodeBranchMispred
- .name(name() + ".decodeBranchMispred")
+ .name(name() + ".DECODE:BranchMispred")
.desc("Number of times decode detected a branch misprediction")
.prereq(decodeBranchMispred);
decodeControlMispred
- .name(name() + ".decodeControlMispred")
+ .name(name() + ".DECODE:ControlMispred")
.desc("Number of times decode detected an instruction incorrectly"
" predicted as a control")
.prereq(decodeControlMispred);
decodeDecodedInsts
- .name(name() + ".decodeDecodedInsts")
+ .name(name() + ".DECODE:DecodedInsts")
.desc("Number of instructions handled by decode")
.prereq(decodeDecodedInsts);
decodeSquashedInsts
- .name(name() + ".decodeSquashedInsts")
+ .name(name() + ".DECODE:SquashedInsts")
.desc("Number of squashed instructions handled by decode")
.prereq(decodeSquashedInsts);
}
template<class Impl>
void
-SimpleDecode<Impl>::setCPU(FullCPU *cpu_ptr)
+DefaultDecode<Impl>::setCPU(FullCPU *cpu_ptr)
{
- DPRINTF(Decode, "Decode: Setting CPU pointer.\n");
+ DPRINTF(Decode, "Setting CPU pointer.\n");
cpu = cpu_ptr;
}
template<class Impl>
void
-SimpleDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
+DefaultDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
{
- DPRINTF(Decode, "Decode: Setting time buffer pointer.\n");
+ DPRINTF(Decode, "Setting time buffer pointer.\n");
timeBuffer = tb_ptr;
// Setup wire to write information back to fetch.
@@ -106,9 +133,9 @@ SimpleDecode<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
template<class Impl>
void
-SimpleDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
+DefaultDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
{
- DPRINTF(Decode, "Decode: Setting decode queue pointer.\n");
+ DPRINTF(Decode, "Setting decode queue pointer.\n");
decodeQueue = dq_ptr;
// Setup wire to write information to proper place in decode queue.
@@ -117,9 +144,9 @@ SimpleDecode<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
template<class Impl>
void
-SimpleDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
+DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
{
- DPRINTF(Decode, "Decode: Setting fetch queue pointer.\n");
+ DPRINTF(Decode, "Setting fetch queue pointer.\n");
fetchQueue = fq_ptr;
// Setup wire to read information from fetch queue.
@@ -127,250 +154,534 @@ SimpleDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
}
template<class Impl>
+void
+DefaultDecode<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+{
+ DPRINTF(Decode, "Setting active threads list pointer.\n");
+ activeThreads = at_ptr;
+}
+
+template <class Impl>
+void
+DefaultDecode<Impl>::switchOut()
+{
+ cpu->signalSwitched();
+}
+
+template <class Impl>
+void
+DefaultDecode<Impl>::takeOverFrom()
+{
+ _status = Inactive;
+
+ for (int i = 0; i < numThreads; ++i) {
+ decodeStatus[i] = Idle;
+
+ stalls[i].rename = false;
+ stalls[i].iew = false;
+ stalls[i].commit = false;
+ while (!insts[i].empty())
+ insts[i].pop();
+ while (!skidBuffer[i].empty())
+ skidBuffer[i].pop();
+ branchCount[i] = 0;
+ }
+ wroteToTimeBuffer = false;
+}
+
+template<class Impl>
+bool
+DefaultDecode<Impl>::checkStall(unsigned tid) const
+{
+ bool ret_val = false;
+
+ if (stalls[tid].rename) {
+ DPRINTF(Decode,"[tid:%i]: Stall fom Rename stage detected.\n", tid);
+ ret_val = true;
+ } else if (stalls[tid].iew) {
+ DPRINTF(Decode,"[tid:%i]: Stall fom IEW stage detected.\n", tid);
+ ret_val = true;
+ } else if (stalls[tid].commit) {
+ DPRINTF(Decode,"[tid:%i]: Stall fom Commit stage detected.\n", tid);
+ ret_val = true;
+ }
+
+ return ret_val;
+}
+
+template<class Impl>
inline bool
-SimpleDecode<Impl>::fetchInstsValid()
+DefaultDecode<Impl>::fetchInstsValid()
{
return fromFetch->size > 0;
}
template<class Impl>
-void
-SimpleDecode<Impl>::block()
+bool
+DefaultDecode<Impl>::block(unsigned tid)
{
- DPRINTF(Decode, "Decode: Blocking.\n");
-
- // Set the status to Blocked.
- _status = Blocked;
+ DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
+
+ // If the decode status is blocked or unblocking then decode has not yet
+ // signalled fetch to unblock. In that case, there is no need to tell
+ // fetch to block.
+ if (decodeStatus[tid] != Blocked &&
+ decodeStatus[tid] != Unblocking) {
+ toFetch->decodeBlock[tid] = true;
+ wroteToTimeBuffer = true;
+ }
// Add the current inputs to the skid buffer so they can be
// reprocessed when this stage unblocks.
- skidBuffer.push(*fromFetch);
+ skidInsert(tid);
+
+ if (decodeStatus[tid] != Blocked) {
+ // Set the status to Blocked.
+ decodeStatus[tid] = Blocked;
+ return true;
+ }
- // Note that this stage only signals previous stages to stall when
- // it is the cause of the stall originates at this stage. Otherwise
- // the previous stages are expected to check all possible stall signals.
+ return false;
}
template<class Impl>
-inline void
-SimpleDecode<Impl>::unblock()
+bool
+DefaultDecode<Impl>::unblock(unsigned tid)
{
- DPRINTF(Decode, "Decode: Unblocking, going to remove "
- "instructions from skid buffer.\n");
- // Remove the now processed instructions from the skid buffer.
- skidBuffer.pop();
-
- // If there's still information in the skid buffer, then
- // continue to tell previous stages to stall. They will be
- // able to restart once the skid buffer is empty.
- if (!skidBuffer.empty()) {
- toFetch->decodeInfo.stall = true;
- } else {
- DPRINTF(Decode, "Decode: Finished unblocking.\n");
- _status = Running;
+ // Decode is done unblocking only if the skid buffer is empty.
+ if (skidBuffer[tid].empty()) {
+ DPRINTF(Decode, "[tid:%u]: Done unblocking.\n", tid);
+ toFetch->decodeUnblock[tid] = true;
+ wroteToTimeBuffer = true;
+
+ decodeStatus[tid] = Running;
+ return true;
}
+
+ DPRINTF(Decode, "[tid:%u]: Currently unblocking.\n", tid);
+
+ return false;
}
-// This squash is specifically for when Decode detects a PC-relative branch
-// was predicted incorrectly.
template<class Impl>
void
-SimpleDecode<Impl>::squash(DynInstPtr &inst)
+DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
{
- DPRINTF(Decode, "Decode: Squashing due to incorrect branch prediction "
- "detected at decode.\n");
- Addr new_PC = inst->readNextPC();
-
- toFetch->decodeInfo.branchMispredict = true;
- toFetch->decodeInfo.doneSeqNum = inst->seqNum;
- toFetch->decodeInfo.predIncorrect = true;
- toFetch->decodeInfo.squash = true;
- toFetch->decodeInfo.nextPC = new_PC;
- toFetch->decodeInfo.branchTaken = true;
+ DPRINTF(Decode, "[tid:%i]: Squashing due to incorrect branch prediction "
+ "detected at decode.\n", tid);
+
+ toFetch->decodeInfo[tid].branchMispredict = true;
+ toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
+ toFetch->decodeInfo[tid].predIncorrect = true;
+ toFetch->decodeInfo[tid].squash = true;
+ toFetch->decodeInfo[tid].nextPC = inst->readNextPC();
+ toFetch->decodeInfo[tid].branchTaken = true;
+
+ if (decodeStatus[tid] == Blocked ||
+ decodeStatus[tid] == Unblocking) {
+ toFetch->decodeUnblock[tid] = 1;
+ }
// Set status to squashing.
- _status = Squashing;
+ decodeStatus[tid] = Squashing;
+
+ for (int i=0; i<fromFetch->size; i++) {
+ if (fromFetch->insts[i]->threadNumber == tid &&
+ fromFetch->insts[i]->seqNum > inst->seqNum) {
+ fromFetch->insts[i]->squashed = true;
+ }
+ }
+
+ while (!insts[tid].empty()) {
+ insts[tid].pop();
+ }
// Clear the skid buffer in case it has any data in it.
- while (!skidBuffer.empty()) {
- skidBuffer.pop();
+ while (!skidBuffer[tid].empty()) {
+ skidBuffer[tid].pop();
}
// Squash instructions up until this one
- // Slightly unrealistic!
- cpu->removeInstsUntil(inst->seqNum);
+ cpu->removeInstsUntil(inst->seqNum, tid);
}
template<class Impl>
-void
-SimpleDecode<Impl>::squash()
+unsigned
+DefaultDecode<Impl>::squash(unsigned tid)
{
- DPRINTF(Decode, "Decode: Squashing.\n");
+ DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
+
+ if (decodeStatus[tid] == Blocked ||
+ decodeStatus[tid] == Unblocking) {
+#if !FULL_SYSTEM
+ // In syscall emulation, we can have both a block and a squash due
+ // to a syscall in the same cycle. This would cause both signals to
+ // be high. This shouldn't happen in full system.
+ // @todo: Determine if this still happens.
+ if (toFetch->decodeBlock[tid]) {
+ toFetch->decodeBlock[tid] = 0;
+ } else {
+ toFetch->decodeUnblock[tid] = 1;
+ }
+#else
+ toFetch->decodeUnblock[tid] = 1;
+#endif
+ }
+
// Set status to squashing.
- _status = Squashing;
+ decodeStatus[tid] = Squashing;
- // Maybe advance the time buffer? Not sure what to do in the normal
- // case.
+ // Go through incoming instructions from fetch and squash them.
+ unsigned squash_count = 0;
+
+ for (int i=0; i<fromFetch->size; i++) {
+ if (fromFetch->insts[i]->threadNumber == tid) {
+ fromFetch->insts[i]->squashed = true;
+ squash_count++;
+ }
+ }
+
+ while (!insts[tid].empty()) {
+ insts[tid].pop();
+ }
// Clear the skid buffer in case it has any data in it.
- while (!skidBuffer.empty())
- {
- skidBuffer.pop();
+ while (!skidBuffer[tid].empty()) {
+ skidBuffer[tid].pop();
}
+
+ return squash_count;
}
template<class Impl>
void
-SimpleDecode<Impl>::tick()
+DefaultDecode<Impl>::skidInsert(unsigned tid)
{
- // Decode should try to execute as many instructions as its bandwidth
- // will allow, as long as it is not currently blocked.
- if (_status != Blocked && _status != Squashing) {
- DPRINTF(Decode, "Decode: Not blocked, so attempting to run "
- "stage.\n");
- // Make sure that the skid buffer has something in it if the
- // status is unblocking.
- assert(_status == Unblocking ? !skidBuffer.empty() : 1);
+ DynInstPtr inst = NULL;
- decode();
+ while (!insts[tid].empty()) {
+ inst = insts[tid].front();
- // If the status was unblocking, then instructions from the skid
- // buffer were used. Remove those instructions and handle
- // the rest of unblocking.
- if (_status == Unblocking) {
- ++decodeUnblockCycles;
+ insts[tid].pop();
- if (fetchInstsValid()) {
- // Add the current inputs to the skid buffer so they can be
- // reprocessed when this stage unblocks.
- skidBuffer.push(*fromFetch);
- }
+ assert(tid == inst->threadNumber);
- unblock();
- }
- } else if (_status == Blocked) {
- ++decodeBlockedCycles;
+ DPRINTF(Decode,"Inserting [sn:%lli] PC:%#x into decode skidBuffer %i\n",
+ inst->seqNum, inst->readPC(), inst->threadNumber);
- if (fetchInstsValid()) {
- block();
- }
+ skidBuffer[tid].push(inst);
+ }
- if (!fromRename->renameInfo.stall &&
- !fromIEW->iewInfo.stall &&
- !fromCommit->commitInfo.stall) {
- DPRINTF(Decode, "Decode: Stall signals cleared, going to "
- "unblock.\n");
- _status = Unblocking;
+ // @todo: Eventually need to enforce this by not letting a thread
+ // fetch past its skidbuffer
+ assert(skidBuffer[tid].size() <= skidBufferMax);
+}
- // Continue to tell previous stage to block until this
- // stage is done unblocking.
- toFetch->decodeInfo.stall = true;
- } else {
- DPRINTF(Decode, "Decode: Still blocked.\n");
- toFetch->decodeInfo.stall = true;
+template<class Impl>
+bool
+DefaultDecode<Impl>::skidsEmpty()
+{
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ if (!skidBuffer[*threads++].empty())
+ return false;
+ }
+
+ return true;
+}
+
+template<class Impl>
+void
+DefaultDecode<Impl>::updateStatus()
+{
+ bool any_unblocking = false;
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ if (decodeStatus[tid] == Unblocking) {
+ any_unblocking = true;
+ break;
}
+ }
+
+ // Decode will have activity if it's unblocking.
+ if (any_unblocking) {
+ if (_status == Inactive) {
+ _status = Active;
+
+ DPRINTF(Activity, "Activating stage.\n");
- if (fromCommit->commitInfo.squash ||
- fromCommit->commitInfo.robSquashing) {
- squash();
+ cpu->activateStage(FullCPU::DecodeIdx);
}
- } else if (_status == Squashing) {
- if (!fromCommit->commitInfo.squash &&
- !fromCommit->commitInfo.robSquashing) {
- _status = Running;
- } else if (fromCommit->commitInfo.squash) {
- ++decodeSquashCycles;
-
- squash();
+ } else {
+ // If it's not unblocking, then decode will not have any internal
+ // activity. Switch it to inactive.
+ if (_status == Active) {
+ _status = Inactive;
+ DPRINTF(Activity, "Deactivating stage.\n");
+
+ cpu->deactivateStage(FullCPU::DecodeIdx);
}
}
}
+template <class Impl>
+void
+DefaultDecode<Impl>::sortInsts()
+{
+ int insts_from_fetch = fromFetch->size;
+#ifdef DEBUG
+ for (int i=0; i < numThreads; i++)
+ assert(insts[i].empty());
+#endif
+ for (int i = 0; i < insts_from_fetch; ++i) {
+ insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
+ }
+}
+
template<class Impl>
void
-SimpleDecode<Impl>::decode()
+DefaultDecode<Impl>::readStallSignals(unsigned tid)
{
- // Check time buffer if being told to squash.
- if (fromCommit->commitInfo.squash) {
- squash();
- return;
+ if (fromRename->renameBlock[tid]) {
+ stalls[tid].rename = true;
}
- // Check time buffer if being told to stall.
- if (fromRename->renameInfo.stall ||
- fromIEW->iewInfo.stall ||
- fromCommit->commitInfo.stall) {
- block();
- return;
+ if (fromRename->renameUnblock[tid]) {
+ assert(stalls[tid].rename);
+ stalls[tid].rename = false;
+ }
+
+ if (fromIEW->iewBlock[tid]) {
+ stalls[tid].iew = true;
+ }
+
+ if (fromIEW->iewUnblock[tid]) {
+ assert(stalls[tid].iew);
+ stalls[tid].iew = false;
+ }
+
+ if (fromCommit->commitBlock[tid]) {
+ stalls[tid].commit = true;
+ }
+
+ if (fromCommit->commitUnblock[tid]) {
+ assert(stalls[tid].commit);
+ stalls[tid].commit = false;
+ }
+}
+
+template <class Impl>
+bool
+DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid)
+{
+ // Check if there's a squash signal, squash if there is.
+ // Check stall signals, block if necessary.
+ // If status was blocked
+ // Check if stall conditions have passed
+ // if so then go to unblocking
+ // If status was Squashing
+ // check if squashing is not high. Switch to running this cycle.
+
+ // Update the per thread stall statuses.
+ readStallSignals(tid);
+
+ // Check squash signals from commit.
+ if (fromCommit->commitInfo[tid].squash) {
+
+ DPRINTF(Decode, "[tid:%u]: Squashing instructions due to squash "
+ "from commit.\n", tid);
+
+ squash(tid);
+
+ return true;
+ }
+
+ // Check ROB squash signals from commit.
+ if (fromCommit->commitInfo[tid].robSquashing) {
+ DPRINTF(Decode, "[tid:%]: ROB is still squashing.\n",tid);
+
+ // Continue to squash.
+ decodeStatus[tid] = Squashing;
+
+ return true;
+ }
+
+ if (checkStall(tid)) {
+ return block(tid);
}
- // Check fetch queue to see if instructions are available.
- // If no available instructions, do nothing, unless this stage is
- // currently unblocking.
- if (!fetchInstsValid() && _status != Unblocking) {
- DPRINTF(Decode, "Decode: Nothing to do, breaking out early.\n");
+ if (decodeStatus[tid] == Blocked) {
+ DPRINTF(Decode, "[tid:%u]: Done blocking, switching to unblocking.\n",
+ tid);
+
+ decodeStatus[tid] = Unblocking;
+
+ unblock(tid);
+
+ return true;
+ }
+
+ if (decodeStatus[tid] == Squashing) {
+ // Switch status to running if decode isn't being told to block or
+ // squash this cycle.
+ DPRINTF(Decode, "[tid:%u]: Done squashing, switching to running.\n",
+ tid);
+
+ decodeStatus[tid] = Running;
+
+ return false;
+ }
+
+ // If we've reached this point, we have not gotten any signals that
+ // cause decode to change its status. Decode remains the same as before.
+ return false;
+}
+
+template<class Impl>
+void
+DefaultDecode<Impl>::tick()
+{
+ wroteToTimeBuffer = false;
+
+ bool status_change = false;
+
+ toRenameIndex = 0;
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ sortInsts();
+
+ //Check stall and squash signals.
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ DPRINTF(Decode,"Processing [tid:%i]\n",tid);
+ status_change = checkSignalsAndUpdate(tid) || status_change;
+
+ decode(status_change, tid);
+ }
+
+ if (status_change) {
+ updateStatus();
+ }
+
+ if (wroteToTimeBuffer) {
+ DPRINTF(Activity, "Activity this cycle.\n");
+
+ cpu->activityThisCycle();
+ }
+}
+
+template<class Impl>
+void
+DefaultDecode<Impl>::decode(bool &status_change, unsigned tid)
+{
+ // If status is Running or idle,
+ // call decodeInsts()
+ // If status is Unblocking,
+ // buffer any instructions coming from fetch
+ // continue trying to empty skid buffer
+ // check if stall conditions have passed
+
+ if (decodeStatus[tid] == Blocked) {
+ ++decodeBlockedCycles;
+ } else if (decodeStatus[tid] == Squashing) {
+ ++decodeSquashCycles;
+ }
+
+ // Decode should try to decode as many instructions as its bandwidth
+ // will allow, as long as it is not currently blocked.
+ if (decodeStatus[tid] == Running ||
+ decodeStatus[tid] == Idle) {
+ DPRINTF(Decode, "[tid:%u] Not blocked, so attempting to run "
+ "stage.\n",tid);
+
+ decodeInsts(tid);
+ } else if (decodeStatus[tid] == Unblocking) {
+ // Make sure that the skid buffer has something in it if the
+ // status is unblocking.
+ assert(!skidsEmpty());
+
+ // If the status was unblocking, then instructions from the skid
+ // buffer were used. Remove those instructions and handle
+ // the rest of unblocking.
+ decodeInsts(tid);
+
+ if (fetchInstsValid()) {
+ // Add the current inputs to the skid buffer so they can be
+ // reprocessed when this stage unblocks.
+ skidInsert(tid);
+ }
+
+ status_change = unblock(tid) || status_change;
+ }
+}
+
+template <class Impl>
+void
+DefaultDecode<Impl>::decodeInsts(unsigned tid)
+{
+ // Instructions can come either from the skid buffer or the list of
+ // instructions coming from fetch, depending on decode's status.
+ int insts_available = decodeStatus[tid] == Unblocking ?
+ skidBuffer[tid].size() : insts[tid].size();
+
+ if (insts_available == 0) {
+ DPRINTF(Decode, "[tid:%u] Nothing to do, breaking out"
+ " early.\n",tid);
// Should I change the status to idle?
++decodeIdleCycles;
return;
+ } else if (decodeStatus[tid] == Unblocking) {
+ DPRINTF(Decode, "[tid:%u] Unblocking, removing insts from skid "
+ "buffer.\n",tid);
+ ++decodeUnblockCycles;
+ } else if (decodeStatus[tid] == Running) {
+ ++decodeRunCycles;
}
- // Might be better to use a base DynInst * instead?
DynInstPtr inst;
- unsigned to_rename_index = 0;
+ std::queue<DynInstPtr>
+ &insts_to_decode = decodeStatus[tid] == Unblocking ?
+ skidBuffer[tid] : insts[tid];
- int insts_available = _status == Unblocking ?
- skidBuffer.front().size - numInst :
- fromFetch->size;
+ DPRINTF(Decode, "[tid:%u]: Sending instruction to rename.\n",tid);
- // Debug block...
-#if 0
- if (insts_available) {
- DPRINTF(Decode, "Decode: Instructions available.\n");
- } else {
- if (_status == Unblocking && skidBuffer.empty()) {
- DPRINTF(Decode, "Decode: No instructions available, skid buffer "
- "empty.\n");
- } else if (_status != Unblocking &&
- !fromFetch->insts[0]) {
- DPRINTF(Decode, "Decode: No instructions available, fetch queue "
- "empty.\n");
- } else {
- panic("Decode: No instructions available, unexpected condition!"
- "\n");
- }
- }
-#endif
+ while (insts_available > 0 && toRenameIndex < decodeWidth) {
+ assert(!insts_to_decode.empty());
- while (insts_available > 0)
- {
- DPRINTF(Decode, "Decode: Sending instruction to rename.\n");
+ inst = insts_to_decode.front();
- inst = _status == Unblocking ? skidBuffer.front().insts[numInst] :
- fromFetch->insts[numInst];
+ insts_to_decode.pop();
- DPRINTF(Decode, "Decode: Processing instruction %i with PC %#x\n",
- inst->seqNum, inst->readPC());
+ DPRINTF(Decode, "[tid:%u]: Processing instruction [sn:%lli] with "
+ "PC %#x\n",
+ tid, inst->seqNum, inst->readPC());
if (inst->isSquashed()) {
- DPRINTF(Decode, "Decode: Instruction %i with PC %#x is "
+ DPRINTF(Decode, "[tid:%u]: Instruction %i with PC %#x is "
"squashed, skipping.\n",
- inst->seqNum, inst->readPC());
+ tid, inst->seqNum, inst->readPC());
++decodeSquashedInsts;
- ++numInst;
--insts_available;
continue;
}
-
// Also check if instructions have no source registers. Mark
// them as ready to issue at any time. Not sure if this check
// should exist here or at a later stage; however it doesn't matter
// too much for function correctness.
- // Isn't this handled by the inst queue?
if (inst->numSrcRegs() == 0) {
inst->setCanIssue();
}
@@ -378,9 +689,12 @@ SimpleDecode<Impl>::decode()
// This current instruction is valid, so add it into the decode
// queue. The next instruction may not be valid, so check to
// see if branches were predicted correctly.
- toRename->insts[to_rename_index] = inst;
+ toRename->insts[toRenameIndex] = inst;
++(toRename->size);
+ ++toRenameIndex;
+ ++decodeDecodedInsts;
+ --insts_available;
// Ensure that if it was predicted as a branch, it really is a
// branch.
@@ -388,38 +702,40 @@ SimpleDecode<Impl>::decode()
panic("Instruction predicted as a branch!");
++decodeControlMispred;
+
// Might want to set some sort of boolean and just do
// a check at the end
- squash(inst);
+ squash(inst, inst->threadNumber);
+
break;
}
// Go ahead and compute any PC-relative branches.
-
if (inst->isDirectCtrl() && inst->isUncondCtrl()) {
-
+ ++decodeBranchResolved;
inst->setNextPC(inst->branchTarget());
if (inst->mispredicted()) {
++decodeBranchMispred;
+
// Might want to set some sort of boolean and just do
// a check at the end
- squash(inst);
+ squash(inst, inst->threadNumber);
+
break;
}
}
+ }
- // Normally can check if a direct branch has the right target
- // addr (either the immediate, or the branch PC + 4) and redirect
- // fetch if it's incorrect.
-
- // Increment which instruction we're looking at.
- ++numInst;
- ++to_rename_index;
- ++decodeDecodedInsts;
-
- --insts_available;
+ // If we didn't process all instructions, then we will need to block
+ // and put all those instructions into the skid buffer.
+ if (!insts_to_decode.empty()) {
+ block(tid);
}
- numInst = 0;
+ // Record that decode has written to the time buffer for activity
+ // tracking.
+ if (toRenameIndex) {
+ wroteToTimeBuffer = true;
+ }
}
diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc
index 8ad5e6565..7959416be 100644
--- a/src/cpu/o3/fetch.cc
+++ b/src/cpu/o3/fetch.cc
@@ -30,4 +30,4 @@
#include "cpu/o3/alpha_impl.hh"
#include "cpu/o3/fetch_impl.hh"
-template class SimpleFetch<AlphaSimpleImpl>;
+template class DefaultFetch<AlphaSimpleImpl>;
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index cc64800d9..3fcfdc3a1 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,11 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-// Todo: SMT fetch,
-// Add a way to get a stage's current status.
-
-#ifndef __CPU_O3_CPU_SIMPLE_FETCH_HH__
-#define __CPU_O3_CPU_SIMPLE_FETCH_HH__
+#ifndef __CPU_O3_FETCH_HH__
+#define __CPU_O3_FETCH_HH__
#include "base/statistics.hh"
#include "base/timebuf.hh"
@@ -38,14 +35,18 @@
#include "mem/mem_interface.hh"
#include "sim/eventq.hh"
+class Sampler;
+
/**
- * SimpleFetch class to fetch a single instruction each cycle. SimpleFetch
- * will stall if there's an Icache miss, but otherwise assumes a one cycle
- * Icache hit.
+ * DefaultFetch class handles both single threaded and SMT fetch. Its
+ * width is specified by the parameters; each cycle it tries to fetch
+ * that many instructions. It supports using a branch predictor to
+ * predict direction and targets.
+ * It supports the idling functionalitiy of the CPU by indicating to
+ * the CPU when it is active and inactive.
*/
-
template <class Impl>
-class SimpleFetch
+class DefaultFetch
{
public:
/** Typedefs from Impl. */
@@ -55,56 +56,134 @@ class SimpleFetch
typedef typename Impl::FullCPU FullCPU;
typedef typename Impl::Params Params;
+ /** Typedefs from the CPU policy. */
typedef typename CPUPol::BPredUnit BPredUnit;
typedef typename CPUPol::FetchStruct FetchStruct;
typedef typename CPUPol::TimeStruct TimeStruct;
/** Typedefs from ISA. */
typedef TheISA::MachInst MachInst;
+ typedef TheISA::ExtMachInst ExtMachInst;
public:
- enum Status {
+ /** Overall fetch status. Used to determine if the CPU can
+ * deschedule itsef due to a lack of activity.
+ */
+ enum FetchStatus {
+ Active,
+ Inactive
+ };
+
+ /** Individual thread status. */
+ enum ThreadStatus {
Running,
Idle,
Squashing,
Blocked,
+ Fetching,
+ TrapPending,
+ QuiescePending,
+ SwitchOut,
IcacheMissStall,
IcacheMissComplete
};
- // May eventually need statuses on a per thread basis.
- Status _status;
+ /** Fetching Policy, Add new policies here.*/
+ enum FetchPriority {
+ SingleThread,
+ RoundRobin,
+ Branch,
+ IQ,
+ LSQ
+ };
+
+ private:
+ /** Fetch status. */
+ FetchStatus _status;
+
+ /** Per-thread status. */
+ ThreadStatus fetchStatus[Impl::MaxThreads];
+
+ /** Fetch policy. */
+ FetchPriority fetchPolicy;
- bool stalled;
+ /** List that has the threads organized by priority. */
+ std::list<unsigned> priorityList;
public:
class CacheCompletionEvent : public Event
{
private:
- SimpleFetch *fetch;
+ MemReqPtr req;
+ /** Pointer to fetch. */
+ DefaultFetch *fetch;
+ /** Thread id. */
+// unsigned threadId;
public:
- CacheCompletionEvent(SimpleFetch *_fetch);
+ /** Constructs a cache completion event, which tells fetch when the
+ * cache miss is complete.
+ */
+ CacheCompletionEvent(MemReqPtr &_req, DefaultFetch *_fetch);
+ /** Processes cache completion event. */
virtual void process();
+ /** Returns the description of the cache completion event. */
virtual const char *description();
};
public:
- /** SimpleFetch constructor. */
- SimpleFetch(Params &params);
+ /** DefaultFetch constructor. */
+ DefaultFetch(Params *params);
+ /** Returns the name of fetch. */
+ std::string name() const;
+
+ /** Registers statistics. */
void regStats();
+ /** Sets CPU pointer. */
void setCPU(FullCPU *cpu_ptr);
+ /** Sets the main backwards communication time buffer pointer. */
void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
+ /** Sets pointer to list of active threads. */
+ void setActiveThreads(std::list<unsigned> *at_ptr);
+
+ /** Sets pointer to time buffer used to communicate to the next stage. */
void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
- void processCacheCompletion();
+ /** Sets pointer to page table. */
+// void setPageTable(PageTable *pt_ptr);
+
+ /** Initialize stage. */
+ void initStage();
+
+ /** Processes cache completion event. */
+ void processCacheCompletion(MemReqPtr &req);
+
+ void switchOut();
+
+ void doSwitchOut();
+
+ void takeOverFrom();
+
+ bool isSwitchedOut() { return switchedOut; }
+
+ void wakeFromQuiesce();
private:
+ /** Changes the status of this stage to active, and indicates this
+ * to the CPU.
+ */
+ inline void switchToActive();
+
+ /** Changes the status of this stage to inactive, and indicates
+ * this to the CPU.
+ */
+ inline void switchToInactive();
+
/**
* Looks up in the branch predictor to see if the next PC should be
* either next PC+=MachInst or a branch target.
@@ -120,24 +199,54 @@ class SimpleFetch
* fault that happened. Puts the data into the class variable
* cacheData.
* @param fetch_PC The PC address that is being fetched from.
+ * @param ret_fault The fault reference that will be set to the result of
+ * the icache access.
+ * @param tid Thread id.
* @return Any fault that occured.
*/
- Fault fetchCacheLine(Addr fetch_PC);
+ bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
- inline void doSquash(const Addr &new_PC);
+ /** Squashes a specific thread and resets the PC. */
+ inline void doSquash(const Addr &new_PC, unsigned tid);
- void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num);
+ /** Squashes a specific thread and resets the PC. Also tells the CPU to
+ * remove any instructions between fetch and decode that should be sqaushed.
+ */
+ void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
+ unsigned tid);
+
+ /** Checks if a thread is stalled. */
+ bool checkStall(unsigned tid) const;
+
+ /** Updates overall fetch stage status; to be called at the end of each
+ * cycle. */
+ FetchStatus updateFetchStatus();
public:
- // Figure out PC vs next PC and how it should be updated
- void squash(const Addr &new_PC);
+ /** Squashes a specific thread and resets the PC. Also tells the CPU to
+ * remove any instructions that are not in the ROB. The source of this
+ * squash should be the commit stage.
+ */
+ void squash(const Addr &new_PC, unsigned tid);
+ /** Ticks the fetch stage, processing all inputs signals and fetching
+ * as many instructions as possible.
+ */
void tick();
- void fetch();
+ /** Checks all input signals and updates the status as necessary.
+ * @return: Returns if the status has changed due to input signals.
+ */
+ bool checkSignalsAndUpdate(unsigned tid);
+
+ /** Does the actual fetching of instructions and passing them on to the
+ * next stage.
+ * @param status_change fetch() sets this variable if there was a status
+ * change (ie switching to IcacheMissStall).
+ */
+ void fetch(bool &status_change);
- // Align an address (typically a PC) to the start of an I-cache block.
- // We fold in the PISA 64- to 32-bit conversion here as well.
+ /** Align a PC to the start of an I-cache block. */
Addr icacheBlockAlignPC(Addr addr)
{
addr = TheISA::realPCToFetchPC(addr);
@@ -145,6 +254,22 @@ class SimpleFetch
}
private:
+ /** Returns the appropriate thread to fetch, given the fetch policy. */
+ int getFetchingThread(FetchPriority &fetch_priority);
+
+ /** Returns the appropriate thread to fetch using a round robin policy. */
+ int roundRobin();
+
+ /** Returns the appropriate thread to fetch using the IQ count policy. */
+ int iqCount();
+
+ /** Returns the appropriate thread to fetch using the LSQ count policy. */
+ int lsqCount();
+
+ /** Returns the appropriate thread to fetch using the branch count policy. */
+ int branchCount();
+
+ private:
/** Pointer to the FullCPU. */
FullCPU *cpu;
@@ -176,8 +301,31 @@ class SimpleFetch
/** BPredUnit. */
BPredUnit branchPred;
+ Addr PC[Impl::MaxThreads];
+
+ Addr nextPC[Impl::MaxThreads];
+
/** Memory request used to access cache. */
- MemReqPtr memReq;
+ MemReqPtr memReq[Impl::MaxThreads];
+
+ /** Variable that tracks if fetch has written to the time buffer this
+ * cycle. Used to tell CPU if there is activity this cycle.
+ */
+ bool wroteToTimeBuffer;
+
+ /** Tracks how many instructions has been fetched this cycle. */
+ int numInst;
+
+ /** Source of possible stalls. */
+ struct Stalls {
+ bool decode;
+ bool rename;
+ bool iew;
+ bool commit;
+ };
+
+ /** Tracks which stages are telling fetch to stall. */
+ Stalls stalls[Impl::MaxThreads];
/** Decode to fetch delay, in ticks. */
unsigned decodeToFetchDelay;
@@ -201,23 +349,63 @@ class SimpleFetch
Addr cacheBlkMask;
/** The cache line being fetched. */
- uint8_t *cacheData;
+ uint8_t *cacheData[Impl::MaxThreads];
/** Size of instructions. */
int instSize;
/** Icache stall statistics. */
- Counter lastIcacheStall;
+ Counter lastIcacheStall[Impl::MaxThreads];
+
+ /** List of Active Threads */
+ std::list<unsigned> *activeThreads;
+
+ /** Number of threads. */
+ unsigned numThreads;
+
+ /** Number of threads that are actively fetching. */
+ unsigned numFetchingThreads;
+ /** Thread ID being fetched. */
+ int threadFetched;
+
+ bool interruptPending;
+
+ bool switchedOut;
+
+#if !FULL_SYSTEM
+ /** Page table pointer. */
+// PageTable *pTable;
+#endif
+
+ // @todo: Consider making these vectors and tracking on a per thread basis.
+ /** Stat for total number of cycles stalled due to an icache miss. */
Stats::Scalar<> icacheStallCycles;
+ /** Stat for total number of fetched instructions. */
Stats::Scalar<> fetchedInsts;
+ Stats::Scalar<> fetchedBranches;
+ /** Stat for total number of predicted branches. */
Stats::Scalar<> predictedBranches;
+ /** Stat for total number of cycles spent fetching. */
Stats::Scalar<> fetchCycles;
+ /** Stat for total number of cycles spent squashing. */
Stats::Scalar<> fetchSquashCycles;
+ /** Stat for total number of cycles spent blocked due to other stages in
+ * the pipeline.
+ */
+ Stats::Scalar<> fetchIdleCycles;
Stats::Scalar<> fetchBlockedCycles;
+
+ Stats::Scalar<> fetchMiscStallCycles;
+ /** Stat for total number of fetched cache lines. */
Stats::Scalar<> fetchedCacheLines;
- Stats::Distribution<> fetch_nisn_dist;
+ Stats::Scalar<> fetchIcacheSquashes;
+ /** Distribution of number of instructions fetched each cycle. */
+ Stats::Distribution<> fetchNisnDist;
+ Stats::Formula idleRate;
+ Stats::Formula branchRate;
+ Stats::Formula fetchRate;
};
-#endif //__CPU_O3_CPU_SIMPLE_FETCH_HH__
+#endif //__CPU_O3_FETCH_HH__
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 8029fc732..1c5e508f6 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,66 +26,100 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-// Remove this later; used only for debugging.
-#define OPCODE(X) (X >> 26) & 0x3f
-
#include "arch/isa_traits.hh"
-#include "sim/byteswap.hh"
#include "cpu/exetrace.hh"
+#include "cpu/o3/fetch.hh"
#include "mem/base_mem.hh"
#include "mem/mem_interface.hh"
#include "mem/mem_req.hh"
-#include "cpu/o3/fetch.hh"
-
+#include "sim/byteswap.hh"
#include "sim/root.hh"
+#if FULL_SYSTEM
+#include "arch/tlb.hh"
+#include "arch/vtophys.hh"
+#include "base/remote_gdb.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
+#include "sim/system.hh"
+#else // !FULL_SYSTEM
+#include "mem/functional/functional.hh"
+#endif // FULL_SYSTEM
+
+#include <algorithm>
+
+using namespace std;
+
template<class Impl>
-SimpleFetch<Impl>::CacheCompletionEvent
-::CacheCompletionEvent(SimpleFetch *_fetch)
- : Event(&mainEventQueue),
+DefaultFetch<Impl>::CacheCompletionEvent::CacheCompletionEvent(MemReqPtr &_req,
+ DefaultFetch *_fetch)
+ : Event(&mainEventQueue, Delayed_Writeback_Pri),
+ req(_req),
fetch(_fetch)
{
+ this->setFlags(Event::AutoDelete);
}
template<class Impl>
void
-SimpleFetch<Impl>::CacheCompletionEvent::process()
+DefaultFetch<Impl>::CacheCompletionEvent::process()
{
- fetch->processCacheCompletion();
+ fetch->processCacheCompletion(req);
}
template<class Impl>
const char *
-SimpleFetch<Impl>::CacheCompletionEvent::description()
+DefaultFetch<Impl>::CacheCompletionEvent::description()
{
- return "SimpleFetch cache completion event";
+ return "DefaultFetch cache completion event";
}
template<class Impl>
-SimpleFetch<Impl>::SimpleFetch(Params &params)
- : icacheInterface(params.icacheInterface),
+DefaultFetch<Impl>::DefaultFetch(Params *params)
+ : icacheInterface(params->icacheInterface),
branchPred(params),
- decodeToFetchDelay(params.decodeToFetchDelay),
- renameToFetchDelay(params.renameToFetchDelay),
- iewToFetchDelay(params.iewToFetchDelay),
- commitToFetchDelay(params.commitToFetchDelay),
- fetchWidth(params.fetchWidth)
+ decodeToFetchDelay(params->decodeToFetchDelay),
+ renameToFetchDelay(params->renameToFetchDelay),
+ iewToFetchDelay(params->iewToFetchDelay),
+ commitToFetchDelay(params->commitToFetchDelay),
+ fetchWidth(params->fetchWidth),
+ numThreads(params->numberOfThreads),
+ numFetchingThreads(params->smtNumFetchingThreads),
+ interruptPending(false)
{
- DPRINTF(Fetch, "Fetch: Fetch constructor called\n");
-
- // Set status to idle.
- _status = Idle;
-
- // Create a new memory request.
- memReq = new MemReq();
- // Not sure of this parameter. I think it should be based on the
- // thread number.
-#if !FULL_SYSTEM
- memReq->asid = 0;
-#else
- memReq->asid = 0;
-#endif // FULL_SYSTEM
- memReq->data = new uint8_t[64];
+ if (numThreads > Impl::MaxThreads)
+ fatal("numThreads is not a valid value\n");
+
+ DPRINTF(Fetch, "Fetch constructor called\n");
+
+ // Set fetch stage's status to inactive.
+ _status = Inactive;
+
+ string policy = params->smtFetchPolicy;
+
+ // Convert string to lowercase
+ std::transform(policy.begin(), policy.end(), policy.begin(),
+ (int(*)(int)) tolower);
+
+ // Figure out fetch policy
+ if (policy == "singlethread") {
+ fetchPolicy = SingleThread;
+ } else if (policy == "roundrobin") {
+ fetchPolicy = RoundRobin;
+ DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
+ } else if (policy == "branch") {
+ fetchPolicy = Branch;
+ DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
+ } else if (policy == "iqcount") {
+ fetchPolicy = IQ;
+ DPRINTF(Fetch, "Fetch policy set to IQ count\n");
+ } else if (policy == "lsqcount") {
+ fetchPolicy = LSQ;
+ DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
+ } else {
+ fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
+ " RoundRobin,LSQcount,IQcount}\n");
+ }
// Size of cache block.
cacheBlkSize = icacheInterface ? icacheInterface->getBlockSize() : 64;
@@ -93,75 +127,142 @@ SimpleFetch<Impl>::SimpleFetch(Params &params)
// Create mask to get rid of offset bits.
cacheBlkMask = (cacheBlkSize - 1);
+ for (int tid=0; tid < numThreads; tid++) {
+
+ fetchStatus[tid] = Running;
+
+ priorityList.push_back(tid);
+
+ // Create a new memory request.
+ memReq[tid] = NULL;
+
+ // Create space to store a cache line.
+ cacheData[tid] = new uint8_t[cacheBlkSize];
+
+ stalls[tid].decode = 0;
+ stalls[tid].rename = 0;
+ stalls[tid].iew = 0;
+ stalls[tid].commit = 0;
+ }
+
// Get the size of an instruction.
instSize = sizeof(MachInst);
+}
- // Create space to store a cache line.
- cacheData = new uint8_t[cacheBlkSize];
+template <class Impl>
+std::string
+DefaultFetch<Impl>::name() const
+{
+ return cpu->name() + ".fetch";
}
template <class Impl>
void
-SimpleFetch<Impl>::regStats()
+DefaultFetch<Impl>::regStats()
{
icacheStallCycles
- .name(name() + ".icacheStallCycles")
+ .name(name() + ".FETCH:icacheStallCycles")
.desc("Number of cycles fetch is stalled on an Icache miss")
.prereq(icacheStallCycles);
fetchedInsts
- .name(name() + ".fetchedInsts")
+ .name(name() + ".FETCH:Insts")
.desc("Number of instructions fetch has processed")
.prereq(fetchedInsts);
+
+ fetchedBranches
+ .name(name() + ".FETCH:Branches")
+ .desc("Number of branches that fetch encountered")
+ .prereq(fetchedBranches);
+
predictedBranches
- .name(name() + ".predictedBranches")
+ .name(name() + ".FETCH:predictedBranches")
.desc("Number of branches that fetch has predicted taken")
.prereq(predictedBranches);
+
fetchCycles
- .name(name() + ".fetchCycles")
+ .name(name() + ".FETCH:Cycles")
.desc("Number of cycles fetch has run and was not squashing or"
" blocked")
.prereq(fetchCycles);
+
fetchSquashCycles
- .name(name() + ".fetchSquashCycles")
+ .name(name() + ".FETCH:SquashCycles")
.desc("Number of cycles fetch has spent squashing")
.prereq(fetchSquashCycles);
+
+ fetchIdleCycles
+ .name(name() + ".FETCH:IdleCycles")
+ .desc("Number of cycles fetch was idle")
+ .prereq(fetchIdleCycles);
+
fetchBlockedCycles
- .name(name() + ".fetchBlockedCycles")
+ .name(name() + ".FETCH:BlockedCycles")
.desc("Number of cycles fetch has spent blocked")
.prereq(fetchBlockedCycles);
+
fetchedCacheLines
- .name(name() + ".fetchedCacheLines")
+ .name(name() + ".FETCH:CacheLines")
.desc("Number of cache lines fetched")
.prereq(fetchedCacheLines);
- fetch_nisn_dist
+ fetchMiscStallCycles
+ .name(name() + ".FETCH:MiscStallCycles")
+ .desc("Number of cycles fetch has spent waiting on interrupts, or "
+ "bad addresses, or out of MSHRs")
+ .prereq(fetchMiscStallCycles);
+
+ fetchIcacheSquashes
+ .name(name() + ".FETCH:IcacheSquashes")
+ .desc("Number of outstanding Icache misses that were squashed")
+ .prereq(fetchIcacheSquashes);
+
+ fetchNisnDist
.init(/* base value */ 0,
/* last value */ fetchWidth,
/* bucket size */ 1)
- .name(name() + ".FETCH:rate_dist")
+ .name(name() + ".FETCH:rateDist")
.desc("Number of instructions fetched each cycle (Total)")
- .flags(Stats::pdf)
- ;
+ .flags(Stats::pdf);
+
+ idleRate
+ .name(name() + ".FETCH:idleRate")
+ .desc("Percent of cycles fetch was idle")
+ .prereq(idleRate);
+ idleRate = fetchIdleCycles * 100 / cpu->numCycles;
+
+ branchRate
+ .name(name() + ".FETCH:branchRate")
+ .desc("Number of branch fetches per cycle")
+ .flags(Stats::total);
+ branchRate = predictedBranches / cpu->numCycles;
+
+ fetchRate
+ .name(name() + ".FETCH:rate")
+ .desc("Number of inst fetches per cycle")
+ .flags(Stats::total);
+ fetchRate = fetchedInsts / cpu->numCycles;
branchPred.regStats();
}
template<class Impl>
void
-SimpleFetch<Impl>::setCPU(FullCPU *cpu_ptr)
+DefaultFetch<Impl>::setCPU(FullCPU *cpu_ptr)
{
- DPRINTF(Fetch, "Fetch: Setting the CPU pointer.\n");
+ DPRINTF(Fetch, "Setting the CPU pointer.\n");
cpu = cpu_ptr;
- // This line will be removed eventually.
- memReq->xc = cpu->xcBase();
+
+ // Fetch needs to start fetching instructions at the very beginning,
+ // so it must start up in active state.
+ switchToActive();
}
template<class Impl>
void
-SimpleFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
+DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
{
- DPRINTF(Fetch, "Fetch: Setting the time buffer pointer.\n");
+ DPRINTF(Fetch, "Setting the time buffer pointer.\n");
timeBuffer = time_buffer;
// Create wires to get information from proper places in time buffer.
@@ -173,32 +274,160 @@ SimpleFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
template<class Impl>
void
-SimpleFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
+DefaultFetch<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+{
+ DPRINTF(Fetch, "Setting active threads list pointer.\n");
+ activeThreads = at_ptr;
+}
+
+template<class Impl>
+void
+DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
{
- DPRINTF(Fetch, "Fetch: Setting the fetch queue pointer.\n");
+ DPRINTF(Fetch, "Setting the fetch queue pointer.\n");
fetchQueue = fq_ptr;
// Create wire to write information to proper place in fetch queue.
toDecode = fetchQueue->getWire(0);
}
+#if 0
+template<class Impl>
+void
+DefaultFetch<Impl>::setPageTable(PageTable *pt_ptr)
+{
+ DPRINTF(Fetch, "Setting the page table pointer.\n");
+#if !FULL_SYSTEM
+ pTable = pt_ptr;
+#endif
+}
+#endif
+
+template<class Impl>
+void
+DefaultFetch<Impl>::initStage()
+{
+ for (int tid = 0; tid < numThreads; tid++) {
+ PC[tid] = cpu->readPC(tid);
+ nextPC[tid] = cpu->readNextPC(tid);
+ }
+}
+
template<class Impl>
void
-SimpleFetch<Impl>::processCacheCompletion()
+DefaultFetch<Impl>::processCacheCompletion(MemReqPtr &req)
{
- DPRINTF(Fetch, "Fetch: Waking up from cache miss.\n");
+ unsigned tid = req->thread_num;
+
+ DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
// Only change the status if it's still waiting on the icache access
// to return.
// Can keep track of how many cache accesses go unused due to
// misspeculation here.
- if (_status == IcacheMissStall)
- _status = IcacheMissComplete;
+ if (fetchStatus[tid] != IcacheMissStall ||
+ req != memReq[tid] ||
+ isSwitchedOut()) {
+ ++fetchIcacheSquashes;
+ return;
+ }
+
+ // Wake up the CPU (if it went to sleep and was waiting on this completion
+ // event).
+ cpu->wakeCPU();
+
+ DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
+ tid);
+
+ switchToActive();
+
+ // Only switch to IcacheMissComplete if we're not stalled as well.
+ if (checkStall(tid)) {
+ fetchStatus[tid] = Blocked;
+ } else {
+ fetchStatus[tid] = IcacheMissComplete;
+ }
+
+// memcpy(cacheData[tid], memReq[tid]->data, memReq[tid]->size);
+
+ // Reset the mem req to NULL.
+ memReq[tid] = NULL;
+}
+
+template <class Impl>
+void
+DefaultFetch<Impl>::switchOut()
+{
+ switchedOut = true;
+ cpu->signalSwitched();
+}
+
+template <class Impl>
+void
+DefaultFetch<Impl>::doSwitchOut()
+{
+ branchPred.switchOut();
+}
+
+template <class Impl>
+void
+DefaultFetch<Impl>::takeOverFrom()
+{
+ // Reset all state
+ for (int i = 0; i < Impl::MaxThreads; ++i) {
+ stalls[i].decode = 0;
+ stalls[i].rename = 0;
+ stalls[i].iew = 0;
+ stalls[i].commit = 0;
+ PC[i] = cpu->readPC(i);
+ nextPC[i] = cpu->readNextPC(i);
+ fetchStatus[i] = Running;
+ }
+ numInst = 0;
+ wroteToTimeBuffer = false;
+ _status = Inactive;
+ switchedOut = false;
+ branchPred.takeOverFrom();
+}
+
+template <class Impl>
+void
+DefaultFetch<Impl>::wakeFromQuiesce()
+{
+ DPRINTF(Fetch, "Waking up from quiesce\n");
+ // Hopefully this is safe
+ fetchStatus[0] = Running;
+}
+
+template <class Impl>
+inline void
+DefaultFetch<Impl>::switchToActive()
+{
+ if (_status == Inactive) {
+ DPRINTF(Activity, "Activating stage.\n");
+
+ cpu->activateStage(FullCPU::FetchIdx);
+
+ _status = Active;
+ }
+}
+
+template <class Impl>
+inline void
+DefaultFetch<Impl>::switchToInactive()
+{
+ if (_status == Active) {
+ DPRINTF(Activity, "Deactivating stage.\n");
+
+ cpu->deactivateStage(FullCPU::FetchIdx);
+
+ _status = Inactive;
+ }
}
template <class Impl>
bool
-SimpleFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
+DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
{
// Do branch prediction check here.
// A bit of a misnomer...next_PC is actually the current PC until
@@ -211,7 +440,9 @@ SimpleFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
return false;
}
- predict_taken = branchPred.predict(inst, next_PC);
+ predict_taken = branchPred.predict(inst, next_PC, inst->threadNumber);
+
+ ++fetchedBranches;
if (predict_taken) {
++predictedBranches;
@@ -221,251 +452,429 @@ SimpleFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
}
template <class Impl>
-Fault
-SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
+bool
+DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
{
- // Check if the instruction exists within the cache.
- // If it does, then proceed on to read the instruction and the rest
- // of the instructions in the cache line until either the end of the
- // cache line or a predicted taken branch is encountered.
+ Fault fault = NoFault;
#if FULL_SYSTEM
// Flag to say whether or not address is physical addr.
- unsigned flags = cpu->inPalMode() ? PHYSICAL : 0;
+ unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0;
#else
unsigned flags = 0;
#endif // FULL_SYSTEM
- Fault fault = NoFault;
+ if (interruptPending && flags == 0 || switchedOut) {
+ // Hold off fetch from getting new instructions while an interrupt
+ // is pending.
+ return false;
+ }
// Align the fetch PC so it's at the start of a cache block.
fetch_PC = icacheBlockAlignPC(fetch_PC);
- // Setup the memReq to do a read of the first isntruction's address.
+ // Setup the memReq to do a read of the first instruction's address.
// Set the appropriate read size and flags as well.
- memReq->cmd = Read;
- memReq->reset(fetch_PC, cacheBlkSize, flags);
+ memReq[tid] = new MemReq();
- // Translate the instruction request.
- // Should this function be
- // in the CPU class ? Probably...ITB/DTB should exist within the
- // CPU.
+ memReq[tid]->asid = tid;
+ memReq[tid]->thread_num = tid;
+ memReq[tid]->data = new uint8_t[64];
+ memReq[tid]->xc = cpu->xcBase(tid);
+ memReq[tid]->cmd = Read;
+ memReq[tid]->reset(fetch_PC, cacheBlkSize, flags);
- fault = cpu->translateInstReq(memReq);
+ // Translate the instruction request.
+//#if FULL_SYSTEM
+ fault = cpu->translateInstReq(memReq[tid]);
+//#else
+// fault = pTable->translate(memReq[tid]);
+//#endif
// In the case of faults, the fetch stage may need to stall and wait
- // on what caused the fetch (ITB or Icache miss).
+ // for the ITB miss to be handled.
// If translation was successful, attempt to read the first
// instruction.
if (fault == NoFault) {
+#if FULL_SYSTEM
+ if (cpu->system->memctrl->badaddr(memReq[tid]->paddr) ||
+ memReq[tid]->flags & UNCACHEABLE) {
+ DPRINTF(Fetch, "Fetch: Bad address %#x (hopefully on a "
+ "misspeculating path)!",
+ memReq[tid]->paddr);
+ ret_fault = TheISA::genMachineCheckFault();
+ return false;
+ }
+#endif
+
DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
- fault = cpu->mem->read(memReq, cacheData);
+ fault = cpu->mem->read(memReq[tid], cacheData[tid]);
// This read may change when the mem interface changes.
- fetchedCacheLines++;
- }
+ // Now do the timing access to see whether or not the instruction
+ // exists within the cache.
+ if (icacheInterface && !icacheInterface->isBlocked()) {
+ DPRINTF(Fetch, "Doing cache access.\n");
- // Now do the timing access to see whether or not the instruction
- // exists within the cache.
- if (icacheInterface && fault == NoFault) {
- DPRINTF(Fetch, "Fetch: Doing timing memory access.\n");
- memReq->completionEvent = NULL;
+ memReq[tid]->completionEvent = NULL;
- memReq->time = curTick;
+ memReq[tid]->time = curTick;
- MemAccessResult result = icacheInterface->access(memReq);
+ MemAccessResult result = icacheInterface->access(memReq[tid]);
- // If the cache missed (in this model functional and timing
- // memories are different), then schedule an event to wake
- // up this stage once the cache miss completes.
- if (result != MA_HIT && icacheInterface->doEvents()) {
- memReq->completionEvent = new CacheCompletionEvent(this);
+ fetchedCacheLines++;
- // How does current model work as far as individual
- // stages scheduling/unscheduling?
- // Perhaps have only the main CPU scheduled/unscheduled,
- // and have it choose what stages to run appropriately.
+ // If the cache missed, then schedule an event to wake
+ // up this stage once the cache miss completes.
+ // @todo: Possibly allow for longer than 1 cycle cache hits.
+ if (result != MA_HIT && icacheInterface->doEvents()) {
- DPRINTF(Fetch, "Fetch: Stalling due to icache miss.\n");
- _status = IcacheMissStall;
+ memReq[tid]->completionEvent =
+ new CacheCompletionEvent(memReq[tid], this);
+
+ lastIcacheStall[tid] = curTick;
+
+ DPRINTF(Activity, "[tid:%i]: Activity: Stalling due to I-cache "
+ "miss.\n", tid);
+
+ fetchStatus[tid] = IcacheMissStall;
+ } else {
+ DPRINTF(Fetch, "[tid:%i]: I-Cache hit. Doing Instruction "
+ "read.\n", tid);
+
+// memcpy(cacheData[tid], memReq[tid]->data, memReq[tid]->size);
+ }
+ } else {
+ DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
+ ret_fault = NoFault;
+ return false;
}
}
- return fault;
+ ret_fault = fault;
+ return true;
}
template <class Impl>
inline void
-SimpleFetch<Impl>::doSquash(const Addr &new_PC)
+DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid)
{
- DPRINTF(Fetch, "Fetch: Squashing, setting PC to: %#x.\n", new_PC);
+ DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x.\n",
+ tid, new_PC);
- cpu->setNextPC(new_PC + instSize);
- cpu->setPC(new_PC);
+ PC[tid] = new_PC;
+ nextPC[tid] = new_PC + instSize;
// Clear the icache miss if it's outstanding.
- if (_status == IcacheMissStall && icacheInterface) {
- DPRINTF(Fetch, "Fetch: Squashing outstanding Icache miss.\n");
- // @todo: Use an actual thread number here.
- icacheInterface->squash(0);
+ if (fetchStatus[tid] == IcacheMissStall && icacheInterface) {
+ DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
+ tid);
+ memReq[tid] = NULL;
}
- _status = Squashing;
+ fetchStatus[tid] = Squashing;
++fetchSquashCycles;
}
template<class Impl>
void
-SimpleFetch<Impl>::squashFromDecode(const Addr &new_PC,
- const InstSeqNum &seq_num)
+DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC,
+ const InstSeqNum &seq_num,
+ unsigned tid)
{
- DPRINTF(Fetch, "Fetch: Squashing from decode.\n");
+ DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
- doSquash(new_PC);
+ doSquash(new_PC, tid);
// Tell the CPU to remove any instructions that are in flight between
// fetch and decode.
- cpu->removeInstsUntil(seq_num);
+ cpu->removeInstsUntil(seq_num, tid);
+}
+
+template<class Impl>
+bool
+DefaultFetch<Impl>::checkStall(unsigned tid) const
+{
+ bool ret_val = false;
+
+ if (cpu->contextSwitch) {
+ DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
+ ret_val = true;
+ } else if (stalls[tid].decode) {
+ DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
+ ret_val = true;
+ } else if (stalls[tid].rename) {
+ DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
+ ret_val = true;
+ } else if (stalls[tid].iew) {
+ DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
+ ret_val = true;
+ } else if (stalls[tid].commit) {
+ DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
+ ret_val = true;
+ }
+
+ return ret_val;
+}
+
+template<class Impl>
+typename DefaultFetch<Impl>::FetchStatus
+DefaultFetch<Impl>::updateFetchStatus()
+{
+ //Check Running
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+
+ unsigned tid = *threads++;
+
+ if (fetchStatus[tid] == Running ||
+ fetchStatus[tid] == Squashing ||
+ fetchStatus[tid] == IcacheMissComplete) {
+
+ if (_status == Inactive) {
+ DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
+
+ if (fetchStatus[tid] == IcacheMissComplete) {
+ DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
+ "completion\n",tid);
+ }
+
+ cpu->activateStage(FullCPU::FetchIdx);
+ }
+
+ return Active;
+ }
+ }
+
+ // Stage is switching from active to inactive, notify CPU of it.
+ if (_status == Active) {
+ DPRINTF(Activity, "Deactivating stage.\n");
+
+ cpu->deactivateStage(FullCPU::FetchIdx);
+ }
+
+ return Inactive;
}
template <class Impl>
void
-SimpleFetch<Impl>::squash(const Addr &new_PC)
+DefaultFetch<Impl>::squash(const Addr &new_PC, unsigned tid)
{
- DPRINTF(Fetch, "Fetch: Squash from commit.\n");
+ DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
- doSquash(new_PC);
+ doSquash(new_PC, tid);
// Tell the CPU to remove any instructions that are not in the ROB.
- cpu->removeInstsNotInROB();
+ cpu->removeInstsNotInROB(tid);
}
-template<class Impl>
+template <class Impl>
void
-SimpleFetch<Impl>::tick()
+DefaultFetch<Impl>::tick()
{
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+ bool status_change = false;
+
+ wroteToTimeBuffer = false;
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ // Check the signals for each thread to determine the proper status
+ // for each thread.
+ bool updated_status = checkSignalsAndUpdate(tid);
+ status_change = status_change || updated_status;
+ }
+
+ DPRINTF(Fetch, "Running stage.\n");
+
+ // Reset the number of the instruction we're fetching.
+ numInst = 0;
+
+ if (fromCommit->commitInfo[0].interruptPending) {
+ interruptPending = true;
+ }
+ if (fromCommit->commitInfo[0].clearInterrupt) {
+ interruptPending = false;
+ }
+
+ for (threadFetched = 0; threadFetched < numFetchingThreads;
+ threadFetched++) {
+ // Fetch each of the actively fetching threads.
+ fetch(status_change);
+ }
+
+ // Record number of instructions fetched this cycle for distribution.
+ fetchNisnDist.sample(numInst);
+
+ if (status_change) {
+ // Change the fetch stage status if there was a status change.
+ _status = updateFetchStatus();
+ }
+
+ // If there was activity this cycle, inform the CPU of it.
+ if (wroteToTimeBuffer || cpu->contextSwitch) {
+ DPRINTF(Activity, "Activity this cycle.\n");
+
+ cpu->activityThisCycle();
+ }
+}
+
+template <class Impl>
+bool
+DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
+{
+ // Update the per thread stall statuses.
+ if (fromDecode->decodeBlock[tid]) {
+ stalls[tid].decode = true;
+ }
+
+ if (fromDecode->decodeUnblock[tid]) {
+ assert(stalls[tid].decode);
+ assert(!fromDecode->decodeBlock[tid]);
+ stalls[tid].decode = false;
+ }
+
+ if (fromRename->renameBlock[tid]) {
+ stalls[tid].rename = true;
+ }
+
+ if (fromRename->renameUnblock[tid]) {
+ assert(stalls[tid].rename);
+ assert(!fromRename->renameBlock[tid]);
+ stalls[tid].rename = false;
+ }
+
+ if (fromIEW->iewBlock[tid]) {
+ stalls[tid].iew = true;
+ }
+
+ if (fromIEW->iewUnblock[tid]) {
+ assert(stalls[tid].iew);
+ assert(!fromIEW->iewBlock[tid]);
+ stalls[tid].iew = false;
+ }
+
+ if (fromCommit->commitBlock[tid]) {
+ stalls[tid].commit = true;
+ }
+
+ if (fromCommit->commitUnblock[tid]) {
+ assert(stalls[tid].commit);
+ assert(!fromCommit->commitBlock[tid]);
+ stalls[tid].commit = false;
+ }
+
// Check squash signals from commit.
- if (fromCommit->commitInfo.squash) {
- DPRINTF(Fetch, "Fetch: Squashing instructions due to squash "
- "from commit.\n");
+ if (fromCommit->commitInfo[tid].squash) {
+
+ DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
+ "from commit.\n",tid);
// In any case, squash.
- squash(fromCommit->commitInfo.nextPC);
+ squash(fromCommit->commitInfo[tid].nextPC,tid);
// Also check if there's a mispredict that happened.
- if (fromCommit->commitInfo.branchMispredict) {
- branchPred.squash(fromCommit->commitInfo.doneSeqNum,
- fromCommit->commitInfo.nextPC,
- fromCommit->commitInfo.branchTaken);
+ if (fromCommit->commitInfo[tid].branchMispredict) {
+ branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
+ fromCommit->commitInfo[tid].nextPC,
+ fromCommit->commitInfo[tid].branchTaken,
+ tid);
} else {
- branchPred.squash(fromCommit->commitInfo.doneSeqNum);
+ branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
+ tid);
}
- return;
- } else if (fromCommit->commitInfo.doneSeqNum) {
+ return true;
+ } else if (fromCommit->commitInfo[tid].doneSeqNum) {
// Update the branch predictor if it wasn't a squashed instruction
- // that was braodcasted.
- branchPred.update(fromCommit->commitInfo.doneSeqNum);
+ // that was broadcasted.
+ branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
}
// Check ROB squash signals from commit.
- if (fromCommit->commitInfo.robSquashing) {
- DPRINTF(Fetch, "Fetch: ROB is still squashing.\n");
+ if (fromCommit->commitInfo[tid].robSquashing) {
+ DPRINTF(Fetch, "[tid:%u]: ROB is still squashing Thread %u.\n", tid);
// Continue to squash.
- _status = Squashing;
+ fetchStatus[tid] = Squashing;
- ++fetchSquashCycles;
- return;
+ return true;
}
// Check squash signals from decode.
- if (fromDecode->decodeInfo.squash) {
- DPRINTF(Fetch, "Fetch: Squashing instructions due to squash "
- "from decode.\n");
+ if (fromDecode->decodeInfo[tid].squash) {
+ DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
+ "from decode.\n",tid);
// Update the branch predictor.
- if (fromDecode->decodeInfo.branchMispredict) {
- branchPred.squash(fromDecode->decodeInfo.doneSeqNum,
- fromDecode->decodeInfo.nextPC,
- fromDecode->decodeInfo.branchTaken);
+ if (fromDecode->decodeInfo[tid].branchMispredict) {
+ branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
+ fromDecode->decodeInfo[tid].nextPC,
+ fromDecode->decodeInfo[tid].branchTaken,
+ tid);
} else {
- branchPred.squash(fromDecode->decodeInfo.doneSeqNum);
+ branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
+ tid);
}
- if (_status != Squashing) {
- // Squash unless we're already squashing?
- squashFromDecode(fromDecode->decodeInfo.nextPC,
- fromDecode->decodeInfo.doneSeqNum);
- return;
+ if (fetchStatus[tid] != Squashing) {
+ // Squash unless we're already squashing
+ squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
+ fromDecode->decodeInfo[tid].doneSeqNum,
+ tid);
+
+ return true;
}
}
- // Check if any of the stall signals are high.
- if (fromDecode->decodeInfo.stall ||
- fromRename->renameInfo.stall ||
- fromIEW->iewInfo.stall ||
- fromCommit->commitInfo.stall)
- {
- // Block stage, regardless of current status.
+ if (checkStall(tid) && fetchStatus[tid] != IcacheMissStall) {
+ DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
- DPRINTF(Fetch, "Fetch: Stalling stage.\n");
- DPRINTF(Fetch, "Fetch: Statuses: Decode: %i Rename: %i IEW: %i "
- "Commit: %i\n",
- fromDecode->decodeInfo.stall,
- fromRename->renameInfo.stall,
- fromIEW->iewInfo.stall,
- fromCommit->commitInfo.stall);
+ fetchStatus[tid] = Blocked;
- _status = Blocked;
-
- ++fetchBlockedCycles;
- return;
- } else if (_status == Blocked) {
- // Unblock stage if status is currently blocked and none of the
- // stall signals are being held high.
- _status = Running;
-
- ++fetchBlockedCycles;
- return;
+ return true;
}
- // If fetch has reached this point, then there are no squash signals
- // still being held high. Check if fetch is in the squashing state;
- // if so, fetch can switch to running.
- // Similarly, there are no blocked signals still being held high.
- // Check if fetch is in the blocked state; if so, fetch can switch to
- // running.
- if (_status == Squashing) {
- DPRINTF(Fetch, "Fetch: Done squashing, switching to running.\n");
-
- // Switch status to running
- _status = Running;
+ if (fetchStatus[tid] == Blocked ||
+ fetchStatus[tid] == Squashing) {
+ // Switch status to running if fetch isn't being told to block or
+ // squash this cycle.
+ DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
+ tid);
- ++fetchCycles;
+ fetchStatus[tid] = Running;
- fetch();
- } else if (_status != IcacheMissStall) {
- DPRINTF(Fetch, "Fetch: Running stage.\n");
-
- ++fetchCycles;
-
- fetch();
+ return true;
}
+
+ // If we've reached this point, we have not gotten any signals that
+ // cause fetch to change its status. Fetch remains the same as before.
+ return false;
}
template<class Impl>
void
-SimpleFetch<Impl>::fetch()
+DefaultFetch<Impl>::fetch(bool &status_change)
{
//////////////////////////////////////////
// Start actual fetch
//////////////////////////////////////////
+ int tid = getFetchingThread(fetchPolicy);
+
+ if (tid == -1) {
+ DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
+
+ // Breaks looping condition in tick()
+ threadFetched = numFetchingThreads;
+ return;
+ }
// The current PC.
- Addr fetch_PC = cpu->readPC();
+ Addr &fetch_PC = PC[tid];
// Fault code for memory access.
Fault fault = NoFault;
@@ -473,60 +882,71 @@ SimpleFetch<Impl>::fetch()
// If returning from the delay of a cache miss, then update the status
// to running, otherwise do the cache access. Possibly move this up
// to tick() function.
- if (_status == IcacheMissComplete) {
- DPRINTF(Fetch, "Fetch: Icache miss is complete.\n");
-
- // Reset the completion event to NULL.
- memReq->completionEvent = NULL;
-
- _status = Running;
+ if (fetchStatus[tid] == IcacheMissComplete) {
+ DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n",
+ tid);
+
+ fetchStatus[tid] = Running;
+ status_change = true;
+ } else if (fetchStatus[tid] == Running) {
+ DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
+ "instruction, starting at PC %08p.\n",
+ tid, fetch_PC);
+
+ bool fetch_success = fetchCacheLine(fetch_PC, fault, tid);
+ if (!fetch_success) {
+ ++fetchMiscStallCycles;
+ return;
+ }
} else {
- DPRINTF(Fetch, "Fetch: Attempting to translate and read "
- "instruction, starting at PC %08p.\n",
- fetch_PC);
+ if (fetchStatus[tid] == Idle) {
+ ++fetchIdleCycles;
+ } else if (fetchStatus[tid] == Blocked) {
+ ++fetchBlockedCycles;
+ } else if (fetchStatus[tid] == Squashing) {
+ ++fetchSquashCycles;
+ } else if (fetchStatus[tid] == IcacheMissStall) {
+ ++icacheStallCycles;
+ }
- fault = fetchCacheLine(fetch_PC);
+ // Status is Idle, Squashing, Blocked, or IcacheMissStall, so
+ // fetch should do nothing.
+ return;
}
- // If we had a stall due to an icache miss, then return. It'd
- // be nicer if this were handled through the kind of fault that
- // is returned by the function.
- if (_status == IcacheMissStall) {
+ ++fetchCycles;
+
+ // If we had a stall due to an icache miss, then return.
+ if (fetchStatus[tid] == IcacheMissStall) {
+ ++icacheStallCycles;
+ status_change = true;
return;
}
- // As far as timing goes, the CPU will need to send an event through
- // the MemReq in order to be woken up once the memory access completes.
- // Probably have a status on a per thread basis so each thread can
- // block independently and be woken up independently.
-
Addr next_PC = fetch_PC;
InstSeqNum inst_seq;
MachInst inst;
- unsigned offset = fetch_PC & cacheBlkMask;
- unsigned fetched;
+ ExtMachInst ext_inst;
+ // @todo: Fix this hack.
+ unsigned offset = (fetch_PC & cacheBlkMask) & ~3;
if (fault == NoFault) {
// If the read of the first instruction was successful, then grab the
// instructions from the rest of the cache line and put them into the
// queue heading to decode.
- DPRINTF(Fetch, "Fetch: Adding instructions to queue to decode.\n");
-
- //////////////////////////
- // Fetch first instruction
- //////////////////////////
+ DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
+ "decode.\n",tid);
// Need to keep track of whether or not a predicted branch
// ended this fetch block.
bool predicted_branch = false;
- for (fetched = 0;
+ for (;
offset < cacheBlkSize &&
- fetched < fetchWidth &&
+ numInst < fetchWidth &&
!predicted_branch;
- ++fetched)
- {
+ ++numInst) {
// Get a sequence number.
inst_seq = cpu->getAndIncrementInstSeq();
@@ -536,31 +956,40 @@ SimpleFetch<Impl>::fetch()
// Get the instruction from the array of the cache line.
inst = gtoh(*reinterpret_cast<MachInst *>
- (&cacheData[offset]));
+ (&cacheData[tid][offset]));
+
+ ext_inst = TheISA::makeExtMI(inst, fetch_PC);
// Create a new DynInst from the instruction fetched.
- DynInstPtr instruction = new DynInst(inst, fetch_PC, next_PC,
+ DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
+ next_PC,
inst_seq, cpu);
+ instruction->setThread(tid);
+
+ instruction->setASID(tid);
- DPRINTF(Fetch, "Fetch: Instruction %i created, with PC %#x\n",
- inst_seq, instruction->readPC());
+ instruction->setState(cpu->thread[tid]);
- DPRINTF(Fetch, "Fetch: Instruction opcode is: %03p\n",
- OPCODE(inst));
+ DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x created "
+ "[sn:%lli]\n",
+ tid, instruction->readPC(), inst_seq);
+
+ DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n",
+ tid, instruction->staticInst->disassemble(fetch_PC));
instruction->traceData =
- Trace::getInstRecord(curTick, cpu->xcBase(), cpu,
+ Trace::getInstRecord(curTick, cpu->xcBase(tid), cpu,
instruction->staticInst,
- instruction->readPC(), 0);
+ instruction->readPC(),tid);
predicted_branch = lookupAndUpdateNextPC(instruction, next_PC);
// Add instruction to the CPU's list of instructions.
- cpu->addInst(instruction);
+ instruction->setInstListIt(cpu->addInst(instruction));
// Write the instruction to the first slot in the queue
// that heads to decode.
- toDecode->insts[fetched] = instruction;
+ toDecode->insts[numInst] = instruction;
toDecode->size++;
@@ -570,48 +999,221 @@ SimpleFetch<Impl>::fetch()
// Move to the next instruction, unless we have a branch.
fetch_PC = next_PC;
+ if (instruction->isQuiesce()) {
+ warn("%lli: Quiesce instruction encountered, halting fetch!",
+ curTick);
+ fetchStatus[tid] = QuiescePending;
+ ++numInst;
+ status_change = true;
+ break;
+ }
+
offset+= instSize;
}
+ }
- fetch_nisn_dist.sample(fetched);
+ if (numInst > 0) {
+ wroteToTimeBuffer = true;
}
// Now that fetching is completed, update the PC to signify what the next
- // cycle will be. Might want to move this to the beginning of this
- // function so that the PC updates at the beginning of everything.
- // Or might want to leave setting the PC to the main CPU, with fetch
- // only changing the nextPC (will require correct determination of
- // next PC).
+ // cycle will be.
if (fault == NoFault) {
- DPRINTF(Fetch, "Fetch: Setting PC to %08p.\n", next_PC);
- cpu->setPC(next_PC);
- cpu->setNextPC(next_PC + instSize);
+ DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
+
+ PC[tid] = next_PC;
+ nextPC[tid] = next_PC + instSize;
} else {
- // If the issue was an icache miss, then we can just return and
- // wait until it is handled.
- if (_status == IcacheMissStall) {
- return;
+ // We shouldn't be in an icache miss and also have a fault (an ITB
+ // miss)
+ if (fetchStatus[tid] == IcacheMissStall) {
+ panic("Fetch should have exited prior to this!");
}
- // Handle the fault.
- // This stage will not be able to continue until all the ROB
- // slots are empty, at which point the fault can be handled.
- // The only other way it can wake up is if a squash comes along
- // and changes the PC. Not sure how to handle that case...perhaps
- // have it handled by the upper level CPU class which peeks into the
- // time buffer and sees if a squash comes along, in which case it
- // changes the status.
+ // Send the fault to commit. This thread will not do anything
+ // until commit handles the fault. The only other way it can
+ // wake up is if a squash comes along and changes the PC.
+#if FULL_SYSTEM
+ assert(numInst != fetchWidth);
+ // Get a sequence number.
+ inst_seq = cpu->getAndIncrementInstSeq();
+ // We will use a nop in order to carry the fault.
+ ext_inst = TheISA::NoopMachInst;
- DPRINTF(Fetch, "Fetch: Blocked, need to handle the trap.\n");
+ // Create a new DynInst from the dummy nop.
+ DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
+ next_PC,
+ inst_seq, cpu);
+ instruction->setPredTarg(next_PC + instSize);
+ instruction->setThread(tid);
- _status = Blocked;
-#if FULL_SYSTEM
-// cpu->trap(fault);
- // Send a signal to the ROB indicating that there's a trap from the
- // fetch stage that needs to be handled. Need to indicate that
- // there's a fault, and the fault type.
+ instruction->setASID(tid);
+
+ instruction->setState(cpu->thread[tid]);
+
+ instruction->traceData = NULL;
+
+ instruction->setInstListIt(cpu->addInst(instruction));
+
+ instruction->fault = fault;
+
+ toDecode->insts[numInst] = instruction;
+ toDecode->size++;
+
+ DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n",tid);
+
+ fetchStatus[tid] = TrapPending;
+ status_change = true;
+
+ warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
#else // !FULL_SYSTEM
- fatal("fault (%d) detected @ PC %08p", fault, cpu->readPC());
+ fatal("fault (%d) detected @ PC %08p", fault, PC[tid]);
#endif // FULL_SYSTEM
}
}
+
+
+///////////////////////////////////////
+// //
+// SMT FETCH POLICY MAINTAINED HERE //
+// //
+///////////////////////////////////////
+template<class Impl>
+int
+DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
+{
+ if (numThreads > 1) {
+ switch (fetch_priority) {
+
+ case SingleThread:
+ return 0;
+
+ case RoundRobin:
+ return roundRobin();
+
+ case IQ:
+ return iqCount();
+
+ case LSQ:
+ return lsqCount();
+
+ case Branch:
+ return branchCount();
+
+ default:
+ return -1;
+ }
+ } else {
+ int tid = *((*activeThreads).begin());
+
+ if (fetchStatus[tid] == Running ||
+ fetchStatus[tid] == IcacheMissComplete ||
+ fetchStatus[tid] == Idle) {
+ return tid;
+ } else {
+ return -1;
+ }
+ }
+
+}
+
+
+template<class Impl>
+int
+DefaultFetch<Impl>::roundRobin()
+{
+ list<unsigned>::iterator pri_iter = priorityList.begin();
+ list<unsigned>::iterator end = priorityList.end();
+
+ int high_pri;
+
+ while (pri_iter != end) {
+ high_pri = *pri_iter;
+
+ assert(high_pri <= numThreads);
+
+ if (fetchStatus[high_pri] == Running ||
+ fetchStatus[high_pri] == IcacheMissComplete ||
+ fetchStatus[high_pri] == Idle) {
+
+ priorityList.erase(pri_iter);
+ priorityList.push_back(high_pri);
+
+ return high_pri;
+ }
+
+ pri_iter++;
+ }
+
+ return -1;
+}
+
+template<class Impl>
+int
+DefaultFetch<Impl>::iqCount()
+{
+ priority_queue<unsigned> PQ;
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ PQ.push(fromIEW->iewInfo[tid].iqCount);
+ }
+
+ while (!PQ.empty()) {
+
+ unsigned high_pri = PQ.top();
+
+ if (fetchStatus[high_pri] == Running ||
+ fetchStatus[high_pri] == IcacheMissComplete ||
+ fetchStatus[high_pri] == Idle)
+ return high_pri;
+ else
+ PQ.pop();
+
+ }
+
+ return -1;
+}
+
+template<class Impl>
+int
+DefaultFetch<Impl>::lsqCount()
+{
+ priority_queue<unsigned> PQ;
+
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ PQ.push(fromIEW->iewInfo[tid].ldstqCount);
+ }
+
+ while (!PQ.empty()) {
+
+ unsigned high_pri = PQ.top();
+
+ if (fetchStatus[high_pri] == Running ||
+ fetchStatus[high_pri] == IcacheMissComplete ||
+ fetchStatus[high_pri] == Idle)
+ return high_pri;
+ else
+ PQ.pop();
+
+ }
+
+ return -1;
+}
+
+template<class Impl>
+int
+DefaultFetch<Impl>::branchCount()
+{
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ return *threads;
+}
diff --git a/src/cpu/o3/free_list.cc b/src/cpu/o3/free_list.cc
index 6f0b4be1e..bd0f4f034 100644
--- a/src/cpu/o3/free_list.cc
+++ b/src/cpu/o3/free_list.cc
@@ -30,7 +30,8 @@
#include "cpu/o3/free_list.hh"
-SimpleFreeList::SimpleFreeList(unsigned _numLogicalIntRegs,
+SimpleFreeList::SimpleFreeList(unsigned activeThreads,
+ unsigned _numLogicalIntRegs,
unsigned _numPhysicalIntRegs,
unsigned _numLogicalFloatRegs,
unsigned _numPhysicalFloatRegs)
@@ -40,43 +41,30 @@ SimpleFreeList::SimpleFreeList(unsigned _numLogicalIntRegs,
numPhysicalFloatRegs(_numPhysicalFloatRegs),
numPhysicalRegs(numPhysicalIntRegs + numPhysicalFloatRegs)
{
- DPRINTF(FreeList, "FreeList: Creating new free list object.\n");
-
- // DEBUG stuff.
- freeIntRegsScoreboard.resize(numPhysicalIntRegs);
-
- freeFloatRegsScoreboard.resize(numPhysicalRegs);
-
- for (PhysRegIndex i = 0; i < numLogicalIntRegs; ++i) {
- freeIntRegsScoreboard[i] = 0;
- }
+ DPRINTF(FreeList, "Creating new free list object.\n");
// Put all of the extra physical registers onto the free list. This
// means excluding all of the base logical registers.
- for (PhysRegIndex i = numLogicalIntRegs;
+ for (PhysRegIndex i = numLogicalIntRegs * activeThreads;
i < numPhysicalIntRegs; ++i)
{
freeIntRegs.push(i);
-
- freeIntRegsScoreboard[i] = 1;
- }
-
- for (PhysRegIndex i = 0; i < numPhysicalIntRegs + numLogicalFloatRegs;
- ++i)
- {
- freeFloatRegsScoreboard[i] = 0;
}
// Put all of the extra physical registers onto the free list. This
// means excluding all of the base logical registers. Because the
// float registers' indices start where the physical registers end,
// some math must be done to determine where the free registers start.
- for (PhysRegIndex i = numPhysicalIntRegs + numLogicalFloatRegs;
- i < numPhysicalRegs; ++i)
+ PhysRegIndex i = numPhysicalIntRegs + (numLogicalFloatRegs * activeThreads);
+
+ for ( ; i < numPhysicalRegs; ++i)
{
freeFloatRegs.push(i);
-
- freeFloatRegsScoreboard[i] = 1;
}
}
+std::string
+SimpleFreeList::name() const
+{
+ return "cpu.freelist";
+}
diff --git a/src/cpu/o3/free_list.hh b/src/cpu/o3/free_list.hh
index 0b85dba1e..29e84cd44 100644
--- a/src/cpu/o3/free_list.hh
+++ b/src/cpu/o3/free_list.hh
@@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_FREE_LIST_HH__
-#define __CPU_O3_CPU_FREE_LIST_HH__
+#ifndef __CPU_O3_FREE_LIST_HH__
+#define __CPU_O3_FREE_LIST_HH__
#include <iostream>
#include <queue>
@@ -45,10 +45,9 @@
* other classes, it assumes that the indices for the floating point
* registers starts after the integer registers end. Hence the variable
* numPhysicalIntRegs is logically equivalent to the baseFP dependency.
- * Note that
- * while this most likely should be called FreeList, the name "FreeList"
- * is used in a typedef within the CPU Policy, and therefore no class
- * can be named simply "FreeList".
+ * Note that while this most likely should be called FreeList, the name
+ * "FreeList" is used in a typedef within the CPU Policy, and therefore no
+ * class can be named simply "FreeList".
* @todo: Give a better name to the base FP dependency.
*/
class SimpleFreeList
@@ -75,36 +74,51 @@ class SimpleFreeList
/** Total number of physical registers. */
int numPhysicalRegs;
- /** DEBUG stuff below. */
- std::vector<int> freeIntRegsScoreboard;
-
- std::vector<bool> freeFloatRegsScoreboard;
-
public:
- SimpleFreeList(unsigned _numLogicalIntRegs,
+ /** Constructs a free list.
+ * @param activeThreads Number of active threads.
+ * @param _numLogicalIntRegs Number of logical integer registers.
+ * @param _numPhysicalIntRegs Number of physical integer registers.
+ * @param _numLogicalFloatRegs Number of logical fp registers.
+ * @param _numPhysicalFloatRegs Number of physical fp registers.
+ */
+ SimpleFreeList(unsigned activeThreads,
+ unsigned _numLogicalIntRegs,
unsigned _numPhysicalIntRegs,
unsigned _numLogicalFloatRegs,
unsigned _numPhysicalFloatRegs);
+ /** Gives the name of the freelist. */
+ std::string name() const;
+
+ /** Gets a free integer register. */
inline PhysRegIndex getIntReg();
+ /** Gets a free fp register. */
inline PhysRegIndex getFloatReg();
+ /** Adds a register back to the free list. */
inline void addReg(PhysRegIndex freed_reg);
+ /** Adds an integer register back to the free list. */
inline void addIntReg(PhysRegIndex freed_reg);
+ /** Adds a fp register back to the free list. */
inline void addFloatReg(PhysRegIndex freed_reg);
+ /** Checks if there are any free integer registers. */
bool hasFreeIntRegs()
{ return !freeIntRegs.empty(); }
+ /** Checks if there are any free fp registers. */
bool hasFreeFloatRegs()
{ return !freeFloatRegs.empty(); }
+ /** Returns the number of free integer registers. */
int numFreeIntRegs()
{ return freeIntRegs.size(); }
+ /** Returns the number of free fp registers. */
int numFreeFloatRegs()
{ return freeFloatRegs.size(); }
};
@@ -112,7 +126,8 @@ class SimpleFreeList
inline PhysRegIndex
SimpleFreeList::getIntReg()
{
- DPRINTF(Rename, "FreeList: Trying to get free integer register.\n");
+ DPRINTF(FreeList, "Trying to get free integer register.\n");
+
if (freeIntRegs.empty()) {
panic("No free integer registers!");
}
@@ -121,17 +136,14 @@ SimpleFreeList::getIntReg()
freeIntRegs.pop();
- // DEBUG
- assert(freeIntRegsScoreboard[free_reg]);
- freeIntRegsScoreboard[free_reg] = 0;
-
return(free_reg);
}
inline PhysRegIndex
SimpleFreeList::getFloatReg()
{
- DPRINTF(Rename, "FreeList: Trying to get free float register.\n");
+ DPRINTF(FreeList, "Trying to get free float register.\n");
+
if (freeFloatRegs.empty()) {
panic("No free integer registers!");
}
@@ -140,42 +152,28 @@ SimpleFreeList::getFloatReg()
freeFloatRegs.pop();
- // DEBUG
- assert(freeFloatRegsScoreboard[free_reg]);
- freeFloatRegsScoreboard[free_reg] = 0;
-
return(free_reg);
}
inline void
SimpleFreeList::addReg(PhysRegIndex freed_reg)
{
- DPRINTF(Rename, "Freelist: Freeing register %i.\n", freed_reg);
+ DPRINTF(FreeList,"Freeing register %i.\n", freed_reg);
//Might want to add in a check for whether or not this register is
//already in there. A bit vector or something similar would be useful.
if (freed_reg < numPhysicalIntRegs) {
- freeIntRegs.push(freed_reg);
-
- // DEBUG
- assert(freeIntRegsScoreboard[freed_reg] == false);
- freeIntRegsScoreboard[freed_reg] = 1;
+ if (freed_reg != TheISA::ZeroReg)
+ freeIntRegs.push(freed_reg);
} else if (freed_reg < numPhysicalRegs) {
- freeFloatRegs.push(freed_reg);
-
- // DEBUG
- assert(freeFloatRegsScoreboard[freed_reg] == false);
- freeFloatRegsScoreboard[freed_reg] = 1;
+ if (freed_reg != (TheISA::ZeroReg + numPhysicalIntRegs))
+ freeFloatRegs.push(freed_reg);
}
}
inline void
SimpleFreeList::addIntReg(PhysRegIndex freed_reg)
{
- DPRINTF(Rename, "Freelist: Freeing int register %i.\n", freed_reg);
-
- // DEBUG
- assert(!freeIntRegsScoreboard[freed_reg]);
- freeIntRegsScoreboard[freed_reg] = 1;
+ DPRINTF(FreeList,"Freeing int register %i.\n", freed_reg);
freeIntRegs.push(freed_reg);
}
@@ -183,13 +181,9 @@ SimpleFreeList::addIntReg(PhysRegIndex freed_reg)
inline void
SimpleFreeList::addFloatReg(PhysRegIndex freed_reg)
{
- DPRINTF(Rename, "Freelist: Freeing float register %i.\n", freed_reg);
-
- // DEBUG
- assert(!freeFloatRegsScoreboard[freed_reg]);
- freeFloatRegsScoreboard[freed_reg] = 1;
+ DPRINTF(FreeList,"Freeing float register %i.\n", freed_reg);
freeFloatRegs.push(freed_reg);
}
-#endif // __CPU_O3_CPU_FREE_LIST_HH__
+#endif // __CPU_O3_FREE_LIST_HH__
diff --git a/src/cpu/o3/iew.cc b/src/cpu/o3/iew.cc
index 45b5610e7..90d035f71 100644
--- a/src/cpu/o3/iew.cc
+++ b/src/cpu/o3/iew.cc
@@ -31,4 +31,4 @@
#include "cpu/o3/iew_impl.hh"
#include "cpu/o3/inst_queue.hh"
-template class SimpleIEW<AlphaSimpleImpl>;
+template class DefaultIEW<AlphaSimpleImpl>;
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index 1e370d4e6..935320628 100644
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,22 +26,41 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-//Todo: Update with statuses.
-//Need to handle delaying writes to the writeback bus if it's full at the
-//given time.
-
-#ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__
-#define __CPU_O3_CPU_SIMPLE_IEW_HH__
+#ifndef __CPU_O3_IEW_HH__
+#define __CPU_O3_IEW_HH__
#include <queue>
-#include "config/full_system.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
+#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
-
+#include "cpu/o3/scoreboard.hh"
+#include "cpu/o3/lsq.hh"
+
+class FUPool;
+
+/**
+ * DefaultIEW handles both single threaded and SMT IEW
+ * (issue/execute/writeback). It handles the dispatching of
+ * instructions to the LSQ/IQ as part of the issue stage, and has the
+ * IQ try to issue instructions each cycle. The execute latency is
+ * actually tied into the issue latency to allow the IQ to be able to
+ * do back-to-back scheduling without having to speculatively schedule
+ * instructions. This happens by having the IQ have access to the
+ * functional units, and the IQ gets the execution latencies from the
+ * FUs when it issues instructions. Instructions reach the execute
+ * stage on the last cycle of their execution, which is when the IQ
+ * knows to wake up any dependent instructions, allowing back to back
+ * scheduling. The execute portion of IEW separates memory
+ * instructions from non-memory instructions, either telling the LSQ
+ * to execute the instruction, or executing the instruction directly.
+ * The writeback portion of IEW completes the instructions by waking
+ * up any dependents, and marking the register ready on the
+ * scoreboard.
+ */
template<class Impl>
-class SimpleIEW
+class DefaultIEW
{
private:
//Typedefs from Impl
@@ -52,7 +71,7 @@ class SimpleIEW
typedef typename CPUPol::IQ IQ;
typedef typename CPUPol::RenameMap RenameMap;
- typedef typename CPUPol::LDSTQ LDSTQ;
+ typedef typename CPUPol::LSQ LSQ;
typedef typename CPUPol::TimeStruct TimeStruct;
typedef typename CPUPol::IEWStruct IEWStruct;
@@ -60,77 +79,222 @@ class SimpleIEW
typedef typename CPUPol::IssueStruct IssueStruct;
friend class Impl::FullCPU;
+ friend class CPUPol::IQ;
+
public:
+ /** Overall IEW stage status. Used to determine if the CPU can
+ * deschedule itself due to a lack of activity.
+ */
enum Status {
+ Active,
+ Inactive
+ };
+
+ /** Status for Issue, Execute, and Writeback stages. */
+ enum StageStatus {
Running,
Blocked,
Idle,
+ StartSquash,
Squashing,
Unblocking
};
private:
+ /** Overall stage status. */
Status _status;
- Status _issueStatus;
- Status _exeStatus;
- Status _wbStatus;
+ /** Dispatch status. */
+ StageStatus dispatchStatus[Impl::MaxThreads];
+ /** Execute status. */
+ StageStatus exeStatus;
+ /** Writeback status. */
+ StageStatus wbStatus;
public:
- class WritebackEvent : public Event {
+ /** LdWriteback event for a load completion. */
+ class LdWritebackEvent : public Event {
private:
+ /** Instruction that is writing back data to the register file. */
DynInstPtr inst;
- SimpleIEW<Impl> *iewStage;
+ /** Pointer to IEW stage. */
+ DefaultIEW<Impl> *iewStage;
public:
- WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew);
+ /** Constructs a load writeback event. */
+ LdWritebackEvent(DynInstPtr &_inst, DefaultIEW<Impl> *_iew);
+ /** Processes writeback event. */
virtual void process();
+ /** Returns the description of the writeback event. */
virtual const char *description();
};
public:
- SimpleIEW(Params &params);
+ /** Constructs a DefaultIEW with the given parameters. */
+ DefaultIEW(Params *params);
+
+ /** Returns the name of the DefaultIEW stage. */
+ std::string name() const;
+ /** Registers statistics. */
void regStats();
+ /** Initializes stage; sends back the number of free IQ and LSQ entries. */
+ void initStage();
+
+ /** Sets CPU pointer for IEW, IQ, and LSQ. */
void setCPU(FullCPU *cpu_ptr);
+ /** Sets main time buffer used for backwards communication. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
+ /** Sets time buffer for getting instructions coming from rename. */
void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
+ /** Sets time buffer to pass on instructions to commit. */
void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
- void setRenameMap(RenameMap *rm_ptr);
+ /** Sets pointer to list of active threads. */
+ void setActiveThreads(std::list<unsigned> *at_ptr);
+
+ /** Sets pointer to the scoreboard. */
+ void setScoreboard(Scoreboard *sb_ptr);
+
+ void switchOut();
- void squash();
+ void doSwitchOut();
- void squashDueToBranch(DynInstPtr &inst);
+ void takeOverFrom();
- void squashDueToMem(DynInstPtr &inst);
+ bool isSwitchedOut() { return switchedOut; }
- void block();
+ /** Sets page table pointer within LSQ. */
+// void setPageTable(PageTable *pt_ptr);
- inline void unblock();
+ /** Squashes instructions in IEW for a specific thread. */
+ void squash(unsigned tid);
+ /** Wakes all dependents of a completed instruction. */
void wakeDependents(DynInstPtr &inst);
+ /** Tells memory dependence unit that a memory instruction needs to be
+ * rescheduled. It will re-execute once replayMemInst() is called.
+ */
+ void rescheduleMemInst(DynInstPtr &inst);
+
+ /** Re-executes all rescheduled memory instructions. */
+ void replayMemInst(DynInstPtr &inst);
+
+ /** Sends an instruction to commit through the time buffer. */
void instToCommit(DynInstPtr &inst);
+ /** Inserts unused instructions of a thread into the skid buffer. */
+ void skidInsert(unsigned tid);
+
+ /** Returns the max of the number of entries in all of the skid buffers. */
+ int skidCount();
+
+ /** Returns if all of the skid buffers are empty. */
+ bool skidsEmpty();
+
+ /** Updates overall IEW status based on all of the stages' statuses. */
+ void updateStatus();
+
+ /** Resets entries of the IQ and the LSQ. */
+ void resetEntries();
+
+ /** Tells the CPU to wakeup if it has descheduled itself due to no
+ * activity. Used mainly by the LdWritebackEvent.
+ */
+ void wakeCPU();
+
+ /** Reports to the CPU that there is activity this cycle. */
+ void activityThisCycle();
+
+ /** Tells CPU that the IEW stage is active and running. */
+ inline void activateStage();
+
+ /** Tells CPU that the IEW stage is inactive and idle. */
+ inline void deactivateStage();
+
+ /** Returns if the LSQ has any stores to writeback. */
+ bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
+
private:
- void dispatchInsts();
+ /** Sends commit proper information for a squash due to a branch
+ * mispredict.
+ */
+ void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
+ /** Sends commit proper information for a squash due to a memory order
+ * violation.
+ */
+ void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id);
+
+ /** Sends commit proper information for a squash due to memory becoming
+ * blocked (younger issued instructions must be retried).
+ */
+ void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id);
+
+ /** Sets Dispatch to blocked, and signals back to other stages to block. */
+ void block(unsigned thread_id);
+
+ /** Unblocks Dispatch if the skid buffer is empty, and signals back to
+ * other stages to unblock.
+ */
+ void unblock(unsigned thread_id);
+
+ /** Determines proper actions to take given Dispatch's status. */
+ void dispatch(unsigned tid);
+
+ /** Dispatches instructions to IQ and LSQ. */
+ void dispatchInsts(unsigned tid);
+
+ /** Executes instructions. In the case of memory operations, it informs the
+ * LSQ to execute the instructions. Also handles any redirects that occur
+ * due to the executed instructions.
+ */
void executeInsts();
+ /** Writebacks instructions. In our model, the instruction's execute()
+ * function atomically reads registers, executes, and writes registers.
+ * Thus this writeback only wakes up dependent instructions, and informs
+ * the scoreboard of registers becoming ready.
+ */
+ void writebackInsts();
+
+ /** Returns the number of valid, non-squashed instructions coming from
+ * rename to dispatch.
+ */
+ unsigned validInstsFromRename();
+
+ /** Reads the stall signals. */
+ void readStallSignals(unsigned tid);
+
+ /** Checks if any of the stall conditions are currently true. */
+ bool checkStall(unsigned tid);
+
+ /** Processes inputs and changes state accordingly. */
+ void checkSignalsAndUpdate(unsigned tid);
+
+ /** Sorts instructions coming from rename into lists separated by thread. */
+ void sortInsts();
+
public:
+ /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and
+ * Writeback to run for one cycle.
+ */
void tick();
- void iew();
+ private:
+ void updateExeInstStats(DynInstPtr &inst);
- //Interfaces to objects inside and outside of IEW.
- /** Time buffer interface. */
+ /** Pointer to main time buffer used for backwards communication. */
TimeBuffer<TimeStruct> *timeBuffer;
+ /** Wire to write information heading to previous stages. */
+ typename TimeBuffer<TimeStruct>::wire toFetch;
+
/** Wire to get commit's output from backwards time buffer. */
typename TimeBuffer<TimeStruct>::wire fromCommit;
@@ -158,32 +322,67 @@ class SimpleIEW
/** Wire to write infromation heading to commit. */
typename TimeBuffer<IEWStruct>::wire toCommit;
- //Will need internal queue to hold onto instructions coming from
- //the rename stage in case of a stall.
+ /** Queue of all instructions coming from rename this cycle. */
+ std::queue<DynInstPtr> insts[Impl::MaxThreads];
+
/** Skid buffer between rename and IEW. */
- std::queue<RenameStruct> skidBuffer;
+ std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads];
- protected:
+ /** Scoreboard pointer. */
+ Scoreboard* scoreboard;
+
+ public:
/** Instruction queue. */
IQ instQueue;
- LDSTQ ldstQueue;
+ /** Load / store queue. */
+ LSQ ldstQueue;
-#if !FULL_SYSTEM
- public:
- void lsqWriteback();
-#endif
+ /** Pointer to the functional unit pool. */
+ FUPool *fuPool;
private:
- /** Pointer to rename map. Might not want this stage to directly
- * access this though...
+ /** CPU pointer. */
+ FullCPU *cpu;
+
+ /** Records if IEW has written to the time buffer this cycle, so that the
+ * CPU can deschedule itself if there is no activity.
*/
- RenameMap *renameMap;
+ bool wroteToTimeBuffer;
- /** CPU interface. */
- FullCPU *cpu;
+ /** Source of possible stalls. */
+ struct Stalls {
+ bool commit;
+ };
+
+ /** Stages that are telling IEW to stall. */
+ Stalls stalls[Impl::MaxThreads];
+
+ /** Debug function to print instructions that are issued this cycle. */
+ void printAvailableInsts();
+
+ public:
+ /** Records if the LSQ needs to be updated on the next cycle, so that
+ * IEW knows if there will be activity on the next cycle.
+ */
+ bool updateLSQNextCycle;
private:
+ /** Records if there is a fetch redirect on this cycle for each thread. */
+ bool fetchRedirect[Impl::MaxThreads];
+
+ /** Used to track if all instructions have been dispatched this cycle.
+ * If they have not, then blocking must have occurred, and the instructions
+ * would already be added to the skid buffer.
+ * @todo: Fix this hack.
+ */
+ bool dispatchedAllInsts;
+
+ /** Records if the queues have been changed (inserted or issued insts),
+ * so that IEW knows to broadcast the updated amount of free entries.
+ */
+ bool updatedQueues;
+
/** Commit to IEW delay, in ticks. */
unsigned commitToIEWDelay;
@@ -211,29 +410,92 @@ class SimpleIEW
*/
unsigned executeWidth;
- /** Number of cycles stage has been squashing. Used so that the stage
- * knows when it can start unblocking, which is when the previous stage
- * has received the stall signal and clears up its outputs.
+ /** Index into queue of instructions being written back. */
+ unsigned wbNumInst;
+
+ /** Cycle number within the queue of instructions being written back.
+ * Used in case there are too many instructions writing back at the current
+ * cycle and writesbacks need to be scheduled for the future. See comments
+ * in instToCommit().
*/
- unsigned cyclesSquashing;
+ unsigned wbCycle;
+
+ /** Number of active threads. */
+ unsigned numThreads;
+
+ /** Pointer to list of active threads. */
+ std::list<unsigned> *activeThreads;
+
+ /** Maximum size of the skid buffer. */
+ unsigned skidBufferMax;
+ bool switchedOut;
+
+ /** Stat for total number of idle cycles. */
Stats::Scalar<> iewIdleCycles;
+ /** Stat for total number of squashing cycles. */
Stats::Scalar<> iewSquashCycles;
+ /** Stat for total number of blocking cycles. */
Stats::Scalar<> iewBlockCycles;
+ /** Stat for total number of unblocking cycles. */
Stats::Scalar<> iewUnblockCycles;
-// Stats::Scalar<> iewWBInsts;
+ /** Stat for total number of instructions dispatched. */
Stats::Scalar<> iewDispatchedInsts;
+ /** Stat for total number of squashed instructions dispatch skips. */
Stats::Scalar<> iewDispSquashedInsts;
+ /** Stat for total number of dispatched load instructions. */
Stats::Scalar<> iewDispLoadInsts;
+ /** Stat for total number of dispatched store instructions. */
Stats::Scalar<> iewDispStoreInsts;
+ /** Stat for total number of dispatched non speculative instructions. */
Stats::Scalar<> iewDispNonSpecInsts;
+ /** Stat for number of times the IQ becomes full. */
Stats::Scalar<> iewIQFullEvents;
+ /** Stat for number of times the LSQ becomes full. */
+ Stats::Scalar<> iewLSQFullEvents;
+ /** Stat for total number of executed instructions. */
Stats::Scalar<> iewExecutedInsts;
- Stats::Scalar<> iewExecLoadInsts;
- Stats::Scalar<> iewExecStoreInsts;
+ /** Stat for total number of executed load instructions. */
+ Stats::Vector<> iewExecLoadInsts;
+ /** Stat for total number of executed store instructions. */
+// Stats::Scalar<> iewExecStoreInsts;
+ /** Stat for total number of squashed instructions skipped at execute. */
Stats::Scalar<> iewExecSquashedInsts;
+ /** Stat for total number of memory ordering violation events. */
Stats::Scalar<> memOrderViolationEvents;
+ /** Stat for total number of incorrect predicted taken branches. */
Stats::Scalar<> predictedTakenIncorrect;
+ /** Stat for total number of incorrect predicted not taken branches. */
+ Stats::Scalar<> predictedNotTakenIncorrect;
+ /** Stat for total number of mispredicted branches detected at execute. */
+ Stats::Formula branchMispredicts;
+
+ Stats::Vector<> exeSwp;
+ Stats::Vector<> exeNop;
+ Stats::Vector<> exeRefs;
+ Stats::Vector<> exeBranches;
+
+// Stats::Vector<> issued_ops;
+/*
+ Stats::Vector<> stat_fu_busy;
+ Stats::Vector2d<> stat_fuBusy;
+ Stats::Vector<> dist_unissued;
+ Stats::Vector2d<> stat_issued_inst_type;
+*/
+ Stats::Formula issueRate;
+ Stats::Formula iewExecStoreInsts;
+// Stats::Formula issue_op_rate;
+// Stats::Formula fu_busy_rate;
+
+ Stats::Vector<> iewInstsToCommit;
+ Stats::Vector<> writebackCount;
+ Stats::Vector<> producerInst;
+ Stats::Vector<> consumerInst;
+ Stats::Vector<> wbPenalized;
+
+ Stats::Formula wbRate;
+ Stats::Formula wbFanout;
+ Stats::Formula wbPenalizedRate;
};
-#endif // __CPU_O3_CPU_IEW_HH__
+#endif // __CPU_O3_IEW_HH__
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 85217dd10..b0137d7fc 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,59 +29,86 @@
// @todo: Fix the instantaneous communication among all the stages within
// iew. There's a clear delay between issue and execute, yet backwards
// communication happens simultaneously.
-// Update the statuses for each stage.
#include <queue>
#include "base/timebuf.hh"
+#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/iew.hh"
+using namespace std;
+
template<class Impl>
-SimpleIEW<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst,
- SimpleIEW<Impl> *_iew)
- : Event(&mainEventQueue, CPU_Tick_Pri), inst(_inst), iewStage(_iew)
+DefaultIEW<Impl>::LdWritebackEvent::LdWritebackEvent(DynInstPtr &_inst,
+ DefaultIEW<Impl> *_iew)
+ : Event(&mainEventQueue), inst(_inst), iewStage(_iew)
{
this->setFlags(Event::AutoDelete);
}
template<class Impl>
void
-SimpleIEW<Impl>::WritebackEvent::process()
+DefaultIEW<Impl>::LdWritebackEvent::process()
{
- DPRINTF(IEW, "IEW: WRITEBACK EVENT!!!!\n");
+ DPRINTF(IEW, "Load writeback event [sn:%lli]\n", inst->seqNum);
+ DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum);
+
+ //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
+
+ if (iewStage->isSwitchedOut()) {
+ inst = NULL;
+ return;
+ } else if (inst->isSquashed()) {
+ iewStage->wakeCPU();
+ inst = NULL;
+ return;
+ }
+
+ iewStage->wakeCPU();
+
+ if (!inst->isExecuted()) {
+ inst->setExecuted();
+
+ // Complete access to copy data to proper place.
+ if (inst->isStore()) {
+ inst->completeAcc();
+ }
+ }
// Need to insert instruction into queue to commit
iewStage->instToCommit(inst);
- // Need to execute second half of the instruction, do actual writing to
- // registers and such
- inst->execute();
+
+ iewStage->activityThisCycle();
+
+ inst = NULL;
}
template<class Impl>
const char *
-SimpleIEW<Impl>::WritebackEvent::description()
+DefaultIEW<Impl>::LdWritebackEvent::description()
{
- return "LSQ writeback event";
+ return "Load writeback event";
}
template<class Impl>
-SimpleIEW<Impl>::SimpleIEW(Params &params)
- : // Just make this time buffer really big for now
+DefaultIEW<Impl>::DefaultIEW(Params *params)
+ : // @todo: Make this into a parameter.
issueToExecQueue(5, 5),
instQueue(params),
ldstQueue(params),
- commitToIEWDelay(params.commitToIEWDelay),
- renameToIEWDelay(params.renameToIEWDelay),
- issueToExecuteDelay(params.issueToExecuteDelay),
- issueReadWidth(params.issueWidth),
- issueWidth(params.issueWidth),
- executeWidth(params.executeWidth)
-{
- DPRINTF(IEW, "IEW: executeIntWidth: %i.\n", params.executeIntWidth);
- _status = Idle;
- _issueStatus = Idle;
- _exeStatus = Idle;
- _wbStatus = Idle;
+ fuPool(params->fuPool),
+ commitToIEWDelay(params->commitToIEWDelay),
+ renameToIEWDelay(params->renameToIEWDelay),
+ issueToExecuteDelay(params->issueToExecuteDelay),
+ issueReadWidth(params->issueWidth),
+ issueWidth(params->issueWidth),
+ executeWidth(params->executeWidth),
+ numThreads(params->numberOfThreads),
+ switchedOut(false)
+{
+ _status = Active;
+ exeStatus = Running;
+ wbStatus = Idle;
// Setup wire to read instructions coming from issue.
fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
@@ -89,13 +116,33 @@ SimpleIEW<Impl>::SimpleIEW(Params &params)
// Instruction queue needs the queue between issue and execute.
instQueue.setIssueToExecuteQueue(&issueToExecQueue);
+ instQueue.setIEW(this);
ldstQueue.setIEW(this);
+
+ for (int i=0; i < numThreads; i++) {
+ dispatchStatus[i] = Running;
+ stalls[i].commit = false;
+ fetchRedirect[i] = false;
+ }
+
+ updateLSQNextCycle = false;
+
+ skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
+}
+
+template <class Impl>
+std::string
+DefaultIEW<Impl>::name() const
+{
+ return cpu->name() + ".iew";
}
template <class Impl>
void
-SimpleIEW<Impl>::regStats()
+DefaultIEW<Impl>::regStats()
{
+ using namespace Stats;
+
instQueue.regStats();
iewIdleCycles
@@ -114,8 +161,6 @@ SimpleIEW<Impl>::regStats()
.name(name() + ".iewUnblockCycles")
.desc("Number of cycles IEW is unblocking");
-// iewWBInsts;
-
iewDispatchedInsts
.name(name() + ".iewDispatchedInsts")
.desc("Number of instructions dispatched to IQ");
@@ -140,17 +185,19 @@ SimpleIEW<Impl>::regStats()
.name(name() + ".iewIQFullEvents")
.desc("Number of times the IQ has become full, causing a stall");
+ iewLSQFullEvents
+ .name(name() + ".iewLSQFullEvents")
+ .desc("Number of times the LSQ has become full, causing a stall");
+
iewExecutedInsts
.name(name() + ".iewExecutedInsts")
.desc("Number of executed instructions");
iewExecLoadInsts
+ .init(cpu->number_of_threads)
.name(name() + ".iewExecLoadInsts")
- .desc("Number of load instructions executed");
-
- iewExecStoreInsts
- .name(name() + ".iewExecStoreInsts")
- .desc("Number of store instructions executed");
+ .desc("Number of load instructions executed")
+ .flags(total);
iewExecSquashedInsts
.name(name() + ".iewExecSquashedInsts")
@@ -163,24 +210,161 @@ SimpleIEW<Impl>::regStats()
predictedTakenIncorrect
.name(name() + ".predictedTakenIncorrect")
.desc("Number of branches that were predicted taken incorrectly");
+
+ predictedNotTakenIncorrect
+ .name(name() + ".predictedNotTakenIncorrect")
+ .desc("Number of branches that were predicted not taken incorrectly");
+
+ branchMispredicts
+ .name(name() + ".branchMispredicts")
+ .desc("Number of branch mispredicts detected at execute");
+
+ branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
+
+ exeSwp
+ .init(cpu->number_of_threads)
+ .name(name() + ".EXEC:swp")
+ .desc("number of swp insts executed")
+ .flags(total)
+ ;
+
+ exeNop
+ .init(cpu->number_of_threads)
+ .name(name() + ".EXEC:nop")
+ .desc("number of nop insts executed")
+ .flags(total)
+ ;
+
+ exeRefs
+ .init(cpu->number_of_threads)
+ .name(name() + ".EXEC:refs")
+ .desc("number of memory reference insts executed")
+ .flags(total)
+ ;
+
+ exeBranches
+ .init(cpu->number_of_threads)
+ .name(name() + ".EXEC:branches")
+ .desc("Number of branches executed")
+ .flags(total)
+ ;
+
+ issueRate
+ .name(name() + ".EXEC:rate")
+ .desc("Inst execution rate")
+ .flags(total)
+ ;
+ issueRate = iewExecutedInsts / cpu->numCycles;
+
+ iewExecStoreInsts
+ .name(name() + ".EXEC:stores")
+ .desc("Number of stores executed")
+ .flags(total)
+ ;
+ iewExecStoreInsts = exeRefs - iewExecLoadInsts;
+/*
+ for (int i=0; i<Num_OpClasses; ++i) {
+ stringstream subname;
+ subname << opClassStrings[i] << "_delay";
+ issue_delay_dist.subname(i, subname.str());
+ }
+*/
+ //
+ // Other stats
+ //
+
+ iewInstsToCommit
+ .init(cpu->number_of_threads)
+ .name(name() + ".WB:sent")
+ .desc("cumulative count of insts sent to commit")
+ .flags(total)
+ ;
+
+ writebackCount
+ .init(cpu->number_of_threads)
+ .name(name() + ".WB:count")
+ .desc("cumulative count of insts written-back")
+ .flags(total)
+ ;
+
+ producerInst
+ .init(cpu->number_of_threads)
+ .name(name() + ".WB:producers")
+ .desc("num instructions producing a value")
+ .flags(total)
+ ;
+
+ consumerInst
+ .init(cpu->number_of_threads)
+ .name(name() + ".WB:consumers")
+ .desc("num instructions consuming a value")
+ .flags(total)
+ ;
+
+ wbPenalized
+ .init(cpu->number_of_threads)
+ .name(name() + ".WB:penalized")
+ .desc("number of instrctions required to write to 'other' IQ")
+ .flags(total)
+ ;
+
+ wbPenalizedRate
+ .name(name() + ".WB:penalized_rate")
+ .desc ("fraction of instructions written-back that wrote to 'other' IQ")
+ .flags(total)
+ ;
+
+ wbPenalizedRate = wbPenalized / writebackCount;
+
+ wbFanout
+ .name(name() + ".WB:fanout")
+ .desc("average fanout of values written-back")
+ .flags(total)
+ ;
+
+ wbFanout = producerInst / consumerInst;
+
+ wbRate
+ .name(name() + ".WB:rate")
+ .desc("insts written-back per cycle")
+ .flags(total)
+ ;
+ wbRate = writebackCount / cpu->numCycles;
}
template<class Impl>
void
-SimpleIEW<Impl>::setCPU(FullCPU *cpu_ptr)
+DefaultIEW<Impl>::initStage()
{
- DPRINTF(IEW, "IEW: Setting CPU pointer.\n");
+ for (int tid=0; tid < numThreads; tid++) {
+ toRename->iewInfo[tid].usedIQ = true;
+ toRename->iewInfo[tid].freeIQEntries =
+ instQueue.numFreeEntries(tid);
+
+ toRename->iewInfo[tid].usedLSQ = true;
+ toRename->iewInfo[tid].freeLSQEntries =
+ ldstQueue.numFreeEntries(tid);
+ }
+}
+
+template<class Impl>
+void
+DefaultIEW<Impl>::setCPU(FullCPU *cpu_ptr)
+{
+ DPRINTF(IEW, "Setting CPU pointer.\n");
cpu = cpu_ptr;
instQueue.setCPU(cpu_ptr);
ldstQueue.setCPU(cpu_ptr);
+
+ cpu->activateStage(FullCPU::IEWIdx);
}
template<class Impl>
void
-SimpleIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
+DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
{
- DPRINTF(IEW, "IEW: Setting time buffer pointer.\n");
+ DPRINTF(IEW, "Setting time buffer pointer.\n");
timeBuffer = tb_ptr;
// Setup wire to read information from time buffer, from commit.
@@ -189,15 +373,17 @@ SimpleIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
// Setup wire to write information back to previous stages.
toRename = timeBuffer->getWire(0);
+ toFetch = timeBuffer->getWire(0);
+
// Instruction queue also needs main time buffer.
instQueue.setTimeBuffer(tb_ptr);
}
template<class Impl>
void
-SimpleIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
+DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
{
- DPRINTF(IEW, "IEW: Setting rename queue pointer.\n");
+ DPRINTF(IEW, "Setting rename queue pointer.\n");
renameQueue = rq_ptr;
// Setup wire to read information from rename queue.
@@ -206,9 +392,9 @@ SimpleIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
template<class Impl>
void
-SimpleIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
+DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
{
- DPRINTF(IEW, "IEW: Setting IEW queue pointer.\n");
+ DPRINTF(IEW, "Setting IEW queue pointer.\n");
iewQueue = iq_ptr;
// Setup wire to write instructions to commit.
@@ -217,355 +403,943 @@ SimpleIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
template<class Impl>
void
-SimpleIEW<Impl>::setRenameMap(RenameMap *rm_ptr)
+DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+{
+ DPRINTF(IEW, "Setting active threads list pointer.\n");
+ activeThreads = at_ptr;
+
+ ldstQueue.setActiveThreads(at_ptr);
+ instQueue.setActiveThreads(at_ptr);
+}
+
+template<class Impl>
+void
+DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
+{
+ DPRINTF(IEW, "Setting scoreboard pointer.\n");
+ scoreboard = sb_ptr;
+}
+
+#if 0
+template<class Impl>
+void
+DefaultIEW<Impl>::setPageTable(PageTable *pt_ptr)
+{
+ ldstQueue.setPageTable(pt_ptr);
+}
+#endif
+
+template <class Impl>
+void
+DefaultIEW<Impl>::switchOut()
+{
+ cpu->signalSwitched();
+}
+
+template <class Impl>
+void
+DefaultIEW<Impl>::doSwitchOut()
{
- DPRINTF(IEW, "IEW: Setting rename map pointer.\n");
- renameMap = rm_ptr;
+ switchedOut = true;
+
+ instQueue.switchOut();
+ ldstQueue.switchOut();
+ fuPool->switchOut();
+
+ for (int i = 0; i < numThreads; i++) {
+ while (!insts[i].empty())
+ insts[i].pop();
+ while (!skidBuffer[i].empty())
+ skidBuffer[i].pop();
+ }
+}
+
+template <class Impl>
+void
+DefaultIEW<Impl>::takeOverFrom()
+{
+ _status = Active;
+ exeStatus = Running;
+ wbStatus = Idle;
+ switchedOut = false;
+
+ instQueue.takeOverFrom();
+ ldstQueue.takeOverFrom();
+ fuPool->takeOverFrom();
+
+ initStage();
+ cpu->activityThisCycle();
+
+ for (int i=0; i < numThreads; i++) {
+ dispatchStatus[i] = Running;
+ stalls[i].commit = false;
+ fetchRedirect[i] = false;
+ }
+
+ updateLSQNextCycle = false;
+
+ // @todo: Fix hardcoded number
+ for (int i = 0; i < 6; ++i) {
+ issueToExecQueue.advance();
+ }
}
template<class Impl>
void
-SimpleIEW<Impl>::squash()
+DefaultIEW<Impl>::squash(unsigned tid)
{
- DPRINTF(IEW, "IEW: Squashing all instructions.\n");
- _status = Squashing;
+ DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
+ tid);
// Tell the IQ to start squashing.
- instQueue.squash();
+ instQueue.squash(tid);
// Tell the LDSTQ to start squashing.
- ldstQueue.squash(fromCommit->commitInfo.doneSeqNum);
+ ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
+
+ updatedQueues = true;
+
+ // Clear the skid buffer in case it has any data in it.
+ while (!skidBuffer[tid].empty()) {
+
+ if (skidBuffer[tid].front()->isLoad() ||
+ skidBuffer[tid].front()->isStore() ) {
+ toRename->iewInfo[tid].dispatchedToLSQ++;
+ }
+
+ toRename->iewInfo[tid].dispatched++;
+
+ skidBuffer[tid].pop();
+ }
+
+ while (!insts[tid].empty()) {
+ if (insts[tid].front()->isLoad() ||
+ insts[tid].front()->isStore() ) {
+ toRename->iewInfo[tid].dispatchedToLSQ++;
+ }
+
+ toRename->iewInfo[tid].dispatched++;
+
+ insts[tid].pop();
+ }
}
template<class Impl>
void
-SimpleIEW<Impl>::squashDueToBranch(DynInstPtr &inst)
-{
- DPRINTF(IEW, "IEW: Squashing from a specific instruction, PC: %#x.\n",
- inst->PC);
- // Perhaps leave the squashing up to the ROB stage to tell it when to
- // squash?
- _status = Squashing;
-
- // Tell rename to squash through the time buffer.
- toCommit->squash = true;
- // Also send PC update information back to prior stages.
- toCommit->squashedSeqNum = inst->seqNum;
- toCommit->mispredPC = inst->readPC();
- toCommit->nextPC = inst->readNextPC();
- toCommit->branchMispredict = true;
- // Prediction was incorrect, so send back inverse.
- toCommit->branchTaken = inst->readNextPC() !=
+DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
+{
+ DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
+ "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
+
+ toCommit->squash[tid] = true;
+ toCommit->squashedSeqNum[tid] = inst->seqNum;
+ toCommit->mispredPC[tid] = inst->readPC();
+ toCommit->nextPC[tid] = inst->readNextPC();
+ toCommit->branchMispredict[tid] = true;
+ toCommit->branchTaken[tid] = inst->readNextPC() !=
(inst->readPC() + sizeof(TheISA::MachInst));
+
+ toCommit->includeSquashInst[tid] = false;
+
+ wroteToTimeBuffer = true;
+}
+
+template<class Impl>
+void
+DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
+{
+ DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
+ "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
+
+ toCommit->squash[tid] = true;
+ toCommit->squashedSeqNum[tid] = inst->seqNum;
+ toCommit->nextPC[tid] = inst->readNextPC();
+
+ toCommit->includeSquashInst[tid] = false;
+
+ wroteToTimeBuffer = true;
}
template<class Impl>
void
-SimpleIEW<Impl>::squashDueToMem(DynInstPtr &inst)
+DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
{
- DPRINTF(IEW, "IEW: Squashing from a specific instruction, PC: %#x.\n",
- inst->PC);
- // Perhaps leave the squashing up to the ROB stage to tell it when to
- // squash?
- _status = Squashing;
+ DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
+ "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
+
+ toCommit->squash[tid] = true;
+ toCommit->squashedSeqNum[tid] = inst->seqNum;
+ toCommit->nextPC[tid] = inst->readPC();
+
+ toCommit->includeSquashInst[tid] = true;
- // Tell rename to squash through the time buffer.
- toCommit->squash = true;
- // Also send PC update information back to prior stages.
- toCommit->squashedSeqNum = inst->seqNum;
- toCommit->nextPC = inst->readNextPC();
+ ldstQueue.setLoadBlockedHandled(tid);
+
+ wroteToTimeBuffer = true;
}
template<class Impl>
void
-SimpleIEW<Impl>::block()
+DefaultIEW<Impl>::block(unsigned tid)
{
- DPRINTF(IEW, "IEW: Blocking.\n");
- // Set the status to Blocked.
- _status = Blocked;
+ DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
+
+ if (dispatchStatus[tid] != Blocked &&
+ dispatchStatus[tid] != Unblocking) {
+ toRename->iewBlock[tid] = true;
+ wroteToTimeBuffer = true;
+ }
// Add the current inputs to the skid buffer so they can be
// reprocessed when this stage unblocks.
- skidBuffer.push(*fromRename);
+ skidInsert(tid);
- // Note that this stage only signals previous stages to stall when
- // it is the cause of the stall originates at this stage. Otherwise
- // the previous stages are expected to check all possible stall signals.
+ dispatchStatus[tid] = Blocked;
}
template<class Impl>
-inline void
-SimpleIEW<Impl>::unblock()
+void
+DefaultIEW<Impl>::unblock(unsigned tid)
{
- // Check if there's information in the skid buffer. If there is, then
- // set status to unblocking, otherwise set it directly to running.
- DPRINTF(IEW, "IEW: Reading instructions out of the skid "
- "buffer.\n");
- // Remove the now processed instructions from the skid buffer.
- skidBuffer.pop();
-
- // If there's still information in the skid buffer, then
- // continue to tell previous stages to stall. They will be
- // able to restart once the skid buffer is empty.
- if (!skidBuffer.empty()) {
- toRename->iewInfo.stall = true;
- } else {
- DPRINTF(IEW, "IEW: Stage is done unblocking.\n");
- _status = Running;
+ DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
+ "buffer %u.\n",tid, tid);
+
+ // If the skid bufffer is empty, signal back to previous stages to unblock.
+ // Also switch status to running.
+ if (skidBuffer[tid].empty()) {
+ toRename->iewUnblock[tid] = true;
+ wroteToTimeBuffer = true;
+ DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
+ dispatchStatus[tid] = Running;
}
}
template<class Impl>
void
-SimpleIEW<Impl>::wakeDependents(DynInstPtr &inst)
+DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
{
instQueue.wakeDependents(inst);
}
+template<class Impl>
+void
+DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
+{
+ instQueue.rescheduleMemInst(inst);
+}
+
+template<class Impl>
+void
+DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
+{
+ instQueue.replayMemInst(inst);
+}
template<class Impl>
void
-SimpleIEW<Impl>::instToCommit(DynInstPtr &inst)
+DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
{
+ // First check the time slot that this instruction will write
+ // to. If there are free write ports at the time, then go ahead
+ // and write the instruction to that time. If there are not,
+ // keep looking back to see where's the first time there's a
+ // free slot.
+ while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
+ ++wbNumInst;
+ if (wbNumInst == issueWidth) {
+ ++wbCycle;
+ wbNumInst = 0;
+ }
+ assert(wbCycle < 5);
+ }
+
+ // Add finished instruction to queue to commit.
+ (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
+ (*iewQueue)[wbCycle].size++;
}
template <class Impl>
+unsigned
+DefaultIEW<Impl>::validInstsFromRename()
+{
+ unsigned inst_count = 0;
+
+ for (int i=0; i<fromRename->size; i++) {
+ if (!fromRename->insts[i]->squashed)
+ inst_count++;
+ }
+
+ return inst_count;
+}
+
+template<class Impl>
void
-SimpleIEW<Impl>::dispatchInsts()
-{
- ////////////////////////////////////////
- // DISPATCH/ISSUE stage
- ////////////////////////////////////////
-
- //Put into its own function?
- //Add instructions to IQ if there are any instructions there
-
- // Check if there are any instructions coming from rename, and we're.
- // not squashing.
- if (fromRename->size > 0) {
- int insts_to_add = fromRename->size;
-
- // Loop through the instructions, putting them in the instruction
- // queue.
- for (int inst_num = 0; inst_num < insts_to_add; ++inst_num)
- {
- DynInstPtr inst = fromRename->insts[inst_num];
-
- // Make sure there's a valid instruction there.
- assert(inst);
-
- DPRINTF(IEW, "IEW: Issue: Adding PC %#x to IQ.\n",
- inst->readPC());
-
- // Be sure to mark these instructions as ready so that the
- // commit stage can go ahead and execute them, and mark
- // them as issued so the IQ doesn't reprocess them.
- if (inst->isSquashed()) {
- ++iewDispSquashedInsts;
- continue;
- } else if (instQueue.isFull()) {
- DPRINTF(IEW, "IEW: Issue: IQ has become full.\n");
- // Call function to start blocking.
- block();
- // Tell previous stage to stall.
- toRename->iewInfo.stall = true;
-
- ++iewIQFullEvents;
- break;
- } else if (inst->isLoad()) {
- DPRINTF(IEW, "IEW: Issue: Memory instruction "
- "encountered, adding to LDSTQ.\n");
-
- // Reserve a spot in the load store queue for this
- // memory access.
- ldstQueue.insertLoad(inst);
-
- ++iewDispLoadInsts;
- } else if (inst->isStore()) {
- ldstQueue.insertStore(inst);
+DefaultIEW<Impl>::skidInsert(unsigned tid)
+{
+ DynInstPtr inst = NULL;
- ++iewDispStoreInsts;
- } else if (inst->isNonSpeculative()) {
- DPRINTF(IEW, "IEW: Issue: Nonspeculative instruction "
- "encountered, skipping.\n");
+ while (!insts[tid].empty()) {
+ inst = insts[tid].front();
- // Same hack as with stores.
- inst->setCanCommit();
+ insts[tid].pop();
+
+ DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
+ "dispatch skidBuffer %i\n",tid, inst->seqNum,
+ inst->readPC(),tid);
+
+ skidBuffer[tid].push(inst);
+ }
+
+ assert(skidBuffer[tid].size() <= skidBufferMax &&
+ "Skidbuffer Exceeded Max Size");
+}
+
+template<class Impl>
+int
+DefaultIEW<Impl>::skidCount()
+{
+ int max=0;
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned thread_count = skidBuffer[*threads++].size();
+ if (max < thread_count)
+ max = thread_count;
+ }
+
+ return max;
+}
+
+template<class Impl>
+bool
+DefaultIEW<Impl>::skidsEmpty()
+{
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ if (!skidBuffer[*threads++].empty())
+ return false;
+ }
+
+ return true;
+}
+
+template <class Impl>
+void
+DefaultIEW<Impl>::updateStatus()
+{
+ bool any_unblocking = false;
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ if (dispatchStatus[tid] == Unblocking) {
+ any_unblocking = true;
+ break;
+ }
+ }
+
+ // If there are no ready instructions waiting to be scheduled by the IQ,
+ // and there's no stores waiting to write back, and dispatch is not
+ // unblocking, then there is no internal activity for the IEW stage.
+ if (_status == Active && !instQueue.hasReadyInsts() &&
+ !ldstQueue.willWB() && !any_unblocking) {
+ DPRINTF(IEW, "IEW switching to idle\n");
+
+ deactivateStage();
+
+ _status = Inactive;
+ } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
+ ldstQueue.willWB() ||
+ any_unblocking)) {
+ // Otherwise there is internal activity. Set to active.
+ DPRINTF(IEW, "IEW switching to active\n");
+
+ activateStage();
+
+ _status = Active;
+ }
+}
+
+template <class Impl>
+void
+DefaultIEW<Impl>::resetEntries()
+{
+ instQueue.resetEntries();
+ ldstQueue.resetEntries();
+}
+
+template <class Impl>
+void
+DefaultIEW<Impl>::readStallSignals(unsigned tid)
+{
+ if (fromCommit->commitBlock[tid]) {
+ stalls[tid].commit = true;
+ }
+
+ if (fromCommit->commitUnblock[tid]) {
+ assert(stalls[tid].commit);
+ stalls[tid].commit = false;
+ }
+}
+
+template <class Impl>
+bool
+DefaultIEW<Impl>::checkStall(unsigned tid)
+{
+ bool ret_val(false);
+
+ if (stalls[tid].commit) {
+ DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
+ ret_val = true;
+ } else if (instQueue.isFull(tid)) {
+ DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid);
+ ret_val = true;
+ } else if (ldstQueue.isFull(tid)) {
+ DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
+
+ if (ldstQueue.numLoads(tid) > 0 ) {
+
+ DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
+ tid,ldstQueue.getLoadHeadSeqNum(tid));
+ }
+
+ if (ldstQueue.numStores(tid) > 0) {
+
+ DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
+ tid,ldstQueue.getStoreHeadSeqNum(tid));
+ }
+
+ ret_val = true;
+ } else if (ldstQueue.isStalled(tid)) {
+ DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
+ ret_val = true;
+ }
+
+ return ret_val;
+}
+
+template <class Impl>
+void
+DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
+{
+ // Check if there's a squash signal, squash if there is
+ // Check stall signals, block if there is.
+ // If status was Blocked
+ // if so then go to unblocking
+ // If status was Squashing
+ // check if squashing is not high. Switch to running this cycle.
+
+ readStallSignals(tid);
+
+ if (fromCommit->commitInfo[tid].squash) {
+ squash(tid);
+
+ if (dispatchStatus[tid] == Blocked ||
+ dispatchStatus[tid] == Unblocking) {
+ toRename->iewUnblock[tid] = true;
+ wroteToTimeBuffer = true;
+ }
+
+ dispatchStatus[tid] = Squashing;
+
+ fetchRedirect[tid] = false;
+ return;
+ }
+
+ if (fromCommit->commitInfo[tid].robSquashing) {
+ DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n");
+
+ dispatchStatus[tid] = Squashing;
+
+ return;
+ }
+
+ if (checkStall(tid)) {
+ block(tid);
+ dispatchStatus[tid] = Blocked;
+ return;
+ }
+
+ if (dispatchStatus[tid] == Blocked) {
+ // Status from previous cycle was blocked, but there are no more stall
+ // conditions. Switch over to unblocking.
+ DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
+ tid);
+
+ dispatchStatus[tid] = Unblocking;
- // Specificall insert it as nonspeculative.
+ unblock(tid);
+
+ return;
+ }
+
+ if (dispatchStatus[tid] == Squashing) {
+ // Switch status to running if rename isn't being told to block or
+ // squash this cycle.
+ DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
+ tid);
+
+ dispatchStatus[tid] = Running;
+
+ return;
+ }
+}
+
+template <class Impl>
+void
+DefaultIEW<Impl>::sortInsts()
+{
+ int insts_from_rename = fromRename->size;
+#ifdef DEBUG
+ for (int i = 0; i < numThreads; i++)
+ assert(insts[i].empty());
+#endif
+ for (int i = 0; i < insts_from_rename; ++i) {
+ insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
+ }
+}
+
+template <class Impl>
+void
+DefaultIEW<Impl>::wakeCPU()
+{
+ cpu->wakeCPU();
+}
+
+template <class Impl>
+void
+DefaultIEW<Impl>::activityThisCycle()
+{
+ DPRINTF(Activity, "Activity this cycle.\n");
+ cpu->activityThisCycle();
+}
+
+template <class Impl>
+inline void
+DefaultIEW<Impl>::activateStage()
+{
+ DPRINTF(Activity, "Activating stage.\n");
+ cpu->activateStage(FullCPU::IEWIdx);
+}
+
+template <class Impl>
+inline void
+DefaultIEW<Impl>::deactivateStage()
+{
+ DPRINTF(Activity, "Deactivating stage.\n");
+ cpu->deactivateStage(FullCPU::IEWIdx);
+}
+
+template<class Impl>
+void
+DefaultIEW<Impl>::dispatch(unsigned tid)
+{
+ // If status is Running or idle,
+ // call dispatchInsts()
+ // If status is Unblocking,
+ // buffer any instructions coming from rename
+ // continue trying to empty skid buffer
+ // check if stall conditions have passed
+
+ if (dispatchStatus[tid] == Blocked) {
+ ++iewBlockCycles;
+
+ } else if (dispatchStatus[tid] == Squashing) {
+ ++iewSquashCycles;
+ }
+
+ // Dispatch should try to dispatch as many instructions as its bandwidth
+ // will allow, as long as it is not currently blocked.
+ if (dispatchStatus[tid] == Running ||
+ dispatchStatus[tid] == Idle) {
+ DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
+ "dispatch.\n", tid);
+
+ dispatchInsts(tid);
+ } else if (dispatchStatus[tid] == Unblocking) {
+ // Make sure that the skid buffer has something in it if the
+ // status is unblocking.
+ assert(!skidsEmpty());
+
+ // If the status was unblocking, then instructions from the skid
+ // buffer were used. Remove those instructions and handle
+ // the rest of unblocking.
+ dispatchInsts(tid);
+
+ ++iewUnblockCycles;
+
+ if (validInstsFromRename() && dispatchedAllInsts) {
+ // Add the current inputs to the skid buffer so they can be
+ // reprocessed when this stage unblocks.
+ skidInsert(tid);
+ }
+
+ unblock(tid);
+ }
+}
+
+template <class Impl>
+void
+DefaultIEW<Impl>::dispatchInsts(unsigned tid)
+{
+ dispatchedAllInsts = true;
+
+ // Obtain instructions from skid buffer if unblocking, or queue from rename
+ // otherwise.
+ std::queue<DynInstPtr> &insts_to_dispatch =
+ dispatchStatus[tid] == Unblocking ?
+ skidBuffer[tid] : insts[tid];
+
+ int insts_to_add = insts_to_dispatch.size();
+
+ DynInstPtr inst;
+ bool add_to_iq = false;
+ int dis_num_inst = 0;
+
+ // Loop through the instructions, putting them in the instruction
+ // queue.
+ for ( ; dis_num_inst < insts_to_add &&
+ dis_num_inst < issueReadWidth;
+ ++dis_num_inst)
+ {
+ inst = insts_to_dispatch.front();
+
+ if (dispatchStatus[tid] == Unblocking) {
+ DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
+ "buffer\n", tid);
+ }
+
+ // Make sure there's a valid instruction there.
+ assert(inst);
+
+ DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
+ "IQ.\n",
+ tid, inst->readPC(), inst->seqNum, inst->threadNumber);
+
+ // Be sure to mark these instructions as ready so that the
+ // commit stage can go ahead and execute them, and mark
+ // them as issued so the IQ doesn't reprocess them.
+
+ // Check for squashed instructions.
+ if (inst->isSquashed()) {
+ DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
+ "not adding to IQ.\n", tid);
+
+ ++iewDispSquashedInsts;
+
+ insts_to_dispatch.pop();
+
+ //Tell Rename That An Instruction has been processed
+ if (inst->isLoad() || inst->isStore()) {
+ toRename->iewInfo[tid].dispatchedToLSQ++;
+ }
+ toRename->iewInfo[tid].dispatched++;
+
+ continue;
+ }
+
+ // Check for full conditions.
+ if (instQueue.isFull(tid)) {
+ DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
+
+ // Call function to start blocking.
+ block(tid);
+
+ // Set unblock to false. Special case where we are using
+ // skidbuffer (unblocking) instructions but then we still
+ // get full in the IQ.
+ toRename->iewUnblock[tid] = false;
+
+ dispatchedAllInsts = false;
+
+ ++iewIQFullEvents;
+ break;
+ } else if (ldstQueue.isFull(tid)) {
+ DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
+
+ // Call function to start blocking.
+ block(tid);
+
+ // Set unblock to false. Special case where we are using
+ // skidbuffer (unblocking) instructions but then we still
+ // get full in the IQ.
+ toRename->iewUnblock[tid] = false;
+
+ dispatchedAllInsts = false;
+
+ ++iewLSQFullEvents;
+ break;
+ }
+
+ // Otherwise issue the instruction just fine.
+ if (inst->isLoad()) {
+ DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
+ "encountered, adding to LSQ.\n", tid);
+
+ // Reserve a spot in the load store queue for this
+ // memory access.
+ ldstQueue.insertLoad(inst);
+
+ ++iewDispLoadInsts;
+
+ add_to_iq = true;
+
+ toRename->iewInfo[tid].dispatchedToLSQ++;
+ } else if (inst->isStore()) {
+ DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
+ "encountered, adding to LSQ.\n", tid);
+
+ ldstQueue.insertStore(inst);
+
+ ++iewDispStoreInsts;
+
+ if (inst->isStoreConditional()) {
+ // Store conditionals need to be set as "canCommit()"
+ // so that commit can process them when they reach the
+ // head of commit.
+ inst->setCanCommit();
instQueue.insertNonSpec(inst);
+ add_to_iq = false;
++iewDispNonSpecInsts;
+ } else {
+ add_to_iq = true;
+ }
- continue;
- } else if (inst->isNop()) {
- DPRINTF(IEW, "IEW: Issue: Nop instruction encountered "
- ", skipping.\n");
+ toRename->iewInfo[tid].dispatchedToLSQ++;
+#if FULL_SYSTEM
+ } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
+ // Same as non-speculative stores.
+ inst->setCanCommit();
+ instQueue.insertBarrier(inst);
+ add_to_iq = false;
+#endif
+ } else if (inst->isNonSpeculative()) {
+ DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
+ "encountered, skipping.\n", tid);
- inst->setIssued();
- inst->setExecuted();
- inst->setCanCommit();
+ // Same as non-speculative stores.
+ inst->setCanCommit();
- instQueue.advanceTail(inst);
+ // Specifically insert it as nonspeculative.
+ instQueue.insertNonSpec(inst);
- continue;
- } else if (inst->isExecuted()) {
- assert(0 && "Instruction shouldn't be executed.\n");
- DPRINTF(IEW, "IEW: Issue: Executed branch encountered, "
- "skipping.\n");
+ ++iewDispNonSpecInsts;
- inst->setIssued();
- inst->setCanCommit();
+ add_to_iq = false;
+ } else if (inst->isNop()) {
+ DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
+ "skipping.\n", tid);
- instQueue.advanceTail(inst);
+ inst->setIssued();
+ inst->setExecuted();
+ inst->setCanCommit();
- continue;
- }
+ instQueue.recordProducer(inst);
- // If the instruction queue is not full, then add the
- // instruction.
- instQueue.insert(fromRename->insts[inst_num]);
+ exeNop[tid]++;
+
+ add_to_iq = false;
+ } else if (inst->isExecuted()) {
+ assert(0 && "Instruction shouldn't be executed.\n");
+ DPRINTF(IEW, "Issue: Executed branch encountered, "
+ "skipping.\n");
+
+ inst->setIssued();
+ inst->setCanCommit();
+
+ instQueue.recordProducer(inst);
+
+ add_to_iq = false;
+ } else {
+ add_to_iq = true;
+ }
- ++iewDispatchedInsts;
+ // If the instruction queue is not full, then add the
+ // instruction.
+ if (add_to_iq) {
+ instQueue.insert(inst);
}
+
+ insts_to_dispatch.pop();
+
+ toRename->iewInfo[tid].dispatched++;
+
+ ++iewDispatchedInsts;
+ }
+
+ if (!insts_to_dispatch.empty()) {
+ DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n");
+ block(tid);
+ toRename->iewUnblock[tid] = false;
+ }
+
+ if (dispatchStatus[tid] == Idle && dis_num_inst) {
+ dispatchStatus[tid] = Running;
+
+ updatedQueues = true;
}
+
+ dis_num_inst = 0;
}
template <class Impl>
void
-SimpleIEW<Impl>::executeInsts()
+DefaultIEW<Impl>::printAvailableInsts()
{
- ////////////////////////////////////////
- //EXECUTE/WRITEBACK stage
- ////////////////////////////////////////
+ int inst = 0;
+
+ cout << "Available Instructions: ";
+
+ while (fromIssue->insts[inst]) {
- //Put into its own function?
- //Similarly should probably have separate execution for int vs FP.
- // Above comment is handled by the issue queue only issuing a valid
- // mix of int/fp instructions.
- //Actually okay to just have one execution, buuuuuut will need
- //somewhere that defines the execution latency of all instructions.
- // @todo: Move to the FU pool used in the current full cpu.
+ if (inst%3==0) cout << "\n\t";
- int fu_usage = 0;
- bool fetch_redirect = false;
- int inst_slot = 0;
- int time_slot = 0;
+ cout << "PC: " << fromIssue->insts[inst]->readPC()
+ << " TN: " << fromIssue->insts[inst]->threadNumber
+ << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
+
+ inst++;
+
+ }
+
+ cout << "\n";
+}
+
+template <class Impl>
+void
+DefaultIEW<Impl>::executeInsts()
+{
+ wbNumInst = 0;
+ wbCycle = 0;
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+ fetchRedirect[tid] = false;
+ }
+
+#if 0
+ printAvailableInsts();
+#endif
// Execute/writeback any instructions that are available.
- for (int inst_num = 0;
- fu_usage < executeWidth && /* Haven't exceeded available FU's. */
- inst_num < issueWidth &&
- fromIssue->insts[inst_num];
- ++inst_num) {
+ int insts_to_execute = fromIssue->size;
+ int inst_num = 0;
+ for (; inst_num < insts_to_execute;
+ ++inst_num) {
- DPRINTF(IEW, "IEW: Execute: Executing instructions from IQ.\n");
+ DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
- // Get instruction from issue's queue.
- DynInstPtr inst = fromIssue->insts[inst_num];
+ DynInstPtr inst = instQueue.getInstToExecute();
- DPRINTF(IEW, "IEW: Execute: Processing PC %#x.\n", inst->readPC());
+ DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
+ inst->readPC(), inst->threadNumber,inst->seqNum);
// Check if the instruction is squashed; if so then skip it
- // and don't count it towards the FU usage.
if (inst->isSquashed()) {
- DPRINTF(IEW, "IEW: Execute: Instruction was squashed.\n");
+ DPRINTF(IEW, "Execute: Instruction was squashed.\n");
// Consider this instruction executed so that commit can go
// ahead and retire the instruction.
inst->setExecuted();
- toCommit->insts[inst_num] = inst;
+ // Not sure if I should set this here or just let commit try to
+ // commit any squashed instructions. I like the latter a bit more.
+ inst->setCanCommit();
++iewExecSquashedInsts;
continue;
}
- inst->setExecuted();
-
- // If an instruction is executed, then count it towards FU usage.
- ++fu_usage;
+ Fault fault = NoFault;
// Execute instruction.
// Note that if the instruction faults, it will be handled
// at the commit stage.
- if (inst->isMemRef()) {
- DPRINTF(IEW, "IEW: Execute: Calculating address for memory "
+ if (inst->isMemRef() &&
+ (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
+ DPRINTF(IEW, "Execute: Calculating address for memory "
"reference.\n");
// Tell the LDSTQ to execute this instruction (if it is a load).
if (inst->isLoad()) {
- ldstQueue.executeLoad(inst);
-
- ++iewExecLoadInsts;
+ // Loads will mark themselves as executed, and their writeback
+ // event adds the instruction to the queue to commit
+ fault = ldstQueue.executeLoad(inst);
} else if (inst->isStore()) {
ldstQueue.executeStore(inst);
- ++iewExecStoreInsts;
+ // If the store had a fault then it may not have a mem req
+ if (inst->req && !(inst->req->flags & LOCKED)) {
+ inst->setExecuted();
+
+ instToCommit(inst);
+ }
+
+ // Store conditionals will mark themselves as
+ // executed, and their writeback event will add the
+ // instruction to the queue to commit.
} else {
- panic("IEW: Unexpected memory type!\n");
+ panic("Unexpected memory type!\n");
}
} else {
inst->execute();
- ++iewExecutedInsts;
+ inst->setExecuted();
+
+ instToCommit(inst);
}
- // First check the time slot that this instruction will write
- // to. If there are free write ports at the time, then go ahead
- // and write the instruction to that time. If there are not,
- // keep looking back to see where's the first time there's a
- // free slot. What happens if you run out of free spaces?
- // For now naively assume that all instructions take one cycle.
- // Otherwise would have to look into the time buffer based on the
- // latency of the instruction.
- (*iewQueue)[time_slot].insts[inst_slot];
- while ((*iewQueue)[time_slot].insts[inst_slot]) {
- if (inst_slot < issueWidth) {
- ++inst_slot;
- } else {
- ++time_slot;
- inst_slot = 0;
- }
+ updateExeInstStats(inst);
- assert(time_slot < 5);
- }
+ // Check if branch prediction was correct, if not then we need
+ // to tell commit to squash in flight instructions. Only
+ // handle this if there hasn't already been something that
+ // redirects fetch in this group of instructions.
- // May actually have to work this out, especially with loads and stores
+ // This probably needs to prioritize the redirects if a different
+ // scheduler is used. Currently the scheduler schedules the oldest
+ // instruction first, so the branch resolution order will be correct.
+ unsigned tid = inst->threadNumber;
- // Add finished instruction to queue to commit.
- (*iewQueue)[time_slot].insts[inst_slot] = inst;
- (*iewQueue)[time_slot].size++;
+ if (!fetchRedirect[tid]) {
- // Check if branch was correct. This check happens after the
- // instruction is added to the queue because even if the branch
- // is mispredicted, the branch instruction itself is still valid.
- // Only handle this if there hasn't already been something that
- // redirects fetch in this group of instructions.
- if (!fetch_redirect) {
if (inst->mispredicted()) {
- fetch_redirect = true;
+ fetchRedirect[tid] = true;
- DPRINTF(IEW, "IEW: Execute: Branch mispredict detected.\n");
- DPRINTF(IEW, "IEW: Execute: Redirecting fetch to PC: %#x.\n",
+ DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
+ DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n",
inst->nextPC);
// If incorrect, then signal the ROB that it must be squashed.
- squashDueToBranch(inst);
+ squashDueToBranch(inst, tid);
if (inst->predTaken()) {
predictedTakenIncorrect++;
+ } else {
+ predictedNotTakenIncorrect++;
}
- } else if (ldstQueue.violation()) {
- fetch_redirect = true;
+ } else if (ldstQueue.violation(tid)) {
+ fetchRedirect[tid] = true;
- // Get the DynInst that caused the violation.
- DynInstPtr violator = ldstQueue.getMemDepViolator();
+ // If there was an ordering violation, then get the
+ // DynInst that caused the violation. Note that this
+ // clears the violation signal.
+ DynInstPtr violator;
+ violator = ldstQueue.getMemDepViolator(tid);
- DPRINTF(IEW, "IEW: LDSTQ detected a violation. Violator PC: "
+ DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: "
"%#x, inst PC: %#x. Addr is: %#x.\n",
violator->readPC(), inst->readPC(), inst->physEffAddr);
@@ -573,164 +1347,232 @@ SimpleIEW<Impl>::executeInsts()
instQueue.violation(inst, violator);
// Squash.
- squashDueToMem(inst);
+ squashDueToMemOrder(inst,tid);
++memOrderViolationEvents;
+ } else if (ldstQueue.loadBlocked(tid) &&
+ !ldstQueue.isLoadBlockedHandled(tid)) {
+ fetchRedirect[tid] = true;
+
+ DPRINTF(IEW, "Load operation couldn't execute because the "
+ "memory system is blocked. PC: %#x [sn:%lli]\n",
+ inst->readPC(), inst->seqNum);
+
+ squashDueToMemBlocked(inst, tid);
}
}
}
+
+ if (inst_num) {
+ if (exeStatus == Idle) {
+ exeStatus = Running;
+ }
+
+ updatedQueues = true;
+
+ cpu->activityThisCycle();
+ }
+
+ // Need to reset this in case a writeback event needs to write into the
+ // iew queue. That way the writeback event will write into the correct
+ // spot in the queue.
+ wbNumInst = 0;
+}
+
+template <class Impl>
+void
+DefaultIEW<Impl>::writebackInsts()
+{
+ // Loop through the head of the time buffer and wake any
+ // dependents. These instructions are about to write back. Also
+ // mark scoreboard that this instruction is finally complete.
+ // Either have IEW have direct access to scoreboard, or have this
+ // as part of backwards communication.
+ for (int inst_num = 0; inst_num < issueWidth &&
+ toCommit->insts[inst_num]; inst_num++) {
+ DynInstPtr inst = toCommit->insts[inst_num];
+ int tid = inst->threadNumber;
+
+ DPRINTF(IEW, "Sending instructions to commit, PC %#x.\n",
+ inst->readPC());
+
+ iewInstsToCommit[tid]++;
+
+ // Some instructions will be sent to commit without having
+ // executed because they need commit to handle them.
+ // E.g. Uncached loads have not actually executed when they
+ // are first sent to commit. Instead commit must tell the LSQ
+ // when it's ready to execute the uncached load.
+ if (!inst->isSquashed() && inst->isExecuted()) {
+ int dependents = instQueue.wakeDependents(inst);
+
+ for (int i = 0; i < inst->numDestRegs(); i++) {
+ //mark as Ready
+ DPRINTF(IEW,"Setting Destination Register %i\n",
+ inst->renamedDestRegIdx(i));
+ scoreboard->setReg(inst->renamedDestRegIdx(i));
+ }
+
+ producerInst[tid]++;
+ consumerInst[tid]+= dependents;
+ writebackCount[tid]++;
+ }
+ }
}
template<class Impl>
void
-SimpleIEW<Impl>::tick()
+DefaultIEW<Impl>::tick()
{
- // Considering putting all the state-determining stuff in this section.
+ wbNumInst = 0;
+ wbCycle = 0;
- // Try to fill up issue queue with as many instructions as bandwidth
- // allows.
- // Decode should try to execute as many instructions as its bandwidth
- // will allow, as long as it is not currently blocked.
+ wroteToTimeBuffer = false;
+ updatedQueues = false;
- // Check if the stage is in a running status.
- if (_status != Blocked && _status != Squashing) {
- DPRINTF(IEW, "IEW: Status is not blocked, attempting to run "
- "stage.\n");
- iew();
+ sortInsts();
- // If it's currently unblocking, check to see if it should switch
- // to running.
- if (_status == Unblocking) {
- unblock();
+ // Free function units marked as being freed this cycle.
+ fuPool->processFreeUnits();
- ++iewUnblockCycles;
- }
- } else if (_status == Squashing) {
+ list<unsigned>::iterator threads = (*activeThreads).begin();
- DPRINTF(IEW, "IEW: Still squashing.\n");
+ // Check stall and squash signals, dispatch any instructions.
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
- // Check if stage should remain squashing. Stop squashing if the
- // squash signal clears.
- if (!fromCommit->commitInfo.squash &&
- !fromCommit->commitInfo.robSquashing) {
- DPRINTF(IEW, "IEW: Done squashing, changing status to "
- "running.\n");
+ DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
- _status = Running;
- instQueue.stopSquash();
- } else {
- instQueue.doSquash();
- }
+ checkSignalsAndUpdate(tid);
+ dispatch(tid);
+ }
- ++iewSquashCycles;
- } else if (_status == Blocked) {
- // Continue to tell previous stage to stall.
- toRename->iewInfo.stall = true;
-
- // Check if possible stall conditions have cleared.
- if (!fromCommit->commitInfo.stall &&
- !instQueue.isFull()) {
- DPRINTF(IEW, "IEW: Stall signals cleared, going to unblock.\n");
- _status = Unblocking;
- }
+ if (exeStatus != Squashing) {
+ executeInsts();
- // If there's still instructions coming from rename, continue to
- // put them on the skid buffer.
- if (fromRename->size == 0) {
- block();
- }
+ writebackInsts();
- if (fromCommit->commitInfo.squash ||
- fromCommit->commitInfo.robSquashing) {
- squash();
- }
+ // Have the instruction queue try to schedule any ready instructions.
+ // (In actuality, this scheduling is for instructions that will
+ // be executed next cycle.)
+ instQueue.scheduleReadyInsts();
- ++iewBlockCycles;
+ // Also should advance its own time buffers if the stage ran.
+ // Not the best place for it, but this works (hopefully).
+ issueToExecQueue.advance();
}
- // @todo: Maybe put these at the beginning, so if it's idle it can
- // return early.
- // Write back number of free IQ entries here.
- toRename->iewInfo.freeIQEntries = instQueue.numFreeEntries();
+ bool broadcast_free_entries = false;
+
+ if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
+ exeStatus = Idle;
+ updateLSQNextCycle = false;
+
+ broadcast_free_entries = true;
+ }
+ // Writeback any stores using any leftover bandwidth.
ldstQueue.writebackStores();
// Check the committed load/store signals to see if there's a load
// or store to commit. Also check if it's being told to execute a
// nonspeculative instruction.
// This is pretty inefficient...
- if (!fromCommit->commitInfo.squash &&
- !fromCommit->commitInfo.robSquashing) {
- ldstQueue.commitStores(fromCommit->commitInfo.doneSeqNum);
- ldstQueue.commitLoads(fromCommit->commitInfo.doneSeqNum);
- }
- if (fromCommit->commitInfo.nonSpecSeqNum != 0) {
- instQueue.scheduleNonSpec(fromCommit->commitInfo.nonSpecSeqNum);
- }
+ threads = (*activeThreads).begin();
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = (*threads++);
- DPRINTF(IEW, "IEW: IQ has %i free entries.\n",
- instQueue.numFreeEntries());
-}
+ DPRINTF(IEW,"Processing [tid:%i]\n",tid);
-template<class Impl>
-void
-SimpleIEW<Impl>::iew()
-{
- // Might want to put all state checks in the tick() function.
- // Check if being told to stall from commit.
- if (fromCommit->commitInfo.stall) {
- block();
- return;
- } else if (fromCommit->commitInfo.squash ||
- fromCommit->commitInfo.robSquashing) {
- // Also check if commit is telling this stage to squash.
- squash();
- return;
- }
+ if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
+ !fromCommit->commitInfo[tid].squash &&
+ !fromCommit->commitInfo[tid].robSquashing) {
- dispatchInsts();
+ ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
- // Have the instruction queue try to schedule any ready instructions.
- instQueue.scheduleReadyInsts();
+ ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
- executeInsts();
+ updateLSQNextCycle = true;
+ instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
+ }
- // Loop through the head of the time buffer and wake any dependents.
- // These instructions are about to write back. In the simple model
- // this loop can really happen within the previous loop, but when
- // instructions have actual latencies, this loop must be separate.
- // Also mark scoreboard that this instruction is finally complete.
- // Either have IEW have direct access to rename map, or have this as
- // part of backwards communication.
- for (int inst_num = 0; inst_num < issueWidth &&
- toCommit->insts[inst_num]; inst_num++)
- {
- DynInstPtr inst = toCommit->insts[inst_num];
+ if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
- DPRINTF(IEW, "IEW: Sending instructions to commit, PC %#x.\n",
- inst->readPC());
+ //DPRINTF(IEW,"NonspecInst from thread %i",tid);
+ if (fromCommit->commitInfo[tid].uncached) {
+ instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
+ } else {
+ instQueue.scheduleNonSpec(
+ fromCommit->commitInfo[tid].nonSpecSeqNum);
+ }
+ }
- if(!inst->isSquashed()) {
- instQueue.wakeDependents(inst);
+ if (broadcast_free_entries) {
+ toFetch->iewInfo[tid].iqCount =
+ instQueue.getCount(tid);
+ toFetch->iewInfo[tid].ldstqCount =
+ ldstQueue.getCount(tid);
- for (int i = 0; i < inst->numDestRegs(); i++)
- {
- renameMap->markAsReady(inst->renamedDestRegIdx(i));
- }
+ toRename->iewInfo[tid].usedIQ = true;
+ toRename->iewInfo[tid].freeIQEntries =
+ instQueue.numFreeEntries();
+ toRename->iewInfo[tid].usedLSQ = true;
+ toRename->iewInfo[tid].freeLSQEntries =
+ ldstQueue.numFreeEntries(tid);
+
+ wroteToTimeBuffer = true;
}
+
+ DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
+ tid, toRename->iewInfo[tid].dispatched);
}
- // Also should advance its own time buffers if the stage ran.
- // Not the best place for it, but this works (hopefully).
- issueToExecQueue.advance();
+ DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). "
+ "LSQ has %i free entries.\n",
+ instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
+ ldstQueue.numFreeEntries());
+
+ updateStatus();
+
+ if (wroteToTimeBuffer) {
+ DPRINTF(Activity, "Activity this cycle.\n");
+ cpu->activityThisCycle();
+ }
}
-#if !FULL_SYSTEM
-template<class Impl>
+template <class Impl>
void
-SimpleIEW<Impl>::lsqWriteback()
+DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
{
- ldstQueue.writebackAllInsts();
-}
+ int thread_number = inst->threadNumber;
+
+ //
+ // Pick off the software prefetches
+ //
+#ifdef TARGET_ALPHA
+ if (inst->isDataPrefetch())
+ exeSwp[thread_number]++;
+ else
+ iewExecutedInsts++;
+#else
+ iewExecutedInsts[thread_number]++;
#endif
+
+ //
+ // Control operations
+ //
+ if (inst->isControl())
+ exeBranches[thread_number]++;
+
+ //
+ // Memory operations
+ //
+ if (inst->isMemRef()) {
+ exeRefs[thread_number]++;
+
+ if (inst->isLoad()) {
+ iewExecLoadInsts[thread_number]++;
+ }
+ }
+}
diff --git a/src/cpu/o3/inst_queue.cc b/src/cpu/o3/inst_queue.cc
index 2ff2282b4..95ae2b699 100644
--- a/src/cpu/o3/inst_queue.cc
+++ b/src/cpu/o3/inst_queue.cc
@@ -32,7 +32,3 @@
// Force instantiation of InstructionQueue.
template class InstructionQueue<AlphaSimpleImpl>;
-
-template<>
-unsigned
-InstructionQueue<AlphaSimpleImpl>::DependencyEntry::mem_alloc_counter = 0;
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 43fe96c49..518de73d9 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_INST_QUEUE_HH__
-#define __CPU_O3_CPU_INST_QUEUE_HH__
+#ifndef __CPU_O3_INST_QUEUE_HH__
+#define __CPU_O3_INST_QUEUE_HH__
#include <list>
#include <map>
@@ -37,8 +37,13 @@
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "cpu/inst_seq.hh"
+#include "cpu/o3/dep_graph.hh"
+#include "encumbered/cpu/full/op_class.hh"
#include "sim/host.hh"
+class FUPool;
+class MemInterface;
+
/**
* A standard instruction queue class. It holds ready instructions, in
* order, in seperate priority queues to facilitate the scheduling of
@@ -47,7 +52,14 @@
* floating point registers have their indices start after the integer
* registers (ie with 96 int and 96 fp registers, regs 0-95 are integer
* and 96-191 are fp). This remains true even for both logical and
- * physical register indices.
+ * physical register indices. The IQ depends on the memory dependence unit to
+ * track when memory operations are ready in terms of ordering; register
+ * dependencies are tracked normally. Right now the IQ also handles the
+ * execution timing; this is mainly to allow back-to-back scheduling without
+ * requiring IEW to be able to peek into the IQ. At the end of the execution
+ * latency, the instruction is put into the queue to execute, where it will
+ * have the execute() function called on it.
+ * @todo: Make IQ able to handle multiple FU pools.
*/
template <class Impl>
class InstructionQueue
@@ -58,87 +70,188 @@ class InstructionQueue
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::Params Params;
+ typedef typename Impl::CPUPol::IEW IEW;
typedef typename Impl::CPUPol::MemDepUnit MemDepUnit;
typedef typename Impl::CPUPol::IssueStruct IssueStruct;
typedef typename Impl::CPUPol::TimeStruct TimeStruct;
- // Typedef of iterator through the list of instructions. Might be
- // better to untie this from the FullCPU or pass its information to
- // the stages.
+ // Typedef of iterator through the list of instructions.
typedef typename std::list<DynInstPtr>::iterator ListIt;
- /**
- * Struct for comparing entries to be added to the priority queue. This
- * gives reverse ordering to the instructions in terms of sequence
- * numbers: the instructions with smaller sequence numbers (and hence
- * are older) will be at the top of the priority queue.
- */
- struct pqCompare
- {
- bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
- {
- return lhs->seqNum > rhs->seqNum;
- }
- };
+ friend class Impl::FullCPU;
- /**
- * Struct for comparing entries to be added to the set. This gives
- * standard ordering in terms of sequence numbers.
- */
- struct setCompare
- {
- bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
- {
- return lhs->seqNum < rhs->seqNum;
- }
+ /** FU completion event class. */
+ class FUCompletion : public Event {
+ private:
+ /** Executing instruction. */
+ DynInstPtr inst;
+
+ /** Index of the FU used for executing. */
+ int fuIdx;
+
+ /** Pointer back to the instruction queue. */
+ InstructionQueue<Impl> *iqPtr;
+
+ bool freeFU;
+
+ public:
+ /** Construct a FU completion event. */
+ FUCompletion(DynInstPtr &_inst, int fu_idx,
+ InstructionQueue<Impl> *iq_ptr);
+
+ virtual void process();
+ virtual const char *description();
+ void setFreeFU() { freeFU = true; }
};
- typedef std::priority_queue<DynInstPtr, vector<DynInstPtr>, pqCompare>
- ReadyInstQueue;
+ /** Constructs an IQ. */
+ InstructionQueue(Params *params);
- InstructionQueue(Params &params);
+ /** Destructs the IQ. */
+ ~InstructionQueue();
+ /** Returns the name of the IQ. */
+ std::string name() const;
+
+ /** Registers statistics. */
void regStats();
- void setCPU(FullCPU *cpu);
+ void resetState();
+
+ /** Sets CPU pointer. */
+ void setCPU(FullCPU *_cpu) { cpu = _cpu; }
+ /** Sets active threads list. */
+ void setActiveThreads(std::list<unsigned> *at_ptr);
+
+ /** Sets the IEW pointer. */
+ void setIEW(IEW *iew_ptr) { iewStage = iew_ptr; }
+
+ /** Sets the timer buffer between issue and execute. */
void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
+ /** Sets the global time buffer. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
+ void switchOut();
+
+ void takeOverFrom();
+
+ bool isSwitchedOut() { return switchedOut; }
+
+ /** Number of entries needed for given amount of threads. */
+ int entryAmount(int num_threads);
+
+ /** Resets max entries for all threads. */
+ void resetEntries();
+
+ /** Returns total number of free entries. */
unsigned numFreeEntries();
+ /** Returns number of free entries for a thread. */
+ unsigned numFreeEntries(unsigned tid);
+
+ /** Returns whether or not the IQ is full. */
bool isFull();
+ /** Returns whether or not the IQ is full for a specific thread. */
+ bool isFull(unsigned tid);
+
+ /** Returns if there are any ready instructions in the IQ. */
+ bool hasReadyInsts();
+
+ /** Inserts a new instruction into the IQ. */
void insert(DynInstPtr &new_inst);
+ /** Inserts a new, non-speculative instruction into the IQ. */
void insertNonSpec(DynInstPtr &new_inst);
- void advanceTail(DynInstPtr &inst);
+ /** Inserts a memory or write barrier into the IQ to make sure
+ * loads and stores are ordered properly.
+ */
+ void insertBarrier(DynInstPtr &barr_inst);
+ DynInstPtr getInstToExecute();
+
+ /**
+ * Records the instruction as the producer of a register without
+ * adding it to the rest of the IQ.
+ */
+ void recordProducer(DynInstPtr &inst)
+ { addToProducers(inst); }
+
+ /** Process FU completion event. */
+ void processFUCompletion(DynInstPtr &inst, int fu_idx);
+
+ /**
+ * Schedules ready instructions, adding the ready ones (oldest first) to
+ * the queue to execute.
+ */
void scheduleReadyInsts();
+ /** Schedules a single specific non-speculative instruction. */
void scheduleNonSpec(const InstSeqNum &inst);
- void wakeDependents(DynInstPtr &completed_inst);
+ /**
+ * Commits all instructions up to and including the given sequence number,
+ * for a specific thread.
+ */
+ void commit(const InstSeqNum &inst, unsigned tid = 0);
+
+ /** Wakes all dependents of a completed instruction. */
+ int wakeDependents(DynInstPtr &completed_inst);
+
+ /** Adds a ready memory instruction to the ready list. */
+ void addReadyMemInst(DynInstPtr &ready_inst);
+
+ /**
+ * Reschedules a memory instruction. It will be ready to issue once
+ * replayMemInst() is called.
+ */
+ void rescheduleMemInst(DynInstPtr &resched_inst);
+
+ /** Replays a memory instruction. It must be rescheduled first. */
+ void replayMemInst(DynInstPtr &replay_inst);
+ /** Completes a memory operation. */
+ void completeMemInst(DynInstPtr &completed_inst);
+
+ /** Indicates an ordering violation between a store and a load. */
void violation(DynInstPtr &store, DynInstPtr &faulting_load);
- // Change this to take in the sequence number
- void squash();
+ /**
+ * Squashes instructions for a thread. Squashing information is obtained
+ * from the time buffer.
+ */
+ void squash(unsigned tid);
- void doSquash();
+ /** Returns the number of used entries for a thread. */
+ unsigned getCount(unsigned tid) { return count[tid]; };
- void stopSquash();
+ /** Debug function to print all instructions. */
+ void printInsts();
private:
+ /** Does the actual squashing. */
+ void doSquash(unsigned tid);
+
+ /////////////////////////
+ // Various pointers
+ /////////////////////////
+
/** Pointer to the CPU. */
FullCPU *cpu;
+ /** Cache interface. */
+ MemInterface *dcacheInterface;
+
+ /** Pointer to IEW stage. */
+ IEW *iewStage;
+
/** The memory dependence unit, which tracks/predicts memory dependences
* between instructions.
*/
- MemDepUnit memDepUnit;
+ MemDepUnit memDepUnit[Impl::MaxThreads];
/** The queue to the execute stage. Issued instructions will be written
* into it.
@@ -151,36 +264,38 @@ class InstructionQueue
/** Wire to read information from timebuffer. */
typename TimeBuffer<TimeStruct>::wire fromCommit;
- enum InstList {
- Int,
- Float,
- Branch,
- Memory,
- Misc,
- Squashed,
- None
- };
+ /** Function unit pool. */
+ FUPool *fuPool;
- /** List of ready int instructions. Used to keep track of the order in
- * which instructions should issue.
- */
- ReadyInstQueue readyIntInsts;
+ //////////////////////////////////////
+ // Instruction lists, ready queues, and ordering
+ //////////////////////////////////////
- /** List of ready floating point instructions. */
- ReadyInstQueue readyFloatInsts;
+ /** List of all the instructions in the IQ (some of which may be issued). */
+ std::list<DynInstPtr> instList[Impl::MaxThreads];
- /** List of ready branch instructions. */
- ReadyInstQueue readyBranchInsts;
+ std::list<DynInstPtr> instsToExecute;
- /** List of ready miscellaneous instructions. */
- ReadyInstQueue readyMiscInsts;
+ /**
+ * Struct for comparing entries to be added to the priority queue. This
+ * gives reverse ordering to the instructions in terms of sequence
+ * numbers: the instructions with smaller sequence numbers (and hence
+ * are older) will be at the top of the priority queue.
+ */
+ struct pqCompare {
+ bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
+ {
+ return lhs->seqNum > rhs->seqNum;
+ }
+ };
+
+ typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare>
+ ReadyInstQueue;
- /** List of squashed instructions (which are still valid and in IQ).
- * Implemented using a priority queue; the entries must contain both
- * the IQ index and sequence number of each instruction so that
- * ordering based on sequence numbers can be used.
+ /** List of ready instructions, per op class. They are separated by op
+ * class to allow for easy mapping to FUs.
*/
- ReadyInstQueue squashedInsts;
+ ReadyInstQueue readyInsts[Num_OpClasses];
/** List of non-speculative instructions that will be scheduled
* once the IQ gets a signal from commit. While it's redundant to
@@ -191,34 +306,80 @@ class InstructionQueue
*/
std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
- typedef typename std::map<InstSeqNum, DynInstPtr>::iterator non_spec_it_t;
+ typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
- /** Number of free IQ entries left. */
- unsigned freeEntries;
+ /** Entry for the list age ordering by op class. */
+ struct ListOrderEntry {
+ OpClass queueType;
+ InstSeqNum oldestInst;
+ };
- /** The number of entries in the instruction queue. */
- unsigned numEntries;
+ /** List that contains the age order of the oldest instruction of each
+ * ready queue. Used to select the oldest instruction available
+ * among op classes.
+ * @todo: Might be better to just move these entries around instead
+ * of creating new ones every time the position changes due to an
+ * instruction issuing. Not sure std::list supports this.
+ */
+ std::list<ListOrderEntry> listOrder;
+
+ typedef typename std::list<ListOrderEntry>::iterator ListOrderIt;
+
+ /** Tracks if each ready queue is on the age order list. */
+ bool queueOnList[Num_OpClasses];
- /** The number of integer instructions that can be issued in one
- * cycle.
+ /** Iterators of each ready queue. Points to their spot in the age order
+ * list.
*/
- unsigned intWidth;
+ ListOrderIt readyIt[Num_OpClasses];
- /** The number of floating point instructions that can be issued
- * in one cycle.
+ /** Add an op class to the age order list. */
+ void addToOrderList(OpClass op_class);
+
+ /**
+ * Called when the oldest instruction has been removed from a ready queue;
+ * this places that ready queue into the proper spot in the age order list.
*/
- unsigned floatWidth;
+ void moveToYoungerInst(ListOrderIt age_order_it);
+
+ DependencyGraph<DynInstPtr> dependGraph;
+
+ //////////////////////////////////////
+ // Various parameters
+ //////////////////////////////////////
+
+ /** IQ Resource Sharing Policy */
+ enum IQPolicy {
+ Dynamic,
+ Partitioned,
+ Threshold
+ };
+
+ /** IQ sharing policy for SMT. */
+ IQPolicy iqPolicy;
- /** The number of branches that can be issued in one cycle. */
- unsigned branchWidth;
+ /** Number of Total Threads*/
+ unsigned numThreads;
- /** The number of memory instructions that can be issued in one cycle. */
- unsigned memoryWidth;
+ /** Pointer to list of active threads. */
+ std::list<unsigned> *activeThreads;
+
+ /** Per Thread IQ count */
+ unsigned count[Impl::MaxThreads];
+
+ /** Max IQ Entries Per Thread */
+ unsigned maxEntries[Impl::MaxThreads];
+
+ /** Number of free IQ entries left. */
+ unsigned freeEntries;
+
+ /** The number of entries in the instruction queue. */
+ unsigned numEntries;
/** The total number of instructions that can be issued in one cycle. */
unsigned totalWidth;
- //The number of physical registers in the CPU.
+ /** The number of physical registers in the CPU. */
unsigned numPhysRegs;
/** The number of physical integer registers in the CPU. */
@@ -232,55 +393,10 @@ class InstructionQueue
*/
unsigned commitToIEWDelay;
- //////////////////////////////////
- // Variables needed for squashing
- //////////////////////////////////
+ bool switchedOut;
/** The sequence number of the squashed instruction. */
- InstSeqNum squashedSeqNum;
-
- /** Iterator that points to the youngest instruction in the IQ. */
- ListIt tail;
-
- /** Iterator that points to the last instruction that has been squashed.
- * This will not be valid unless the IQ is in the process of squashing.
- */
- ListIt squashIt;
-
- ///////////////////////////////////
- // Dependency graph stuff
- ///////////////////////////////////
-
- class DependencyEntry
- {
- public:
- DynInstPtr inst;
- //Might want to include data about what arch. register the
- //dependence is waiting on.
- DependencyEntry *next;
-
- //This function, and perhaps this whole class, stand out a little
- //bit as they don't fit a classification well. I want access
- //to the underlying structure of the linked list, yet at
- //the same time it feels like this should be something abstracted
- //away. So for now it will sit here, within the IQ, until
- //a better implementation is decided upon.
- // This function probably shouldn't be within the entry...
- void insert(DynInstPtr &new_inst);
-
- void remove(DynInstPtr &inst_to_remove);
-
- // Debug variable, remove when done testing.
- static unsigned mem_alloc_counter;
- };
-
- /** Array of linked lists. Each linked list is a list of all the
- * instructions that depend upon a given register. The actual
- * register's index is used to index into the graph; ie all
- * instructions in flight that are dependent upon r34 will be
- * in the linked list of dependGraph[34].
- */
- DependencyEntry *dependGraph;
+ InstSeqNum squashedSeqNum[Impl::MaxThreads];
/** A cache of the recently woken registers. It is 1 if the register
* has been woken up recently, and 0 if the register has been added
@@ -288,49 +404,76 @@ class InstructionQueue
* is basically a secondary scoreboard, and should pretty much mirror
* the scoreboard that exists in the rename map.
*/
- vector<bool> regScoreboard;
+ std::vector<bool> regScoreboard;
+ /** Adds an instruction to the dependency graph, as a consumer. */
bool addToDependents(DynInstPtr &new_inst);
- void insertDependency(DynInstPtr &new_inst);
- void createDependency(DynInstPtr &new_inst);
+ /** Adds an instruction to the dependency graph, as a producer. */
+ void addToProducers(DynInstPtr &new_inst);
+
+ /** Moves an instruction to the ready queue if it is ready. */
void addIfReady(DynInstPtr &inst);
- private:
/** Debugging function to count how many entries are in the IQ. It does
* a linear walk through the instructions, so do not call this function
* during normal execution.
*/
int countInsts();
- /** Debugging function to dump out the dependency graph.
- */
- void dumpDependGraph();
-
/** Debugging function to dump all the list sizes, as well as print
* out the list of nonspeculative instructions. Should not be used
* in any other capacity, but it has no harmful sideaffects.
*/
void dumpLists();
+ /** Debugging function to dump out all instructions that are in the
+ * IQ.
+ */
+ void dumpInsts();
+
+ /** Stat for number of instructions added. */
Stats::Scalar<> iqInstsAdded;
+ /** Stat for number of non-speculative instructions added. */
Stats::Scalar<> iqNonSpecInstsAdded;
-// Stats::Scalar<> iqIntInstsAdded;
+
+ Stats::Scalar<> iqInstsIssued;
+ /** Stat for number of integer instructions issued. */
Stats::Scalar<> iqIntInstsIssued;
-// Stats::Scalar<> iqFloatInstsAdded;
+ /** Stat for number of floating point instructions issued. */
Stats::Scalar<> iqFloatInstsIssued;
-// Stats::Scalar<> iqBranchInstsAdded;
+ /** Stat for number of branch instructions issued. */
Stats::Scalar<> iqBranchInstsIssued;
-// Stats::Scalar<> iqMemInstsAdded;
+ /** Stat for number of memory instructions issued. */
Stats::Scalar<> iqMemInstsIssued;
-// Stats::Scalar<> iqMiscInstsAdded;
+ /** Stat for number of miscellaneous instructions issued. */
Stats::Scalar<> iqMiscInstsIssued;
+ /** Stat for number of squashed instructions that were ready to issue. */
Stats::Scalar<> iqSquashedInstsIssued;
- Stats::Scalar<> iqLoopSquashStalls;
+ /** Stat for number of squashed instructions examined when squashing. */
Stats::Scalar<> iqSquashedInstsExamined;
+ /** Stat for number of squashed instruction operands examined when
+ * squashing.
+ */
Stats::Scalar<> iqSquashedOperandsExamined;
+ /** Stat for number of non-speculative instructions removed due to a squash.
+ */
Stats::Scalar<> iqSquashedNonSpecRemoved;
+ Stats::VectorDistribution<> queueResDist;
+ Stats::Distribution<> numIssuedDist;
+ Stats::VectorDistribution<> issueDelayDist;
+
+ Stats::Vector<> statFuBusy;
+// Stats::Vector<> dist_unissued;
+ Stats::Vector2d<> statIssuedInstType;
+
+ Stats::Formula issueRate;
+// Stats::Formula issue_stores;
+// Stats::Formula issue_op_rate;
+ Stats::Vector<> fuBusy; //cumulative fu busy
+
+ Stats::Formula fuBusyRate;
};
-#endif //__CPU_O3_CPU_INST_QUEUE_HH__
+#endif //__CPU_O3_INST_QUEUE_HH__
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 048dc7c00..f1dc4e01f 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,73 +26,147 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-// Todo:
-// Current ordering allows for 0 cycle added-to-scheduled. Could maybe fake
-// it; either do in reverse order, or have added instructions put into a
-// different ready queue that, in scheduleRreadyInsts(), gets put onto the
-// normal ready queue. This would however give only a one cycle delay,
-// but probably is more flexible to actually add in a delay parameter than
-// just running it backwards.
-
#include <limits>
#include <vector>
#include "sim/root.hh"
+#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/inst_queue.hh"
-// Either compile error or max int due to sign extension.
-// Hack to avoid compile warnings.
-const InstSeqNum MaxInstSeqNum = std::numeric_limits<InstSeqNum>::max();
+using namespace std;
template <class Impl>
-InstructionQueue<Impl>::InstructionQueue(Params &params)
- : memDepUnit(params),
- numEntries(params.numIQEntries),
- intWidth(params.executeIntWidth),
- floatWidth(params.executeFloatWidth),
- branchWidth(params.executeBranchWidth),
- memoryWidth(params.executeMemoryWidth),
- totalWidth(params.issueWidth),
- numPhysIntRegs(params.numPhysIntRegs),
- numPhysFloatRegs(params.numPhysFloatRegs),
- commitToIEWDelay(params.commitToIEWDelay)
+InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
+ int fu_idx,
+ InstructionQueue<Impl> *iq_ptr)
+ : Event(&mainEventQueue, Stat_Event_Pri),
+ inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
{
- // Initialize the number of free IQ entries.
- freeEntries = numEntries;
+ this->setFlags(Event::AutoDelete);
+}
+
+template <class Impl>
+void
+InstructionQueue<Impl>::FUCompletion::process()
+{
+ iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
+ inst = NULL;
+}
+
+
+template <class Impl>
+const char *
+InstructionQueue<Impl>::FUCompletion::description()
+{
+ return "Functional unit completion event";
+}
+
+template <class Impl>
+InstructionQueue<Impl>::InstructionQueue(Params *params)
+ : dcacheInterface(params->dcacheInterface),
+ fuPool(params->fuPool),
+ numEntries(params->numIQEntries),
+ totalWidth(params->issueWidth),
+ numPhysIntRegs(params->numPhysIntRegs),
+ numPhysFloatRegs(params->numPhysFloatRegs),
+ commitToIEWDelay(params->commitToIEWDelay)
+{
+ assert(fuPool);
+
+ switchedOut = false;
+
+ numThreads = params->numberOfThreads;
// Set the number of physical registers as the number of int + float
numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
- DPRINTF(IQ, "IQ: There are %i physical registers.\n", numPhysRegs);
+ DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs);
//Create an entry for each physical register within the
//dependency graph.
- dependGraph = new DependencyEntry[numPhysRegs];
+ dependGraph.resize(numPhysRegs);
// Resize the register scoreboard.
regScoreboard.resize(numPhysRegs);
- // Initialize all the head pointers to point to NULL, and all the
- // entries as unready.
- // Note that in actuality, the registers corresponding to the logical
- // registers start off as ready. However this doesn't matter for the
- // IQ as the instruction should have been correctly told if those
- // registers are ready in rename. Thus it can all be initialized as
- // unready.
- for (int i = 0; i < numPhysRegs; ++i)
- {
- dependGraph[i].next = NULL;
- dependGraph[i].inst = NULL;
- regScoreboard[i] = false;
+ //Initialize Mem Dependence Units
+ for (int i = 0; i < numThreads; i++) {
+ memDepUnit[i].init(params,i);
+ memDepUnit[i].setIQ(this);
}
+ resetState();
+
+ string policy = params->smtIQPolicy;
+
+ //Convert string to lowercase
+ std::transform(policy.begin(), policy.end(), policy.begin(),
+ (int(*)(int)) tolower);
+
+ //Figure out resource sharing policy
+ if (policy == "dynamic") {
+ iqPolicy = Dynamic;
+
+ //Set Max Entries to Total ROB Capacity
+ for (int i = 0; i < numThreads; i++) {
+ maxEntries[i] = numEntries;
+ }
+
+ } else if (policy == "partitioned") {
+ iqPolicy = Partitioned;
+
+ //@todo:make work if part_amt doesnt divide evenly.
+ int part_amt = numEntries / numThreads;
+
+ //Divide ROB up evenly
+ for (int i = 0; i < numThreads; i++) {
+ maxEntries[i] = part_amt;
+ }
+
+ DPRINTF(Fetch, "IQ sharing policy set to Partitioned:"
+ "%i entries per thread.\n",part_amt);
+
+ } else if (policy == "threshold") {
+ iqPolicy = Threshold;
+
+ double threshold = (double)params->smtIQThreshold / 100;
+
+ int thresholdIQ = (int)((double)threshold * numEntries);
+
+ //Divide up by threshold amount
+ for (int i = 0; i < numThreads; i++) {
+ maxEntries[i] = thresholdIQ;
+ }
+
+ DPRINTF(Fetch, "IQ sharing policy set to Threshold:"
+ "%i entries per thread.\n",thresholdIQ);
+ } else {
+ assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
+ "Partitioned, Threshold}");
+ }
+}
+
+template <class Impl>
+InstructionQueue<Impl>::~InstructionQueue()
+{
+ dependGraph.reset();
+ cprintf("Nodes traversed: %i, removed: %i\n",
+ dependGraph.nodesTraversed, dependGraph.nodesRemoved);
+}
+
+template <class Impl>
+std::string
+InstructionQueue<Impl>::name() const
+{
+ return cpu->name() + ".iq";
}
template <class Impl>
void
InstructionQueue<Impl>::regStats()
{
+ using namespace Stats;
iqInstsAdded
.name(name() + ".iqInstsAdded")
.desc("Number of instructions added to the IQ (excludes non-spec)")
@@ -103,36 +177,31 @@ InstructionQueue<Impl>::regStats()
.desc("Number of non-speculative instructions added to the IQ")
.prereq(iqNonSpecInstsAdded);
-// iqIntInstsAdded;
+ iqInstsIssued
+ .name(name() + ".iqInstsIssued")
+ .desc("Number of instructions issued")
+ .prereq(iqInstsIssued);
iqIntInstsIssued
.name(name() + ".iqIntInstsIssued")
.desc("Number of integer instructions issued")
.prereq(iqIntInstsIssued);
-// iqFloatInstsAdded;
-
iqFloatInstsIssued
.name(name() + ".iqFloatInstsIssued")
.desc("Number of float instructions issued")
.prereq(iqFloatInstsIssued);
-// iqBranchInstsAdded;
-
iqBranchInstsIssued
.name(name() + ".iqBranchInstsIssued")
.desc("Number of branch instructions issued")
.prereq(iqBranchInstsIssued);
-// iqMemInstsAdded;
-
iqMemInstsIssued
.name(name() + ".iqMemInstsIssued")
.desc("Number of memory instructions issued")
.prereq(iqMemInstsIssued);
-// iqMiscInstsAdded;
-
iqMiscInstsIssued
.name(name() + ".iqMiscInstsIssued")
.desc("Number of miscellaneous instructions issued")
@@ -143,12 +212,6 @@ InstructionQueue<Impl>::regStats()
.desc("Number of squashed instructions issued")
.prereq(iqSquashedInstsIssued);
- iqLoopSquashStalls
- .name(name() + ".iqLoopSquashStalls")
- .desc("Number of times issue loop had to restart due to squashed "
- "inst; mainly for profiling")
- .prereq(iqLoopSquashStalls);
-
iqSquashedInstsExamined
.name(name() + ".iqSquashedInstsExamined")
.desc("Number of squashed instructions iterated over during squash;"
@@ -166,25 +229,158 @@ InstructionQueue<Impl>::regStats()
.desc("Number of squashed non-spec instructions that were removed")
.prereq(iqSquashedNonSpecRemoved);
- // Tell mem dependence unit to reg stats as well.
- memDepUnit.regStats();
+ queueResDist
+ .init(Num_OpClasses, 0, 99, 2)
+ .name(name() + ".IQ:residence:")
+ .desc("cycles from dispatch to issue")
+ .flags(total | pdf | cdf )
+ ;
+ for (int i = 0; i < Num_OpClasses; ++i) {
+ queueResDist.subname(i, opClassStrings[i]);
+ }
+ numIssuedDist
+ .init(0,totalWidth,1)
+ .name(name() + ".ISSUE:issued_per_cycle")
+ .desc("Number of insts issued each cycle")
+ .flags(pdf)
+ ;
+/*
+ dist_unissued
+ .init(Num_OpClasses+2)
+ .name(name() + ".ISSUE:unissued_cause")
+ .desc("Reason ready instruction not issued")
+ .flags(pdf | dist)
+ ;
+ for (int i=0; i < (Num_OpClasses + 2); ++i) {
+ dist_unissued.subname(i, unissued_names[i]);
+ }
+*/
+ statIssuedInstType
+ .init(numThreads,Num_OpClasses)
+ .name(name() + ".ISSUE:FU_type")
+ .desc("Type of FU issued")
+ .flags(total | pdf | dist)
+ ;
+ statIssuedInstType.ysubnames(opClassStrings);
+
+ //
+ // How long did instructions for a particular FU type wait prior to issue
+ //
+
+ issueDelayDist
+ .init(Num_OpClasses,0,99,2)
+ .name(name() + ".ISSUE:")
+ .desc("cycles from operands ready to issue")
+ .flags(pdf | cdf)
+ ;
+
+ for (int i=0; i<Num_OpClasses; ++i) {
+ stringstream subname;
+ subname << opClassStrings[i] << "_delay";
+ issueDelayDist.subname(i, subname.str());
+ }
+
+ issueRate
+ .name(name() + ".ISSUE:rate")
+ .desc("Inst issue rate")
+ .flags(total)
+ ;
+ issueRate = iqInstsIssued / cpu->numCycles;
+/*
+ issue_stores
+ .name(name() + ".ISSUE:stores")
+ .desc("Number of stores issued")
+ .flags(total)
+ ;
+ issue_stores = exe_refs - exe_loads;
+*/
+/*
+ issue_op_rate
+ .name(name() + ".ISSUE:op_rate")
+ .desc("Operation issue rate")
+ .flags(total)
+ ;
+ issue_op_rate = issued_ops / numCycles;
+*/
+ statFuBusy
+ .init(Num_OpClasses)
+ .name(name() + ".ISSUE:fu_full")
+ .desc("attempts to use FU when none available")
+ .flags(pdf | dist)
+ ;
+ for (int i=0; i < Num_OpClasses; ++i) {
+ statFuBusy.subname(i, opClassStrings[i]);
+ }
+
+ fuBusy
+ .init(numThreads)
+ .name(name() + ".ISSUE:fu_busy_cnt")
+ .desc("FU busy when requested")
+ .flags(total)
+ ;
+
+ fuBusyRate
+ .name(name() + ".ISSUE:fu_busy_rate")
+ .desc("FU busy rate (busy events/executed inst)")
+ .flags(total)
+ ;
+ fuBusyRate = fuBusy / iqInstsIssued;
+
+ for ( int i=0; i < numThreads; i++) {
+ // Tell mem dependence unit to reg stats as well.
+ memDepUnit[i].regStats();
+ }
}
template <class Impl>
void
-InstructionQueue<Impl>::setCPU(FullCPU *cpu_ptr)
+InstructionQueue<Impl>::resetState()
{
- cpu = cpu_ptr;
+ //Initialize thread IQ counts
+ for (int i = 0; i <numThreads; i++) {
+ count[i] = 0;
+ instList[i].clear();
+ }
+
+ // Initialize the number of free IQ entries.
+ freeEntries = numEntries;
+
+ // Note that in actuality, the registers corresponding to the logical
+ // registers start off as ready. However this doesn't matter for the
+ // IQ as the instruction should have been correctly told if those
+ // registers are ready in rename. Thus it can all be initialized as
+ // unready.
+ for (int i = 0; i < numPhysRegs; ++i) {
+ regScoreboard[i] = false;
+ }
+
+ for (int i = 0; i < numThreads; ++i) {
+ squashedSeqNum[i] = 0;
+ }
+
+ for (int i = 0; i < Num_OpClasses; ++i) {
+ while (!readyInsts[i].empty())
+ readyInsts[i].pop();
+ queueOnList[i] = false;
+ readyIt[i] = listOrder.end();
+ }
+ nonSpecInsts.clear();
+ listOrder.clear();
+}
- tail = cpu->instList.begin();
+template <class Impl>
+void
+InstructionQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+{
+ DPRINTF(IQ, "Setting active threads list pointer.\n");
+ activeThreads = at_ptr;
}
template <class Impl>
void
-InstructionQueue<Impl>::setIssueToExecuteQueue(
- TimeBuffer<IssueStruct> *i2e_ptr)
+InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
{
- DPRINTF(IQ, "IQ: Set the issue to execute queue.\n");
+ DPRINTF(IQ, "Set the issue to execute queue.\n");
issueToExecuteQueue = i2e_ptr;
}
@@ -192,19 +388,77 @@ template <class Impl>
void
InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
{
- DPRINTF(IQ, "IQ: Set the time buffer.\n");
+ DPRINTF(IQ, "Set the time buffer.\n");
timeBuffer = tb_ptr;
fromCommit = timeBuffer->getWire(-commitToIEWDelay);
}
template <class Impl>
+void
+InstructionQueue<Impl>::switchOut()
+{
+ resetState();
+ dependGraph.reset();
+ switchedOut = true;
+ for (int i = 0; i < numThreads; ++i) {
+ memDepUnit[i].switchOut();
+ }
+}
+
+template <class Impl>
+void
+InstructionQueue<Impl>::takeOverFrom()
+{
+ switchedOut = false;
+}
+
+template <class Impl>
+int
+InstructionQueue<Impl>::entryAmount(int num_threads)
+{
+ if (iqPolicy == Partitioned) {
+ return numEntries / num_threads;
+ } else {
+ return 0;
+ }
+}
+
+
+template <class Impl>
+void
+InstructionQueue<Impl>::resetEntries()
+{
+ if (iqPolicy != Dynamic || numThreads > 1) {
+ int active_threads = (*activeThreads).size();
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+ list<unsigned>::iterator list_end = (*activeThreads).end();
+
+ while (threads != list_end) {
+ if (iqPolicy == Partitioned) {
+ maxEntries[*threads++] = numEntries / active_threads;
+ } else if(iqPolicy == Threshold && active_threads == 1) {
+ maxEntries[*threads++] = numEntries;
+ }
+ }
+ }
+}
+
+template <class Impl>
unsigned
InstructionQueue<Impl>::numFreeEntries()
{
return freeEntries;
}
+template <class Impl>
+unsigned
+InstructionQueue<Impl>::numFreeEntries(unsigned tid)
+{
+ return maxEntries[tid] - count[tid];
+}
+
// Might want to do something more complex if it knows how many instructions
// will be issued this cycle.
template <class Impl>
@@ -219,447 +473,420 @@ InstructionQueue<Impl>::isFull()
}
template <class Impl>
+bool
+InstructionQueue<Impl>::isFull(unsigned tid)
+{
+ if (numFreeEntries(tid) == 0) {
+ return(true);
+ } else {
+ return(false);
+ }
+}
+
+template <class Impl>
+bool
+InstructionQueue<Impl>::hasReadyInsts()
+{
+ if (!listOrder.empty()) {
+ return true;
+ }
+
+ for (int i = 0; i < Num_OpClasses; ++i) {
+ if (!readyInsts[i].empty()) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+template <class Impl>
void
InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
{
// Make sure the instruction is valid
assert(new_inst);
- DPRINTF(IQ, "IQ: Adding instruction PC %#x to the IQ.\n",
- new_inst->readPC());
+ DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n",
+ new_inst->seqNum, new_inst->readPC());
- // Check if there are any free entries. Panic if there are none.
- // Might want to have this return a fault in the future instead of
- // panicing.
assert(freeEntries != 0);
- // If the IQ currently has nothing in it, then there's a possibility
- // that the tail iterator is invalid (might have been pointing at an
- // instruction that was retired). Reset the tail iterator.
- if (freeEntries == numEntries) {
- tail = cpu->instList.begin();
- }
-
- // Move the tail iterator. Instructions may not have been issued
- // to the IQ, so we may have to increment the iterator more than once.
- while ((*tail) != new_inst) {
- tail++;
-
- // Make sure the tail iterator points at something legal.
- assert(tail != cpu->instList.end());
- }
-
+ instList[new_inst->threadNumber].push_back(new_inst);
- // Decrease the number of free entries.
--freeEntries;
+ new_inst->setInIQ();
+
// Look through its source registers (physical regs), and mark any
// dependencies.
addToDependents(new_inst);
// Have this instruction set itself as the producer of its destination
// register(s).
- createDependency(new_inst);
+ addToProducers(new_inst);
- // If it's a memory instruction, add it to the memory dependency
- // unit.
if (new_inst->isMemRef()) {
- memDepUnit.insert(new_inst);
- // Uh..forgot to look it up and put it on the proper dependency list
- // if the instruction should not go yet.
+ memDepUnit[new_inst->threadNumber].insert(new_inst);
} else {
- // If the instruction is ready then add it to the ready list.
addIfReady(new_inst);
}
++iqInstsAdded;
+ count[new_inst->threadNumber]++;
+
assert(freeEntries == (numEntries - countInsts()));
}
template <class Impl>
void
-InstructionQueue<Impl>::insertNonSpec(DynInstPtr &inst)
+InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
{
- nonSpecInsts[inst->seqNum] = inst;
-
// @todo: Clean up this code; can do it by setting inst as unable
// to issue, then calling normal insert on the inst.
- // Make sure the instruction is valid
- assert(inst);
-
- DPRINTF(IQ, "IQ: Adding instruction PC %#x to the IQ.\n",
- inst->readPC());
+ assert(new_inst);
- // Check if there are any free entries. Panic if there are none.
- // Might want to have this return a fault in the future instead of
- // panicing.
- assert(freeEntries != 0);
+ nonSpecInsts[new_inst->seqNum] = new_inst;
- // If the IQ currently has nothing in it, then there's a possibility
- // that the tail iterator is invalid (might have been pointing at an
- // instruction that was retired). Reset the tail iterator.
- if (freeEntries == numEntries) {
- tail = cpu->instList.begin();
- }
+ DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x "
+ "to the IQ.\n",
+ new_inst->seqNum, new_inst->readPC());
- // Move the tail iterator. Instructions may not have been issued
- // to the IQ, so we may have to increment the iterator more than once.
- while ((*tail) != inst) {
- tail++;
+ assert(freeEntries != 0);
- // Make sure the tail iterator points at something legal.
- assert(tail != cpu->instList.end());
- }
+ instList[new_inst->threadNumber].push_back(new_inst);
- // Decrease the number of free entries.
--freeEntries;
+ new_inst->setInIQ();
+
// Have this instruction set itself as the producer of its destination
// register(s).
- createDependency(inst);
+ addToProducers(new_inst);
// If it's a memory instruction, add it to the memory dependency
// unit.
- if (inst->isMemRef()) {
- memDepUnit.insertNonSpec(inst);
+ if (new_inst->isMemRef()) {
+ memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
}
++iqNonSpecInstsAdded;
+
+ count[new_inst->threadNumber]++;
+
+ assert(freeEntries == (numEntries - countInsts()));
}
-// Slightly hack function to advance the tail iterator in the case that
-// the IEW stage issues an instruction that is not added to the IQ. This
-// is needed in case a long chain of such instructions occurs.
-// I don't think this is used anymore.
template <class Impl>
void
-InstructionQueue<Impl>::advanceTail(DynInstPtr &inst)
+InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
{
- // Make sure the instruction is valid
- assert(inst);
-
- DPRINTF(IQ, "IQ: Adding instruction PC %#x to the IQ.\n",
- inst->readPC());
-
- // Check if there are any free entries. Panic if there are none.
- // Might want to have this return a fault in the future instead of
- // panicing.
- assert(freeEntries != 0);
-
- // If the IQ currently has nothing in it, then there's a possibility
- // that the tail iterator is invalid (might have been pointing at an
- // instruction that was retired). Reset the tail iterator.
- if (freeEntries == numEntries) {
- tail = cpu->instList.begin();
- }
-
- // Move the tail iterator. Instructions may not have been issued
- // to the IQ, so we may have to increment the iterator more than once.
- while ((*tail) != inst) {
- tail++;
-
- // Make sure the tail iterator points at something legal.
- assert(tail != cpu->instList.end());
- }
+ memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
- assert(freeEntries <= numEntries);
+ insertNonSpec(barr_inst);
+}
- // Have this instruction set itself as the producer of its destination
- // register(s).
- createDependency(inst);
+template <class Impl>
+typename Impl::DynInstPtr
+InstructionQueue<Impl>::getInstToExecute()
+{
+ assert(!instsToExecute.empty());
+ DynInstPtr inst = instsToExecute.front();
+ instsToExecute.pop_front();
+ return inst;
}
-// Need to make sure the number of float and integer instructions
-// issued does not exceed the total issue bandwidth.
-// @todo: Figure out a better way to remove the squashed items from the
-// lists. Checking the top item of each list to see if it's squashed
-// wastes time and forces jumps.
template <class Impl>
void
-InstructionQueue<Impl>::scheduleReadyInsts()
+InstructionQueue<Impl>::addToOrderList(OpClass op_class)
{
- DPRINTF(IQ, "IQ: Attempting to schedule ready instructions from "
- "the IQ.\n");
-
- int int_issued = 0;
- int float_issued = 0;
- int branch_issued = 0;
- int memory_issued = 0;
- int squashed_issued = 0;
- int total_issued = 0;
-
- IssueStruct *i2e_info = issueToExecuteQueue->access(0);
+ assert(!readyInsts[op_class].empty());
- bool insts_available = !readyBranchInsts.empty() ||
- !readyIntInsts.empty() ||
- !readyFloatInsts.empty() ||
- !memDepUnit.empty() ||
- !readyMiscInsts.empty() ||
- !squashedInsts.empty();
-
- // Note: Requires a globally defined constant.
- InstSeqNum oldest_inst = MaxInstSeqNum;
- InstList list_with_oldest = None;
-
- // Temporary values.
- DynInstPtr int_head_inst;
- DynInstPtr float_head_inst;
- DynInstPtr branch_head_inst;
- DynInstPtr mem_head_inst;
- DynInstPtr misc_head_inst;
- DynInstPtr squashed_head_inst;
-
- // Somewhat nasty code to look at all of the lists where issuable
- // instructions are located, and choose the oldest instruction among
- // those lists. Consider a rewrite in the future.
- while (insts_available && total_issued < totalWidth)
- {
- // Set this to false. Each if-block is required to set it to true
- // if there were instructions available this check. This will cause
- // this loop to run once more than necessary, but avoids extra calls.
- insts_available = false;
-
- oldest_inst = MaxInstSeqNum;
-
- list_with_oldest = None;
-
- if (!readyIntInsts.empty() &&
- int_issued < intWidth) {
+ ListOrderEntry queue_entry;
- insts_available = true;
+ queue_entry.queueType = op_class;
- int_head_inst = readyIntInsts.top();
+ queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
- if (int_head_inst->isSquashed()) {
- readyIntInsts.pop();
+ ListOrderIt list_it = listOrder.begin();
+ ListOrderIt list_end_it = listOrder.end();
- ++iqLoopSquashStalls;
-
- continue;
- }
-
- oldest_inst = int_head_inst->seqNum;
-
- list_with_oldest = Int;
+ while (list_it != list_end_it) {
+ if ((*list_it).oldestInst > queue_entry.oldestInst) {
+ break;
}
- if (!readyFloatInsts.empty() &&
- float_issued < floatWidth) {
-
- insts_available = true;
-
- float_head_inst = readyFloatInsts.top();
-
- if (float_head_inst->isSquashed()) {
- readyFloatInsts.pop();
-
- ++iqLoopSquashStalls;
+ list_it++;
+ }
- continue;
- } else if (float_head_inst->seqNum < oldest_inst) {
- oldest_inst = float_head_inst->seqNum;
+ readyIt[op_class] = listOrder.insert(list_it, queue_entry);
+ queueOnList[op_class] = true;
+}
- list_with_oldest = Float;
- }
- }
+template <class Impl>
+void
+InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
+{
+ // Get iterator of next item on the list
+ // Delete the original iterator
+ // Determine if the next item is either the end of the list or younger
+ // than the new instruction. If so, then add in a new iterator right here.
+ // If not, then move along.
+ ListOrderEntry queue_entry;
+ OpClass op_class = (*list_order_it).queueType;
+ ListOrderIt next_it = list_order_it;
+
+ ++next_it;
+
+ queue_entry.queueType = op_class;
+ queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
+
+ while (next_it != listOrder.end() &&
+ (*next_it).oldestInst < queue_entry.oldestInst) {
+ ++next_it;
+ }
- if (!readyBranchInsts.empty() &&
- branch_issued < branchWidth) {
+ readyIt[op_class] = listOrder.insert(next_it, queue_entry);
+}
- insts_available = true;
+template <class Impl>
+void
+InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
+{
+ // The CPU could have been sleeping until this op completed (*extremely*
+ // long latency op). Wake it if it was. This may be overkill.
+ if (isSwitchedOut()) {
+ return;
+ }
- branch_head_inst = readyBranchInsts.top();
+ iewStage->wakeCPU();
- if (branch_head_inst->isSquashed()) {
- readyBranchInsts.pop();
+ if (fu_idx > -1)
+ fuPool->freeUnitNextCycle(fu_idx);
- ++iqLoopSquashStalls;
+ // @todo: Ensure that these FU Completions happen at the beginning
+ // of a cycle, otherwise they could add too many instructions to
+ // the queue.
+ // @todo: This could break if there's multiple multi-cycle ops
+ // finishing on this cycle. Maybe implement something like
+ // instToCommit in iew_impl.hh.
+ issueToExecuteQueue->access(0)->size++;
+ instsToExecute.push_back(inst);
+// int &size = issueToExecuteQueue->access(0)->size;
- continue;
- } else if (branch_head_inst->seqNum < oldest_inst) {
- oldest_inst = branch_head_inst->seqNum;
+// issueToExecuteQueue->access(0)->insts[size++] = inst;
+}
- list_with_oldest = Branch;
- }
+// @todo: Figure out a better way to remove the squashed items from the
+// lists. Checking the top item of each list to see if it's squashed
+// wastes time and forces jumps.
+template <class Impl>
+void
+InstructionQueue<Impl>::scheduleReadyInsts()
+{
+ DPRINTF(IQ, "Attempting to schedule ready instructions from "
+ "the IQ.\n");
- }
+ IssueStruct *i2e_info = issueToExecuteQueue->access(0);
- if (!memDepUnit.empty() &&
- memory_issued < memoryWidth) {
+ // Have iterator to head of the list
+ // While I haven't exceeded bandwidth or reached the end of the list,
+ // Try to get a FU that can do what this op needs.
+ // If successful, change the oldestInst to the new top of the list, put
+ // the queue in the proper place in the list.
+ // Increment the iterator.
+ // This will avoid trying to schedule a certain op class if there are no
+ // FUs that handle it.
+ ListOrderIt order_it = listOrder.begin();
+ ListOrderIt order_end_it = listOrder.end();
+ int total_issued = 0;
- insts_available = true;
+ while (total_issued < totalWidth &&
+ order_it != order_end_it) {
+ OpClass op_class = (*order_it).queueType;
- mem_head_inst = memDepUnit.top();
+ assert(!readyInsts[op_class].empty());
- if (mem_head_inst->isSquashed()) {
- memDepUnit.pop();
+ DynInstPtr issuing_inst = readyInsts[op_class].top();
- ++iqLoopSquashStalls;
+ assert(issuing_inst->seqNum == (*order_it).oldestInst);
- continue;
- } else if (mem_head_inst->seqNum < oldest_inst) {
- oldest_inst = mem_head_inst->seqNum;
+ if (issuing_inst->isSquashed()) {
+ readyInsts[op_class].pop();
- list_with_oldest = Memory;
+ if (!readyInsts[op_class].empty()) {
+ moveToYoungerInst(order_it);
+ } else {
+ readyIt[op_class] = listOrder.end();
+ queueOnList[op_class] = false;
}
- }
-
- if (!readyMiscInsts.empty()) {
- insts_available = true;
+ listOrder.erase(order_it++);
- misc_head_inst = readyMiscInsts.top();
+ ++iqSquashedInstsIssued;
- if (misc_head_inst->isSquashed()) {
- readyMiscInsts.pop();
-
- ++iqLoopSquashStalls;
-
- continue;
- } else if (misc_head_inst->seqNum < oldest_inst) {
- oldest_inst = misc_head_inst->seqNum;
-
- list_with_oldest = Misc;
- }
+ continue;
}
- if (!squashedInsts.empty()) {
+ int idx = -2;
+ int op_latency = 1;
+ int tid = issuing_inst->threadNumber;
- insts_available = true;
+ if (op_class != No_OpClass) {
+ idx = fuPool->getUnit(op_class);
- squashed_head_inst = squashedInsts.top();
-
- if (squashed_head_inst->seqNum < oldest_inst) {
- list_with_oldest = Squashed;
+ if (idx > -1) {
+ op_latency = fuPool->getOpLatency(op_class);
}
-
}
- DynInstPtr issuing_inst = NULL;
-
- switch (list_with_oldest) {
- case None:
- DPRINTF(IQ, "IQ: Not able to schedule any instructions. Issuing "
- "inst is %#x.\n", issuing_inst);
- break;
+ if (idx == -2 || idx != -1) {
+ if (op_latency == 1) {
+// i2e_info->insts[exec_queue_slot++] = issuing_inst;
+ i2e_info->size++;
+ instsToExecute.push_back(issuing_inst);
- case Int:
- issuing_inst = int_head_inst;
- readyIntInsts.pop();
- ++int_issued;
- DPRINTF(IQ, "IQ: Issuing integer instruction PC %#x.\n",
- issuing_inst->readPC());
- break;
-
- case Float:
- issuing_inst = float_head_inst;
- readyFloatInsts.pop();
- ++float_issued;
- DPRINTF(IQ, "IQ: Issuing float instruction PC %#x.\n",
- issuing_inst->readPC());
- break;
-
- case Branch:
- issuing_inst = branch_head_inst;
- readyBranchInsts.pop();
- ++branch_issued;
- DPRINTF(IQ, "IQ: Issuing branch instruction PC %#x.\n",
- issuing_inst->readPC());
- break;
-
- case Memory:
- issuing_inst = mem_head_inst;
+ // Add the FU onto the list of FU's to be freed next
+ // cycle if we used one.
+ if (idx >= 0)
+ fuPool->freeUnitNextCycle(idx);
+ } else {
+ int issue_latency = fuPool->getIssueLatency(op_class);
+ // Generate completion event for the FU
+ FUCompletion *execution = new FUCompletion(issuing_inst,
+ idx, this);
+
+ execution->schedule(curTick + cpu->cycles(issue_latency - 1));
+
+ // @todo: Enforce that issue_latency == 1 or op_latency
+ if (issue_latency > 1) {
+ execution->setFreeFU();
+ } else {
+ // @todo: Not sure I'm accounting for the
+ // multi-cycle op in a pipelined FU properly, or
+ // the number of instructions issued in one cycle.
+// i2e_info->insts[exec_queue_slot++] = issuing_inst;
+// i2e_info->size++;
+
+ // Add the FU onto the list of FU's to be freed next cycle.
+ fuPool->freeUnitNextCycle(idx);
+ }
+ }
- memDepUnit.pop();
- ++memory_issued;
- DPRINTF(IQ, "IQ: Issuing memory instruction PC %#x.\n",
- issuing_inst->readPC());
- break;
+ DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x "
+ "[sn:%lli]\n",
+ tid, issuing_inst->readPC(),
+ issuing_inst->seqNum);
- case Misc:
- issuing_inst = misc_head_inst;
- readyMiscInsts.pop();
+ readyInsts[op_class].pop();
- ++iqMiscInstsIssued;
+ if (!readyInsts[op_class].empty()) {
+ moveToYoungerInst(order_it);
+ } else {
+ readyIt[op_class] = listOrder.end();
+ queueOnList[op_class] = false;
+ }
- DPRINTF(IQ, "IQ: Issuing a miscellaneous instruction PC %#x.\n",
- issuing_inst->readPC());
- break;
+ issuing_inst->setIssued();
+ ++total_issued;
- case Squashed:
- assert(0 && "Squashed insts should not issue any more!");
- squashedInsts.pop();
- // Set the squashed instruction as able to commit so that commit
- // can just drop it from the ROB. This is a bit faked.
- ++squashed_issued;
- ++freeEntries;
+ if (!issuing_inst->isMemRef()) {
+ // Memory instructions can not be freed from the IQ until they
+ // complete.
+ ++freeEntries;
+ count[tid]--;
+ issuing_inst->removeInIQ();
+ } else {
+ memDepUnit[tid].issue(issuing_inst);
+ }
- DPRINTF(IQ, "IQ: Issuing squashed instruction PC %#x.\n",
- squashed_head_inst->readPC());
- break;
+ listOrder.erase(order_it++);
+ statIssuedInstType[tid][op_class]++;
+ } else {
+ statFuBusy[op_class]++;
+ fuBusy[tid]++;
+ ++order_it;
}
+ }
- if (list_with_oldest != None && list_with_oldest != Squashed) {
- i2e_info->insts[total_issued] = issuing_inst;
- i2e_info->size++;
-
- issuing_inst->setIssued();
-
- ++freeEntries;
- ++total_issued;
- }
+ numIssuedDist.sample(total_issued);
+ iqInstsIssued+= total_issued;
- assert(freeEntries == (numEntries - countInsts()));
+ if (total_issued) {
+ cpu->activityThisCycle();
+ } else {
+ DPRINTF(IQ, "Not able to schedule any instructions.\n");
}
-
- iqIntInstsIssued += int_issued;
- iqFloatInstsIssued += float_issued;
- iqBranchInstsIssued += branch_issued;
- iqMemInstsIssued += memory_issued;
- iqSquashedInstsIssued += squashed_issued;
}
template <class Impl>
void
InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
{
- DPRINTF(IQ, "IQ: Marking nonspeculative instruction with sequence "
- "number %i as ready to execute.\n", inst);
+ DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
+ "to execute.\n", inst);
- non_spec_it_t inst_it = nonSpecInsts.find(inst);
+ NonSpecMapIt inst_it = nonSpecInsts.find(inst);
assert(inst_it != nonSpecInsts.end());
- // Mark this instruction as ready to issue.
+ unsigned tid = (*inst_it).second->threadNumber;
+
(*inst_it).second->setCanIssue();
- // Now schedule the instruction.
if (!(*inst_it).second->isMemRef()) {
addIfReady((*inst_it).second);
} else {
- memDepUnit.nonSpecInstReady((*inst_it).second);
+ memDepUnit[tid].nonSpecInstReady((*inst_it).second);
}
+ (*inst_it).second = NULL;
+
nonSpecInsts.erase(inst_it);
}
template <class Impl>
void
+InstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid)
+{
+ DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
+ tid,inst);
+
+ ListIt iq_it = instList[tid].begin();
+
+ while (iq_it != instList[tid].end() &&
+ (*iq_it)->seqNum <= inst) {
+ ++iq_it;
+ instList[tid].pop_front();
+ }
+
+ assert(freeEntries == (numEntries - countInsts()));
+}
+
+template <class Impl>
+int
InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
{
- DPRINTF(IQ, "IQ: Waking dependents of completed instruction.\n");
- //Look at the physical destination register of the DynInst
- //and look it up on the dependency graph. Then mark as ready
- //any instructions within the instruction queue.
- DependencyEntry *curr;
+ int dependents = 0;
- // Tell the memory dependence unit to wake any dependents on this
- // instruction if it is a memory instruction.
+ DPRINTF(IQ, "Waking dependents of completed instruction.\n");
+ assert(!completed_inst->isSquashed());
+
+ // Tell the memory dependence unit to wake any dependents on this
+ // instruction if it is a memory instruction. Also complete the memory
+ // instruction at this point since we know it executed without issues.
+ // @todo: Might want to rename "completeMemInst" to something that
+ // indicates that it won't need to be replayed, and call this
+ // earlier. Might not be a big deal.
if (completed_inst->isMemRef()) {
- memDepUnit.wakeDependents(completed_inst);
+ memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
+ completeMemInst(completed_inst);
+ } else if (completed_inst->isMemBarrier() ||
+ completed_inst->isWriteBarrier()) {
+ memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
}
for (int dest_reg_idx = 0;
@@ -676,44 +903,94 @@ InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
continue;
}
- DPRINTF(IQ, "IQ: Waking any dependents on register %i.\n",
+ DPRINTF(IQ, "Waking any dependents on register %i.\n",
(int) dest_reg);
- //Maybe abstract this part into a function.
- //Go through the dependency chain, marking the registers as ready
- //within the waiting instructions.
- while (dependGraph[dest_reg].next) {
-
- curr = dependGraph[dest_reg].next;
+ //Go through the dependency chain, marking the registers as
+ //ready within the waiting instructions.
+ DynInstPtr dep_inst = dependGraph.pop(dest_reg);
- DPRINTF(IQ, "IQ: Waking up a dependent instruction, PC%#x.\n",
- curr->inst->readPC());
+ while (dep_inst) {
+ DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
+ dep_inst->readPC());
// Might want to give more information to the instruction
- // so that it knows which of its source registers is ready.
- // However that would mean that the dependency graph entries
- // would need to hold the src_reg_idx.
- curr->inst->markSrcRegReady();
+ // so that it knows which of its source registers is
+ // ready. However that would mean that the dependency
+ // graph entries would need to hold the src_reg_idx.
+ dep_inst->markSrcRegReady();
- addIfReady(curr->inst);
+ addIfReady(dep_inst);
- dependGraph[dest_reg].next = curr->next;
+ dep_inst = dependGraph.pop(dest_reg);
- DependencyEntry::mem_alloc_counter--;
-
- curr->inst = NULL;
-
- delete curr;
+ ++dependents;
}
- // Reset the head node now that all of its dependents have been woken
- // up.
- dependGraph[dest_reg].next = NULL;
- dependGraph[dest_reg].inst = NULL;
+ // Reset the head node now that all of its dependents have
+ // been woken up.
+ assert(dependGraph.empty(dest_reg));
+ dependGraph.clearInst(dest_reg);
// Mark the scoreboard as having that register ready.
regScoreboard[dest_reg] = true;
}
+ return dependents;
+}
+
+template <class Impl>
+void
+InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
+{
+ OpClass op_class = ready_inst->opClass();
+
+ readyInsts[op_class].push(ready_inst);
+
+ // Will need to reorder the list if either a queue is not on the list,
+ // or it has an older instruction than last time.
+ if (!queueOnList[op_class]) {
+ addToOrderList(op_class);
+ } else if (readyInsts[op_class].top()->seqNum <
+ (*readyIt[op_class]).oldestInst) {
+ listOrder.erase(readyIt[op_class]);
+ addToOrderList(op_class);
+ }
+
+ DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
+ "the ready list, PC %#x opclass:%i [sn:%lli].\n",
+ ready_inst->readPC(), op_class, ready_inst->seqNum);
+}
+
+template <class Impl>
+void
+InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
+{
+ memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
+}
+
+template <class Impl>
+void
+InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
+{
+ memDepUnit[replay_inst->threadNumber].replay(replay_inst);
+}
+
+template <class Impl>
+void
+InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
+{
+ int tid = completed_inst->threadNumber;
+
+ DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
+ completed_inst->readPC(), completed_inst->seqNum);
+
+ ++freeEntries;
+
+ completed_inst->memOpDone = true;
+
+ memDepUnit[tid].completed(completed_inst);
+
+ count[tid]--;
}
template <class Impl>
@@ -721,58 +998,64 @@ void
InstructionQueue<Impl>::violation(DynInstPtr &store,
DynInstPtr &faulting_load)
{
- memDepUnit.violation(store, faulting_load);
+ memDepUnit[store->threadNumber].violation(store, faulting_load);
}
template <class Impl>
void
-InstructionQueue<Impl>::squash()
+InstructionQueue<Impl>::squash(unsigned tid)
{
- DPRINTF(IQ, "IQ: Starting to squash instructions in the IQ.\n");
+ DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
+ "the IQ.\n", tid);
// Read instruction sequence number of last instruction out of the
// time buffer.
- squashedSeqNum = fromCommit->commitInfo.doneSeqNum;
-
- // Setup the squash iterator to point to the tail.
- squashIt = tail;
+ squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
// Call doSquash if there are insts in the IQ
- if (freeEntries != numEntries) {
- doSquash();
+ if (count[tid] > 0) {
+ doSquash(tid);
}
// Also tell the memory dependence unit to squash.
- memDepUnit.squash(squashedSeqNum);
+ memDepUnit[tid].squash(squashedSeqNum[tid], tid);
}
template <class Impl>
void
-InstructionQueue<Impl>::doSquash()
+InstructionQueue<Impl>::doSquash(unsigned tid)
{
- // Make sure the squash iterator isn't pointing to nothing.
- assert(squashIt != cpu->instList.end());
- // Make sure the squashed sequence number is valid.
- assert(squashedSeqNum != 0);
+ // Start at the tail.
+ ListIt squash_it = instList[tid].end();
+ --squash_it;
- DPRINTF(IQ, "IQ: Squashing instructions in the IQ.\n");
+ DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
+ tid, squashedSeqNum[tid]);
// Squash any instructions younger than the squashed sequence number
// given.
- while ((*squashIt)->seqNum > squashedSeqNum) {
- DynInstPtr squashed_inst = (*squashIt);
+ while (squash_it != instList[tid].end() &&
+ (*squash_it)->seqNum > squashedSeqNum[tid]) {
+
+ DynInstPtr squashed_inst = (*squash_it);
// Only handle the instruction if it actually is in the IQ and
// hasn't already been squashed in the IQ.
- if (!squashed_inst->isIssued() &&
- !squashed_inst->isSquashedInIQ()) {
+ if (squashed_inst->threadNumber != tid ||
+ squashed_inst->isSquashedInIQ()) {
+ --squash_it;
+ continue;
+ }
+
+ if (!squashed_inst->isIssued() ||
+ (squashed_inst->isMemRef() &&
+ !squashed_inst->memOpDone)) {
// Remove the instruction from the dependency list.
- // Hack for now: These below don't add themselves to the
- // dependency list, so don't try to remove them.
- if (!squashed_inst->isNonSpeculative()/* &&
- !squashed_inst->isStore()*/
- ) {
+ if (!squashed_inst->isNonSpeculative() &&
+ !squashed_inst->isStoreConditional() &&
+ !squashed_inst->isMemBarrier() &&
+ !squashed_inst->isWriteBarrier()) {
for (int src_reg_idx = 0;
src_reg_idx < squashed_inst->numSrcRegs();
@@ -781,25 +1064,31 @@ InstructionQueue<Impl>::doSquash()
PhysRegIndex src_reg =
squashed_inst->renamedSrcRegIdx(src_reg_idx);
- // Only remove it from the dependency graph if it was
- // placed there in the first place.
- // HACK: This assumes that instructions woken up from the
- // dependency chain aren't informed that a specific src
- // register has become ready. This may not always be true
- // in the future.
+ // Only remove it from the dependency graph if it
+ // was placed there in the first place.
+
+ // Instead of doing a linked list traversal, we
+ // can just remove these squashed instructions
+ // either at issue time, or when the register is
+ // overwritten. The only downside to this is it
+ // leaves more room for error.
+
if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
src_reg < numPhysRegs) {
- dependGraph[src_reg].remove(squashed_inst);
+ dependGraph.remove(src_reg, squashed_inst);
}
+
++iqSquashedOperandsExamined;
}
-
- // Might want to remove producers as well.
} else {
- nonSpecInsts[squashed_inst->seqNum] = NULL;
+ NonSpecMapIt ns_inst_it =
+ nonSpecInsts.find(squashed_inst->seqNum);
+ assert(ns_inst_it != nonSpecInsts.end());
+
+ (*ns_inst_it).second = NULL;
- nonSpecInsts.erase(squashed_inst->seqNum);
+ nonSpecInsts.erase(ns_inst_it);
++iqSquashedNonSpecRemoved;
}
@@ -809,91 +1098,25 @@ InstructionQueue<Impl>::doSquash()
// Mark it as squashed within the IQ.
squashed_inst->setSquashedInIQ();
-// squashedInsts.push(squashed_inst);
+ // @todo: Remove this hack where several statuses are set so the
+ // inst will flow through the rest of the pipeline.
squashed_inst->setIssued();
squashed_inst->setCanCommit();
+ squashed_inst->removeInIQ();
+
+ //Update Thread IQ Count
+ count[squashed_inst->threadNumber]--;
++freeEntries;
- DPRINTF(IQ, "IQ: Instruction PC %#x squashed.\n",
- squashed_inst->readPC());
+ DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
+ "squashed.\n",
+ tid, squashed_inst->seqNum, squashed_inst->readPC());
}
- --squashIt;
+ instList[tid].erase(squash_it--);
++iqSquashedInstsExamined;
}
-
- assert(freeEntries <= numEntries);
-
- if (freeEntries == numEntries) {
- tail = cpu->instList.end();
- }
-
-}
-
-template <class Impl>
-void
-InstructionQueue<Impl>::stopSquash()
-{
- // Clear up the squash variables to ensure that squashing doesn't
- // get called improperly.
- squashedSeqNum = 0;
-
- squashIt = cpu->instList.end();
-}
-
-template <class Impl>
-void
-InstructionQueue<Impl>::DependencyEntry::insert(DynInstPtr &new_inst)
-{
- //Add this new, dependent instruction at the head of the dependency
- //chain.
-
- // First create the entry that will be added to the head of the
- // dependency chain.
- DependencyEntry *new_entry = new DependencyEntry;
- new_entry->next = this->next;
- new_entry->inst = new_inst;
-
- // Then actually add it to the chain.
- this->next = new_entry;
-
- ++mem_alloc_counter;
-}
-
-template <class Impl>
-void
-InstructionQueue<Impl>::DependencyEntry::remove(DynInstPtr &inst_to_remove)
-{
- DependencyEntry *prev = this;
- DependencyEntry *curr = this->next;
-
- // Make sure curr isn't NULL. Because this instruction is being
- // removed from a dependency list, it must have been placed there at
- // an earlier time. The dependency chain should not be empty,
- // unless the instruction dependent upon it is already ready.
- if (curr == NULL) {
- return;
- }
-
- // Find the instruction to remove within the dependency linked list.
- while(curr->inst != inst_to_remove)
- {
- prev = curr;
- curr = curr->next;
-
- assert(curr != NULL);
- }
-
- // Now remove this instruction from the list.
- prev->next = curr->next;
-
- --mem_alloc_counter;
-
- // Could push this off to the destructor of DependencyEntry
- curr->inst = NULL;
-
- delete curr;
}
template <class Impl>
@@ -920,21 +1143,21 @@ InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
if (src_reg >= numPhysRegs) {
continue;
} else if (regScoreboard[src_reg] == false) {
- DPRINTF(IQ, "IQ: Instruction PC %#x has src reg %i that "
+ DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
"is being added to the dependency chain.\n",
new_inst->readPC(), src_reg);
- dependGraph[src_reg].insert(new_inst);
+ dependGraph.insert(src_reg, new_inst);
// Change the return value to indicate that something
// was added to the dependency graph.
return_val = true;
} else {
- DPRINTF(IQ, "IQ: Instruction PC %#x has src reg %i that "
+ DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
"became ready before it reached the IQ.\n",
new_inst->readPC(), src_reg);
// Mark a register ready within the instruction.
- new_inst->markSrcRegReady();
+ new_inst->markSrcRegReady(src_reg_idx);
}
}
}
@@ -944,12 +1167,12 @@ InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
template <class Impl>
void
-InstructionQueue<Impl>::createDependency(DynInstPtr &new_inst)
+InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
{
- //Actually nothing really needs to be marked when an
- //instruction becomes the producer of a register's value,
- //but for convenience a ptr to the producing instruction will
- //be placed in the head node of the dependency links.
+ // Nothing really needs to be marked when an instruction becomes
+ // the producer of a register's value, but for convenience a ptr
+ // to the producing instruction will be placed in the head node of
+ // the dependency links.
int8_t total_dest_regs = new_inst->numDestRegs();
for (int dest_reg_idx = 0;
@@ -966,13 +1189,13 @@ InstructionQueue<Impl>::createDependency(DynInstPtr &new_inst)
continue;
}
- dependGraph[dest_reg].inst = new_inst;
-
- if (dependGraph[dest_reg].next) {
- dumpDependGraph();
- panic("IQ: Dependency graph not empty!");
+ if (!dependGraph.empty(dest_reg)) {
+ dependGraph.dump();
+ panic("Dependency graph %i not empty!", dest_reg);
}
+ dependGraph.setInst(dest_reg, new_inst);
+
// Mark the scoreboard to say it's not yet ready.
regScoreboard[dest_reg] = false;
}
@@ -982,155 +1205,163 @@ template <class Impl>
void
InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
{
- //If the instruction now has all of its source registers
+ // If the instruction now has all of its source registers
// available, then add it to the list of ready instructions.
if (inst->readyToIssue()) {
//Add the instruction to the proper ready list.
- if (inst->isControl()) {
+ if (inst->isMemRef()) {
- DPRINTF(IQ, "IQ: Branch instruction is ready to issue, "
- "putting it onto the ready list, PC %#x.\n",
- inst->readPC());
- readyBranchInsts.push(inst);
-
- } else if (inst->isMemRef()) {
-
- DPRINTF(IQ, "IQ: Checking if memory instruction can issue.\n");
+ DPRINTF(IQ, "Checking if memory instruction can issue.\n");
// Message to the mem dependence unit that this instruction has
// its registers ready.
+ memDepUnit[inst->threadNumber].regsReady(inst);
- memDepUnit.regsReady(inst);
-
-#if 0
- if (memDepUnit.readyToIssue(inst)) {
- DPRINTF(IQ, "IQ: Memory instruction is ready to issue, "
- "putting it onto the ready list, PC %#x.\n",
- inst->readPC());
- readyMemInsts.push(inst);
- } else {
- // Make dependent on the store.
- // Will need some way to get the store instruction it should
- // be dependent upon; then when the store issues it can
- // put the instruction on the ready list.
- // Yet another tree?
- assert(0 && "Instruction has no way to actually issue");
- }
-#endif
-
- } else if (inst->isInteger()) {
+ return;
+ }
- DPRINTF(IQ, "IQ: Integer instruction is ready to issue, "
- "putting it onto the ready list, PC %#x.\n",
- inst->readPC());
- readyIntInsts.push(inst);
+ OpClass op_class = inst->opClass();
- } else if (inst->isFloating()) {
+ DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
+ "the ready list, PC %#x opclass:%i [sn:%lli].\n",
+ inst->readPC(), op_class, inst->seqNum);
- DPRINTF(IQ, "IQ: Floating instruction is ready to issue, "
- "putting it onto the ready list, PC %#x.\n",
- inst->readPC());
- readyFloatInsts.push(inst);
+ readyInsts[op_class].push(inst);
- } else {
- DPRINTF(IQ, "IQ: Miscellaneous instruction is ready to issue, "
- "putting it onto the ready list, PC %#x..\n",
- inst->readPC());
-
- readyMiscInsts.push(inst);
+ // Will need to reorder the list if either a queue is not on the list,
+ // or it has an older instruction than last time.
+ if (!queueOnList[op_class]) {
+ addToOrderList(op_class);
+ } else if (readyInsts[op_class].top()->seqNum <
+ (*readyIt[op_class]).oldestInst) {
+ listOrder.erase(readyIt[op_class]);
+ addToOrderList(op_class);
}
}
}
-/*
- * Caution, this function must not be called prior to tail being updated at
- * least once, otherwise it will fail the assertion. This is because
- * instList.begin() actually changes upon the insertion of an element into the
- * list when the list is empty.
- */
template <class Impl>
int
InstructionQueue<Impl>::countInsts()
{
- ListIt count_it = cpu->instList.begin();
+ //ksewell:This works but definitely could use a cleaner write
+ //with a more intuitive way of counting. Right now it's
+ //just brute force ....
+
+#if 0
int total_insts = 0;
- if (tail == cpu->instList.end())
- return 0;
+ for (int i = 0; i < numThreads; ++i) {
+ ListIt count_it = instList[i].begin();
+
+ while (count_it != instList[i].end()) {
+ if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
+ if (!(*count_it)->isIssued()) {
+ ++total_insts;
+ } else if ((*count_it)->isMemRef() &&
+ !(*count_it)->memOpDone) {
+ // Loads that have not been marked as executed still count
+ // towards the total instructions.
+ ++total_insts;
+ }
+ }
- while (count_it != tail) {
- if (!(*count_it)->isIssued()) {
- ++total_insts;
+ ++count_it;
}
-
- ++count_it;
-
- assert(count_it != cpu->instList.end());
- }
-
- // Need to count the tail iterator as well.
- if (count_it != cpu->instList.end() &&
- (*count_it) &&
- !(*count_it)->isIssued()) {
- ++total_insts;
}
return total_insts;
+#else
+ return numEntries - freeEntries;
+#endif
}
template <class Impl>
void
-InstructionQueue<Impl>::dumpDependGraph()
+InstructionQueue<Impl>::dumpLists()
{
- DependencyEntry *curr;
+ for (int i = 0; i < Num_OpClasses; ++i) {
+ cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
- for (int i = 0; i < numPhysRegs; ++i)
- {
- curr = &dependGraph[i];
+ cprintf("\n");
+ }
- if (curr->inst) {
- cprintf("dependGraph[%i]: producer: %#x consumer: ", i,
- curr->inst->readPC());
- } else {
- cprintf("dependGraph[%i]: No producer. consumer: ", i);
- }
+ cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
- while (curr->next != NULL) {
- curr = curr->next;
+ NonSpecMapIt non_spec_it = nonSpecInsts.begin();
+ NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
- cprintf("%#x ", curr->inst->readPC());
- }
+ cprintf("Non speculative list: ");
- cprintf("\n");
+ while (non_spec_it != non_spec_end_it) {
+ cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(),
+ (*non_spec_it).second->seqNum);
+ ++non_spec_it;
}
-}
-template <class Impl>
-void
-InstructionQueue<Impl>::dumpLists()
-{
- cprintf("Ready integer list size: %i\n", readyIntInsts.size());
+ cprintf("\n");
- cprintf("Ready float list size: %i\n", readyFloatInsts.size());
+ ListOrderIt list_order_it = listOrder.begin();
+ ListOrderIt list_order_end_it = listOrder.end();
+ int i = 1;
- cprintf("Ready branch list size: %i\n", readyBranchInsts.size());
+ cprintf("List order: ");
- cprintf("Ready misc list size: %i\n", readyMiscInsts.size());
+ while (list_order_it != list_order_end_it) {
+ cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
+ (*list_order_it).oldestInst);
- cprintf("Squashed list size: %i\n", squashedInsts.size());
+ ++list_order_it;
+ ++i;
+ }
- cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
+ cprintf("\n");
+}
- non_spec_it_t non_spec_it = nonSpecInsts.begin();
- cprintf("Non speculative list: ");
+template <class Impl>
+void
+InstructionQueue<Impl>::dumpInsts()
+{
+ for (int i = 0; i < numThreads; ++i) {
+ int num = 0;
+ int valid_num = 0;
+ ListIt inst_list_it = instList[i].begin();
+
+ while (inst_list_it != instList[i].end())
+ {
+ cprintf("Instruction:%i\n",
+ num);
+ if (!(*inst_list_it)->isSquashed()) {
+ if (!(*inst_list_it)->isIssued()) {
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ } else if ((*inst_list_it)->isMemRef() &&
+ !(*inst_list_it)->memOpDone) {
+ // Loads that have not been marked as executed
+ // still count towards the total instructions.
+ ++valid_num;
+ cprintf("Count:%i\n", valid_num);
+ }
+ }
- while (non_spec_it != nonSpecInsts.end()) {
- cprintf("%#x ", (*non_spec_it).second->readPC());
- ++non_spec_it;
- }
+ cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
+ "Issued:%i\nSquashed:%i\n",
+ (*inst_list_it)->readPC(),
+ (*inst_list_it)->seqNum,
+ (*inst_list_it)->threadNumber,
+ (*inst_list_it)->isIssued(),
+ (*inst_list_it)->isSquashed());
- cprintf("\n");
+ if ((*inst_list_it)->isMemRef()) {
+ cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
+ }
+ cprintf("\n");
+
+ inst_list_it++;
+ ++num;
+ }
+ }
}
diff --git a/src/cpu/o3/mem_dep_unit.cc b/src/cpu/o3/mem_dep_unit.cc
index 9c1e7f9d8..ccdd1a515 100644
--- a/src/cpu/o3/mem_dep_unit.cc
+++ b/src/cpu/o3/mem_dep_unit.cc
@@ -34,3 +34,13 @@
// Force instantation of memory dependency unit using store sets and
// AlphaSimpleImpl.
template class MemDepUnit<StoreSet, AlphaSimpleImpl>;
+
+template <>
+int
+MemDepUnit<StoreSet, AlphaSimpleImpl>::MemDepEntry::memdep_count = 0;
+template <>
+int
+MemDepUnit<StoreSet, AlphaSimpleImpl>::MemDepEntry::memdep_insert = 0;
+template <>
+int
+MemDepUnit<StoreSet, AlphaSimpleImpl>::MemDepEntry::memdep_erase = 0;
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index ca63577a1..acbe08ec2 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,15 +26,29 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_MEM_DEP_UNIT_HH__
-#define __CPU_O3_CPU_MEM_DEP_UNIT_HH__
+#ifndef __CPU_O3_MEM_DEP_UNIT_HH__
+#define __CPU_O3_MEM_DEP_UNIT_HH__
-#include <map>
+#include <list>
#include <set>
+#include "base/hashmap.hh"
+#include "base/refcnt.hh"
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
+struct SNHash {
+ size_t operator() (const InstSeqNum &seq_num) const {
+ unsigned a = (unsigned)seq_num;
+ unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
+
+ return hash;
+ }
+};
+
+template <class Impl>
+class InstructionQueue;
+
/**
* Memory dependency unit class. This holds the memory dependence predictor.
* As memory operations are issued to the IQ, they are also issued to this
@@ -52,101 +66,159 @@ class MemDepUnit {
typedef typename Impl::Params Params;
typedef typename Impl::DynInstPtr DynInstPtr;
- public:
- MemDepUnit(Params &params);
+ /** Empty constructor. Must call init() prior to using in this case. */
+ MemDepUnit() {}
+
+ /** Constructs a MemDepUnit with given parameters. */
+ MemDepUnit(Params *params);
+ /** Frees up any memory allocated. */
+ ~MemDepUnit();
+
+ /** Returns the name of the memory dependence unit. */
+ std::string name() const;
+
+ /** Initializes the unit with parameters and a thread id. */
+ void init(Params *params, int tid);
+
+ /** Registers statistics. */
void regStats();
+ void switchOut();
+
+ void takeOverFrom();
+
+ /** Sets the pointer to the IQ. */
+ void setIQ(InstructionQueue<Impl> *iq_ptr);
+
+ /** Inserts a memory instruction. */
void insert(DynInstPtr &inst);
+ /** Inserts a non-speculative memory instruction. */
void insertNonSpec(DynInstPtr &inst);
- // Will want to make this operation relatively fast. Right now it
- // is somewhat slow.
- DynInstPtr &top();
-
- void pop();
+ /** Inserts a barrier instruction. */
+ void insertBarrier(DynInstPtr &barr_inst);
+ /** Indicate that an instruction has its registers ready. */
void regsReady(DynInstPtr &inst);
+ /** Indicate that a non-speculative instruction is ready. */
void nonSpecInstReady(DynInstPtr &inst);
- void issue(DynInstPtr &inst);
+ /** Reschedules an instruction to be re-executed. */
+ void reschedule(DynInstPtr &inst);
+
+ /** Replays all instructions that have been rescheduled by moving them to
+ * the ready list.
+ */
+ void replay(DynInstPtr &inst);
+
+ /** Completes a memory instruction. */
+ void completed(DynInstPtr &inst);
+ /** Completes a barrier instruction. */
+ void completeBarrier(DynInstPtr &inst);
+
+ /** Wakes any dependents of a memory instruction. */
void wakeDependents(DynInstPtr &inst);
- void squash(const InstSeqNum &squashed_num);
+ /** Squashes all instructions up until a given sequence number for a
+ * specific thread.
+ */
+ void squash(const InstSeqNum &squashed_num, unsigned tid);
+ /** Indicates an ordering violation between a store and a younger load. */
void violation(DynInstPtr &store_inst, DynInstPtr &violating_load);
- inline bool empty()
- { return readyInsts.empty(); }
+ /** Issues the given instruction */
+ void issue(DynInstPtr &inst);
+
+ /** Debugging function to dump the lists of instructions. */
+ void dumpLists();
private:
- typedef typename std::set<InstSeqNum>::iterator sn_it_t;
- typedef typename std::map<InstSeqNum, DynInstPtr>::iterator dyn_it_t;
-
- // Forward declarations so that the following two typedefs work.
- class Dependency;
- class ltDependency;
-
- typedef typename std::set<Dependency, ltDependency>::iterator dep_it_t;
- typedef typename std::map<InstSeqNum, vector<dep_it_t> >::iterator
- sd_it_t;
-
- struct Dependency {
- Dependency(const InstSeqNum &_seqNum)
- : seqNum(_seqNum), regsReady(0), memDepReady(0)
- { }
-
- Dependency(const InstSeqNum &_seqNum, bool _regsReady,
- bool _memDepReady)
- : seqNum(_seqNum), regsReady(_regsReady),
- memDepReady(_memDepReady)
- { }
-
- InstSeqNum seqNum;
- mutable bool regsReady;
- mutable bool memDepReady;
- mutable sd_it_t storeDep;
- };
+ typedef typename std::list<DynInstPtr>::iterator ListIt;
- struct ltDependency {
- bool operator() (const Dependency &lhs, const Dependency &rhs)
+ class MemDepEntry;
+
+ typedef RefCountingPtr<MemDepEntry> MemDepEntryPtr;
+
+ /** Memory dependence entries that track memory operations, marking
+ * when the instruction is ready to execute and what instructions depend
+ * upon it.
+ */
+ class MemDepEntry : public RefCounted {
+ public:
+ /** Constructs a memory dependence entry. */
+ MemDepEntry(DynInstPtr &new_inst)
+ : inst(new_inst), regsReady(false), memDepReady(false),
+ completed(false), squashed(false)
{
- return lhs.seqNum < rhs.seqNum;
+ ++memdep_count;
+
+ DPRINTF(MemDepUnit, "Memory dependency entry created. "
+ "memdep_count=%i\n", memdep_count);
}
+
+ /** Frees any pointers. */
+ ~MemDepEntry()
+ {
+ for (int i = 0; i < dependInsts.size(); ++i) {
+ dependInsts[i] = NULL;
+ }
+
+ --memdep_count;
+
+ DPRINTF(MemDepUnit, "Memory dependency entry deleted. "
+ "memdep_count=%i\n", memdep_count);
+ }
+
+ /** Returns the name of the memory dependence entry. */
+ std::string name() const { return "memdepentry"; }
+
+ /** The instruction being tracked. */
+ DynInstPtr inst;
+
+ /** The iterator to the instruction's location inside the list. */
+ ListIt listIt;
+
+ /** A vector of any dependent instructions. */
+ std::vector<MemDepEntryPtr> dependInsts;
+
+ /** If the registers are ready or not. */
+ bool regsReady;
+ /** If all memory dependencies have been satisfied. */
+ bool memDepReady;
+ /** If the instruction is completed. */
+ bool completed;
+ /** If the instruction is squashed. */
+ bool squashed;
+
+ /** For debugging. */
+ static int memdep_count;
+ static int memdep_insert;
+ static int memdep_erase;
};
- inline void moveToReady(dep_it_t &woken_inst);
+ /** Finds the memory dependence entry in the hash map. */
+ inline MemDepEntryPtr &findInHash(const DynInstPtr &inst);
- /** List of instructions that have passed through rename, yet are still
- * waiting on either a memory dependence to resolve or source registers to
- * become available before they can issue.
- */
- std::set<Dependency, ltDependency> waitingInsts;
+ /** Moves an entry to the ready list. */
+ inline void moveToReady(MemDepEntryPtr &ready_inst_entry);
- /** List of instructions that have all their predicted memory dependences
- * resolved and their source registers ready.
- */
- std::set<InstSeqNum> readyInsts;
+ typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
- // Change this to hold a vector of iterators, which will point to the
- // entry of the waiting instructions.
- /** List of stores' sequence numbers, each of which has a vector of
- * iterators. The iterators point to the appropriate node within
- * waitingInsts that has the depenendent instruction.
- */
- std::map<InstSeqNum, vector<dep_it_t> > storeDependents;
+ typedef typename MemDepHash::iterator MemDepHashIt;
+
+ /** A hash map of all memory dependence entries. */
+ MemDepHash memDepHash;
- // For now will implement this as a map...hash table might not be too
- // bad, or could move to something that mimics the current dependency
- // graph.
- std::map<InstSeqNum, DynInstPtr> memInsts;
+ /** A list of all instructions in the memory dependence unit. */
+ std::list<DynInstPtr> instList[Impl::MaxThreads];
- // Iterator pointer to the top instruction which has is ready.
- // Is set by the top() call.
- dyn_it_t topInst;
+ /** A list of all instructions that are going to be replayed. */
+ std::list<DynInstPtr> instsToReplay;
/** The memory dependence predictor. It is accessed upon new
* instructions being added to the IQ, and responds by telling
@@ -155,10 +227,25 @@ class MemDepUnit {
*/
MemDepPred depPred;
+ bool loadBarrier;
+ InstSeqNum loadBarrierSN;
+ bool storeBarrier;
+ InstSeqNum storeBarrierSN;
+
+ /** Pointer to the IQ. */
+ InstructionQueue<Impl> *iqPtr;
+
+ /** The thread id of this memory dependence unit. */
+ int id;
+
+ /** Stat for number of inserted loads. */
Stats::Scalar<> insertedLoads;
+ /** Stat for number of inserted stores. */
Stats::Scalar<> insertedStores;
+ /** Stat for number of conflicting loads that had to wait for a store. */
Stats::Scalar<> conflictingLoads;
+ /** Stat for number of conflicting stores that had to wait for a store. */
Stats::Scalar<> conflictingStores;
};
-#endif // __CPU_O3_CPU_MEM_DEP_UNIT_HH__
+#endif // __CPU_O3_MEM_DEP_UNIT_HH__
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh b/src/cpu/o3/mem_dep_unit_impl.hh
index 296db4c4e..8b195baab 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -28,13 +28,56 @@
#include <map>
+#include "cpu/o3/inst_queue.hh"
#include "cpu/o3/mem_dep_unit.hh"
template <class MemDepPred, class Impl>
-MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params &params)
- : depPred(params.SSITSize, params.LFSTSize)
+MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
+ : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
+ loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
{
- DPRINTF(MemDepUnit, "MemDepUnit: Creating MemDepUnit object.\n");
+ DPRINTF(MemDepUnit, "Creating MemDepUnit object.\n");
+}
+
+template <class MemDepPred, class Impl>
+MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
+{
+ for (int tid=0; tid < Impl::MaxThreads; tid++) {
+
+ ListIt inst_list_it = instList[tid].begin();
+
+ MemDepHashIt hash_it;
+
+ while (!instList[tid].empty()) {
+ hash_it = memDepHash.find((*inst_list_it)->seqNum);
+
+ assert(hash_it != memDepHash.end());
+
+ memDepHash.erase(hash_it);
+
+ instList[tid].erase(inst_list_it++);
+ }
+ }
+
+ assert(MemDepEntry::memdep_count == 0);
+}
+
+template <class MemDepPred, class Impl>
+std::string
+MemDepUnit<MemDepPred, Impl>::name() const
+{
+ return "memdepunit";
+}
+
+template <class MemDepPred, class Impl>
+void
+MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
+{
+ DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
+
+ id = tid;
+
+ depPred.init(params->SSITSize, params->LFSTSize);
}
template <class MemDepPred, class Impl>
@@ -60,56 +103,95 @@ MemDepUnit<MemDepPred, Impl>::regStats()
template <class MemDepPred, class Impl>
void
+MemDepUnit<MemDepPred, Impl>::switchOut()
+{
+ for (int i = 0; i < Impl::MaxThreads; ++i) {
+ instList[i].clear();
+ }
+ instsToReplay.clear();
+ memDepHash.clear();
+}
+
+template <class MemDepPred, class Impl>
+void
+MemDepUnit<MemDepPred, Impl>::takeOverFrom()
+{
+ loadBarrier = storeBarrier = false;
+ loadBarrierSN = storeBarrierSN = 0;
+ depPred.clear();
+}
+
+template <class MemDepPred, class Impl>
+void
+MemDepUnit<MemDepPred, Impl>::setIQ(InstructionQueue<Impl> *iq_ptr)
+{
+ iqPtr = iq_ptr;
+}
+
+template <class MemDepPred, class Impl>
+void
MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
{
- InstSeqNum inst_seq_num = inst->seqNum;
+ unsigned tid = inst->threadNumber;
+
+ MemDepEntryPtr inst_entry = new MemDepEntry(inst);
+
+ // Add the MemDepEntry to the hash.
+ memDepHash.insert(
+ std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
+ MemDepEntry::memdep_insert++;
+
+ instList[tid].push_back(inst);
+
+ inst_entry->listIt = --(instList[tid].end());
+
+ // Check any barriers and the dependence predictor for any
+ // producing stores.
+ InstSeqNum producing_store;
+ if (inst->isLoad() && loadBarrier) {
+ producing_store = loadBarrierSN;
+ } else if (inst->isStore() && storeBarrier) {
+ producing_store = storeBarrierSN;
+ } else {
+ producing_store = depPred.checkInst(inst->readPC());
+ }
- Dependency unresolved_dependencies(inst_seq_num);
+ MemDepEntryPtr store_entry = NULL;
- InstSeqNum producing_store = depPred.checkInst(inst->readPC());
+ // If there is a producing store, try to find the entry.
+ if (producing_store != 0) {
+ MemDepHashIt hash_it = memDepHash.find(producing_store);
- if (producing_store == 0 ||
- storeDependents.find(producing_store) == storeDependents.end()) {
+ if (hash_it != memDepHash.end()) {
+ store_entry = (*hash_it).second;
+ }
+ }
- DPRINTF(MemDepUnit, "MemDepUnit: No dependency for inst PC "
- "%#x.\n", inst->readPC());
+ // If no store entry, then instruction can issue as soon as the registers
+ // are ready.
+ if (!store_entry) {
+ DPRINTF(MemDepUnit, "No dependency for inst PC "
+ "%#x [sn:%lli].\n", inst->readPC(), inst->seqNum);
- unresolved_dependencies.storeDep = storeDependents.end();
+ inst_entry->memDepReady = true;
if (inst->readyToIssue()) {
- readyInsts.insert(inst_seq_num);
- } else {
- unresolved_dependencies.memDepReady = true;
+ inst_entry->regsReady = true;
- waitingInsts.insert(unresolved_dependencies);
+ moveToReady(inst_entry);
}
} else {
- DPRINTF(MemDepUnit, "MemDepUnit: Adding to dependency list; "
- "inst PC %#x is dependent on seq num %i.\n",
+ // Otherwise make the instruction dependent on the store/barrier.
+ DPRINTF(MemDepUnit, "Adding to dependency list; "
+ "inst PC %#x is dependent on [sn:%lli].\n",
inst->readPC(), producing_store);
if (inst->readyToIssue()) {
- unresolved_dependencies.regsReady = true;
+ inst_entry->regsReady = true;
}
- // Find the store that this instruction is dependent on.
- sd_it_t store_loc = storeDependents.find(producing_store);
-
- assert(store_loc != storeDependents.end());
-
- // Record the location of the store that this instruction is
- // dependent on.
- unresolved_dependencies.storeDep = store_loc;
-
- // If it's not already ready, then add it to the renamed
- // list and the dependencies.
- dep_it_t inst_loc =
- (waitingInsts.insert(unresolved_dependencies)).first;
-
// Add this instruction to the list of dependents.
- (*store_loc).second.push_back(inst_loc);
-
- assert(!(*store_loc).second.empty());
+ store_entry->dependInsts.push_back(inst_entry);
if (inst->isLoad()) {
++conflictingLoads;
@@ -119,277 +201,278 @@ MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
}
if (inst->isStore()) {
- DPRINTF(MemDepUnit, "MemDepUnit: Inserting store PC %#x.\n",
- inst->readPC());
-
- depPred.insertStore(inst->readPC(), inst_seq_num);
-
- // Make sure this store isn't already in this list.
- assert(storeDependents.find(inst_seq_num) == storeDependents.end());
-
- // Put a dependency entry in at the store's sequence number.
- // Uh, not sure how this works...I want to create an entry but
- // I don't have anything to put into the value yet.
- storeDependents[inst_seq_num];
+ DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
+ inst->readPC(), inst->seqNum);
- assert(storeDependents.size() != 0);
+ depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
++insertedStores;
-
} else if (inst->isLoad()) {
++insertedLoads;
} else {
- panic("MemDepUnit: Unknown type! (most likely a barrier).");
+ panic("Unknown type! (most likely a barrier).");
}
-
- memInsts[inst_seq_num] = inst;
}
template <class MemDepPred, class Impl>
void
MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
{
- InstSeqNum inst_seq_num = inst->seqNum;
+ unsigned tid = inst->threadNumber;
+
+ MemDepEntryPtr inst_entry = new MemDepEntry(inst);
- Dependency non_spec_inst(inst_seq_num);
+ // Insert the MemDepEntry into the hash.
+ memDepHash.insert(
+ std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
+ MemDepEntry::memdep_insert++;
- non_spec_inst.storeDep = storeDependents.end();
+ // Add the instruction to the list.
+ instList[tid].push_back(inst);
- waitingInsts.insert(non_spec_inst);
+ inst_entry->listIt = --(instList[tid].end());
// Might want to turn this part into an inline function or something.
// It's shared between both insert functions.
if (inst->isStore()) {
- DPRINTF(MemDepUnit, "MemDepUnit: Inserting store PC %#x.\n",
- inst->readPC());
-
- depPred.insertStore(inst->readPC(), inst_seq_num);
-
- // Make sure this store isn't already in this list.
- assert(storeDependents.find(inst_seq_num) == storeDependents.end());
-
- // Put a dependency entry in at the store's sequence number.
- // Uh, not sure how this works...I want to create an entry but
- // I don't have anything to put into the value yet.
- storeDependents[inst_seq_num];
+ DPRINTF(MemDepUnit, "Inserting store PC %#x [sn:%lli].\n",
+ inst->readPC(), inst->seqNum);
- assert(storeDependents.size() != 0);
+ depPred.insertStore(inst->readPC(), inst->seqNum, inst->threadNumber);
++insertedStores;
-
} else if (inst->isLoad()) {
++insertedLoads;
} else {
- panic("MemDepUnit: Unknown type! (most likely a barrier).");
+ panic("Unknown type! (most likely a barrier).");
}
-
- memInsts[inst_seq_num] = inst;
}
template <class MemDepPred, class Impl>
-typename Impl::DynInstPtr &
-MemDepUnit<MemDepPred, Impl>::top()
+void
+MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
{
- topInst = memInsts.find( (*readyInsts.begin()) );
+ InstSeqNum barr_sn = barr_inst->seqNum;
+ if (barr_inst->isMemBarrier()) {
+ loadBarrier = true;
+ loadBarrierSN = barr_sn;
+ storeBarrier = true;
+ storeBarrierSN = barr_sn;
+ DPRINTF(MemDepUnit, "Inserted a memory barrier\n");
+ } else if (barr_inst->isWriteBarrier()) {
+ storeBarrier = true;
+ storeBarrierSN = barr_sn;
+ DPRINTF(MemDepUnit, "Inserted a write barrier\n");
+ }
+
+ unsigned tid = barr_inst->threadNumber;
+
+ MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
+
+ // Add the MemDepEntry to the hash.
+ memDepHash.insert(
+ std::pair<InstSeqNum, MemDepEntryPtr>(barr_sn, inst_entry));
+ MemDepEntry::memdep_insert++;
- DPRINTF(MemDepUnit, "MemDepUnit: Top instruction is PC %#x.\n",
- (*topInst).second->readPC());
+ // Add the instruction to the instruction list.
+ instList[tid].push_back(barr_inst);
- return (*topInst).second;
+ inst_entry->listIt = --(instList[tid].end());
}
template <class MemDepPred, class Impl>
void
-MemDepUnit<MemDepPred, Impl>::pop()
+MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
{
- DPRINTF(MemDepUnit, "MemDepUnit: Removing instruction PC %#x.\n",
- (*topInst).second->readPC());
+ DPRINTF(MemDepUnit, "Marking registers as ready for "
+ "instruction PC %#x [sn:%lli].\n",
+ inst->readPC(), inst->seqNum);
- wakeDependents((*topInst).second);
+ MemDepEntryPtr inst_entry = findInHash(inst);
- issue((*topInst).second);
+ inst_entry->regsReady = true;
- memInsts.erase(topInst);
+ if (inst_entry->memDepReady) {
+ DPRINTF(MemDepUnit, "Instruction has its memory "
+ "dependencies resolved, adding it to the ready list.\n");
- topInst = memInsts.end();
+ moveToReady(inst_entry);
+ } else {
+ DPRINTF(MemDepUnit, "Instruction still waiting on "
+ "memory dependency.\n");
+ }
}
template <class MemDepPred, class Impl>
void
-MemDepUnit<MemDepPred, Impl>::regsReady(DynInstPtr &inst)
+MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
{
- DPRINTF(MemDepUnit, "MemDepUnit: Marking registers as ready for "
- "instruction PC %#x.\n",
- inst->readPC());
+ DPRINTF(MemDepUnit, "Marking non speculative "
+ "instruction PC %#x as ready [sn:%lli].\n",
+ inst->readPC(), inst->seqNum);
- InstSeqNum inst_seq_num = inst->seqNum;
+ MemDepEntryPtr inst_entry = findInHash(inst);
- Dependency inst_to_find(inst_seq_num);
+ moveToReady(inst_entry);
+}
- dep_it_t waiting_inst = waitingInsts.find(inst_to_find);
+template <class MemDepPred, class Impl>
+void
+MemDepUnit<MemDepPred, Impl>::reschedule(DynInstPtr &inst)
+{
+ instsToReplay.push_back(inst);
+}
- assert(waiting_inst != waitingInsts.end());
+template <class MemDepPred, class Impl>
+void
+MemDepUnit<MemDepPred, Impl>::replay(DynInstPtr &inst)
+{
+ DynInstPtr temp_inst;
+ bool found_inst = false;
- if ((*waiting_inst).memDepReady) {
- DPRINTF(MemDepUnit, "MemDepUnit: Instruction has its memory "
- "dependencies resolved, adding it to the ready list.\n");
+ while (!instsToReplay.empty()) {
+ temp_inst = instsToReplay.front();
- moveToReady(waiting_inst);
- } else {
- DPRINTF(MemDepUnit, "MemDepUnit: Instruction still waiting on "
- "memory dependency.\n");
+ MemDepEntryPtr inst_entry = findInHash(temp_inst);
- (*waiting_inst).regsReady = true;
+ DPRINTF(MemDepUnit, "Replaying mem instruction PC %#x "
+ "[sn:%lli].\n",
+ temp_inst->readPC(), temp_inst->seqNum);
+
+ moveToReady(inst_entry);
+
+ if (temp_inst == inst) {
+ found_inst = true;
+ }
+
+ instsToReplay.pop_front();
}
+
+ assert(found_inst);
}
template <class MemDepPred, class Impl>
void
-MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(DynInstPtr &inst)
+MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
{
- DPRINTF(MemDepUnit, "MemDepUnit: Marking non speculative "
- "instruction PC %#x as ready.\n",
- inst->readPC());
+ DPRINTF(MemDepUnit, "Completed mem instruction PC %#x "
+ "[sn:%lli].\n",
+ inst->readPC(), inst->seqNum);
+
+ unsigned tid = inst->threadNumber;
- InstSeqNum inst_seq_num = inst->seqNum;
+ // Remove the instruction from the hash and the list.
+ MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
- Dependency inst_to_find(inst_seq_num);
+ assert(hash_it != memDepHash.end());
- dep_it_t waiting_inst = waitingInsts.find(inst_to_find);
+ instList[tid].erase((*hash_it).second->listIt);
- assert(waiting_inst != waitingInsts.end());
+ (*hash_it).second = NULL;
- moveToReady(waiting_inst);
+ memDepHash.erase(hash_it);
+ MemDepEntry::memdep_erase++;
}
template <class MemDepPred, class Impl>
void
-MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
+MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
{
- assert(readyInsts.find(inst->seqNum) != readyInsts.end());
-
- DPRINTF(MemDepUnit, "MemDepUnit: Issuing instruction PC %#x.\n",
- inst->readPC());
-
- // Remove the instruction from the ready list.
- readyInsts.erase(inst->seqNum);
-
- depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
+ wakeDependents(inst);
+ completed(inst);
+
+ InstSeqNum barr_sn = inst->seqNum;
+
+ if (inst->isMemBarrier()) {
+ assert(loadBarrier && storeBarrier);
+ if (loadBarrierSN == barr_sn)
+ loadBarrier = false;
+ if (storeBarrierSN == barr_sn)
+ storeBarrier = false;
+ } else if (inst->isWriteBarrier()) {
+ assert(storeBarrier);
+ if (storeBarrierSN == barr_sn)
+ storeBarrier = false;
+ }
}
template <class MemDepPred, class Impl>
void
MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
{
- // Only stores have dependents.
- if (!inst->isStore()) {
+ // Only stores and barriers have dependents.
+ if (!inst->isStore() && !inst->isMemBarrier() && !inst->isWriteBarrier()) {
return;
}
- // Wake any dependencies.
- sd_it_t sd_it = storeDependents.find(inst->seqNum);
+ MemDepEntryPtr inst_entry = findInHash(inst);
- // If there's no entry, then return. Really there should only be
- // no entry if the instruction is a load.
- if (sd_it == storeDependents.end()) {
- DPRINTF(MemDepUnit, "MemDepUnit: Instruction PC %#x, sequence "
- "number %i has no dependents.\n",
- inst->readPC(), inst->seqNum);
+ for (int i = 0; i < inst_entry->dependInsts.size(); ++i ) {
+ MemDepEntryPtr woken_inst = inst_entry->dependInsts[i];
- return;
- }
-
- for (int i = 0; i < (*sd_it).second.size(); ++i ) {
- dep_it_t woken_inst = (*sd_it).second[i];
-
- DPRINTF(MemDepUnit, "MemDepUnit: Waking up a dependent inst, "
- "sequence number %i.\n",
- (*woken_inst).seqNum);
-#if 0
- // Should we have reached instructions that are actually squashed,
- // there will be no more useful instructions in this dependency
- // list. Break out early.
- if (waitingInsts.find(woken_inst) == waitingInsts.end()) {
- DPRINTF(MemDepUnit, "MemDepUnit: Dependents on inst PC %#x "
- "are squashed, starting at SN %i. Breaking early.\n",
- inst->readPC(), woken_inst);
- break;
+ if (!woken_inst->inst) {
+ // Potentially removed mem dep entries could be on this list
+ continue;
}
-#endif
- if ((*woken_inst).regsReady) {
+ DPRINTF(MemDepUnit, "Waking up a dependent inst, "
+ "[sn:%lli].\n",
+ woken_inst->inst->seqNum);
+
+ if (woken_inst->regsReady && !woken_inst->squashed) {
moveToReady(woken_inst);
} else {
- (*woken_inst).memDepReady = true;
+ woken_inst->memDepReady = true;
}
}
- storeDependents.erase(sd_it);
+ inst_entry->dependInsts.clear();
}
template <class MemDepPred, class Impl>
void
-MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num)
+MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
+ unsigned tid)
{
-
- if (!waitingInsts.empty()) {
- dep_it_t waiting_it = waitingInsts.end();
-
- --waiting_it;
-
- // Remove entries from the renamed list as long as we haven't reached
- // the end and the entries continue to be younger than the squashed.
- while (!waitingInsts.empty() &&
- (*waiting_it).seqNum > squashed_num)
- {
- if (!(*waiting_it).memDepReady &&
- (*waiting_it).storeDep != storeDependents.end()) {
- sd_it_t sd_it = (*waiting_it).storeDep;
-
- // Make sure the iterator that the store has pointing
- // back is actually to this instruction.
- assert((*sd_it).second.back() == waiting_it);
-
- // Now remove this from the store's list of dependent
- // instructions.
- (*sd_it).second.pop_back();
+ if (!instsToReplay.empty()) {
+ ListIt replay_it = instsToReplay.begin();
+ while (replay_it != instsToReplay.end()) {
+ if ((*replay_it)->threadNumber == tid &&
+ (*replay_it)->seqNum > squashed_num) {
+ instsToReplay.erase(replay_it++);
+ } else {
+ ++replay_it;
}
-
- waitingInsts.erase(waiting_it--);
}
}
- if (!readyInsts.empty()) {
- sn_it_t ready_it = readyInsts.end();
+ ListIt squash_it = instList[tid].end();
+ --squash_it;
- --ready_it;
+ MemDepHashIt hash_it;
- // Same for the ready list.
- while (!readyInsts.empty() &&
- (*ready_it) > squashed_num)
- {
- readyInsts.erase(ready_it--);
- }
- }
+ while (!instList[tid].empty() &&
+ (*squash_it)->seqNum > squashed_num) {
- if (!storeDependents.empty()) {
- sd_it_t dep_it = storeDependents.end();
+ DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
+ (*squash_it)->seqNum);
- --dep_it;
+ hash_it = memDepHash.find((*squash_it)->seqNum);
- // Same for the dependencies list.
- while (!storeDependents.empty() &&
- (*dep_it).first > squashed_num)
- {
- // This store's list of dependent instructions should be empty.
- assert((*dep_it).second.empty());
+ assert(hash_it != memDepHash.end());
- storeDependents.erase(dep_it--);
- }
+ (*hash_it).second->squashed = true;
+
+ (*hash_it).second = NULL;
+
+ memDepHash.erase(hash_it);
+ MemDepEntry::memdep_erase++;
+
+ instList[tid].erase(squash_it--);
}
// Tell the dependency predictor to squash as well.
- depPred.squash(squashed_num);
+ depPred.squash(squashed_num, tid);
}
template <class MemDepPred, class Impl>
@@ -397,7 +480,7 @@ void
MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
DynInstPtr &violating_load)
{
- DPRINTF(MemDepUnit, "MemDepUnit: Passing violating PCs to store sets,"
+ DPRINTF(MemDepUnit, "Passing violating PCs to store sets,"
" load: %#x, store: %#x\n", violating_load->readPC(),
store_inst->readPC());
// Tell the memory dependence unit of the violation.
@@ -405,15 +488,64 @@ MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
}
template <class MemDepPred, class Impl>
+void
+MemDepUnit<MemDepPred, Impl>::issue(DynInstPtr &inst)
+{
+ DPRINTF(MemDepUnit, "Issuing instruction PC %#x [sn:%lli].\n",
+ inst->readPC(), inst->seqNum);
+
+ depPred.issued(inst->readPC(), inst->seqNum, inst->isStore());
+}
+
+template <class MemDepPred, class Impl>
+inline typename MemDepUnit<MemDepPred,Impl>::MemDepEntryPtr &
+MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstPtr &inst)
+{
+ MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
+
+ assert(hash_it != memDepHash.end());
+
+ return (*hash_it).second;
+}
+
+template <class MemDepPred, class Impl>
inline void
-MemDepUnit<MemDepPred, Impl>::moveToReady(dep_it_t &woken_inst)
+MemDepUnit<MemDepPred, Impl>::moveToReady(MemDepEntryPtr &woken_inst_entry)
+{
+ DPRINTF(MemDepUnit, "Adding instruction [sn:%lli] "
+ "to the ready list.\n", woken_inst_entry->inst->seqNum);
+
+ assert(!woken_inst_entry->squashed);
+
+ iqPtr->addReadyMemInst(woken_inst_entry->inst);
+}
+
+
+template <class MemDepPred, class Impl>
+void
+MemDepUnit<MemDepPred, Impl>::dumpLists()
{
- DPRINTF(MemDepUnit, "MemDepUnit: Adding instruction sequence number %i "
- "to the ready list.\n", (*woken_inst).seqNum);
+ for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
+ cprintf("Instruction list %i size: %i\n",
+ tid, instList[tid].size());
+
+ ListIt inst_list_it = instList[tid].begin();
+ int num = 0;
+
+ while (inst_list_it != instList[tid].end()) {
+ cprintf("Instruction:%i\nPC:%#x\n[sn:%i]\n[tid:%i]\nIssued:%i\n"
+ "Squashed:%i\n\n",
+ num, (*inst_list_it)->readPC(),
+ (*inst_list_it)->seqNum,
+ (*inst_list_it)->threadNumber,
+ (*inst_list_it)->isIssued(),
+ (*inst_list_it)->isSquashed());
+ inst_list_it++;
+ ++num;
+ }
+ }
- // Add it to the ready list.
- readyInsts.insert((*woken_inst).seqNum);
+ cprintf("Memory dependence hash size: %i\n", memDepHash.size());
- // Remove it from the waiting instructions.
- waitingInsts.erase(woken_inst);
+ cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count);
}
diff --git a/src/cpu/o3/ras.cc b/src/cpu/o3/ras.cc
index 0a7d6ca63..0b3ea4918 100644
--- a/src/cpu/o3/ras.cc
+++ b/src/cpu/o3/ras.cc
@@ -28,12 +28,24 @@
#include "cpu/o3/ras.hh"
-ReturnAddrStack::ReturnAddrStack(unsigned _numEntries)
- : numEntries(_numEntries), usedEntries(0),
- tos(0)
+void
+ReturnAddrStack::init(unsigned _numEntries)
{
- addrStack = new Addr[numEntries];
+ numEntries = _numEntries;
+ usedEntries = 0;
+ tos = 0;
+
+ addrStack.resize(numEntries);
+
+ for (int i = 0; i < numEntries; ++i)
+ addrStack[i] = 0;
+}
+void
+ReturnAddrStack::reset()
+{
+ usedEntries = 0;
+ tos = 0;
for (int i = 0; i < numEntries; ++i)
addrStack[i] = 0;
}
@@ -53,9 +65,6 @@ ReturnAddrStack::push(const Addr &return_addr)
void
ReturnAddrStack::pop()
{
- // Not sure it's possible to really track usedEntries properly.
-// assert(usedEntries > 0);
-
if (usedEntries > 0) {
--usedEntries;
}
diff --git a/src/cpu/o3/ras.hh b/src/cpu/o3/ras.hh
index 46d98181e..27e7c2df4 100644
--- a/src/cpu/o3/ras.hh
+++ b/src/cpu/o3/ras.hh
@@ -26,43 +26,70 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_RAS_HH__
-#define __CPU_O3_CPU_RAS_HH__
+#ifndef __CPU_O3_RAS_HH__
+#define __CPU_O3_RAS_HH__
// For Addr type.
#include "arch/isa_traits.hh"
+#include <vector>
+/** Return address stack class, implements a simple RAS. */
class ReturnAddrStack
{
public:
- ReturnAddrStack(unsigned numEntries);
+ /** Creates a return address stack, but init() must be called prior to
+ * use.
+ */
+ ReturnAddrStack() {}
+ /** Initializes RAS with a specified number of entries.
+ * @param numEntries Number of entries in the RAS.
+ */
+ void init(unsigned numEntries);
+
+ void reset();
+
+ /** Returns the top address on the RAS. */
Addr top()
{ return addrStack[tos]; }
+ /** Returns the index of the top of the RAS. */
unsigned topIdx()
{ return tos; }
+ /** Pushes an address onto the RAS. */
void push(const Addr &return_addr);
+ /** Pops the top address from the RAS. */
void pop();
+ /** Changes index to the top of the RAS, and replaces the top address with
+ * a new target.
+ * @param top_entry_idx The index of the RAS that will now be the top.
+ * @param restored_target The new target address of the new top of the RAS.
+ */
void restore(unsigned top_entry_idx, const Addr &restored_target);
private:
+ /** Increments the top of stack index. */
inline void incrTos()
{ if (++tos == numEntries) tos = 0; }
+ /** Decrements the top of stack index. */
inline void decrTos()
{ tos = (tos == 0 ? numEntries - 1 : tos - 1); }
- Addr *addrStack;
+ /** The RAS itself. */
+ std::vector<Addr> addrStack;
+ /** The number of entries in the RAS. */
unsigned numEntries;
+ /** The number of used entries in the RAS. */
unsigned usedEntries;
+ /** The top of stack index. */
unsigned tos;
};
-#endif // __CPU_O3_CPU_RAS_HH__
+#endif // __CPU_O3_RAS_HH__
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index a5cfa8f3c..3350903db 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -26,10 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_REGFILE_HH__
-#define __CPU_O3_CPU_REGFILE_HH__
-
-// @todo: Destructor
+#ifndef __CPU_O3_REGFILE_HH__
+#define __CPU_O3_REGFILE_HH__
#include "arch/isa_traits.hh"
#include "arch/faults.hh"
@@ -42,11 +40,14 @@
#endif
-// This really only depends on the ISA, and not the Impl. It might be nicer
-// to see if I can make it depend on nothing...
-// Things that are in the ifdef FULL_SYSTEM are pretty dependent on the ISA,
-// and should go in the AlphaFullCPU.
+#include <vector>
+/**
+ * Simple physical register file class.
+ * This really only depends on the ISA, and not the Impl. Things that are
+ * in the ifdef FULL_SYSTEM are pretty dependent on the ISA, and probably
+ * should go in the AlphaFullCPU.
+ */
template <class Impl>
class PhysRegFile
{
@@ -55,19 +56,18 @@ class PhysRegFile
typedef TheISA::FloatReg FloatReg;
typedef TheISA::MiscRegFile MiscRegFile;
typedef TheISA::MiscReg MiscReg;
+ // Note that most of the definitions of the IntReg, FloatReg, etc. exist
+ // within the Impl/ISA class and not within this PhysRegFile class.
- //Note that most of the definitions of the IntReg, FloatReg, etc. exist
- //within the Impl/ISA class and not within this PhysRegFile class.
-
- //Will need some way to allow stuff like swap_palshadow to access the
- //correct registers. Might require code changes to swap_palshadow and
- //other execution contexts.
-
- //Will make these registers public for now, but they probably should
- //be private eventually with some accessor functions.
+ // Will make these registers public for now, but they probably should
+ // be private eventually with some accessor functions.
public:
typedef typename Impl::FullCPU FullCPU;
+ /**
+ * Constructs a physical register file with the specified amount of
+ * integer and floating point registers.
+ */
PhysRegFile(unsigned _numPhysicalIntRegs,
unsigned _numPhysicalFloatRegs);
@@ -80,6 +80,7 @@ class PhysRegFile
// void serialize(std::ostream &os);
// void unserialize(Checkpoint *cp, const std::string &section);
+ /** Reads an integer register. */
uint64_t readIntReg(PhysRegIndex reg_idx)
{
assert(reg_idx < numPhysicalIntRegs);
@@ -104,6 +105,7 @@ class PhysRegFile
return floatReg;
}
+ /** Reads a floating point register (double precision). */
FloatReg readFloatReg(PhysRegIndex reg_idx)
{
// Remove the base Float reg dependency.
@@ -119,6 +121,7 @@ class PhysRegFile
return floatReg;
}
+ /** Reads a floating point register as an integer. */
FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
{
// Remove the base Float reg dependency.
@@ -149,6 +152,7 @@ class PhysRegFile
return floatRegBits;
}
+ /** Sets an integer register to the given value. */
void setIntReg(PhysRegIndex reg_idx, uint64_t val)
{
assert(reg_idx < numPhysicalIntRegs);
@@ -156,9 +160,11 @@ class PhysRegFile
DPRINTF(IEW, "RegFile: Setting int register %i to %lli\n",
int(reg_idx), val);
- intRegFile[reg_idx] = val;
+ if (reg_idx != TheISA::ZeroReg)
+ intRegFile[reg_idx] = val;
}
+ /** Sets a single precision floating point register to the given value. */
void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
{
// Remove the base Float reg dependency.
@@ -169,9 +175,11 @@ class PhysRegFile
DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
int(reg_idx), (double)val);
- floatRegFile.setReg(reg_idx, val, width);
+ if (reg_idx != TheISA::ZeroReg)
+ floatRegFile.setReg(reg_idx, val, width);
}
+ /** Sets a double precision floating point register to the given value. */
void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
{
// Remove the base Float reg dependency.
@@ -182,9 +190,11 @@ class PhysRegFile
DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
int(reg_idx), (double)val);
- floatRegFile.setReg(reg_idx, val);
+ if (reg_idx != TheISA::ZeroReg)
+ floatRegFile.setReg(reg_idx, val);
}
+ /** Sets a floating point register to the given integer value. */
void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
{
// Remove the base Float reg dependency.
@@ -207,79 +217,59 @@ class PhysRegFile
DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
int(reg_idx), (uint64_t)val);
-
- floatRegFile.setRegBits(reg_idx, val);
- }
-
- uint64_t readPC()
- {
- return pc;
- }
-
- void setPC(uint64_t val)
- {
- pc = val;
}
- void setNextPC(uint64_t val)
+ MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault,
+ unsigned thread_id)
{
- npc = val;
+ return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
+ cpu->xcBase(thread_id));
}
- //Consider leaving this stuff and below in some implementation specific
- //file as opposed to the general register file. Or have a derived class.
- MiscReg readMiscReg(int misc_reg)
+ Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
{
- // Dummy function for now.
- // @todo: Fix this once proxy XC is used.
- return 0;
+ return miscRegs[thread_id].setReg(misc_reg, val);
}
- Fault setMiscReg(int misc_reg, const MiscReg &val)
+ Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val,
+ unsigned thread_id)
{
- // Dummy function for now.
- // @todo: Fix this once proxy XC is used.
- return NoFault;
+ return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
+ cpu->xcBase(thread_id));
}
#if FULL_SYSTEM
int readIntrFlag() { return intrflag; }
+ /** Sets an interrupt flag. */
void setIntrFlag(int val) { intrflag = val; }
#endif
- // These should be private eventually, but will be public for now
- // so that I can hack around the initregs issue.
public:
/** (signed) integer register file. */
- IntReg *intRegFile;
+ std::vector<IntReg> intRegFile;
/** Floating point register file. */
- FloatReg *floatRegFile;
+ std::vector<FloatReg> floatRegFile;
/** Miscellaneous register file. */
- MiscRegFile miscRegs;
-
- /** Program counter. */
- Addr pc;
-
- /** Next-cycle program counter. */
- Addr npc;
+ MiscRegFile miscRegs[Impl::MaxThreads];
#if FULL_SYSTEM
private:
- // This is ISA specifc stuff; remove it eventually once ISAImpl is used
-// IntReg palregs[NumIntRegs]; // PAL shadow registers
int intrflag; // interrupt flag
- bool pal_shadow; // using pal_shadow registers
#endif
private:
+ /** CPU pointer. */
FullCPU *cpu;
public:
+ /** Sets the CPU pointer. */
void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; }
+ /** Number of physical integer registers. */
unsigned numPhysicalIntRegs;
+ /** Number of physical floating point registers. */
unsigned numPhysicalFloatRegs;
};
@@ -289,11 +279,11 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
: numPhysicalIntRegs(_numPhysicalIntRegs),
numPhysicalFloatRegs(_numPhysicalFloatRegs)
{
- intRegFile = new IntReg[numPhysicalIntRegs];
- floatRegFile = new FloatReg[numPhysicalFloatRegs];
+ intRegFile.resize(numPhysicalIntRegs);
+ floatRegFile.resize(numPhysicalFloatRegs);
- memset(intRegFile, 0, sizeof(*intRegFile));
- memset(floatRegFile, 0, sizeof(*floatRegFile));
+ //memset(intRegFile, 0, sizeof(*intRegFile));
+ //memset(floatRegFile, 0, sizeof(*floatRegFile));
}
-#endif // __CPU_O3_CPU_REGFILE_HH__
+#endif
diff --git a/src/cpu/o3/rename.cc b/src/cpu/o3/rename.cc
index 6e9ee23da..4dc3bf6b2 100644
--- a/src/cpu/o3/rename.cc
+++ b/src/cpu/o3/rename.cc
@@ -30,4 +30,4 @@
#include "cpu/o3/alpha_impl.hh"
#include "cpu/o3/rename_impl.hh"
-template class SimpleRename<AlphaSimpleImpl>;
+template class DefaultRename<AlphaSimpleImpl>;
diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh
index 07b442964..3f1a27bb5 100644
--- a/src/cpu/o3/rename.hh
+++ b/src/cpu/o3/rename.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,23 +26,28 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-// Todo:
-// Fix up trap and barrier handling.
-// May want to have different statuses to differentiate the different stall
-// conditions.
-
-#ifndef __CPU_O3_CPU_SIMPLE_RENAME_HH__
-#define __CPU_O3_CPU_SIMPLE_RENAME_HH__
+#ifndef __CPU_O3_RENAME_HH__
+#define __CPU_O3_RENAME_HH__
#include <list>
#include "base/statistics.hh"
#include "base/timebuf.hh"
-// Will need rename maps for both the int reg file and fp reg file.
-// Or change rename map class to handle both. (RegFile handles both.)
+/**
+ * DefaultRename handles both single threaded and SMT rename. Its
+ * width is specified by the parameters; each cycle it tries to rename
+ * that many instructions. It holds onto the rename history of all
+ * instructions with destination registers, storing the
+ * arch. register, the new physical register, and the old physical
+ * register, to allow for undoing of mappings if squashing happens, or
+ * freeing up registers upon commit. Rename handles blocking if the
+ * ROB, IQ, or LSQ is going to be full. Rename also handles barriers,
+ * and does so by stalling on the instruction until the ROB is empty
+ * and there are no instructions in flight to the ROB.
+ */
template<class Impl>
-class SimpleRename
+class DefaultRename
{
public:
// Typedefs from the Impl.
@@ -51,112 +56,237 @@ class SimpleRename
typedef typename Impl::FullCPU FullCPU;
typedef typename Impl::Params Params;
- typedef typename CPUPol::FetchStruct FetchStruct;
+ // Typedefs from the CPUPol
typedef typename CPUPol::DecodeStruct DecodeStruct;
typedef typename CPUPol::RenameStruct RenameStruct;
typedef typename CPUPol::TimeStruct TimeStruct;
-
- // Typedefs from the CPUPol
typedef typename CPUPol::FreeList FreeList;
typedef typename CPUPol::RenameMap RenameMap;
+ // These are used only for initialization.
+ typedef typename CPUPol::IEW IEW;
+ typedef typename CPUPol::Commit Commit;
// Typedefs from the ISA.
typedef TheISA::RegIndex RegIndex;
+ // A list is used to queue the instructions. Barrier insts must
+ // be added to the front of the list, which is the only reason for
+ // using a list instead of a queue. (Most other stages use a
+ // queue)
+ typedef std::list<DynInstPtr> InstQueue;
+
public:
- // Rename will block if ROB becomes full or issue queue becomes full,
- // or there are no free registers to rename to.
- // Only case where rename squashes is if IEW squashes.
- enum Status {
+ /** Overall rename status. Used to determine if the CPU can
+ * deschedule itself due to a lack of activity.
+ */
+ enum RenameStatus {
+ Active,
+ Inactive
+ };
+
+ /** Individual thread status. */
+ enum ThreadStatus {
Running,
Idle,
+ StartSquash,
Squashing,
Blocked,
Unblocking,
- BarrierStall
+ SerializeStall
};
private:
- Status _status;
+ /** Rename status. */
+ RenameStatus _status;
+
+ /** Per-thread status. */
+ ThreadStatus renameStatus[Impl::MaxThreads];
public:
- SimpleRename(Params &params);
+ /** DefaultRename constructor. */
+ DefaultRename(Params *params);
+ /** Returns the name of rename. */
+ std::string name() const;
+
+ /** Registers statistics. */
void regStats();
+ /** Sets CPU pointer. */
void setCPU(FullCPU *cpu_ptr);
+ /** Sets the main backwards communication time buffer pointer. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
+ /** Sets pointer to time buffer used to communicate to the next stage. */
void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
+ /** Sets pointer to time buffer coming from decode. */
void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
- void setRenameMap(RenameMap *rm_ptr);
+ /** Sets pointer to IEW stage. Used only for initialization. */
+ void setIEWStage(IEW *iew_stage)
+ { iew_ptr = iew_stage; }
+
+ /** Sets pointer to commit stage. Used only for initialization. */
+ void setCommitStage(Commit *commit_stage)
+ { commit_ptr = commit_stage; }
+
+ private:
+ /** Pointer to IEW stage. Used only for initialization. */
+ IEW *iew_ptr;
+
+ /** Pointer to commit stage. Used only for initialization. */
+ Commit *commit_ptr;
+ public:
+ /** Initializes variables for the stage. */
+ void initStage();
+
+ /** Sets pointer to list of active threads. */
+ void setActiveThreads(std::list<unsigned> *at_ptr);
+
+ /** Sets pointer to rename maps (per-thread structures). */
+ void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
+
+ /** Sets pointer to the free list. */
void setFreeList(FreeList *fl_ptr);
- void dumpHistory();
+ /** Sets pointer to the scoreboard. */
+ void setScoreboard(Scoreboard *_scoreboard);
- void tick();
+ void switchOut();
+
+ void doSwitchOut();
+
+ void takeOverFrom();
- void rename();
+ /** Squashes all instructions in a thread. */
+ void squash(unsigned tid);
+
+ /** Ticks rename, which processes all input signals and attempts to rename
+ * as many instructions as possible.
+ */
+ void tick();
- void squash();
+ /** Debugging function used to dump history buffer of renamings. */
+ void dumpHistory();
private:
- void block();
+ /** Determines what to do based on rename's current status.
+ * @param status_change rename() sets this variable if there was a status
+ * change (ie switching from blocking to unblocking).
+ * @param tid Thread id to rename instructions from.
+ */
+ void rename(bool &status_change, unsigned tid);
+
+ /** Renames instructions for the given thread. Also handles serializing
+ * instructions.
+ */
+ void renameInsts(unsigned tid);
+
+ /** Inserts unused instructions from a given thread into the skid buffer,
+ * to be renamed once rename unblocks.
+ */
+ void skidInsert(unsigned tid);
+
+ /** Separates instructions from decode into individual lists of instructions
+ * sorted by thread.
+ */
+ void sortInsts();
+
+ /** Returns if all of the skid buffers are empty. */
+ bool skidsEmpty();
+
+ /** Updates overall rename status based on all of the threads' statuses. */
+ void updateStatus();
+
+ /** Switches rename to blocking, and signals back that rename has become
+ * blocked.
+ * @return Returns true if there is a status change.
+ */
+ bool block(unsigned tid);
+
+ /** Switches rename to unblocking if the skid buffer is empty, and signals
+ * back that rename has unblocked.
+ * @return Returns true if there is a status change.
+ */
+ bool unblock(unsigned tid);
- inline void unblock();
+ /** Executes actual squash, removing squashed instructions. */
+ void doSquash(unsigned tid);
- void doSquash();
+ /** Removes a committed instruction's rename history. */
+ void removeFromHistory(InstSeqNum inst_seq_num, unsigned tid);
- void removeFromHistory(InstSeqNum inst_seq_num);
+ /** Renames the source registers of an instruction. */
+ inline void renameSrcRegs(DynInstPtr &inst, unsigned tid);
- inline void renameSrcRegs(DynInstPtr &inst);
+ /** Renames the destination registers of an instruction. */
+ inline void renameDestRegs(DynInstPtr &inst, unsigned tid);
- inline void renameDestRegs(DynInstPtr &inst);
+ /** Calculates the number of free ROB entries for a specific thread. */
+ inline int calcFreeROBEntries(unsigned tid);
- inline int calcFreeROBEntries();
+ /** Calculates the number of free IQ entries for a specific thread. */
+ inline int calcFreeIQEntries(unsigned tid);
- inline int calcFreeIQEntries();
+ /** Calculates the number of free LSQ entries for a specific thread. */
+ inline int calcFreeLSQEntries(unsigned tid);
- /** Holds the previous information for each rename.
- * Note that often times the inst may have been deleted, so only access
- * the pointer for the address and do not dereference it.
+ /** Returns the number of valid instructions coming from decode. */
+ unsigned validInsts();
+
+ /** Reads signals telling rename to block/unblock. */
+ void readStallSignals(unsigned tid);
+
+ /** Checks if any stages are telling rename to block. */
+ bool checkStall(unsigned tid);
+
+ void readFreeEntries(unsigned tid);
+
+ bool checkSignalsAndUpdate(unsigned tid);
+
+ /** Either serializes on the next instruction available in the InstQueue,
+ * or records that it must serialize on the next instruction to enter
+ * rename.
+ * @param inst_list The list of younger, unprocessed instructions for the
+ * thread that has the serializeAfter instruction.
+ * @param tid The thread id.
+ */
+ void serializeAfter(InstQueue &inst_list, unsigned tid);
+
+ /** Holds the information for each destination register rename. It holds
+ * the instruction's sequence number, the arch register, the old physical
+ * register for that arch. register, and the new physical register.
*/
struct RenameHistory {
RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
: instSeqNum(_instSeqNum), archReg(_archReg),
- newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg),
- placeHolder(false)
- {
- }
-
- /** Constructor used specifically for cases where a place holder
- * rename history entry is being made.
- */
- RenameHistory(InstSeqNum _instSeqNum)
- : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0),
- prevPhysReg(0), placeHolder(true)
+ newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
{
}
+ /** The sequence number of the instruction that renamed. */
InstSeqNum instSeqNum;
+ /** The architectural register index that was renamed. */
RegIndex archReg;
+ /** The new physical register that the arch. register is renamed to. */
PhysRegIndex newPhysReg;
+ /** The old physical register that the arch. register was renamed to. */
PhysRegIndex prevPhysReg;
- bool placeHolder;
};
- std::list<RenameHistory> historyBuffer;
+ /** A per-thread list of all destination register renames, used to either
+ * undo rename mappings or free old physical registers.
+ */
+ std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
- /** CPU interface. */
+ /** Pointer to CPU. */
FullCPU *cpu;
- // Interfaces to objects outside of rename.
- /** Time buffer interface. */
+ /** Pointer to main time buffer used for backwards communication. */
TimeBuffer<TimeStruct> *timeBuffer;
/** Wire to get IEW's output from backwards time buffer. */
@@ -166,7 +296,6 @@ class SimpleRename
typename TimeBuffer<TimeStruct>::wire fromCommit;
/** Wire to write infromation heading to previous stages. */
- // Might not be the best name as not only decode will read it.
typename TimeBuffer<TimeStruct>::wire toDecode;
/** Rename instruction queue. */
@@ -181,15 +310,71 @@ class SimpleRename
/** Wire to get decode's output from decode queue. */
typename TimeBuffer<DecodeStruct>::wire fromDecode;
+ /** Queue of all instructions coming from decode this cycle. */
+ InstQueue insts[Impl::MaxThreads];
+
/** Skid buffer between rename and decode. */
- std::queue<DecodeStruct> skidBuffer;
+ InstQueue skidBuffer[Impl::MaxThreads];
/** Rename map interface. */
- SimpleRenameMap *renameMap;
+ RenameMap *renameMap[Impl::MaxThreads];
/** Free list interface. */
FreeList *freeList;
+ /** Pointer to the list of active threads. */
+ std::list<unsigned> *activeThreads;
+
+ /** Pointer to the scoreboard. */
+ Scoreboard *scoreboard;
+
+ /** Count of instructions in progress that have been sent off to the IQ
+ * and ROB, but are not yet included in their occupancy counts.
+ */
+ int instsInProgress[Impl::MaxThreads];
+
+ /** Variable that tracks if decode has written to the time buffer this
+ * cycle. Used to tell CPU if there is activity this cycle.
+ */
+ bool wroteToTimeBuffer;
+
+ /** Structures whose free entries impact the amount of instructions that
+ * can be renamed.
+ */
+ struct FreeEntries {
+ unsigned iqEntries;
+ unsigned lsqEntries;
+ unsigned robEntries;
+ };
+
+ /** Per-thread tracking of the number of free entries of back-end
+ * structures.
+ */
+ FreeEntries freeEntries[Impl::MaxThreads];
+
+ /** Records if the ROB is empty. In SMT mode the ROB may be dynamically
+ * partitioned between threads, so the ROB must tell rename when it is
+ * empty.
+ */
+ bool emptyROB[Impl::MaxThreads];
+
+ /** Source of possible stalls. */
+ struct Stalls {
+ bool iew;
+ bool commit;
+ };
+
+ /** Tracks which stages are telling decode to stall. */
+ Stalls stalls[Impl::MaxThreads];
+
+ /** The serialize instruction that rename has stalled on. */
+ DynInstPtr serializeInst[Impl::MaxThreads];
+
+ /** Records if rename needs to serialize on the next instruction for any
+ * thread.
+ */
+ bool serializeOnNextInst[Impl::MaxThreads];
+
/** Delay between iew and rename, in ticks. */
int iewToRenameDelay;
@@ -207,27 +392,71 @@ class SimpleRename
*/
unsigned commitWidth;
- /** The instruction that rename is currently on. It needs to have
- * persistent state so that when a stall occurs in the middle of a
- * group of instructions, it can restart at the proper instruction.
+ /** The index of the instruction in the time buffer to IEW that rename is
+ * currently using.
+ */
+ unsigned toIEWIndex;
+
+ /** Whether or not rename needs to block this cycle. */
+ bool blockThisCycle;
+
+ /** The number of threads active in rename. */
+ unsigned numThreads;
+
+ /** The maximum skid buffer size. */
+ unsigned skidBufferMax;
+
+ /** Enum to record the source of a structure full stall. Can come from
+ * either ROB, IQ, LSQ, and it is priortized in that order.
+ */
+ enum FullSource {
+ ROB,
+ IQ,
+ LSQ,
+ NONE
+ };
+
+ /** Function used to increment the stat that corresponds to the source of
+ * the stall.
*/
- unsigned numInst;
+ inline void incrFullStat(const FullSource &source);
+ /** Stat for total number of cycles spent squashing. */
Stats::Scalar<> renameSquashCycles;
+ /** Stat for total number of cycles spent idle. */
Stats::Scalar<> renameIdleCycles;
+ /** Stat for total number of cycles spent blocking. */
Stats::Scalar<> renameBlockCycles;
+ /** Stat for total number of cycles spent stalling for a serializing inst. */
+ Stats::Scalar<> renameSerializeStallCycles;
+ /** Stat for total number of cycles spent running normally. */
+ Stats::Scalar<> renameRunCycles;
+ /** Stat for total number of cycles spent unblocking. */
Stats::Scalar<> renameUnblockCycles;
+ /** Stat for total number of renamed instructions. */
Stats::Scalar<> renameRenamedInsts;
+ /** Stat for total number of squashed instructions that rename discards. */
Stats::Scalar<> renameSquashedInsts;
+ /** Stat for total number of times that the ROB starts a stall in rename. */
Stats::Scalar<> renameROBFullEvents;
+ /** Stat for total number of times that the IQ starts a stall in rename. */
Stats::Scalar<> renameIQFullEvents;
+ /** Stat for total number of times that the LSQ starts a stall in rename. */
+ Stats::Scalar<> renameLSQFullEvents;
+ /** Stat for total number of times that rename runs out of free registers
+ * to use to rename. */
Stats::Scalar<> renameFullRegistersEvents;
+ /** Stat for total number of renamed destination registers. */
Stats::Scalar<> renameRenamedOperands;
+ /** Stat for total number of source register rename lookups. */
Stats::Scalar<> renameRenameLookups;
- Stats::Scalar<> renameHBPlaceHolders;
+ /** Stat for total number of committed renaming mappings. */
Stats::Scalar<> renameCommittedMaps;
+ /** Stat for total number of mappings that were undone due to a squash. */
Stats::Scalar<> renameUndoneMaps;
- Stats::Scalar<> renameValidUndoneMaps;
+ Stats::Scalar<> renamedSerializing;
+ Stats::Scalar<> renamedTempSerializing;
+ Stats::Scalar<> renameSkidInsts;
};
-#endif // __CPU_O3_CPU_SIMPLE_RENAME_HH__
+#endif // __CPU_O3_RENAME_HH__
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 2068b36ab..b4f1077d1 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -31,97 +31,146 @@
#include "config/full_system.hh"
#include "cpu/o3/rename.hh"
+using namespace std;
+
+template <class Impl>
+DefaultRename<Impl>::DefaultRename(Params *params)
+ : iewToRenameDelay(params->iewToRenameDelay),
+ decodeToRenameDelay(params->decodeToRenameDelay),
+ commitToRenameDelay(params->commitToRenameDelay),
+ renameWidth(params->renameWidth),
+ commitWidth(params->commitWidth),
+ numThreads(params->numberOfThreads)
+{
+ _status = Inactive;
+
+ for (int i=0; i< numThreads; i++) {
+ renameStatus[i] = Idle;
+
+ freeEntries[i].iqEntries = 0;
+ freeEntries[i].lsqEntries = 0;
+ freeEntries[i].robEntries = 0;
+
+ stalls[i].iew = false;
+ stalls[i].commit = false;
+ serializeInst[i] = NULL;
+
+ instsInProgress[i] = 0;
+
+ emptyROB[i] = true;
+
+ serializeOnNextInst[i] = false;
+ }
+
+ // @todo: Make into a parameter.
+ skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
+}
+
template <class Impl>
-SimpleRename<Impl>::SimpleRename(Params &params)
- : iewToRenameDelay(params.iewToRenameDelay),
- decodeToRenameDelay(params.decodeToRenameDelay),
- commitToRenameDelay(params.commitToRenameDelay),
- renameWidth(params.renameWidth),
- commitWidth(params.commitWidth),
- numInst(0)
+std::string
+DefaultRename<Impl>::name() const
{
- _status = Idle;
+ return cpu->name() + ".rename";
}
template <class Impl>
void
-SimpleRename<Impl>::regStats()
+DefaultRename<Impl>::regStats()
{
renameSquashCycles
- .name(name() + ".renameSquashCycles")
+ .name(name() + ".RENAME:SquashCycles")
.desc("Number of cycles rename is squashing")
.prereq(renameSquashCycles);
renameIdleCycles
- .name(name() + ".renameIdleCycles")
+ .name(name() + ".RENAME:IdleCycles")
.desc("Number of cycles rename is idle")
.prereq(renameIdleCycles);
renameBlockCycles
- .name(name() + ".renameBlockCycles")
+ .name(name() + ".RENAME:BlockCycles")
.desc("Number of cycles rename is blocking")
.prereq(renameBlockCycles);
+ renameSerializeStallCycles
+ .name(name() + ".RENAME:serializeStallCycles")
+ .desc("count of cycles rename stalled for serializing inst")
+ .flags(Stats::total);
+ renameRunCycles
+ .name(name() + ".RENAME:RunCycles")
+ .desc("Number of cycles rename is running")
+ .prereq(renameIdleCycles);
renameUnblockCycles
- .name(name() + ".renameUnblockCycles")
+ .name(name() + ".RENAME:UnblockCycles")
.desc("Number of cycles rename is unblocking")
.prereq(renameUnblockCycles);
renameRenamedInsts
- .name(name() + ".renameRenamedInsts")
+ .name(name() + ".RENAME:RenamedInsts")
.desc("Number of instructions processed by rename")
.prereq(renameRenamedInsts);
renameSquashedInsts
- .name(name() + ".renameSquashedInsts")
+ .name(name() + ".RENAME:SquashedInsts")
.desc("Number of squashed instructions processed by rename")
.prereq(renameSquashedInsts);
renameROBFullEvents
- .name(name() + ".renameROBFullEvents")
- .desc("Number of times rename has considered the ROB 'full'")
+ .name(name() + ".RENAME:ROBFullEvents")
+ .desc("Number of times rename has blocked due to ROB full")
.prereq(renameROBFullEvents);
renameIQFullEvents
- .name(name() + ".renameIQFullEvents")
- .desc("Number of times rename has considered the IQ 'full'")
+ .name(name() + ".RENAME:IQFullEvents")
+ .desc("Number of times rename has blocked due to IQ full")
.prereq(renameIQFullEvents);
+ renameLSQFullEvents
+ .name(name() + ".RENAME:LSQFullEvents")
+ .desc("Number of times rename has blocked due to LSQ full")
+ .prereq(renameLSQFullEvents);
renameFullRegistersEvents
- .name(name() + ".renameFullRegisterEvents")
+ .name(name() + ".RENAME:FullRegisterEvents")
.desc("Number of times there has been no free registers")
.prereq(renameFullRegistersEvents);
renameRenamedOperands
- .name(name() + ".renameRenamedOperands")
+ .name(name() + ".RENAME:RenamedOperands")
.desc("Number of destination operands rename has renamed")
.prereq(renameRenamedOperands);
renameRenameLookups
- .name(name() + ".renameRenameLookups")
+ .name(name() + ".RENAME:RenameLookups")
.desc("Number of register rename lookups that rename has made")
.prereq(renameRenameLookups);
- renameHBPlaceHolders
- .name(name() + ".renameHBPlaceHolders")
- .desc("Number of place holders added to the history buffer")
- .prereq(renameHBPlaceHolders);
renameCommittedMaps
- .name(name() + ".renameCommittedMaps")
+ .name(name() + ".RENAME:CommittedMaps")
.desc("Number of HB maps that are committed")
.prereq(renameCommittedMaps);
renameUndoneMaps
- .name(name() + ".renameUndoneMaps")
+ .name(name() + ".RENAME:UndoneMaps")
.desc("Number of HB maps that are undone due to squashing")
.prereq(renameUndoneMaps);
- renameValidUndoneMaps
- .name(name() + ".renameValidUndoneMaps")
- .desc("Number of HB maps that are undone, and are not place holders")
- .prereq(renameValidUndoneMaps);
+ renamedSerializing
+ .name(name() + ".RENAME:serializingInsts")
+ .desc("count of serializing insts renamed")
+ .flags(Stats::total)
+ ;
+ renamedTempSerializing
+ .name(name() + ".RENAME:tempSerializingInsts")
+ .desc("count of temporary serializing insts renamed")
+ .flags(Stats::total)
+ ;
+ renameSkidInsts
+ .name(name() + ".RENAME:skidInsts")
+ .desc("count of insts added to the skid buffer")
+ .flags(Stats::total)
+ ;
}
template <class Impl>
void
-SimpleRename<Impl>::setCPU(FullCPU *cpu_ptr)
+DefaultRename<Impl>::setCPU(FullCPU *cpu_ptr)
{
- DPRINTF(Rename, "Rename: Setting CPU pointer.\n");
+ DPRINTF(Rename, "Setting CPU pointer.\n");
cpu = cpu_ptr;
}
template <class Impl>
void
-SimpleRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
+DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
{
- DPRINTF(Rename, "Rename: Setting time buffer pointer.\n");
+ DPRINTF(Rename, "Setting time buffer pointer.\n");
timeBuffer = tb_ptr;
// Setup wire to read information from time buffer, from IEW stage.
@@ -136,9 +185,9 @@ SimpleRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
template <class Impl>
void
-SimpleRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
+DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
{
- DPRINTF(Rename, "Rename: Setting rename queue pointer.\n");
+ DPRINTF(Rename, "Setting rename queue pointer.\n");
renameQueue = rq_ptr;
// Setup wire to write information to future stages.
@@ -147,9 +196,9 @@ SimpleRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
template <class Impl>
void
-SimpleRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
+DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
{
- DPRINTF(Rename, "Rename: Setting decode queue pointer.\n");
+ DPRINTF(Rename, "Setting decode queue pointer.\n");
decodeQueue = dq_ptr;
// Setup wire to get information from decode.
@@ -158,214 +207,728 @@ SimpleRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
template <class Impl>
void
-SimpleRename<Impl>::setRenameMap(RenameMap *rm_ptr)
+DefaultRename<Impl>::initStage()
+{
+ // Grab the number of free entries directly from the stages.
+ for (int tid=0; tid < numThreads; tid++) {
+ freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
+ freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
+ freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
+ emptyROB[tid] = true;
+ }
+}
+
+template<class Impl>
+void
+DefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr)
{
- DPRINTF(Rename, "Rename: Setting rename map pointer.\n");
- renameMap = rm_ptr;
+ DPRINTF(Rename, "Setting active threads list pointer.\n");
+ activeThreads = at_ptr;
}
+
template <class Impl>
void
-SimpleRename<Impl>::setFreeList(FreeList *fl_ptr)
+DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
{
- DPRINTF(Rename, "Rename: Setting free list pointer.\n");
+ DPRINTF(Rename, "Setting rename map pointers.\n");
+
+ for (int i=0; i<numThreads; i++) {
+ renameMap[i] = &rm_ptr[i];
+ }
+}
+
+template <class Impl>
+void
+DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
+{
+ DPRINTF(Rename, "Setting free list pointer.\n");
freeList = fl_ptr;
}
+template<class Impl>
+void
+DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
+{
+ DPRINTF(Rename, "Setting scoreboard pointer.\n");
+ scoreboard = _scoreboard;
+}
+
template <class Impl>
void
-SimpleRename<Impl>::dumpHistory()
+DefaultRename<Impl>::switchOut()
{
- typename list<RenameHistory>::iterator buf_it = historyBuffer.begin();
+ cpu->signalSwitched();
+}
+
+template <class Impl>
+void
+DefaultRename<Impl>::doSwitchOut()
+{
+ for (int i = 0; i < numThreads; i++) {
+ typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin();
+
+ while (!historyBuffer[i].empty()) {
+ assert(hb_it != historyBuffer[i].end());
- while (buf_it != historyBuffer.end())
- {
- cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
- "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
- (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
+ DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
+ "number %i.\n", i, (*hb_it).instSeqNum);
- buf_it++;
+ // Tell the rename map to set the architected register to the
+ // previous physical register that it was renamed to.
+ renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
+
+ // Put the renamed physical register back on the free list.
+ freeList->addReg(hb_it->newPhysReg);
+
+ historyBuffer[i].erase(hb_it++);
+ }
+ insts[i].clear();
+ skidBuffer[i].clear();
}
}
template <class Impl>
void
-SimpleRename<Impl>::block()
+DefaultRename<Impl>::takeOverFrom()
{
- DPRINTF(Rename, "Rename: Blocking.\n");
- // Set status to Blocked.
- _status = Blocked;
+ _status = Inactive;
+ initStage();
- // Add the current inputs onto the skid buffer, so they can be
- // reprocessed when this stage unblocks.
- skidBuffer.push(*fromDecode);
+ // Reset all state prior to taking over from the other CPU.
+ for (int i=0; i< numThreads; i++) {
+ renameStatus[i] = Idle;
+
+ stalls[i].iew = false;
+ stalls[i].commit = false;
+ serializeInst[i] = NULL;
+
+ instsInProgress[i] = 0;
+
+ emptyROB[i] = true;
- // Note that this stage only signals previous stages to stall when
- // it is the cause of the stall originates at this stage. Otherwise
- // the previous stages are expected to check all possible stall signals.
+ serializeOnNextInst[i] = false;
+ }
}
template <class Impl>
-inline void
-SimpleRename<Impl>::unblock()
-{
- DPRINTF(Rename, "Rename: Read instructions out of skid buffer this "
- "cycle.\n");
- // Remove the now processed instructions from the skid buffer.
- skidBuffer.pop();
-
- // If there's still information in the skid buffer, then
- // continue to tell previous stages to stall. They will be
- // able to restart once the skid buffer is empty.
- if (!skidBuffer.empty()) {
- toDecode->renameInfo.stall = true;
- } else {
- DPRINTF(Rename, "Rename: Done unblocking.\n");
- _status = Running;
+void
+DefaultRename<Impl>::squash(unsigned tid)
+{
+ DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
+
+ // Clear the stall signal if rename was blocked or unblocking before.
+ // If it still needs to block, the blocking should happen the next
+ // cycle and there should be space to hold everything due to the squash.
+ if (renameStatus[tid] == Blocked ||
+ renameStatus[tid] == Unblocking ||
+ renameStatus[tid] == SerializeStall) {
+#if 0
+ // In syscall emulation, we can have both a block and a squash due
+ // to a syscall in the same cycle. This would cause both signals to
+ // be high. This shouldn't happen in full system.
+ if (toDecode->renameBlock[tid]) {
+ toDecode->renameBlock[tid] = 0;
+ } else {
+ toDecode->renameUnblock[tid] = 1;
+ }
+#else
+ toDecode->renameUnblock[tid] = 1;
+#endif
+ serializeInst[tid] = NULL;
+ }
+
+ // Set the status to Squashing.
+ renameStatus[tid] = Squashing;
+
+ // Squash any instructions from decode.
+ unsigned squashCount = 0;
+
+ for (int i=0; i<fromDecode->size; i++) {
+ if (fromDecode->insts[i]->threadNumber == tid) {
+ fromDecode->insts[i]->squashed = true;
+ wroteToTimeBuffer = true;
+ squashCount++;
+ }
}
+
+ insts[tid].clear();
+
+ // Clear the skid buffer in case it has any data in it.
+ skidBuffer[tid].clear();
+
+ doSquash(tid);
}
template <class Impl>
void
-SimpleRename<Impl>::doSquash()
+DefaultRename<Impl>::tick()
{
- typename list<RenameHistory>::iterator hb_it = historyBuffer.begin();
+ wroteToTimeBuffer = false;
- InstSeqNum squashed_seq_num = fromCommit->commitInfo.doneSeqNum;
+ blockThisCycle = false;
-#if FULL_SYSTEM
- assert(!historyBuffer.empty());
-#else
- // After a syscall squashes everything, the history buffer may be empty
- // but the ROB may still be squashing instructions.
- if (historyBuffer.empty()) {
+ bool status_change = false;
+
+ toIEWIndex = 0;
+
+ sortInsts();
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ // Check stall and squash signals.
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ DPRINTF(Rename, "Processing [tid:%i]\n", tid);
+
+ status_change = checkSignalsAndUpdate(tid) || status_change;
+
+ rename(status_change, tid);
+ }
+
+ if (status_change) {
+ updateStatus();
+ }
+
+ if (wroteToTimeBuffer) {
+ DPRINTF(Activity, "Activity this cycle.\n");
+ cpu->activityThisCycle();
+ }
+
+ threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ // If we committed this cycle then doneSeqNum will be > 0
+ if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
+ !fromCommit->commitInfo[tid].squash &&
+ renameStatus[tid] != Squashing) {
+
+ removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
+ tid);
+ }
+ }
+
+ // @todo: make into updateProgress function
+ for (int tid=0; tid < numThreads; tid++) {
+ instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
+
+ assert(instsInProgress[tid] >=0);
+ }
+
+}
+
+template<class Impl>
+void
+DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
+{
+ // If status is Running or idle,
+ // call renameInsts()
+ // If status is Unblocking,
+ // buffer any instructions coming from decode
+ // continue trying to empty skid buffer
+ // check if stall conditions have passed
+
+ if (renameStatus[tid] == Blocked) {
+ ++renameBlockCycles;
+ } else if (renameStatus[tid] == Squashing) {
+ ++renameSquashCycles;
+ } else if (renameStatus[tid] == SerializeStall) {
+ ++renameSerializeStallCycles;
+ }
+
+ if (renameStatus[tid] == Running ||
+ renameStatus[tid] == Idle) {
+ DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
+ "stage.\n", tid);
+
+ renameInsts(tid);
+ } else if (renameStatus[tid] == Unblocking) {
+ renameInsts(tid);
+
+ if (validInsts()) {
+ // Add the current inputs to the skid buffer so they can be
+ // reprocessed when this stage unblocks.
+ skidInsert(tid);
+ }
+
+ // If we switched over to blocking, then there's a potential for
+ // an overall status change.
+ status_change = unblock(tid) || status_change || blockThisCycle;
+ }
+}
+
+template <class Impl>
+void
+DefaultRename<Impl>::renameInsts(unsigned tid)
+{
+ // Instructions can be either in the skid buffer or the queue of
+ // instructions coming from decode, depending on the status.
+ int insts_available = renameStatus[tid] == Unblocking ?
+ skidBuffer[tid].size() : insts[tid].size();
+
+ // Check the decode queue to see if instructions are available.
+ // If there are no available instructions to rename, then do nothing.
+ if (insts_available == 0) {
+ DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
+ tid);
+ // Should I change status to idle?
+ ++renameIdleCycles;
return;
+ } else if (renameStatus[tid] == Unblocking) {
+ ++renameUnblockCycles;
+ } else if (renameStatus[tid] == Running) {
+ ++renameRunCycles;
}
-#endif // FULL_SYSTEM
- // Go through the most recent instructions, undoing the mappings
- // they did and freeing up the registers.
- while ((*hb_it).instSeqNum > squashed_seq_num)
- {
- assert(hb_it != historyBuffer.end());
+ DynInstPtr inst;
- DPRINTF(Rename, "Rename: Removing history entry with sequence "
- "number %i.\n", (*hb_it).instSeqNum);
+ // Will have to do a different calculation for the number of free
+ // entries.
+ int free_rob_entries = calcFreeROBEntries(tid);
+ int free_iq_entries = calcFreeIQEntries(tid);
+ int free_lsq_entries = calcFreeLSQEntries(tid);
+ int min_free_entries = free_rob_entries;
- // If it's not simply a place holder, then add the registers.
- if (!(*hb_it).placeHolder) {
- // Tell the rename map to set the architected register to the
- // previous physical register that it was renamed to.
- renameMap->setEntry(hb_it->archReg, hb_it->prevPhysReg);
+ FullSource source = ROB;
- // Put the renamed physical register back on the free list.
- freeList->addReg(hb_it->newPhysReg);
+ if (free_iq_entries < min_free_entries) {
+ min_free_entries = free_iq_entries;
+ source = IQ;
+ }
- ++renameValidUndoneMaps;
+ if (free_lsq_entries < min_free_entries) {
+ min_free_entries = free_lsq_entries;
+ source = LSQ;
+ }
+
+ // Check if there's any space left.
+ if (min_free_entries <= 0) {
+ DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
+ "entries.\n"
+ "ROB has %i free entries.\n"
+ "IQ has %i free entries.\n"
+ "LSQ has %i free entries.\n",
+ tid,
+ free_rob_entries,
+ free_iq_entries,
+ free_lsq_entries);
+
+ blockThisCycle = true;
+
+ block(tid);
+
+ incrFullStat(source);
+
+ return;
+ } else if (min_free_entries < insts_available) {
+ DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
+ "%i insts available, but only %i insts can be "
+ "renamed due to ROB/IQ/LSQ limits.\n",
+ tid, insts_available, min_free_entries);
+
+ insts_available = min_free_entries;
+
+ blockThisCycle = true;
+
+ incrFullStat(source);
+ }
+
+ InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
+ skidBuffer[tid] : insts[tid];
+
+ DPRINTF(Rename, "[tid:%u]: %i available instructions to "
+ "send iew.\n", tid, insts_available);
+
+ DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
+ "dispatched to IQ last cycle.\n",
+ tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
+
+ // Handle serializing the next instruction if necessary.
+ if (serializeOnNextInst[tid]) {
+ if (emptyROB[tid] && instsInProgress[tid] == 0) {
+ // ROB already empty; no need to serialize.
+ serializeOnNextInst[tid] = false;
+ } else if (!insts_to_rename.empty()) {
+ insts_to_rename.front()->setSerializeBefore();
}
+ }
- historyBuffer.erase(hb_it++);
+ int renamed_insts = 0;
- ++renameUndoneMaps;
+ while (insts_available > 0 && toIEWIndex < renameWidth) {
+ DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
+
+ assert(!insts_to_rename.empty());
+
+ inst = insts_to_rename.front();
+
+ insts_to_rename.pop_front();
+
+ if (renameStatus[tid] == Unblocking) {
+ DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
+ "skidBuffer\n",
+ tid, inst->seqNum, inst->readPC());
+ }
+
+ if (inst->isSquashed()) {
+ DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
+ "squashed, skipping.\n",
+ tid, inst->seqNum, inst->threadNumber,inst->readPC());
+
+ ++renameSquashedInsts;
+
+ // Decrement how many instructions are available.
+ --insts_available;
+
+ continue;
+ }
+
+ DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
+ "PC %#x.\n",
+ tid, inst->seqNum, inst->readPC());
+
+ // Handle serializeAfter/serializeBefore instructions.
+ // serializeAfter marks the next instruction as serializeBefore.
+ // serializeBefore makes the instruction wait in rename until the ROB
+ // is empty.
+
+ // In this model, IPR accesses are serialize before
+ // instructions, and store conditionals are serialize after
+ // instructions. This is mainly due to lack of support for
+ // out-of-order operations of either of those classes of
+ // instructions.
+ if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
+ !inst->isSerializeHandled()) {
+ DPRINTF(Rename, "Serialize before instruction encountered.\n");
+
+ if (!inst->isTempSerializeBefore()) {
+ renamedSerializing++;
+ inst->setSerializeHandled();
+ } else {
+ renamedTempSerializing++;
+ }
+
+ // Change status over to SerializeStall so that other stages know
+ // what this is blocked on.
+ renameStatus[tid] = SerializeStall;
+
+ serializeInst[tid] = inst;
+
+ blockThisCycle = true;
+
+ break;
+ } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
+ !inst->isSerializeHandled()) {
+ DPRINTF(Rename, "Serialize after instruction encountered.\n");
+
+ renamedSerializing++;
+
+ inst->setSerializeHandled();
+
+ serializeAfter(insts_to_rename, tid);
+ }
+
+ // Check here to make sure there are enough destination registers
+ // to rename to. Otherwise block.
+ if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
+ DPRINTF(Rename, "Blocking due to lack of free "
+ "physical registers to rename to.\n");
+ blockThisCycle = true;
+
+ ++renameFullRegistersEvents;
+
+ break;
+ }
+
+ renameSrcRegs(inst, inst->threadNumber);
+
+ renameDestRegs(inst, inst->threadNumber);
+
+ ++renamed_insts;
+
+ // Put instruction in rename queue.
+ toIEW->insts[toIEWIndex] = inst;
+ ++(toIEW->size);
+
+ // Increment which instruction we're on.
+ ++toIEWIndex;
+
+ // Decrement how many instructions are available.
+ --insts_available;
+ }
+
+ instsInProgress[tid] += renamed_insts;
+ renameRenamedInsts += renamed_insts;
+
+ // If we wrote to the time buffer, record this.
+ if (toIEWIndex) {
+ wroteToTimeBuffer = true;
+ }
+
+ // Check if there's any instructions left that haven't yet been renamed.
+ // If so then block.
+ if (insts_available) {
+ blockThisCycle = true;
+ }
+
+ if (blockThisCycle) {
+ block(tid);
+ toDecode->renameUnblock[tid] = false;
}
}
+template<class Impl>
+void
+DefaultRename<Impl>::skidInsert(unsigned tid)
+{
+ DynInstPtr inst = NULL;
+
+ while (!insts[tid].empty()) {
+ inst = insts[tid].front();
+
+ insts[tid].pop_front();
+
+ assert(tid == inst->threadNumber);
+
+ DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
+ "skidBuffer\n", tid, inst->seqNum, inst->readPC());
+
+ ++renameSkidInsts;
+
+ skidBuffer[tid].push_back(inst);
+ }
+
+ if (skidBuffer[tid].size() > skidBufferMax)
+ panic("Skidbuffer Exceeded Max Size");
+}
+
template <class Impl>
void
-SimpleRename<Impl>::squash()
+DefaultRename<Impl>::sortInsts()
{
- DPRINTF(Rename, "Rename: Squashing instructions.\n");
- // Set the status to Squashing.
- _status = Squashing;
+ int insts_from_decode = fromDecode->size;
+#ifdef DEBUG
+ for (int i=0; i < numThreads; i++)
+ assert(insts[i].empty());
+#endif
+ for (int i = 0; i < insts_from_decode; ++i) {
+ DynInstPtr inst = fromDecode->insts[i];
+ insts[inst->threadNumber].push_back(inst);
+ }
+}
- numInst = 0;
+template<class Impl>
+bool
+DefaultRename<Impl>::skidsEmpty()
+{
+ list<unsigned>::iterator threads = (*activeThreads).begin();
- // Clear the skid buffer in case it has any data in it.
- while (!skidBuffer.empty())
- {
- skidBuffer.pop();
+ while (threads != (*activeThreads).end()) {
+ if (!skidBuffer[*threads++].empty())
+ return false;
}
- doSquash();
+ return true;
}
template<class Impl>
void
-SimpleRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num)
+DefaultRename<Impl>::updateStatus()
{
- DPRINTF(Rename, "Rename: Removing a committed instruction from the "
- "history buffer, until sequence number %lli.\n", inst_seq_num);
- typename list<RenameHistory>::iterator hb_it = historyBuffer.end();
+ bool any_unblocking = false;
- --hb_it;
+ list<unsigned>::iterator threads = (*activeThreads).begin();
- if (hb_it->instSeqNum > inst_seq_num) {
- DPRINTF(Rename, "Rename: Old sequence number encountered. Ensure "
- "that a syscall happened recently.\n");
- return;
+ threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ if (renameStatus[tid] == Unblocking) {
+ any_unblocking = true;
+ break;
+ }
}
- while ((*hb_it).instSeqNum != inst_seq_num)
- {
- // Make sure we haven't gone off the end of the list.
- assert(hb_it != historyBuffer.end());
-
- // In theory instructions at the end of the history buffer
- // should be older than the instruction being removed, which
- // means they will have a lower sequence number. Also the
- // instruction being removed from the history really should
- // be the last instruction in the list, as it is the instruction
- // that was just committed that is being removed.
- assert(hb_it->instSeqNum < inst_seq_num);
- DPRINTF(Rename, "Rename: Freeing up older rename of reg %i, sequence"
- " number %i.\n",
- (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
-
- if (!(*hb_it).placeHolder) {
- freeList->addReg((*hb_it).prevPhysReg);
- ++renameCommittedMaps;
+ // Rename will have activity if it's unblocking.
+ if (any_unblocking) {
+ if (_status == Inactive) {
+ _status = Active;
+
+ DPRINTF(Activity, "Activating stage.\n");
+
+ cpu->activateStage(FullCPU::RenameIdx);
}
+ } else {
+ // If it's not unblocking, then rename will not have any internal
+ // activity. Switch it to inactive.
+ if (_status == Active) {
+ _status = Inactive;
+ DPRINTF(Activity, "Deactivating stage.\n");
- historyBuffer.erase(hb_it--);
+ cpu->deactivateStage(FullCPU::RenameIdx);
+ }
}
+}
- // Finally free up the previous register of the finished instruction
- // itself.
- if (!(*hb_it).placeHolder) {
- freeList->addReg(hb_it->prevPhysReg);
- ++renameCommittedMaps;
+template <class Impl>
+bool
+DefaultRename<Impl>::block(unsigned tid)
+{
+ DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
+
+ // Add the current inputs onto the skid buffer, so they can be
+ // reprocessed when this stage unblocks.
+ skidInsert(tid);
+
+ // Only signal backwards to block if the previous stages do not think
+ // rename is already blocked.
+ if (renameStatus[tid] != Blocked) {
+ if (renameStatus[tid] != Unblocking) {
+ toDecode->renameBlock[tid] = true;
+ toDecode->renameUnblock[tid] = false;
+ wroteToTimeBuffer = true;
+ }
+
+ // Rename can not go from SerializeStall to Blocked, otherwise
+ // it would not know to complete the serialize stall.
+ if (renameStatus[tid] != SerializeStall) {
+ // Set status to Blocked.
+ renameStatus[tid] = Blocked;
+ return true;
+ }
+ }
+
+ return false;
+}
+
+template <class Impl>
+bool
+DefaultRename<Impl>::unblock(unsigned tid)
+{
+ DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
+
+ // Rename is done unblocking if the skid buffer is empty.
+ if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
+
+ DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
+
+ toDecode->renameUnblock[tid] = true;
+ wroteToTimeBuffer = true;
+
+ renameStatus[tid] = Running;
+ return true;
}
- historyBuffer.erase(hb_it);
+ return false;
+}
+
+template <class Impl>
+void
+DefaultRename<Impl>::doSquash(unsigned tid)
+{
+ typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin();
+
+ InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
+
+ // After a syscall squashes everything, the history buffer may be empty
+ // but the ROB may still be squashing instructions.
+ if (historyBuffer[tid].empty()) {
+ return;
+ }
+
+ // Go through the most recent instructions, undoing the mappings
+ // they did and freeing up the registers.
+ while (!historyBuffer[tid].empty() &&
+ (*hb_it).instSeqNum > squashed_seq_num) {
+ assert(hb_it != historyBuffer[tid].end());
+
+ DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
+ "number %i.\n", tid, (*hb_it).instSeqNum);
+
+ // Tell the rename map to set the architected register to the
+ // previous physical register that it was renamed to.
+ renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
+
+ // Put the renamed physical register back on the free list.
+ freeList->addReg(hb_it->newPhysReg);
+
+ historyBuffer[tid].erase(hb_it++);
+
+ ++renameUndoneMaps;
+ }
+}
+
+template<class Impl>
+void
+DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
+{
+ DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
+ "history buffer %u (size=%i), until [sn:%lli].\n",
+ tid, tid, historyBuffer[tid].size(), inst_seq_num);
+
+ typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end();
+
+ --hb_it;
+
+ if (historyBuffer[tid].empty()) {
+ DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
+ return;
+ } else if (hb_it->instSeqNum > inst_seq_num) {
+ DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure "
+ "that a syscall happened recently.\n", tid);
+ return;
+ }
+
+ // Commit all the renames up until (and including) the committed sequence
+ // number. Some or even all of the committed instructions may not have
+ // rename histories if they did not have destination registers that were
+ // renamed.
+ while (!historyBuffer[tid].empty() &&
+ hb_it != historyBuffer[tid].end() &&
+ (*hb_it).instSeqNum <= inst_seq_num) {
+
+ DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
+ "[sn:%lli].\n",
+ tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
+
+ freeList->addReg((*hb_it).prevPhysReg);
+ ++renameCommittedMaps;
+
+ historyBuffer[tid].erase(hb_it--);
+ }
}
template <class Impl>
inline void
-SimpleRename<Impl>::renameSrcRegs(DynInstPtr &inst)
+DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
{
+ assert(renameMap[tid] != 0);
+
unsigned num_src_regs = inst->numSrcRegs();
// Get the architectual register numbers from the source and
// destination operands, and redirect them to the right register.
// Will need to mark dependencies though.
- for (int src_idx = 0; src_idx < num_src_regs; src_idx++)
- {
+ for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
RegIndex src_reg = inst->srcRegIdx(src_idx);
// Look up the source registers to get the phys. register they've
// been renamed to, and set the sources to those registers.
- PhysRegIndex renamed_reg = renameMap->lookup(src_reg);
+ PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg);
- DPRINTF(Rename, "Rename: Looking up arch reg %i, got "
- "physical reg %i.\n", (int)src_reg, (int)renamed_reg);
+ DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
+ "physical reg %i.\n", tid, (int)src_reg,
+ (int)renamed_reg);
inst->renameSrcReg(src_idx, renamed_reg);
- // Either incorporate it into the info passed back,
- // or make another function call to see if that register is
- // ready or not.
- if (renameMap->isReady(renamed_reg)) {
- DPRINTF(Rename, "Rename: Register is ready.\n");
+ // See if the register is ready or not.
+ if (scoreboard->getReg(renamed_reg) == true) {
+ DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
inst->markSrcRegReady(src_idx);
}
@@ -376,379 +939,341 @@ SimpleRename<Impl>::renameSrcRegs(DynInstPtr &inst)
template <class Impl>
inline void
-SimpleRename<Impl>::renameDestRegs(DynInstPtr &inst)
+DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
{
- typename SimpleRenameMap::RenameInfo rename_result;
+ typename RenameMap::RenameInfo rename_result;
unsigned num_dest_regs = inst->numDestRegs();
- // If it's an instruction with no destination registers, then put
- // a placeholder within the history buffer. It might be better
- // to not put it in the history buffer at all (other than branches,
- // which always need at least a place holder), and differentiate
- // between instructions with and without destination registers
- // when getting from commit the instructions that committed.
- if (num_dest_regs == 0) {
- RenameHistory hb_entry(inst->seqNum);
+ // Rename the destination registers.
+ for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
+ RegIndex dest_reg = inst->destRegIdx(dest_idx);
- historyBuffer.push_front(hb_entry);
+ // Get the physical register that the destination will be
+ // renamed to.
+ rename_result = renameMap[tid]->rename(dest_reg);
- DPRINTF(Rename, "Rename: Adding placeholder instruction to "
- "history buffer, sequence number %lli.\n",
- inst->seqNum);
+ //Mark Scoreboard entry as not ready
+ scoreboard->unsetReg(rename_result.first);
- ++renameHBPlaceHolders;
- } else {
+ DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
+ "reg %i.\n", tid, (int)dest_reg,
+ (int)rename_result.first);
- // Rename the destination registers.
- for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++)
- {
- RegIndex dest_reg = inst->destRegIdx(dest_idx);
+ // Record the rename information so that a history can be kept.
+ RenameHistory hb_entry(inst->seqNum, dest_reg,
+ rename_result.first,
+ rename_result.second);
- // Get the physical register that the destination will be
- // renamed to.
- rename_result = renameMap->rename(dest_reg);
+ historyBuffer[tid].push_front(hb_entry);
- DPRINTF(Rename, "Rename: Renaming arch reg %i to physical "
- "reg %i.\n", (int)dest_reg,
- (int)rename_result.first);
+ DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, "
+ "[sn:%lli].\n",tid,
+ (*historyBuffer[tid].begin()).instSeqNum);
- // Record the rename information so that a history can be kept.
- RenameHistory hb_entry(inst->seqNum, dest_reg,
- rename_result.first,
- rename_result.second);
+ // Tell the instruction to rename the appropriate destination
+ // register (dest_idx) to the new physical register
+ // (rename_result.first), and record the previous physical
+ // register that the same logical register was renamed to
+ // (rename_result.second).
+ inst->renameDestReg(dest_idx,
+ rename_result.first,
+ rename_result.second);
- historyBuffer.push_front(hb_entry);
+ ++renameRenamedOperands;
+ }
+}
- DPRINTF(Rename, "Rename: Adding instruction to history buffer, "
- "sequence number %lli.\n",
- (*historyBuffer.begin()).instSeqNum);
+template <class Impl>
+inline int
+DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
+{
+ int num_free = freeEntries[tid].robEntries -
+ (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
- // Tell the instruction to rename the appropriate destination
- // register (dest_idx) to the new physical register
- // (rename_result.first), and record the previous physical
- // register that the same logical register was renamed to
- // (rename_result.second).
- inst->renameDestReg(dest_idx,
- rename_result.first,
- rename_result.second);
+ //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
- ++renameRenamedOperands;
- }
- }
+ return num_free;
}
template <class Impl>
inline int
-SimpleRename<Impl>::calcFreeROBEntries()
+DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
{
- return fromCommit->commitInfo.freeROBEntries -
- renameWidth * iewToRenameDelay;
+ int num_free = freeEntries[tid].iqEntries -
+ (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
+
+ //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
+
+ return num_free;
}
template <class Impl>
inline int
-SimpleRename<Impl>::calcFreeIQEntries()
+DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
{
- return fromIEW->iewInfo.freeIQEntries - renameWidth * iewToRenameDelay;
-}
+ int num_free = freeEntries[tid].lsqEntries -
+ (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
-template<class Impl>
-void
-SimpleRename<Impl>::tick()
-{
- // Rename will need to try to rename as many instructions as it
- // has bandwidth, unless it is blocked.
-
- // Check if _status is BarrierStall. If so, then check if the number
- // of free ROB entries is equal to the number of total ROB entries.
- // Once equal then wake this stage up. Set status to unblocking maybe.
-
- if (_status != Blocked && _status != Squashing) {
- DPRINTF(Rename, "Rename: Status is not blocked, will attempt to "
- "run stage.\n");
- // Make sure that the skid buffer has something in it if the
- // status is unblocking.
- assert(_status == Unblocking ? !skidBuffer.empty() : 1);
-
- rename();
-
- // If the status was unblocking, then instructions from the skid
- // buffer were used. Remove those instructions and handle
- // the rest of unblocking.
- if (_status == Unblocking) {
- ++renameUnblockCycles;
-
- if (fromDecode->size > 0) {
- // Add the current inputs onto the skid buffer, so they can be
- // reprocessed when this stage unblocks.
- skidBuffer.push(*fromDecode);
- }
+ //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
- unblock();
- }
- } else if (_status == Blocked) {
- ++renameBlockCycles;
+ return num_free;
+}
- // If stage is blocked and still receiving valid instructions,
- // make sure to store them in the skid buffer.
- if (fromDecode->size > 0) {
+template <class Impl>
+unsigned
+DefaultRename<Impl>::validInsts()
+{
+ unsigned inst_count = 0;
- block();
+ for (int i=0; i<fromDecode->size; i++) {
+ if (!fromDecode->insts[i]->squashed)
+ inst_count++;
+ }
- // Continue to tell previous stage to stall.
- toDecode->renameInfo.stall = true;
- }
+ return inst_count;
+}
- if (!fromIEW->iewInfo.stall &&
- !fromCommit->commitInfo.stall &&
- calcFreeROBEntries() > 0 &&
- calcFreeIQEntries() > 0 &&
- renameMap->numFreeEntries() > 0) {
-
- // Need to be sure to check all blocking conditions above.
- // If they have cleared, then start unblocking.
- DPRINTF(Rename, "Rename: Stall signals cleared, going to "
- "unblock.\n");
- _status = Unblocking;
-
- // Continue to tell previous stage to block until this stage
- // is done unblocking.
- toDecode->renameInfo.stall = true;
- } else {
- // Otherwise no conditions have changed. Tell previous
- // stage to continue blocking.
- toDecode->renameInfo.stall = true;
- }
+template <class Impl>
+void
+DefaultRename<Impl>::readStallSignals(unsigned tid)
+{
+ if (fromIEW->iewBlock[tid]) {
+ stalls[tid].iew = true;
+ }
- if (fromCommit->commitInfo.squash ||
- fromCommit->commitInfo.robSquashing) {
- squash();
- return;
- }
- } else if (_status == Squashing) {
- ++renameSquashCycles;
+ if (fromIEW->iewUnblock[tid]) {
+ assert(stalls[tid].iew);
+ stalls[tid].iew = false;
+ }
- if (fromCommit->commitInfo.squash) {
- squash();
- } else if (!fromCommit->commitInfo.squash &&
- !fromCommit->commitInfo.robSquashing) {
+ if (fromCommit->commitBlock[tid]) {
+ stalls[tid].commit = true;
+ }
- DPRINTF(Rename, "Rename: Done squashing, going to running.\n");
- _status = Running;
- rename();
- } else {
- doSquash();
- }
+ if (fromCommit->commitUnblock[tid]) {
+ assert(stalls[tid].commit);
+ stalls[tid].commit = false;
}
+}
- // Ugly code, revamp all of the tick() functions eventually.
- if (fromCommit->commitInfo.doneSeqNum != 0 && _status != Squashing) {
-#if !FULL_SYSTEM
- if (!fromCommit->commitInfo.squash) {
- removeFromHistory(fromCommit->commitInfo.doneSeqNum);
- }
-#else
- removeFromHistory(fromCommit->commitInfo.doneSeqNum);
-#endif
+template <class Impl>
+bool
+DefaultRename<Impl>::checkStall(unsigned tid)
+{
+ bool ret_val = false;
+
+ if (stalls[tid].iew) {
+ DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
+ ret_val = true;
+ } else if (stalls[tid].commit) {
+ DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
+ ret_val = true;
+ } else if (calcFreeROBEntries(tid) <= 0) {
+ DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
+ ret_val = true;
+ } else if (calcFreeIQEntries(tid) <= 0) {
+ DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
+ ret_val = true;
+ } else if (calcFreeLSQEntries(tid) <= 0) {
+ DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
+ ret_val = true;
+ } else if (renameMap[tid]->numFreeEntries() <= 0) {
+ DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
+ ret_val = true;
+ } else if (renameStatus[tid] == SerializeStall &&
+ (!emptyROB[tid] || instsInProgress[tid])) {
+ DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
+ "empty.\n",
+ tid);
+ ret_val = true;
}
+ return ret_val;
}
-template<class Impl>
+template <class Impl>
void
-SimpleRename<Impl>::rename()
-{
- // Check if any of the stages ahead of rename are telling rename
- // to squash. The squash() function will also take care of fixing up
- // the rename map and the free list.
- if (fromCommit->commitInfo.squash ||
- fromCommit->commitInfo.robSquashing) {
- DPRINTF(Rename, "Rename: Receiving signal from Commit to squash.\n");
- squash();
- return;
+DefaultRename<Impl>::readFreeEntries(unsigned tid)
+{
+ bool updated = false;
+ if (fromIEW->iewInfo[tid].usedIQ) {
+ freeEntries[tid].iqEntries =
+ fromIEW->iewInfo[tid].freeIQEntries;
+ updated = true;
}
- // Check if time buffer is telling this stage to stall.
- if (fromIEW->iewInfo.stall ||
- fromCommit->commitInfo.stall) {
- DPRINTF(Rename, "Rename: Receiving signal from IEW/Commit to "
- "stall.\n");
- block();
- return;
+ if (fromIEW->iewInfo[tid].usedLSQ) {
+ freeEntries[tid].lsqEntries =
+ fromIEW->iewInfo[tid].freeLSQEntries;
+ updated = true;
}
- // Check if the current status is squashing. If so, set its status
- // to running and resume execution the next cycle.
- if (_status == Squashing) {
- DPRINTF(Rename, "Rename: Done squashing.\n");
- _status = Running;
- return;
+ if (fromCommit->commitInfo[tid].usedROB) {
+ freeEntries[tid].robEntries =
+ fromCommit->commitInfo[tid].freeROBEntries;
+ emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
+ updated = true;
}
- // Check the decode queue to see if instructions are available.
- // If there are no available instructions to rename, then do nothing.
- // Or, if the stage is currently unblocking, then go ahead and run it.
- if (fromDecode->size == 0 && _status != Unblocking) {
- DPRINTF(Rename, "Rename: Nothing to do, breaking out early.\n");
- // Should I change status to idle?
- return;
- }
-
- ////////////////////////////////////
- // Actual rename part.
- ////////////////////////////////////
-
- DynInstPtr inst;
+ DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
+ tid,
+ freeEntries[tid].iqEntries,
+ freeEntries[tid].robEntries,
+ freeEntries[tid].lsqEntries);
- // If we're unblocking, then we may be in the middle of an instruction
- // group. Subtract off numInst to get the proper number of instructions
- // left.
- int insts_available = _status == Unblocking ?
- skidBuffer.front().size - numInst :
- fromDecode->size;
+ DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
+ tid, instsInProgress[tid]);
+}
- bool block_this_cycle = false;
+template <class Impl>
+bool
+DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
+{
+ // Check if there's a squash signal, squash if there is
+ // Check stall signals, block if necessary.
+ // If status was blocked
+ // check if stall conditions have passed
+ // if so then go to unblocking
+ // If status was Squashing
+ // check if squashing is not high. Switch to running this cycle.
+ // If status was serialize stall
+ // check if ROB is empty and no insts are in flight to the ROB
+
+ readFreeEntries(tid);
+ readStallSignals(tid);
+
+ if (fromCommit->commitInfo[tid].squash) {
+ DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
+ "commit.\n", tid);
+
+ squash(tid);
+
+ return true;
+ }
- // Will have to do a different calculation for the number of free
- // entries. Number of free entries recorded on this cycle -
- // renameWidth * renameToDecodeDelay
- int free_rob_entries = calcFreeROBEntries();
- int free_iq_entries = calcFreeIQEntries();
- int min_iq_rob = min(free_rob_entries, free_iq_entries);
+ if (fromCommit->commitInfo[tid].robSquashing) {
+ DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
- unsigned to_iew_index = 0;
+ renameStatus[tid] = Squashing;
- // Check if there's any space left.
- if (min_iq_rob <= 0) {
- DPRINTF(Rename, "Rename: Blocking due to no free ROB or IQ "
- "entries.\n"
- "Rename: ROB has %d free entries.\n"
- "Rename: IQ has %d free entries.\n",
- free_rob_entries,
- free_iq_entries);
- block();
- // Tell previous stage to stall.
- toDecode->renameInfo.stall = true;
+ return true;
+ }
- if (free_rob_entries <= 0) {
- ++renameROBFullEvents;
- } else {
- ++renameIQFullEvents;
- }
+ if (checkStall(tid)) {
+ return block(tid);
+ }
- return;
- } else if (min_iq_rob < insts_available) {
- DPRINTF(Rename, "Rename: Will have to block this cycle. Only "
- "%i insts can be renamed due to IQ/ROB limits.\n",
- min_iq_rob);
+ if (renameStatus[tid] == Blocked) {
+ DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
+ tid);
- insts_available = min_iq_rob;
+ renameStatus[tid] = Unblocking;
- block_this_cycle = true;
+ unblock(tid);
- if (free_rob_entries < free_iq_entries) {
- ++renameROBFullEvents;
- } else {
- ++renameIQFullEvents;
- }
+ return true;
}
- while (insts_available > 0) {
- DPRINTF(Rename, "Rename: Sending instructions to iew.\n");
+ if (renameStatus[tid] == Squashing) {
+ // Switch status to running if rename isn't being told to block or
+ // squash this cycle.
+ DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
+ tid);
- // Get the next instruction either from the skid buffer or the
- // decode queue.
- inst = _status == Unblocking ? skidBuffer.front().insts[numInst] :
- fromDecode->insts[numInst];
+ renameStatus[tid] = Running;
- if (inst->isSquashed()) {
- DPRINTF(Rename, "Rename: instruction %i with PC %#x is "
- "squashed, skipping.\n",
- inst->seqNum, inst->readPC());
+ return false;
+ }
- // Go to the next instruction.
- ++numInst;
+ if (renameStatus[tid] == SerializeStall) {
+ // Stall ends once the ROB is free.
+ DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
+ "unblocking.\n", tid);
- ++renameSquashedInsts;
+ DynInstPtr serial_inst = serializeInst[tid];
- // Decrement how many instructions are available.
- --insts_available;
+ renameStatus[tid] = Unblocking;
- continue;
- }
+ unblock(tid);
- DPRINTF(Rename, "Rename: Processing instruction %i with PC %#x.\n",
- inst->seqNum, inst->readPC());
-
- // If it's a trap instruction, then it needs to wait here within
- // rename until the ROB is empty. Needs a way to detect that the
- // ROB is empty. Maybe an event?
- // Would be nice if it could be avoided putting this into a
- // specific stage and instead just put it into the AlphaFullCPU.
- // Might not really be feasible though...
- // (EXCB, TRAPB)
- if (inst->isSerializing()) {
- panic("Rename: Serializing instruction encountered.\n");
- DPRINTF(Rename, "Rename: Serializing instruction "
- "encountered.\n");
-
- // Change status over to BarrierStall so that other stages know
- // what this is blocked on.
- _status = BarrierStall;
+ DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
+ "PC %#x.\n",
+ tid, serial_inst->seqNum, serial_inst->readPC());
- block_this_cycle = true;
+ // Put instruction into queue here.
+ serial_inst->clearSerializeBefore();
- break;
+ if (!skidBuffer[tid].empty()) {
+ skidBuffer[tid].push_front(serial_inst);
+ } else {
+ insts[tid].push_front(serial_inst);
}
- // Check here to make sure there are enough destination registers
- // to rename to. Otherwise block.
- if (renameMap->numFreeEntries() < inst->numDestRegs())
- {
- DPRINTF(Rename, "Rename: Blocking due to lack of free "
- "physical registers to rename to.\n");
- // Need some sort of event based on a register being freed.
-
- block_this_cycle = true;
+ DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
+ " Adding to front of list.", tid);
- ++renameFullRegistersEvents;
+ serializeInst[tid] = NULL;
- break;
- }
+ return true;
+ }
- renameSrcRegs(inst);
+ // If we've reached this point, we have not gotten any signals that
+ // cause rename to change its status. Rename remains the same as before.
+ return false;
+}
- renameDestRegs(inst);
+template<class Impl>
+void
+DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
+ unsigned tid)
+{
+ if (inst_list.empty()) {
+ // Mark a bit to say that I must serialize on the next instruction.
+ serializeOnNextInst[tid] = true;
+ return;
+ }
- // Put instruction in rename queue.
- toIEW->insts[to_iew_index] = inst;
- ++(toIEW->size);
+ // Set the next instruction as serializing.
+ inst_list.front()->setSerializeBefore();
+}
- // Decrease the number of free ROB and IQ entries.
- --free_rob_entries;
- --free_iq_entries;
+template <class Impl>
+inline void
+DefaultRename<Impl>::incrFullStat(const FullSource &source)
+{
+ switch (source) {
+ case ROB:
+ ++renameROBFullEvents;
+ break;
+ case IQ:
+ ++renameIQFullEvents;
+ break;
+ case LSQ:
+ ++renameLSQFullEvents;
+ break;
+ default:
+ panic("Rename full stall stat should be incremented for a reason!");
+ break;
+ }
+}
- // Increment which instruction we're on.
- ++to_iew_index;
- ++numInst;
+template <class Impl>
+void
+DefaultRename<Impl>::dumpHistory()
+{
+ typename list<RenameHistory>::iterator buf_it;
- ++renameRenamedInsts;
+ for (int i = 0; i < numThreads; i++) {
- // Decrement how many instructions are available.
- --insts_available;
- }
+ buf_it = historyBuffer[i].begin();
- // Check if there's any instructions left that haven't yet been renamed.
- // If so then block.
- if (block_this_cycle) {
- block();
+ while (buf_it != historyBuffer[i].end()) {
+ cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
+ "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
+ (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
- toDecode->renameInfo.stall = true;
- } else {
- // If we had a successful rename and didn't have to exit early, then
- // reset numInst so it will refer to the correct instruction on next
- // run.
- numInst = 0;
+ buf_it++;
+ }
}
}
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index 10963f7de..fc59058a1 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -32,118 +32,105 @@
using namespace std;
-// Todo: Consider making functions inline. Avoid having things that are
-// using the zero register or misc registers from adding on the registers
-// to the free list. Possibly remove the direct communication between
-// this and the freelist. Considering making inline bool functions that
-// determine if the register is a logical int, logical fp, physical int,
-// physical fp, etc.
-
-SimpleRenameMap::SimpleRenameMap(unsigned _numLogicalIntRegs,
- unsigned _numPhysicalIntRegs,
- unsigned _numLogicalFloatRegs,
- unsigned _numPhysicalFloatRegs,
- unsigned _numMiscRegs,
- RegIndex _intZeroReg,
- RegIndex _floatZeroReg)
- : numLogicalIntRegs(_numLogicalIntRegs),
- numPhysicalIntRegs(_numPhysicalIntRegs),
- numLogicalFloatRegs(_numLogicalFloatRegs),
- numPhysicalFloatRegs(_numPhysicalFloatRegs),
- numMiscRegs(_numMiscRegs),
- intZeroReg(_intZeroReg),
- floatZeroReg(_floatZeroReg)
+// @todo: Consider making inline bool functions that determine if the
+// register is a logical int, logical fp, physical int, physical fp,
+// etc.
+
+SimpleRenameMap::~SimpleRenameMap()
+{
+}
+
+void
+SimpleRenameMap::init(unsigned _numLogicalIntRegs,
+ unsigned _numPhysicalIntRegs,
+ PhysRegIndex &ireg_idx,
+
+ unsigned _numLogicalFloatRegs,
+ unsigned _numPhysicalFloatRegs,
+ PhysRegIndex &freg_idx,
+
+ unsigned _numMiscRegs,
+
+ RegIndex _intZeroReg,
+ RegIndex _floatZeroReg,
+
+ int map_id,
+ bool bindRegs)
{
- DPRINTF(Rename, "Rename: Creating rename map. Phys: %i / %i, Float: "
- "%i / %i.\n", numLogicalIntRegs, numPhysicalIntRegs,
+ id = map_id;
+
+ numLogicalIntRegs = _numLogicalIntRegs;
+
+ numLogicalFloatRegs = _numLogicalFloatRegs;
+
+ numPhysicalIntRegs = _numPhysicalIntRegs;
+
+ numPhysicalFloatRegs = _numPhysicalFloatRegs;
+
+ numMiscRegs = _numMiscRegs;
+
+ intZeroReg = _intZeroReg;
+ floatZeroReg = _floatZeroReg;
+
+ DPRINTF(Rename, "Creating rename map %i. Phys: %i / %i, Float: "
+ "%i / %i.\n", id, numLogicalIntRegs, numPhysicalIntRegs,
numLogicalFloatRegs, numPhysicalFloatRegs);
numLogicalRegs = numLogicalIntRegs + numLogicalFloatRegs;
numPhysicalRegs = numPhysicalIntRegs + numPhysicalFloatRegs;
- //Create the rename maps, and their scoreboards.
- intRenameMap = new RenameEntry[numLogicalIntRegs];
- floatRenameMap = new RenameEntry[numLogicalRegs];
-
- // Should combine this into one scoreboard.
- intScoreboard.resize(numPhysicalIntRegs);
- floatScoreboard.resize(numPhysicalRegs);
- miscScoreboard.resize(numPhysicalRegs + numMiscRegs);
-
- // Initialize the entries in the integer rename map to point to the
- // physical registers of the same index, and consider each register
- // ready until the first rename occurs.
- for (RegIndex index = 0; index < numLogicalIntRegs; ++index)
- {
- intRenameMap[index].physical_reg = index;
- intScoreboard[index] = 1;
- }
+ //Create the rename maps
+ intRenameMap.resize(numLogicalIntRegs);
+ floatRenameMap.resize(numLogicalRegs);
- // Initialize the rest of the physical registers (the ones that don't
- // directly map to a logical register) as unready.
- for (PhysRegIndex index = numLogicalIntRegs;
- index < numPhysicalIntRegs;
- ++index)
- {
- intScoreboard[index] = 0;
- }
+ if (bindRegs) {
+ DPRINTF(Rename, "Binding registers into rename map %i",id);
- int float_reg_idx = numPhysicalIntRegs;
-
- // Initialize the entries in the floating point rename map to point to
- // the physical registers of the same index, and consider each register
- // ready until the first rename occurs.
- // Although the index refers purely to architected registers, because
- // the floating reg indices come after the integer reg indices, they
- // may exceed the size of a normal RegIndex (short).
- for (PhysRegIndex index = numLogicalIntRegs;
- index < numLogicalRegs; ++index)
- {
- floatRenameMap[index].physical_reg = float_reg_idx++;
- }
+ // Initialize the entries in the integer rename map to point to the
+ // physical registers of the same index
+ for (RegIndex index = 0; index < numLogicalIntRegs; ++index)
+ {
+ intRenameMap[index].physical_reg = ireg_idx++;
+ }
- for (PhysRegIndex index = numPhysicalIntRegs;
- index < numPhysicalIntRegs + numLogicalFloatRegs; ++index)
- {
- floatScoreboard[index] = 1;
- }
+ // Initialize the entries in the floating point rename map to point to
+ // the physical registers of the same index
+ // Although the index refers purely to architected registers, because
+ // the floating reg indices come after the integer reg indices, they
+ // may exceed the size of a normal RegIndex (short).
+ for (PhysRegIndex index = numLogicalIntRegs;
+ index < numLogicalRegs; ++index)
+ {
+ floatRenameMap[index].physical_reg = freg_idx++;
+ }
+ } else {
+ DPRINTF(Rename, "Binding registers into rename map %i",id);
- // Initialize the rest of the physical registers (the ones that don't
- // directly map to a logical register) as unready.
- for (PhysRegIndex index = numPhysicalIntRegs + numLogicalFloatRegs;
- index < numPhysicalRegs;
- ++index)
- {
- floatScoreboard[index] = 0;
- }
+ PhysRegIndex temp_ireg = ireg_idx;
- // Initialize the entries in the misc register scoreboard to be ready.
- for (PhysRegIndex index = numPhysicalRegs;
- index < numPhysicalRegs + numMiscRegs; ++index)
- {
- miscScoreboard[index] = 1;
- }
-}
+ for (RegIndex index = 0; index < numLogicalIntRegs; ++index)
+ {
+ intRenameMap[index].physical_reg = temp_ireg++;
+ }
-SimpleRenameMap::~SimpleRenameMap()
-{
- // Delete the rename maps as they were allocated with new.
- delete [] intRenameMap;
- delete [] floatRenameMap;
+ PhysRegIndex temp_freg = freg_idx;
+
+ for (PhysRegIndex index = numLogicalIntRegs;
+ index < numLogicalRegs; ++index)
+ {
+ floatRenameMap[index].physical_reg = temp_freg++;
+ }
+ }
}
void
SimpleRenameMap::setFreeList(SimpleFreeList *fl_ptr)
{
- //Setup the interface to the freelist.
freeList = fl_ptr;
}
-// Don't allow this stage to fault; force that check to the rename stage.
-// Simply ask to rename a logical register and get back a new physical
-// register index.
SimpleRenameMap::RenameInfo
SimpleRenameMap::rename(RegIndex arch_reg)
{
@@ -156,45 +143,33 @@ SimpleRenameMap::rename(RegIndex arch_reg)
// requested architected register.
prev_reg = intRenameMap[arch_reg].physical_reg;
- // If it's not referencing the zero register, then mark the register
- // as not ready.
+ // If it's not referencing the zero register, then rename the
+ // register.
if (arch_reg != intZeroReg) {
- // Get a free physical register to rename to.
renamed_reg = freeList->getIntReg();
- // Update the integer rename map.
intRenameMap[arch_reg].physical_reg = renamed_reg;
assert(renamed_reg >= 0 && renamed_reg < numPhysicalIntRegs);
- // Mark register as not ready.
- intScoreboard[renamed_reg] = false;
} else {
// Otherwise return the zero register so nothing bad happens.
renamed_reg = intZeroReg;
}
} else if (arch_reg < numLogicalRegs) {
- // Subtract off the base offset for floating point registers.
-// arch_reg = arch_reg - numLogicalIntRegs;
-
// Record the current physical register that is renamed to the
// requested architected register.
prev_reg = floatRenameMap[arch_reg].physical_reg;
- // If it's not referencing the zero register, then mark the register
- // as not ready.
+ // If it's not referencing the zero register, then rename the
+ // register.
if (arch_reg != floatZeroReg) {
- // Get a free floating point register to rename to.
renamed_reg = freeList->getFloatReg();
- // Update the floating point rename map.
floatRenameMap[arch_reg].physical_reg = renamed_reg;
assert(renamed_reg < numPhysicalRegs &&
renamed_reg >= numPhysicalIntRegs);
-
- // Mark register as not ready.
- floatScoreboard[renamed_reg] = false;
} else {
// Otherwise return the zero register so nothing bad happens.
renamed_reg = floatZeroReg;
@@ -203,10 +178,10 @@ SimpleRenameMap::rename(RegIndex arch_reg)
// Subtract off the base offset for miscellaneous registers.
arch_reg = arch_reg - numLogicalRegs;
- // No renaming happens to the misc. registers. They are simply the
- // registers that come after all the physical registers; thus
- // take the base architected register and add the physical registers
- // to it.
+ // No renaming happens to the misc. registers. They are
+ // simply the registers that come after all the physical
+ // registers; thus take the base architected register and add
+ // the physical registers to it.
renamed_reg = arch_reg + numPhysicalRegs;
// Set the previous register to the same register; mainly it must be
@@ -215,24 +190,17 @@ SimpleRenameMap::rename(RegIndex arch_reg)
prev_reg = renamed_reg;
assert(renamed_reg < numPhysicalRegs + numMiscRegs);
-
- miscScoreboard[renamed_reg] = false;
}
return RenameInfo(renamed_reg, prev_reg);
}
-//Perhaps give this a pair as a return value, of the physical register
-//and whether or not it's ready.
PhysRegIndex
SimpleRenameMap::lookup(RegIndex arch_reg)
{
if (arch_reg < numLogicalIntRegs) {
return intRenameMap[arch_reg].physical_reg;
} else if (arch_reg < numLogicalRegs) {
- // Subtract off the base FP offset.
-// arch_reg = arch_reg - numLogicalIntRegs;
-
return floatRenameMap[arch_reg].physical_reg;
} else {
// Subtract off the misc registers offset.
@@ -244,38 +212,18 @@ SimpleRenameMap::lookup(RegIndex arch_reg)
}
}
-bool
-SimpleRenameMap::isReady(PhysRegIndex phys_reg)
-{
- if (phys_reg < numPhysicalIntRegs) {
- return intScoreboard[phys_reg];
- } else if (phys_reg < numPhysicalRegs) {
-
- // Subtract off the base FP offset.
-// phys_reg = phys_reg - numPhysicalIntRegs;
-
- return floatScoreboard[phys_reg];
- } else {
- // Subtract off the misc registers offset.
-// phys_reg = phys_reg - numPhysicalRegs;
-
- return miscScoreboard[phys_reg];
- }
-}
-
-// In this implementation the miscellaneous registers do not actually rename,
-// so this function does not allow you to try to change their mappings.
void
SimpleRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg)
{
+ // In this implementation the miscellaneous registers do not
+ // actually rename, so this function does not allow you to try to
+ // change their mappings.
if (arch_reg < numLogicalIntRegs) {
DPRINTF(Rename, "Rename Map: Integer register %i being set to %i.\n",
(int)arch_reg, renamed_reg);
intRenameMap[arch_reg].physical_reg = renamed_reg;
- } else {
- assert(arch_reg < (numLogicalIntRegs + numLogicalFloatRegs));
-
+ } else if (arch_reg < numLogicalIntRegs + numLogicalFloatRegs) {
DPRINTF(Rename, "Rename Map: Float register %i being set to %i.\n",
(int)arch_reg - numLogicalIntRegs, renamed_reg);
@@ -283,55 +231,6 @@ SimpleRenameMap::setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg)
}
}
-void
-SimpleRenameMap::squash(vector<RegIndex> freed_regs,
- vector<UnmapInfo> unmaps)
-{
- panic("Not sure this function should be called.");
-
- // Not sure the rename map should be able to access the free list
- // like this.
- while (!freed_regs.empty()) {
- RegIndex free_register = freed_regs.back();
-
- if (free_register < numPhysicalIntRegs) {
- freeList->addIntReg(free_register);
- } else {
- // Subtract off the base FP dependence tag.
- free_register = free_register - numPhysicalIntRegs;
- freeList->addFloatReg(free_register);
- }
-
- freed_regs.pop_back();
- }
-
- // Take unmap info and roll back the rename map.
-}
-
-void
-SimpleRenameMap::markAsReady(PhysRegIndex ready_reg)
-{
- DPRINTF(Rename, "Rename map: Marking register %i as ready.\n",
- (int)ready_reg);
-
- if (ready_reg < numPhysicalIntRegs) {
- assert(ready_reg >= 0);
-
- intScoreboard[ready_reg] = 1;
- } else if (ready_reg < numPhysicalRegs) {
-
- // Subtract off the base FP offset.
-// ready_reg = ready_reg - numPhysicalIntRegs;
-
- floatScoreboard[ready_reg] = 1;
- } else {
- //Subtract off the misc registers offset.
-// ready_reg = ready_reg - numPhysicalRegs;
-
- miscScoreboard[ready_reg] = 1;
- }
-}
-
int
SimpleRenameMap::numFreeEntries()
{
diff --git a/src/cpu/o3/rename_map.hh b/src/cpu/o3/rename_map.hh
index 57be4a64a..d7e49ae83 100644
--- a/src/cpu/o3/rename_map.hh
+++ b/src/cpu/o3/rename_map.hh
@@ -30,8 +30,8 @@
// Have it so that there's a more meaningful name given to the variable
// that marks the beginning of the FP registers.
-#ifndef __CPU_O3_CPU_RENAME_MAP_HH__
-#define __CPU_O3_CPU_RENAME_MAP_HH__
+#ifndef __CPU_O3_RENAME_MAP_HH__
+#define __CPU_O3_RENAME_MAP_HH__
#include <iostream>
#include <utility>
@@ -63,17 +63,27 @@ class SimpleRenameMap
public:
//Constructor
- SimpleRenameMap(unsigned _numLogicalIntRegs,
- unsigned _numPhysicalIntRegs,
- unsigned _numLogicalFloatRegs,
- unsigned _numPhysicalFloatRegs,
- unsigned _numMiscRegs,
- RegIndex _intZeroReg,
- RegIndex _floatZeroReg);
+ SimpleRenameMap() {};
/** Destructor. */
~SimpleRenameMap();
+ void init(unsigned _numLogicalIntRegs,
+ unsigned _numPhysicalIntRegs,
+ PhysRegIndex &_int_reg_start,
+
+ unsigned _numLogicalFloatRegs,
+ unsigned _numPhysicalFloatRegs,
+ PhysRegIndex &_float_reg_start,
+
+ unsigned _numMiscRegs,
+
+ RegIndex _intZeroReg,
+ RegIndex _floatZeroReg,
+
+ int id,
+ bool bindRegs);
+
void setFreeList(SimpleFreeList *fl_ptr);
//Tell rename map to get a free physical register for a given
@@ -84,23 +94,19 @@ class SimpleRenameMap
PhysRegIndex lookup(RegIndex phys_reg);
- bool isReady(PhysRegIndex arch_reg);
-
/**
* Marks the given register as ready, meaning that its value has been
* calculated and written to the register file.
* @param ready_reg The index of the physical register that is now ready.
*/
- void markAsReady(PhysRegIndex ready_reg);
-
void setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg);
- void squash(std::vector<RegIndex> freed_regs,
- std::vector<UnmapInfo> unmaps);
-
int numFreeEntries();
private:
+ /** Rename Map ID */
+ int id;
+
/** Number of logical integer registers. */
int numLogicalIntRegs;
@@ -143,31 +149,17 @@ class SimpleRenameMap
{ }
};
+ //Change this to private
+ private:
/** Integer rename map. */
- RenameEntry *intRenameMap;
+ std::vector<RenameEntry> intRenameMap;
/** Floating point rename map. */
- RenameEntry *floatRenameMap;
+ std::vector<RenameEntry> floatRenameMap;
+ private:
/** Free list interface. */
SimpleFreeList *freeList;
-
- // Might want to make all these scoreboards into one large scoreboard.
-
- /** Scoreboard of physical integer registers, saying whether or not they
- * are ready.
- */
- std::vector<bool> intScoreboard;
-
- /** Scoreboard of physical floating registers, saying whether or not they
- * are ready.
- */
- std::vector<bool> floatScoreboard;
-
- /** Scoreboard of miscellaneous registers, saying whether or not they
- * are ready.
- */
- std::vector<bool> miscScoreboard;
};
-#endif //__CPU_O3_CPU_RENAME_MAP_HH__
+#endif //__CPU_O3_RENAME_MAP_HH__
diff --git a/src/cpu/o3/rob.hh b/src/cpu/o3/rob.hh
index 1185564ad..e05eebe5a 100644
--- a/src/cpu/o3/rob.hh
+++ b/src/cpu/o3/rob.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,23 +26,15 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-// Todo: Probably add in support for scheduling events (more than one as
-// well) on the case of the ROB being empty or full. Considering tracking
-// free entries instead of insts in ROB. Differentiate between squashing
-// all instructions after the instruction, and all instructions after *and*
-// including that instruction.
-
-#ifndef __CPU_O3_CPU_ROB_HH__
-#define __CPU_O3_CPU_ROB_HH__
+#ifndef __CPU_O3_ROB_HH__
+#define __CPU_O3_ROB_HH__
+#include <string>
#include <utility>
#include <vector>
/**
- * ROB class. Uses the instruction list that exists within the CPU to
- * represent the ROB. This class doesn't contain that list, but instead
- * a pointer to the CPU to get access to the list. The ROB, in this first
- * implementation, is largely what drives squashing.
+ * ROB class. The ROB is largely what drives squashing.
*/
template <class Impl>
class ROB
@@ -54,16 +46,43 @@ class ROB
typedef typename Impl::FullCPU FullCPU;
typedef typename Impl::DynInstPtr DynInstPtr;
- typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo_t;
- typedef typename list<DynInstPtr>::iterator InstIt_t;
+ typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo;
+ typedef typename std::list<DynInstPtr>::iterator InstIt;
+
+ /** Possible ROB statuses. */
+ enum Status {
+ Running,
+ Idle,
+ ROBSquashing
+ };
+
+ /** SMT ROB Sharing Policy */
+ enum ROBPolicy{
+ Dynamic,
+ Partitioned,
+ Threshold
+ };
+
+ private:
+ /** Per-thread ROB status. */
+ Status robStatus[Impl::MaxThreads];
+
+ /** ROB resource sharing policy for SMT mode. */
+ ROBPolicy robPolicy;
public:
/** ROB constructor.
- * @param _numEntries Number of entries in ROB.
- * @param _squashWidth Number of instructions that can be squashed in a
- * single cycle.
+ * @param _numEntries Number of entries in ROB.
+ * @param _squashWidth Number of instructions that can be squashed in a
+ * single cycle.
+ * @param _smtROBPolicy ROB Partitioning Scheme for SMT.
+ * @param _smtROBThreshold Max Resources(by %) a thread can have in the ROB.
+ * @param _numThreads The number of active threads.
*/
- ROB(unsigned _numEntries, unsigned _squashWidth);
+ ROB(unsigned _numEntries, unsigned _squashWidth, std::string smtROBPolicy,
+ unsigned _smtROBThreshold, unsigned _numThreads);
+
+ std::string name() const;
/** Function to set the CPU pointer, necessary due to which object the ROB
* is created within.
@@ -71,12 +90,19 @@ class ROB
*/
void setCPU(FullCPU *cpu_ptr);
- /** Function to insert an instruction into the ROB. The parameter inst is
- * not truly required, but is useful for checking correctness. Note
- * that whatever calls this function must ensure that there is enough
- * space within the ROB for the new instruction.
+ /** Sets pointer to the list of active threads.
+ * @param at_ptr Pointer to the list of active threads.
+ */
+ void setActiveThreads(std::list<unsigned>* at_ptr);
+
+ void switchOut();
+
+ void takeOverFrom();
+
+ /** Function to insert an instruction into the ROB. Note that whatever
+ * calls this function must ensure that there is enough space within the
+ * ROB for the new instruction.
* @param inst The instruction being inserted into the ROB.
- * @todo Remove the parameter once correctness is ensured.
*/
void insertInst(DynInstPtr &inst);
@@ -84,40 +110,134 @@ class ROB
* no guarantee as to the return value if the ROB is empty.
* @retval Pointer to the DynInst that is at the head of the ROB.
*/
- DynInstPtr readHeadInst() { return cpu->instList.front(); }
+// DynInstPtr readHeadInst();
+
+ /** Returns a pointer to the head instruction of a specific thread within
+ * the ROB.
+ * @return Pointer to the DynInst that is at the head of the ROB.
+ */
+ DynInstPtr readHeadInst(unsigned tid);
+
+ /** Returns pointer to the tail instruction within the ROB. There is
+ * no guarantee as to the return value if the ROB is empty.
+ * @retval Pointer to the DynInst that is at the tail of the ROB.
+ */
+// DynInstPtr readTailInst();
+
+ /** Returns a pointer to the tail instruction of a specific thread within
+ * the ROB.
+ * @return Pointer to the DynInst that is at the tail of the ROB.
+ */
+ DynInstPtr readTailInst(unsigned tid);
+
+ /** Retires the head instruction, removing it from the ROB. */
+// void retireHead();
+
+ /** Retires the head instruction of a specific thread, removing it from the
+ * ROB.
+ */
+ void retireHead(unsigned tid);
- DynInstPtr readTailInst() { return (*tail); }
+ /** Is the oldest instruction across all threads ready. */
+// bool isHeadReady();
- void retireHead();
+ /** Is the oldest instruction across a particular thread ready. */
+ bool isHeadReady(unsigned tid);
- bool isHeadReady();
+ /** Is there any commitable head instruction across all threads ready. */
+ bool canCommit();
+ /** Re-adjust ROB partitioning. */
+ void resetEntries();
+
+ /** Number of entries needed For 'num_threads' amount of threads. */
+ int entryAmount(int num_threads);
+
+ /** Returns the number of total free entries in the ROB. */
unsigned numFreeEntries();
+ /** Returns the number of free entries in a specific ROB paritition. */
+ unsigned numFreeEntries(unsigned tid);
+
+ /** Returns the maximum number of entries for a specific thread. */
+ unsigned getMaxEntries(unsigned tid)
+ { return maxEntries[tid]; }
+
+ /** Returns the number of entries being used by a specific thread. */
+ unsigned getThreadEntries(unsigned tid)
+ { return threadEntries[tid]; }
+
+ /** Returns if the ROB is full. */
bool isFull()
{ return numInstsInROB == numEntries; }
+ /** Returns if a specific thread's partition is full. */
+ bool isFull(unsigned tid)
+ { return threadEntries[tid] == numEntries; }
+
+ /** Returns if the ROB is empty. */
bool isEmpty()
{ return numInstsInROB == 0; }
- void doSquash();
+ /** Returns if a specific thread's partition is empty. */
+ bool isEmpty(unsigned tid)
+ { return threadEntries[tid] == 0; }
- void squash(InstSeqNum squash_num);
+ /** Executes the squash, marking squashed instructions. */
+ void doSquash(unsigned tid);
- uint64_t readHeadPC();
+ /** Squashes all instructions younger than the given sequence number for
+ * the specific thread.
+ */
+ void squash(InstSeqNum squash_num, unsigned tid);
- uint64_t readHeadNextPC();
+ /** Updates the head instruction with the new oldest instruction. */
+ void updateHead();
- InstSeqNum readHeadSeqNum();
+ /** Updates the tail instruction with the new youngest instruction. */
+ void updateTail();
- uint64_t readTailPC();
+ /** Reads the PC of the oldest head instruction. */
+// uint64_t readHeadPC();
- InstSeqNum readTailSeqNum();
+ /** Reads the PC of the head instruction of a specific thread. */
+// uint64_t readHeadPC(unsigned tid);
+
+ /** Reads the next PC of the oldest head instruction. */
+// uint64_t readHeadNextPC();
+
+ /** Reads the next PC of the head instruction of a specific thread. */
+// uint64_t readHeadNextPC(unsigned tid);
+
+ /** Reads the sequence number of the oldest head instruction. */
+// InstSeqNum readHeadSeqNum();
+
+ /** Reads the sequence number of the head instruction of a specific thread.
+ */
+// InstSeqNum readHeadSeqNum(unsigned tid);
+
+ /** Reads the PC of the youngest tail instruction. */
+// uint64_t readTailPC();
+
+ /** Reads the PC of the tail instruction of a specific thread. */
+// uint64_t readTailPC(unsigned tid);
+
+ /** Reads the sequence number of the youngest tail instruction. */
+// InstSeqNum readTailSeqNum();
+
+ /** Reads the sequence number of tail instruction of a specific thread. */
+// InstSeqNum readTailSeqNum(unsigned tid);
/** Checks if the ROB is still in the process of squashing instructions.
* @retval Whether or not the ROB is done squashing.
*/
- bool isDoneSquashing() const { return doneSquashing; }
+ bool isDoneSquashing(unsigned tid) const
+ { return doneSquashing[tid]; }
+
+ /** Checks if the ROB is still in the process of squashing instructions for
+ * any thread.
+ */
+ bool isDoneSquashing();
/** This is more of a debugging function than anything. Use
* numInstsInROB to get the instructions in the ROB unless you are
@@ -125,23 +245,46 @@ class ROB
*/
int countInsts();
- private:
+ /** This is more of a debugging function than anything. Use
+ * threadEntries to get the instructions in the ROB unless you are
+ * double checking that variable.
+ */
+ int countInsts(unsigned tid);
+ private:
/** Pointer to the CPU. */
FullCPU *cpu;
+ /** Active Threads in CPU */
+ std::list<unsigned>* activeThreads;
+
/** Number of instructions in the ROB. */
unsigned numEntries;
+ /** Entries Per Thread */
+ unsigned threadEntries[Impl::MaxThreads];
+
+ /** Max Insts a Thread Can Have in the ROB */
+ unsigned maxEntries[Impl::MaxThreads];
+
+ /** ROB List of Instructions */
+ std::list<DynInstPtr> instList[Impl::MaxThreads];
+
/** Number of instructions that can be squashed in a single cycle. */
unsigned squashWidth;
+ public:
/** Iterator pointing to the instruction which is the last instruction
* in the ROB. This may at times be invalid (ie when the ROB is empty),
* however it should never be incorrect.
*/
- InstIt_t tail;
+ InstIt tail;
+ /** Iterator pointing to the instruction which is the first instruction in
+ * in the ROB*/
+ InstIt head;
+
+ private:
/** Iterator used for walking through the list of instructions when
* squashing. Used so that there is persistent state between cycles;
* when squashing, the instructions are marked as squashed but not
@@ -149,16 +292,23 @@ class ROB
* and after a squash.
* This will always be set to cpu->instList.end() if it is invalid.
*/
- InstIt_t squashIt;
+ InstIt squashIt[Impl::MaxThreads];
+ public:
/** Number of instructions in the ROB. */
int numInstsInROB;
+ DynInstPtr dummyInst;
+
+ private:
/** The sequence number of the squashed instruction. */
InstSeqNum squashedSeqNum;
/** Is the ROB done squashing. */
- bool doneSquashing;
+ bool doneSquashing[Impl::MaxThreads];
+
+ /** Number of active threads. */
+ unsigned numThreads;
};
-#endif //__CPU_O3_CPU_ROB_HH__
+#endif //__CPU_O3_ROB_HH__
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index e7a5671d9..25e0c80fd 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,20 +26,74 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_ROB_IMPL_HH__
-#define __CPU_O3_CPU_ROB_IMPL_HH__
-
#include "config/full_system.hh"
#include "cpu/o3/rob.hh"
+using namespace std;
+
template <class Impl>
-ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth)
+ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth,
+ string _smtROBPolicy, unsigned _smtROBThreshold,
+ unsigned _numThreads)
: numEntries(_numEntries),
squashWidth(_squashWidth),
numInstsInROB(0),
- squashedSeqNum(0)
+ squashedSeqNum(0),
+ numThreads(_numThreads)
+{
+ for (int tid=0; tid < numThreads; tid++) {
+ doneSquashing[tid] = true;
+ threadEntries[tid] = 0;
+ }
+
+ string policy = _smtROBPolicy;
+
+ //Convert string to lowercase
+ std::transform(policy.begin(), policy.end(), policy.begin(),
+ (int(*)(int)) tolower);
+
+ //Figure out rob policy
+ if (policy == "dynamic") {
+ robPolicy = Dynamic;
+
+ //Set Max Entries to Total ROB Capacity
+ for (int i = 0; i < numThreads; i++) {
+ maxEntries[i]=numEntries;
+ }
+
+ } else if (policy == "partitioned") {
+ robPolicy = Partitioned;
+ DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n");
+
+ //@todo:make work if part_amt doesnt divide evenly.
+ int part_amt = numEntries / numThreads;
+
+ //Divide ROB up evenly
+ for (int i = 0; i < numThreads; i++) {
+ maxEntries[i]=part_amt;
+ }
+
+ } else if (policy == "threshold") {
+ robPolicy = Threshold;
+ DPRINTF(Fetch, "ROB sharing policy set to Threshold\n");
+
+ int threshold = _smtROBThreshold;;
+
+ //Divide up by threshold amount
+ for (int i = 0; i < numThreads; i++) {
+ maxEntries[i]=threshold;
+ }
+ } else {
+ assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic,"
+ "Partitioned, Threshold}");
+ }
+}
+
+template <class Impl>
+std::string
+ROB<Impl>::name() const
{
- doneSquashing = true;
+ return cpu->name() + ".rob";
}
template <class Impl>
@@ -48,124 +102,227 @@ ROB<Impl>::setCPU(FullCPU *cpu_ptr)
{
cpu = cpu_ptr;
- // Set the tail to the beginning of the CPU instruction list so that
- // upon the first instruction being inserted into the ROB, the tail
- // iterator can simply be incremented.
- tail = cpu->instList.begin();
+ // Set the per-thread iterators to the end of the instruction list.
+ for (int i=0; i < numThreads;i++) {
+ squashIt[i] = instList[i].end();
+ }
- // Set the squash iterator to the end of the instruction list.
- squashIt = cpu->instList.end();
+ // Initialize the "universal" ROB head & tail point to invalid
+ // pointers
+ head = instList[0].end();
+ tail = instList[0].end();
}
template <class Impl>
-int
-ROB<Impl>::countInsts()
+void
+ROB<Impl>::setActiveThreads(list<unsigned> *at_ptr)
{
- // Start at 1; if the tail matches cpu->instList.begin(), then there is
- // one inst in the ROB.
- int return_val = 1;
+ DPRINTF(ROB, "Setting active threads list pointer.\n");
+ activeThreads = at_ptr;
+}
- // There are quite a few special cases. Do not use this function other
- // than for debugging purposes.
- if (cpu->instList.begin() == cpu->instList.end()) {
- // In this case there are no instructions in the list. The ROB
- // must be empty.
- return 0;
- } else if (tail == cpu->instList.end()) {
- // In this case, the tail is not yet pointing to anything valid.
- // The ROB must be empty.
- return 0;
+template <class Impl>
+void
+ROB<Impl>::switchOut()
+{
+ for (int tid = 0; tid < numThreads; tid++) {
+ instList[tid].clear();
}
+}
- // Iterate through the ROB from the head to the tail, counting the
- // entries.
- for (InstIt_t i = cpu->instList.begin(); i != tail; ++i)
- {
- assert(i != cpu->instList.end());
- ++return_val;
+template <class Impl>
+void
+ROB<Impl>::takeOverFrom()
+{
+ for (int tid=0; tid < numThreads; tid++) {
+ doneSquashing[tid] = true;
+ threadEntries[tid] = 0;
+ squashIt[tid] = instList[tid].end();
+ }
+ numInstsInROB = 0;
+
+ // Initialize the "universal" ROB head & tail point to invalid
+ // pointers
+ head = instList[0].end();
+ tail = instList[0].end();
+}
+
+template <class Impl>
+void
+ROB<Impl>::resetEntries()
+{
+ if (robPolicy != Dynamic || numThreads > 1) {
+ int active_threads = (*activeThreads).size();
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+ list<unsigned>::iterator list_end = (*activeThreads).end();
+
+ while (threads != list_end) {
+ if (robPolicy == Partitioned) {
+ maxEntries[*threads++] = numEntries / active_threads;
+ } else if (robPolicy == Threshold && active_threads == 1) {
+ maxEntries[*threads++] = numEntries;
+ }
+ }
}
+}
+
+template <class Impl>
+int
+ROB<Impl>::entryAmount(int num_threads)
+{
+ if (robPolicy == Partitioned) {
+ return numEntries / num_threads;
+ } else {
+ return 0;
+ }
+}
+
+template <class Impl>
+int
+ROB<Impl>::countInsts()
+{
+ int total=0;
- return return_val;
+ for (int i=0;i < numThreads;i++)
+ total += countInsts(i);
- // Because the head won't be tracked properly until the ROB gets the
- // first instruction, and any time that the ROB is empty and has not
- // yet gotten the instruction, this function doesn't work.
-// return numInstsInROB;
+ return total;
+}
+
+template <class Impl>
+int
+ROB<Impl>::countInsts(unsigned tid)
+{
+ return instList[tid].size();
}
template <class Impl>
void
ROB<Impl>::insertInst(DynInstPtr &inst)
{
- // Make sure we have the right number of instructions.
- assert(numInstsInROB == countInsts());
- // Make sure the instruction is valid.
+ //assert(numInstsInROB == countInsts());
assert(inst);
- DPRINTF(ROB, "ROB: Adding inst PC %#x to the ROB.\n", inst->readPC());
+ DPRINTF(ROB, "Adding inst PC %#x to the ROB.\n", inst->readPC());
- // If the ROB is full then exit.
assert(numInstsInROB != numEntries);
- ++numInstsInROB;
+ int tid = inst->threadNumber;
- // Increment the tail iterator, moving it one instruction back.
- // There is a special case if the ROB was empty prior to this insertion,
- // in which case the tail will be pointing at instList.end(). If that
- // happens, then reset the tail to the beginning of the list.
- if (tail != cpu->instList.end()) {
- ++tail;
- } else {
- tail = cpu->instList.begin();
+ instList[tid].push_back(inst);
+
+ //Set Up head iterator if this is the 1st instruction in the ROB
+ if (numInstsInROB == 0) {
+ head = instList[tid].begin();
+ assert((*head) == inst);
}
- // Make sure the tail iterator is actually pointing at the instruction
- // added.
- assert((*tail) == inst);
+ //Must Decrement for iterator to actually be valid since __.end()
+ //actually points to 1 after the last inst
+ tail = instList[tid].end();
+ tail--;
- DPRINTF(ROB, "ROB: Now has %d instructions.\n", numInstsInROB);
+ inst->setInROB();
+
+ ++numInstsInROB;
+ ++threadEntries[tid];
+ assert((*tail) == inst);
+
+ DPRINTF(ROB, "[tid:%i] Now has %d instructions.\n", tid, threadEntries[tid]);
}
// Whatever calls this function needs to ensure that it properly frees up
// registers prior to this function.
+/*
template <class Impl>
void
ROB<Impl>::retireHead()
{
- assert(numInstsInROB == countInsts());
+ //assert(numInstsInROB == countInsts());
+ assert(numInstsInROB > 0);
+
+ int tid = (*head)->threadNumber;
+
+ retireHead(tid);
+
+ if (numInstsInROB == 0) {
+ tail = instList[tid].end();
+ }
+}
+*/
+
+template <class Impl>
+void
+ROB<Impl>::retireHead(unsigned tid)
+{
+ //assert(numInstsInROB == countInsts());
assert(numInstsInROB > 0);
// Get the head ROB instruction.
- DynInstPtr head_inst = cpu->instList.front();
+ InstIt head_it = instList[tid].begin();
+
+ DynInstPtr head_inst = (*head_it);
- // Make certain this can retire.
assert(head_inst->readyToCommit());
- DPRINTF(ROB, "ROB: Retiring head instruction of the ROB, "
- "instruction PC %#x, seq num %i\n", head_inst->readPC(),
+ DPRINTF(ROB, "[tid:%u]: Retiring head instruction, "
+ "instruction PC %#x,[sn:%lli]\n", tid, head_inst->readPC(),
head_inst->seqNum);
- // Keep track of how many instructions are in the ROB.
--numInstsInROB;
+ --threadEntries[tid];
+
+ head_inst->removeInROB();
+ head_inst->setCommitted();
+
+ instList[tid].erase(head_it);
- // Tell CPU to remove the instruction from the list of instructions.
- // A special case is needed if the instruction being retired is the
- // only instruction in the ROB; otherwise the tail iterator will become
- // invalidated.
+ //Update "Global" Head of ROB
+ updateHead();
+
+ // @todo: A special case is needed if the instruction being
+ // retired is the only instruction in the ROB; otherwise the tail
+ // iterator will become invalidated.
cpu->removeFrontInst(head_inst);
+}
+/*
+template <class Impl>
+bool
+ROB<Impl>::isHeadReady()
+{
+ if (numInstsInROB != 0) {
+ return (*head)->readyToCommit();
+ }
- if (numInstsInROB == 0) {
- tail = cpu->instList.end();
+ return false;
+}
+*/
+template <class Impl>
+bool
+ROB<Impl>::isHeadReady(unsigned tid)
+{
+ if (threadEntries[tid] != 0) {
+ return instList[tid].front()->readyToCommit();
}
+
+ return false;
}
template <class Impl>
bool
-ROB<Impl>::isHeadReady()
+ROB<Impl>::canCommit()
{
- if (numInstsInROB != 0) {
- return cpu->instList.front()->readyToCommit();
+ //@todo: set ActiveThreads through ROB or CPU
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ if (isHeadReady(tid)) {
+ return true;
+ }
}
return false;
@@ -175,131 +332,339 @@ template <class Impl>
unsigned
ROB<Impl>::numFreeEntries()
{
- assert(numInstsInROB == countInsts());
+ //assert(numInstsInROB == countInsts());
return numEntries - numInstsInROB;
}
template <class Impl>
+unsigned
+ROB<Impl>::numFreeEntries(unsigned tid)
+{
+ return maxEntries[tid] - threadEntries[tid];
+}
+
+template <class Impl>
void
-ROB<Impl>::doSquash()
+ROB<Impl>::doSquash(unsigned tid)
{
- DPRINTF(ROB, "ROB: Squashing instructions.\n");
+ DPRINTF(ROB, "[tid:%u]: Squashing instructions until [sn:%i].\n",
+ tid, squashedSeqNum);
+
+ assert(squashIt[tid] != instList[tid].end());
+
+ if ((*squashIt[tid])->seqNum < squashedSeqNum) {
+ DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n",
+ tid);
- assert(squashIt != cpu->instList.end());
+ squashIt[tid] = instList[tid].end();
+
+ doneSquashing[tid] = true;
+ return;
+ }
+
+ bool robTailUpdate = false;
for (int numSquashed = 0;
- numSquashed < squashWidth && (*squashIt)->seqNum != squashedSeqNum;
+ numSquashed < squashWidth &&
+ squashIt[tid] != instList[tid].end() &&
+ (*squashIt[tid])->seqNum > squashedSeqNum;
++numSquashed)
{
- // Ensure that the instruction is younger.
- assert((*squashIt)->seqNum > squashedSeqNum);
-
- DPRINTF(ROB, "ROB: Squashing instruction PC %#x, seq num %i.\n",
- (*squashIt)->readPC(), (*squashIt)->seqNum);
+ DPRINTF(ROB, "[tid:%u]: Squashing instruction PC %#x, seq num %i.\n",
+ (*squashIt[tid])->threadNumber,
+ (*squashIt[tid])->readPC(),
+ (*squashIt[tid])->seqNum);
// Mark the instruction as squashed, and ready to commit so that
// it can drain out of the pipeline.
- (*squashIt)->setSquashed();
-
- (*squashIt)->setCanCommit();
-
- // Special case for when squashing due to a syscall. It's possible
- // that the squash happened after the head instruction was already
- // committed, meaning that (*squashIt)->seqNum != squashedSeqNum
- // will never be false. Normally the squash would never be able
- // to go past the head of the ROB; in this case it might, so it
- // must be handled otherwise it will segfault.
-#if !FULL_SYSTEM
- if (squashIt == cpu->instList.begin()) {
- DPRINTF(ROB, "ROB: Reached head of instruction list while "
+ (*squashIt[tid])->setSquashed();
+
+ (*squashIt[tid])->setCanCommit();
+
+
+ if (squashIt[tid] == instList[tid].begin()) {
+ DPRINTF(ROB, "Reached head of instruction list while "
"squashing.\n");
- squashIt = cpu->instList.end();
+ squashIt[tid] = instList[tid].end();
- doneSquashing = true;
+ doneSquashing[tid] = true;
return;
}
-#endif
- // Move the tail iterator to the next instruction.
- squashIt--;
+ InstIt tail_thread = instList[tid].end();
+ tail_thread--;
+
+ if ((*squashIt[tid]) == (*tail_thread))
+ robTailUpdate = true;
+
+ squashIt[tid]--;
}
// Check if ROB is done squashing.
- if ((*squashIt)->seqNum == squashedSeqNum) {
- DPRINTF(ROB, "ROB: Done squashing instructions.\n");
+ if ((*squashIt[tid])->seqNum <= squashedSeqNum) {
+ DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n",
+ tid);
+
+ squashIt[tid] = instList[tid].end();
+
+ doneSquashing[tid] = true;
+ }
+
+ if (robTailUpdate) {
+ updateTail();
+ }
+}
+
+
+template <class Impl>
+void
+ROB<Impl>::updateHead()
+{
+ DynInstPtr head_inst;
+ InstSeqNum lowest_num = 0;
+ bool first_valid = true;
+
+ // @todo: set ActiveThreads through ROB or CPU
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned thread_num = *threads++;
+
+ if (instList[thread_num].empty())
+ continue;
+
+ if (first_valid) {
+ head = instList[thread_num].begin();
+ lowest_num = (*head)->seqNum;
+ first_valid = false;
+ continue;
+ }
+
+ InstIt head_thread = instList[thread_num].begin();
+
+ DynInstPtr head_inst = (*head_thread);
+
+ assert(head_inst != 0);
+
+ if (head_inst->seqNum < lowest_num) {
+ head = head_thread;
+ lowest_num = head_inst->seqNum;
+ }
+ }
+
+ if (first_valid) {
+ head = instList[0].end();
+ }
- squashIt = cpu->instList.end();
+}
+
+template <class Impl>
+void
+ROB<Impl>::updateTail()
+{
+ tail = instList[0].end();
+ bool first_valid = true;
+
+ list<unsigned>::iterator threads = (*activeThreads).begin();
+
+ while (threads != (*activeThreads).end()) {
+ unsigned tid = *threads++;
+
+ if (instList[tid].empty()) {
+ continue;
+ }
+
+ // If this is the first valid then assign w/out
+ // comparison
+ if (first_valid) {
+ tail = instList[tid].end();
+ tail--;
+ first_valid = false;
+ continue;
+ }
- doneSquashing = true;
+ // Assign new tail if this thread's tail is younger
+ // than our current "tail high"
+ InstIt tail_thread = instList[tid].end();
+ tail_thread--;
+
+ if ((*tail_thread)->seqNum > (*tail)->seqNum) {
+ tail = tail_thread;
+ }
}
}
+
template <class Impl>
void
-ROB<Impl>::squash(InstSeqNum squash_num)
+ROB<Impl>::squash(InstSeqNum squash_num,unsigned tid)
{
- DPRINTF(ROB, "ROB: Starting to squash within the ROB.\n");
- doneSquashing = false;
+ if (isEmpty()) {
+ DPRINTF(ROB, "Does not need to squash due to being empty "
+ "[sn:%i]\n",
+ squash_num);
+
+ return;
+ }
+
+ DPRINTF(ROB, "Starting to squash within the ROB.\n");
+
+ robStatus[tid] = ROBSquashing;
+
+ doneSquashing[tid] = false;
squashedSeqNum = squash_num;
- assert(tail != cpu->instList.end());
+ if (!instList[tid].empty()) {
+ InstIt tail_thread = instList[tid].end();
+ tail_thread--;
- squashIt = tail;
+ squashIt[tid] = tail_thread;
- doSquash();
+ doSquash(tid);
+ }
+}
+/*
+template <class Impl>
+typename Impl::DynInstPtr
+ROB<Impl>::readHeadInst()
+{
+ if (numInstsInROB != 0) {
+ assert((*head)->isInROB()==true);
+ return *head;
+ } else {
+ return dummyInst;
+ }
}
+*/
+template <class Impl>
+typename Impl::DynInstPtr
+ROB<Impl>::readHeadInst(unsigned tid)
+{
+ if (threadEntries[tid] != 0) {
+ InstIt head_thread = instList[tid].begin();
+ assert((*head_thread)->isInROB()==true);
+
+ return *head_thread;
+ } else {
+ return dummyInst;
+ }
+}
+/*
template <class Impl>
uint64_t
ROB<Impl>::readHeadPC()
{
- assert(numInstsInROB == countInsts());
+ //assert(numInstsInROB == countInsts());
- DynInstPtr head_inst = cpu->instList.front();
+ DynInstPtr head_inst = *head;
return head_inst->readPC();
}
template <class Impl>
uint64_t
+ROB<Impl>::readHeadPC(unsigned tid)
+{
+ //assert(numInstsInROB == countInsts());
+ InstIt head_thread = instList[tid].begin();
+
+ return (*head_thread)->readPC();
+}
+
+
+template <class Impl>
+uint64_t
ROB<Impl>::readHeadNextPC()
{
- assert(numInstsInROB == countInsts());
+ //assert(numInstsInROB == countInsts());
- DynInstPtr head_inst = cpu->instList.front();
+ DynInstPtr head_inst = *head;
return head_inst->readNextPC();
}
template <class Impl>
+uint64_t
+ROB<Impl>::readHeadNextPC(unsigned tid)
+{
+ //assert(numInstsInROB == countInsts());
+ InstIt head_thread = instList[tid].begin();
+
+ return (*head_thread)->readNextPC();
+}
+
+template <class Impl>
InstSeqNum
ROB<Impl>::readHeadSeqNum()
{
- // Return the last sequence number that has not been squashed. Other
- // stages can use it to squash any instructions younger than the current
- // tail.
- DynInstPtr head_inst = cpu->instList.front();
+ //assert(numInstsInROB == countInsts());
+ DynInstPtr head_inst = *head;
return head_inst->seqNum;
}
template <class Impl>
+InstSeqNum
+ROB<Impl>::readHeadSeqNum(unsigned tid)
+{
+ InstIt head_thread = instList[tid].begin();
+
+ return ((*head_thread)->seqNum);
+}
+
+template <class Impl>
+typename Impl::DynInstPtr
+ROB<Impl>::readTailInst()
+{
+ //assert(numInstsInROB == countInsts());
+ //assert(tail != instList[0].end());
+
+ return (*tail);
+}
+*/
+template <class Impl>
+typename Impl::DynInstPtr
+ROB<Impl>::readTailInst(unsigned tid)
+{
+ //assert(tail_thread[tid] != instList[tid].end());
+
+ InstIt tail_thread = instList[tid].end();
+ tail_thread--;
+
+ return *tail_thread;
+}
+
+/*
+template <class Impl>
uint64_t
ROB<Impl>::readTailPC()
{
- assert(numInstsInROB == countInsts());
+ //assert(numInstsInROB == countInsts());
- assert(tail != cpu->instList.end());
+ //assert(tail != instList[0].end());
return (*tail)->readPC();
}
template <class Impl>
+uint64_t
+ROB<Impl>::readTailPC(unsigned tid)
+{
+ //assert(tail_thread[tid] != instList[tid].end());
+
+ InstIt tail_thread = instList[tid].end();
+ tail_thread--;
+
+ return (*tail_thread)->readPC();
+}
+
+template <class Impl>
InstSeqNum
ROB<Impl>::readTailSeqNum()
{
@@ -309,4 +674,18 @@ ROB<Impl>::readTailSeqNum()
return (*tail)->seqNum;
}
-#endif // __CPU_O3_CPU_ROB_IMPL_HH__
+template <class Impl>
+InstSeqNum
+ROB<Impl>::readTailSeqNum(unsigned tid)
+{
+ // Return the last sequence number that has not been squashed. Other
+ // stages can use it to squash any instructions younger than the current
+ // tail.
+ // assert(tail_thread[tid] != instList[tid].end());
+
+ InstIt tail_thread = instList[tid].end();
+ tail_thread--;
+
+ return (*tail_thread)->seqNum;
+}
+*/
diff --git a/src/cpu/o3/sat_counter.cc b/src/cpu/o3/sat_counter.cc
index d20fff650..b481b4ad2 100644
--- a/src/cpu/o3/sat_counter.cc
+++ b/src/cpu/o3/sat_counter.cc
@@ -30,21 +30,21 @@
#include "cpu/o3/sat_counter.hh"
SatCounter::SatCounter()
- : maxVal(0), counter(0)
+ : initialVal(0), counter(0)
{
}
SatCounter::SatCounter(unsigned bits)
- : maxVal((1 << bits) - 1), counter(0)
+ : initialVal(0), maxVal((1 << bits) - 1), counter(0)
{
}
-SatCounter::SatCounter(unsigned bits, unsigned initial_val)
- : maxVal((1 << bits) - 1), counter(initial_val)
+SatCounter::SatCounter(unsigned bits, uint8_t initial_val)
+ : initialVal(initialVal), maxVal((1 << bits) - 1), counter(initial_val)
{
// Check to make sure initial value doesn't exceed the max counter value.
if (initial_val > maxVal) {
- panic("BP: Initial counter value exceeds max size.");
+ fatal("BP: Initial counter value exceeds max size.");
}
}
@@ -53,19 +53,3 @@ SatCounter::setBits(unsigned bits)
{
maxVal = (1 << bits) - 1;
}
-
-void
-SatCounter::increment()
-{
- if(counter < maxVal) {
- ++counter;
- }
-}
-
-void
-SatCounter::decrement()
-{
- if(counter > 0) {
- --counter;
- }
-}
diff --git a/src/cpu/o3/sat_counter.hh b/src/cpu/o3/sat_counter.hh
index b7cfe6423..d01fd93ce 100644
--- a/src/cpu/o3/sat_counter.hh
+++ b/src/cpu/o3/sat_counter.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2005 The Regents of The University of Michigan
+ * Copyright (c) 2005-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,8 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_SAT_COUNTER_HH__
-#define __CPU_O3_CPU_SAT_COUNTER_HH__
+#ifndef __CPU_O3_SAT_COUNTER_HH__
+#define __CPU_O3_SAT_COUNTER_HH__
#include "sim/host.hh"
@@ -44,47 +44,70 @@ class SatCounter
/**
* Constructor for the counter.
*/
- SatCounter();
+ SatCounter()
+ : initialVal(0), counter(0)
+ { }
/**
* Constructor for the counter.
* @param bits How many bits the counter will have.
*/
- SatCounter(unsigned bits);
+ SatCounter(unsigned bits)
+ : initialVal(0), maxVal((1 << bits) - 1), counter(0)
+ { }
/**
* Constructor for the counter.
* @param bits How many bits the counter will have.
* @param initial_val Starting value for each counter.
*/
- SatCounter(unsigned bits, unsigned initial_val);
+ SatCounter(unsigned bits, uint8_t initial_val)
+ : initialVal(initialVal), maxVal((1 << bits) - 1), counter(initial_val)
+ {
+ // Check to make sure initial value doesn't exceed the max
+ // counter value.
+ if (initial_val > maxVal) {
+ fatal("BP: Initial counter value exceeds max size.");
+ }
+ }
/**
* Sets the number of bits.
*/
- void setBits(unsigned bits);
+ void setBits(unsigned bits) { maxVal = (1 << bits) - 1; }
+
+ void reset() { counter = initialVal; }
/**
* Increments the counter's current value.
*/
- void increment();
+ void increment()
+ {
+ if (counter < maxVal) {
+ ++counter;
+ }
+ }
/**
* Decrements the counter's current value.
*/
- void decrement();
+ void decrement()
+ {
+ if (counter > 0) {
+ --counter;
+ }
+ }
/**
* Read the counter's value.
*/
const uint8_t read() const
- {
- return counter;
- }
+ { return counter; }
private:
+ uint8_t initialVal;
uint8_t maxVal;
uint8_t counter;
};
-#endif // __CPU_O3_CPU_SAT_COUNTER_HH__
+#endif // __CPU_O3_SAT_COUNTER_HH__
diff --git a/src/cpu/o3/store_set.cc b/src/cpu/o3/store_set.cc
index 11023f4a8..0c957c8c7 100644
--- a/src/cpu/o3/store_set.cc
+++ b/src/cpu/o3/store_set.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -30,43 +30,76 @@
#include "cpu/o3/store_set.hh"
StoreSet::StoreSet(int _SSIT_size, int _LFST_size)
- : SSIT_size(_SSIT_size), LFST_size(_LFST_size)
+ : SSITSize(_SSIT_size), LFSTSize(_LFST_size)
{
DPRINTF(StoreSet, "StoreSet: Creating store set object.\n");
DPRINTF(StoreSet, "StoreSet: SSIT size: %i, LFST size: %i.\n",
- SSIT_size, LFST_size);
+ SSITSize, LFSTSize);
- SSIT = new SSID[SSIT_size];
+ SSIT.resize(SSITSize);
- validSSIT.resize(SSIT_size);
+ validSSIT.resize(SSITSize);
- for (int i = 0; i < SSIT_size; ++i)
+ for (int i = 0; i < SSITSize; ++i)
validSSIT[i] = false;
- LFST = new InstSeqNum[LFST_size];
+ LFST.resize(LFSTSize);
- validLFST.resize(LFST_size);
+ validLFST.resize(LFSTSize);
- SSCounters = new int[LFST_size];
+ for (int i = 0; i < LFSTSize; ++i) {
+ validLFST[i] = false;
+ LFST[i] = 0;
+ }
+
+ indexMask = SSITSize - 1;
+
+ offsetBits = 2;
+}
+
+StoreSet::~StoreSet()
+{
+}
+
+void
+StoreSet::init(int _SSIT_size, int _LFST_size)
+{
+ SSITSize = _SSIT_size;
+ LFSTSize = _LFST_size;
- for (int i = 0; i < LFST_size; ++i)
- {
+ DPRINTF(StoreSet, "StoreSet: Creating store set object.\n");
+ DPRINTF(StoreSet, "StoreSet: SSIT size: %i, LFST size: %i.\n",
+ SSITSize, LFSTSize);
+
+ SSIT.resize(SSITSize);
+
+ validSSIT.resize(SSITSize);
+
+ for (int i = 0; i < SSITSize; ++i)
+ validSSIT[i] = false;
+
+ LFST.resize(LFSTSize);
+
+ validLFST.resize(LFSTSize);
+
+ for (int i = 0; i < LFSTSize; ++i) {
validLFST[i] = false;
- SSCounters[i] = 0;
+ LFST[i] = 0;
}
- index_mask = SSIT_size - 1;
+ indexMask = SSITSize - 1;
- offset_bits = 2;
+ offsetBits = 2;
}
+
void
StoreSet::violation(Addr store_PC, Addr load_PC)
{
int load_index = calcIndex(load_PC);
int store_index = calcIndex(store_PC);
- assert(load_index < SSIT_size && store_index < SSIT_size);
+ assert(load_index < SSITSize && store_index < SSITSize);
bool valid_load_SSID = validSSIT[load_index];
bool valid_store_SSID = validSSIT[store_index];
@@ -83,10 +116,7 @@ StoreSet::violation(Addr store_PC, Addr load_PC)
SSIT[store_index] = new_set;
- assert(new_set < LFST_size);
-
- SSCounters[new_set]++;
-
+ assert(new_set < LFSTSize);
DPRINTF(StoreSet, "StoreSet: Neither load nor store had a valid "
"storeset, creating a new one: %i for load %#x, store %#x\n",
@@ -98,9 +128,7 @@ StoreSet::violation(Addr store_PC, Addr load_PC)
SSIT[store_index] = load_SSID;
- assert(load_SSID < LFST_size);
-
- SSCounters[load_SSID]++;
+ assert(load_SSID < LFSTSize);
DPRINTF(StoreSet, "StoreSet: Load had a valid store set. Adding "
"store to that set: %i for load %#x, store %#x\n",
@@ -112,9 +140,6 @@ StoreSet::violation(Addr store_PC, Addr load_PC)
SSIT[load_index] = store_SSID;
- // Because we are having a load point to an already existing set,
- // the size of the store set is not incremented.
-
DPRINTF(StoreSet, "StoreSet: Store had a valid store set: %i for "
"load %#x, store %#x\n",
store_SSID, load_PC, store_PC);
@@ -122,29 +147,19 @@ StoreSet::violation(Addr store_PC, Addr load_PC)
SSID load_SSID = SSIT[load_index];
SSID store_SSID = SSIT[store_index];
- assert(load_SSID < LFST_size && store_SSID < LFST_size);
-
- int load_SS_size = SSCounters[load_SSID];
- int store_SS_size = SSCounters[store_SSID];
+ assert(load_SSID < LFSTSize && store_SSID < LFSTSize);
- // If the load has the bigger store set, then assign the store
- // to the same store set as the load. Otherwise vice-versa.
- if (load_SS_size > store_SS_size) {
+ // The store set with the lower number wins
+ if (store_SSID > load_SSID) {
SSIT[store_index] = load_SSID;
- SSCounters[load_SSID]++;
- SSCounters[store_SSID]--;
-
- DPRINTF(StoreSet, "StoreSet: Load had bigger store set: %i; "
+ DPRINTF(StoreSet, "StoreSet: Load had smaller store set: %i; "
"for load %#x, store %#x\n",
load_SSID, load_PC, store_PC);
} else {
SSIT[load_index] = store_SSID;
- SSCounters[store_SSID]++;
- SSCounters[load_SSID]--;
-
- DPRINTF(StoreSet, "StoreSet: Store had bigger store set: %i; "
+ DPRINTF(StoreSet, "StoreSet: Store had smaller store set: %i; "
"for load %#x, store %#x\n",
store_SSID, load_PC, store_PC);
}
@@ -159,13 +174,14 @@ StoreSet::insertLoad(Addr load_PC, InstSeqNum load_seq_num)
}
void
-StoreSet::insertStore(Addr store_PC, InstSeqNum store_seq_num)
+StoreSet::insertStore(Addr store_PC, InstSeqNum store_seq_num,
+ unsigned tid)
{
int index = calcIndex(store_PC);
int store_SSID;
- assert(index < SSIT_size);
+ assert(index < SSITSize);
if (!validSSIT[index]) {
// Do nothing if there's no valid entry.
@@ -173,13 +189,15 @@ StoreSet::insertStore(Addr store_PC, InstSeqNum store_seq_num)
} else {
store_SSID = SSIT[index];
- assert(store_SSID < LFST_size);
+ assert(store_SSID < LFSTSize);
// Update the last store that was fetched with the current one.
LFST[store_SSID] = store_seq_num;
validLFST[store_SSID] = 1;
+ storeList[store_seq_num] = store_SSID;
+
DPRINTF(StoreSet, "Store %#x updated the LFST, SSID: %i\n",
store_PC, store_SSID);
}
@@ -192,7 +210,7 @@ StoreSet::checkInst(Addr PC)
int inst_SSID;
- assert(index < SSIT_size);
+ assert(index < SSITSize);
if (!validSSIT[index]) {
DPRINTF(StoreSet, "Inst %#x with index %i had no SSID\n",
@@ -203,7 +221,7 @@ StoreSet::checkInst(Addr PC)
} else {
inst_SSID = SSIT[index];
- assert(inst_SSID < LFST_size);
+ assert(inst_SSID < LFSTSize);
if (!validLFST[inst_SSID]) {
@@ -232,7 +250,13 @@ StoreSet::issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store)
int store_SSID;
- assert(index < SSIT_size);
+ assert(index < SSITSize);
+
+ SeqNumMapIt store_list_it = storeList.find(issued_seq_num);
+
+ if (store_list_it != storeList.end()) {
+ storeList.erase(store_list_it);
+ }
// Make sure the SSIT still has a valid entry for the issued store.
if (!validSSIT[index]) {
@@ -241,7 +265,7 @@ StoreSet::issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store)
store_SSID = SSIT[index];
- assert(store_SSID < LFST_size);
+ assert(store_SSID < LFSTSize);
// If the last fetched store in the store set refers to the store that
// was just issued, then invalidate the entry.
@@ -252,18 +276,31 @@ StoreSet::issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store)
}
void
-StoreSet::squash(InstSeqNum squashed_num)
+StoreSet::squash(InstSeqNum squashed_num, unsigned tid)
{
- // Not really sure how to do this well.
- // Generally this is small enough that it should be okay; short circuit
- // evaluation should take care of invalid entries.
-
DPRINTF(StoreSet, "StoreSet: Squashing until inum %i\n",
squashed_num);
- for (int i = 0; i < LFST_size; ++i) {
- if (validLFST[i] && LFST[i] < squashed_num) {
- validLFST[i] = false;
+ int idx;
+ SeqNumMapIt store_list_it = storeList.begin();
+
+ //@todo:Fix to only delete from correct thread
+ while (!storeList.empty()) {
+ idx = (*store_list_it).second;
+
+ if ((*store_list_it).first <= squashed_num) {
+ break;
+ }
+
+ bool younger = LFST[idx] > squashed_num;
+
+ if (validLFST[idx] && younger) {
+ DPRINTF(StoreSet, "Squashed [sn:%lli]\n", LFST[idx]);
+ validLFST[idx] = false;
+
+ storeList.erase(store_list_it++);
+ } else if (!validLFST[idx] && younger) {
+ storeList.erase(store_list_it++);
}
}
}
@@ -271,12 +308,13 @@ StoreSet::squash(InstSeqNum squashed_num)
void
StoreSet::clear()
{
- for (int i = 0; i < SSIT_size; ++i) {
+ for (int i = 0; i < SSITSize; ++i) {
validSSIT[i] = false;
}
- for (int i = 0; i < LFST_size; ++i) {
+ for (int i = 0; i < LFSTSize; ++i) {
validLFST[i] = false;
}
-}
+ storeList.clear();
+}
diff --git a/src/cpu/o3/store_set.hh b/src/cpu/o3/store_set.hh
index 5a885d838..7189db3ab 100644
--- a/src/cpu/o3/store_set.hh
+++ b/src/cpu/o3/store_set.hh
@@ -26,61 +26,80 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_STORE_SET_HH__
-#define __CPU_O3_CPU_STORE_SET_HH__
+#ifndef __CPU_O3_STORE_SET_HH__
+#define __CPU_O3_STORE_SET_HH__
+#include <list>
+#include <map>
+#include <utility>
#include <vector>
#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
+struct ltseqnum {
+ bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
+ {
+ return lhs > rhs;
+ }
+};
+
class StoreSet
{
public:
typedef unsigned SSID;
public:
+ StoreSet() { };
+
StoreSet(int SSIT_size, int LFST_size);
+ ~StoreSet();
+
+ void init(int SSIT_size, int LFST_size);
+
void violation(Addr store_PC, Addr load_PC);
void insertLoad(Addr load_PC, InstSeqNum load_seq_num);
- void insertStore(Addr store_PC, InstSeqNum store_seq_num);
+ void insertStore(Addr store_PC, InstSeqNum store_seq_num,
+ unsigned tid);
InstSeqNum checkInst(Addr PC);
void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
- void squash(InstSeqNum squashed_num);
+ void squash(InstSeqNum squashed_num, unsigned tid);
void clear();
private:
inline int calcIndex(Addr PC)
- { return (PC >> offset_bits) & index_mask; }
+ { return (PC >> offsetBits) & indexMask; }
inline SSID calcSSID(Addr PC)
- { return ((PC ^ (PC >> 10)) % LFST_size); }
+ { return ((PC ^ (PC >> 10)) % LFSTSize); }
- SSID *SSIT;
+ std::vector<SSID> SSIT;
std::vector<bool> validSSIT;
- InstSeqNum *LFST;
+ std::vector<InstSeqNum> LFST;
std::vector<bool> validLFST;
- int *SSCounters;
+ std::map<InstSeqNum, int, ltseqnum> storeList;
+
+ typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt;
- int SSIT_size;
+ int SSITSize;
- int LFST_size;
+ int LFSTSize;
- int index_mask;
+ int indexMask;
// HACK: Hardcoded for now.
- int offset_bits;
+ int offsetBits;
};
-#endif // __CPU_O3_CPU_STORE_SET_HH__
+#endif // __CPU_O3_STORE_SET_HH__
diff --git a/src/cpu/o3/tournament_pred.cc b/src/cpu/o3/tournament_pred.cc
index 3fb580510..89da7b9f5 100644
--- a/src/cpu/o3/tournament_pred.cc
+++ b/src/cpu/o3/tournament_pred.cc
@@ -28,37 +28,37 @@
#include "cpu/o3/tournament_pred.hh"
-TournamentBP::TournamentBP(unsigned _local_predictor_size,
- unsigned _local_ctr_bits,
- unsigned _local_history_table_size,
- unsigned _local_history_bits,
- unsigned _global_predictor_size,
- unsigned _global_ctr_bits,
- unsigned _global_history_bits,
- unsigned _choice_predictor_size,
- unsigned _choice_ctr_bits,
+TournamentBP::TournamentBP(unsigned _localPredictorSize,
+ unsigned _localCtrBits,
+ unsigned _localHistoryTableSize,
+ unsigned _localHistoryBits,
+ unsigned _globalPredictorSize,
+ unsigned _globalCtrBits,
+ unsigned _globalHistoryBits,
+ unsigned _choicePredictorSize,
+ unsigned _choiceCtrBits,
unsigned _instShiftAmt)
- : localPredictorSize(_local_predictor_size),
- localCtrBits(_local_ctr_bits),
- localHistoryTableSize(_local_history_table_size),
- localHistoryBits(_local_history_bits),
- globalPredictorSize(_global_predictor_size),
- globalCtrBits(_global_ctr_bits),
- globalHistoryBits(_global_history_bits),
- choicePredictorSize(_global_predictor_size),
- choiceCtrBits(_choice_ctr_bits),
+ : localPredictorSize(_localPredictorSize),
+ localCtrBits(_localCtrBits),
+ localHistoryTableSize(_localHistoryTableSize),
+ localHistoryBits(_localHistoryBits),
+ globalPredictorSize(_globalPredictorSize),
+ globalCtrBits(_globalCtrBits),
+ globalHistoryBits(_globalHistoryBits),
+ choicePredictorSize(_globalPredictorSize),
+ choiceCtrBits(_choiceCtrBits),
instShiftAmt(_instShiftAmt)
{
//Should do checks here to make sure sizes are correct (powers of 2)
//Setup the array of counters for the local predictor
- localCtrs = new SatCounter[localPredictorSize];
+ localCtrs.resize(localPredictorSize);
for (int i = 0; i < localPredictorSize; ++i)
localCtrs[i].setBits(localCtrBits);
//Setup the history table for the local table
- localHistoryTable = new unsigned[localHistoryTableSize];
+ localHistoryTable.resize(localHistoryTableSize);
for (int i = 0; i < localHistoryTableSize; ++i)
localHistoryTable[i] = 0;
@@ -67,7 +67,7 @@ TournamentBP::TournamentBP(unsigned _local_predictor_size,
localHistoryMask = (1 << localHistoryBits) - 1;
//Setup the array of counters for the global predictor
- globalCtrs = new SatCounter[globalPredictorSize];
+ globalCtrs.resize(globalPredictorSize);
for (int i = 0; i < globalPredictorSize; ++i)
globalCtrs[i].setBits(globalCtrBits);
@@ -78,7 +78,7 @@ TournamentBP::TournamentBP(unsigned _local_predictor_size,
globalHistoryMask = (1 << globalHistoryBits) - 1;
//Setup the array of counters for the choice predictor
- choiceCtrs = new SatCounter[choicePredictorSize];
+ choiceCtrs.resize(choicePredictorSize);
for (int i = 0; i < choicePredictorSize; ++i)
choiceCtrs[i].setBits(choiceCtrBits);
@@ -240,8 +240,7 @@ TournamentBP::update(Addr &branch_addr, unsigned correct_gh, bool taken)
globalHistory = globalHistory & globalHistoryMask;
localHistoryTable[local_history_idx] |= 1;
- }
- else {
+ } else {
assert(globalHistory < globalPredictorSize &&
local_predictor_idx < localPredictorSize);
diff --git a/src/cpu/o3/tournament_pred.hh b/src/cpu/o3/tournament_pred.hh
index cb93c2f67..7b600aa53 100644
--- a/src/cpu/o3/tournament_pred.hh
+++ b/src/cpu/o3/tournament_pred.hh
@@ -26,12 +26,13 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_O3_CPU_TOURNAMENT_PRED_HH__
-#define __CPU_O3_CPU_TOURNAMENT_PRED_HH__
+#ifndef __CPU_O3_TOURNAMENT_PRED_HH__
+#define __CPU_O3_TOURNAMENT_PRED_HH__
// For Addr type.
#include "arch/isa_traits.hh"
#include "cpu/o3/sat_counter.hh"
+#include <vector>
class TournamentBP
{
@@ -39,15 +40,15 @@ class TournamentBP
/**
* Default branch predictor constructor.
*/
- TournamentBP(unsigned local_predictor_size,
- unsigned local_ctr_bits,
- unsigned local_history_table_size,
- unsigned local_history_bits,
- unsigned global_predictor_size,
- unsigned global_history_bits,
- unsigned global_ctr_bits,
- unsigned choice_predictor_size,
- unsigned choice_ctr_bits,
+ TournamentBP(unsigned localPredictorSize,
+ unsigned localCtrBits,
+ unsigned localHistoryTableSize,
+ unsigned localHistoryBits,
+ unsigned globalPredictorSize,
+ unsigned globalHistoryBits,
+ unsigned globalCtrBits,
+ unsigned choicePredictorSize,
+ unsigned choiceCtrBits,
unsigned instShiftAmt);
/**
@@ -78,7 +79,7 @@ class TournamentBP
inline void updateHistoriesNotTaken(unsigned local_history_idx);
/** Local counters. */
- SatCounter *localCtrs;
+ std::vector<SatCounter> localCtrs;
/** Size of the local predictor. */
unsigned localPredictorSize;
@@ -87,7 +88,7 @@ class TournamentBP
unsigned localCtrBits;
/** Array of local history table entries. */
- unsigned *localHistoryTable;
+ std::vector<unsigned> localHistoryTable;
/** Size of the local history table. */
unsigned localHistoryTableSize;
@@ -102,7 +103,7 @@ class TournamentBP
/** Array of counters that make up the global predictor. */
- SatCounter *globalCtrs;
+ std::vector<SatCounter> globalCtrs;
/** Size of the global predictor. */
unsigned globalPredictorSize;
@@ -121,7 +122,7 @@ class TournamentBP
/** Array of counters that make up the choice predictor. */
- SatCounter *choiceCtrs;
+ std::vector<SatCounter> choiceCtrs;
/** Size of the choice predictor (identical to the global predictor). */
unsigned choicePredictorSize;
@@ -140,4 +141,4 @@ class TournamentBP
unsigned threshold;
};
-#endif // __CPU_O3_CPU_TOURNAMENT_PRED_HH__
+#endif // __CPU_O3_TOURNAMENT_PRED_HH__
diff --git a/src/cpu/ozone/cpu.cc b/src/cpu/ozone/cpu.cc
index cbeca9d3b..d2ea0164c 100644
--- a/src/cpu/ozone/cpu.cc
+++ b/src/cpu/ozone/cpu.cc
@@ -26,8 +26,9 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "cpu/ooo_cpu/ooo_cpu_impl.hh"
-#include "cpu/ooo_cpu/ooo_dyn_inst.hh"
-#include "cpu/ooo_cpu/ooo_impl.hh"
+#include "cpu/ozone/cpu_impl.hh"
+#include "cpu/ozone/ozone_impl.hh"
+#include "cpu/ozone/simple_impl.hh"
-template class OoOCPU<OoOImpl>;
+template class OzoneCPU<SimpleImpl>;
+template class OzoneCPU<OzoneImpl>;
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index fa849bb09..5af2b02b2 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -26,15 +26,19 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_OOO_CPU_OOO_CPU_HH__
-#define __CPU_OOO_CPU_OOO_CPU_HH__
+#ifndef __CPU_OZONE_CPU_HH__
+#define __CPU_OZONE_CPU_HH__
+
+#include <set>
#include "base/statistics.hh"
+#include "base/timebuf.hh"
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/exec_context.hh"
-#include "encumbered/cpu/full/fu_pool.hh"
-#include "cpu/ooo_cpu/ea_list.hh"
+#include "cpu/inst_seq.hh"
+#include "cpu/ozone/rename_table.hh"
+#include "cpu/ozone/thread_state.hh"
#include "cpu/pc_event.hh"
#include "cpu/static_inst.hh"
#include "mem/mem_interface.hh"
@@ -42,14 +46,21 @@
// forward declarations
#if FULL_SYSTEM
-class Processor;
+#include "arch/alpha/tlb.hh"
+
class AlphaITB;
class AlphaDTB;
class PhysicalMemory;
+class MemoryController;
+class Sampler;
class RemoteGDB;
class GDBListener;
+namespace Kernel {
+ class Statistics;
+};
+
#else
class Process;
@@ -57,12 +68,16 @@ class Process;
#endif // FULL_SYSTEM
class Checkpoint;
+class EndQuiesceEvent;
class MemInterface;
namespace Trace {
class InstRecord;
}
+template <class>
+class Checker;
+
/**
* Declaration of Out-of-Order CPU class. Basically it is a SimpleCPU with
* simple out-of-order capabilities added to it. It is still a 1 CPI machine
@@ -72,23 +87,177 @@ namespace Trace {
*/
template <class Impl>
-class OoOCPU : public BaseCPU
+class OzoneCPU : public BaseCPU
{
private:
+ typedef typename Impl::FrontEnd FrontEnd;
+ typedef typename Impl::BackEnd BackEnd;
typedef typename Impl::DynInst DynInst;
typedef typename Impl::DynInstPtr DynInstPtr;
+ typedef TheISA::MiscReg MiscReg;
+
+ public:
+ class OzoneXC : public ExecContext {
+ public:
+ OzoneCPU<Impl> *cpu;
+
+ OzoneThreadState<Impl> *thread;
+
+ BaseCPU *getCpuPtr();
+
+ void setCpuId(int id);
+
+ int readCpuId() { return thread->cpuId; }
+
+ FunctionalMemory *getMemPtr() { return thread->mem; }
+
+#if FULL_SYSTEM
+ System *getSystemPtr() { return cpu->system; }
+
+ PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
+
+ AlphaITB *getITBPtr() { return cpu->itb; }
+
+ AlphaDTB * getDTBPtr() { return cpu->dtb; }
+
+ Kernel::Statistics *getKernelStats() { return thread->kernelStats; }
+#else
+ Process *getProcessPtr() { return thread->process; }
+#endif
+
+ Status status() const { return thread->_status; }
+
+ void setStatus(Status new_status);
+
+ /// Set the status to Active. Optional delay indicates number of
+ /// cycles to wait before beginning execution.
+ void activate(int delay = 1);
+
+ /// Set the status to Suspended.
+ void suspend();
+
+ /// Set the status to Unallocated.
+ void deallocate();
+
+ /// Set the status to Halted.
+ void halt();
+
+#if FULL_SYSTEM
+ void dumpFuncProfile();
+#endif
+
+ void takeOverFrom(ExecContext *old_context);
+
+ void regStats(const std::string &name);
+
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string &section);
+
+#if FULL_SYSTEM
+ EndQuiesceEvent *getQuiesceEvent();
+
+ Tick readLastActivate();
+ Tick readLastSuspend();
+
+ void profileClear();
+ void profileSample();
+#endif
+
+ int getThreadNum();
+
+ // Also somewhat obnoxious. Really only used for the TLB fault.
+ TheISA::MachInst getInst();
+
+ void copyArchRegs(ExecContext *xc);
+
+ void clearArchRegs();
+
+ uint64_t readIntReg(int reg_idx);
+
+ float readFloatRegSingle(int reg_idx);
+
+ double readFloatRegDouble(int reg_idx);
+
+ uint64_t readFloatRegInt(int reg_idx);
+
+ void setIntReg(int reg_idx, uint64_t val);
+
+ void setFloatRegSingle(int reg_idx, float val);
+
+ void setFloatRegDouble(int reg_idx, double val);
+
+ void setFloatRegInt(int reg_idx, uint64_t val);
+
+ uint64_t readPC() { return thread->PC; }
+ void setPC(Addr val);
+
+ uint64_t readNextPC() { return thread->nextPC; }
+ void setNextPC(Addr val);
+
+ public:
+ // ISA stuff:
+ MiscReg readMiscReg(int misc_reg);
+
+ MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
+
+ Fault setMiscReg(int misc_reg, const MiscReg &val);
+
+ Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
+
+ unsigned readStCondFailures()
+ { return thread->storeCondFailures; }
+
+ void setStCondFailures(unsigned sc_failures)
+ { thread->storeCondFailures = sc_failures; }
+
+#if FULL_SYSTEM
+ bool inPalMode() { return cpu->inPalMode(); }
+#endif
+
+ bool misspeculating() { return false; }
+
+#if !FULL_SYSTEM
+ TheISA::IntReg getSyscallArg(int i)
+ { return thread->renameTable[TheISA::ArgumentReg0 + i]->readIntResult(); }
+
+ // used to shift args for indirect syscall
+ void setSyscallArg(int i, TheISA::IntReg val)
+ { thread->renameTable[TheISA::ArgumentReg0 + i]->setIntResult(i); }
+
+ void setSyscallReturn(SyscallReturn return_value)
+ { cpu->setSyscallReturn(return_value, thread->tid); }
+
+ Counter readFuncExeInst() { return thread->funcExeInst; }
+
+ void setFuncExeInst(Counter new_val)
+ { thread->funcExeInst = new_val; }
+#endif
+ };
+
+ // execution context proxy
+ OzoneXC ozoneXC;
+ ExecContext *xcProxy;
+ ExecContext *checkerXC;
+
+ typedef OzoneThreadState<Impl> ImplState;
+
+ private:
+ OzoneThreadState<Impl> thread;
+
public:
// main simulation loop (one cycle)
void tick();
+ std::set<InstSeqNum> snList;
+ std::set<Addr> lockAddrList;
private:
struct TickEvent : public Event
{
- OoOCPU *cpu;
+ OzoneCPU *cpu;
int width;
- TickEvent(OoOCPU *c, int w);
+ TickEvent(OzoneCPU *c, int w);
void process();
const char *description();
};
@@ -99,9 +268,9 @@ class OoOCPU : public BaseCPU
void scheduleTickEvent(int delay)
{
if (tickEvent.squashed())
- tickEvent.reschedule(curTick + delay);
+ tickEvent.reschedule(curTick + cycles(delay));
else if (!tickEvent.scheduled())
- tickEvent.schedule(curTick + delay);
+ tickEvent.schedule(curTick + cycles(delay));
}
/// Unschedule tick event, regardless of its current state.
@@ -118,20 +287,17 @@ class OoOCPU : public BaseCPU
void trace_data(T data);
public:
- //
enum Status {
Running,
Idle,
- IcacheMiss,
- IcacheMissComplete,
- DcacheMissStall,
SwitchedOut
};
- private:
Status _status;
public:
+ bool checkInterrupts;
+
void post_interrupt(int int_num, int index);
void zero_fill_64(Addr addr) {
@@ -142,41 +308,45 @@ class OoOCPU : public BaseCPU
}
};
- struct Params : public BaseCPU::Params
- {
- MemInterface *icache_interface;
- MemInterface *dcache_interface;
- int width;
-#if FULL_SYSTEM
- AlphaITB *itb;
- AlphaDTB *dtb;
- FunctionalMemory *mem;
-#else
- Process *process;
-#endif
- int issueWidth;
- };
+ typedef typename Impl::Params Params;
- OoOCPU(Params *params);
+ OzoneCPU(Params *params);
- virtual ~OoOCPU();
+ virtual ~OzoneCPU();
void init();
- private:
- void copyFromXC();
-
public:
- // execution context
- ExecContext *xc;
+ BaseCPU *getCpuPtr() { return this; }
+
+ void setCpuId(int id) { cpuId = id; }
+
+ int readCpuId() { return cpuId; }
+
+ int cpuId;
- void switchOut();
+ void switchOut(Sampler *sampler);
+ void signalSwitched();
void takeOverFrom(BaseCPU *oldCPU);
+ Sampler *sampler;
+
+ int switchCount;
+
#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr);
bool interval_stats;
+
+ AlphaITB *itb;
+ AlphaDTB *dtb;
+ System *system;
+
+ // the following two fields are redundant, since we can always
+ // look them up through the system pointer, but we'll leave them
+ // here for now for convenience
+ MemoryController *memctrl;
+ PhysicalMemory *physmem;
#endif
// L1 instruction cache
@@ -185,54 +355,15 @@ class OoOCPU : public BaseCPU
// L1 data cache
MemInterface *dcacheInterface;
- FuncUnitPool *fuPool;
+ /** Pointer to memory. */
+ FunctionalMemory *mem;
- // Refcounted pointer to the one memory request.
- MemReqPtr cacheMemReq;
-
- class ICacheCompletionEvent : public Event
- {
- private:
- OoOCPU *cpu;
-
- public:
- ICacheCompletionEvent(OoOCPU *_cpu);
-
- virtual void process();
- virtual const char *description();
- };
-
- // Will need to create a cache completion event upon any memory miss.
- ICacheCompletionEvent iCacheCompletionEvent;
-
- class DCacheCompletionEvent;
-
- typedef typename
- std::list<DCacheCompletionEvent>::iterator DCacheCompEventIt;
-
- class DCacheCompletionEvent : public Event
- {
- private:
- OoOCPU *cpu;
- DynInstPtr inst;
- DCacheCompEventIt dcceIt;
-
- public:
- DCacheCompletionEvent(OoOCPU *_cpu, DynInstPtr &_inst,
- DCacheCompEventIt &_dcceIt);
-
- virtual void process();
- virtual const char *description();
- };
-
- friend class DCacheCompletionEvent;
-
- protected:
- std::list<DCacheCompletionEvent> dCacheCompList;
- DCacheCompEventIt dcceIt;
+ FrontEnd *frontEnd;
+ BackEnd *backEnd;
private:
Status status() const { return _status; }
+ void setStatus(Status new_status) { _status = new_status; }
virtual void activateContext(int thread_num, int delay);
virtual void suspendContext(int thread_num);
@@ -244,18 +375,16 @@ class OoOCPU : public BaseCPU
virtual void resetStats();
// number of simulated instructions
+ public:
Counter numInst;
Counter startNumInst;
- Stats::Scalar<> numInsts;
virtual Counter totalInstructions() const
{
return numInst - startNumInst;
}
- // number of simulated memory references
- Stats::Scalar<> numMemRefs;
-
+ private:
// number of simulated loads
Counter numLoad;
Counter startNumLoad;
@@ -263,27 +392,15 @@ class OoOCPU : public BaseCPU
// number of idle cycles
Stats::Average<> notIdleFraction;
Stats::Formula idleFraction;
-
- // number of cycles stalled for I-cache misses
- Stats::Scalar<> icacheStallCycles;
- Counter lastIcacheStall;
-
- // number of cycles stalled for D-cache misses
- Stats::Scalar<> dcacheStallCycles;
- Counter lastDcacheStall;
-
- void processICacheCompletion();
-
public:
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
+
#if FULL_SYSTEM
bool validInstAddr(Addr addr) { return true; }
bool validDataAddr(Addr addr) { return true; }
- int getInstAsid() { return xc->regs.instAsid(); }
- int getDataAsid() { return xc->regs.dataAsid(); }
Fault translateInstReq(MemReqPtr &req)
{
@@ -302,13 +419,13 @@ class OoOCPU : public BaseCPU
#else
bool validInstAddr(Addr addr)
- { return xc->validInstAddr(addr); }
+ { return true; }
bool validDataAddr(Addr addr)
- { return xc->validDataAddr(addr); }
+ { return true; }
- int getInstAsid() { return xc->asid; }
- int getDataAsid() { return xc->asid; }
+ int getInstAsid() { return thread.asid; }
+ int getDataAsid() { return thread.asid; }
Fault dummyTranslation(MemReqPtr &req)
{
@@ -321,318 +438,192 @@ class OoOCPU : public BaseCPU
req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
return NoFault;
}
+
+ /** Translates instruction requestion in syscall emulation mode. */
Fault translateInstReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
+
+ /** Translates data read request in syscall emulation mode. */
Fault translateDataReadReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
+
+ /** Translates data write request in syscall emulation mode. */
Fault translateDataWriteReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
-
#endif
+ /** Old CPU read from memory function. No longer used. */
template <class T>
- Fault read(Addr addr, T &data, unsigned flags, DynInstPtr inst);
-
- template <class T>
- Fault write(T data, Addr addr, unsigned flags,
- uint64_t *res, DynInstPtr inst);
-
- void prefetch(Addr addr, unsigned flags)
+ Fault read(MemReqPtr &req, T &data)
{
- // need to do this...
- }
-
- void writeHint(Addr addr, int size, unsigned flags)
- {
- // need to do this...
- }
-
- Fault copySrcTranslate(Addr src);
-
- Fault copy(Addr dest);
-
- private:
- bool executeInst(DynInstPtr &inst);
-
- void renameInst(DynInstPtr &inst);
-
- void addInst(DynInstPtr &inst);
-
- void commitHeadInst();
-
- bool getOneInst();
-
- Fault fetchCacheLine();
-
- InstSeqNum getAndIncrementInstSeq();
-
- bool ambigMemAddr;
-
- private:
- InstSeqNum globalSeqNum;
-
- DynInstPtr renameTable[TheISA::TotalNumRegs];
- DynInstPtr commitTable[TheISA::TotalNumRegs];
-
- // Might need a table of the shadow registers as well.
-#if FULL_SYSTEM
- DynInstPtr palShadowTable[TheISA::NumIntRegs];
+#if 0
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
+ if (req->flags & LOCKED) {
+ req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
+ req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
+ }
+#endif
#endif
+ Fault error;
+ if (req->flags & LOCKED) {
+ lockAddrList.insert(req->paddr);
+ lockFlag = true;
+ }
- public:
- // The register accessor methods provide the index of the
- // instruction's operand (e.g., 0 or 1), not the architectural
- // register index, to simplify the implementation of register
- // renaming. We find the architectural register index by indexing
- // into the instruction's own operand index table. Note that a
- // raw pointer to the StaticInst is provided instead of a
- // ref-counted StaticInstPtr to redice overhead. This is fine as
- // long as these methods don't copy the pointer into any long-term
- // storage (which is pretty hard to imagine they would have reason
- // to do).
-
- // In the OoO case these shouldn't read from the XC but rather from the
- // rename table of DynInsts. Also these likely shouldn't be called very
- // often, other than when adding things into the xc during say a syscall.
-
- uint64_t readIntReg(StaticInst *si, int idx)
- {
- return xc->readIntReg(si->srcRegIdx(idx));
+ error = this->mem->read(req, data);
+ data = gtoh(data);
+ return error;
}
- FloatReg readFloatReg(StaticInst *si, int idx, width)
- {
- int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return xc->readFloatReg(reg_idx, width);
- }
- FloatReg readFloatReg(StaticInst *si, int idx)
+ /** CPU read function, forwards read to LSQ. */
+ template <class T>
+ Fault read(MemReqPtr &req, T &data, int load_idx)
{
- int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return xc->readFloatReg(reg_idx);
+ return backEnd->read(req, data, load_idx);
}
- FloatRegBits readFloatRegBits(StaticInst *si, int idx, int width)
+ /** Old CPU write to memory function. No longer used. */
+ template <class T>
+ Fault write(MemReqPtr &req, T &data)
{
- int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return xc->readFloatRegBits(reg_idx, width);
- }
+#if 0
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
+ ExecContext *xc;
+
+ // If this is a store conditional, act appropriately
+ if (req->flags & LOCKED) {
+ xc = req->xc;
+
+ if (req->flags & UNCACHEABLE) {
+ // Don't update result register (see stq_c in isa_desc)
+ req->result = 2;
+ xc->setStCondFailures(0);//Needed? [RGD]
+ } else {
+ bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
+ Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
+ req->result = lock_flag;
+ if (!lock_flag ||
+ ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
+ xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
+ xc->setStCondFailures(xc->readStCondFailures() + 1);
+ if (((xc->readStCondFailures()) % 100000) == 0) {
+ std::cerr << "Warning: "
+ << xc->readStCondFailures()
+ << " consecutive store conditional failures "
+ << "on cpu " << req->xc->readCpuId()
+ << std::endl;
+ }
+ return NoFault;
+ }
+ else xc->setStCondFailures(0);
+ }
+ }
- FloatRegBits readFloatRegBits(StaticInst *si, int idx)
- {
- int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
- return xc->readFloatRegBits(reg_idx);
- }
+ // Need to clear any locked flags on other proccessors for
+ // this address. Only do this for succsful Store Conditionals
+ // and all other stores (WH64?). Unsuccessful Store
+ // Conditionals would have returned above, and wouldn't fall
+ // through.
+ for (int i = 0; i < this->system->execContexts.size(); i++){
+ xc = this->system->execContexts[i];
+ if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
+ (req->paddr & ~0xf)) {
+ xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
+ }
+ }
- void setIntReg(StaticInst *si, int idx, uint64_t val)
- {
- xc->setIntReg(si->destRegIdx(idx), val);
- }
+#endif
+#endif
- void setFloatReg(StaticInst *si, int idx, FloatReg val, int width)
- {
- int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- xc->setFloatReg(reg_idx, val, width);
- }
+ if (req->flags & LOCKED) {
+ if (req->flags & UNCACHEABLE) {
+ req->result = 2;
+ } else {
+ if (this->lockFlag) {
+ if (lockAddrList.find(req->paddr) !=
+ lockAddrList.end()) {
+ req->result = 1;
+ } else {
+ req->result = 0;
+ return NoFault;
+ }
+ } else {
+ req->result = 0;
+ return NoFault;
+ }
+ }
+ }
- void setFloatReg(StaticInst *si, int idx, FloatReg val)
- {
- int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- xc->setFloatReg(reg_idx, val);
+ return this->mem->write(req, (T)htog(data));
}
- void setFloatRegBits(StaticInst *si, int idx, FloatRegBits val, int width)
+ /** CPU write function, forwards write to LSQ. */
+ template <class T>
+ Fault write(MemReqPtr &req, T &data, int store_idx)
{
- int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- xc->setFloatRegBits(reg_idx, val, width);
+ return backEnd->write(req, data, store_idx);
}
- void setFloatRegBits(StaticInst *si, int idx, FloatRegBits val)
+ void prefetch(Addr addr, unsigned flags)
{
- int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
- xc->setFloatRegBits(reg_idx, val);
+ // need to do this...
}
- uint64_t readPC() { return PC; }
- void setNextPC(Addr val) { nextPC = val; }
-
- private:
- Addr PC;
- Addr nextPC;
-
- unsigned issueWidth;
-
- bool fetchRedirExcp;
- bool fetchRedirBranch;
-
- /** Mask to get a cache block's address. */
- Addr cacheBlkMask;
-
- unsigned cacheBlkSize;
-
- Addr cacheBlkPC;
-
- /** The cache line being fetched. */
- uint8_t *cacheData;
-
- protected:
- bool cacheBlkValid;
-
- private:
-
- // Align an address (typically a PC) to the start of an I-cache block.
- // We fold in the PISA 64- to 32-bit conversion here as well.
- Addr icacheBlockAlignPC(Addr addr)
+ void writeHint(Addr addr, int size, unsigned flags)
{
- addr = TheISA::realPCToFetchPC(addr);
- return (addr & ~(cacheBlkMask));
+ // need to do this...
}
- unsigned instSize;
+ Fault copySrcTranslate(Addr src);
- // ROB tracking stuff.
- DynInstPtr robHeadPtr;
- DynInstPtr robTailPtr;
- unsigned robSize;
- unsigned robInsts;
+ Fault copy(Addr dest);
- // List of outstanding EA instructions.
- protected:
- EAList eaList;
+ InstSeqNum globalSeqNum;
public:
- void branchToTarget(Addr val)
- {
- if (!fetchRedirExcp) {
- fetchRedirBranch = true;
- PC = val;
- }
- }
-
- // ISA stuff:
- uint64_t readUniq() { return xc->readUniq(); }
- void setUniq(uint64_t val) { xc->setUniq(val); }
+ void squashFromXC();
- uint64_t readFpcr() { return xc->readFpcr(); }
- void setFpcr(uint64_t val) { xc->setFpcr(val); }
+ // @todo: This can be a useful debug function. Implement it.
+ void dumpInsts() { frontEnd->dumpInsts(); }
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
- Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
- Fault hwrei() { return xc->hwrei(); }
- int readIntrFlag() { return xc->readIntrFlag(); }
- void setIntrFlag(int val) { xc->setIntrFlag(val); }
- bool inPalMode() { return xc->inPalMode(); }
- void trap(Fault fault) { fault->invoke(xc); }
- bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
+ Fault hwrei();
+ int readIntrFlag() { return thread.regs.intrflag; }
+ void setIntrFlag(int val) { thread.regs.intrflag = val; }
+ bool inPalMode() { return AlphaISA::PcPAL(thread.PC); }
+ bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); }
+ bool simPalCheck(int palFunc);
+ void processInterrupts();
#else
- void syscall() { xc->syscall(); }
-#endif
-
- ExecContext *xcBase() { return xc; }
-};
-
-
-// precise architected memory state accessor macros
-template <class Impl>
-template <class T>
-Fault
-OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
-{
- MemReqPtr readReq = new MemReq();
- readReq->xc = xc;
- readReq->asid = 0;
- readReq->data = new uint8_t[64];
-
- readReq->reset(addr, sizeof(T), flags);
-
- // translate to physical address - This might be an ISA impl call
- Fault fault = translateDataReadReq(readReq);
-
- // do functional access
- if (fault == NoFault)
- fault = xc->mem->read(readReq, data);
-#if 0
- if (traceData) {
- traceData->setAddr(addr);
- if (fault == NoFault)
- traceData->setData(data);
- }
+ void syscall();
+ void setSyscallReturn(SyscallReturn return_value, int tid);
#endif
- // if we have a cache, do cache access too
- if (fault == NoFault && dcacheInterface) {
- readReq->cmd = Read;
- readReq->completionEvent = NULL;
- readReq->time = curTick;
- /*MemAccessResult result = */dcacheInterface->access(readReq);
+ ExecContext *xcBase() { return xcProxy; }
- if (dcacheInterface->doEvents()) {
- readReq->completionEvent = new DCacheCompletionEvent(this, inst,
- dcceIt);
- }
- }
-
- if (!dcacheInterface && (readReq->flags & UNCACHEABLE))
- recordEvent("Uncached Read");
-
- return fault;
-}
-
-template <class Impl>
-template <class T>
-Fault
-OoOCPU<Impl>::write(T data, Addr addr, unsigned flags,
- uint64_t *res, DynInstPtr inst)
-{
- MemReqPtr writeReq = new MemReq();
- writeReq->xc = xc;
- writeReq->asid = 0;
- writeReq->data = new uint8_t[64];
+ bool decoupledFrontEnd;
+ struct CommStruct {
+ InstSeqNum doneSeqNum;
+ InstSeqNum nonSpecSeqNum;
+ bool uncached;
+ unsigned lqIdx;
-#if 0
- if (traceData) {
- traceData->setAddr(addr);
- traceData->setData(data);
- }
-#endif
-
- writeReq->reset(addr, sizeof(T), flags);
-
- // translate to physical address
- Fault fault = translateDataWriteReq(writeReq);
-
- // do functional access
- if (fault == NoFault)
- fault = xc->write(writeReq, data);
-
- if (fault == NoFault && dcacheInterface) {
- writeReq->cmd = Write;
- memcpy(writeReq->data,(uint8_t *)&data,writeReq->size);
- writeReq->completionEvent = NULL;
- writeReq->time = curTick;
- /*MemAccessResult result = */dcacheInterface->access(writeReq);
-
- if (dcacheInterface->doEvents()) {
- writeReq->completionEvent = new DCacheCompletionEvent(this, inst,
- dcceIt);
- }
- }
-
- if (res && (fault == NoFault))
- *res = writeReq->result;
+ bool stall;
+ };
+ TimeBuffer<CommStruct> comm;
- if (!dcacheInterface && (writeReq->flags & UNCACHEABLE))
- recordEvent("Uncached Write");
+ bool lockFlag;
- return fault;
-}
+ Stats::Scalar<> quiesceCycles;
+ Checker<DynInstPtr> *checker;
+};
-#endif // __CPU_OOO_CPU_OOO_CPU_HH__
+#endif // __CPU_OZONE_CPU_HH__
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index e7ed3cfe0..5675da3a8 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -26,23 +26,1024 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __CPU_OOO_CPU_OOO_IMPL_HH__
-#define __CPU_OOO_CPU_OOO_IMPL_HH__
+//#include <cstdio>
+//#include <cstdlib>
-#include "arch/isa_traits.hh"
+#include "arch/isa_traits.hh" // For MachInst
+#include "base/trace.hh"
+#include "config/full_system.hh"
+#include "cpu/base.hh"
+#include "cpu/checker/exec_context.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/exetrace.hh"
+#include "cpu/ozone/cpu.hh"
+#include "cpu/quiesce_event.hh"
+#include "cpu/static_inst.hh"
+//#include "mem/base_mem.hh"
+#include "mem/mem_interface.hh"
+#include "sim/sim_object.hh"
+#include "sim/stats.hh"
+
+#if FULL_SYSTEM
+#include "arch/faults.hh"
+#include "arch/alpha/osfpal.hh"
+#include "arch/alpha/tlb.hh"
+#include "arch/vtophys.hh"
+#include "base/callback.hh"
+//#include "base/remote_gdb.hh"
+#include "cpu/profile.hh"
+#include "kern/kernel_stats.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
+#include "sim/faults.hh"
+#include "sim/sim_events.hh"
+#include "sim/sim_exit.hh"
+#include "sim/system.hh"
+#else // !FULL_SYSTEM
+#include "mem/functional/functional.hh"
+#include "sim/process.hh"
+#endif // FULL_SYSTEM
+
+using namespace TheISA;
+
+template <class Impl>
+template<typename T>
+void
+OzoneCPU<Impl>::trace_data(T data) {
+ if (traceData) {
+ traceData->setData(data);
+ }
+}
+
+template <class Impl>
+OzoneCPU<Impl>::TickEvent::TickEvent(OzoneCPU *c, int w)
+ : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
+{
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::TickEvent::process()
+{
+ cpu->tick();
+}
+
+template <class Impl>
+const char *
+OzoneCPU<Impl>::TickEvent::description()
+{
+ return "OzoneCPU tick event";
+}
+
+template <class Impl>
+OzoneCPU<Impl>::OzoneCPU(Params *p)
+#if FULL_SYSTEM
+ : BaseCPU(p), thread(this, 0, p->mem), tickEvent(this, p->width),
+ mem(p->mem),
+#else
+ : BaseCPU(p), thread(this, 0, p->workload[0], 0), tickEvent(this, p->width),
+ mem(p->workload[0]->getMemory()),
+#endif
+ comm(5, 5)
+{
+ frontEnd = new FrontEnd(p);
+ backEnd = new BackEnd(p);
+
+ _status = Idle;
+
+ if (p->checker) {
+ BaseCPU *temp_checker = p->checker;
+ checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
+ checker->setMemory(mem);
+#if FULL_SYSTEM
+ checker->setSystem(p->system);
+#endif
+ checkerXC = new CheckerExecContext<OzoneXC>(&ozoneXC, checker);
+ thread.xcProxy = checkerXC;
+ xcProxy = checkerXC;
+ } else {
+ checker = NULL;
+ thread.xcProxy = &ozoneXC;
+ xcProxy = &ozoneXC;
+ }
+
+ ozoneXC.cpu = this;
+ ozoneXC.thread = &thread;
+
+ thread.inSyscall = false;
+
+ thread.setStatus(ExecContext::Suspended);
+#if FULL_SYSTEM
+ /***** All thread state stuff *****/
+ thread.cpu = this;
+ thread.tid = 0;
+ thread.mem = p->mem;
+
+ thread.quiesceEvent = new EndQuiesceEvent(xcProxy);
+
+ system = p->system;
+ itb = p->itb;
+ dtb = p->dtb;
+ memctrl = p->system->memctrl;
+ physmem = p->system->physmem;
+
+ if (p->profile) {
+ thread.profile = new FunctionProfile(p->system->kernelSymtab);
+ // @todo: This might be better as an ExecContext instead of OzoneXC
+ Callback *cb =
+ new MakeCallback<OzoneXC,
+ &OzoneXC::dumpFuncProfile>(&ozoneXC);
+ registerExitCallback(cb);
+ }
+
+ // let's fill with a dummy node for now so we don't get a segfault
+ // on the first cycle when there's no node available.
+ static ProfileNode dummyNode;
+ thread.profileNode = &dummyNode;
+ thread.profilePC = 3;
+#else
+ thread.cpu = this;
+ thread.tid = 0;
+ thread.process = p->workload[0];
+ thread.asid = 0;
+#endif // !FULL_SYSTEM
+
+ numInst = 0;
+ startNumInst = 0;
+
+ execContexts.push_back(xcProxy);
+
+ frontEnd->setCPU(this);
+ backEnd->setCPU(this);
+
+ frontEnd->setXC(xcProxy);
+ backEnd->setXC(xcProxy);
+
+ frontEnd->setThreadState(&thread);
+ backEnd->setThreadState(&thread);
+
+ frontEnd->setCommBuffer(&comm);
+ backEnd->setCommBuffer(&comm);
+
+ frontEnd->setBackEnd(backEnd);
+ backEnd->setFrontEnd(frontEnd);
+
+ decoupledFrontEnd = p->decoupledFrontEnd;
+
+ globalSeqNum = 1;
+
+ checkInterrupts = false;
+
+ for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
+ thread.renameTable[i] = new DynInst(this);
+ thread.renameTable[i]->setResultReady();
+ }
+
+ frontEnd->renameTable.copyFrom(thread.renameTable);
+ backEnd->renameTable.copyFrom(thread.renameTable);
+
+#if !FULL_SYSTEM
+// pTable = p->pTable;
+#endif
+
+ lockFlag = 0;
+
+ DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
+}
+
+template <class Impl>
+OzoneCPU<Impl>::~OzoneCPU()
+{
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::switchOut(Sampler *_sampler)
+{
+ sampler = _sampler;
+ switchCount = 0;
+ // Front end needs state from back end, so switch out the back end first.
+ backEnd->switchOut();
+ frontEnd->switchOut();
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::signalSwitched()
+{
+ if (++switchCount == 2) {
+ backEnd->doSwitchOut();
+ frontEnd->doSwitchOut();
+ if (checker)
+ checker->switchOut(sampler);
+ _status = SwitchedOut;
+ if (tickEvent.scheduled())
+ tickEvent.squash();
+ sampler->signalSwitched();
+ }
+ assert(switchCount <= 2);
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
+{
+ BaseCPU::takeOverFrom(oldCPU);
+
+ backEnd->takeOverFrom();
+ frontEnd->takeOverFrom();
+ assert(!tickEvent.scheduled());
+
+ // @todo: Fix hardcoded number
+ // Clear out any old information in time buffer.
+ for (int i = 0; i < 6; ++i) {
+ comm.advance();
+ }
+
+ // if any of this CPU's ExecContexts are active, mark the CPU as
+ // running and schedule its tick event.
+ for (int i = 0; i < execContexts.size(); ++i) {
+ ExecContext *xc = execContexts[i];
+ if (xc->status() == ExecContext::Active &&
+ _status != Running) {
+ _status = Running;
+ tickEvent.schedule(curTick);
+ }
+ }
+ // Nothing running, change status to reflect that we're no longer
+ // switched out.
+ if (_status == SwitchedOut) {
+ _status = Idle;
+ }
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::activateContext(int thread_num, int delay)
+{
+ // Eventually change this in SMT.
+ assert(thread_num == 0);
+
+ assert(_status == Idle);
+ notIdleFraction++;
+ scheduleTickEvent(delay);
+ _status = Running;
+ thread._status = ExecContext::Active;
+ frontEnd->wakeFromQuiesce();
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::suspendContext(int thread_num)
+{
+ // Eventually change this in SMT.
+ assert(thread_num == 0);
+ // @todo: Figure out how to initially set the status properly so
+ // this is running.
+// assert(_status == Running);
+ notIdleFraction--;
+ unscheduleTickEvent();
+ _status = Idle;
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::deallocateContext(int thread_num)
+{
+ // for now, these are equivalent
+ suspendContext(thread_num);
+}
template <class Impl>
-class OoOCPU;
+void
+OzoneCPU<Impl>::haltContext(int thread_num)
+{
+ // for now, these are equivalent
+ suspendContext(thread_num);
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::regStats()
+{
+ using namespace Stats;
+
+ BaseCPU::regStats();
+
+ thread.numInsts
+ .name(name() + ".num_insts")
+ .desc("Number of instructions executed")
+ ;
+
+ thread.numMemRefs
+ .name(name() + ".num_refs")
+ .desc("Number of memory references")
+ ;
+
+ notIdleFraction
+ .name(name() + ".not_idle_fraction")
+ .desc("Percentage of non-idle cycles")
+ ;
+
+ idleFraction
+ .name(name() + ".idle_fraction")
+ .desc("Percentage of idle cycles")
+ ;
+
+ quiesceCycles
+ .name(name() + ".quiesce_cycles")
+ .desc("Number of cycles spent in quiesce")
+ ;
+
+ idleFraction = constant(1.0) - notIdleFraction;
+
+ frontEnd->regStats();
+ backEnd->regStats();
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::resetStats()
+{
+ startNumInst = numInst;
+ notIdleFraction = (_status != Idle);
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::init()
+{
+ BaseCPU::init();
+
+ // Mark this as in syscall so it won't need to squash
+ thread.inSyscall = true;
+#if FULL_SYSTEM
+ for (int i = 0; i < execContexts.size(); ++i) {
+ ExecContext *xc = execContexts[i];
+
+ // initialize CPU, including PC
+ TheISA::initCPU(xc, xc->readCpuId());
+ }
+#endif
+ frontEnd->renameTable.copyFrom(thread.renameTable);
+ backEnd->renameTable.copyFrom(thread.renameTable);
+
+ thread.inSyscall = false;
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::serialize(std::ostream &os)
+{
+ BaseCPU::serialize(os);
+ SERIALIZE_ENUM(_status);
+ nameOut(os, csprintf("%s.xc", name()));
+ ozoneXC.serialize(os);
+ nameOut(os, csprintf("%s.tickEvent", name()));
+ tickEvent.serialize(os);
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
+{
+ BaseCPU::unserialize(cp, section);
+ UNSERIALIZE_ENUM(_status);
+ ozoneXC.unserialize(cp, csprintf("%s.xc", section));
+ tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
+}
+
+template <class Impl>
+Fault
+OzoneCPU<Impl>::copySrcTranslate(Addr src)
+{
+ panic("Copy not implemented!\n");
+ return NoFault;
+#if 0
+ static bool no_warn = true;
+ int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
+ // Only support block sizes of 64 atm.
+ assert(blk_size == 64);
+ int offset = src & (blk_size - 1);
+
+ // Make sure block doesn't span page
+ if (no_warn &&
+ (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
+ (src >> 40) != 0xfffffc) {
+ warn("Copied block source spans pages %x.", src);
+ no_warn = false;
+ }
+
+ memReq->reset(src & ~(blk_size - 1), blk_size);
+
+ // translate to physical address
+ Fault fault = xc->translateDataReadReq(memReq);
+
+ assert(fault != Alignment_Fault);
+
+ if (fault == NoFault) {
+ xc->copySrcAddr = src;
+ xc->copySrcPhysAddr = memReq->paddr + offset;
+ } else {
+ xc->copySrcAddr = 0;
+ xc->copySrcPhysAddr = 0;
+ }
+ return fault;
+#endif
+}
+
+template <class Impl>
+Fault
+OzoneCPU<Impl>::copy(Addr dest)
+{
+ panic("Copy not implemented!\n");
+ return NoFault;
+#if 0
+ static bool no_warn = true;
+ int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
+ // Only support block sizes of 64 atm.
+ assert(blk_size == 64);
+ uint8_t data[blk_size];
+ //assert(xc->copySrcAddr);
+ int offset = dest & (blk_size - 1);
+
+ // Make sure block doesn't span page
+ if (no_warn &&
+ (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
+ (dest >> 40) != 0xfffffc) {
+ no_warn = false;
+ warn("Copied block destination spans pages %x. ", dest);
+ }
+
+ memReq->reset(dest & ~(blk_size -1), blk_size);
+ // translate to physical address
+ Fault fault = xc->translateDataWriteReq(memReq);
+
+ assert(fault != Alignment_Fault);
+
+ if (fault == NoFault) {
+ Addr dest_addr = memReq->paddr + offset;
+ // Need to read straight from memory since we have more than 8 bytes.
+ memReq->paddr = xc->copySrcPhysAddr;
+ xc->mem->read(memReq, data);
+ memReq->paddr = dest_addr;
+ xc->mem->write(memReq, data);
+ if (dcacheInterface) {
+ memReq->cmd = Copy;
+ memReq->completionEvent = NULL;
+ memReq->paddr = xc->copySrcPhysAddr;
+ memReq->dest = dest_addr;
+ memReq->size = 64;
+ memReq->time = curTick;
+ dcacheInterface->access(memReq);
+ }
+ }
+ return fault;
+#endif
+}
+
+#if FULL_SYSTEM
+template <class Impl>
+Addr
+OzoneCPU<Impl>::dbg_vtophys(Addr addr)
+{
+ return vtophys(xcProxy, addr);
+}
+#endif // FULL_SYSTEM
+
+#if FULL_SYSTEM
+template <class Impl>
+void
+OzoneCPU<Impl>::post_interrupt(int int_num, int index)
+{
+ BaseCPU::post_interrupt(int_num, index);
+
+ if (_status == Idle) {
+ DPRINTF(IPI,"Suspended Processor awoke\n");
+// thread.activate();
+ // Hack for now. Otherwise might have to go through the xcProxy, or
+ // I need to figure out what's the right thing to call.
+ activateContext(thread.tid, 1);
+ }
+}
+#endif // FULL_SYSTEM
+
+/* start simulation, program loaded, processor precise state initialized */
+template <class Impl>
+void
+OzoneCPU<Impl>::tick()
+{
+ DPRINTF(OzoneCPU, "\n\nOzoneCPU: Ticking cpu.\n");
+
+ _status = Running;
+ thread.renameTable[ZeroReg]->setIntResult(0);
+ thread.renameTable[ZeroReg+TheISA::FP_Base_DepTag]->
+ setDoubleResult(0.0);
+
+ comm.advance();
+ frontEnd->tick();
+ backEnd->tick();
+
+ // check for instruction-count-based events
+ comInstEventQueue[0]->serviceEvents(numInst);
+
+ if (!tickEvent.scheduled() && _status == Running)
+ tickEvent.schedule(curTick + cycles(1));
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::squashFromXC()
+{
+ thread.inSyscall = true;
+ backEnd->generateXCEvent();
+}
+
+#if !FULL_SYSTEM
+template <class Impl>
+void
+OzoneCPU<Impl>::syscall()
+{
+ // Not sure this copy is needed, depending on how the XC proxy is made.
+ thread.renameTable.copyFrom(backEnd->renameTable);
+
+ thread.inSyscall = true;
+
+ thread.funcExeInst++;
+
+ DPRINTF(OzoneCPU, "FuncExeInst: %i\n", thread.funcExeInst);
+
+ thread.process->syscall(xcProxy);
+
+ thread.funcExeInst--;
+
+ thread.inSyscall = false;
+
+ frontEnd->renameTable.copyFrom(thread.renameTable);
+ backEnd->renameTable.copyFrom(thread.renameTable);
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
+{
+ // check for error condition. Alpha syscall convention is to
+ // indicate success/failure in reg a3 (r19) and put the
+ // return value itself in the standard return value reg (v0).
+ if (return_value.successful()) {
+ // no error
+ thread.renameTable[SyscallSuccessReg]->setIntResult(0);
+ thread.renameTable[ReturnValueReg]->setIntResult(
+ return_value.value());
+ } else {
+ // got an error, return details
+ thread.renameTable[SyscallSuccessReg]->setIntResult((IntReg) -1);
+ thread.renameTable[ReturnValueReg]->setIntResult(
+ -return_value.value());
+ }
+}
+#else
+template <class Impl>
+Fault
+OzoneCPU<Impl>::hwrei()
+{
+ // Need to move this to ISA code
+ // May also need to make this per thread
+
+ lockFlag = false;
+ lockAddrList.clear();
+ thread.kernelStats->hwrei();
+
+ checkInterrupts = true;
+
+ // FIXME: XXX check for interrupts? XXX
+ return NoFault;
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::processInterrupts()
+{
+ // Check for interrupts here. For now can copy the code that
+ // exists within isa_fullsys_traits.hh. Also assume that thread 0
+ // is the one that handles the interrupts.
+
+ // Check if there are any outstanding interrupts
+ //Handle the interrupts
+ int ipl = 0;
+ int summary = 0;
+
+ checkInterrupts = false;
+
+ if (thread.readMiscReg(IPR_ASTRR))
+ panic("asynchronous traps not implemented\n");
+
+ if (thread.readMiscReg(IPR_SIRR)) {
+ for (int i = INTLEVEL_SOFTWARE_MIN;
+ i < INTLEVEL_SOFTWARE_MAX; i++) {
+ if (thread.readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+ // See table 4-19 of the 21164 hardware reference
+ ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
+ summary |= (ULL(1) << i);
+ }
+ }
+ }
+
+ uint64_t interrupts = intr_status();
+
+ if (interrupts) {
+ for (int i = INTLEVEL_EXTERNAL_MIN;
+ i < INTLEVEL_EXTERNAL_MAX; i++) {
+ if (interrupts & (ULL(1) << i)) {
+ // See table 4-19 of the 21164 hardware reference
+ ipl = i;
+ summary |= (ULL(1) << i);
+ }
+ }
+ }
+
+ if (ipl && ipl > thread.readMiscReg(IPR_IPLR)) {
+ thread.setMiscReg(IPR_ISR, summary);
+ thread.setMiscReg(IPR_INTID, ipl);
+ // @todo: Make this more transparent
+ if (checker) {
+ checker->cpuXCBase()->setMiscReg(IPR_ISR, summary);
+ checker->cpuXCBase()->setMiscReg(IPR_INTID, ipl);
+ }
+ Fault fault = new InterruptFault;
+ fault->invoke(thread.getXCProxy());
+ DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
+ thread.readMiscReg(IPR_IPLR), ipl, summary);
+ }
+}
+
+template <class Impl>
+bool
+OzoneCPU<Impl>::simPalCheck(int palFunc)
+{
+ // Need to move this to ISA code
+ // May also need to make this per thread
+ thread.kernelStats->callpal(palFunc, xcProxy);
+
+ switch (palFunc) {
+ case PAL::halt:
+ haltContext(thread.tid);
+ if (--System::numSystemsRunning == 0)
+ new SimExitEvent("all cpus halted");
+ break;
+
+ case PAL::bpt:
+ case PAL::bugchk:
+ if (system->breakpoint())
+ return false;
+ break;
+ }
+
+ return true;
+}
+#endif
+
+template <class Impl>
+BaseCPU *
+OzoneCPU<Impl>::OzoneXC::getCpuPtr()
+{
+ return cpu;
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::setCpuId(int id)
+{
+ cpu->cpuId = id;
+ thread->cpuId = id;
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::setStatus(Status new_status)
+{
+ thread->_status = new_status;
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::activate(int delay)
+{
+ cpu->activateContext(thread->tid, delay);
+}
+
+/// Set the status to Suspended.
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::suspend()
+{
+ cpu->suspendContext(thread->tid);
+}
+
+/// Set the status to Unallocated.
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::deallocate()
+{
+ cpu->deallocateContext(thread->tid);
+}
+
+/// Set the status to Halted.
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::halt()
+{
+ cpu->haltContext(thread->tid);
+}
+
+#if FULL_SYSTEM
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::dumpFuncProfile()
+{ }
+#endif
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::takeOverFrom(ExecContext *old_context)
+{
+ // some things should already be set up
+ assert(getMemPtr() == old_context->getMemPtr());
+#if FULL_SYSTEM
+ assert(getSystemPtr() == old_context->getSystemPtr());
+#else
+ assert(getProcessPtr() == old_context->getProcessPtr());
+#endif
+
+ // copy over functional state
+ setStatus(old_context->status());
+ copyArchRegs(old_context);
+ setCpuId(old_context->readCpuId());
+
+#if !FULL_SYSTEM
+ setFuncExeInst(old_context->readFuncExeInst());
+#else
+ EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
+ if (other_quiesce) {
+ // Point the quiesce event's XC at this XC so that it wakes up
+ // the proper CPU.
+ other_quiesce->xc = this;
+ }
+ if (thread->quiesceEvent) {
+ thread->quiesceEvent->xc = this;
+ }
+
+ thread->kernelStats = old_context->getKernelStats();
+// storeCondFailures = 0;
+ cpu->lockFlag = false;
+#endif
+
+ old_context->setStatus(ExecContext::Unallocated);
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::regStats(const std::string &name)
+{
+#if FULL_SYSTEM
+ thread->kernelStats = new Kernel::Statistics(cpu->system);
+ thread->kernelStats->regStats(name + ".kern");
+#endif
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::serialize(std::ostream &os)
+{ }
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::unserialize(Checkpoint *cp, const std::string &section)
+{ }
+
+#if FULL_SYSTEM
+template <class Impl>
+EndQuiesceEvent *
+OzoneCPU<Impl>::OzoneXC::getQuiesceEvent()
+{
+ return thread->quiesceEvent;
+}
+
+template <class Impl>
+Tick
+OzoneCPU<Impl>::OzoneXC::readLastActivate()
+{
+ return thread->lastActivate;
+}
+
+template <class Impl>
+Tick
+OzoneCPU<Impl>::OzoneXC::readLastSuspend()
+{
+ return thread->lastSuspend;
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::profileClear()
+{
+ if (thread->profile)
+ thread->profile->clear();
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::profileSample()
+{
+ if (thread->profile)
+ thread->profile->sample(thread->profileNode, thread->profilePC);
+}
+#endif
+
+template <class Impl>
+int
+OzoneCPU<Impl>::OzoneXC::getThreadNum()
+{
+ return thread->tid;
+}
+
+// Also somewhat obnoxious. Really only used for the TLB fault.
+template <class Impl>
+TheISA::MachInst
+OzoneCPU<Impl>::OzoneXC::getInst()
+{
+ return thread->inst;
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::copyArchRegs(ExecContext *xc)
+{
+ thread->PC = xc->readPC();
+ thread->nextPC = xc->readNextPC();
+
+ cpu->frontEnd->setPC(thread->PC);
+ cpu->frontEnd->setNextPC(thread->nextPC);
+
+ for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
+ if (i < TheISA::FP_Base_DepTag) {
+ thread->renameTable[i]->setIntResult(xc->readIntReg(i));
+ } else if (i < (TheISA::FP_Base_DepTag + TheISA::NumFloatRegs)) {
+ int fp_idx = i - TheISA::FP_Base_DepTag;
+ thread->renameTable[i]->setDoubleResult(
+ xc->readFloatRegDouble(fp_idx));
+ }
+ }
+
+#if !FULL_SYSTEM
+ thread->funcExeInst = xc->readFuncExeInst();
+#endif
+
+ // Need to copy the XC values into the current rename table,
+ // copy the misc regs.
+ thread->regs.miscRegs.copyMiscRegs(xc);
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::clearArchRegs()
+{
+ panic("Unimplemented!");
+}
+
+template <class Impl>
+uint64_t
+OzoneCPU<Impl>::OzoneXC::readIntReg(int reg_idx)
+{
+ return thread->renameTable[reg_idx]->readIntResult();
+}
+
+template <class Impl>
+float
+OzoneCPU<Impl>::OzoneXC::readFloatRegSingle(int reg_idx)
+{
+ int idx = reg_idx + TheISA::FP_Base_DepTag;
+ return thread->renameTable[idx]->readFloatResult();
+}
+
+template <class Impl>
+double
+OzoneCPU<Impl>::OzoneXC::readFloatRegDouble(int reg_idx)
+{
+ int idx = reg_idx + TheISA::FP_Base_DepTag;
+ return thread->renameTable[idx]->readDoubleResult();
+}
+
+template <class Impl>
+uint64_t
+OzoneCPU<Impl>::OzoneXC::readFloatRegInt(int reg_idx)
+{
+ int idx = reg_idx + TheISA::FP_Base_DepTag;
+ return thread->renameTable[idx]->readIntResult();
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::setIntReg(int reg_idx, uint64_t val)
+{
+ thread->renameTable[reg_idx]->setIntResult(val);
+
+ if (!thread->inSyscall) {
+ cpu->squashFromXC();
+ }
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::setFloatRegSingle(int reg_idx, float val)
+{
+ panic("Unimplemented!");
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::setFloatRegDouble(int reg_idx, double val)
+{
+ int idx = reg_idx + TheISA::FP_Base_DepTag;
+
+ thread->renameTable[idx]->setDoubleResult(val);
+
+ if (!thread->inSyscall) {
+ cpu->squashFromXC();
+ }
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::setFloatRegInt(int reg_idx, uint64_t val)
+{
+ panic("Unimplemented!");
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::setPC(Addr val)
+{
+ thread->PC = val;
+ cpu->frontEnd->setPC(val);
+
+ if (!thread->inSyscall) {
+ cpu->squashFromXC();
+ }
+}
+
+template <class Impl>
+void
+OzoneCPU<Impl>::OzoneXC::setNextPC(Addr val)
+{
+ thread->nextPC = val;
+ cpu->frontEnd->setNextPC(val);
+
+ if (!thread->inSyscall) {
+ cpu->squashFromXC();
+ }
+}
+
+template <class Impl>
+TheISA::MiscReg
+OzoneCPU<Impl>::OzoneXC::readMiscReg(int misc_reg)
+{
+ return thread->regs.miscRegs.readReg(misc_reg);
+}
+
+template <class Impl>
+TheISA::MiscReg
+OzoneCPU<Impl>::OzoneXC::readMiscRegWithEffect(int misc_reg, Fault &fault)
+{
+ return thread->regs.miscRegs.readRegWithEffect(misc_reg,
+ fault, this);
+}
+
+template <class Impl>
+Fault
+OzoneCPU<Impl>::OzoneXC::setMiscReg(int misc_reg, const MiscReg &val)
+{
+ // Needs to setup a squash event unless we're in syscall mode
+ Fault ret_fault = thread->regs.miscRegs.setReg(misc_reg, val);
+
+ if (!thread->inSyscall) {
+ cpu->squashFromXC();
+ }
+
+ return ret_fault;
+}
template <class Impl>
-class OoODynInst;
+Fault
+OzoneCPU<Impl>::OzoneXC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+{
+ // Needs to setup a squash event unless we're in syscall mode
+ Fault ret_fault = thread->regs.miscRegs.setRegWithEffect(misc_reg, val,
+ this);
-struct OoOImpl {
- typedef AlphaISA ISA;
- typedef OoOCPU<OoOImpl> OoOCPU;
- typedef OoOCPU FullCPU;
- typedef OoODynInst<OoOImpl> DynInst;
- typedef RefCountingPtr<DynInst> DynInstPtr;
-};
+ if (!thread->inSyscall) {
+ cpu->squashFromXC();
+ }
-#endif // __CPU_OOO_CPU_OOO_IMPL_HH__
+ return ret_fault;
+}
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 33c9144fb..803b7a09b 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -41,6 +41,8 @@
// forward declarations
struct AlphaSimpleImpl;
+struct OzoneImpl;
+struct SimpleImpl;
class ExecContext;
class DynInst;
class Packet;
@@ -48,6 +50,10 @@ class Packet;
template <class Impl>
class AlphaDynInst;
+template <class Impl>
+class OzoneDynInst;
+
+class CheckerCPU;
class FastCPU;
class AtomicSimpleCPU;
class TimingSimpleCPU;
@@ -100,6 +106,7 @@ class StaticInstBase : public RefCounted
IsMemRef, ///< References memory (load, store, or prefetch).
IsLoad, ///< Reads from memory (load or prefetch).
IsStore, ///< Writes to memory.
+ IsStoreConditional, ///< Store conditional instruction.
IsInstPrefetch, ///< Instruction-cache prefetch.
IsDataPrefetch, ///< Data-cache prefetch.
IsCopy, ///< Fast Cache block copy
@@ -124,6 +131,10 @@ class StaticInstBase : public RefCounted
IsWriteBarrier, ///< Is a write barrier
IsNonSpeculative, ///< Should not be executed speculatively
+ IsQuiesce, ///< Is a quiesce instruction
+
+ IsIprAccess, ///< Accesses IPRs
+ IsUnverifiable, ///< Can't be verified by a checker
NumFlags
};
@@ -187,6 +198,7 @@ class StaticInstBase : public RefCounted
bool isMemRef() const { return flags[IsMemRef]; }
bool isLoad() const { return flags[IsLoad]; }
bool isStore() const { return flags[IsStore]; }
+ bool isStoreConditional() const { return flags[IsStoreConditional]; }
bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
bool isCopy() const { return flags[IsCopy];}
@@ -211,6 +223,9 @@ class StaticInstBase : public RefCounted
bool isMemBarrier() const { return flags[IsMemBarrier]; }
bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
+ bool isQuiesce() const { return flags[IsQuiesce]; }
+ bool isIprAccess() const { return flags[IsIprAccess]; }
+ bool isUnverifiable() const { return flags[IsUnverifiable]; }
//@}
/// Operation class. Used to select appropriate function unit in issue.
diff --git a/src/kern/system_events.cc b/src/kern/system_events.cc
index fd5c12e44..f3b1bf91d 100644
--- a/src/kern/system_events.cc
+++ b/src/kern/system_events.cc
@@ -71,15 +71,17 @@ FnEvent::process(ExecContext *xc)
void
IdleStartEvent::process(ExecContext *xc)
{
- xc->getCpuPtr()->kernelStats->setIdleProcess(
- xc->readMiscReg(AlphaISA::IPR_PALtemp23), xc);
+ if (xc->getKernelStats())
+ xc->getKernelStats()->setIdleProcess(
+ xc->readMiscReg(AlphaISA::IPR_PALtemp23), xc);
remove();
}
void
InterruptStartEvent::process(ExecContext *xc)
{
- xc->getCpuPtr()->kernelStats->mode(Kernel::interrupt, xc);
+ if (xc->getKernelStats())
+ xc->getKernelStats()->mode(Kernel::interrupt, xc);
}
void
@@ -87,5 +89,6 @@ InterruptEndEvent::process(ExecContext *xc)
{
// We go back to kernel, if we are user, inside the rti
// pal code we will get switched to user because of the ICM write
- xc->getCpuPtr()->kernelStats->mode(Kernel::kernel, xc);
+ if (xc->getKernelStats())
+ xc->getKernelStats()->mode(Kernel::kernel, xc);
}
diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh
index 91db5bb84..fff91f8ca 100644
--- a/src/kern/tru64/tru64.hh
+++ b/src/kern/tru64/tru64.hh
@@ -922,7 +922,7 @@ class Tru64 {
for (int i = 0; i < process->numCpus(); ++i) {
ExecContext *xc = process->execContexts[i];
- if (xc->status() == ExecContext::Unallocated) {
+ if (xc->status() == ExecContext::Suspended) {
// inactive context... grab it
init_exec_context(xc, attrp, uniq_val);
diff --git a/src/python/m5/objects/AlphaFullCPU.py b/src/python/m5/objects/AlphaFullCPU.py
index 48989d057..d719bf783 100644
--- a/src/python/m5/objects/AlphaFullCPU.py
+++ b/src/python/m5/objects/AlphaFullCPU.py
@@ -3,12 +3,16 @@ from BaseCPU import BaseCPU
class DerivAlphaFullCPU(BaseCPU):
type = 'DerivAlphaFullCPU'
-
+ activity = Param.Unsigned("Initial count")
numThreads = Param.Unsigned("number of HW thread contexts")
if not build_env['FULL_SYSTEM']:
mem = Param.FunctionalMemory(NULL, "memory")
+ checker = Param.BaseCPU(NULL, "checker")
+
+ cachePorts = Param.Unsigned("Cache Ports")
+
decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
@@ -41,22 +45,25 @@ class DerivAlphaFullCPU(BaseCPU):
executeFloatWidth = Param.Unsigned("Floating point execute width")
executeBranchWidth = Param.Unsigned("Branch execute width")
executeMemoryWidth = Param.Unsigned("Memory execute width")
+ fuPool = Param.FUPool(NULL, "Functional Unit pool")
iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
"delay")
renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
commitWidth = Param.Unsigned("Commit width")
squashWidth = Param.Unsigned("Squash width")
+ trapLatency = Param.Tick("Trap latency")
+ fetchTrapLatency = Param.Tick("Fetch trap latency")
- local_predictor_size = Param.Unsigned("Size of local predictor")
- local_ctr_bits = Param.Unsigned("Bits per counter")
- local_history_table_size = Param.Unsigned("Size of local history table")
- local_history_bits = Param.Unsigned("Bits for the local history")
- global_predictor_size = Param.Unsigned("Size of global predictor")
- global_ctr_bits = Param.Unsigned("Bits per counter")
- global_history_bits = Param.Unsigned("Bits of history")
- choice_predictor_size = Param.Unsigned("Size of choice predictor")
- choice_ctr_bits = Param.Unsigned("Bits of choice counters")
+ localPredictorSize = Param.Unsigned("Size of local predictor")
+ localCtrBits = Param.Unsigned("Bits per counter")
+ localHistoryTableSize = Param.Unsigned("Size of local history table")
+ localHistoryBits = Param.Unsigned("Bits for the local history")
+ globalPredictorSize = Param.Unsigned("Size of global predictor")
+ globalCtrBits = Param.Unsigned("Bits per counter")
+ globalHistoryBits = Param.Unsigned("Bits of history")
+ choicePredictorSize = Param.Unsigned("Size of choice predictor")
+ choiceCtrBits = Param.Unsigned("Bits of choice counters")
BTBEntries = Param.Unsigned("Number of BTB entries")
BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
@@ -68,6 +75,8 @@ class DerivAlphaFullCPU(BaseCPU):
LFSTSize = Param.Unsigned("Last fetched store table size")
SSITSize = Param.Unsigned("Store set ID table size")
+ numRobs = Param.Unsigned("Number of Reorder Buffers");
+
numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
"registers")
@@ -78,3 +87,13 @@ class DerivAlphaFullCPU(BaseCPU):
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
+
+ smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads")
+ smtFetchPolicy = Param.String("SMT Fetch policy")
+ smtLSQPolicy = Param.String("SMT LSQ Sharing Policy")
+ smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter")
+ smtIQPolicy = Param.String("SMT IQ Sharing Policy")
+ smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter")
+ smtROBPolicy = Param.String("SMT ROB Sharing Policy")
+ smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter")
+ smtCommitPolicy = Param.String("SMT Commit Policy")
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 7897b5c8b..12c076c08 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -37,6 +37,7 @@
#include "cpu/base.hh"
#include "cpu/sampler/sampler.hh"
#include "cpu/exec_context.hh"
+#include "cpu/quiesce_event.hh"
#include "kern/kernel_stats.hh"
#include "sim/param.hh"
#include "sim/serialize.hh"
@@ -63,7 +64,8 @@ namespace AlphaPseudo
void
arm(ExecContext *xc)
{
- xc->getCpuPtr()->kernelStats->arm();
+ if (xc->getKernelStats())
+ xc->getKernelStats()->arm();
}
void
@@ -73,7 +75,8 @@ namespace AlphaPseudo
return;
xc->suspend();
- xc->getCpuPtr()->kernelStats->quiesce();
+ if (xc->getKernelStats())
+ xc->getKernelStats()->quiesce();
}
void
@@ -82,7 +85,7 @@ namespace AlphaPseudo
if (!doQuiesce || ns == 0)
return;
- Event *quiesceEvent = xc->getQuiesceEvent();
+ EndQuiesceEvent *quiesceEvent = xc->getQuiesceEvent();
if (quiesceEvent->scheduled())
quiesceEvent->reschedule(curTick + Clock::Int::ns * ns);
@@ -90,7 +93,8 @@ namespace AlphaPseudo
quiesceEvent->schedule(curTick + Clock::Int::ns * ns);
xc->suspend();
- xc->getCpuPtr()->kernelStats->quiesce();
+ if (xc->getKernelStats())
+ xc->getKernelStats()->quiesce();
}
void
@@ -99,7 +103,7 @@ namespace AlphaPseudo
if (!doQuiesce || cycles == 0)
return;
- Event *quiesceEvent = xc->getQuiesceEvent();
+ EndQuiesceEvent *quiesceEvent = xc->getQuiesceEvent();
if (quiesceEvent->scheduled())
quiesceEvent->reschedule(curTick +
@@ -109,7 +113,8 @@ namespace AlphaPseudo
xc->getCpuPtr()->cycles(cycles));
xc->suspend();
- xc->getCpuPtr()->kernelStats->quiesce();
+ if (xc->getKernelStats())
+ xc->getKernelStats()->quiesce();
}
uint64_t
@@ -121,7 +126,8 @@ namespace AlphaPseudo
void
ivlb(ExecContext *xc)
{
- xc->getCpuPtr()->kernelStats->ivlb();
+ if (xc->getKernelStats())
+ xc->getKernelStats()->ivlb();
}
void