diff options
| -rw-r--r-- | src/arch/alpha/isa_traits.hh | 4 | ||||
| -rw-r--r-- | src/arch/arm/isa_traits.hh | 3 | ||||
| -rw-r--r-- | src/arch/mips/isa_traits.hh | 3 | ||||
| -rw-r--r-- | src/arch/power/isa_traits.hh | 3 | ||||
| -rw-r--r-- | src/arch/riscv/isa_traits.hh | 2 | ||||
| -rw-r--r-- | src/arch/sparc/isa_traits.hh | 3 | ||||
| -rw-r--r-- | src/arch/x86/isa_traits.hh | 17 |
7 files changed, 0 insertions, 35 deletions
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh index f1c39cb05..54b8003be 100644 --- a/src/arch/alpha/isa_traits.hh +++ b/src/arch/alpha/isa_traits.hh @@ -111,10 +111,6 @@ enum mode_type const int MachineBytes = 8; -// return a no-op instruction... used for instruction fetch faults -// Alpha UNOP (ldq_u r31,0(r0)) -const ExtMachInst NoopMachInst = 0x2ffe0000; - // Memory accesses cannot be unaligned const bool HasUnalignedMemAcc = false; diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh index 8be2bf04a..fa2779558 100644 --- a/src/arch/arm/isa_traits.hh +++ b/src/arch/arm/isa_traits.hh @@ -96,9 +96,6 @@ namespace ArmISA // Max. physical address range in bits supported by the architecture const unsigned MaxPhysAddrRange = 48; - // return a no-op instruction... used for instruction fetch faults - const ExtMachInst NoopMachInst = 0x01E320F000ULL; - const int MachineBytes = 4; const uint32_t HighVecs = 0xFFFF0000; diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index ca375f2e8..7a1607183 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -142,9 +142,6 @@ enum mode_type mode_number // number of modes }; -// return a no-op instruction... used for instruction fetch faults -const ExtMachInst NoopMachInst = 0x00000000; - const int ANNOTE_NONE = 0; const uint32_t ITOUCH_ANNOTE = 0xffffffff; diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh index 3abc831ff..41a8d7d1b 100644 --- a/src/arch/power/isa_traits.hh +++ b/src/arch/power/isa_traits.hh @@ -63,9 +63,6 @@ const Addr PteMask = NPtePage - 1; const int MachineBytes = 4; -// This is ori 0, 0, 0 -const ExtMachInst NoopMachInst = 0x60000000; - // Memory accesses can be unaligned const bool HasUnalignedMemAcc = true; diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh index 327d64498..21e684a25 100644 --- a/src/arch/riscv/isa_traits.hh +++ b/src/arch/riscv/isa_traits.hh @@ -63,8 +63,6 @@ using namespace LittleEndianGuest; const Addr PageShift = 12; const Addr PageBytes = ULL(1) << PageShift; -const ExtMachInst NoopMachInst = 0x00000013; - // Memory accesses can be unaligned (at least for double-word memory accesses) const bool HasUnalignedMemAcc = true; diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index b9253863e..4f98f7580 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -47,9 +47,6 @@ using namespace BigEndianGuest; // SPARC has a delay slot #define ISA_HAS_DELAY_SLOT 1 -// SPARC NOP (sethi %(hi(0), g0) -const MachInst NoopMachInst = 0x01000000; - // real address virtual mapping // sort of like alpha super page, but less frequently used const Addr SegKPMEnd = ULL(0xfffffffc00000000); diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh index 88cd16eff..2b19b1ba7 100644 --- a/src/arch/x86/isa_traits.hh +++ b/src/arch/x86/isa_traits.hh @@ -56,10 +56,6 @@ namespace X86ISA // X86 does not have a delay slot #define ISA_HAS_DELAY_SLOT 0 - // X86 NOP (XCHG rAX, rAX) - //XXX This needs to be set to an intermediate instruction struct - //which encodes this instruction - const Addr PageShift = 12; const Addr PageBytes = ULL(1) << PageShift; @@ -68,19 +64,6 @@ namespace X86ISA const bool CurThreadInfoImplemented = false; const int CurThreadInfoReg = -1; - - const ExtMachInst NoopMachInst M5_VAR_USED = { - 0x0, // No legacy prefixes. - 0x0, // No rex prefix. - 0x0, // No two / three byte escape sequence - { OneByteOpcode, 0x90 }, // One opcode byte, 0x90. - 0x0, 0x0, // No modrm or sib. - 0, 0, // No immediate or displacement. - 8, 8, 8, // All sizes are 8. - 0, // Displacement size is 0. - SixtyFourBitMode // Behave as if we're in 64 bit - // mode (this doesn't actually matter). - }; } #endif // __ARCH_X86_ISATRAITS_HH__ |