diff options
127 files changed, 1701 insertions, 1684 deletions
diff --git a/src/arch/alpha/arguments.cc b/src/arch/alpha/arguments.cc index f19ed7ff7..9f9002003 100644 --- a/src/arch/alpha/arguments.cc +++ b/src/arch/alpha/arguments.cc @@ -30,7 +30,7 @@ #include "arch/alpha/arguments.hh" #include "arch/alpha/vtophys.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "mem/vport.hh" using namespace AlphaISA; @@ -56,14 +56,14 @@ AlphaArguments::getArg(bool fp) { if (number < 6) { if (fp) - return xc->readFloatRegBits(16 + number); + return tc->readFloatRegBits(16 + number); else - return xc->readIntReg(16 + number); + return tc->readIntReg(16 + number); } else { - Addr sp = xc->readIntReg(30); - VirtualPort *vp = xc->getVirtPort(xc); + Addr sp = tc->readIntReg(30); + VirtualPort *vp = tc->getVirtPort(tc); uint64_t arg = vp->read<uint64_t>(sp + (number-6) * sizeof(uint64_t)); - xc->delVirtPort(vp); + tc->delVirtPort(vp); return arg; } } diff --git a/src/arch/alpha/arguments.hh b/src/arch/alpha/arguments.hh index 11a67f3d4..d977d48d6 100644 --- a/src/arch/alpha/arguments.hh +++ b/src/arch/alpha/arguments.hh @@ -37,14 +37,14 @@ #include "base/refcnt.hh" #include "sim/host.hh" -class ExecContext; +class ThreadContext; namespace AlphaISA { class AlphaArguments { protected: - ExecContext *xc; + ThreadContext *tc; int number; uint64_t getArg(bool fp = false); @@ -65,17 +65,17 @@ class AlphaArguments RefCountingPtr<Data> data; public: - AlphaArguments(ExecContext *ctx, int n = 0) - : xc(ctx), number(n), data(NULL) + AlphaArguments(ThreadContext *ctx, int n = 0) + : tc(ctx), number(n), data(NULL) { assert(number >= 0); data = new Data;} AlphaArguments(const AlphaArguments &args) - : xc(args.xc), number(args.number), data(args.data) {} + : tc(args.tc), number(args.number), data(args.data) {} ~AlphaArguments() {} - ExecContext *getExecContext() const { return xc; } + ThreadContext *getThreadContext() const { return tc; } const AlphaArguments &operator=(const AlphaArguments &args) { - xc = args.xc; + tc = args.tc; number = args.number; data = args.data; return *this; @@ -120,7 +120,7 @@ class AlphaArguments } AlphaArguments operator[](int index) { - return AlphaArguments(xc, index); + return AlphaArguments(tc, index); } template <class T> @@ -133,13 +133,13 @@ class AlphaArguments template <class T> operator T *() { T *buf = (T *)data->alloc(sizeof(T)); - CopyData(xc, buf, getArg(), sizeof(T)); + CopyData(tc, buf, getArg(), sizeof(T)); return buf; } operator char *() { char *buf = data->alloc(2048); - CopyStringOut(xc, buf, getArg(), 2048); + CopyStringOut(tc, buf, getArg(), 2048); return buf; } }; diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc index 5be185002..50ce6b78a 100644 --- a/src/arch/alpha/ev5.cc +++ b/src/arch/alpha/ev5.cc @@ -38,7 +38,7 @@ #include "config/full_system.hh" #include "cpu/base.hh" #include "cpu/cpu_exec_context.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/kernel_stats.hh" #include "sim/debug.hh" #include "sim/sim_events.hh" @@ -52,15 +52,15 @@ using namespace EV5; // Machine dependent functions // void -AlphaISA::initCPU(ExecContext *xc, int cpuId) +AlphaISA::initCPU(ThreadContext *tc, int cpuId) { - initIPRs(xc, cpuId); + initIPRs(tc, cpuId); - xc->setIntReg(16, cpuId); - xc->setIntReg(0, cpuId); + tc->setIntReg(16, cpuId); + tc->setIntReg(0, cpuId); - xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect()); - xc->setNextPC(xc->readPC() + sizeof(MachInst)); + tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect()); + tc->setNextPC(tc->readPC() + sizeof(MachInst)); } //////////////////////////////////////////////////////////////////////// @@ -68,15 +68,15 @@ AlphaISA::initCPU(ExecContext *xc, int cpuId) // // void -AlphaISA::initIPRs(ExecContext *xc, int cpuId) +AlphaISA::initIPRs(ThreadContext *tc, int cpuId) { for (int i = 0; i < NumInternalProcRegs; ++i) { - xc->setMiscReg(i, 0); + tc->setMiscReg(i, 0); } - xc->setMiscReg(IPR_PAL_BASE, PalBase); - xc->setMiscReg(IPR_MCSR, 0x6); - xc->setMiscReg(IPR_PALtemp16, cpuId); + tc->setMiscReg(IPR_PAL_BASE, PalBase); + tc->setMiscReg(IPR_MCSR, 0x6); + tc->setMiscReg(IPR_PALtemp16, cpuId); } @@ -171,7 +171,7 @@ AlphaISA::MiscRegFile::getDataAsid() } AlphaISA::MiscReg -AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc) +AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc) { uint64_t retval = 0; // return value, default 0 @@ -225,7 +225,7 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc) case AlphaISA::IPR_CC: retval |= ipr[idx] & ULL(0xffffffff00000000); - retval |= xc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); + retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); break; case AlphaISA::IPR_VA: @@ -242,7 +242,7 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc) case AlphaISA::IPR_DTB_PTE: { - AlphaISA::PTE &pte = xc->getDTBPtr()->index(!xc->misspeculating()); + AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating()); retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32; retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8; @@ -282,11 +282,11 @@ int break_ipl = -1; #endif Fault -AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) +AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc) { uint64_t old; - if (xc->misspeculating()) + if (tc->misspeculating()) return NoFault; switch (idx) { @@ -339,8 +339,8 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) // write entire quad w/ no side-effect old = ipr[idx]; ipr[idx] = val; - if (xc->getKernelStats()) - xc->getKernelStats()->context(old, val, xc); + if (tc->getKernelStats()) + tc->getKernelStats()->context(old, val, tc); break; case AlphaISA::IPR_DTB_PTE: @@ -367,17 +367,17 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) // only write least significant five bits - interrupt level ipr[idx] = val & 0x1f; - if (xc->getKernelStats()) - xc->getKernelStats()->swpipl(ipr[idx]); + if (tc->getKernelStats()) + tc->getKernelStats()->swpipl(ipr[idx]); break; case AlphaISA::IPR_DTB_CM: if (val & 0x18) { - if (xc->getKernelStats()) - xc->getKernelStats()->mode(Kernel::user, xc); + if (tc->getKernelStats()) + tc->getKernelStats()->mode(Kernel::user, tc); } else { - if (xc->getKernelStats()) - xc->getKernelStats()->mode(Kernel::kernel, xc); + if (tc->getKernelStats()) + tc->getKernelStats()->mode(Kernel::kernel, tc); } case AlphaISA::IPR_ICM: @@ -452,21 +452,21 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) // really a control write ipr[idx] = 0; - xc->getDTBPtr()->flushAll(); + tc->getDTBPtr()->flushAll(); break; case AlphaISA::IPR_DTB_IAP: // really a control write ipr[idx] = 0; - xc->getDTBPtr()->flushProcesses(); + tc->getDTBPtr()->flushProcesses(); break; case AlphaISA::IPR_DTB_IS: // really a control write ipr[idx] = val; - xc->getDTBPtr()->flushAddr(val, + tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN])); break; @@ -490,7 +490,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]); // insert new TAG/PTE value into data TLB - xc->getDTBPtr()->insert(val, pte); + tc->getDTBPtr()->insert(val, pte); } break; @@ -514,7 +514,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]); // insert new TAG/PTE value into data TLB - xc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); + tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte); } break; @@ -522,21 +522,21 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) // really a control write ipr[idx] = 0; - xc->getITBPtr()->flushAll(); + tc->getITBPtr()->flushAll(); break; case AlphaISA::IPR_ITB_IAP: // really a control write ipr[idx] = 0; - xc->getITBPtr()->flushProcesses(); + tc->getITBPtr()->flushProcesses(); break; case AlphaISA::IPR_ITB_IS: // really a control write ipr[idx] = val; - xc->getITBPtr()->flushAddr(val, + tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN])); break; @@ -550,7 +550,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) } void -AlphaISA::copyIprs(ExecContext *src, ExecContext *dest) +AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest) { for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) { dest->setMiscReg(i, src->readMiscReg(i)); @@ -565,7 +565,7 @@ bool CPUExecContext::simPalCheck(int palFunc) { if (kernelStats) - kernelStats->callpal(palFunc, proxy); + kernelStats->callpal(palFunc, tc); switch (palFunc) { case PAL::halt: diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc index 88084bf86..8493223ff 100644 --- a/src/arch/alpha/faults.cc +++ b/src/arch/alpha/faults.cc @@ -30,7 +30,7 @@ */ #include "arch/alpha/faults.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/base.hh" #include "base/trace.hh" #if FULL_SYSTEM @@ -110,67 +110,67 @@ FaultStat IntegerOverflowFault::_count; #if FULL_SYSTEM -void AlphaFault::invoke(ExecContext * xc) +void AlphaFault::invoke(ThreadContext * tc) { - FaultBase::invoke(xc); + FaultBase::invoke(tc); countStat()++; // exception restart address - if (setRestartAddress() || !xc->inPalMode()) - xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->readPC()); + if (setRestartAddress() || !tc->inPalMode()) + tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC()); if (skipFaultingInstruction()) { // traps... skip faulting instruction. - xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, - xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); + tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, + tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); } - xc->setPC(xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect()); - xc->setNextPC(xc->readPC() + sizeof(MachInst)); + tc->setPC(tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect()); + tc->setNextPC(tc->readPC() + sizeof(MachInst)); } -void ArithmeticFault::invoke(ExecContext * xc) +void ArithmeticFault::invoke(ThreadContext * tc) { - FaultBase::invoke(xc); + FaultBase::invoke(tc); panic("Arithmetic traps are unimplemented!"); } -void DtbFault::invoke(ExecContext * xc) +void DtbFault::invoke(ThreadContext * tc) { // Set fault address and flags. Even though we're modeling an // EV5, we use the EV6 technique of not latching fault registers // on VPTE loads (instead of locking the registers until IPR_VA is // read, like the EV5). The EV6 approach is cleaner and seems to // work with EV5 PAL code, but not the other way around. - if (!xc->misspeculating() + if (!tc->misspeculating() && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) { // set VA register with faulting address - xc->setMiscReg(AlphaISA::IPR_VA, vaddr); + tc->setMiscReg(AlphaISA::IPR_VA, vaddr); // set MM_STAT register flags - xc->setMiscReg(AlphaISA::IPR_MM_STAT, - (((EV5::Opcode(xc->getInst()) & 0x3f) << 11) - | ((EV5::Ra(xc->getInst()) & 0x1f) << 6) + tc->setMiscReg(AlphaISA::IPR_MM_STAT, + (((EV5::Opcode(tc->getInst()) & 0x3f) << 11) + | ((EV5::Ra(tc->getInst()) & 0x1f) << 6) | (flags & 0x3f))); // set VA_FORM register with faulting formatted address - xc->setMiscReg(AlphaISA::IPR_VA_FORM, - xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3)); + tc->setMiscReg(AlphaISA::IPR_VA_FORM, + tc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3)); } - AlphaFault::invoke(xc); + AlphaFault::invoke(tc); } -void ItbFault::invoke(ExecContext * xc) +void ItbFault::invoke(ThreadContext * tc) { - if (!xc->misspeculating()) { - xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc); - xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM, - xc->readMiscReg(AlphaISA::IPR_IVPTBR) | + if (!tc->misspeculating()) { + tc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc); + tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM, + tc->readMiscReg(AlphaISA::IPR_IVPTBR) | (AlphaISA::VAddr(pc).vpn() << 3)); } - AlphaFault::invoke(xc); + AlphaFault::invoke(tc); } #endif diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh index 0d60367f7..f952cf9d6 100644 --- a/src/arch/alpha/faults.hh +++ b/src/arch/alpha/faults.hh @@ -49,7 +49,7 @@ class AlphaFault : public FaultBase virtual bool setRestartAddress() {return true;} public: #if FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif virtual FaultVect vect() = 0; virtual FaultStat & countStat() = 0; @@ -116,7 +116,7 @@ class ArithmeticFault : public AlphaFault FaultVect vect() {return _vect;} FaultStat & countStat() {return _count;} #if FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif }; @@ -150,7 +150,7 @@ class DtbFault : public AlphaFault FaultVect vect() = 0; FaultStat & countStat() = 0; #if FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif }; @@ -251,7 +251,7 @@ class ItbFault : public AlphaFault FaultVect vect() = 0; FaultStat & countStat() = 0; #if FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif }; diff --git a/src/arch/alpha/freebsd/system.cc b/src/arch/alpha/freebsd/system.cc index 2781fed3d..91f8b5af1 100644 --- a/src/arch/alpha/freebsd/system.cc +++ b/src/arch/alpha/freebsd/system.cc @@ -38,7 +38,7 @@ #include "arch/alpha/system.hh" #include "arch/alpha/freebsd/system.hh" #include "base/loader/symtab.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "mem/physical.hh" #include "mem/port.hh" #include "arch/isa_traits.hh" @@ -72,13 +72,13 @@ FreebsdAlphaSystem::~FreebsdAlphaSystem() void -FreebsdAlphaSystem::doCalibrateClocks(ExecContext *xc) +FreebsdAlphaSystem::doCalibrateClocks(ThreadContext *tc) { Addr ppc_vaddr = 0; Addr timer_vaddr = 0; - ppc_vaddr = (Addr)xc->readIntReg(ArgumentReg1); - timer_vaddr = (Addr)xc->readIntReg(ArgumentReg2); + ppc_vaddr = (Addr)tc->readIntReg(ArgumentReg1); + timer_vaddr = (Addr)tc->readIntReg(ArgumentReg2); virtPort.write(ppc_vaddr, (uint32_t)Clock::Frequency); virtPort.write(timer_vaddr, (uint32_t)TIMER_FREQUENCY); @@ -86,10 +86,10 @@ FreebsdAlphaSystem::doCalibrateClocks(ExecContext *xc) void -FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ExecContext *xc) +FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ThreadContext *tc) { - SkipFuncEvent::process(xc); - ((FreebsdAlphaSystem *)xc->getSystemPtr())->doCalibrateClocks(xc); + SkipFuncEvent::process(tc); + ((FreebsdAlphaSystem *)tc->getSystemPtr())->doCalibrateClocks(tc); } diff --git a/src/arch/alpha/freebsd/system.hh b/src/arch/alpha/freebsd/system.hh index 46a5e665c..e0d874e8f 100644 --- a/src/arch/alpha/freebsd/system.hh +++ b/src/arch/alpha/freebsd/system.hh @@ -42,7 +42,7 @@ class FreebsdAlphaSystem : public AlphaSystem SkipCalibrateClocksEvent(PCEventQueue *q, const std::string &desc, Addr addr) : SkipFuncEvent(q, desc, addr) {} - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; SkipFuncEvent *skipDelayEvent; @@ -51,7 +51,7 @@ class FreebsdAlphaSystem : public AlphaSystem public: FreebsdAlphaSystem(Params *p); ~FreebsdAlphaSystem(); - void doCalibrateClocks(ExecContext *xc); + void doCalibrateClocks(ThreadContext *tc); }; diff --git a/src/arch/alpha/isa/branch.isa b/src/arch/alpha/isa/branch.isa index aa7abf289..7438e7e18 100644 --- a/src/arch/alpha/isa/branch.isa +++ b/src/arch/alpha/isa/branch.isa @@ -106,7 +106,7 @@ output header {{ { } - Addr branchTarget(ExecContext *xc) const; + Addr branchTarget(ThreadContext *tc) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; @@ -121,10 +121,10 @@ output decoder {{ } Addr - Jump::branchTarget(ExecContext *xc) const + Jump::branchTarget(ThreadContext *tc) const { - Addr NPC = xc->readPC() + 4; - uint64_t Rb = xc->readIntReg(_srcRegIdx[0]); + Addr NPC = tc->readPC() + 4; + uint64_t Rb = tc->readIntReg(_srcRegIdx[0]); return (Rb & ~3) | (NPC & 1); } diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 6e19f2343..fab2ca2e1 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -765,56 +765,56 @@ decode OPCODE default Unknown::unknown() { // M5 special opcodes use the reserved 0x01 opcode space 0x01: decode M5FUNC { 0x00: arm({{ - AlphaPseudo::arm(xc->xcBase()); + AlphaPseudo::arm(xc->tcBase()); }}, IsNonSpeculative); 0x01: quiesce({{ - AlphaPseudo::quiesce(xc->xcBase()); + AlphaPseudo::quiesce(xc->tcBase()); }}, IsNonSpeculative, IsQuiesce); 0x02: quiesceNs({{ - AlphaPseudo::quiesceNs(xc->xcBase(), R16); + AlphaPseudo::quiesceNs(xc->tcBase(), R16); }}, IsNonSpeculative, IsQuiesce); 0x03: quiesceCycles({{ - AlphaPseudo::quiesceCycles(xc->xcBase(), R16); + AlphaPseudo::quiesceCycles(xc->tcBase(), R16); }}, IsNonSpeculative, IsQuiesce); 0x04: quiesceTime({{ - R0 = AlphaPseudo::quiesceTime(xc->xcBase()); + R0 = AlphaPseudo::quiesceTime(xc->tcBase()); }}, IsNonSpeculative); 0x10: ivlb({{ - AlphaPseudo::ivlb(xc->xcBase()); + AlphaPseudo::ivlb(xc->tcBase()); }}, No_OpClass, IsNonSpeculative); 0x11: ivle({{ - AlphaPseudo::ivle(xc->xcBase()); + AlphaPseudo::ivle(xc->tcBase()); }}, No_OpClass, IsNonSpeculative); 0x20: m5exit_old({{ - AlphaPseudo::m5exit_old(xc->xcBase()); + AlphaPseudo::m5exit_old(xc->tcBase()); }}, No_OpClass, IsNonSpeculative); 0x21: m5exit({{ - AlphaPseudo::m5exit(xc->xcBase(), R16); + AlphaPseudo::m5exit(xc->tcBase(), R16); }}, No_OpClass, IsNonSpeculative); - 0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }}); + 0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }}); 0x40: resetstats({{ - AlphaPseudo::resetstats(xc->xcBase(), R16, R17); + AlphaPseudo::resetstats(xc->tcBase(), R16, R17); }}, IsNonSpeculative); 0x41: dumpstats({{ - AlphaPseudo::dumpstats(xc->xcBase(), R16, R17); + AlphaPseudo::dumpstats(xc->tcBase(), R16, R17); }}, IsNonSpeculative); 0x42: dumpresetstats({{ - AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17); + AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17); }}, IsNonSpeculative); 0x43: m5checkpoint({{ - AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17); + AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17); }}, IsNonSpeculative); 0x50: m5readfile({{ - R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18); + R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18); }}, IsNonSpeculative); 0x51: m5break({{ - AlphaPseudo::debugbreak(xc->xcBase()); + AlphaPseudo::debugbreak(xc->tcBase()); }}, IsNonSpeculative); 0x52: m5switchcpu({{ - AlphaPseudo::switchcpu(xc->xcBase()); + AlphaPseudo::switchcpu(xc->tcBase()); }}, IsNonSpeculative); 0x53: m5addsymbol({{ - AlphaPseudo::addsymbol(xc->xcBase(), R16, R17); + AlphaPseudo::addsymbol(xc->tcBase(), R16, R17); }}, IsNonSpeculative); 0x54: m5panic({{ panic("M5 panic instruction called at pc=%#x.", xc->readPC()); diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index 91ece0935..1270bf8d8 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -56,7 +56,7 @@ output decoder {{ #include "base/fenv.hh" #include "base/loader/symtab.hh" #include "config/ss_compatible_fp.hh" -#include "cpu/exec_context.hh" // for Jump::branchTarget() +#include "cpu/thread_context.hh" // for Jump::branchTarget() #include <math.h> diff --git a/src/arch/alpha/linux/process.cc b/src/arch/alpha/linux/process.cc index abd17c224..997c78ac9 100644 --- a/src/arch/alpha/linux/process.cc +++ b/src/arch/alpha/linux/process.cc @@ -34,7 +34,7 @@ #include "arch/alpha/isa_traits.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/linux/linux.hh" #include "sim/process.hh" @@ -48,9 +48,9 @@ using namespace AlphaISA; /// Target uname() handler. static SyscallReturn unameFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0)); + TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0)); strcpy(name->sysname, "Linux"); strcpy(name->nodename, "m5.eecs.umich.edu"); @@ -58,7 +58,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); strcpy(name->machine, "alpha"); - name.copyOut(xc->getMemPort()); + name.copyOut(tc->getMemPort()); return 0; } @@ -67,18 +67,18 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, /// different in practice from those used by Tru64 processes. static SyscallReturn osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - unsigned op = xc->getSyscallArg(0); - // unsigned nbytes = xc->getSyscallArg(2); + unsigned op = tc->getSyscallArg(0); + // unsigned nbytes = tc->getSyscallArg(2); switch (op) { case 45: { // GSI_IEEE_FP_CONTROL - TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1)); // I don't think this exactly matches the HW FPCR *fpcr = 0; - fpcr.copyOut(xc->getMemPort()); + fpcr.copyOut(tc->getMemPort()); return 0; } @@ -94,17 +94,17 @@ osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, /// Target osf_setsysinfo() handler. static SyscallReturn osf_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - unsigned op = xc->getSyscallArg(0); - // unsigned nbytes = xc->getSyscallArg(2); + unsigned op = tc->getSyscallArg(0); + // unsigned nbytes = tc->getSyscallArg(2); switch (op) { case 14: { // SSI_IEEE_FP_CONTROL - TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1)); // I don't think this exactly matches the HW FPCR - fpcr.copyIn(xc->getMemPort()); + fpcr.copyIn(tc->getMemPort()); DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): " " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr)); return 0; diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc index f267e9d42..e6c6f42e9 100644 --- a/src/arch/alpha/linux/system.cc +++ b/src/arch/alpha/linux/system.cc @@ -46,7 +46,7 @@ #include "arch/alpha/linux/threadinfo.hh" #include "arch/alpha/system.hh" #include "base/loader/symtab.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/base.hh" #include "dev/platform.hh" #include "kern/linux/printk.hh" @@ -175,30 +175,30 @@ LinuxAlphaSystem::~LinuxAlphaSystem() void -LinuxAlphaSystem::setDelayLoop(ExecContext *xc) +LinuxAlphaSystem::setDelayLoop(ThreadContext *tc) { Addr addr = 0; if (kernelSymtab->findAddress("loops_per_jiffy", addr)) { - Tick cpuFreq = xc->getCpuPtr()->frequency(); + Tick cpuFreq = tc->getCpuPtr()->frequency(); Tick intrFreq = platform->intrFrequency(); - xc->getVirtPort(xc)->write(addr, + tc->getVirtPort(tc)->write(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988)); } } void -LinuxAlphaSystem::SkipDelayLoopEvent::process(ExecContext *xc) +LinuxAlphaSystem::SkipDelayLoopEvent::process(ThreadContext *tc) { - SkipFuncEvent::process(xc); + SkipFuncEvent::process(tc); // calculate and set loops_per_jiffy - ((LinuxAlphaSystem *)xc->getSystemPtr())->setDelayLoop(xc); + ((LinuxAlphaSystem *)tc->getSystemPtr())->setDelayLoop(tc); } void -LinuxAlphaSystem::PrintThreadInfo::process(ExecContext *xc) +LinuxAlphaSystem::PrintThreadInfo::process(ThreadContext *tc) { - Linux::ThreadInfo ti(xc); + Linux::ThreadInfo ti(tc); DPRINTF(Thread, "Currently Executing Thread %s, pid %d, started at: %d\n", ti.curTaskName(), ti.curTaskPID(), ti.curTaskStart()); diff --git a/src/arch/alpha/linux/system.hh b/src/arch/alpha/linux/system.hh index 46bf6ea91..c03586ac5 100644 --- a/src/arch/alpha/linux/system.hh +++ b/src/arch/alpha/linux/system.hh @@ -33,7 +33,7 @@ #ifndef __ARCH_ALPHA_LINUX_SYSTEM_HH__ #define __ARCH_ALPHA_LINUX_SYSTEM_HH__ -class ExecContext; +class ThreadContext; class BreakPCEvent; class IdleStartEvent; @@ -57,7 +57,7 @@ class LinuxAlphaSystem : public AlphaSystem public: SkipDelayLoopEvent(PCEventQueue *q, const std::string &desc, Addr addr) : SkipFuncEvent(q, desc, addr) {} - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; class PrintThreadInfo : public PCEvent @@ -65,7 +65,7 @@ class LinuxAlphaSystem : public AlphaSystem public: PrintThreadInfo(PCEventQueue *q, const std::string &desc, Addr addr) : PCEvent(q, desc, addr) {} - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; @@ -143,7 +143,7 @@ class LinuxAlphaSystem : public AlphaSystem LinuxAlphaSystem(Params *p); ~LinuxAlphaSystem(); - void setDelayLoop(ExecContext *xc); + void setDelayLoop(ThreadContext *tc); }; #endif // __ARCH_ALPHA_LINUX_SYSTEM_HH__ diff --git a/src/arch/alpha/linux/threadinfo.hh b/src/arch/alpha/linux/threadinfo.hh index 74444f427..caeb69f15 100644 --- a/src/arch/alpha/linux/threadinfo.hh +++ b/src/arch/alpha/linux/threadinfo.hh @@ -33,7 +33,7 @@ #define __ARCH_ALPHA_LINUX_LINUX_TREADNIFO_HH__ #include "arch/alpha/linux/thread_info.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/linux/sched.hh" #include "sim/vptr.hh" @@ -42,10 +42,10 @@ namespace Linux { class ThreadInfo { private: - ExecContext *xc; + ThreadContext *tc; public: - ThreadInfo(ExecContext *exec) : xc(exec) {} + ThreadInfo(ThreadContext *_tc) : tc(_tc) {} ~ThreadInfo() {} inline VPtr<thread_info> @@ -57,15 +57,15 @@ class ThreadInfo * thread_info struct. So we can get the address by masking off * the lower 14 bits. */ - current = xc->readIntReg(TheISA::StackPointerReg) & ~0x3fff; - return VPtr<thread_info>(xc, current); + current = tc->readIntReg(TheISA::StackPointerReg) & ~0x3fff; + return VPtr<thread_info>(tc, current); } inline VPtr<task_struct> curTaskInfo() { Addr task = curThreadInfo()->task; - return VPtr<task_struct>(xc, task); + return VPtr<task_struct>(tc, task); } std::string diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc index 490e04972..4c0c68761 100644 --- a/src/arch/alpha/process.cc +++ b/src/arch/alpha/process.cc @@ -35,7 +35,7 @@ #include "arch/alpha/tru64/process.hh" #include "base/loader/object_file.hh" #include "base/misc.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "sim/builder.hh" #include "sim/system.hh" @@ -107,7 +107,7 @@ AlphaLiveProcess::startup() { argsInit(MachineBytes, VMPageSize); - execContexts[0]->setIntReg(GlobalPointerReg, objFile->globalPointer()); + threadContexts[0]->setIntReg(GlobalPointerReg, objFile->globalPointer()); } diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index 2652144b6..ed410fddb 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -36,7 +36,7 @@ #include "sim/faults.hh" class Checkpoint; -class ExecContext; +class ThreadContext; namespace AlphaISA { @@ -90,7 +90,7 @@ namespace AlphaISA MiscReg readReg(int misc_reg); MiscReg readRegWithEffect(int misc_reg, Fault &fault, - ExecContext *xc); + ThreadContext *tc); //These functions should be removed once the simplescalar cpu model //has been replaced. @@ -100,7 +100,7 @@ namespace AlphaISA Fault setReg(int misc_reg, const MiscReg &val); Fault setRegWithEffect(int misc_reg, const MiscReg &val, - ExecContext *xc); + ThreadContext *tc); #if FULL_SYSTEM protected: @@ -109,9 +109,9 @@ namespace AlphaISA InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs private: - InternalProcReg readIpr(int idx, Fault &fault, ExecContext *xc); + InternalProcReg readIpr(int idx, Fault &fault, ThreadContext *tc); - Fault setIpr(int idx, InternalProcReg val, ExecContext *xc); + Fault setIpr(int idx, InternalProcReg val, ThreadContext *tc); #endif friend class RegFile; }; @@ -182,10 +182,10 @@ namespace AlphaISA } MiscReg readMiscRegWithEffect(int miscReg, - Fault &fault, ExecContext *xc) + Fault &fault, ThreadContext *tc) { fault = NoFault; - return miscRegFile.readRegWithEffect(miscReg, fault, xc); + return miscRegFile.readRegWithEffect(miscReg, fault, tc); } Fault setMiscReg(int miscReg, const MiscReg &val) @@ -194,9 +194,9 @@ namespace AlphaISA } Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, - ExecContext * xc) + ThreadContext * tc) { - return miscRegFile.setRegWithEffect(miscReg, val, xc); + return miscRegFile.setRegWithEffect(miscReg, val, tc); } FloatReg readFloatReg(int floatReg) @@ -268,12 +268,12 @@ namespace AlphaISA } }; - void copyRegs(ExecContext *src, ExecContext *dest); + void copyRegs(ThreadContext *src, ThreadContext *dest); - void copyMiscRegs(ExecContext *src, ExecContext *dest); + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); #if FULL_SYSTEM - void copyIprs(ExecContext *src, ExecContext *dest); + void copyIprs(ThreadContext *src, ThreadContext *dest); #endif } // namespace AlphaISA diff --git a/src/arch/alpha/stacktrace.cc b/src/arch/alpha/stacktrace.cc index 792b63e2f..3519fd940 100644 --- a/src/arch/alpha/stacktrace.cc +++ b/src/arch/alpha/stacktrace.cc @@ -36,36 +36,36 @@ #include "base/bitfield.hh" #include "base/trace.hh" #include "cpu/base.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "sim/system.hh" using namespace std; using namespace AlphaISA; -ProcessInfo::ProcessInfo(ExecContext *_xc) - : xc(_xc) +ProcessInfo::ProcessInfo(ThreadContext *_tc) + : tc(_tc) { Addr addr = 0; - if (!xc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr)) + if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr)) panic("thread info not compiled into kernel\n"); - thread_info_size = gtoh(xc->getVirtPort()->read<int32_t>(addr)); + thread_info_size = gtoh(tc->getVirtPort()->read<int32_t>(addr)); - if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr)) + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr)) panic("thread info not compiled into kernel\n"); - task_struct_size = gtoh(xc->getVirtPort()->read<int32_t>(addr)); + task_struct_size = gtoh(tc->getVirtPort()->read<int32_t>(addr)); - if (!xc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr)) + if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr)) panic("thread info not compiled into kernel\n"); - task_off = gtoh(xc->getVirtPort()->read<int32_t>(addr)); + task_off = gtoh(tc->getVirtPort()->read<int32_t>(addr)); - if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr)) + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr)) panic("thread info not compiled into kernel\n"); - pid_off = gtoh(xc->getVirtPort()->read<int32_t>(addr)); + pid_off = gtoh(tc->getVirtPort()->read<int32_t>(addr)); - if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr)) + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr)) panic("thread info not compiled into kernel\n"); - name_off = gtoh(xc->getVirtPort()->read<int32_t>(addr)); + name_off = gtoh(tc->getVirtPort()->read<int32_t>(addr)); } Addr @@ -75,7 +75,7 @@ ProcessInfo::task(Addr ksp) const if (base == ULL(0xfffffc0000000000)) return 0; - return gtoh(xc->getVirtPort()->read<Addr>(base + task_off)); + return gtoh(tc->getVirtPort()->read<Addr>(base + task_off)); } int @@ -85,7 +85,7 @@ ProcessInfo::pid(Addr ksp) const if (!task) return -1; - return gtoh(xc->getVirtPort()->read<uint16_t>(task + pid_off)); + return gtoh(tc->getVirtPort()->read<uint16_t>(task + pid_off)); } string @@ -96,7 +96,7 @@ ProcessInfo::name(Addr ksp) const return "console"; char comm[256]; - CopyStringOut(xc, comm, task + name_off, sizeof(comm)); + CopyStringOut(tc, comm, task + name_off, sizeof(comm)); if (!comm[0]) return "startup"; @@ -104,14 +104,14 @@ ProcessInfo::name(Addr ksp) const } StackTrace::StackTrace() - : xc(0), stack(64) + : tc(0), stack(64) { } -StackTrace::StackTrace(ExecContext *_xc, StaticInstPtr inst) - : xc(0), stack(64) +StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst) + : tc(0), stack(64) { - trace(_xc, inst); + trace(_tc, inst); } StackTrace::~StackTrace() @@ -119,15 +119,15 @@ StackTrace::~StackTrace() } void -StackTrace::trace(ExecContext *_xc, bool is_call) +StackTrace::trace(ThreadContext *_tc, bool is_call) { - xc = _xc; + tc = _tc; - bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; + bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; - Addr pc = xc->readNextPC(); - bool kernel = xc->getSystemPtr()->kernelStart <= pc && - pc <= xc->getSystemPtr()->kernelEnd; + Addr pc = tc->readNextPC(); + bool kernel = tc->getSystemPtr()->kernelStart <= pc && + pc <= tc->getSystemPtr()->kernelEnd; if (usermode) { stack.push_back(user); @@ -139,8 +139,8 @@ StackTrace::trace(ExecContext *_xc, bool is_call) return; } - SymbolTable *symtab = xc->getSystemPtr()->kernelSymtab; - Addr ksp = xc->readIntReg(TheISA::StackPointerReg); + SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; + Addr ksp = tc->readIntReg(TheISA::StackPointerReg); Addr bottom = ksp & ~0x3fff; Addr addr; @@ -149,7 +149,7 @@ StackTrace::trace(ExecContext *_xc, bool is_call) panic("could not find address %#x", pc); stack.push_back(addr); - pc = xc->readPC(); + pc = tc->readPC(); } Addr ra; @@ -181,8 +181,8 @@ StackTrace::trace(ExecContext *_xc, bool is_call) return; } - bool kernel = xc->getSystemPtr()->kernelStart <= pc && - pc <= xc->getSystemPtr()->kernelEnd; + bool kernel = tc->getSystemPtr()->kernelStart <= pc && + pc <= tc->getSystemPtr()->kernelEnd; if (!kernel) return; @@ -196,22 +196,22 @@ StackTrace::trace(ExecContext *_xc, bool is_call) bool StackTrace::isEntry(Addr addr) { - if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp12)) + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12)) return true; - if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp7)) + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7)) return true; - if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp11)) + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11)) return true; - if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp21)) + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21)) return true; - if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp9)) + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9)) return true; - if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp2)) + if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2)) return true; return false; @@ -296,7 +296,7 @@ StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) { MachInst inst; - CopyOut(xc, (uint8_t *)&inst, pc, sizeof(MachInst)); + CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst)); int reg, disp; if (decodeStack(inst, disp)) { @@ -307,7 +307,7 @@ StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, size += disp; } else if (decodeSave(inst, reg, disp)) { if (!ra && reg == ReturnAddressReg) { - CopyOut(xc, (uint8_t *)&ra, sp + disp, sizeof(Addr)); + CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr)); if (!ra) { // panic("no return address value pc=%#x\n", pc); return false; @@ -323,8 +323,8 @@ StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, void StackTrace::dump() { - StringWrap name(xc->getCpuPtr()->name()); - SymbolTable *symtab = xc->getSystemPtr()->kernelSymtab; + StringWrap name(tc->getCpuPtr()->name()); + SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; DPRINTFN("------ Stack ------\n"); diff --git a/src/arch/alpha/stacktrace.hh b/src/arch/alpha/stacktrace.hh index dd86a1553..d12aee211 100644 --- a/src/arch/alpha/stacktrace.hh +++ b/src/arch/alpha/stacktrace.hh @@ -34,13 +34,13 @@ #include "base/trace.hh" #include "cpu/static_inst.hh" -class ExecContext; +class ThreadContext; class StackTrace; class ProcessInfo { private: - ExecContext *xc; + ThreadContext *tc; int thread_info_size; int task_struct_size; @@ -49,7 +49,7 @@ class ProcessInfo int name_off; public: - ProcessInfo(ExecContext *_xc); + ProcessInfo(ThreadContext *_tc); Addr task(Addr ksp) const; int pid(Addr ksp) const; @@ -61,7 +61,7 @@ class StackTrace protected: typedef TheISA::MachInst MachInst; private: - ExecContext *xc; + ThreadContext *tc; std::vector<Addr> stack; private: @@ -70,21 +70,21 @@ class StackTrace bool decodeSave(MachInst inst, int ®, int &disp); bool decodeStack(MachInst inst, int &disp); - void trace(ExecContext *xc, bool is_call); + void trace(ThreadContext *tc, bool is_call); public: StackTrace(); - StackTrace(ExecContext *xc, StaticInstPtr inst); + StackTrace(ThreadContext *tc, StaticInstPtr inst); ~StackTrace(); void clear() { - xc = 0; + tc = 0; stack.clear(); } - bool valid() const { return xc != NULL; } - bool trace(ExecContext *xc, StaticInstPtr inst); + bool valid() const { return tc != NULL; } + bool trace(ThreadContext *tc, StaticInstPtr inst); public: const std::vector<Addr> &getstack() const { return stack; } @@ -106,7 +106,7 @@ class StackTrace }; inline bool -StackTrace::trace(ExecContext *xc, StaticInstPtr inst) +StackTrace::trace(ThreadContext *tc, StaticInstPtr inst) { if (!inst->isCall() && !inst->isReturn()) return false; @@ -114,7 +114,7 @@ StackTrace::trace(ExecContext *xc, StaticInstPtr inst) if (valid()) clear(); - trace(xc, !inst->isReturn()); + trace(tc, !inst->isReturn()); return true; } diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc index 0bcca1887..c6684274b 100644 --- a/src/arch/alpha/tlb.cc +++ b/src/arch/alpha/tlb.cc @@ -38,7 +38,7 @@ #include "base/str.hh" #include "base/trace.hh" #include "config/alpha_tlaser.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "sim/builder.hh" using namespace std; @@ -286,7 +286,7 @@ AlphaITB::regStats() Fault -AlphaITB::translate(RequestPtr &req, ExecContext *xc) const +AlphaITB::translate(RequestPtr &req, ThreadContext *tc) const { if (AlphaISA::PcPAL(req->getVaddr())) { // strip off PAL PC marker (lsb is 1) @@ -308,13 +308,13 @@ AlphaITB::translate(RequestPtr &req, ExecContext *xc) const // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 #if ALPHA_TLASER - if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && + if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && VAddrSpaceEV5(req->getVaddr()) == 2) { #else if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { #endif // only valid in kernel mode - if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) != + if (ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM)) != AlphaISA::mode_kernel) { acv++; return new ItbAcvFault(req->getVaddr()); @@ -332,7 +332,7 @@ AlphaITB::translate(RequestPtr &req, ExecContext *xc) const } else { // not a physical address: need to look up pte - int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN)); + int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN)); AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(), asn); @@ -347,7 +347,7 @@ AlphaITB::translate(RequestPtr &req, ExecContext *xc) const // check permissions for this access if (!(pte->xre & - (1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) { + (1 << ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM))))) { // instruction access fault acv++; return new ItbAcvFault(req->getVaddr()); @@ -443,12 +443,12 @@ AlphaDTB::regStats() } Fault -AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const +AlphaDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const { - Addr pc = xc->readPC(); + Addr pc = tc->readPC(); AlphaISA::mode_type mode = - (AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)); + (AlphaISA::mode_type)DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)); /** @@ -464,7 +464,7 @@ AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const if (pc & 0x1) { mode = (req->getFlags() & ALTMODE) ? (AlphaISA::mode_type)ALT_MODE_AM( - xc->readMiscReg(AlphaISA::IPR_ALT_MODE)) + tc->readMiscReg(AlphaISA::IPR_ALT_MODE)) : AlphaISA::mode_kernel; } @@ -482,14 +482,14 @@ AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const // Check for "superpage" mapping #if ALPHA_TLASER - if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && + if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) && VAddrSpaceEV5(req->getVaddr()) == 2) { #else if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { #endif // only valid in kernel mode - if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) != + if (DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)) != AlphaISA::mode_kernel) { if (write) { write_acv++; } else { read_acv++; } uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | @@ -513,7 +513,7 @@ AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const else read_accesses++; - int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN)); + int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN)); // not a physical address: need to look up pte AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(), diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index 81719cc48..07d01fa5c 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -41,7 +41,7 @@ #include "mem/request.hh" #include "sim/sim_object.hh" -class ExecContext; +class ThreadContext; class AlphaTLB : public SimObject { @@ -95,7 +95,7 @@ class AlphaITB : public AlphaTLB AlphaITB(const std::string &name, int size); virtual void regStats(); - Fault translate(RequestPtr &req, ExecContext *xc) const; + Fault translate(RequestPtr &req, ThreadContext *tc) const; }; class AlphaDTB : public AlphaTLB @@ -118,7 +118,7 @@ class AlphaDTB : public AlphaTLB AlphaDTB(const std::string &name, int size); virtual void regStats(); - Fault translate(RequestPtr &req, ExecContext *xc, bool write) const; + Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const; }; #endif // __ALPHA_MEMORY_HH__ diff --git a/src/arch/alpha/tru64/process.cc b/src/arch/alpha/tru64/process.cc index d2d148cc6..82e44b9e7 100644 --- a/src/arch/alpha/tru64/process.cc +++ b/src/arch/alpha/tru64/process.cc @@ -33,7 +33,7 @@ #include "arch/alpha/isa_traits.hh" #include "arch/alpha/tru64/process.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/tru64/tru64.hh" #include "sim/process.hh" @@ -45,9 +45,9 @@ using namespace AlphaISA; /// Target uname() handler. static SyscallReturn unameFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - TypedBufferArg<AlphaTru64::utsname> name(xc->getSyscallArg(0)); + TypedBufferArg<AlphaTru64::utsname> name(tc->getSyscallArg(0)); strcpy(name->sysname, "OSF1"); strcpy(name->nodename, "m5.eecs.umich.edu"); @@ -55,43 +55,43 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, strcpy(name->version, "732"); strcpy(name->machine, "alpha"); - name.copyOut(xc->getMemPort()); + name.copyOut(tc->getMemPort()); return 0; } /// Target getsysyinfo() handler. static SyscallReturn getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - unsigned op = xc->getSyscallArg(0); - unsigned nbytes = xc->getSyscallArg(2); + unsigned op = tc->getSyscallArg(0); + unsigned nbytes = tc->getSyscallArg(2); switch (op) { case AlphaTru64::GSI_MAX_CPU: { - TypedBufferArg<uint32_t> max_cpu(xc->getSyscallArg(1)); + TypedBufferArg<uint32_t> max_cpu(tc->getSyscallArg(1)); *max_cpu = htog((uint32_t)process->numCpus()); - max_cpu.copyOut(xc->getMemPort()); + max_cpu.copyOut(tc->getMemPort()); return 1; } case AlphaTru64::GSI_CPUS_IN_BOX: { - TypedBufferArg<uint32_t> cpus_in_box(xc->getSyscallArg(1)); + TypedBufferArg<uint32_t> cpus_in_box(tc->getSyscallArg(1)); *cpus_in_box = htog((uint32_t)process->numCpus()); - cpus_in_box.copyOut(xc->getMemPort()); + cpus_in_box.copyOut(tc->getMemPort()); return 1; } case AlphaTru64::GSI_PHYSMEM: { - TypedBufferArg<uint64_t> physmem(xc->getSyscallArg(1)); + TypedBufferArg<uint64_t> physmem(tc->getSyscallArg(1)); *physmem = htog((uint64_t)1024 * 1024); // physical memory in KB - physmem.copyOut(xc->getMemPort()); + physmem.copyOut(tc->getMemPort()); return 1; } case AlphaTru64::GSI_CPU_INFO: { - TypedBufferArg<AlphaTru64::cpu_info> infop(xc->getSyscallArg(1)); + TypedBufferArg<AlphaTru64::cpu_info> infop(tc->getSyscallArg(1)); infop->current_cpu = htog(0); infop->cpus_in_box = htog(process->numCpus()); @@ -103,30 +103,30 @@ getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, infop->cpu_ex_binding = htog(0); infop->mhz = htog(667); - infop.copyOut(xc->getMemPort()); + infop.copyOut(tc->getMemPort()); return 1; } case AlphaTru64::GSI_PROC_TYPE: { - TypedBufferArg<uint64_t> proc_type(xc->getSyscallArg(1)); + TypedBufferArg<uint64_t> proc_type(tc->getSyscallArg(1)); *proc_type = htog((uint64_t)11); - proc_type.copyOut(xc->getMemPort()); + proc_type.copyOut(tc->getMemPort()); return 1; } case AlphaTru64::GSI_PLATFORM_NAME: { - BufferArg bufArg(xc->getSyscallArg(1), nbytes); + BufferArg bufArg(tc->getSyscallArg(1), nbytes); strncpy((char *)bufArg.bufferPtr(), "COMPAQ Professional Workstation XP1000", nbytes); - bufArg.copyOut(xc->getMemPort()); + bufArg.copyOut(tc->getMemPort()); return 1; } case AlphaTru64::GSI_CLK_TCK: { - TypedBufferArg<uint64_t> clk_hz(xc->getSyscallArg(1)); + TypedBufferArg<uint64_t> clk_hz(tc->getSyscallArg(1)); *clk_hz = htog((uint64_t)1024); - clk_hz.copyOut(xc->getMemPort()); + clk_hz.copyOut(tc->getMemPort()); return 1; } @@ -141,14 +141,14 @@ getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, /// Target setsysyinfo() handler. static SyscallReturn setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - unsigned op = xc->getSyscallArg(0); + unsigned op = tc->getSyscallArg(0); switch (op) { case AlphaTru64::SSI_IEEE_FP_CONTROL: warn("setsysinfo: ignoring ieee_set_fp_control() arg 0x%x\n", - xc->getSyscallArg(1)); + tc->getSyscallArg(1)); break; default: @@ -163,22 +163,22 @@ setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, /// Target table() handler. static SyscallReturn tableFunc(SyscallDesc *desc, int callnum,Process *process, - ExecContext *xc) + ThreadContext *tc) { using namespace std; using namespace TheISA; - int id = xc->getSyscallArg(0); // table ID - int index = xc->getSyscallArg(1); // index into table + int id = tc->getSyscallArg(0); // table ID + int index = tc->getSyscallArg(1); // index into table // arg 2 is buffer pointer; type depends on table ID - int nel = xc->getSyscallArg(3); // number of elements - int lel = xc->getSyscallArg(4); // expected element size + int nel = tc->getSyscallArg(3); // number of elements + int lel = tc->getSyscallArg(4); // expected element size switch (id) { case AlphaTru64::TBL_SYSINFO: { if (index != 0 || nel != 1 || lel != sizeof(Tru64::tbl_sysinfo)) return -EINVAL; - TypedBufferArg<Tru64::tbl_sysinfo> elp(xc->getSyscallArg(2)); + TypedBufferArg<Tru64::tbl_sysinfo> elp(tc->getSyscallArg(2)); const int clk_hz = one_million; elp->si_user = htog(curTick / (Clock::Frequency / clk_hz)); @@ -190,7 +190,7 @@ SyscallReturn tableFunc(SyscallDesc *desc, int callnum,Process *process, elp->si_phz = htog(clk_hz); elp->si_boottime = htog(seconds_since_epoch); // seconds since epoch? elp->si_max_procs = htog(process->numCpus()); - elp.copyOut(xc->getMemPort()); + elp.copyOut(tc->getMemPort()); return 0; } diff --git a/src/arch/alpha/tru64/system.cc b/src/arch/alpha/tru64/system.cc index 13e5c36db..8d9a53273 100644 --- a/src/arch/alpha/tru64/system.cc +++ b/src/arch/alpha/tru64/system.cc @@ -35,7 +35,7 @@ #include "base/loader/symtab.hh" #include "base/trace.hh" #include "cpu/base.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/tru64/tru64_events.hh" #include "kern/system_events.hh" #include "mem/physical.hh" diff --git a/src/arch/alpha/tru64/system.hh b/src/arch/alpha/tru64/system.hh index 7f64d1042..947e92f50 100644 --- a/src/arch/alpha/tru64/system.hh +++ b/src/arch/alpha/tru64/system.hh @@ -36,7 +36,7 @@ #include "arch/isa_traits.hh" #include "sim/system.hh" -class ExecContext; +class ThreadContext; class BreakPCEvent; class BadAddrEvent; diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index a94742320..ec136091c 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -109,10 +109,10 @@ namespace AlphaISA /** * Function to insure ISA semantics about 0 registers. - * @param xc The execution context. + * @param tc The thread context. */ - template <class XC> - void zeroRegisters(XC *xc); + template <class TC> + void zeroRegisters(TC *tc); #if FULL_SYSTEM // Alpha IPR register accessors @@ -143,15 +143,15 @@ namespace AlphaISA RoundPage(Addr addr) { return (addr + PageBytes - 1) & ~(PageBytes - 1); } - void initCPU(ExecContext *xc, int cpuId); - void initIPRs(ExecContext *xc, int cpuId); + void initCPU(ThreadContext *tc, int cpuId); + void initIPRs(ThreadContext *tc, int cpuId); /** * Function to check for and process any interrupts. - * @param xc The execution context. + * @param tc The thread context. */ - template <class XC> - void processInterrupts(XC *xc); + template <class TC> + void processInterrupts(TC *tc); #endif } // namespace AlphaISA diff --git a/src/arch/alpha/vtophys.cc b/src/arch/alpha/vtophys.cc index 0c69ea0a9..f7fd92c15 100644 --- a/src/arch/alpha/vtophys.cc +++ b/src/arch/alpha/vtophys.cc @@ -36,7 +36,7 @@ #include "arch/alpha/vtophys.hh" #include "base/chunk_generator.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "mem/vport.hh" using namespace std; @@ -85,10 +85,10 @@ AlphaISA::vtophys(Addr vaddr) } Addr -AlphaISA::vtophys(ExecContext *xc, Addr addr) +AlphaISA::vtophys(ThreadContext *tc, Addr addr) { AlphaISA::VAddr vaddr = addr; - Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20); + Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20); Addr paddr = 0; //@todo Andrew couldn't remember why he commented some of this code //so I put it back in. Perhaps something to do with gdb debugging? @@ -101,7 +101,7 @@ AlphaISA::vtophys(ExecContext *xc, Addr addr) paddr = vaddr; } else { AlphaISA::PageTableEntry pte = - kernel_pte_lookup(xc->getPhysPort(), ptbr, vaddr); + kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr); if (pte.valid()) paddr = pte.paddr() | vaddr.offset(); } @@ -115,52 +115,52 @@ AlphaISA::vtophys(ExecContext *xc, Addr addr) void -AlphaISA::CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen) +AlphaISA::CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen) { uint8_t *dst = (uint8_t *)dest; - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); vp->readBlob(src, dst, cplen); - xc->delVirtPort(vp); + tc->delVirtPort(vp); } void -AlphaISA::CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen) +AlphaISA::CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen) { uint8_t *src = (uint8_t *)source; - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); vp->writeBlob(dest, src, cplen); - xc->delVirtPort(vp); + tc->delVirtPort(vp); } void -AlphaISA::CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen) +AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen) { int len = 0; - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); do { vp->readBlob(vaddr++, (uint8_t*)dst++, 1); len++; } while (len < maxlen && dst[len] != 0 ); - xc->delVirtPort(vp); + tc->delVirtPort(vp); dst[len] = 0; } void -AlphaISA::CopyStringIn(ExecContext *xc, char *src, Addr vaddr) +AlphaISA::CopyStringIn(ThreadContext *tc, char *src, Addr vaddr) { - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done(); gen.next()) { vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size()); src += gen.size(); } - xc->delVirtPort(vp); + tc->delVirtPort(vp); } diff --git a/src/arch/alpha/vtophys.hh b/src/arch/alpha/vtophys.hh index 57782a87a..472c694ff 100644 --- a/src/arch/alpha/vtophys.hh +++ b/src/arch/alpha/vtophys.hh @@ -34,7 +34,7 @@ #include "arch/alpha/isa_traits.hh" -class ExecContext; +class ThreadContext; class FunctionalPort; namespace AlphaISA { @@ -43,12 +43,12 @@ PageTableEntry kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr); Addr vtophys(Addr vaddr); -Addr vtophys(ExecContext *xc, Addr vaddr); +Addr vtophys(ThreadContext *tc, Addr vaddr); -void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len); -void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len); -void CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen); -void CopyStringIn(ExecContext *xc, char *src, Addr vaddr); +void CopyOut(ThreadContext *tc, void *dst, Addr src, size_t len); +void CopyIn(ThreadContext *tc, Addr dst, void *src, size_t len); +void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen); +void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr); }; #endif // __ARCH_ALPHA_VTOPHYS_H__ diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc index fa7275908..810c3fed4 100644 --- a/src/arch/mips/faults.cc +++ b/src/arch/mips/faults.cc @@ -29,7 +29,7 @@ */ #include "arch/mips/faults.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/base.hh" #include "base/trace.hh" @@ -102,28 +102,28 @@ FaultStat IntegerOverflowFault::_count; #if FULL_SYSTEM -void MipsFault::invoke(ExecContext * xc) +void MipsFault::invoke(ThreadContext * tc) { - FaultBase::invoke(xc); + FaultBase::invoke(tc); countStat()++; // exception restart address - if (setRestartAddress() || !xc->inPalMode()) - xc->setMiscReg(MipsISA::IPR_EXC_ADDR, xc->readPC()); + if (setRestartAddress() || !tc->inPalMode()) + tc->setMiscReg(MipsISA::IPR_EXC_ADDR, tc->readPC()); if (skipFaultingInstruction()) { // traps... skip faulting instruction. - xc->setMiscReg(MipsISA::IPR_EXC_ADDR, - xc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4); + tc->setMiscReg(MipsISA::IPR_EXC_ADDR, + tc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4); } - xc->setPC(xc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect()); - xc->setNextPC(xc->readPC() + sizeof(MachInst)); + tc->setPC(tc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect()); + tc->setNextPC(tc->readPC() + sizeof(MachInst)); } -void ArithmeticFault::invoke(ExecContext * xc) +void ArithmeticFault::invoke(ThreadContext * tc) { - FaultBase::invoke(xc); + FaultBase::invoke(tc); panic("Arithmetic traps are unimplemented!"); } diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh index 134fa2c4e..d8bf59cc1 100644 --- a/src/arch/mips/faults.hh +++ b/src/arch/mips/faults.hh @@ -47,7 +47,7 @@ class MipsFault : public FaultBase virtual bool setRestartAddress() {return true;} public: #if FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif virtual FaultVect vect() = 0; virtual FaultStat & countStat() = 0; @@ -114,7 +114,7 @@ class ArithmeticFault : public MipsFault FaultVect vect() {return _vect;} FaultStat & countStat() {return _count;} #if FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif }; diff --git a/src/arch/mips/isa_traits.cc b/src/arch/mips/isa_traits.cc index f577a1c94..056c8baff 100644 --- a/src/arch/mips/isa_traits.cc +++ b/src/arch/mips/isa_traits.cc @@ -40,7 +40,7 @@ using namespace std; void -MipsISA::copyRegs(ExecContext *src, ExecContext *dest) +MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest) { /*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag); uniq = xc->readMiscReg(MipsISA::Uniq_DepTag); @@ -53,7 +53,7 @@ MipsISA::copyRegs(ExecContext *src, ExecContext *dest) } void -MipsISA::MiscRegFile::copyMiscRegs(ExecContext *xc) +MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc) { /*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag); uniq = xc->readMiscReg(MipsISA::Uniq_DepTag); diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index e99bc7395..dc8b6758a 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -48,7 +48,7 @@ class FastCPU; class FullCPU; class Checkpoint; -class ExecContext; +class ThreadContext; namespace LittleEndianGuest {}; @@ -131,14 +131,14 @@ namespace MipsISA /** * Function to insure ISA semantics about 0 registers. - * @param xc The execution context. + * @param tc The thread context. */ - template <class XC> - void zeroRegisters(XC *xc); + template <class TC> + void zeroRegisters(TC *tc); const Addr MaxAddr = (Addr)-1; - void copyRegs(ExecContext *src, ExecContext *dest); + void copyRegs(ThreadContext *src, ThreadContext *dest); uint64_t fpConvert(double fp_val, ConvertType cvt_type); double roundFP(double val, int digits); diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc index 1408dbac0..4a919ac27 100644 --- a/src/arch/mips/linux/process.cc +++ b/src/arch/mips/linux/process.cc @@ -33,7 +33,7 @@ #include "arch/mips/isa_traits.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/linux/linux.hh" #include "sim/process.hh" @@ -45,9 +45,9 @@ using namespace MipsISA; /// Target uname() handler. static SyscallReturn unameFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0)); + TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0)); strcpy(name->sysname, "Linux"); strcpy(name->nodename, "m5.eecs.umich.edu"); @@ -55,7 +55,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); strcpy(name->machine, "mips"); - name.copyOut(xc->getMemPort()); + name.copyOut(tc->getMemPort()); return 0; } @@ -64,18 +64,18 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, /// different in practice from those used by Tru64 processes. static SyscallReturn sys_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - unsigned op = xc->getSyscallArg(0); - // unsigned nbytes = xc->getSyscallArg(2); + unsigned op = tc->getSyscallArg(0); + // unsigned nbytes = tc->getSyscallArg(2); switch (op) { case 45: { // GSI_IEEE_FP_CONTROL - TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1)); // I don't think this exactly matches the HW FPCR *fpcr = 0; - fpcr.copyOut(xc->getMemPort()); + fpcr.copyOut(tc->getMemPort()); return 0; } @@ -91,17 +91,17 @@ sys_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, /// Target sys_setsysinfo() handler. static SyscallReturn sys_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - unsigned op = xc->getSyscallArg(0); - // unsigned nbytes = xc->getSyscallArg(2); + unsigned op = tc->getSyscallArg(0); + // unsigned nbytes = tc->getSyscallArg(2); switch (op) { case 14: { // SSI_IEEE_FP_CONTROL - TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1)); + TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1)); // I don't think this exactly matches the HW FPCR - fpcr.copyIn(xc->getMemPort()); + fpcr.copyIn(tc->getMemPort()); DPRINTFR(SyscallVerbose, "sys_setsysinfo(SSI_IEEE_FP_CONTROL): " " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr)); return 0; diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc index 13d8ac3a8..bd7aa394e 100644 --- a/src/arch/mips/process.cc +++ b/src/arch/mips/process.cc @@ -34,7 +34,7 @@ #include "arch/mips/linux/process.hh" #include "base/loader/object_file.hh" #include "base/misc.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "sim/builder.hh" #include "sim/system.hh" diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh index 3781a91f3..013aa01c7 100644 --- a/src/arch/mips/regfile/float_regfile.hh +++ b/src/arch/mips/regfile/float_regfile.hh @@ -40,7 +40,7 @@ #include "sim/host.hh" class Checkpoint; -class ExecContext; +class ThreadContext; class Regfile; namespace MipsISA diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh index 2a0db38a4..dc82a3c26 100644 --- a/src/arch/mips/regfile/int_regfile.hh +++ b/src/arch/mips/regfile/int_regfile.hh @@ -37,7 +37,7 @@ #include "sim/faults.hh" class Checkpoint; -class ExecContext; +class ThreadContext; class Regfile; namespace MipsISA diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh index 72aa17424..f8aeab8cb 100644 --- a/src/arch/mips/regfile/misc_regfile.hh +++ b/src/arch/mips/regfile/misc_regfile.hh @@ -36,7 +36,7 @@ #include "sim/faults.hh" class Checkpoint; -class ExecContext; +class ThreadContext; class Regfile; namespace MipsISA @@ -57,14 +57,14 @@ namespace MipsISA int getInstAsid(); int getDataAsid(); - void copyMiscRegs(ExecContext *xc); + void copyMiscRegs(ThreadContext *tc); MiscReg readReg(int misc_reg) { return miscRegFile[misc_reg]; } - MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc) + MiscReg readRegWithEffect(int misc_reg, Fault &fault, ThreadContext *tc) { return miscRegFile[misc_reg]; } @@ -75,7 +75,7 @@ namespace MipsISA } Fault setRegWithEffect(int misc_reg, const MiscReg &val, - ExecContext *xc) + ThreadContext *tc) { miscRegFile[misc_reg] = val; return NoFault; } @@ -87,9 +87,9 @@ namespace MipsISA InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs private: - MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { } + MiscReg readIpr(int idx, Fault &fault, ThreadContext *tc) { } - Fault setIpr(int idx, uint64_t val, ExecContext *xc) { } + Fault setIpr(int idx, uint64_t val, ThreadContext *tc) { } #endif friend class RegFile; }; diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh index e1b834568..af61e62cd 100644 --- a/src/arch/mips/regfile/regfile.hh +++ b/src/arch/mips/regfile/regfile.hh @@ -39,7 +39,7 @@ #include "sim/faults.hh" class Checkpoint; -class ExecContext; +class ThreadContext; namespace MipsISA { @@ -64,10 +64,10 @@ namespace MipsISA } MiscReg readMiscRegWithEffect(int miscReg, - Fault &fault, ExecContext *xc) + Fault &fault, ThreadContext *tc) { fault = NoFault; - return miscRegFile.readRegWithEffect(miscReg, fault, xc); + return miscRegFile.readRegWithEffect(miscReg, fault, tc); } Fault setMiscReg(int miscReg, const MiscReg &val) @@ -76,9 +76,9 @@ namespace MipsISA } Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, - ExecContext * xc) + ThreadContext * tc) { - return miscRegFile.setRegWithEffect(miscReg, val, xc); + return miscRegFile.setRegWithEffect(miscReg, val, tc); } FloatReg readFloatReg(int floatReg) @@ -189,12 +189,12 @@ namespace MipsISA } }; - void copyRegs(ExecContext *src, ExecContext *dest); + void copyRegs(ThreadContext *src, ThreadContext *dest); - void copyMiscRegs(ExecContext *src, ExecContext *dest); + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); #if FULL_SYSTEM - void copyIprs(ExecContext *src, ExecContext *dest); + void copyIprs(ThreadContext *src, ThreadContext *dest); #endif } // namespace MipsISA diff --git a/src/arch/mips/stacktrace.hh b/src/arch/mips/stacktrace.hh index 3516b1d19..38767cef7 100644 --- a/src/arch/mips/stacktrace.hh +++ b/src/arch/mips/stacktrace.hh @@ -34,13 +34,13 @@ #include "base/trace.hh" #include "cpu/static_inst.hh" -class ExecContext; +class ThreadContext; class StackTrace; class ProcessInfo { private: - ExecContext *xc; + ThreadContext *tc; int thread_info_size; int task_struct_size; @@ -49,7 +49,7 @@ class ProcessInfo int name_off; public: - ProcessInfo(ExecContext *_xc); + ProcessInfo(ThreadContext *_tc); Addr task(Addr ksp) const; int pid(Addr ksp) const; @@ -61,7 +61,7 @@ class StackTrace protected: typedef TheISA::MachInst MachInst; private: - ExecContext *xc; + ThreadContext *tc; std::vector<Addr> stack; private: @@ -70,21 +70,21 @@ class StackTrace bool decodeSave(MachInst inst, int ®, int &disp); bool decodeStack(MachInst inst, int &disp); - void trace(ExecContext *xc, bool is_call); + void trace(ThreadContext *tc, bool is_call); public: StackTrace(); - StackTrace(ExecContext *xc, StaticInstPtr inst); + StackTrace(ThreadContext *tc, StaticInstPtr inst); ~StackTrace(); void clear() { - xc = 0; + tc = 0; stack.clear(); } - bool valid() const { return xc != NULL; } - bool trace(ExecContext *xc, StaticInstPtr inst); + bool valid() const { return tc != NULL; } + bool trace(ThreadContext *tc, StaticInstPtr inst); public: const std::vector<Addr> &getstack() const { return stack; } @@ -106,7 +106,7 @@ class StackTrace }; inline bool -StackTrace::trace(ExecContext *xc, StaticInstPtr inst) +StackTrace::trace(ThreadContext *tc, StaticInstPtr inst) { if (!inst->isCall() && !inst->isReturn()) return false; @@ -114,7 +114,7 @@ StackTrace::trace(ExecContext *xc, StaticInstPtr inst) if (valid()) clear(); - trace(xc, !inst->isReturn()); + trace(tc, !inst->isReturn()); return true; } diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 09fdf230a..57b4d4d86 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -30,7 +30,7 @@ */ #include "arch/sparc/faults.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/base.hh" #include "base/trace.hh" @@ -220,36 +220,36 @@ FaultStat TrapInstruction::_count; #if FULL_SYSTEM -void SparcFault::invoke(ExecContext * xc) +void SparcFault::invoke(ThreadContext * tc) { - FaultBase::invoke(xc); + FaultBase::invoke(tc); countStat()++; //Use the SPARC trap state machine /*// exception restart address - if (setRestartAddress() || !xc->inPalMode()) - xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc); + if (setRestartAddress() || !tc->inPalMode()) + tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->regs.pc); if (skipFaultingInstruction()) { // traps... skip faulting instruction. - xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, - xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); + tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, + tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4); } - if (!xc->inPalMode()) - AlphaISA::swap_palshadow(&(xc->regs), true); + if (!tc->inPalMode()) + AlphaISA::swap_palshadow(&(tc->regs), true); - xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect(); - xc->regs.npc = xc->regs.pc + sizeof(MachInst);*/ + tc->regs.pc = tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect(); + tc->regs.npc = tc->regs.pc + sizeof(MachInst);*/ } #endif #if !FULL_SYSTEM -void TrapInstruction::invoke(ExecContext * xc) +void TrapInstruction::invoke(ThreadContext * tc) { - xc->syscall(syscall_num); + tc->syscall(syscall_num); } #endif diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh index 88efe2eee..9f595a28b 100644 --- a/src/arch/sparc/faults.hh +++ b/src/arch/sparc/faults.hh @@ -46,7 +46,7 @@ class SparcFault : public FaultBase { public: #if FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif virtual TrapType trapType() = 0; virtual FaultPriority priority() = 0; @@ -585,7 +585,7 @@ class TrapInstruction : public EnumeratedFault FaultPriority priority() {return _priority;} FaultStat & countStat() {return _count;} #if !FULL_SYSTEM - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); #endif }; diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index d4fcbb522..346f7b730 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -36,7 +36,7 @@ #include "config/full_system.hh" #include "sim/host.hh" -class ExecContext; +class ThreadContext; class FastCPU; //class FullCPU; class Checkpoint; diff --git a/src/arch/sparc/linux/process.cc b/src/arch/sparc/linux/process.cc index db9a32c28..e27255e67 100644 --- a/src/arch/sparc/linux/process.cc +++ b/src/arch/sparc/linux/process.cc @@ -35,7 +35,7 @@ #include "arch/sparc/regfile.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/linux/linux.hh" #include "sim/process.hh" @@ -48,9 +48,9 @@ using namespace SparcISA; /// Target uname() handler. static SyscallReturn unameFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0)); + TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0)); strcpy(name->sysname, "Linux"); strcpy(name->nodename, "m5.eecs.umich.edu"); @@ -58,40 +58,40 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); strcpy(name->machine, "sparc"); - name.copyOut(xc->getMemPort()); + name.copyOut(tc->getMemPort()); return 0; } SyscallReturn SparcISA::getresuidFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc) + Process *p, ThreadContext *tc) { const IntReg id = htog(100); - Addr ruid = xc->getSyscallArg(0); - Addr euid = xc->getSyscallArg(1); - Addr suid = xc->getSyscallArg(2); + Addr ruid = tc->getSyscallArg(0); + Addr euid = tc->getSyscallArg(1); + Addr suid = tc->getSyscallArg(2); //Handle the EFAULT case //Set the ruid if(ruid) { BufferArg ruidBuff(ruid, sizeof(IntReg)); memcpy(ruidBuff.bufferPtr(), &id, sizeof(IntReg)); - ruidBuff.copyOut(xc->getMemPort()); + ruidBuff.copyOut(tc->getMemPort()); } //Set the euid if(euid) { BufferArg euidBuff(euid, sizeof(IntReg)); memcpy(euidBuff.bufferPtr(), &id, sizeof(IntReg)); - euidBuff.copyOut(xc->getMemPort()); + euidBuff.copyOut(tc->getMemPort()); } //Set the suid if(suid) { BufferArg suidBuff(suid, sizeof(IntReg)); memcpy(suidBuff.bufferPtr(), &id, sizeof(IntReg)); - suidBuff.copyOut(xc->getMemPort()); + suidBuff.copyOut(tc->getMemPort()); } return 0; } diff --git a/src/arch/sparc/linux/process.hh b/src/arch/sparc/linux/process.hh index cd59e4fd2..f4819ba84 100644 --- a/src/arch/sparc/linux/process.hh +++ b/src/arch/sparc/linux/process.hh @@ -61,7 +61,7 @@ class SparcLinuxProcess : public SparcLiveProcess }; SyscallReturn getresuidFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); } // namespace SparcISA #endif // __ALPHA_LINUX_PROCESS_HH__ diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 4b18dcca9..633c202ca 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -35,7 +35,7 @@ #include "arch/sparc/solaris/process.hh" #include "base/loader/object_file.hh" #include "base/misc.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "mem/page_table.hh" #include "mem/translating_port.hh" #include "sim/builder.hh" @@ -113,27 +113,27 @@ SparcLiveProcess::startup() //From the SPARC ABI //The process runs in user mode - execContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02); + threadContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02); //Setup default FP state - execContexts[0]->setMiscReg(MISCREG_FSR, 0); + threadContexts[0]->setMiscReg(MISCREG_FSR, 0); - execContexts[0]->setMiscReg(MISCREG_TICK, 0); + threadContexts[0]->setMiscReg(MISCREG_TICK, 0); // /* * Register window management registers */ //No windows contain info from other programs - execContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0); + threadContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0); //There are no windows to pop - execContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0); + threadContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0); //All windows are available to save into - execContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2); + threadContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2); //All windows are "clean" - execContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows); + threadContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows); //Start with register window 0 - execContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0); + threadContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0); } m5_auxv_t buildAuxVect(int64_t type, int64_t val) @@ -311,14 +311,14 @@ SparcLiveProcess::argsInit(int intSize, int pageSize) initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); - execContexts[0]->setIntReg(ArgumentReg0, argc); - execContexts[0]->setIntReg(ArgumentReg1, argv_array_base); - execContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias); + threadContexts[0]->setIntReg(ArgumentReg0, argc); + threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base); + threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias); Addr prog_entry = objFile->entryPoint(); - execContexts[0]->setPC(prog_entry); - execContexts[0]->setNextPC(prog_entry + sizeof(MachInst)); - execContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst))); + threadContexts[0]->setPC(prog_entry); + threadContexts[0]->setNextPC(prog_entry + sizeof(MachInst)); + threadContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst))); // num_processes++; } diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index 2739048eb..aaf1fcf24 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -563,9 +563,9 @@ namespace SparcISA #if FULL_SYSTEM /** Process a tick compare event and generate an interrupt on the cpu if * appropriate. */ - void processTickCompare(ExecContext *xc); - void processSTickCompare(ExecContext *xc); - void processHSTickCompare(ExecContext *xc); + void processTickCompare(ThreadContext *tc); + void processSTickCompare(ThreadContext *tc); + void processHSTickCompare(ThreadContext *tc); typedef CpuEventWrapper<MiscRegFile, &MiscRegFile::processTickCompare> TickCompareEvent; @@ -580,10 +580,10 @@ namespace SparcISA HSTickCompareEvent *hSTickCompare; /** Fullsystem only register version of ReadRegWithEffect() */ - MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ExecContext *xc); + MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc); /** Fullsystem only register version of SetRegWithEffect() */ Fault setFSRegWithEffect(int miscReg, const MiscReg &val, - ExecContext * xc); + ThreadContext * tc); #endif public: @@ -657,7 +657,7 @@ namespace SparcISA * are are readFSRegWithEffect (which is called by readRegWithEffect()). * Checking is done for permission based on state bits in the miscreg * file. */ - MiscReg readRegWithEffect(int miscReg, Fault &fault, ExecContext *xc); + MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc); /** write a value into an either an SE or FS IPR. No checking is done * about SE vs. FS as this is mostly used to copy the regfile. Thus more @@ -671,13 +671,13 @@ namespace SparcISA * Checking is done for permission based on state bits in the miscreg * file. */ Fault setRegWithEffect(int miscReg, - const MiscReg &val, ExecContext * xc); + const MiscReg &val, ThreadContext * tc); void serialize(std::ostream & os); void unserialize(Checkpoint * cp, const std::string & section); - void copyMiscRegs(ExecContext * xc); + void copyMiscRegs(ThreadContext * tc); bool isHyperPriv() { return hpstateFields.hpriv; } bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; } @@ -753,9 +753,9 @@ namespace SparcISA } MiscReg readMiscRegWithEffect(int miscReg, - Fault &fault, ExecContext *xc) + Fault &fault, ThreadContext *tc) { - return miscRegFile.readRegWithEffect(miscReg, fault, xc); + return miscRegFile.readRegWithEffect(miscReg, fault, tc); } Fault setMiscReg(int miscReg, const MiscReg &val) @@ -764,9 +764,9 @@ namespace SparcISA } Fault setMiscRegWithEffect(int miscReg, const MiscReg &val, - ExecContext * xc) + ThreadContext * tc) { - return miscRegFile.setRegWithEffect(miscReg, val, xc); + return miscRegFile.setRegWithEffect(miscReg, val, tc); } FloatReg readFloatReg(int floatReg, int width) @@ -853,9 +853,9 @@ namespace SparcISA } }; - void copyRegs(ExecContext *src, ExecContext *dest); + void copyRegs(ThreadContext *src, ThreadContext *dest); - void copyMiscRegs(ExecContext *src, ExecContext *dest); + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); int InterruptLevel(uint64_t softint); diff --git a/src/arch/sparc/solaris/process.cc b/src/arch/sparc/solaris/process.cc index 74f77991d..af0550910 100644 --- a/src/arch/sparc/solaris/process.cc +++ b/src/arch/sparc/solaris/process.cc @@ -33,7 +33,7 @@ #include "arch/sparc/regfile.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/solaris/solaris.hh" #include "sim/process.hh" @@ -46,9 +46,9 @@ using namespace SparcISA; /// Target uname() handler. static SyscallReturn unameFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - TypedBufferArg<Solaris::utsname> name(xc->getSyscallArg(0)); + TypedBufferArg<Solaris::utsname> name(tc->getSyscallArg(0)); strcpy(name->sysname, "SunOS"); strcpy(name->nodename, "m5.eecs.umich.edu"); @@ -56,7 +56,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process, strcpy(name->version, "Generic_118558-21"); strcpy(name->machine, "sun4u"); - name.copyOut(xc->getMemPort()); + name.copyOut(tc->getMemPort()); return 0; } diff --git a/src/arch/sparc/stacktrace.hh b/src/arch/sparc/stacktrace.hh index dd86a1553..d12aee211 100644 --- a/src/arch/sparc/stacktrace.hh +++ b/src/arch/sparc/stacktrace.hh @@ -34,13 +34,13 @@ #include "base/trace.hh" #include "cpu/static_inst.hh" -class ExecContext; +class ThreadContext; class StackTrace; class ProcessInfo { private: - ExecContext *xc; + ThreadContext *tc; int thread_info_size; int task_struct_size; @@ -49,7 +49,7 @@ class ProcessInfo int name_off; public: - ProcessInfo(ExecContext *_xc); + ProcessInfo(ThreadContext *_tc); Addr task(Addr ksp) const; int pid(Addr ksp) const; @@ -61,7 +61,7 @@ class StackTrace protected: typedef TheISA::MachInst MachInst; private: - ExecContext *xc; + ThreadContext *tc; std::vector<Addr> stack; private: @@ -70,21 +70,21 @@ class StackTrace bool decodeSave(MachInst inst, int ®, int &disp); bool decodeStack(MachInst inst, int &disp); - void trace(ExecContext *xc, bool is_call); + void trace(ThreadContext *tc, bool is_call); public: StackTrace(); - StackTrace(ExecContext *xc, StaticInstPtr inst); + StackTrace(ThreadContext *tc, StaticInstPtr inst); ~StackTrace(); void clear() { - xc = 0; + tc = 0; stack.clear(); } - bool valid() const { return xc != NULL; } - bool trace(ExecContext *xc, StaticInstPtr inst); + bool valid() const { return tc != NULL; } + bool trace(ThreadContext *tc, StaticInstPtr inst); public: const std::vector<Addr> &getstack() const { return stack; } @@ -106,7 +106,7 @@ class StackTrace }; inline bool -StackTrace::trace(ExecContext *xc, StaticInstPtr inst) +StackTrace::trace(ThreadContext *tc, StaticInstPtr inst) { if (!inst->isCall() && !inst->isReturn()) return false; @@ -114,7 +114,7 @@ StackTrace::trace(ExecContext *xc, StaticInstPtr inst) if (valid()) clear(); - trace(xc, !inst->isReturn()); + trace(tc, !inst->isReturn()); return true; } diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 9f4805058..b89d48663 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -32,7 +32,7 @@ Fault SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, - ExecContext *xc) + ThreadContext *tc) { int64_t time; SparcSystem *sys; @@ -47,25 +47,25 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, setReg(miscReg, val); if (newLevel > oldLevel) ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX - //xc->getCpuPtr()->checkInterrupts = true; + //tc->getCpuPtr()->checkInterrupts = true; return NoFault; case MISCREG_SOFTINT_CLR: - return setRegWithEffect(miscReg, ~val & softint, xc); + return setRegWithEffect(miscReg, ~val & softint, tc); case MISCREG_SOFTINT_SET: - return setRegWithEffect(miscReg, val | softint, xc); + return setRegWithEffect(miscReg, val | softint, tc); case MISCREG_TICK_CMPR: if (isNonPriv()) return new PrivilegedOpcode; if (tickCompare == NULL) - tickCompare = new TickCompareEvent(this, xc); + tickCompare = new TickCompareEvent(this, tc); setReg(miscReg, val); if (tick_cmprFields.int_dis && tickCompare.scheduled()) tickCompare.deschedule(); time = tick_cmprFields.tick_cmpr - tickFields.counter; if (!tick_cmprFields.int_dis && time > 0) - tickCompare.schedule(time * xc->getCpuPtr()->cycles(1)); + tickCompare.schedule(time * tc->getCpuPtr()->cycles(1)); return NoFault; case MISCREG_STICK: @@ -73,7 +73,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, return new PrivilegedOpcode; if (isPriv()) return new PrivilegedAction; - sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); + sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); assert(sys != NULL); sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64; stickFields.npt = val & Bit64 ? 1 : 0; @@ -83,8 +83,8 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, if (isNonPriv()) return new PrivilegedOpcode; if (sTickCompare == NULL) - sTickCompare = new STickCompareEvent(this, xc); - sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); + sTickCompare = new STickCompareEvent(this, tc); + sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); assert(sys != NULL); setReg(miscReg, val); if (stick_cmprFields.int_dis && sTickCompare.scheduled()) @@ -98,7 +98,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, case MISCREG_PIL: if (FULL_SYSTEM) { setReg(miscReg, val); - //xc->getCpuPtr()->checkInterrupts; + //tc->getCpuPtr()->checkInterrupts; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX return NoFault; } else @@ -127,8 +127,8 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, if (isNonPriv()) return new PrivilegedOpcode; if (hSTickCompare == NULL) - hSTickCompare = new HSTickCompareEvent(this, xc); - sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); + hSTickCompare = new HSTickCompareEvent(this, tc); + sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); assert(sys != NULL); setReg(miscReg, val); if (hstick_cmprFields.int_dis && hSTickCompare.scheduled()) @@ -143,7 +143,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, } MiscReg -MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc) +MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc) { switch (miscReg) { @@ -166,7 +166,7 @@ MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc) fault = new PrivilegedAction; return 0; } - sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); + sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); assert(sys != NULL); return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63; case MISCREG_STICK_CMPR: @@ -204,19 +204,19 @@ MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc) } void -MiscRegFile::processTickCompare(ExecContext *xc) +MiscRegFile::processTickCompare(ThreadContext *tc) { panic("tick compare not implemented\n"); } void -MiscRegFile::processSTickCompare(ExecContext *xc) +MiscRegFile::processSTickCompare(ThreadContext *tc) { panic("tick compare not implemented\n"); } void -MiscRegFile::processHSTickCompare(ExecContext *xc) +MiscRegFile::processHSTickCompare(ThreadContext *tc) { panic("tick compare not implemented\n"); } diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh index f75beb04a..f1c071148 100644 --- a/src/arch/sparc/utility.hh +++ b/src/arch/sparc/utility.hh @@ -81,10 +81,10 @@ namespace SparcISA /** * Function to insure ISA semantics about 0 registers. - * @param xc The execution context. + * @param tc The thread context. */ - template <class XC> - void zeroRegisters(XC *xc); + template <class TC> + void zeroRegisters(TC *tc); } // namespace SparcISA diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc index 0c69ea0a9..f7fd92c15 100644 --- a/src/arch/sparc/vtophys.cc +++ b/src/arch/sparc/vtophys.cc @@ -36,7 +36,7 @@ #include "arch/alpha/vtophys.hh" #include "base/chunk_generator.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "mem/vport.hh" using namespace std; @@ -85,10 +85,10 @@ AlphaISA::vtophys(Addr vaddr) } Addr -AlphaISA::vtophys(ExecContext *xc, Addr addr) +AlphaISA::vtophys(ThreadContext *tc, Addr addr) { AlphaISA::VAddr vaddr = addr; - Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20); + Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20); Addr paddr = 0; //@todo Andrew couldn't remember why he commented some of this code //so I put it back in. Perhaps something to do with gdb debugging? @@ -101,7 +101,7 @@ AlphaISA::vtophys(ExecContext *xc, Addr addr) paddr = vaddr; } else { AlphaISA::PageTableEntry pte = - kernel_pte_lookup(xc->getPhysPort(), ptbr, vaddr); + kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr); if (pte.valid()) paddr = pte.paddr() | vaddr.offset(); } @@ -115,52 +115,52 @@ AlphaISA::vtophys(ExecContext *xc, Addr addr) void -AlphaISA::CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen) +AlphaISA::CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen) { uint8_t *dst = (uint8_t *)dest; - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); vp->readBlob(src, dst, cplen); - xc->delVirtPort(vp); + tc->delVirtPort(vp); } void -AlphaISA::CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen) +AlphaISA::CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen) { uint8_t *src = (uint8_t *)source; - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); vp->writeBlob(dest, src, cplen); - xc->delVirtPort(vp); + tc->delVirtPort(vp); } void -AlphaISA::CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen) +AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen) { int len = 0; - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); do { vp->readBlob(vaddr++, (uint8_t*)dst++, 1); len++; } while (len < maxlen && dst[len] != 0 ); - xc->delVirtPort(vp); + tc->delVirtPort(vp); dst[len] = 0; } void -AlphaISA::CopyStringIn(ExecContext *xc, char *src, Addr vaddr) +AlphaISA::CopyStringIn(ThreadContext *tc, char *src, Addr vaddr) { - VirtualPort *vp = xc->getVirtPort(xc); + VirtualPort *vp = tc->getVirtPort(tc); for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done(); gen.next()) { vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size()); src += gen.size(); } - xc->delVirtPort(vp); + tc->delVirtPort(vp); } diff --git a/src/arch/sparc/vtophys.hh b/src/arch/sparc/vtophys.hh index d9b1a25c9..bf2b757d6 100644 --- a/src/arch/sparc/vtophys.hh +++ b/src/arch/sparc/vtophys.hh @@ -34,7 +34,7 @@ #include "arch/sparc/isa_traits.hh" -class ExecContext; +class ThreadContext; class FunctionalPort; namespace SparcISA { @@ -43,12 +43,12 @@ PageTableEntry kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr); Addr vtophys(Addr vaddr); -Addr vtophys(ExecContext *xc, Addr vaddr); +Addr vtophys(ThreadContext *tc, Addr vaddr); -void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len); -void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len); -void CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen); -void CopyStringIn(ExecContext *xc, char *src, Addr vaddr); +void CopyOut(ThreadContext *tc, void *dst, Addr src, size_t len); +void CopyIn(ThreadContext *tc, Addr dst, void *src, size_t len); +void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen); +void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr); }; #endif // __ARCH_SPARC_VTOPHYS_H__ diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc index 716e5bd49..2b545d13c 100644 --- a/src/base/remote_gdb.cc +++ b/src/base/remote_gdb.cc @@ -128,7 +128,7 @@ #include "base/socket.hh" #include "base/trace.hh" #include "config/full_system.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/static_inst.hh" #include "mem/physical.hh" #include "mem/port.hh" @@ -252,7 +252,7 @@ RemoteGDB::Event::process(int revent) gdb->detach(); } -RemoteGDB::RemoteGDB(System *_system, ExecContext *c) +RemoteGDB::RemoteGDB(System *_system, ThreadContext *c) : event(NULL), listener(NULL), number(-1), fd(-1), active(false), attached(false), system(_system), pmem(_system->physmem), context(c) @@ -704,11 +704,11 @@ RemoteGDB::HardBreakpoint::HardBreakpoint(RemoteGDB *_gdb, Addr pc) } void -RemoteGDB::HardBreakpoint::process(ExecContext *xc) +RemoteGDB::HardBreakpoint::process(ThreadContext *tc) { DPRINTF(GDBMisc, "handling hardware breakpoint at %#x\n", pc()); - if (xc == gdb->context) + if (tc == gdb->context) gdb->trap(ALPHA_KENTRY_INT); } diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh index df86f11f7..90b53e53f 100644 --- a/src/base/remote_gdb.hh +++ b/src/base/remote_gdb.hh @@ -39,7 +39,7 @@ #include "base/socket.hh" class System; -class ExecContext; +class ThreadContext; class PhysicalMemory; class GDBListener; @@ -80,7 +80,7 @@ class RemoteGDB System *system; PhysicalMemory *pmem; - ExecContext *context; + ThreadContext *context; protected: uint8_t getbyte(); @@ -98,10 +98,10 @@ class RemoteGDB template <class T> void write(Addr addr, T data); public: - RemoteGDB(System *system, ExecContext *context); + RemoteGDB(System *system, ThreadContext *context); ~RemoteGDB(); - void replaceExecContext(ExecContext *xc) { context = xc; } + void replaceThreadContext(ThreadContext *tc) { context = tc; } void attach(int fd); void detach(); @@ -133,7 +133,7 @@ class RemoteGDB HardBreakpoint(RemoteGDB *_gdb, Addr addr); std::string name() { return gdb->name() + ".hwbkpt"; } - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; friend class HardBreakpoint; diff --git a/src/cpu/base.cc b/src/cpu/base.cc index e48edb2a8..d77f03126 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -39,7 +39,7 @@ #include "base/output.hh" #include "cpu/base.hh" #include "cpu/cpuevent.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/profile.hh" #include "cpu/sampler/sampler.hh" #include "sim/param.hh" @@ -179,7 +179,7 @@ void BaseCPU::init() { if (!params->deferRegistration) - registerExecContexts(); + registerThreadContexts(); } void @@ -202,15 +202,15 @@ BaseCPU::regStats() .desc("number of cpu cycles simulated") ; - int size = execContexts.size(); + int size = threadContexts.size(); if (size > 1) { for (int i = 0; i < size; ++i) { stringstream namestr; ccprintf(namestr, "%s.ctx%d", name(), i); - execContexts[i]->regStats(namestr.str()); + threadContexts[i]->regStats(namestr.str()); } } else if (size == 1) - execContexts[0]->regStats(name()); + threadContexts[0]->regStats(name()); #if FULL_SYSTEM #endif @@ -218,19 +218,19 @@ BaseCPU::regStats() void -BaseCPU::registerExecContexts() +BaseCPU::registerThreadContexts() { - for (int i = 0; i < execContexts.size(); ++i) { - ExecContext *xc = execContexts[i]; + for (int i = 0; i < threadContexts.size(); ++i) { + ThreadContext *tc = threadContexts[i]; #if FULL_SYSTEM int id = params->cpu_id; if (id != -1) id += i; - xc->setCpuId(system->registerExecContext(xc, id)); + tc->setCpuId(system->registerThreadContext(tc, id)); #else - xc->setCpuId(xc->getProcessPtr()->registerExecContext(xc)); + tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc)); #endif } } @@ -245,22 +245,22 @@ BaseCPU::switchOut(Sampler *sampler) void BaseCPU::takeOverFrom(BaseCPU *oldCPU) { - assert(execContexts.size() == oldCPU->execContexts.size()); + assert(threadContexts.size() == oldCPU->threadContexts.size()); - for (int i = 0; i < execContexts.size(); ++i) { - ExecContext *newXC = execContexts[i]; - ExecContext *oldXC = oldCPU->execContexts[i]; + for (int i = 0; i < threadContexts.size(); ++i) { + ThreadContext *newTC = threadContexts[i]; + ThreadContext *oldTC = oldCPU->threadContexts[i]; - newXC->takeOverFrom(oldXC); + newTC->takeOverFrom(oldTC); - CpuEvent::replaceExecContext(oldXC, newXC); + CpuEvent::replaceThreadContext(oldTC, newTC); - assert(newXC->readCpuId() == oldXC->readCpuId()); + assert(newTC->readCpuId() == oldTC->readCpuId()); #if FULL_SYSTEM - system->replaceExecContext(newXC, newXC->readCpuId()); + system->replaceThreadContext(newTC, newTC->readCpuId()); #else - assert(newXC->getProcessPtr() == oldXC->getProcessPtr()); - newXC->getProcessPtr()->replaceExecContext(newXC, newXC->readCpuId()); + assert(newTC->getProcessPtr() == oldTC->getProcessPtr()); + newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId()); #endif } @@ -269,8 +269,8 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) interrupts[i] = oldCPU->interrupts[i]; intstatus = oldCPU->intstatus; - for (int i = 0; i < execContexts.size(); ++i) - execContexts[i]->profileClear(); + for (int i = 0; i < threadContexts.size(); ++i) + threadContexts[i]->profileClear(); if (profileEvent) profileEvent->schedule(curTick); @@ -286,9 +286,9 @@ BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval) void BaseCPU::ProfileEvent::process() { - for (int i = 0, size = cpu->execContexts.size(); i < size; ++i) { - ExecContext *xc = cpu->execContexts[i]; - xc->profileSample(); + for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) { + ThreadContext *tc = cpu->threadContexts[i]; + tc->profileSample(); } schedule(curTick + interval); diff --git a/src/cpu/base.hh b/src/cpu/base.hh index c28812b61..43122f238 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -43,7 +43,7 @@ class BranchPred; class CheckerCPU; -class ExecContext; +class ThreadContext; class System; class BaseCPU : public SimObject @@ -92,7 +92,7 @@ class BaseCPU : public SimObject #endif protected: - std::vector<ExecContext *> execContexts; + std::vector<ThreadContext *> threadContexts; public: @@ -144,7 +144,7 @@ class BaseCPU : public SimObject virtual void activateWhenReady(int tid) {}; - void registerExecContexts(); + void registerThreadContexts(); /// Prepare for another CPU to take over execution. When it is /// is ready (drained pipe) it signals the sampler. diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 1f2b44e02..0657be324 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -193,7 +193,7 @@ class BaseDynInst : public FastAlloc, public RefCounted /** Pointer to the FullCPU object. */ FullCPU *cpu; - /** Pointer to the exec context. */ + /** Pointer to the thread state. */ ImplState *thread; /** The kind of fault this instruction has generated. */ @@ -587,10 +587,9 @@ class BaseDynInst : public FastAlloc, public RefCounted void setState(ImplState *state) { thread = state; } - /** Returns the exec context. - * @todo: Remove this once the ExecContext is no longer used. + /** Returns the thread context. */ - ExecContext *xcBase() { return thread->getXCProxy(); } + ThreadContext *tcBase() { return thread->getTC(); } private: /** Instruction effective address. diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index c94570d7d..7ae7047e8 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -34,7 +34,7 @@ #include "cpu/base_dyn_inst.hh" #include "cpu/checker/cpu.hh" #include "cpu/cpu_exec_context.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/static_inst.hh" #include "sim/byteswap.hh" #include "sim/sim_object.hh" @@ -62,7 +62,7 @@ CheckerCPU::init() } CheckerCPU::CheckerCPU(Params *p) - : BaseCPU(p), cpuXC(NULL), xcProxy(NULL) + : BaseCPU(p), cpuXC(NULL), tc(NULL) { memReq = NULL; @@ -97,17 +97,16 @@ CheckerCPU::setMemory(MemObject *mem) cpuXC = new CPUExecContext(this, /* thread_num */ 0, process, /* asid */ 0, mem); - cpuXC->setStatus(ExecContext::Suspended); - xcProxy = cpuXC->getProxy(); - execContexts.push_back(xcProxy); + cpuXC->setStatus(ThreadContext::Suspended); + tc = cpuXC->getTC(); + threadContexts.push_back(tc); #else if (systemPtr) { cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false); - cpuXC->setStatus(ExecContext::Suspended); - xcProxy = cpuXC->getProxy(); - execContexts.push_back(xcProxy); - memReq->xc = xcProxy; + cpuXC->setStatus(ThreadContext::Suspended); + tc = cpuXC->getTC(); + threadContexts.push_back(tc); delete cpuXC->kernelStats; cpuXC->kernelStats = NULL; } @@ -123,10 +122,9 @@ CheckerCPU::setSystem(System *system) if (memPtr) { cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false); - cpuXC->setStatus(ExecContext::Suspended); - xcProxy = cpuXC->getProxy(); - execContexts.push_back(xcProxy); - memReq->xc = xcProxy; + cpuXC->setStatus(ThreadContext::Suspended); + tc = cpuXC->getTC(); + threadContexts.push_back(tc); delete cpuXC->kernelStats; cpuXC->kernelStats = NULL; } @@ -742,12 +740,12 @@ Checker<DynInstPtr>::validateExecution(DynInstPtr &inst) int misc_reg_idx = miscRegIdxs.front(); miscRegIdxs.pop(); - if (inst->xcBase()->readMiscReg(misc_reg_idx) != + if (inst->tcBase()->readMiscReg(misc_reg_idx) != cpuXC->readMiscReg(misc_reg_idx)) { warn("%lli: Misc reg idx %i (side effect) does not match! " "Inst: %#x, checker: %#x", curTick, misc_reg_idx, - inst->xcBase()->readMiscReg(misc_reg_idx), + inst->tcBase()->readMiscReg(misc_reg_idx), cpuXC->readMiscReg(misc_reg_idx)); handleError(); } diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 704580d80..484f4cf04 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -60,7 +60,7 @@ class Process; #endif // FULL_SYSTEM template <class> class BaseDynInst; -class ExecContext; +class ThreadContext; class MemInterface; class Checkpoint; class Request; @@ -76,11 +76,11 @@ class Sampler; * the values of uncached accesses. In these cases, and with * instructions marked as "IsUnverifiable", the checker assumes that * the value from the main CPU's execution is correct and simply - * copies that value. It provides a CheckerExecContext (see + * copies that value. It provides a CheckerThreadContext (see * checker/exec_context.hh) that provides hooks for updating the - * Checker's state through any ExecContext accesses. This allows the + * Checker's state through any ThreadContext accesses. This allows the * checker to be able to correctly verify instructions, even with - * external accesses to the ExecContext that change state. + * external accesses to the ThreadContext that change state. */ class CheckerCPU : public BaseCPU { @@ -132,7 +132,7 @@ class CheckerCPU : public BaseCPU // execution context CPUExecContext *cpuXC; - ExecContext *xcProxy; + ThreadContext *tc; AlphaITB *itb; AlphaDTB *dtb; @@ -340,7 +340,7 @@ class CheckerCPU : public BaseCPU } bool checkFlags(Request *req); - ExecContext *xcBase() { return xcProxy; } + ThreadContext *tcBase() { return tc; } CPUExecContext *cpuXCBase() { return cpuXC; } Result unverifiedResult; diff --git a/src/cpu/checker/exec_context.hh b/src/cpu/checker/exec_context.hh index 054739a6a..48890584d 100644 --- a/src/cpu/checker/exec_context.hh +++ b/src/cpu/checker/exec_context.hh @@ -31,7 +31,7 @@ #include "cpu/checker/cpu.hh" #include "cpu/cpu_exec_context.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" class EndQuiesceEvent; namespace Kernel { @@ -39,251 +39,251 @@ namespace Kernel { }; /** - * Derived ExecContext class for use with the Checker. The template - * parameter is the ExecContext class used by the specific CPU being - * verified. This CheckerExecContext is then used by the main CPU in - * place of its usual ExecContext class. It handles updating the - * checker's state any time state is updated through the ExecContext. + * Derived ThreadContext class for use with the Checker. The template + * parameter is the ThreadContext class used by the specific CPU being + * verified. This CheckerThreadContext is then used by the main CPU in + * place of its usual ThreadContext class. It handles updating the + * checker's state any time state is updated through the ThreadContext. */ -template <class XC> -class CheckerExecContext : public ExecContext +template <class TC> +class CheckerThreadContext : public ThreadContext { public: - CheckerExecContext(XC *actual_xc, + CheckerThreadContext(TC *actual_tc, CheckerCPU *checker_cpu) - : actualXC(actual_xc), checkerXC(checker_cpu->cpuXC), + : actualTC(actual_tc), checkerTC(checker_cpu->cpuXC), checkerCPU(checker_cpu) { } private: - XC *actualXC; - CPUExecContext *checkerXC; + TC *actualTC; + CPUExecContext *checkerTC; CheckerCPU *checkerCPU; public: - BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); } + BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } void setCpuId(int id) { - actualXC->setCpuId(id); - checkerXC->setCpuId(id); + actualTC->setCpuId(id); + checkerTC->setCpuId(id); } - int readCpuId() { return actualXC->readCpuId(); } + int readCpuId() { return actualTC->readCpuId(); } - TranslatingPort *getMemPort() { return actualXC->getMemPort(); } + TranslatingPort *getMemPort() { return actualTC->getMemPort(); } #if FULL_SYSTEM - System *getSystemPtr() { return actualXC->getSystemPtr(); } + System *getSystemPtr() { return actualTC->getSystemPtr(); } - PhysicalMemory *getPhysMemPtr() { return actualXC->getPhysMemPtr(); } + PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); } - AlphaITB *getITBPtr() { return actualXC->getITBPtr(); } + AlphaITB *getITBPtr() { return actualTC->getITBPtr(); } - AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); } + AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); } - Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); } + Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } #else - Process *getProcessPtr() { return actualXC->getProcessPtr(); } + Process *getProcessPtr() { return actualTC->getProcessPtr(); } #endif - Status status() const { return actualXC->status(); } + Status status() const { return actualTC->status(); } void setStatus(Status new_status) { - actualXC->setStatus(new_status); - checkerXC->setStatus(new_status); + actualTC->setStatus(new_status); + checkerTC->setStatus(new_status); } /// Set the status to Active. Optional delay indicates number of /// cycles to wait before beginning execution. - void activate(int delay = 1) { actualXC->activate(delay); } + void activate(int delay = 1) { actualTC->activate(delay); } /// Set the status to Suspended. - void suspend() { actualXC->suspend(); } + void suspend() { actualTC->suspend(); } /// Set the status to Unallocated. - void deallocate() { actualXC->deallocate(); } + void deallocate() { actualTC->deallocate(); } /// Set the status to Halted. - void halt() { actualXC->halt(); } + void halt() { actualTC->halt(); } #if FULL_SYSTEM - void dumpFuncProfile() { actualXC->dumpFuncProfile(); } + void dumpFuncProfile() { actualTC->dumpFuncProfile(); } #endif - void takeOverFrom(ExecContext *oldContext) + void takeOverFrom(ThreadContext *oldContext) { - actualXC->takeOverFrom(oldContext); - checkerXC->takeOverFrom(oldContext); + actualTC->takeOverFrom(oldContext); + checkerTC->takeOverFrom(oldContext); } - void regStats(const std::string &name) { actualXC->regStats(name); } + void regStats(const std::string &name) { actualTC->regStats(name); } - void serialize(std::ostream &os) { actualXC->serialize(os); } + void serialize(std::ostream &os) { actualTC->serialize(os); } void unserialize(Checkpoint *cp, const std::string §ion) - { actualXC->unserialize(cp, section); } + { actualTC->unserialize(cp, section); } #if FULL_SYSTEM - EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); } + EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } - Tick readLastActivate() { return actualXC->readLastActivate(); } - Tick readLastSuspend() { return actualXC->readLastSuspend(); } + Tick readLastActivate() { return actualTC->readLastActivate(); } + Tick readLastSuspend() { return actualTC->readLastSuspend(); } - void profileClear() { return actualXC->profileClear(); } - void profileSample() { return actualXC->profileSample(); } + void profileClear() { return actualTC->profileClear(); } + void profileSample() { return actualTC->profileSample(); } #endif - int getThreadNum() { return actualXC->getThreadNum(); } + int getThreadNum() { return actualTC->getThreadNum(); } // @todo: Do I need this? - MachInst getInst() { return actualXC->getInst(); } + MachInst getInst() { return actualTC->getInst(); } // @todo: Do I need this? - void copyArchRegs(ExecContext *xc) + void copyArchRegs(ThreadContext *tc) { - actualXC->copyArchRegs(xc); - checkerXC->copyArchRegs(xc); + actualTC->copyArchRegs(tc); + checkerTC->copyArchRegs(tc); } void clearArchRegs() { - actualXC->clearArchRegs(); - checkerXC->clearArchRegs(); + actualTC->clearArchRegs(); + checkerTC->clearArchRegs(); } // // New accessors for new decoder. // uint64_t readIntReg(int reg_idx) - { return actualXC->readIntReg(reg_idx); } + { return actualTC->readIntReg(reg_idx); } FloatReg readFloatReg(int reg_idx, int width) - { return actualXC->readFloatReg(reg_idx, width); } + { return actualTC->readFloatReg(reg_idx, width); } FloatReg readFloatReg(int reg_idx) - { return actualXC->readFloatReg(reg_idx); } + { return actualTC->readFloatReg(reg_idx); } FloatRegBits readFloatRegBits(int reg_idx, int width) - { return actualXC->readFloatRegBits(reg_idx, width); } + { return actualTC->readFloatRegBits(reg_idx, width); } FloatRegBits readFloatRegBits(int reg_idx) - { return actualXC->readFloatRegBits(reg_idx); } + { return actualTC->readFloatRegBits(reg_idx); } void setIntReg(int reg_idx, uint64_t val) { - actualXC->setIntReg(reg_idx, val); - checkerXC->setIntReg(reg_idx, val); + actualTC->setIntReg(reg_idx, val); + checkerTC->setIntReg(reg_idx, val); } void setFloatReg(int reg_idx, FloatReg val, int width) { - actualXC->setFloatReg(reg_idx, val, width); - checkerXC->setFloatReg(reg_idx, val, width); + actualTC->setFloatReg(reg_idx, val, width); + checkerTC->setFloatReg(reg_idx, val, width); } void setFloatReg(int reg_idx, FloatReg val) { - actualXC->setFloatReg(reg_idx, val); - checkerXC->setFloatReg(reg_idx, val); + actualTC->setFloatReg(reg_idx, val); + checkerTC->setFloatReg(reg_idx, val); } void setFloatRegBits(int reg_idx, FloatRegBits val, int width) { - actualXC->setFloatRegBits(reg_idx, val, width); - checkerXC->setFloatRegBits(reg_idx, val, width); + actualTC->setFloatRegBits(reg_idx, val, width); + checkerTC->setFloatRegBits(reg_idx, val, width); } void setFloatRegBits(int reg_idx, FloatRegBits val) { - actualXC->setFloatRegBits(reg_idx, val); - checkerXC->setFloatRegBits(reg_idx, val); + actualTC->setFloatRegBits(reg_idx, val); + checkerTC->setFloatRegBits(reg_idx, val); } - uint64_t readPC() { return actualXC->readPC(); } + uint64_t readPC() { return actualTC->readPC(); } void setPC(uint64_t val) { - actualXC->setPC(val); - checkerXC->setPC(val); + actualTC->setPC(val); + checkerTC->setPC(val); checkerCPU->recordPCChange(val); } - uint64_t readNextPC() { return actualXC->readNextPC(); } + uint64_t readNextPC() { return actualTC->readNextPC(); } void setNextPC(uint64_t val) { - actualXC->setNextPC(val); - checkerXC->setNextPC(val); + actualTC->setNextPC(val); + checkerTC->setNextPC(val); checkerCPU->recordNextPCChange(val); } - uint64_t readNextNPC() { return actualXC->readNextNPC(); } + uint64_t readNextNPC() { return actualTC->readNextNPC(); } void setNextNPC(uint64_t val) { - actualXC->setNextNPC(val); - checkerXC->setNextNPC(val); + actualTC->setNextNPC(val); + checkerTC->setNextNPC(val); checkerCPU->recordNextPCChange(val); } MiscReg readMiscReg(int misc_reg) - { return actualXC->readMiscReg(misc_reg); } + { return actualTC->readMiscReg(misc_reg); } MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) - { return actualXC->readMiscRegWithEffect(misc_reg, fault); } + { return actualTC->readMiscRegWithEffect(misc_reg, fault); } Fault setMiscReg(int misc_reg, const MiscReg &val) { - checkerXC->setMiscReg(misc_reg, val); - return actualXC->setMiscReg(misc_reg, val); + checkerTC->setMiscReg(misc_reg, val); + return actualTC->setMiscReg(misc_reg, val); } Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - checkerXC->setMiscRegWithEffect(misc_reg, val); - return actualXC->setMiscRegWithEffect(misc_reg, val); + checkerTC->setMiscRegWithEffect(misc_reg, val); + return actualTC->setMiscRegWithEffect(misc_reg, val); } unsigned readStCondFailures() - { return actualXC->readStCondFailures(); } + { return actualTC->readStCondFailures(); } void setStCondFailures(unsigned sc_failures) { - checkerXC->setStCondFailures(sc_failures); - actualXC->setStCondFailures(sc_failures); + checkerTC->setStCondFailures(sc_failures); + actualTC->setStCondFailures(sc_failures); } #if FULL_SYSTEM - bool inPalMode() { return actualXC->inPalMode(); } + bool inPalMode() { return actualTC->inPalMode(); } #endif // @todo: Fix this! - bool misspeculating() { return actualXC->misspeculating(); } + bool misspeculating() { return actualTC->misspeculating(); } #if !FULL_SYSTEM - IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); } + IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } // used to shift args for indirect syscall void setSyscallArg(int i, IntReg val) { - checkerXC->setSyscallArg(i, val); - actualXC->setSyscallArg(i, val); + checkerTC->setSyscallArg(i, val); + actualTC->setSyscallArg(i, val); } void setSyscallReturn(SyscallReturn return_value) { - checkerXC->setSyscallReturn(return_value); - actualXC->setSyscallReturn(return_value); + checkerTC->setSyscallReturn(return_value); + actualTC->setSyscallReturn(return_value); } - Counter readFuncExeInst() { return actualXC->readFuncExeInst(); } + Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } #endif void changeRegFileContext(RegFile::ContextParam param, RegFile::ContextVal val) { - actualXC->changeRegFileContext(param, val); - checkerXC->changeRegFileContext(param, val); + actualTC->changeRegFileContext(param, val); + checkerTC->changeRegFileContext(param, val); } }; diff --git a/src/cpu/cpu_exec_context.cc b/src/cpu/cpu_exec_context.cc index 1227d52f5..1e8071ca8 100644 --- a/src/cpu/cpu_exec_context.cc +++ b/src/cpu/cpu_exec_context.cc @@ -36,7 +36,7 @@ #include "arch/isa_traits.hh" #include "cpu/base.hh" #include "cpu/cpu_exec_context.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #if FULL_SYSTEM #include "base/callback.hh" @@ -62,14 +62,14 @@ using namespace std; CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys, AlphaITB *_itb, AlphaDTB *_dtb, bool use_kernel_stats) - : _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num), + : _status(ThreadContext::Unallocated), cpu(_cpu), thread_num(_thread_num), cpu_id(-1), lastActivate(0), lastSuspend(0), system(_sys), itb(_itb), dtb(_dtb), profile(NULL), func_exe_inst(0), storeCondFailures(0) { - proxy = new ProxyExecContext<CPUExecContext>(this); + tc = new ProxyThreadContext<CPUExecContext>(this); - quiesceEvent = new EndQuiesceEvent(proxy); + quiesceEvent = new EndQuiesceEvent(tc); regs.clear(); @@ -109,7 +109,7 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys, #else CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid, MemObject* memobj) - : _status(ExecContext::Unallocated), + : _status(ThreadContext::Unallocated), cpu(_cpu), thread_num(_thread_num), cpu_id(-1), lastActivate(0), lastSuspend(0), process(_process), asid(_asid), func_exe_inst(0), storeCondFailures(0) @@ -124,7 +124,7 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, port->setPeer(mem_port); regs.clear(); - proxy = new ProxyExecContext<CPUExecContext>(this); + tc = new ProxyThreadContext<CPUExecContext>(this); } CPUExecContext::CPUExecContext(RegFile *regFile) @@ -132,14 +132,14 @@ CPUExecContext::CPUExecContext(RegFile *regFile) func_exe_inst(0), storeCondFailures(0) { regs = *regFile; - proxy = new ProxyExecContext<CPUExecContext>(this); + tc = new ProxyThreadContext<CPUExecContext>(this); } #endif CPUExecContext::~CPUExecContext() { - delete proxy; + delete tc; } #if FULL_SYSTEM @@ -147,7 +147,7 @@ void CPUExecContext::dumpFuncProfile() { std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); - profile->dump(proxy, *os); + profile->dump(tc, *os); } void @@ -167,7 +167,7 @@ CPUExecContext::profileSample() #endif void -CPUExecContext::takeOverFrom(ExecContext *oldContext) +CPUExecContext::takeOverFrom(ThreadContext *oldContext) { // some things should already be set up #if FULL_SYSTEM @@ -185,18 +185,18 @@ CPUExecContext::takeOverFrom(ExecContext *oldContext) #else EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); if (quiesce) { - // Point the quiesce event's XC at this XC so that it wakes up + // Point the quiesce event's TC at this TC so that it wakes up // the proper CPU. - quiesce->xc = proxy; + quiesce->tc = tc; } if (quiesceEvent) { - quiesceEvent->xc = proxy; + quiesceEvent->tc = tc; } #endif storeCondFailures = 0; - oldContext->setStatus(ExecContext::Unallocated); + oldContext->setStatus(ThreadContext::Unallocated); } void @@ -242,17 +242,17 @@ CPUExecContext::unserialize(Checkpoint *cp, const std::string §ion) void CPUExecContext::activate(int delay) { - if (status() == ExecContext::Active) + if (status() == ThreadContext::Active) return; lastActivate = curTick; - if (status() == ExecContext::Unallocated) { + if (status() == ThreadContext::Unallocated) { cpu->activateWhenReady(thread_num); return; } - _status = ExecContext::Active; + _status = ThreadContext::Active; // status() == Suspended cpu->activateContext(thread_num, delay); @@ -261,7 +261,7 @@ CPUExecContext::activate(int delay) void CPUExecContext::suspend() { - if (status() == ExecContext::Suspended) + if (status() == ThreadContext::Suspended) return; lastActivate = curTick; @@ -270,32 +270,32 @@ CPUExecContext::suspend() #if FULL_SYSTEM // Don't change the status from active if there are pending interrupts if (cpu->check_interrupts()) { - assert(status() == ExecContext::Active); + assert(status() == ThreadContext::Active); return; } #endif */ - _status = ExecContext::Suspended; + _status = ThreadContext::Suspended; cpu->suspendContext(thread_num); } void CPUExecContext::deallocate() { - if (status() == ExecContext::Unallocated) + if (status() == ThreadContext::Unallocated) return; - _status = ExecContext::Unallocated; + _status = ThreadContext::Unallocated; cpu->deallocateContext(thread_num); } void CPUExecContext::halt() { - if (status() == ExecContext::Halted) + if (status() == ThreadContext::Halted) return; - _status = ExecContext::Halted; + _status = ThreadContext::Halted; cpu->haltContext(thread_num); } @@ -310,22 +310,22 @@ CPUExecContext::regStats(const string &name) } void -CPUExecContext::copyArchRegs(ExecContext *xc) +CPUExecContext::copyArchRegs(ThreadContext *src_tc) { - TheISA::copyRegs(xc, proxy); + TheISA::copyRegs(src_tc, tc); } #if FULL_SYSTEM VirtualPort* -CPUExecContext::getVirtPort(ExecContext *xc) +CPUExecContext::getVirtPort(ThreadContext *src_tc) { - if (!xc) + if (!src_tc) return virtPort; VirtualPort *vp; Port *mem_port; - vp = new VirtualPort("xc-vport", xc); + vp = new VirtualPort("tc-vport", src_tc); mem_port = system->physmem->getPort("functional"); mem_port->setPeer(vp); vp->setPeer(mem_port); @@ -335,7 +335,7 @@ CPUExecContext::getVirtPort(ExecContext *xc) void CPUExecContext::delVirtPort(VirtualPort *vp) { -// assert(!vp->nullExecContext()); +// assert(!vp->nullThreadContext()); delete vp->getPeer(); delete vp; } diff --git a/src/cpu/cpu_exec_context.hh b/src/cpu/cpu_exec_context.hh index 5faa8d19c..01b5cbb15 100644 --- a/src/cpu/cpu_exec_context.hh +++ b/src/cpu/cpu_exec_context.hh @@ -34,7 +34,7 @@ #include "arch/isa_traits.hh" #include "config/full_system.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "mem/physical.hh" #include "mem/request.hh" #include "sim/byteswap.hh" @@ -84,7 +84,7 @@ class CPUExecContext typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; public: - typedef ExecContext::Status Status; + typedef ThreadContext::Status Status; private: Status _status; @@ -114,7 +114,7 @@ class CPUExecContext // pointer to CPU associated with this context BaseCPU *cpu; - ProxyExecContext<CPUExecContext> *proxy; + ProxyThreadContext<CPUExecContext> *tc; // Current instruction MachInst inst; @@ -215,7 +215,7 @@ class CPUExecContext #endif virtual ~CPUExecContext(); - virtual void takeOverFrom(ExecContext *oldContext); + virtual void takeOverFrom(ThreadContext *oldContext); void regStats(const std::string &name); @@ -224,7 +224,7 @@ class CPUExecContext BaseCPU *getCpuPtr() { return cpu; } - ExecContext *getProxy() { return proxy; } + ThreadContext *getTC() { return tc; } int getThreadNum() { return thread_num; } @@ -240,25 +240,25 @@ class CPUExecContext Fault translateInstReq(RequestPtr &req) { - return itb->translate(req, proxy); + return itb->translate(req, tc); } Fault translateDataReadReq(RequestPtr &req) { - return dtb->translate(req, proxy, false); + return dtb->translate(req, tc, false); } Fault translateDataWriteReq(RequestPtr &req) { - return dtb->translate(req, proxy, true); + return dtb->translate(req, tc, true); } FunctionalPort *getPhysPort() { return physPort; } - /** Return a virtual port. If no exec context is specified then a static + /** Return a virtual port. If no thread context is specified then a static * port is returned. Otherwise a port is created and returned. It must be * deleted by deleteVirtPort(). */ - VirtualPort *getVirtPort(ExecContext *xc); + VirtualPort *getVirtPort(ThreadContext *tc); void delVirtPort(VirtualPort *vp); @@ -377,7 +377,7 @@ class CPUExecContext int readCpuId() { return cpu_id; } - void copyArchRegs(ExecContext *xc); + void copyArchRegs(ThreadContext *tc); // // New accessors for new decoder. @@ -470,7 +470,7 @@ class CPUExecContext MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) { - return regs.readMiscRegWithEffect(misc_reg, fault, proxy); + return regs.readMiscRegWithEffect(misc_reg, fault, tc); } Fault setMiscReg(int misc_reg, const MiscReg &val) @@ -480,7 +480,7 @@ class CPUExecContext Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - return regs.setMiscRegWithEffect(misc_reg, val, proxy); + return regs.setMiscRegWithEffect(misc_reg, val, tc); } unsigned readStCondFailures() { return storeCondFailures; } @@ -517,7 +517,7 @@ class CPUExecContext void syscall(int64_t callnum) { - process->syscall(callnum, proxy); + process->syscall(callnum, tc); } Counter readFuncExeInst() { return func_exe_inst; } diff --git a/src/cpu/cpuevent.cc b/src/cpu/cpuevent.cc index ae1dd7fa3..679244a6b 100644 --- a/src/cpu/cpuevent.cc +++ b/src/cpu/cpuevent.cc @@ -30,7 +30,7 @@ #include "cpu/cpuevent.hh" -/** Static list of all CpuEvent objects so we can modify their execution +/** Static list of all CpuEvent objects so we can modify their thread * contexts as needed. */ CpuEvent::CpuEventList CpuEvent::cpuEventList; @@ -48,14 +48,14 @@ CpuEvent::~CpuEvent() } void -CpuEvent::replaceExecContext(ExecContext *oldXc, ExecContext *newXc) +CpuEvent::replaceThreadContext(ThreadContext *oldTc, ThreadContext *newTc) { CpuEventList::iterator i; - // Update any events that have the old execution context with the new exec + // Update any events that have the old thread context with the new thread // context for (i = cpuEventList.begin(); i != cpuEventList.end(); i++) { - if ((*i)->xc == oldXc) - (*i)->xc = newXc; + if ((*i)->tc == oldTc) + (*i)->tc = newTc; } } diff --git a/src/cpu/cpuevent.hh b/src/cpu/cpuevent.hh index 10359b121..11ac7aafb 100644 --- a/src/cpu/cpuevent.hh +++ b/src/cpu/cpuevent.hh @@ -34,11 +34,11 @@ #include <vector> #include "sim/eventq.hh" -class ExecContext; +class ThreadContext; /** This class creates a global list of events than need a pointer to an - * execution context. When a switchover takes place the events can be migrated - * to the new execution context, otherwise you could have a wake timer interrupt + * thread context. When a switchover takes place the events can be migrated + * to the new thread context, otherwise you could have a wake timer interrupt * go off on a switched out cpu or other unfortunate events. This object MUST be * dynamically allocated to avoid it being deleted after a cpu switch happens. * */ @@ -52,36 +52,37 @@ class CpuEvent : public Event * happens. */ static CpuEventList cpuEventList; - /** The execution context that is switched to the new cpus. */ - ExecContext *xc; + /** The thread context that is switched to the new cpus. */ + ThreadContext *tc; public: - CpuEvent(EventQueue *q, ExecContext *_xc, Priority p = Default_Pri) - : Event(q, p), xc(_xc) + CpuEvent(EventQueue *q, ThreadContext *_tc, Priority p = Default_Pri) + : Event(q, p), tc(_tc) { cpuEventList.push_back(this); } /** delete the cpu event from the global list. */ ~CpuEvent(); - /** Update all events switching old xc to new xc. - * @param oldXc the old exeuction context we are switching from - * @param newXc the new execution context we are switching to. + /** Update all events switching old tc to new tc. + * @param oldTc the old thread context we are switching from + * @param newTc the new thread context we are switching to. */ - static void replaceExecContext(ExecContext *oldXc, ExecContext *newXc); + static void replaceThreadContext(ThreadContext *oldTc, + ThreadContext *newTc); }; -template <class T, void (T::* F)(ExecContext *xc)> +template <class T, void (T::* F)(ThreadContext *tc)> class CpuEventWrapper : public CpuEvent { private: T *object; public: - CpuEventWrapper(T *obj, ExecContext *_xc, EventQueue *q = &mainEventQueue, + CpuEventWrapper(T *obj, ThreadContext *_tc, EventQueue *q = &mainEventQueue, Priority p = Default_Pri) - : CpuEvent(q, _xc, p), object(obj) + : CpuEvent(q, _tc, p), object(obj) { } - void process() { (object->*F)(xc); } + void process() { (object->*F)(tc); } }; #endif // __CPU_CPUEVENT_HH__ diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh index d31e99c4a..95f8b449c 100644 --- a/src/cpu/exetrace.hh +++ b/src/cpu/exetrace.hh @@ -38,7 +38,7 @@ #include "sim/host.hh" #include "cpu/inst_seq.hh" // for InstSeqNum #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/static_inst.hh" class BaseCPU; @@ -173,14 +173,14 @@ InstRecord::setRegs(const IntRegFile ®s) inline InstRecord * -getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu, +getInstRecord(Tick cycle, ThreadContext *tc, BaseCPU *cpu, const StaticInstPtr staticInst, Addr pc, int thread = 0) { if (DTRACE(InstExec) && - (InstRecord::traceMisspec() || !xc->misspeculating())) { + (InstRecord::traceMisspec() || !tc->misspeculating())) { return new InstRecord(cycle, cpu, staticInst, pc, - xc->misspeculating(), thread); + tc->misspeculating(), thread); } return NULL; diff --git a/src/cpu/intr_control.cc b/src/cpu/intr_control.cc index 3171a352f..4cbc86891 100644 --- a/src/cpu/intr_control.cc +++ b/src/cpu/intr_control.cc @@ -33,7 +33,7 @@ #include <vector> #include "cpu/base.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/intr_control.hh" #include "sim/builder.hh" #include "sim/sim_object.hh" @@ -51,32 +51,32 @@ IntrControl::IntrControl(const string &name, BaseCPU *c) void IntrControl::post(int int_num, int index) { - std::vector<ExecContext *> &xcvec = cpu->system->execContexts; - BaseCPU *temp = xcvec[0]->getCpuPtr(); + std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts; + BaseCPU *temp = tcvec[0]->getCpuPtr(); temp->post_interrupt(int_num, index); } void IntrControl::post(int cpu_id, int int_num, int index) { - std::vector<ExecContext *> &xcvec = cpu->system->execContexts; - BaseCPU *temp = xcvec[cpu_id]->getCpuPtr(); + std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts; + BaseCPU *temp = tcvec[cpu_id]->getCpuPtr(); temp->post_interrupt(int_num, index); } void IntrControl::clear(int int_num, int index) { - std::vector<ExecContext *> &xcvec = cpu->system->execContexts; - BaseCPU *temp = xcvec[0]->getCpuPtr(); + std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts; + BaseCPU *temp = tcvec[0]->getCpuPtr(); temp->clear_interrupt(int_num, index); } void IntrControl::clear(int cpu_id, int int_num, int index) { - std::vector<ExecContext *> &xcvec = cpu->system->execContexts; - BaseCPU *temp = xcvec[cpu_id]->getCpuPtr(); + std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts; + BaseCPU *temp = tcvec[cpu_id]->getCpuPtr(); temp->clear_interrupt(int_num, index); } diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh index 60b3c1335..9976000e9 100644 --- a/src/cpu/memtest/memtest.hh +++ b/src/cpu/memtest/memtest.hh @@ -42,7 +42,7 @@ #include "sim/sim_object.hh" #include "sim/stats.hh" -class ExecContext; +class ThreadContext; class MemTest : public SimObject { public: diff --git a/src/cpu/o3/alpha_cpu.hh b/src/cpu/o3/alpha_cpu.hh index 3c16c3b2e..588b11724 100644 --- a/src/cpu/o3/alpha_cpu.hh +++ b/src/cpu/o3/alpha_cpu.hh @@ -32,7 +32,7 @@ #define __CPU_O3_ALPHA_FULL_CPU_HH__ #include "arch/isa_traits.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/o3/cpu.hh" #include "sim/byteswap.hh" @@ -71,20 +71,20 @@ class AlphaFullCPU : public FullO3CPU<Impl> AlphaFullCPU(Params *params); /** - * Derived ExecContext class for use with the AlphaFullCPU. It + * Derived ThreadContext class for use with the AlphaFullCPU. It * provides the interface for any external objects to access a * single thread's state and some general CPU state. Any time * external objects try to update state through this interface, * the CPU will create an event to squash all in-flight * instructions in order to ensure state is maintained correctly. */ - class AlphaXC : public ExecContext + class AlphaTC : public ThreadContext { public: /** Pointer to the CPU. */ AlphaFullCPU<Impl> *cpu; - /** Pointer to the thread state that this XC corrseponds to. */ + /** Pointer to the thread state that this TC corrseponds to. */ O3ThreadState<Impl> *thread; /** Returns a pointer to this CPU. */ @@ -145,9 +145,9 @@ class AlphaFullCPU : public FullO3CPU<Impl> virtual void dumpFuncProfile(); #endif /** Takes over execution of a thread from another CPU. */ - virtual void takeOverFrom(ExecContext *old_context); + virtual void takeOverFrom(ThreadContext *old_context); - /** Registers statistics associated with this XC. */ + /** Registers statistics associated with this TC. */ virtual void regStats(const std::string &name); /** Serializes state. */ @@ -177,8 +177,8 @@ class AlphaFullCPU : public FullO3CPU<Impl> */ virtual TheISA::MachInst getInst(); - /** Copies the architectural registers from another XC into this XC. */ - virtual void copyArchRegs(ExecContext *xc); + /** Copies the architectural registers from another TC into this TC. */ + virtual void copyArchRegs(ThreadContext *tc); /** Resets all architectural registers to 0. */ virtual void clearArchRegs(); @@ -359,9 +359,9 @@ class AlphaFullCPU : public FullO3CPU<Impl> /** Initiates a squash of all in-flight instructions for a given * thread. The source of the squash is an external update of - * state through the XC. + * state through the TC. */ - void squashFromXC(unsigned tid); + void squashFromTC(unsigned tid); #if FULL_SYSTEM /** Posts an interrupt. */ diff --git a/src/cpu/o3/alpha_cpu_impl.hh b/src/cpu/o3/alpha_cpu_impl.hh index 7c136638d..7f3d91640 100644 --- a/src/cpu/o3/alpha_cpu_impl.hh +++ b/src/cpu/o3/alpha_cpu_impl.hh @@ -68,7 +68,7 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params) // SMT is not supported in FS mode yet. assert(this->numThreads == 1); this->thread[i] = new Thread(this, 0, params->mem); - this->thread[i]->setStatus(ExecContext::Suspended); + this->thread[i]->setStatus(ThreadContext::Suspended); #else if (i < params->workload.size()) { DPRINTF(FullCPU, "FullCPU: Workload[%i] process is %#x", @@ -76,11 +76,11 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params) this->thread[i] = new Thread(this, i, params->workload[i], i, params->mem); - this->thread[i]->setStatus(ExecContext::Suspended); + this->thread[i]->setStatus(ThreadContext::Suspended); //usedTids[i] = true; //threadMap[i] = i; } else { - //Allocate Empty execution context so M5 can use later + //Allocate Empty thread so M5 can use later //when scheduling threads to CPU Process* dummy_proc = NULL; @@ -89,35 +89,35 @@ AlphaFullCPU<Impl>::AlphaFullCPU(Params *params) } #endif // !FULL_SYSTEM - ExecContext *xc_proxy; + ThreadContext *tc; - // Setup the XC that will serve as the interface to the threads/CPU. - AlphaXC *alpha_xc = new AlphaXC; + // Setup the TC that will serve as the interface to the threads/CPU. + AlphaTC *alpha_tc = new AlphaTC; - // If we're using a checker, then the XC should be the - // CheckerExecContext. + // If we're using a checker, then the TC should be the + // CheckerThreadContext. if (params->checker) { - xc_proxy = new CheckerExecContext<AlphaXC>( - alpha_xc, this->checker); + tc = new CheckerThreadContext<AlphaTC>( + alpha_tc, this->checker); } else { - xc_proxy = alpha_xc; + tc = alpha_tc; } - alpha_xc->cpu = this; - alpha_xc->thread = this->thread[i]; + alpha_tc->cpu = this; + alpha_tc->thread = this->thread[i]; #if FULL_SYSTEM // Setup quiesce event. this->thread[i]->quiesceEvent = - new EndQuiesceEvent(xc_proxy); + new EndQuiesceEvent(tc); this->thread[i]->lastActivate = 0; this->thread[i]->lastSuspend = 0; #endif - // Give the thread the XC. - this->thread[i]->xcProxy = xc_proxy; + // Give the thread the TC. + this->thread[i]->tc = tc; - // Add the XC to the CPU's list of XC's. - this->execContexts.push_back(xc_proxy); + // Add the TC to the CPU's list of TC's. + this->threadContexts.push_back(tc); } @@ -156,7 +156,7 @@ AlphaFullCPU<Impl>::regStats() #if FULL_SYSTEM template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::dumpFuncProfile() +AlphaFullCPU<Impl>::AlphaTC::dumpFuncProfile() { // Currently not supported } @@ -164,7 +164,7 @@ AlphaFullCPU<Impl>::AlphaXC::dumpFuncProfile() template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context) +AlphaFullCPU<Impl>::AlphaTC::takeOverFrom(ThreadContext *old_context) { // some things should already be set up assert(getMemPort() == old_context->getMemPort()); @@ -184,12 +184,12 @@ AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context) #else EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); if (other_quiesce) { - // Point the quiesce event's XC at this XC so that it wakes up + // Point the quiesce event's TC at this TC so that it wakes up // the proper CPU. - other_quiesce->xc = this; + other_quiesce->tc = this; } if (thread->quiesceEvent) { - thread->quiesceEvent->xc = this; + thread->quiesceEvent->tc = this; } // Transfer kernel stats from one CPU to the other. @@ -198,7 +198,7 @@ AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context) cpu->lockFlag = false; #endif - old_context->setStatus(ExecContext::Unallocated); + old_context->setStatus(ThreadContext::Unallocated); thread->inSyscall = false; thread->trapPending = false; @@ -206,23 +206,23 @@ AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context) template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::activate(int delay) +AlphaFullCPU<Impl>::AlphaTC::activate(int delay) { - DPRINTF(FullCPU, "Calling activate on AlphaXC\n"); + DPRINTF(FullCPU, "Calling activate on AlphaTC\n"); - if (thread->status() == ExecContext::Active) + if (thread->status() == ThreadContext::Active) return; #if FULL_SYSTEM thread->lastActivate = curTick; #endif - if (thread->status() == ExecContext::Unallocated) { + if (thread->status() == ThreadContext::Unallocated) { cpu->activateWhenReady(thread->tid); return; } - thread->setStatus(ExecContext::Active); + thread->setStatus(ThreadContext::Active); // status() == Suspended cpu->activateContext(thread->tid, delay); @@ -230,11 +230,11 @@ AlphaFullCPU<Impl>::AlphaXC::activate(int delay) template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::suspend() +AlphaFullCPU<Impl>::AlphaTC::suspend() { - DPRINTF(FullCPU, "Calling suspend on AlphaXC\n"); + DPRINTF(FullCPU, "Calling suspend on AlphaTC\n"); - if (thread->status() == ExecContext::Suspended) + if (thread->status() == ThreadContext::Suspended) return; #if FULL_SYSTEM @@ -245,44 +245,44 @@ AlphaFullCPU<Impl>::AlphaXC::suspend() #if FULL_SYSTEM // Don't change the status from active if there are pending interrupts if (cpu->check_interrupts()) { - assert(status() == ExecContext::Active); + assert(status() == ThreadContext::Active); return; } #endif */ - thread->setStatus(ExecContext::Suspended); + thread->setStatus(ThreadContext::Suspended); cpu->suspendContext(thread->tid); } template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::deallocate() +AlphaFullCPU<Impl>::AlphaTC::deallocate() { - DPRINTF(FullCPU, "Calling deallocate on AlphaXC\n"); + DPRINTF(FullCPU, "Calling deallocate on AlphaTC\n"); - if (thread->status() == ExecContext::Unallocated) + if (thread->status() == ThreadContext::Unallocated) return; - thread->setStatus(ExecContext::Unallocated); + thread->setStatus(ThreadContext::Unallocated); cpu->deallocateContext(thread->tid); } template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::halt() +AlphaFullCPU<Impl>::AlphaTC::halt() { - DPRINTF(FullCPU, "Calling halt on AlphaXC\n"); + DPRINTF(FullCPU, "Calling halt on AlphaTC\n"); - if (thread->status() == ExecContext::Halted) + if (thread->status() == ThreadContext::Halted) return; - thread->setStatus(ExecContext::Halted); + thread->setStatus(ThreadContext::Halted); cpu->haltContext(thread->tid); } template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::regStats(const std::string &name) +AlphaFullCPU<Impl>::AlphaTC::regStats(const std::string &name) { #if FULL_SYSTEM thread->kernelStats = new Kernel::Statistics(cpu->system); @@ -292,7 +292,7 @@ AlphaFullCPU<Impl>::AlphaXC::regStats(const std::string &name) template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::serialize(std::ostream &os) +AlphaFullCPU<Impl>::AlphaTC::serialize(std::ostream &os) { #if FULL_SYSTEM if (thread->kernelStats) @@ -303,7 +303,7 @@ AlphaFullCPU<Impl>::AlphaXC::serialize(std::ostream &os) template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::unserialize(Checkpoint *cp, const std::string §ion) +AlphaFullCPU<Impl>::AlphaTC::unserialize(Checkpoint *cp, const std::string §ion) { #if FULL_SYSTEM if (thread->kernelStats) @@ -315,46 +315,46 @@ AlphaFullCPU<Impl>::AlphaXC::unserialize(Checkpoint *cp, const std::string § #if FULL_SYSTEM template <class Impl> EndQuiesceEvent * -AlphaFullCPU<Impl>::AlphaXC::getQuiesceEvent() +AlphaFullCPU<Impl>::AlphaTC::getQuiesceEvent() { return thread->quiesceEvent; } template <class Impl> Tick -AlphaFullCPU<Impl>::AlphaXC::readLastActivate() +AlphaFullCPU<Impl>::AlphaTC::readLastActivate() { return thread->lastActivate; } template <class Impl> Tick -AlphaFullCPU<Impl>::AlphaXC::readLastSuspend() +AlphaFullCPU<Impl>::AlphaTC::readLastSuspend() { return thread->lastSuspend; } template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::profileClear() +AlphaFullCPU<Impl>::AlphaTC::profileClear() {} template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::profileSample() +AlphaFullCPU<Impl>::AlphaTC::profileSample() {} #endif template <class Impl> TheISA::MachInst -AlphaFullCPU<Impl>::AlphaXC:: getInst() +AlphaFullCPU<Impl>::AlphaTC:: getInst() { return thread->inst; } template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::copyArchRegs(ExecContext *xc) +AlphaFullCPU<Impl>::AlphaTC::copyArchRegs(ThreadContext *tc) { // This function will mess things up unless the ROB is empty and // there are no instructions in the pipeline. @@ -368,44 +368,44 @@ AlphaFullCPU<Impl>::AlphaXC::copyArchRegs(ExecContext *xc) DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, " "now has data %lli.\n", renamed_reg, cpu->readIntReg(renamed_reg), - xc->readIntReg(i)); + tc->readIntReg(i)); - cpu->setIntReg(renamed_reg, xc->readIntReg(i)); + cpu->setIntReg(renamed_reg, tc->readIntReg(i)); } // Then loop through the floating point registers. for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) { renamed_reg = cpu->renameMap[tid].lookup(i + AlphaISA::FP_Base_DepTag); cpu->setFloatRegBits(renamed_reg, - xc->readFloatRegBits(i)); + tc->readFloatRegBits(i)); } // Copy the misc regs. - copyMiscRegs(xc, this); + copyMiscRegs(tc, this); // Then finally set the PC and the next PC. - cpu->setPC(xc->readPC(), tid); - cpu->setNextPC(xc->readNextPC(), tid); + cpu->setPC(tc->readPC(), tid); + cpu->setNextPC(tc->readNextPC(), tid); #if !FULL_SYSTEM - this->thread->funcExeInst = xc->readFuncExeInst(); + this->thread->funcExeInst = tc->readFuncExeInst(); #endif } template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::clearArchRegs() +AlphaFullCPU<Impl>::AlphaTC::clearArchRegs() {} template <class Impl> uint64_t -AlphaFullCPU<Impl>::AlphaXC::readIntReg(int reg_idx) +AlphaFullCPU<Impl>::AlphaTC::readIntReg(int reg_idx) { return cpu->readArchIntReg(reg_idx, thread->tid); } template <class Impl> FloatReg -AlphaFullCPU<Impl>::AlphaXC::readFloatReg(int reg_idx, int width) +AlphaFullCPU<Impl>::AlphaTC::readFloatReg(int reg_idx, int width) { switch(width) { case 32: @@ -420,41 +420,41 @@ AlphaFullCPU<Impl>::AlphaXC::readFloatReg(int reg_idx, int width) template <class Impl> FloatReg -AlphaFullCPU<Impl>::AlphaXC::readFloatReg(int reg_idx) +AlphaFullCPU<Impl>::AlphaTC::readFloatReg(int reg_idx) { return cpu->readArchFloatRegSingle(reg_idx, thread->tid); } template <class Impl> FloatRegBits -AlphaFullCPU<Impl>::AlphaXC::readFloatRegBits(int reg_idx, int width) +AlphaFullCPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx, int width) { - DPRINTF(Fault, "Reading floatint register through the XC!\n"); + DPRINTF(Fault, "Reading floatint register through the TC!\n"); return cpu->readArchFloatRegInt(reg_idx, thread->tid); } template <class Impl> FloatRegBits -AlphaFullCPU<Impl>::AlphaXC::readFloatRegBits(int reg_idx) +AlphaFullCPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx) { return cpu->readArchFloatRegInt(reg_idx, thread->tid); } template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::setIntReg(int reg_idx, uint64_t val) +AlphaFullCPU<Impl>::AlphaTC::setIntReg(int reg_idx, uint64_t val) { cpu->setArchIntReg(reg_idx, val, thread->tid); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromXC(thread->tid); + cpu->squashFromTC(thread->tid); } } template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::setFloatReg(int reg_idx, FloatReg val, int width) +AlphaFullCPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val, int width) { switch(width) { case 32: @@ -467,80 +467,80 @@ AlphaFullCPU<Impl>::AlphaXC::setFloatReg(int reg_idx, FloatReg val, int width) // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromXC(thread->tid); + cpu->squashFromTC(thread->tid); } } template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::setFloatReg(int reg_idx, FloatReg val) +AlphaFullCPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val) { cpu->setArchFloatRegSingle(reg_idx, val, thread->tid); if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromXC(thread->tid); + cpu->squashFromTC(thread->tid); } } template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::setFloatRegBits(int reg_idx, FloatRegBits val, +AlphaFullCPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val, int width) { - DPRINTF(Fault, "Setting floatint register through the XC!\n"); + DPRINTF(Fault, "Setting floatint register through the TC!\n"); cpu->setArchFloatRegInt(reg_idx, val, thread->tid); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromXC(thread->tid); + cpu->squashFromTC(thread->tid); } } template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::setFloatRegBits(int reg_idx, FloatRegBits val) +AlphaFullCPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val) { cpu->setArchFloatRegInt(reg_idx, val, thread->tid); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromXC(thread->tid); + cpu->squashFromTC(thread->tid); } } template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::setPC(uint64_t val) +AlphaFullCPU<Impl>::AlphaTC::setPC(uint64_t val) { cpu->setPC(val, thread->tid); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromXC(thread->tid); + cpu->squashFromTC(thread->tid); } } template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::setNextPC(uint64_t val) +AlphaFullCPU<Impl>::AlphaTC::setNextPC(uint64_t val) { cpu->setNextPC(val, thread->tid); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromXC(thread->tid); + cpu->squashFromTC(thread->tid); } } template <class Impl> Fault -AlphaFullCPU<Impl>::AlphaXC::setMiscReg(int misc_reg, const MiscReg &val) +AlphaFullCPU<Impl>::AlphaTC::setMiscReg(int misc_reg, const MiscReg &val) { Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->tid); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromXC(thread->tid); + cpu->squashFromTC(thread->tid); } return ret_fault; @@ -548,14 +548,14 @@ AlphaFullCPU<Impl>::AlphaXC::setMiscReg(int misc_reg, const MiscReg &val) template <class Impl> Fault -AlphaFullCPU<Impl>::AlphaXC::setMiscRegWithEffect(int misc_reg, +AlphaFullCPU<Impl>::AlphaTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val) { Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, thread->tid); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromXC(thread->tid); + cpu->squashFromTC(thread->tid); } return ret_fault; @@ -565,21 +565,21 @@ AlphaFullCPU<Impl>::AlphaXC::setMiscRegWithEffect(int misc_reg, template <class Impl> TheISA::IntReg -AlphaFullCPU<Impl>::AlphaXC::getSyscallArg(int i) +AlphaFullCPU<Impl>::AlphaTC::getSyscallArg(int i) { return cpu->getSyscallArg(i, thread->tid); } template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::setSyscallArg(int i, IntReg val) +AlphaFullCPU<Impl>::AlphaTC::setSyscallArg(int i, IntReg val) { cpu->setSyscallArg(i, val, thread->tid); } template <class Impl> void -AlphaFullCPU<Impl>::AlphaXC::setSyscallReturn(SyscallReturn return_value) +AlphaFullCPU<Impl>::AlphaTC::setSyscallReturn(SyscallReturn return_value) { cpu->setSyscallReturn(return_value, thread->tid); } @@ -618,10 +618,10 @@ AlphaFullCPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val, template <class Impl> void -AlphaFullCPU<Impl>::squashFromXC(unsigned tid) +AlphaFullCPU<Impl>::squashFromTC(unsigned tid) { this->thread[tid]->inSyscall = true; - this->commit.generateXCEvent(tid); + this->commit.generateTCEvent(tid); } #if FULL_SYSTEM @@ -632,9 +632,9 @@ AlphaFullCPU<Impl>::post_interrupt(int int_num, int index) { BaseCPU::post_interrupt(int_num, index); - if (this->thread[0]->status() == ExecContext::Suspended) { + if (this->thread[0]->status() == ThreadContext::Suspended) { DPRINTF(IPI,"Suspended Processor awoke\n"); - this->execContexts[0]->activate(); + this->threadContexts[0]->activate(); } } @@ -673,7 +673,7 @@ AlphaFullCPU<Impl>::simPalCheck(int palFunc, unsigned tid) { if (this->thread[tid]->kernelStats) this->thread[tid]->kernelStats->callpal(palFunc, - this->execContexts[tid]); + this->threadContexts[tid]); switch (palFunc) { case PAL::halt: @@ -696,8 +696,8 @@ template <class Impl> void AlphaFullCPU<Impl>::trap(Fault fault, unsigned tid) { - // Pass the thread's XC into the invoke method. - fault->invoke(this->execContexts[tid]); + // Pass the thread's TC into the invoke method. + fault->invoke(this->threadContexts[tid]); } template <class Impl> diff --git a/src/cpu/o3/alpha_dyn_inst_impl.hh b/src/cpu/o3/alpha_dyn_inst_impl.hh index 3a0727b45..a73cf4a7d 100644 --- a/src/cpu/o3/alpha_dyn_inst_impl.hh +++ b/src/cpu/o3/alpha_dyn_inst_impl.hh @@ -67,9 +67,9 @@ Fault AlphaDynInst<Impl>::execute() { // @todo: Pretty convoluted way to avoid squashing from happening - // when using the XC during an instruction's execution + // when using the TC during an instruction's execution // (specifically for instructions that have side-effects that use - // the XC). Fix this. + // the TC). Fix this. bool in_syscall = this->thread->inSyscall; this->thread->inSyscall = true; @@ -85,9 +85,9 @@ Fault AlphaDynInst<Impl>::initiateAcc() { // @todo: Pretty convoluted way to avoid squashing from happening - // when using the XC during an instruction's execution + // when using the TC during an instruction's execution // (specifically for instructions that have side-effects that use - // the XC). Fix this. + // the TC). Fix this. bool in_syscall = this->thread->inSyscall; this->thread->inSyscall = true; diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index eef96b5fd..b7404c488 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -210,9 +210,9 @@ class DefaultCommit void generateTrapEvent(unsigned tid); /** Records that commit needs to initiate a squash due to an - * external state update through the XC. + * external state update through the TC. */ - void generateXCEvent(unsigned tid); + void generateTCEvent(unsigned tid); private: /** Updates the overall status of commit with the nextStatus, and @@ -242,8 +242,8 @@ class DefaultCommit /** Handles squashing due to a trap. */ void squashFromTrap(unsigned tid); - /** Handles squashing due to an XC write. */ - void squashFromXC(unsigned tid); + /** Handles squashing due to an TC write. */ + void squashFromTC(unsigned tid); /** Commits as many instructions as possible. */ void commitInsts(); @@ -344,7 +344,7 @@ class DefaultCommit bool trapSquash[Impl::MaxThreads]; /** Records if a thread has to squash this cycle due to an XC write. */ - bool xcSquash[Impl::MaxThreads]; + bool tcSquash[Impl::MaxThreads]; /** Priority List used for Commit Policy */ std::list<unsigned> priority_list; diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 629acb310..8ee47e907 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -115,7 +115,7 @@ DefaultCommit<Impl>::DefaultCommit(Params *params) commitStatus[i] = Idle; changedROBNumEntries[i] = false; trapSquash[i] = false; - xcSquash[i] = false; + tcSquash[i] = false; PC[i] = nextPC[i] = 0; } @@ -384,7 +384,7 @@ DefaultCommit<Impl>::takeOverFrom() commitStatus[i] = Idle; changedROBNumEntries[i] = false; trapSquash[i] = false; - xcSquash[i] = false; + tcSquash[i] = false; } squashCounter = 0; rob->takeOverFrom(); @@ -482,11 +482,11 @@ DefaultCommit<Impl>::generateTrapEvent(unsigned tid) template <class Impl> void -DefaultCommit<Impl>::generateXCEvent(unsigned tid) +DefaultCommit<Impl>::generateTCEvent(unsigned tid) { - DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid); + DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); - xcSquash[tid] = true; + tcSquash[tid] = true; } template <class Impl> @@ -545,11 +545,11 @@ DefaultCommit<Impl>::squashFromTrap(unsigned tid) template <class Impl> void -DefaultCommit<Impl>::squashFromXC(unsigned tid) +DefaultCommit<Impl>::squashFromTC(unsigned tid) { squashAll(tid); - DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]); + DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]); thread[tid]->inSyscall = false; assert(!thread[tid]->trapPending); @@ -557,7 +557,7 @@ DefaultCommit<Impl>::squashFromXC(unsigned tid) commitStatus[tid] = ROBSquashing; cpu->activityThisCycle(); - xcSquash[tid] = false; + tcSquash[tid] = false; ++squashCounter; } @@ -651,7 +651,7 @@ DefaultCommit<Impl>::commit() cpu->check_interrupts() && !cpu->inPalMode(readPC()) && !trapSquash[0] && - !xcSquash[0]) { + !tcSquash[0]) { // Tell fetch that there is an interrupt pending. This will // make fetch wait until it sees a non PAL-mode PC, at which // point it stops fetching instructions. @@ -720,10 +720,10 @@ DefaultCommit<Impl>::commit() // Not sure which one takes priority. I think if we have // both, that's a bad sign. if (trapSquash[tid] == true) { - assert(!xcSquash[tid]); + assert(!tcSquash[tid]); squashFromTrap(tid); - } else if (xcSquash[tid] == true) { - squashFromXC(tid); + } else if (tcSquash[tid] == true) { + squashFromTC(tid); } // Squashed sequence number must be older than youngest valid diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index ec804ee96..f523766cc 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -39,7 +39,7 @@ #include "cpu/activity.hh" #include "cpu/checker/cpu.hh" #include "cpu/cpu_exec_context.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/o3/alpha_dyn_inst.hh" #include "cpu/o3/alpha_impl.hh" #include "cpu/o3/cpu.hh" @@ -384,7 +384,7 @@ void FullO3CPU<Impl>::init() { if (!deferRegistration) { - registerExecContexts(); + registerThreadContexts(); } // Set inSyscall so that the CPU doesn't squash when initially @@ -394,17 +394,17 @@ FullO3CPU<Impl>::init() for (int tid=0; tid < number_of_threads; tid++) { #if FULL_SYSTEM - ExecContext *src_xc = execContexts[tid]; + ThreadContext *src_tc = threadContexts[tid]; #else - ExecContext *src_xc = thread[tid]->getXCProxy(); + ThreadContext *src_tc = thread[tid]->getTC(); #endif // Threads start in the Suspended State - if (src_xc->status() != ExecContext::Suspended) { + if (src_tc->status() != ThreadContext::Suspended) { continue; } #if FULL_SYSTEM - TheISA::initCPU(src_xc, src_xc->readCpuId()); + TheISA::initCPU(src_tc, src_tc->readCpuId()); #endif } @@ -430,9 +430,9 @@ FullO3CPU<Impl>::insertThread(unsigned tid) // and not in the CPUExecContext. #if 0 #if FULL_SYSTEM - ExecContext *src_xc = system->execContexts[tid]; + ThreadContext *src_tc = system->threadContexts[tid]; #else - CPUExecContext *src_xc = thread[tid]; + CPUExecContext *src_tc = thread[tid]; #endif //Bind Int Regs to Rename Map @@ -452,13 +452,13 @@ FullO3CPU<Impl>::insertThread(unsigned tid) } //Copy Thread Data Into RegFile - this->copyFromXC(tid); + this->copyFromTC(tid); //Set PC/NPC - regFile.pc[tid] = src_xc->readPC(); - regFile.npc[tid] = src_xc->readNextPC(); + regFile.pc[tid] = src_tc->readPC(); + regFile.npc[tid] = src_tc->readNextPC(); - src_xc->setStatus(ExecContext::Active); + src_tc->setStatus(ThreadContext::Active); activateContext(tid,1); @@ -496,7 +496,7 @@ FullO3CPU<Impl>::removeThread(unsigned tid) * in the sense that it's finished (exiting)? If the thread is just * being suspended we might... */ -// this->copyToXC(tid); +// this->copyToTC(tid); //Squash Throughout Pipeline fetch.squash(0,tid); @@ -745,9 +745,9 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU) // Set all statuses to active, schedule the CPU's tick event. // @todo: Fix up statuses so this is handled properly - for (int i = 0; i < execContexts.size(); ++i) { - ExecContext *xc = execContexts[i]; - if (xc->status() == ExecContext::Active && _status != Running) { + for (int i = 0; i < threadContexts.size(); ++i) { + ThreadContext *tc = threadContexts[i]; + if (tc->status() == ThreadContext::Active && _status != Running) { _status = Running; tickEvent.schedule(curTick); } diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index c2c5289bf..69f52f147 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -52,7 +52,7 @@ template <class> class Checker; -class ExecContext; +class ThreadContext; class MemObject; class Process; @@ -455,10 +455,10 @@ class FullO3CPU : public BaseFullCPU int getFreeTid(); public: - /** Returns a pointer to a thread's exec context. */ - ExecContext *xcBase(unsigned tid) + /** Returns a pointer to a thread context. */ + ThreadContext *tcBase(unsigned tid) { - return thread[tid]->getXCProxy(); + return thread[tid]->getTC(); } /** The global sequence number counter. */ diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 3a41de721..f3793db6d 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1011,7 +1011,7 @@ DefaultFetch<Impl>::fetch(bool &status_change) tid, instruction->staticInst->disassemble(fetch_PC)); instruction->traceData = - Trace::getInstRecord(curTick, cpu->xcBase(tid), cpu, + Trace::getInstRecord(curTick, cpu->tcBase(tid), cpu, instruction->staticInst, instruction->readPC(),tid); diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index c2ad75060..ee95b9ab8 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -240,7 +240,7 @@ class PhysRegFile unsigned thread_id) { return miscRegs[thread_id].readRegWithEffect(misc_reg, fault, - cpu->xcBase(thread_id)); + cpu->tcBase(thread_id)); } Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id) @@ -252,7 +252,7 @@ class PhysRegFile unsigned thread_id) { return miscRegs[thread_id].setRegWithEffect(misc_reg, val, - cpu->xcBase(thread_id)); + cpu->tcBase(thread_id)); } #if FULL_SYSTEM diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh index 3fa60f093..7322161e6 100644 --- a/src/cpu/o3/thread_state.hh +++ b/src/cpu/o3/thread_state.hh @@ -31,7 +31,7 @@ #include "arch/faults.hh" #include "arch/isa_traits.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/thread_state.hh" class Event; @@ -49,13 +49,13 @@ class Process; /** * Class that has various thread state, such as the status, the * current instruction being processed, whether or not the thread has - * a trap pending or is being externally updated, the ExecContext - * proxy pointer, etc. It also handles anything related to a specific + * a trap pending or is being externally updated, the ThreadContext + * pointer, etc. It also handles anything related to a specific * thread's process, such as syscalls and checking valid addresses. */ template <class Impl> struct O3ThreadState : public ThreadState { - typedef ExecContext::Status Status; + typedef ThreadContext::Status Status; typedef typename Impl::FullCPU FullCPU; /** Current status of the thread. */ @@ -93,12 +93,11 @@ struct O3ThreadState : public ThreadState { { } #endif - /** Pointer to the ExecContext of this thread. @todo: Don't call - this a proxy.*/ - ExecContext *xcProxy; + /** Pointer to the ThreadContext of this thread. */ + ThreadContext *tc; - /** Returns a pointer to the XC of this thread. */ - ExecContext *getXCProxy() { return xcProxy; } + /** Returns a pointer to the TC of this thread. */ + ThreadContext *getTC() { return tc; } /** Returns the status of this thread. */ Status status() const { return _status; } @@ -121,7 +120,7 @@ struct O3ThreadState : public ThreadState { #if !FULL_SYSTEM /** Handles the syscall. */ - void syscall(int64_t callnum) { process->syscall(callnum, xcProxy); } + void syscall(int64_t callnum) { process->syscall(callnum, tc); } #endif }; diff --git a/src/cpu/ozone/back_end.hh b/src/cpu/ozone/back_end.hh index 63823363e..75ef310b3 100644 --- a/src/cpu/ozone/back_end.hh +++ b/src/cpu/ozone/back_end.hh @@ -14,7 +14,7 @@ #include "mem/request.hh" #include "sim/eventq.hh" -class ExecContext; +class ThreadContext; template <class Impl> class OzoneThreadState; @@ -172,8 +172,8 @@ class BackEnd void setFrontEnd(FrontEnd *front_end_ptr) { frontEnd = front_end_ptr; } - void setXC(ExecContext *xc_ptr) - { xc = xc_ptr; } + void setTC(ThreadContext *tc_ptr) + { tc = tc_ptr; } void setThreadState(Thread *thread_ptr) { thread = thread_ptr; } @@ -182,8 +182,8 @@ class BackEnd void tick(); void squash(); - void squashFromXC(); - bool xcSquash; + void squashFromTC(); + bool tcSquash; template <class T> Fault read(RequestPtr req, T &data, int load_idx); @@ -240,7 +240,7 @@ class BackEnd FrontEnd *frontEnd; - ExecContext *xc; + ThreadContext *tc; Thread *thread; diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index d82527c8d..55e3813ae 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -37,7 +37,7 @@ #include "base/timebuf.hh" #include "config/full_system.hh" #include "cpu/base.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/inst_seq.hh" #include "cpu/ozone/rename_table.hh" #include "cpu/ozone/thread_state.hh" @@ -101,7 +101,7 @@ class OzoneCPU : public BaseCPU typedef TheISA::MiscReg MiscReg; public: - class OzoneXC : public ExecContext { + class OzoneTC : public ThreadContext { public: OzoneCPU<Impl> *cpu; @@ -150,7 +150,7 @@ class OzoneCPU : public BaseCPU void dumpFuncProfile(); #endif - void takeOverFrom(ExecContext *old_context); + void takeOverFrom(ThreadContext *old_context); void regStats(const std::string &name); @@ -172,7 +172,7 @@ class OzoneCPU : public BaseCPU // Also somewhat obnoxious. Really only used for the TLB fault. TheISA::MachInst getInst(); - void copyArchRegs(ExecContext *xc); + void copyArchRegs(ThreadContext *tc); void clearArchRegs(); @@ -254,10 +254,13 @@ class OzoneCPU : public BaseCPU { panic("Not supported on Alpha!"); } }; - // execution context proxy - OzoneXC ozoneXC; - ExecContext *xcProxy; - ExecContext *checkerXC; + // Ozone specific thread context + OzoneTC ozoneTC; + // Thread context to be used + ThreadContext *tc; + // Checker thread context; will wrap the OzoneTC if a checker is + // being used. + ThreadContext *checkerTC; typedef OzoneThreadState<Impl> ImplState; @@ -538,8 +541,8 @@ class OzoneCPU : public BaseCPU // and all other stores (WH64?). Unsuccessful Store // Conditionals would have returned above, and wouldn't fall // through. - for (int i = 0; i < this->system->execContexts.size(); i++){ - xc = this->system->execContexts[i]; + for (int i = 0; i < this->system->threadContexts.size(); i++){ + xc = this->system->threadContexts[i]; if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) == (req->paddr & ~0xf)) { xc->setMiscReg(TheISA::Lock_Flag_DepTag, false); @@ -595,7 +598,7 @@ class OzoneCPU : public BaseCPU InstSeqNum globalSeqNum; public: - void squashFromXC(); + void squashFromTC(); // @todo: This can be a useful debug function. Implement it. void dumpInsts() { frontEnd->dumpInsts(); } @@ -613,7 +616,7 @@ class OzoneCPU : public BaseCPU void setSyscallReturn(SyscallReturn return_value, int tid); #endif - ExecContext *xcBase() { return xcProxy; } + ThreadContext *tcBase() { return tc; } bool decoupledFrontEnd; struct CommStruct { diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index c8803813d..0763a30b3 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -37,7 +37,7 @@ #include "config/full_system.hh" #include "cpu/base.hh" #include "cpu/checker/exec_context.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/exetrace.hh" #include "cpu/ozone/cpu.hh" #include "cpu/quiesce_event.hh" @@ -121,28 +121,28 @@ OzoneCPU<Impl>::OzoneCPU(Params *p) #if FULL_SYSTEM checker->setSystem(p->system); #endif - checkerXC = new CheckerExecContext<OzoneXC>(&ozoneXC, checker); - thread.xcProxy = checkerXC; - xcProxy = checkerXC; + checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker); + thread.tc = checkerTC; + tc = checkerXC; } else { checker = NULL; - thread.xcProxy = &ozoneXC; - xcProxy = &ozoneXC; + thread.tc = &ozoneTC; + tc = &ozoneTC; } - ozoneXC.cpu = this; - ozoneXC.thread = &thread; + ozoneTC.cpu = this; + ozoneTC.thread = &thread; thread.inSyscall = false; - thread.setStatus(ExecContext::Suspended); + thread.setStatus(ThreadContext::Suspended); #if FULL_SYSTEM /***** All thread state stuff *****/ thread.cpu = this; thread.tid = 0; thread.mem = p->mem; - thread.quiesceEvent = new EndQuiesceEvent(xcProxy); + thread.quiesceEvent = new EndQuiesceEvent(tc); system = p->system; itb = p->itb; @@ -152,10 +152,10 @@ OzoneCPU<Impl>::OzoneCPU(Params *p) if (p->profile) { thread.profile = new FunctionProfile(p->system->kernelSymtab); - // @todo: This might be better as an ExecContext instead of OzoneXC + // @todo: This might be better as an ThreadContext instead of OzoneTC Callback *cb = - new MakeCallback<OzoneXC, - &OzoneXC::dumpFuncProfile>(&ozoneXC); + new MakeCallback<OzoneTC, + &OzoneTC::dumpFuncProfile>(&ozoneTC); registerExitCallback(cb); } @@ -174,13 +174,13 @@ OzoneCPU<Impl>::OzoneCPU(Params *p) numInst = 0; startNumInst = 0; - execContexts.push_back(xcProxy); + threadContexts.push_back(tc); frontEnd->setCPU(this); backEnd->setCPU(this); - frontEnd->setXC(xcProxy); - backEnd->setXC(xcProxy); + frontEnd->setTC(tc); + backEnd->setTC(tc); frontEnd->setThreadState(&thread); backEnd->setThreadState(&thread); @@ -263,11 +263,11 @@ OzoneCPU<Impl>::takeOverFrom(BaseCPU *oldCPU) comm.advance(); } - // if any of this CPU's ExecContexts are active, mark the CPU as + // if any of this CPU's ThreadContexts are active, mark the CPU as // running and schedule its tick event. - for (int i = 0; i < execContexts.size(); ++i) { - ExecContext *xc = execContexts[i]; - if (xc->status() == ExecContext::Active && + for (int i = 0; i < threadContexts.size(); ++i) { + ThreadContext *tc = threadContexts[i]; + if (tc->status() == ThreadContext::Active && _status != Running) { _status = Running; tickEvent.schedule(curTick); @@ -291,7 +291,7 @@ OzoneCPU<Impl>::activateContext(int thread_num, int delay) notIdleFraction++; scheduleTickEvent(delay); _status = Running; - thread._status = ExecContext::Active; + thread._status = ThreadContext::Active; frontEnd->wakeFromQuiesce(); } @@ -381,11 +381,11 @@ OzoneCPU<Impl>::init() // Mark this as in syscall so it won't need to squash thread.inSyscall = true; #if FULL_SYSTEM - for (int i = 0; i < execContexts.size(); ++i) { - ExecContext *xc = execContexts[i]; + for (int i = 0; i < threadContexts.size(); ++i) { + ThreadContext *tc = threadContexts[i]; // initialize CPU, including PC - TheISA::initCPU(xc, xc->readCpuId()); + TheISA::initCPU(tc, tc->readCpuId()); } #endif frontEnd->renameTable.copyFrom(thread.renameTable); @@ -400,8 +400,8 @@ OzoneCPU<Impl>::serialize(std::ostream &os) { BaseCPU::serialize(os); SERIALIZE_ENUM(_status); - nameOut(os, csprintf("%s.xc", name())); - ozoneXC.serialize(os); + nameOut(os, csprintf("%s.tc", name())); + ozoneTC.serialize(os); nameOut(os, csprintf("%s.tickEvent", name())); tickEvent.serialize(os); } @@ -412,7 +412,7 @@ OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion) { BaseCPU::unserialize(cp, section); UNSERIALIZE_ENUM(_status); - ozoneXC.unserialize(cp, csprintf("%s.xc", section)); + ozoneTC.unserialize(cp, csprintf("%s.tc", section)); tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); } @@ -440,16 +440,16 @@ OzoneCPU<Impl>::copySrcTranslate(Addr src) memReq->reset(src & ~(blk_size - 1), blk_size); // translate to physical address - Fault fault = xc->translateDataReadReq(memReq); + Fault fault = tc->translateDataReadReq(memReq); assert(fault != Alignment_Fault); if (fault == NoFault) { - xc->copySrcAddr = src; - xc->copySrcPhysAddr = memReq->paddr + offset; + tc->copySrcAddr = src; + tc->copySrcPhysAddr = memReq->paddr + offset; } else { - xc->copySrcAddr = 0; - xc->copySrcPhysAddr = 0; + tc->copySrcAddr = 0; + tc->copySrcPhysAddr = 0; } return fault; #endif @@ -467,7 +467,7 @@ OzoneCPU<Impl>::copy(Addr dest) // Only support block sizes of 64 atm. assert(blk_size == 64); uint8_t data[blk_size]; - //assert(xc->copySrcAddr); + //assert(tc->copySrcAddr); int offset = dest & (blk_size - 1); // Make sure block doesn't span page @@ -480,21 +480,21 @@ OzoneCPU<Impl>::copy(Addr dest) memReq->reset(dest & ~(blk_size -1), blk_size); // translate to physical address - Fault fault = xc->translateDataWriteReq(memReq); + Fault fault = tc->translateDataWriteReq(memReq); assert(fault != Alignment_Fault); if (fault == NoFault) { Addr dest_addr = memReq->paddr + offset; // Need to read straight from memory since we have more than 8 bytes. - memReq->paddr = xc->copySrcPhysAddr; - xc->mem->read(memReq, data); + memReq->paddr = tc->copySrcPhysAddr; + tc->mem->read(memReq, data); memReq->paddr = dest_addr; - xc->mem->write(memReq, data); + tc->mem->write(memReq, data); if (dcacheInterface) { memReq->cmd = Copy; memReq->completionEvent = NULL; - memReq->paddr = xc->copySrcPhysAddr; + memReq->paddr = tc->copySrcPhysAddr; memReq->dest = dest_addr; memReq->size = 64; memReq->time = curTick; @@ -510,7 +510,7 @@ template <class Impl> Addr OzoneCPU<Impl>::dbg_vtophys(Addr addr) { - return vtophys(xcProxy, addr); + return vtophys(tcProxy, addr); } #endif // FULL_SYSTEM @@ -524,7 +524,7 @@ OzoneCPU<Impl>::post_interrupt(int int_num, int index) if (_status == Idle) { DPRINTF(IPI,"Suspended Processor awoke\n"); // thread.activate(); - // Hack for now. Otherwise might have to go through the xcProxy, or + // Hack for now. Otherwise might have to go through the tc, or // I need to figure out what's the right thing to call. activateContext(thread.tid, 1); } @@ -556,10 +556,10 @@ OzoneCPU<Impl>::tick() template <class Impl> void -OzoneCPU<Impl>::squashFromXC() +OzoneCPU<Impl>::squashFromTC() { thread.inSyscall = true; - backEnd->generateXCEvent(); + backEnd->generateTCEvent(); } #if !FULL_SYSTEM @@ -567,7 +567,7 @@ template <class Impl> void OzoneCPU<Impl>::syscall() { - // Not sure this copy is needed, depending on how the XC proxy is made. + // Not sure this copy is needed, depending on how the TC proxy is made. thread.renameTable.copyFrom(backEnd->renameTable); thread.inSyscall = true; @@ -576,7 +576,7 @@ OzoneCPU<Impl>::syscall() DPRINTF(OzoneCPU, "FuncExeInst: %i\n", thread.funcExeInst); - thread.process->syscall(xcProxy); + thread.process->syscall(yc); thread.funcExeInst--; @@ -674,7 +674,7 @@ OzoneCPU<Impl>::processInterrupts() checker->cpuXCBase()->setMiscReg(IPR_INTID, ipl); } Fault fault = new InterruptFault; - fault->invoke(thread.getXCProxy()); + fault->invoke(thread.getTC()); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", thread.readMiscReg(IPR_IPLR), ipl, summary); } @@ -686,7 +686,7 @@ OzoneCPU<Impl>::simPalCheck(int palFunc) { // Need to move this to ISA code // May also need to make this per thread - thread.kernelStats->callpal(palFunc, xcProxy); + thread.kernelStats->callpal(palFunc, tc); switch (palFunc) { case PAL::halt: @@ -708,14 +708,14 @@ OzoneCPU<Impl>::simPalCheck(int palFunc) template <class Impl> BaseCPU * -OzoneCPU<Impl>::OzoneXC::getCpuPtr() +OzoneCPU<Impl>::OzoneTC::getCpuPtr() { return cpu; } template <class Impl> void -OzoneCPU<Impl>::OzoneXC::setCpuId(int id) +OzoneCPU<Impl>::OzoneTC::setCpuId(int id) { cpu->cpuId = id; thread->cpuId = id; @@ -723,14 +723,14 @@ OzoneCPU<Impl>::OzoneXC::setCpuId(int id) template <class Impl> void -OzoneCPU<Impl>::OzoneXC::setStatus(Status new_status) +OzoneCPU<Impl>::OzoneTC::setStatus(Status new_status) { thread->_status = new_status; } template <class Impl> void -OzoneCPU<Impl>::OzoneXC::activate(int delay) +OzoneCPU<Impl>::OzoneTC::activate(int delay) { cpu->activateContext(thread->tid, delay); } @@ -738,7 +738,7 @@ OzoneCPU<Impl>::OzoneXC::activate(int delay) /// Set the status to Suspended. template <class Impl> void -OzoneCPU<Impl>::OzoneXC::suspend() +OzoneCPU<Impl>::OzoneTC::suspend() { cpu->suspendContext(thread->tid); } @@ -746,7 +746,7 @@ OzoneCPU<Impl>::OzoneXC::suspend() /// Set the status to Unallocated. template <class Impl> void -OzoneCPU<Impl>::OzoneXC::deallocate() +OzoneCPU<Impl>::OzoneTC::deallocate() { cpu->deallocateContext(thread->tid); } @@ -754,7 +754,7 @@ OzoneCPU<Impl>::OzoneXC::deallocate() /// Set the status to Halted. template <class Impl> void -OzoneCPU<Impl>::OzoneXC::halt() +OzoneCPU<Impl>::OzoneTC::halt() { cpu->haltContext(thread->tid); } @@ -762,13 +762,13 @@ OzoneCPU<Impl>::OzoneXC::halt() #if FULL_SYSTEM template <class Impl> void -OzoneCPU<Impl>::OzoneXC::dumpFuncProfile() +OzoneCPU<Impl>::OzoneTC::dumpFuncProfile() { } #endif template <class Impl> void -OzoneCPU<Impl>::OzoneXC::takeOverFrom(ExecContext *old_context) +OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context) { // some things should already be set up assert(getMemPtr() == old_context->getMemPtr()); @@ -788,12 +788,12 @@ OzoneCPU<Impl>::OzoneXC::takeOverFrom(ExecContext *old_context) #else EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent(); if (other_quiesce) { - // Point the quiesce event's XC at this XC so that it wakes up + // Point the quiesce event's TC at this TC so that it wakes up // the proper CPU. - other_quiesce->xc = this; + other_quiesce->tc = this; } if (thread->quiesceEvent) { - thread->quiesceEvent->xc = this; + thread->quiesceEvent->tc = this; } thread->kernelStats = old_context->getKernelStats(); @@ -801,12 +801,12 @@ OzoneCPU<Impl>::OzoneXC::takeOverFrom(ExecContext *old_context) cpu->lockFlag = false; #endif - old_context->setStatus(ExecContext::Unallocated); + old_context->setStatus(ThreadContext::Unallocated); } template <class Impl> void -OzoneCPU<Impl>::OzoneXC::regStats(const std::string &name) +OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name) { #if FULL_SYSTEM thread->kernelStats = new Kernel::Statistics(cpu->system); @@ -816,39 +816,39 @@ OzoneCPU<Impl>::OzoneXC::regStats(const std::string &name) template <class Impl> void -OzoneCPU<Impl>::OzoneXC::serialize(std::ostream &os) +OzoneCPU<Impl>::OzoneTC::serialize(std::ostream &os) { } template <class Impl> void -OzoneCPU<Impl>::OzoneXC::unserialize(Checkpoint *cp, const std::string §ion) +OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string §ion) { } #if FULL_SYSTEM template <class Impl> EndQuiesceEvent * -OzoneCPU<Impl>::OzoneXC::getQuiesceEvent() +OzoneCPU<Impl>::OzoneTC::getQuiesceEvent() { return thread->quiesceEvent; } template <class Impl> Tick -OzoneCPU<Impl>::OzoneXC::readLastActivate() +OzoneCPU<Impl>::OzoneTC::readLastActivate() { return thread->lastActivate; } template <class Impl> Tick -OzoneCPU<Impl>::OzoneXC::readLastSuspend() +OzoneCPU<Impl>::OzoneTC::readLastSuspend() { return thread->lastSuspend; } template <class Impl> void -OzoneCPU<Impl>::OzoneXC::profileClear() +OzoneCPU<Impl>::OzoneTC::profileClear() { if (thread->profile) thread->profile->clear(); @@ -856,7 +856,7 @@ OzoneCPU<Impl>::OzoneXC::profileClear() template <class Impl> void -OzoneCPU<Impl>::OzoneXC::profileSample() +OzoneCPU<Impl>::OzoneTC::profileSample() { if (thread->profile) thread->profile->sample(thread->profileNode, thread->profilePC); @@ -865,7 +865,7 @@ OzoneCPU<Impl>::OzoneXC::profileSample() template <class Impl> int -OzoneCPU<Impl>::OzoneXC::getThreadNum() +OzoneCPU<Impl>::OzoneTC::getThreadNum() { return thread->tid; } @@ -873,57 +873,57 @@ OzoneCPU<Impl>::OzoneXC::getThreadNum() // Also somewhat obnoxious. Really only used for the TLB fault. template <class Impl> TheISA::MachInst -OzoneCPU<Impl>::OzoneXC::getInst() +OzoneCPU<Impl>::OzoneTC::getInst() { return thread->inst; } template <class Impl> void -OzoneCPU<Impl>::OzoneXC::copyArchRegs(ExecContext *xc) +OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc) { - thread->PC = xc->readPC(); - thread->nextPC = xc->readNextPC(); + thread->PC = tc->readPC(); + thread->nextPC = tc->readNextPC(); cpu->frontEnd->setPC(thread->PC); cpu->frontEnd->setNextPC(thread->nextPC); for (int i = 0; i < TheISA::TotalNumRegs; ++i) { if (i < TheISA::FP_Base_DepTag) { - thread->renameTable[i]->setIntResult(xc->readIntReg(i)); + thread->renameTable[i]->setIntResult(tc->readIntReg(i)); } else if (i < (TheISA::FP_Base_DepTag + TheISA::NumFloatRegs)) { int fp_idx = i - TheISA::FP_Base_DepTag; thread->renameTable[i]->setDoubleResult( - xc->readFloatRegDouble(fp_idx)); + tc->readFloatRegDouble(fp_idx)); } } #if !FULL_SYSTEM - thread->funcExeInst = xc->readFuncExeInst(); + thread->funcExeInst = tc->readFuncExeInst(); #endif - // Need to copy the XC values into the current rename table, + // Need to copy the TC values into the current rename table, // copy the misc regs. - thread->regs.miscRegs.copyMiscRegs(xc); + thread->regs.miscRegs.copyMiscRegs(tc); } template <class Impl> void -OzoneCPU<Impl>::OzoneXC::clearArchRegs() +OzoneCPU<Impl>::OzoneTC::clearArchRegs() { panic("Unimplemented!"); } template <class Impl> uint64_t -OzoneCPU<Impl>::OzoneXC::readIntReg(int reg_idx) +OzoneCPU<Impl>::OzoneTC::readIntReg(int reg_idx) { return thread->renameTable[reg_idx]->readIntResult(); } template <class Impl> float -OzoneCPU<Impl>::OzoneXC::readFloatReg(int reg_idx, int width) +OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx, int width) { int idx = reg_idx + TheISA::FP_Base_DepTag; switch(width) { @@ -939,7 +939,7 @@ OzoneCPU<Impl>::OzoneXC::readFloatReg(int reg_idx, int width) template <class Impl> double -OzoneCPU<Impl>::OzoneXC::readFloatReg(int reg_idx) +OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx) { int idx = reg_idx + TheISA::FP_Base_DepTag; return thread->renameTable[idx]->readFloatResult(); @@ -947,7 +947,7 @@ OzoneCPU<Impl>::OzoneXC::readFloatReg(int reg_idx) template <class Impl> uint64_t -OzoneCPU<Impl>::OzoneXC::readFloatRegBits(int reg_idx, int width) +OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx, int width) { int idx = reg_idx + TheISA::FP_Base_DepTag; return thread->renameTable[idx]->readIntResult(); @@ -955,7 +955,7 @@ OzoneCPU<Impl>::OzoneXC::readFloatRegBits(int reg_idx, int width) template <class Impl> uint64_t -OzoneCPU<Impl>::OzoneXC::readFloatRegBits(int reg_idx) +OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx) { int idx = reg_idx + TheISA::FP_Base_DepTag; return thread->renameTable[idx]->readIntResult(); @@ -963,18 +963,18 @@ OzoneCPU<Impl>::OzoneXC::readFloatRegBits(int reg_idx) template <class Impl> void -OzoneCPU<Impl>::OzoneXC::setIntReg(int reg_idx, uint64_t val) +OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val) { thread->renameTable[reg_idx]->setIntResult(val); if (!thread->inSyscall) { - cpu->squashFromXC(); + cpu->squashFromTC(); } } template <class Impl> void -OzoneCPU<Impl>::OzoneXC::setFloatReg(int reg_idx, FloatReg val, int width) +OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val, int width) { int idx = reg_idx + TheISA::FP_Base_DepTag; switch(width) { @@ -989,26 +989,26 @@ OzoneCPU<Impl>::OzoneXC::setFloatReg(int reg_idx, FloatReg val, int width) } if (!thread->inSyscall) { - cpu->squashFromXC(); + cpu->squashFromTC(); } } template <class Impl> void -OzoneCPU<Impl>::OzoneXC::setFloatReg(int reg_idx, FloatReg val) +OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val) { int idx = reg_idx + TheISA::FP_Base_DepTag; thread->renameTable[idx]->setDoubleResult(val); if (!thread->inSyscall) { - cpu->squashFromXC(); + cpu->squashFromTC(); } } template <class Impl> void -OzoneCPU<Impl>::OzoneXC::setFloatRegBits(int reg_idx, FloatRegBits val, +OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val, int width) { panic("Unimplemented!"); @@ -1016,45 +1016,45 @@ OzoneCPU<Impl>::OzoneXC::setFloatRegBits(int reg_idx, FloatRegBits val, template <class Impl> void -OzoneCPU<Impl>::OzoneXC::setFloatRegBits(int reg_idx, FloatRegBits val) +OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val) { panic("Unimplemented!"); } template <class Impl> void -OzoneCPU<Impl>::OzoneXC::setPC(Addr val) +OzoneCPU<Impl>::OzoneTC::setPC(Addr val) { thread->PC = val; cpu->frontEnd->setPC(val); if (!thread->inSyscall) { - cpu->squashFromXC(); + cpu->squashFromTC(); } } template <class Impl> void -OzoneCPU<Impl>::OzoneXC::setNextPC(Addr val) +OzoneCPU<Impl>::OzoneTC::setNextPC(Addr val) { thread->nextPC = val; cpu->frontEnd->setNextPC(val); if (!thread->inSyscall) { - cpu->squashFromXC(); + cpu->squashFromTC(); } } template <class Impl> TheISA::MiscReg -OzoneCPU<Impl>::OzoneXC::readMiscReg(int misc_reg) +OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg) { return thread->regs.miscRegs.readReg(misc_reg); } template <class Impl> TheISA::MiscReg -OzoneCPU<Impl>::OzoneXC::readMiscRegWithEffect(int misc_reg, Fault &fault) +OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg, Fault &fault) { return thread->regs.miscRegs.readRegWithEffect(misc_reg, fault, this); @@ -1062,13 +1062,13 @@ OzoneCPU<Impl>::OzoneXC::readMiscRegWithEffect(int misc_reg, Fault &fault) template <class Impl> Fault -OzoneCPU<Impl>::OzoneXC::setMiscReg(int misc_reg, const MiscReg &val) +OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val) { // Needs to setup a squash event unless we're in syscall mode Fault ret_fault = thread->regs.miscRegs.setReg(misc_reg, val); if (!thread->inSyscall) { - cpu->squashFromXC(); + cpu->squashFromTC(); } return ret_fault; @@ -1076,14 +1076,14 @@ OzoneCPU<Impl>::OzoneXC::setMiscReg(int misc_reg, const MiscReg &val) template <class Impl> Fault -OzoneCPU<Impl>::OzoneXC::setMiscRegWithEffect(int misc_reg, const MiscReg &val) +OzoneCPU<Impl>::OzoneTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val) { // Needs to setup a squash event unless we're in syscall mode Fault ret_fault = thread->regs.miscRegs.setRegWithEffect(misc_reg, val, this); if (!thread->inSyscall) { - cpu->squashFromXC(); + cpu->squashFromTC(); } return ret_fault; diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh index b3131149d..45ef6eb4b 100644 --- a/src/cpu/ozone/front_end.hh +++ b/src/cpu/ozone/front_end.hh @@ -38,7 +38,7 @@ #include "sim/eventq.hh" #include "sim/stats.hh" -class ExecContext; +class ThreadContext; class MemInterface; template <class> class OzoneThreadState; @@ -56,7 +56,7 @@ class FrontEnd typedef typename Impl::FullCPU FullCPU; typedef typename Impl::BackEnd BackEnd; - typedef typename Impl::FullCPU::OzoneXC OzoneXC; + typedef typename Impl::FullCPU::OzoneTC OzoneTC; typedef typename Impl::FullCPU::CommStruct CommStruct; FrontEnd(Params *params); @@ -71,7 +71,7 @@ class FrontEnd void setCommBuffer(TimeBuffer<CommStruct> *_comm); - void setXC(ExecContext *xc_ptr); + void setTC(ThreadContext *tc_ptr); void setThreadState(OzoneThreadState<Impl> *thread_ptr) { thread = thread_ptr; } @@ -95,7 +95,7 @@ class FrontEnd void doSwitchOut(); - void takeOverFrom(ExecContext *old_xc = NULL); + void takeOverFrom(ThreadContext *old_tc = NULL); bool isSwitchedOut() { return switchedOut; } @@ -132,7 +132,7 @@ class FrontEnd BackEnd *backEnd; - ExecContext *xc; + ThreadContext *tc; OzoneThreadState<Impl> *thread; diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index ffbcf3340..bf6a8c144 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -29,7 +29,7 @@ #include "arch/faults.hh" #include "arch/isa_traits.hh" #include "base/statistics.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/exetrace.hh" #include "cpu/ozone/front_end.hh" #include "mem/mem_interface.hh" @@ -93,9 +93,9 @@ FrontEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm) template <class Impl> void -FrontEnd<Impl>::setXC(ExecContext *xc_ptr) +FrontEnd<Impl>::setTC(ThreadContext *tc_ptr) { - xc = xc_ptr; + tc = tc_ptr; } template <class Impl> @@ -407,7 +407,7 @@ FrontEnd<Impl>::fetchCacheLine() memReq->asid = 0; memReq->thread_num = 0; memReq->data = new uint8_t[64]; - memReq->xc = xc; + memReq->tc = tc; memReq->cmd = Read; memReq->reset(fetch_PC, cacheBlkSize, flags); @@ -780,7 +780,7 @@ FrontEnd<Impl>::getInstFromCacheline() instruction->staticInst->disassemble(PC)); instruction->traceData = - Trace::getInstRecord(curTick, xc, cpu, + Trace::getInstRecord(curTick, tc, cpu, instruction->staticInst, instruction->readPC(), 0); @@ -862,7 +862,7 @@ FrontEnd<Impl>::doSwitchOut() template <class Impl> void -FrontEnd<Impl>::takeOverFrom(ExecContext *old_xc) +FrontEnd<Impl>::takeOverFrom(ThreadContext *old_tc) { assert(freeRegs == numPhysRegs); fetchCacheLineNextCycle = true; diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh index 578ae4ce2..aae2b1c32 100644 --- a/src/cpu/ozone/inorder_back_end.hh +++ b/src/cpu/ozone/inorder_back_end.hh @@ -6,7 +6,7 @@ #include "arch/faults.hh" #include "base/timebuf.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/inst_seq.hh" #include "cpu/ozone/rename_table.hh" #include "cpu/ozone/thread_state.hh" @@ -22,7 +22,7 @@ class InorderBackEnd typedef typename Impl::FullCPU FullCPU; typedef typename Impl::FrontEnd FrontEnd; - typedef typename FullCPU::OzoneXC OzoneXC; + typedef typename FullCPU::OzoneTC OzoneTC; typedef typename Impl::FullCPU::CommStruct CommStruct; InorderBackEnd(Params *params); @@ -38,7 +38,7 @@ class InorderBackEnd void setCommBuffer(TimeBuffer<CommStruct> *_comm) { comm = _comm; } - void setXC(ExecContext *xc_ptr); + void setTC(ThreadContext *tc_ptr); void setThreadState(OzoneThreadState<Impl> *thread_ptr); @@ -69,7 +69,7 @@ class InorderBackEnd private: void handleFault(); - void setSquashInfoFromXC(); + void setSquashInfoFromTC(); bool squashPending; InstSeqNum squashSeqNum; @@ -98,14 +98,14 @@ class InorderBackEnd void switchOut() { panic("Not implemented!"); } void doSwitchOut() { panic("Not implemented!"); } - void takeOverFrom(ExecContext *old_xc = NULL) { panic("Not implemented!"); } + void takeOverFrom(ThreadContext *old_tc = NULL) { panic("Not implemented!"); } public: FullCPU *cpu; FrontEnd *frontEnd; - ExecContext *xc; + ThreadContext *tc; OzoneThreadState<Impl> *thread; diff --git a/src/cpu/ozone/lw_back_end.hh b/src/cpu/ozone/lw_back_end.hh index 021381dd0..f0946b8d4 100644 --- a/src/cpu/ozone/lw_back_end.hh +++ b/src/cpu/ozone/lw_back_end.hh @@ -44,7 +44,7 @@ template <class> class Checker; -class ExecContext; +class ThreadContext; template <class Impl> class OzoneThreadState; @@ -126,8 +126,8 @@ class LWBackEnd void setFrontEnd(FrontEnd *front_end_ptr) { frontEnd = front_end_ptr; } - void setXC(ExecContext *xc_ptr) - { xc = xc_ptr; } + void setTC(ThreadContext *tc_ptr) + { tc = tc_ptr; } void setThreadState(Thread *thread_ptr) { thread = thread_ptr; } @@ -136,12 +136,12 @@ class LWBackEnd void tick(); void squash(); - void generateXCEvent() { xcSquash = true; } - void squashFromXC(); + void generateTCEvent() { tcSquash = true; } + void squashFromTC(); void squashFromTrap(); void checkInterrupts(); bool trapSquash; - bool xcSquash; + bool tcSquash; template <class T> Fault read(RequestPtr req, T &data, int load_idx); @@ -213,7 +213,7 @@ class LWBackEnd void switchOut(); void doSwitchOut(); - void takeOverFrom(ExecContext *old_xc = NULL); + void takeOverFrom(ThreadContext *old_tc = NULL); bool isSwitchedOut() { return switchedOut; } @@ -241,7 +241,7 @@ class LWBackEnd FrontEnd *frontEnd; - ExecContext *xc; + ThreadContext *tc; Thread *thread; diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh index 41b4ea24b..0f5c01c0d 100644 --- a/src/cpu/ozone/lw_back_end_impl.hh +++ b/src/cpu/ozone/lw_back_end_impl.hh @@ -209,7 +209,7 @@ LWBackEnd<Impl>::DCacheCompletionEvent::description() template <class Impl> LWBackEnd<Impl>::LWBackEnd(Params *params) : d2i(5, 5), i2e(5, 5), e2c(5, 5), numInstsToWB(5, 5), - trapSquash(false), xcSquash(false), cacheCompletionEvent(this), + trapSquash(false), tcSquash(false), cacheCompletionEvent(this), dcacheInterface(params->dcacheInterface), width(params->backEndWidth), exactFullStall(true) { @@ -592,7 +592,7 @@ LWBackEnd<Impl>::checkInterrupts() cpu->check_interrupts() && !cpu->inPalMode(thread->readPC()) && !trapSquash && - !xcSquash) { + !tcSquash) { frontEnd->interruptPending = true; if (robEmpty() && !LSQ.hasStoresToWB()) { // Will need to squash all instructions currently in flight and have @@ -637,7 +637,7 @@ LWBackEnd<Impl>::handleFault(Fault &fault, Tick latency) // Consider holding onto the trap and waiting until the trap event // happens for this to be executed. - fault->invoke(thread->getXCProxy()); + fault->invoke(thread->getTCProxy()); // Exit state update mode to avoid accidental updating. thread->inSyscall = false; @@ -671,10 +671,10 @@ LWBackEnd<Impl>::tick() checkInterrupts(); if (trapSquash) { - assert(!xcSquash); + assert(!tcSquash); squashFromTrap(); - } else if (xcSquash) { - squashFromXC(); + } else if (tcSquash) { + squashFromTC(); } #endif @@ -1257,12 +1257,12 @@ LWBackEnd<Impl>::commitInst(int inst_num) assert(!thread->inSyscall && !thread->trapPending); oldpc = thread->readPC(); cpu->system->pcEventQueue.service( - thread->getXCProxy()); + thread->getTCProxy()); count++; } while (oldpc != thread->readPC()); if (count > 1) { DPRINTF(BE, "PC skip function event, stopping commit\n"); - xcSquash = true; + tcSquash = true; return false; } #endif @@ -1396,7 +1396,7 @@ LWBackEnd<Impl>::squash(const InstSeqNum &sn) template <class Impl> void -LWBackEnd<Impl>::squashFromXC() +LWBackEnd<Impl>::squashFromTC() { InstSeqNum squashed_inst = robEmpty() ? 0 : instList.back()->seqNum - 1; squash(squashed_inst); @@ -1406,7 +1406,7 @@ LWBackEnd<Impl>::squashFromXC() thread->trapPending = false; thread->inSyscall = false; - xcSquash = false; + tcSquash = false; commitStatus = Running; } @@ -1483,7 +1483,7 @@ LWBackEnd<Impl>::doSwitchOut() switchedOut = true; switchPending = false; // Need to get rid of all committed, non-speculative state and write it - // to memory/XC. In this case this is stores that have committed and not + // to memory/TC. In this case this is stores that have committed and not // yet written back. assert(robEmpty()); assert(!LSQ.hasStoresToWB()); @@ -1495,7 +1495,7 @@ LWBackEnd<Impl>::doSwitchOut() template <class Impl> void -LWBackEnd<Impl>::takeOverFrom(ExecContext *old_xc) +LWBackEnd<Impl>::takeOverFrom(ThreadContext *old_xc) { switchedOut = false; xcSquash = false; diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh index e1488dd6f..d27fa565c 100644 --- a/src/cpu/ozone/lw_lsq.hh +++ b/src/cpu/ozone/lw_lsq.hh @@ -234,7 +234,7 @@ class OzoneLWLSQ { void switchOut(); - void takeOverFrom(ExecContext *old_xc = NULL); + void takeOverFrom(ThreadContext *old_tc = NULL); bool isSwitchedOut() { return switchedOut; } diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh index f72bbb1cc..0841e0b57 100644 --- a/src/cpu/ozone/lw_lsq_impl.hh +++ b/src/cpu/ozone/lw_lsq_impl.hh @@ -846,7 +846,7 @@ OzoneLWLSQ<Impl>::switchOut() template <class Impl> void -OzoneLWLSQ<Impl>::takeOverFrom(ExecContext *old_xc) +OzoneLWLSQ<Impl>::takeOverFrom(ThreadContext *old_tc) { // Clear out any old state. May be redundant if this is the first time // the CPU is being used. diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh index 9b5433815..c91297e73 100644 --- a/src/cpu/ozone/thread_state.hh +++ b/src/cpu/ozone/thread_state.hh @@ -31,7 +31,7 @@ #include "arch/faults.hh" #include "arch/isa_traits.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/thread_state.hh" #include "sim/process.hh" @@ -52,10 +52,10 @@ class FunctionalMemory; // has benefits for SMT; basically serves same use as CPUExecContext. // Makes the ExecContext proxy easier. Gives organization/central access point // to state of a thread that can be accessed normally (i.e. not in-flight -// stuff within a OoO processor). Does this need an XC proxy within it? +// stuff within a OoO processor). Does this need an TC proxy within it? template <class Impl> struct OzoneThreadState : public ThreadState { - typedef typename ExecContext::Status Status; + typedef typename ThreadContext::Status Status; typedef typename Impl::FullCPU FullCPU; typedef TheISA::MiscReg MiscReg; @@ -104,9 +104,9 @@ struct OzoneThreadState : public ThreadState { bool trapPending; - ExecContext *xcProxy; + ThreadContext *tc; - ExecContext *getXCProxy() { return xcProxy; } + ThreadContext *getTC() { return tc; } #if !FULL_SYSTEM Fault translateInstReq(Request *req) @@ -145,7 +145,7 @@ struct OzoneThreadState : public ThreadState { MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) { - return regs.readMiscRegWithEffect(misc_reg, fault, xcProxy); + return regs.readMiscRegWithEffect(misc_reg, fault, tc); } Fault setMiscReg(int misc_reg, const MiscReg &val) @@ -155,7 +155,7 @@ struct OzoneThreadState : public ThreadState { Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - return regs.setMiscRegWithEffect(misc_reg, val, xcProxy); + return regs.setMiscRegWithEffect(misc_reg, val, tc); } uint64_t readPC() diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc index ad94a8457..fca357fe3 100644 --- a/src/cpu/pc_event.cc +++ b/src/cpu/pc_event.cc @@ -37,7 +37,7 @@ #include "base/trace.hh" #include "config/full_system.hh" #include "cpu/base.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/pc_event.hh" #include "sim/debug.hh" #include "sim/root.hh" @@ -81,9 +81,9 @@ PCEventQueue::schedule(PCEvent *event) } bool -PCEventQueue::doService(ExecContext *xc) +PCEventQueue::doService(ThreadContext *tc) { - Addr pc = xc->readPC() & ~0x3; + Addr pc = tc->readPC() & ~0x3; int serviced = 0; range_t range = equal_range(pc); for (iterator i = range.first; i != range.second; ++i) { @@ -91,13 +91,13 @@ PCEventQueue::doService(ExecContext *xc) // another event. This for example, prevents two invocations // of the SkipFuncEvent. Maybe we should have separate PC // event queues for each processor? - if (pc != (xc->readPC() & ~0x3)) + if (pc != (tc->readPC() & ~0x3)) continue; DPRINTF(PCEvent, "PC based event serviced at %#x: %s\n", (*i)->pc(), (*i)->descr()); - (*i)->process(xc); + (*i)->process(tc); ++serviced; } @@ -128,9 +128,9 @@ BreakPCEvent::BreakPCEvent(PCEventQueue *q, const std::string &desc, Addr addr, } void -BreakPCEvent::process(ExecContext *xc) +BreakPCEvent::process(ThreadContext *tc) { - StringWrap name(xc->getCpuPtr()->name() + ".break_event"); + StringWrap name(tc->getCpuPtr()->name() + ".break_event"); DPRINTFN("break event %s triggered\n", descr()); debug_break(); if (remove) diff --git a/src/cpu/pc_event.hh b/src/cpu/pc_event.hh index 819472391..6b048b2c2 100644 --- a/src/cpu/pc_event.hh +++ b/src/cpu/pc_event.hh @@ -36,7 +36,7 @@ #include "base/misc.hh" -class ExecContext; +class ThreadContext; class PCEventQueue; class PCEvent @@ -58,7 +58,7 @@ class PCEvent Addr pc() const { return evpc; } bool remove(); - virtual void process(ExecContext *xc) = 0; + virtual void process(ThreadContext *tc) = 0; }; class PCEventQueue @@ -90,7 +90,7 @@ class PCEventQueue protected: map_t pc_map; - bool doService(ExecContext *xc); + bool doService(ThreadContext *tc); public: PCEventQueue(); @@ -98,12 +98,12 @@ class PCEventQueue bool remove(PCEvent *event); bool schedule(PCEvent *event); - bool service(ExecContext *xc) + bool service(ThreadContext *tc) { if (pc_map.empty()) return false; - return doService(xc); + return doService(tc); } range_t equal_range(Addr pc); @@ -137,7 +137,7 @@ class BreakPCEvent : public PCEvent public: BreakPCEvent(PCEventQueue *q, const std::string &desc, Addr addr, bool del = false); - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; #endif // __PC_EVENT_HH__ diff --git a/src/cpu/profile.cc b/src/cpu/profile.cc index 5f6ca53c3..4f04615e9 100644 --- a/src/cpu/profile.cc +++ b/src/cpu/profile.cc @@ -36,7 +36,7 @@ #include "base/trace.hh" #include "base/loader/symtab.hh" #include "cpu/base.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/profile.hh" using namespace std; @@ -120,7 +120,7 @@ FunctionProfile::clear() } void -FunctionProfile::dump(ExecContext *xc, ostream &os) const +FunctionProfile::dump(ThreadContext *tc, ostream &os) const { ccprintf(os, ">>>PC data\n"); map<Addr, Counter>::const_iterator i, end = pc_count.end(); diff --git a/src/cpu/profile.hh b/src/cpu/profile.hh index 8f5be4001..7f9625241 100644 --- a/src/cpu/profile.hh +++ b/src/cpu/profile.hh @@ -37,7 +37,7 @@ #include "sim/host.hh" #include "arch/stacktrace.hh" -class ExecContext; +class ThreadContext; class ProfileNode { @@ -72,17 +72,17 @@ class FunctionProfile FunctionProfile(const SymbolTable *symtab); ~FunctionProfile(); - ProfileNode *consume(ExecContext *xc, StaticInstPtr inst); + ProfileNode *consume(ThreadContext *tc, StaticInstPtr inst); ProfileNode *consume(const std::vector<Addr> &stack); void clear(); - void dump(ExecContext *xc, std::ostream &out) const; + void dump(ThreadContext *tc, std::ostream &out) const; void sample(ProfileNode *node, Addr pc); }; inline ProfileNode * -FunctionProfile::consume(ExecContext *xc, StaticInstPtr inst) +FunctionProfile::consume(ThreadContext *tc, StaticInstPtr inst) { - if (!trace.trace(xc, inst)) + if (!trace.trace(tc, inst)) return NULL; trace.dprintf(); return consume(trace.getstack()); diff --git a/src/cpu/quiesce_event.cc b/src/cpu/quiesce_event.cc index 37814ae09..664a7aa01 100644 --- a/src/cpu/quiesce_event.cc +++ b/src/cpu/quiesce_event.cc @@ -1,16 +1,16 @@ -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/quiesce_event.hh" -EndQuiesceEvent::EndQuiesceEvent(ExecContext *_xc) - : Event(&mainEventQueue), xc(_xc) +EndQuiesceEvent::EndQuiesceEvent(ThreadContext *_tc) + : Event(&mainEventQueue), tc(_tc) { } void EndQuiesceEvent::process() { - xc->activate(); + tc->activate(); } const char* diff --git a/src/cpu/quiesce_event.hh b/src/cpu/quiesce_event.hh index 18e88ecce..cc6adf828 100644 --- a/src/cpu/quiesce_event.hh +++ b/src/cpu/quiesce_event.hh @@ -3,15 +3,15 @@ #include "sim/eventq.hh" -class ExecContext; +class ThreadContext; /** Event for timing out quiesce instruction */ struct EndQuiesceEvent : public Event { - /** A pointer to the execution context that is quiesced */ - ExecContext *xc; + /** A pointer to the thread context that is quiesced */ + ThreadContext *tc; - EndQuiesceEvent(ExecContext *_xc); + EndQuiesceEvent(ThreadContext *_tc); /** Event process to occur at interrupt*/ virtual void process(); diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 2d47f9624..91ac0b6a5 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -70,11 +70,11 @@ AtomicSimpleCPU::init() BaseCPU::init(); #if FULL_SYSTEM - for (int i = 0; i < execContexts.size(); ++i) { - ExecContext *xc = execContexts[i]; + for (int i = 0; i < threadContexts.size(); ++i) { + ThreadContext *tc = threadContexts[i]; // initialize CPU, including PC - TheISA::initCPU(xc, xc->readCpuId()); + TheISA::initCPU(tc, tc->readCpuId()); } #endif } @@ -179,11 +179,11 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) assert(!tickEvent.scheduled()); - // if any of this CPU's ExecContexts are active, mark the CPU as + // if any of this CPU's ThreadContexts are active, mark the CPU as // running and schedule its tick event. - for (int i = 0; i < execContexts.size(); ++i) { - ExecContext *xc = execContexts[i]; - if (xc->status() == ExecContext::Active && _status != Running) { + for (int i = 0; i < threadContexts.size(); ++i) { + ThreadContext *tc = threadContexts[i]; + if (tc->status() == ThreadContext::Active && _status != Running) { _status = Running; tickEvent.schedule(curTick); break; diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 12fb4f165..d36aa93a2 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -39,7 +39,7 @@ #include "base/trace.hh" #include "cpu/base.hh" #include "cpu/cpu_exec_context.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/exetrace.hh" #include "cpu/profile.hh" #include "cpu/sampler/sampler.hh" @@ -79,9 +79,9 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p) /* asid */ 0, mem); #endif // !FULL_SYSTEM - cpuXC->setStatus(ExecContext::Suspended); + cpuXC->setStatus(ThreadContext::Suspended); - xcProxy = cpuXC->getProxy(); + tc = cpuXC->getTC(); numInst = 0; startNumInst = 0; @@ -90,7 +90,7 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p) lastIcacheStall = 0; lastDcacheStall = 0; - execContexts.push_back(xcProxy); + threadContexts.push_back(tc); } BaseSimpleCPU::~BaseSimpleCPU() @@ -290,7 +290,7 @@ BaseSimpleCPU::copy(Addr dest) Addr BaseSimpleCPU::dbg_vtophys(Addr addr) { - return vtophys(xcProxy, addr); + return vtophys(tc, addr); } #endif // FULL_SYSTEM @@ -300,7 +300,7 @@ BaseSimpleCPU::post_interrupt(int int_num, int index) { BaseCPU::post_interrupt(int_num, index); - if (cpuXC->status() == ExecContext::Suspended) { + if (cpuXC->status() == ThreadContext::Suspended) { DPRINTF(IPI,"Suspended Processor awoke\n"); cpuXC->activate(); } @@ -344,7 +344,7 @@ BaseSimpleCPU::checkForInterrupts() cpuXC->setMiscReg(IPR_ISR, summary); cpuXC->setMiscReg(IPR_INTID, ipl); - Fault(new InterruptFault)->invoke(xcProxy); + Fault(new InterruptFault)->invoke(tc); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", cpuXC->readMiscReg(IPR_IPLR), ipl, summary); @@ -393,7 +393,7 @@ BaseSimpleCPU::preExecute() inst = gtoh(inst); curStaticInst = StaticInst::decode(makeExtMI(inst, cpuXC->readPC())); - traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst, + traceData = Trace::getInstRecord(curTick, tc, this, curStaticInst, cpuXC->readPC()); DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n", @@ -411,14 +411,14 @@ BaseSimpleCPU::postExecute() #if FULL_SYSTEM if (system->kernelBinning->fnbin) { assert(cpuXC->getKernelStats()); - system->kernelBinning->execute(xcProxy, inst); + system->kernelBinning->execute(tc, inst); } if (cpuXC->profile) { bool usermode = (cpuXC->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; cpuXC->profilePC = usermode ? 1 : cpuXC->readPC(); - ProfileNode *node = cpuXC->profile->consume(xcProxy, inst); + ProfileNode *node = cpuXC->profile->consume(tc, inst); if (node) cpuXC->profileNode = node; } @@ -446,7 +446,7 @@ BaseSimpleCPU::advancePC(Fault fault) { if (fault != NoFault) { #if FULL_SYSTEM - fault->invoke(xcProxy); + fault->invoke(tc); #else // !FULL_SYSTEM fatal("fault (%s) detected @ PC %08p", fault->name(), cpuXC->readPC()); #endif // FULL_SYSTEM @@ -467,7 +467,7 @@ BaseSimpleCPU::advancePC(Fault fault) Addr oldpc; do { oldpc = cpuXC->readPC(); - system->pcEventQueue.service(xcProxy); + system->pcEventQueue.service(tc); } while (oldpc != cpuXC->readPC()); #endif } diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index e7d90f95d..bc17ece56 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -61,7 +61,7 @@ class Process; #endif // FULL_SYSTEM -class ExecContext; +class ThreadContext; class Checkpoint; namespace Trace { @@ -111,7 +111,7 @@ class BaseSimpleCPU : public BaseCPU // execution context CPUExecContext *cpuXC; - ExecContext *xcProxy; + ThreadContext *tc; #if FULL_SYSTEM Addr dbg_vtophys(Addr addr); @@ -307,14 +307,14 @@ class BaseSimpleCPU : public BaseCPU int readIntrFlag() { return cpuXC->readIntrFlag(); } void setIntrFlag(int val) { cpuXC->setIntrFlag(val); } bool inPalMode() { return cpuXC->inPalMode(); } - void ev5_trap(Fault fault) { fault->invoke(xcProxy); } + void ev5_trap(Fault fault) { fault->invoke(tc); } bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); } #else void syscall(int64_t callnum) { cpuXC->syscall(callnum); } #endif bool misspeculating() { return cpuXC->misspeculating(); } - ExecContext *xcBase() { return xcProxy; } + ThreadContext *tcBase() { return tc; } }; #endif // __CPU_SIMPLE_BASE_HH__ diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 1e5a628c7..00c6de037 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -52,11 +52,11 @@ TimingSimpleCPU::init() BaseCPU::init(); #if FULL_SYSTEM - for (int i = 0; i < execContexts.size(); ++i) { - ExecContext *xc = execContexts[i]; + for (int i = 0; i < threadContexts.size(); ++i) { + ThreadContext *tc = threadContexts[i]; // initialize CPU, including PC - TheISA::initCPU(xc, xc->readCpuId()); + TheISA::initCPU(tc, tc->readCpuId()); } #endif } @@ -125,11 +125,11 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) { BaseCPU::takeOverFrom(oldCPU); - // if any of this CPU's ExecContexts are active, mark the CPU as + // if any of this CPU's ThreadContexts are active, mark the CPU as // running and schedule its tick event. - for (int i = 0; i < execContexts.size(); ++i) { - ExecContext *xc = execContexts[i]; - if (xc->status() == ExecContext::Active && _status != Running) { + for (int i = 0; i < threadContexts.size(); ++i) { + ThreadContext *tc = threadContexts[i]; + if (tc->status() == ThreadContext::Active && _status != Running) { _status = Running; break; } diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc index 86517a5f4..c311d2282 100644 --- a/src/cpu/static_inst.cc +++ b/src/cpu/static_inst.cc @@ -60,7 +60,7 @@ StaticInst::dumpDecodeCacheStats() } bool -StaticInst::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const +StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const { if (isDirectCtrl()) { tgt = branchTarget(pc); @@ -68,7 +68,7 @@ StaticInst::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const } if (isIndirectCtrl()) { - tgt = branchTarget(xc); + tgt = branchTarget(tc); return true; } diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index 6f6cf45da..bea52f510 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -45,7 +45,7 @@ struct AlphaSimpleImpl; struct OzoneImpl; struct SimpleImpl; -class ExecContext; +class ThreadContext; class DynInst; class Packet; @@ -357,12 +357,12 @@ class StaticInst : public StaticInstBase /** * Return the target address for an indirect branch (jump). The - * register value is read from the supplied execution context, so - * the result is valid only if the execution context is about to + * register value is read from the supplied thread context, so + * the result is valid only if the thread context is about to * execute the branch in question. Invalid if not an indirect * branch (i.e. isIndirectCtrl() should be true). */ - virtual Addr branchTarget(ExecContext *xc) const + virtual Addr branchTarget(ThreadContext *tc) const { panic("StaticInst::branchTarget() called on instruction " "that is not an indirect branch."); @@ -372,7 +372,7 @@ class StaticInst : public StaticInstBase * Return true if the instruction is a control transfer, and if so, * return the target address as well. */ - bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const; + bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const; /** * Return string representation of disassembled instruction. diff --git a/src/cpu/exec_context.hh b/src/cpu/thread_context.hh index c9a060b0b..ac2b44ba8 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/thread_context.hh @@ -28,8 +28,8 @@ * Authors: Kevin Lim */ -#ifndef __CPU_EXEC_CONTEXT_HH__ -#define __CPU_EXEC_CONTEXT_HH__ +#ifndef __CPU_THREAD_CONTEXT_HH__ +#define __CPU_THREAD_CONTEXT_HH__ #include "config/full_system.hh" #include "mem/request.hh" @@ -54,7 +54,23 @@ namespace Kernel { class Statistics; }; -class ExecContext +/** + * ThreadContext is the external interface to all thread state for + * anything outside of the CPU. It provides all accessor methods to + * state that might be needed by external objects, ranging from + * register values to things such as kernel stats. It is an abstract + * base class; the CPU can create its own ThreadContext by either + * deriving from it, or using the templated ProxyThreadContext. + * + * The ThreadContext is slightly different than the ExecContext. The + * ThreadContext provides access to an individual thread's state; an + * ExecContext provides ISA access to the CPU (meaning it is + * implicitly multithreaded on MT systems). Additionally the + * ThreadState is an abstract class that exactly defines the + * interface; the ExecContext is a more implicit interface that must + * be implemented so that the ISA can access whatever state it needs. + */ +class ThreadContext { protected: typedef TheISA::RegFile RegFile; @@ -87,7 +103,7 @@ class ExecContext Halted }; - virtual ~ExecContext() { }; + virtual ~ThreadContext() { }; virtual BaseCPU *getCpuPtr() = 0; @@ -106,7 +122,7 @@ class ExecContext virtual FunctionalPort *getPhysPort() = 0; - virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0; + virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0; virtual void delVirtPort(VirtualPort *vp) = 0; #else @@ -136,7 +152,7 @@ class ExecContext virtual void dumpFuncProfile() = 0; #endif - virtual void takeOverFrom(ExecContext *old_context) = 0; + virtual void takeOverFrom(ThreadContext *old_context) = 0; virtual void regStats(const std::string &name) = 0; @@ -161,7 +177,7 @@ class ExecContext // However, may be quite useful in SPARC. virtual TheISA::MachInst getInst() = 0; - virtual void copyArchRegs(ExecContext *xc) = 0; + virtual void copyArchRegs(ThreadContext *tc) = 0; virtual void clearArchRegs() = 0; @@ -238,181 +254,181 @@ class ExecContext RegFile::ContextVal val) = 0; }; -template <class XC> -class ProxyExecContext : public ExecContext +template <class TC> +class ProxyThreadContext : public ThreadContext { public: - ProxyExecContext(XC *actual_xc) - { actualXC = actual_xc; } + ProxyThreadContext(TC *actual_tc) + { actualTC = actual_tc; } private: - XC *actualXC; + TC *actualTC; public: - BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); } + BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } - void setCpuId(int id) { actualXC->setCpuId(id); } + void setCpuId(int id) { actualTC->setCpuId(id); } - int readCpuId() { return actualXC->readCpuId(); } + int readCpuId() { return actualTC->readCpuId(); } #if FULL_SYSTEM - System *getSystemPtr() { return actualXC->getSystemPtr(); } + System *getSystemPtr() { return actualTC->getSystemPtr(); } - AlphaITB *getITBPtr() { return actualXC->getITBPtr(); } + AlphaITB *getITBPtr() { return actualTC->getITBPtr(); } - AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); } + AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); } - Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); } + Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } - FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); } + FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } - VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); } + VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); } - void delVirtPort(VirtualPort *vp) { return actualXC->delVirtPort(vp); } + void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); } #else - TranslatingPort *getMemPort() { return actualXC->getMemPort(); } + TranslatingPort *getMemPort() { return actualTC->getMemPort(); } - Process *getProcessPtr() { return actualXC->getProcessPtr(); } + Process *getProcessPtr() { return actualTC->getProcessPtr(); } #endif - Status status() const { return actualXC->status(); } + Status status() const { return actualTC->status(); } - void setStatus(Status new_status) { actualXC->setStatus(new_status); } + void setStatus(Status new_status) { actualTC->setStatus(new_status); } /// Set the status to Active. Optional delay indicates number of /// cycles to wait before beginning execution. - void activate(int delay = 1) { actualXC->activate(delay); } + void activate(int delay = 1) { actualTC->activate(delay); } /// Set the status to Suspended. - void suspend() { actualXC->suspend(); } + void suspend() { actualTC->suspend(); } /// Set the status to Unallocated. - void deallocate() { actualXC->deallocate(); } + void deallocate() { actualTC->deallocate(); } /// Set the status to Halted. - void halt() { actualXC->halt(); } + void halt() { actualTC->halt(); } #if FULL_SYSTEM - void dumpFuncProfile() { actualXC->dumpFuncProfile(); } + void dumpFuncProfile() { actualTC->dumpFuncProfile(); } #endif - void takeOverFrom(ExecContext *oldContext) - { actualXC->takeOverFrom(oldContext); } + void takeOverFrom(ThreadContext *oldContext) + { actualTC->takeOverFrom(oldContext); } - void regStats(const std::string &name) { actualXC->regStats(name); } + void regStats(const std::string &name) { actualTC->regStats(name); } - void serialize(std::ostream &os) { actualXC->serialize(os); } + void serialize(std::ostream &os) { actualTC->serialize(os); } void unserialize(Checkpoint *cp, const std::string §ion) - { actualXC->unserialize(cp, section); } + { actualTC->unserialize(cp, section); } #if FULL_SYSTEM - EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); } + EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } - Tick readLastActivate() { return actualXC->readLastActivate(); } - Tick readLastSuspend() { return actualXC->readLastSuspend(); } + Tick readLastActivate() { return actualTC->readLastActivate(); } + Tick readLastSuspend() { return actualTC->readLastSuspend(); } - void profileClear() { return actualXC->profileClear(); } - void profileSample() { return actualXC->profileSample(); } + void profileClear() { return actualTC->profileClear(); } + void profileSample() { return actualTC->profileSample(); } #endif - int getThreadNum() { return actualXC->getThreadNum(); } + int getThreadNum() { return actualTC->getThreadNum(); } // @todo: Do I need this? - MachInst getInst() { return actualXC->getInst(); } + MachInst getInst() { return actualTC->getInst(); } // @todo: Do I need this? - void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); } + void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } - void clearArchRegs() { actualXC->clearArchRegs(); } + void clearArchRegs() { actualTC->clearArchRegs(); } // // New accessors for new decoder. // uint64_t readIntReg(int reg_idx) - { return actualXC->readIntReg(reg_idx); } + { return actualTC->readIntReg(reg_idx); } FloatReg readFloatReg(int reg_idx, int width) - { return actualXC->readFloatReg(reg_idx, width); } + { return actualTC->readFloatReg(reg_idx, width); } FloatReg readFloatReg(int reg_idx) - { return actualXC->readFloatReg(reg_idx); } + { return actualTC->readFloatReg(reg_idx); } FloatRegBits readFloatRegBits(int reg_idx, int width) - { return actualXC->readFloatRegBits(reg_idx, width); } + { return actualTC->readFloatRegBits(reg_idx, width); } FloatRegBits readFloatRegBits(int reg_idx) - { return actualXC->readFloatRegBits(reg_idx); } + { return actualTC->readFloatRegBits(reg_idx); } void setIntReg(int reg_idx, uint64_t val) - { actualXC->setIntReg(reg_idx, val); } + { actualTC->setIntReg(reg_idx, val); } void setFloatReg(int reg_idx, FloatReg val, int width) - { actualXC->setFloatReg(reg_idx, val, width); } + { actualTC->setFloatReg(reg_idx, val, width); } void setFloatReg(int reg_idx, FloatReg val) - { actualXC->setFloatReg(reg_idx, val); } + { actualTC->setFloatReg(reg_idx, val); } void setFloatRegBits(int reg_idx, FloatRegBits val, int width) - { actualXC->setFloatRegBits(reg_idx, val, width); } + { actualTC->setFloatRegBits(reg_idx, val, width); } void setFloatRegBits(int reg_idx, FloatRegBits val) - { actualXC->setFloatRegBits(reg_idx, val); } + { actualTC->setFloatRegBits(reg_idx, val); } - uint64_t readPC() { return actualXC->readPC(); } + uint64_t readPC() { return actualTC->readPC(); } - void setPC(uint64_t val) { actualXC->setPC(val); } + void setPC(uint64_t val) { actualTC->setPC(val); } - uint64_t readNextPC() { return actualXC->readNextPC(); } + uint64_t readNextPC() { return actualTC->readNextPC(); } - void setNextPC(uint64_t val) { actualXC->setNextPC(val); } + void setNextPC(uint64_t val) { actualTC->setNextPC(val); } - uint64_t readNextNPC() { return actualXC->readNextNPC(); } + uint64_t readNextNPC() { return actualTC->readNextNPC(); } - void setNextNPC(uint64_t val) { actualXC->setNextNPC(val); } + void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } MiscReg readMiscReg(int misc_reg) - { return actualXC->readMiscReg(misc_reg); } + { return actualTC->readMiscReg(misc_reg); } MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) - { return actualXC->readMiscRegWithEffect(misc_reg, fault); } + { return actualTC->readMiscRegWithEffect(misc_reg, fault); } Fault setMiscReg(int misc_reg, const MiscReg &val) - { return actualXC->setMiscReg(misc_reg, val); } + { return actualTC->setMiscReg(misc_reg, val); } Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) - { return actualXC->setMiscRegWithEffect(misc_reg, val); } + { return actualTC->setMiscRegWithEffect(misc_reg, val); } unsigned readStCondFailures() - { return actualXC->readStCondFailures(); } + { return actualTC->readStCondFailures(); } void setStCondFailures(unsigned sc_failures) - { actualXC->setStCondFailures(sc_failures); } + { actualTC->setStCondFailures(sc_failures); } #if FULL_SYSTEM - bool inPalMode() { return actualXC->inPalMode(); } + bool inPalMode() { return actualTC->inPalMode(); } #endif // @todo: Fix this! - bool misspeculating() { return actualXC->misspeculating(); } + bool misspeculating() { return actualTC->misspeculating(); } #if !FULL_SYSTEM - IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); } + IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } // used to shift args for indirect syscall void setSyscallArg(int i, IntReg val) - { actualXC->setSyscallArg(i, val); } + { actualTC->setSyscallArg(i, val); } void setSyscallReturn(SyscallReturn return_value) - { actualXC->setSyscallReturn(return_value); } + { actualTC->setSyscallReturn(return_value); } - Counter readFuncExeInst() { return actualXC->readFuncExeInst(); } + Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } #endif void changeRegFileContext(RegFile::ContextParam param, RegFile::ContextVal val) { - actualXC->changeRegFileContext(param, val); + actualTC->changeRegFileContext(param, val); } }; diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index a96884d5b..6d64c94f7 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -29,7 +29,7 @@ #ifndef __CPU_THREAD_STATE_HH__ #define __CPU_THREAD_STATE_HH__ -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #if !FULL_SYSTEM #include "mem/translating_port.hh" @@ -78,7 +78,7 @@ struct ThreadState { #endif } - ExecContext::Status status; + ThreadContext::Status status; int cpuId; diff --git a/src/dev/alpha_console.cc b/src/dev/alpha_console.cc index aa3261f01..181bbf934 100644 --- a/src/dev/alpha_console.cc +++ b/src/dev/alpha_console.cc @@ -43,7 +43,7 @@ #include "base/str.hh" #include "base/trace.hh" #include "cpu/base.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "dev/alpha_console.hh" #include "dev/platform.hh" #include "dev/simconsole.hh" diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc index 1f2fea418..decffaf73 100644 --- a/src/dev/ns_gige.cc +++ b/src/dev/ns_gige.cc @@ -37,7 +37,7 @@ #include "arch/alpha/ev5.hh" #include "base/inet.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "dev/etherlink.hh" #include "dev/ns_gige.hh" #include "dev/pciconfigall.hh" diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index d186c0036..a0223733b 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -33,7 +33,7 @@ #include <string> #include "base/inet.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/intr_control.hh" #include "dev/etherlink.hh" #include "dev/sinic.hh" diff --git a/src/dev/tsunami_cchip.cc b/src/dev/tsunami_cchip.cc index e4be98642..3feb7439f 100644 --- a/src/dev/tsunami_cchip.cc +++ b/src/dev/tsunami_cchip.cc @@ -43,7 +43,7 @@ #include "dev/tsunamireg.h" #include "dev/tsunami.hh" #include "mem/port.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/intr_control.hh" #include "sim/builder.hh" #include "sim/system.hh" @@ -368,7 +368,7 @@ TsunamiCChip::write(Packet *pkt) void TsunamiCChip::clearIPI(uint64_t ipintr) { - int numcpus = tsunami->intrctrl->cpu->system->execContexts.size(); + int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size(); assert(numcpus <= Tsunami::Max_CPUs); if (ipintr) { @@ -394,7 +394,7 @@ TsunamiCChip::clearIPI(uint64_t ipintr) void TsunamiCChip::clearITI(uint64_t itintr) { - int numcpus = tsunami->intrctrl->cpu->system->execContexts.size(); + int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size(); assert(numcpus <= Tsunami::Max_CPUs); if (itintr) { @@ -414,7 +414,7 @@ TsunamiCChip::clearITI(uint64_t itintr) void TsunamiCChip::reqIPI(uint64_t ipreq) { - int numcpus = tsunami->intrctrl->cpu->system->execContexts.size(); + int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size(); assert(numcpus <= Tsunami::Max_CPUs); if (ipreq) { @@ -441,7 +441,7 @@ TsunamiCChip::reqIPI(uint64_t ipreq) void TsunamiCChip::postRTC() { - int size = tsunami->intrctrl->cpu->system->execContexts.size(); + int size = tsunami->intrctrl->cpu->system->threadContexts.size(); assert(size <= Tsunami::Max_CPUs); for (int i = 0; i < size; i++) { @@ -459,7 +459,7 @@ void TsunamiCChip::postDRIR(uint32_t interrupt) { uint64_t bitvector = ULL(1) << interrupt; - uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size(); + uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size(); assert(size <= Tsunami::Max_CPUs); drir |= bitvector; @@ -477,7 +477,7 @@ void TsunamiCChip::clearDRIR(uint32_t interrupt) { uint64_t bitvector = ULL(1) << interrupt; - uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size(); + uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size(); assert(size <= Tsunami::Max_CPUs); if (drir & bitvector) diff --git a/src/kern/kernel_stats.cc b/src/kern/kernel_stats.cc index 7927ad931..2ba120b6f 100644 --- a/src/kern/kernel_stats.cc +++ b/src/kern/kernel_stats.cc @@ -35,7 +35,7 @@ #include "arch/alpha/osfpal.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/kernel_stats.hh" #include "kern/tru64/tru64_syscalls.hh" #include "sim/system.hh" @@ -184,16 +184,16 @@ Statistics::regStats(const string &_name) } void -Statistics::setIdleProcess(Addr idlepcbb, ExecContext *xc) +Statistics::setIdleProcess(Addr idlepcbb, ThreadContext *tc) { assert(themode == kernel || themode == interrupt); idleProcess = idlepcbb; themode = idle; - changeMode(themode, xc); + changeMode(themode, tc); } void -Statistics::changeMode(cpu_mode newmode, ExecContext *xc) +Statistics::changeMode(cpu_mode newmode, ThreadContext *tc) { _mode[newmode]++; @@ -206,7 +206,7 @@ Statistics::changeMode(cpu_mode newmode, ExecContext *xc) _modeGood[newmode]++; _modeTicks[themode] += curTick - lastModeTick; - xc->getSystemPtr()->kernelBinning->changeMode(newmode); + tc->getSystemPtr()->kernelBinning->changeMode(newmode); lastModeTick = curTick; themode = newmode; @@ -229,9 +229,9 @@ Statistics::swpipl(int ipl) } void -Statistics::mode(cpu_mode newmode, ExecContext *xc) +Statistics::mode(cpu_mode newmode, ThreadContext *tc) { - Addr pcbb = xc->readMiscReg(AlphaISA::IPR_PALtemp23); + Addr pcbb = tc->readMiscReg(AlphaISA::IPR_PALtemp23); if ((newmode == kernel || newmode == interrupt) && pcbb == idleProcess) @@ -240,20 +240,20 @@ Statistics::mode(cpu_mode newmode, ExecContext *xc) if (bin_int == false && newmode == interrupt) newmode = kernel; - changeMode(newmode, xc); + changeMode(newmode, tc); } void -Statistics::context(Addr oldpcbb, Addr newpcbb, ExecContext *xc) +Statistics::context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc) { assert(themode != user); _swap_context++; - changeMode(newpcbb == idleProcess ? idle : kernel, xc); + changeMode(newpcbb == idleProcess ? idle : kernel, tc); } void -Statistics::callpal(int code, ExecContext *xc) +Statistics::callpal(int code, ThreadContext *tc) { if (!PAL::name(code)) return; @@ -262,7 +262,7 @@ Statistics::callpal(int code, ExecContext *xc) switch (code) { case PAL::callsys: { - int number = xc->readIntReg(0); + int number = tc->readIntReg(0); if (SystemCalls<Tru64>::validSyscallNumber(number)) { int cvtnum = SystemCalls<Tru64>::convert(number); _syscall[cvtnum]++; @@ -270,8 +270,8 @@ Statistics::callpal(int code, ExecContext *xc) } break; case PAL::swpctx: - if (xc->getSystemPtr()->kernelBinning) - xc->getSystemPtr()->kernelBinning->palSwapContext(xc); + if (tc->getSystemPtr()->kernelBinning) + tc->getSystemPtr()->kernelBinning->palSwapContext(tc); break; } } diff --git a/src/kern/kernel_stats.hh b/src/kern/kernel_stats.hh index 5e2c7daf8..781b6f6da 100644 --- a/src/kern/kernel_stats.hh +++ b/src/kern/kernel_stats.hh @@ -40,7 +40,7 @@ #include "cpu/static_inst.hh" class BaseCPU; -class ExecContext; +class ThreadContext; class FnEvent; // What does kernel stats expect is included? class System; @@ -107,9 +107,9 @@ class Binning const bool fnbin; cpu_mode themode; - void palSwapContext(ExecContext *xc); - void execute(ExecContext *xc, StaticInstPtr inst); - void call(ExecContext *xc, Stats::MainBin *myBin); + void palSwapContext(ThreadContext *tc); + void execute(ThreadContext *tc, StaticInstPtr inst); + void call(ThreadContext *tc, Stats::MainBin *myBin); void changeMode(cpu_mode mode); public: @@ -137,7 +137,7 @@ class Statistics : public Serializable Tick lastModeTick; bool bin_int; - void changeMode(cpu_mode newmode, ExecContext *xc); + void changeMode(cpu_mode newmode, ThreadContext *tc); private: Stats::Scalar<> _arm; @@ -179,11 +179,11 @@ class Statistics : public Serializable void ivle() { _ivle++; } void hwrei() { _hwrei++; } void swpipl(int ipl); - void mode(cpu_mode newmode, ExecContext *xc); - void context(Addr oldpcbb, Addr newpcbb, ExecContext *xc); - void callpal(int code, ExecContext *xc); + void mode(cpu_mode newmode, ThreadContext *tc); + void context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc); + void callpal(int code, ThreadContext *tc); - void setIdleProcess(Addr idle, ExecContext *xc); + void setIdleProcess(Addr idle, ThreadContext *tc); public: virtual void serialize(std::ostream &os); diff --git a/src/kern/linux/events.cc b/src/kern/linux/events.cc index 425109053..5ff7e26db 100644 --- a/src/kern/linux/events.cc +++ b/src/kern/linux/events.cc @@ -30,7 +30,7 @@ #include "arch/arguments.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/linux/events.hh" #include "kern/linux/printk.hh" #include "kern/system_events.hh" @@ -40,17 +40,17 @@ namespace Linux { void -DebugPrintkEvent::process(ExecContext *xc) +DebugPrintkEvent::process(ThreadContext *tc) { if (DTRACE(DebugPrintf)) { if (!raw) { - StringWrap name(xc->getSystemPtr()->name() + ".dprintk"); + StringWrap name(tc->getSystemPtr()->name() + ".dprintk"); DPRINTFN(""); } - AlphaISA::AlphaArguments args(xc); + AlphaISA::AlphaArguments args(tc); Printk(args); - SkipFuncEvent::process(xc); + SkipFuncEvent::process(tc); } } diff --git a/src/kern/linux/events.hh b/src/kern/linux/events.hh index 0e4c433e1..65f794a9c 100644 --- a/src/kern/linux/events.hh +++ b/src/kern/linux/events.hh @@ -44,7 +44,7 @@ class DebugPrintkEvent : public SkipFuncEvent DebugPrintkEvent(PCEventQueue *q, const std::string &desc, Addr addr, bool r = false) : SkipFuncEvent(q, desc, addr), raw(r) {} - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *xc); }; } diff --git a/src/kern/system_events.cc b/src/kern/system_events.cc index af700039c..aca75e27d 100644 --- a/src/kern/system_events.cc +++ b/src/kern/system_events.cc @@ -38,19 +38,19 @@ using namespace TheISA; void -SkipFuncEvent::process(ExecContext *xc) +SkipFuncEvent::process(ThreadContext *tc) { - Addr newpc = xc->readIntReg(ReturnAddressReg); + Addr newpc = tc->readIntReg(ReturnAddressReg); DPRINTF(PCEvent, "skipping %s: pc=%x, newpc=%x\n", description, - xc->readPC(), newpc); + tc->readPC(), newpc); - xc->setPC(newpc); - xc->setNextPC(xc->readPC() + sizeof(TheISA::MachInst)); + tc->setPC(newpc); + tc->setNextPC(tc->readPC() + sizeof(TheISA::MachInst)); /* - BranchPred *bp = xc->getCpuPtr()->getBranchPred(); + BranchPred *bp = tc->getCpuPtr()->getBranchPred(); if (bp != NULL) { - bp->popRAS(xc->getThreadNum()); + bp->popRAS(tc->getThreadNum()); } */ } @@ -63,35 +63,35 @@ FnEvent::FnEvent(PCEventQueue *q, const std::string &desc, Addr addr, } void -FnEvent::process(ExecContext *xc) +FnEvent::process(ThreadContext *tc) { - if (xc->misspeculating()) + if (tc->misspeculating()) return; - xc->getSystemPtr()->kernelBinning->call(xc, mybin); + tc->getSystemPtr()->kernelBinning->call(tc, mybin); } void -IdleStartEvent::process(ExecContext *xc) +IdleStartEvent::process(ThreadContext *tc) { - if (xc->getKernelStats()) - xc->getKernelStats()->setIdleProcess( - xc->readMiscReg(AlphaISA::IPR_PALtemp23), xc); + if (tc->getKernelStats()) + tc->getKernelStats()->setIdleProcess( + tc->readMiscReg(AlphaISA::IPR_PALtemp23), tc); remove(); } void -InterruptStartEvent::process(ExecContext *xc) +InterruptStartEvent::process(ThreadContext *tc) { - if (xc->getKernelStats()) - xc->getKernelStats()->mode(Kernel::interrupt, xc); + if (tc->getKernelStats()) + tc->getKernelStats()->mode(Kernel::interrupt, tc); } void -InterruptEndEvent::process(ExecContext *xc) +InterruptEndEvent::process(ThreadContext *tc) { // We go back to kernel, if we are user, inside the rti // pal code we will get switched to user because of the ICM write - if (xc->getKernelStats()) - xc->getKernelStats()->mode(Kernel::kernel, xc); + if (tc->getKernelStats()) + tc->getKernelStats()->mode(Kernel::kernel, tc); } diff --git a/src/kern/system_events.hh b/src/kern/system_events.hh index ea3601a89..05c878577 100644 --- a/src/kern/system_events.hh +++ b/src/kern/system_events.hh @@ -42,7 +42,7 @@ class SkipFuncEvent : public PCEvent SkipFuncEvent(PCEventQueue *q, const std::string &desc, Addr addr) : PCEvent(q, desc, addr) {} - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; class FnEvent : public PCEvent @@ -50,7 +50,7 @@ class FnEvent : public PCEvent public: FnEvent(PCEventQueue *q, const std::string &desc, Addr addr, Stats::MainBin *bin); - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); std::string myname() const { return _name; } private: @@ -64,7 +64,7 @@ class IdleStartEvent : public PCEvent IdleStartEvent(PCEventQueue *q, const std::string &desc, Addr addr) : PCEvent(q, desc, addr) {} - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; class InterruptStartEvent : public PCEvent @@ -73,7 +73,7 @@ class InterruptStartEvent : public PCEvent InterruptStartEvent(PCEventQueue *q, const std::string &desc, Addr addr) : PCEvent(q, desc, addr) {} - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; class InterruptEndEvent : public PCEvent @@ -82,7 +82,7 @@ class InterruptEndEvent : public PCEvent InterruptEndEvent(PCEventQueue *q, const std::string &desc, Addr addr) : PCEvent(q, desc, addr) {} - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; diff --git a/src/kern/tru64/dump_mbuf.cc b/src/kern/tru64/dump_mbuf.cc index 44f18e62f..8f88f8904 100644 --- a/src/kern/tru64/dump_mbuf.cc +++ b/src/kern/tru64/dump_mbuf.cc @@ -34,7 +34,7 @@ #include "base/cprintf.hh" #include "base/trace.hh" #include "base/loader/symtab.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "kern/tru64/mbuf.hh" #include "sim/host.hh" #include "sim/system.hh" @@ -49,11 +49,11 @@ namespace tru64 { void DumpMbuf(AlphaArguments args) { - ExecContext *xc = args.getExecContext(); + ThreadContext *tc = args.getThreadContext(); Addr addr = (Addr)args; struct mbuf m; - CopyOut(xc, &m, addr, sizeof(m)); + CopyOut(tc, &m, addr, sizeof(m)); int count = m.m_pkthdr.len; @@ -64,8 +64,8 @@ DumpMbuf(AlphaArguments args) ccprintf(DebugOut(), "m=%#lx, m->m_data=%#lx, m->m_len=%d\n", addr, m.m_data, m.m_len); char *buffer = new char[m.m_len]; - CopyOut(xc, buffer, m.m_data, m.m_len); - Trace::dataDump(curTick, xc->getSystemPtr()->name(), (uint8_t *)buffer, + CopyOut(tc, buffer, m.m_data, m.m_len); + Trace::dataDump(curTick, tc->getSystemPtr()->name(), (uint8_t *)buffer, m.m_len); delete [] buffer; @@ -73,7 +73,7 @@ DumpMbuf(AlphaArguments args) if (!m.m_next) break; - CopyOut(xc, &m, m.m_next, sizeof(m)); + CopyOut(tc, &m, m.m_next, sizeof(m)); } } diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh index ee41ec736..d2b7c862f 100644 --- a/src/kern/tru64/tru64.hh +++ b/src/kern/tru64/tru64.hh @@ -579,23 +579,23 @@ class Tru64 { /// Target getdirentries() handler. static SyscallReturn getdirentriesFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { using namespace TheISA; #ifdef __CYGWIN__ panic("getdirent not implemented on cygwin!"); #else - int fd = process->sim_fd(xc->getSyscallArg(0)); - Addr tgt_buf = xc->getSyscallArg(1); - int tgt_nbytes = xc->getSyscallArg(2); - Addr tgt_basep = xc->getSyscallArg(3); + int fd = process->sim_fd(tc->getSyscallArg(0)); + Addr tgt_buf = tc->getSyscallArg(1); + int tgt_nbytes = tc->getSyscallArg(2); + Addr tgt_basep = tc->getSyscallArg(3); char * const host_buf = new char[tgt_nbytes]; // just pass basep through uninterpreted. TypedBufferArg<int64_t> basep(tgt_basep); - basep.copyIn(xc->getMemPort()); + basep.copyIn(tc->getMemPort()); long host_basep = (off_t)htog((int64_t)*basep); int host_result = getdirentries(fd, host_buf, tgt_nbytes, &host_basep); @@ -622,7 +622,7 @@ class Tru64 { tgt_dp->d_reclen = tgt_bufsize; tgt_dp->d_namlen = namelen; strcpy(tgt_dp->d_name, host_dp->d_name); - tgt_dp.copyOut(xc->getMemPort()); + tgt_dp.copyOut(tc->getMemPort()); tgt_buf_ptr += tgt_bufsize; host_buf_ptr += host_dp->d_reclen; @@ -631,7 +631,7 @@ class Tru64 { delete [] host_buf; *basep = htog((int64_t)host_basep); - basep.copyOut(xc->getMemPort()); + basep.copyOut(tc->getMemPort()); return tgt_buf_ptr - tgt_buf; #endif @@ -640,27 +640,27 @@ class Tru64 { /// Target sigreturn() handler. static SyscallReturn sigreturnFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { using namespace TheISA; using TheISA::RegFile; - TypedBufferArg<Tru64::sigcontext> sc(xc->getSyscallArg(0)); + TypedBufferArg<Tru64::sigcontext> sc(tc->getSyscallArg(0)); - sc.copyIn(xc->getMemPort()); + sc.copyIn(tc->getMemPort()); // Restore state from sigcontext structure. // Note that we'll advance PC <- NPC before the end of the cycle, // so we need to restore the desired PC into NPC. // The current regs->pc will get clobbered. - xc->setNextPC(htog(sc->sc_pc)); + tc->setNextPC(htog(sc->sc_pc)); for (int i = 0; i < 31; ++i) { - xc->setIntReg(i, htog(sc->sc_regs[i])); - xc->setFloatRegBits(i, htog(sc->sc_fpregs[i])); + tc->setIntReg(i, htog(sc->sc_regs[i])); + tc->setFloatRegBits(i, htog(sc->sc_fpregs[i])); } - xc->setMiscReg(TheISA::Fpcr_DepTag, htog(sc->sc_fpcr)); + tc->setMiscReg(TheISA::Fpcr_DepTag, htog(sc->sc_fpcr)); return 0; } @@ -673,13 +673,13 @@ class Tru64 { /// Create a stack region for a thread. static SyscallReturn stack_createFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { using namespace TheISA; - TypedBufferArg<Tru64::vm_stack> argp(xc->getSyscallArg(0)); + TypedBufferArg<Tru64::vm_stack> argp(tc->getSyscallArg(0)); - argp.copyIn(xc->getMemPort()); + argp.copyIn(tc->getMemPort()); // if the user chose an address, just let them have it. Otherwise // pick one for them. @@ -688,7 +688,7 @@ class Tru64 { int stack_size = (htog(argp->rsize) + htog(argp->ysize) + htog(argp->gsize)); process->next_thread_stack_base -= stack_size; - argp.copyOut(xc->getMemPort()); + argp.copyOut(tc->getMemPort()); } return 0; @@ -703,15 +703,15 @@ class Tru64 { /// region has several structs, some global, some per-RAD, some per-VP. static SyscallReturn nxm_task_initFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { using namespace std; using namespace TheISA; - TypedBufferArg<Tru64::nxm_task_attr> attrp(xc->getSyscallArg(0)); - TypedBufferArg<Addr> configptr_ptr(xc->getSyscallArg(1)); + TypedBufferArg<Tru64::nxm_task_attr> attrp(tc->getSyscallArg(0)); + TypedBufferArg<Addr> configptr_ptr(tc->getSyscallArg(1)); - attrp.copyIn(xc->getMemPort()); + attrp.copyIn(tc->getMemPort()); if (gtoh(attrp->nxm_version) != NXM_LIB_VERSION) { cerr << "nxm_task_init: thread library version mismatch! " @@ -752,7 +752,7 @@ class Tru64 { config->nxm_slot_state = htog(slot_state_addr); config->nxm_rad[0] = htog(rad_state_addr); - config.copyOut(xc->getMemPort()); + config.copyOut(tc->getMemPort()); // initialize the slot_state array and copy it out TypedBufferArg<Tru64::nxm_slot_state_t> slot_state(slot_state_addr, @@ -765,7 +765,7 @@ class Tru64 { (i == 0) ? Tru64::NXM_SLOT_BOUND : Tru64::NXM_SLOT_AVAIL; } - slot_state.copyOut(xc->getMemPort()); + slot_state.copyOut(tc->getMemPort()); // same for the per-RAD "shared" struct. Note that we need to // allocate extra bytes for the per-VP array which is embedded at @@ -789,7 +789,7 @@ class Tru64 { ssp->nxm_sysevent = htog(0); if (i == 0) { - uint64_t uniq = xc->readMiscReg(TheISA::Uniq_DepTag); + uint64_t uniq = tc->readMiscReg(TheISA::Uniq_DepTag); ssp->nxm_u.pth_id = htog(uniq + gtoh(attrp->nxm_uniq_offset)); ssp->nxm_u.nxm_active = htog(uniq | 1); } @@ -799,13 +799,13 @@ class Tru64 { } } - rad_state.copyOut(xc->getMemPort()); + rad_state.copyOut(tc->getMemPort()); // // copy pointer to shared config area out to user // *configptr_ptr = htog(config_addr); - configptr_ptr.copyOut(xc->getMemPort()); + configptr_ptr.copyOut(tc->getMemPort()); // Register this as a valid address range with the process process->nxm_start = base_addr; @@ -814,40 +814,40 @@ class Tru64 { return 0; } - /// Initialize execution context. + /// Initialize thread context. static void - init_exec_context(ExecContext *ec, + init_thread_context(ThreadContext *tc, Tru64::nxm_thread_attr *attrp, uint64_t uniq_val) { using namespace TheISA; - ec->clearArchRegs(); + tc->clearArchRegs(); - ec->setIntReg(TheISA::ArgumentReg0, gtoh(attrp->registers.a0)); - ec->setIntReg(27/*t12*/, gtoh(attrp->registers.pc)); - ec->setIntReg(TheISA::StackPointerReg, gtoh(attrp->registers.sp)); - ec->setMiscReg(TheISA::Uniq_DepTag, uniq_val); + tc->setIntReg(TheISA::ArgumentReg0, gtoh(attrp->registers.a0)); + tc->setIntReg(27/*t12*/, gtoh(attrp->registers.pc)); + tc->setIntReg(TheISA::StackPointerReg, gtoh(attrp->registers.sp)); + tc->setMiscReg(TheISA::Uniq_DepTag, uniq_val); - ec->setPC(gtoh(attrp->registers.pc)); - ec->setNextPC(gtoh(attrp->registers.pc) + sizeof(TheISA::MachInst)); + tc->setPC(gtoh(attrp->registers.pc)); + tc->setNextPC(gtoh(attrp->registers.pc) + sizeof(TheISA::MachInst)); - ec->activate(); + tc->activate(); } /// Create thread. static SyscallReturn nxm_thread_createFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { using namespace std; using namespace TheISA; - TypedBufferArg<Tru64::nxm_thread_attr> attrp(xc->getSyscallArg(0)); - TypedBufferArg<uint64_t> kidp(xc->getSyscallArg(1)); - int thread_index = xc->getSyscallArg(2); + TypedBufferArg<Tru64::nxm_thread_attr> attrp(tc->getSyscallArg(0)); + TypedBufferArg<uint64_t> kidp(tc->getSyscallArg(1)); + int thread_index = tc->getSyscallArg(2); // get attribute args - attrp.copyIn(xc->getMemPort()); + attrp.copyIn(tc->getMemPort()); if (gtoh(attrp->version) != NXM_LIB_VERSION) { cerr << "nxm_thread_create: thread library version mismatch! " @@ -872,7 +872,7 @@ class Tru64 { TypedBufferArg<Tru64::nxm_shared> rad_state(0x14000, rad_state_size); - rad_state.copyIn(xc->getMemPort()); + rad_state.copyIn(tc->getMemPort()); uint64_t uniq_val = gtoh(attrp->pthid) - gtoh(rad_state->nxm_uniq_offset); @@ -883,7 +883,7 @@ class Tru64 { // This is supposed to be a port number. Make something up. *kidp = htog(99); - kidp.copyOut(xc->getMemPort()); + kidp.copyOut(tc->getMemPort()); return 0; } else if (gtoh(attrp->type) == Tru64::NXM_TYPE_VP) { @@ -897,7 +897,7 @@ class Tru64 { ssp->nxm_u.pth_id = attrp->pthid; ssp->nxm_u.nxm_active = htog(uniq_val | 1); - rad_state.copyOut(xc->getMemPort()); + rad_state.copyOut(tc->getMemPort()); Addr slot_state_addr = 0x12000 + sizeof(Tru64::nxm_config_info); int slot_state_size = @@ -907,7 +907,7 @@ class Tru64 { slot_state(slot_state_addr, slot_state_size); - slot_state.copyIn(xc->getMemPort()); + slot_state.copyIn(tc->getMemPort()); if (slot_state[thread_index] != Tru64::NXM_SLOT_AVAIL) { cerr << "nxm_thread_createFunc: requested VP slot " @@ -919,21 +919,21 @@ class Tru64 { // doesn't work anyway slot_state[thread_index] = Tru64::NXM_SLOT_BOUND; - slot_state.copyOut(xc->getMemPort()); + slot_state.copyOut(tc->getMemPort()); - // Find a free simulator execution context. + // Find a free simulator thread context. for (int i = 0; i < process->numCpus(); ++i) { - ExecContext *xc = process->execContexts[i]; + ThreadContext *tc = process->threadContexts[i]; - if (xc->status() == ExecContext::Suspended) { + if (tc->status() == ThreadContext::Suspended) { // inactive context... grab it - init_exec_context(xc, attrp, uniq_val); + init_thread_context(tc, attrp, uniq_val); // This is supposed to be a port number, but we'll try // and get away with just sticking the thread index // here. *kidp = htog(thread_index); - kidp.copyOut(xc->getMemPort()); + kidp.copyOut(tc->getMemPort()); return 0; } @@ -954,7 +954,7 @@ class Tru64 { /// Thread idle call (like yield()). static SyscallReturn nxm_idleFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { return 0; } @@ -962,17 +962,17 @@ class Tru64 { /// Block thread. static SyscallReturn nxm_thread_blockFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { using namespace std; - uint64_t tid = xc->getSyscallArg(0); - uint64_t secs = xc->getSyscallArg(1); - uint64_t flags = xc->getSyscallArg(2); - uint64_t action = xc->getSyscallArg(3); - uint64_t usecs = xc->getSyscallArg(4); + uint64_t tid = tc->getSyscallArg(0); + uint64_t secs = tc->getSyscallArg(1); + uint64_t flags = tc->getSyscallArg(2); + uint64_t action = tc->getSyscallArg(3); + uint64_t usecs = tc->getSyscallArg(4); - cout << xc->getCpuPtr()->name() << ": nxm_thread_block " << tid << " " + cout << tc->getCpuPtr()->name() << ": nxm_thread_block " << tid << " " << secs << " " << flags << " " << action << " " << usecs << endl; return 0; @@ -981,17 +981,17 @@ class Tru64 { /// block. static SyscallReturn nxm_blockFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { using namespace std; - Addr uaddr = xc->getSyscallArg(0); - uint64_t val = xc->getSyscallArg(1); - uint64_t secs = xc->getSyscallArg(2); - uint64_t usecs = xc->getSyscallArg(3); - uint64_t flags = xc->getSyscallArg(4); + Addr uaddr = tc->getSyscallArg(0); + uint64_t val = tc->getSyscallArg(1); + uint64_t secs = tc->getSyscallArg(2); + uint64_t usecs = tc->getSyscallArg(3); + uint64_t flags = tc->getSyscallArg(4); - BaseCPU *cpu = xc->getCpuPtr(); + BaseCPU *cpu = tc->getCpuPtr(); cout << cpu->name() << ": nxm_block " << hex << uaddr << dec << " " << val @@ -1004,13 +1004,13 @@ class Tru64 { /// Unblock thread. static SyscallReturn nxm_unblockFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { using namespace std; - Addr uaddr = xc->getSyscallArg(0); + Addr uaddr = tc->getSyscallArg(0); - cout << xc->getCpuPtr()->name() << ": nxm_unblock " + cout << tc->getCpuPtr()->name() << ": nxm_unblock " << hex << uaddr << dec << endl; return 0; @@ -1019,7 +1019,7 @@ class Tru64 { /// Switch thread priority. static SyscallReturn swtch_priFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { // Attempts to switch to another runnable thread (if there is // one). Returns false if there are no other threads to run @@ -1032,7 +1032,7 @@ class Tru64 { } - /// Activate exec context waiting on a channel. Just activate one + /// Activate thread context waiting on a channel. Just activate one /// by default. static int activate_waiting_context(Addr uaddr, Process *process, @@ -1048,8 +1048,8 @@ class Tru64 { while (i != end && (num_activated == 0 || activate_all)) { if (i->waitChan == uaddr) { // found waiting process: make it active - ExecContext *newCtx = i->waitingContext; - assert(newCtx->status() == ExecContext::Suspended); + ThreadContext *newCtx = i->waitingContext; + assert(newCtx->status() == ThreadContext::Suspended); newCtx->activate(); // get rid of this record @@ -1066,32 +1066,32 @@ class Tru64 { /// M5 hacked-up lock acquire. static void - m5_lock_mutex(Addr uaddr, Process *process, ExecContext *xc) + m5_lock_mutex(Addr uaddr, Process *process, ThreadContext *tc) { using namespace TheISA; TypedBufferArg<uint64_t> lockp(uaddr); - lockp.copyIn(xc->getMemPort()); + lockp.copyIn(tc->getMemPort()); if (gtoh(*lockp) == 0) { // lock is free: grab it *lockp = htog(1); - lockp.copyOut(xc->getMemPort()); + lockp.copyOut(tc->getMemPort()); } else { // lock is busy: disable until free - process->waitList.push_back(Process::WaitRec(uaddr, xc)); - xc->suspend(); + process->waitList.push_back(Process::WaitRec(uaddr, tc)); + tc->suspend(); } } /// M5 unlock call. static void - m5_unlock_mutex(Addr uaddr, Process *process, ExecContext *xc) + m5_unlock_mutex(Addr uaddr, Process *process, ThreadContext *tc) { TypedBufferArg<uint64_t> lockp(uaddr); - lockp.copyIn(xc->getMemPort()); + lockp.copyIn(tc->getMemPort()); assert(*lockp != 0); // Check for a process waiting on the lock. @@ -1100,18 +1100,18 @@ class Tru64 { // clear lock field if no waiting context is taking over the lock if (num_waiting == 0) { *lockp = 0; - lockp.copyOut(xc->getMemPort()); + lockp.copyOut(tc->getMemPort()); } } /// Lock acquire syscall handler. static SyscallReturn m5_mutex_lockFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - Addr uaddr = xc->getSyscallArg(0); + Addr uaddr = tc->getSyscallArg(0); - m5_lock_mutex(uaddr, process, xc); + m5_lock_mutex(uaddr, process, tc); // Return 0 since we will always return to the user with the lock // acquired. We will just keep the context inactive until that is @@ -1122,19 +1122,19 @@ class Tru64 { /// Try lock (non-blocking). static SyscallReturn m5_mutex_trylockFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { using namespace TheISA; - Addr uaddr = xc->getSyscallArg(0); + Addr uaddr = tc->getSyscallArg(0); TypedBufferArg<uint64_t> lockp(uaddr); - lockp.copyIn(xc->getMemPort()); + lockp.copyIn(tc->getMemPort()); if (gtoh(*lockp) == 0) { // lock is free: grab it *lockp = htog(1); - lockp.copyOut(xc->getMemPort()); + lockp.copyOut(tc->getMemPort()); return 0; } else { return 1; @@ -1144,11 +1144,11 @@ class Tru64 { /// Unlock syscall handler. static SyscallReturn m5_mutex_unlockFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - Addr uaddr = xc->getSyscallArg(0); + Addr uaddr = tc->getSyscallArg(0); - m5_unlock_mutex(uaddr, process, xc); + m5_unlock_mutex(uaddr, process, tc); return 0; } @@ -1156,9 +1156,9 @@ class Tru64 { /// Signal ocndition. static SyscallReturn m5_cond_signalFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - Addr cond_addr = xc->getSyscallArg(0); + Addr cond_addr = tc->getSyscallArg(0); // Wake up one process waiting on the condition variable. activate_waiting_context(cond_addr, process); @@ -1169,9 +1169,9 @@ class Tru64 { /// Wake up all processes waiting on the condition variable. static SyscallReturn m5_cond_broadcastFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - Addr cond_addr = xc->getSyscallArg(0); + Addr cond_addr = tc->getSyscallArg(0); activate_waiting_context(cond_addr, process, true); @@ -1181,23 +1181,23 @@ class Tru64 { /// Wait on a condition. static SyscallReturn m5_cond_waitFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { using namespace TheISA; - Addr cond_addr = xc->getSyscallArg(0); - Addr lock_addr = xc->getSyscallArg(1); + Addr cond_addr = tc->getSyscallArg(0); + Addr lock_addr = tc->getSyscallArg(1); TypedBufferArg<uint64_t> condp(cond_addr); TypedBufferArg<uint64_t> lockp(lock_addr); // user is supposed to acquire lock before entering - lockp.copyIn(xc->getMemPort()); + lockp.copyIn(tc->getMemPort()); assert(gtoh(*lockp) != 0); - m5_unlock_mutex(lock_addr, process, xc); + m5_unlock_mutex(lock_addr, process, tc); - process->waitList.push_back(Process::WaitRec(cond_addr, xc)); - xc->suspend(); + process->waitList.push_back(Process::WaitRec(cond_addr, tc)); + tc->suspend(); return 0; } @@ -1205,10 +1205,10 @@ class Tru64 { /// Thread exit. static SyscallReturn m5_thread_exitFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - assert(xc->status() == ExecContext::Active); - xc->deallocate(); + assert(tc->status() == ThreadContext::Active); + tc->deallocate(); return 0; } @@ -1216,21 +1216,21 @@ class Tru64 { /// Indirect syscall invocation (call #0). static SyscallReturn indirectSyscallFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - int new_callnum = xc->getSyscallArg(0); + int new_callnum = tc->getSyscallArg(0); LiveProcess *lp = dynamic_cast<LiveProcess*>(process); assert(lp); for (int i = 0; i < 5; ++i) - xc->setSyscallArg(i, xc->getSyscallArg(i+1)); + tc->setSyscallArg(i, tc->getSyscallArg(i+1)); SyscallDesc *new_desc = lp->getDesc(new_callnum); if (desc == NULL) fatal("Syscall %d out of range", callnum); - new_desc->doSyscall(new_callnum, process, xc); + new_desc->doSyscall(new_callnum, process, tc); return 0; } diff --git a/src/kern/tru64/tru64_events.cc b/src/kern/tru64/tru64_events.cc index eb3f34836..69638bde1 100644 --- a/src/kern/tru64/tru64_events.cc +++ b/src/kern/tru64/tru64_events.cc @@ -29,7 +29,7 @@ * Lisa Hsu */ -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/base.hh" #include "kern/system_events.hh" #include "kern/tru64/tru64_events.hh" @@ -42,23 +42,23 @@ using namespace TheISA; -//void SkipFuncEvent::process(ExecContext *xc); +//void SkipFuncEvent::process(ExecContext *tc); void -BadAddrEvent::process(ExecContext *xc) +BadAddrEvent::process(ThreadContext *tc) { // The following gross hack is the equivalent function to the // annotation for vmunix::badaddr in: // simos/simulation/apps/tcl/osf/tlaser.tcl - uint64_t a0 = xc->readIntReg(ArgumentReg0); + uint64_t a0 = tc->readIntReg(ArgumentReg0); AddrRangeList resp; AddrRangeList snoop; AddrRangeIter iter; bool found = false; - xc->getPhysPort()->getPeerAddressRanges(resp, snoop); + tc->getPhysPort()->getPeerAddressRanges(resp, snoop); for(iter = resp.begin(); iter != resp.end(); iter++) { if (*iter == (TheISA::K0Seg2Phys(a0) & EV5::PAddrImplMask)) @@ -68,41 +68,41 @@ BadAddrEvent::process(ExecContext *xc) if (!TheISA::IsK0Seg(a0) || found ) { DPRINTF(BADADDR, "badaddr arg=%#x bad\n", a0); - xc->setIntReg(ReturnValueReg, 0x1); - SkipFuncEvent::process(xc); + tc->setIntReg(ReturnValueReg, 0x1); + SkipFuncEvent::process(tc); } else DPRINTF(BADADDR, "badaddr arg=%#x good\n", a0); } void -PrintfEvent::process(ExecContext *xc) +PrintfEvent::process(ThreadContext *tc) { if (DTRACE(Printf)) { - DebugOut() << curTick << ": " << xc->getCpuPtr()->name() << ": "; + DebugOut() << curTick << ": " << tc->getCpuPtr()->name() << ": "; - AlphaArguments args(xc); + AlphaArguments args(tc); tru64::Printf(args); } } void -DebugPrintfEvent::process(ExecContext *xc) +DebugPrintfEvent::process(ThreadContext *tc) { if (DTRACE(DebugPrintf)) { if (!raw) - DebugOut() << curTick << ": " << xc->getCpuPtr()->name() << ": "; + DebugOut() << curTick << ": " << tc->getCpuPtr()->name() << ": "; - AlphaArguments args(xc); + AlphaArguments args(tc); tru64::Printf(args); } } void -DumpMbufEvent::process(ExecContext *xc) +DumpMbufEvent::process(ThreadContext *tc) { if (DTRACE(DebugPrintf)) { - AlphaArguments args(xc); + AlphaArguments args(tc); tru64::DumpMbuf(args); } } diff --git a/src/kern/tru64/tru64_events.hh b/src/kern/tru64/tru64_events.hh index 6549d14a5..6a1ab2e51 100644 --- a/src/kern/tru64/tru64_events.hh +++ b/src/kern/tru64/tru64_events.hh @@ -37,14 +37,14 @@ #include "cpu/pc_event.hh" #include "kern/system_events.hh" -class ExecContext; +class ThreadContext; class BadAddrEvent : public SkipFuncEvent { public: BadAddrEvent(PCEventQueue *q, const std::string &desc, Addr addr) : SkipFuncEvent(q, desc, addr) {} - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; class PrintfEvent : public PCEvent @@ -52,7 +52,7 @@ class PrintfEvent : public PCEvent public: PrintfEvent(PCEventQueue *q, const std::string &desc, Addr addr) : PCEvent(q, desc, addr) {} - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; class DebugPrintfEvent : public PCEvent @@ -64,7 +64,7 @@ class DebugPrintfEvent : public PCEvent DebugPrintfEvent(PCEventQueue *q, const std::string &desc, Addr addr, bool r = false) : PCEvent(q, desc, addr), raw(r) {} - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; class DebugPrintfrEvent : public DebugPrintfEvent @@ -80,7 +80,7 @@ class DumpMbufEvent : public PCEvent public: DumpMbufEvent(PCEventQueue *q, const std::string &desc, Addr addr) : PCEvent(q, desc, addr) {} - virtual void process(ExecContext *xc); + virtual void process(ThreadContext *tc); }; #endif // __TRU64_EVENTS_HH__ diff --git a/src/mem/vport.cc b/src/mem/vport.cc index 0d53e4609..cd297bb8e 100644 --- a/src/mem/vport.cc +++ b/src/mem/vport.cc @@ -42,8 +42,8 @@ VirtualPort::readBlob(Addr addr, uint8_t *p, int size) for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done(); gen.next()) { - if (xc) - paddr = TheISA::vtophys(xc,gen.addr()); + if (tc) + paddr = TheISA::vtophys(tc,gen.addr()); else paddr = TheISA::vtophys(gen.addr()); @@ -59,8 +59,8 @@ VirtualPort::writeBlob(Addr addr, uint8_t *p, int size) for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done(); gen.next()) { - if (xc) - paddr = TheISA::vtophys(xc,gen.addr()); + if (tc) + paddr = TheISA::vtophys(tc,gen.addr()); else paddr = TheISA::vtophys(gen.addr()); diff --git a/src/mem/vport.hh b/src/mem/vport.hh index 43f6e0db2..56f2ff29e 100644 --- a/src/mem/vport.hh +++ b/src/mem/vport.hh @@ -44,7 +44,7 @@ /** A class that translates a virtual address to a physical address and then - * calls the above read/write functions. If an execution context is provided the + * calls the above read/write functions. If a thread context is provided the * address can alway be translated, If not it can only be translated if it is a * simple address masking operation (such as alpha super page accesses). */ @@ -52,18 +52,19 @@ class VirtualPort : public FunctionalPort { private: - ExecContext *xc; + ThreadContext *tc; public: - VirtualPort(const std::string &_name, ExecContext *_xc = NULL) - : FunctionalPort(_name), xc(_xc) + VirtualPort(const std::string &_name, ThreadContext *_tc = NULL) + : FunctionalPort(_name), tc(_tc) {} - /** Return true if we have an exec context. This is used to prevent someone - * from accidently deleting the cpus statically allocated vport. - * @return true if an execution context isn't valid + /** Return true if we have an thread context. This is used to + * prevent someone from accidently deleting the cpus statically + * allocated vport. + * @return true if a thread context isn't valid */ - bool nullExecContext() { return xc != NULL; } + bool nullThreadContext() { return tc != NULL; } /** Version of readblob that translates virt->phys and deals * with page boundries. */ diff --git a/src/sim/faults.cc b/src/sim/faults.cc index 6a598a3f4..650b728f7 100644 --- a/src/sim/faults.cc +++ b/src/sim/faults.cc @@ -31,25 +31,25 @@ #include "base/misc.hh" #include "sim/faults.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/base.hh" #if !FULL_SYSTEM -void FaultBase::invoke(ExecContext * xc) +void FaultBase::invoke(ThreadContext * tc) { - fatal("fault (%s) detected @ PC 0x%08p", name(), xc->readPC()); + fatal("fault (%s) detected @ PC 0x%08p", name(), tc->readPC()); } #else -void FaultBase::invoke(ExecContext * xc) +void FaultBase::invoke(ThreadContext * tc) { - DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->readPC()); - xc->getCpuPtr()->recordEvent(csprintf("Fault %s", name())); + DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), tc->readPC()); + tc->getCpuPtr()->recordEvent(csprintf("Fault %s", name())); - assert(!xc->misspeculating()); + assert(!tc->misspeculating()); } #endif -void UnimpFault::invoke(ExecContext * xc) +void UnimpFault::invoke(ThreadContext * tc) { panic("Unimpfault: %s\n", panicStr.c_str()); } diff --git a/src/sim/faults.hh b/src/sim/faults.hh index 7da69a916..23385c649 100644 --- a/src/sim/faults.hh +++ b/src/sim/faults.hh @@ -36,7 +36,7 @@ #include "sim/stats.hh" #include "config/full_system.hh" -class ExecContext; +class ThreadContext; class FaultBase; typedef RefCountingPtr<FaultBase> Fault; @@ -55,9 +55,9 @@ class FaultBase : public RefCounted public: virtual FaultName name() = 0; #if FULL_SYSTEM - virtual void invoke(ExecContext * xc); + virtual void invoke(ThreadContext * tc); #else - virtual void invoke(ExecContext * xc); + virtual void invoke(ThreadContext * tc); #endif // template<typename T> // bool isA() {return dynamic_cast<T *>(this);} @@ -77,7 +77,7 @@ class UnimpFault : public FaultBase { } FaultName name() {return "Unimplemented simulator feature";} - void invoke(ExecContext * xc); + void invoke(ThreadContext * tc); }; #endif // __FAULTS_HH__ diff --git a/src/sim/process.cc b/src/sim/process.cc index e8a5284d4..1533a376d 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -40,7 +40,7 @@ #include "base/loader/symtab.hh" #include "base/statistics.hh" #include "config/full_system.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "mem/page_table.hh" #include "mem/physical.hh" #include "mem/translating_port.hh" @@ -134,11 +134,11 @@ Process::openOutputFile(const string &filename) int -Process::registerExecContext(ExecContext *xc) +Process::registerThreadContext(ThreadContext *tc) { // add to list - int myIndex = execContexts.size(); - execContexts.push_back(xc); + int myIndex = threadContexts.size(); + threadContexts.push_back(tc); // return CPU number to caller return myIndex; @@ -147,14 +147,14 @@ Process::registerExecContext(ExecContext *xc) void Process::startup() { - if (execContexts.empty()) + if (threadContexts.empty()) fatal("Process %s is not associated with any CPUs!\n", name()); - // first exec context for this process... initialize & enable - ExecContext *xc = execContexts[0]; + // first thread context for this process... initialize & enable + ThreadContext *tc = threadContexts[0]; // mark this context as active so it will start ticking. - xc->activate(0); + tc->activate(0); Port *mem_port; mem_port = system->physmem->getPort("functional"); @@ -164,14 +164,14 @@ Process::startup() } void -Process::replaceExecContext(ExecContext *xc, int xcIndex) +Process::replaceThreadContext(ThreadContext *tc, int tcIndex) { - if (xcIndex >= execContexts.size()) { - panic("replaceExecContext: bad xcIndex, %d >= %d\n", - xcIndex, execContexts.size()); + if (tcIndex >= threadContexts.size()) { + panic("replaceThreadContext: bad tcIndex, %d >= %d\n", + tcIndex, threadContexts.size()); } - execContexts[xcIndex] = xc; + threadContexts[tcIndex] = tc; } // map simulator fd sim_fd to target fd tgt_fd @@ -338,20 +338,20 @@ LiveProcess::argsInit(int intSize, int pageSize) copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); - execContexts[0]->setIntReg(ArgumentReg0, argc); - execContexts[0]->setIntReg(ArgumentReg1, argv_array_base); - execContexts[0]->setIntReg(StackPointerReg, stack_min); + threadContexts[0]->setIntReg(ArgumentReg0, argc); + threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base); + threadContexts[0]->setIntReg(StackPointerReg, stack_min); Addr prog_entry = objFile->entryPoint(); - execContexts[0]->setPC(prog_entry); - execContexts[0]->setNextPC(prog_entry + sizeof(MachInst)); - execContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst))); + threadContexts[0]->setPC(prog_entry); + threadContexts[0]->setNextPC(prog_entry + sizeof(MachInst)); + threadContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst))); num_processes++; } void -LiveProcess::syscall(int64_t callnum, ExecContext *xc) +LiveProcess::syscall(int64_t callnum, ThreadContext *tc) { num_syscalls++; @@ -359,7 +359,7 @@ LiveProcess::syscall(int64_t callnum, ExecContext *xc) if (desc == NULL) fatal("Syscall %d out of range", callnum); - desc->doSyscall(callnum, this, xc); + desc->doSyscall(callnum, this, tc); } DEFINE_SIM_OBJECT_CLASS_NAME("LiveProcess", LiveProcess); diff --git a/src/sim/process.hh b/src/sim/process.hh index d50c937be..15d564455 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -47,7 +47,7 @@ #include "sim/sim_object.hh" class CPUExecContext; -class ExecContext; +class ThreadContext; class SyscallDesc; class PageTable; class TranslatingPort; @@ -65,24 +65,24 @@ class Process : public SimObject /// running on. System *system; - // have we initialized an execution context from this process? If + // have we initialized a thread context from this process? If // yes, subsequent contexts are assumed to be for dynamically // created threads and are not initialized. bool initialContextLoaded; - // execution contexts associated with this process - std::vector<ExecContext *> execContexts; + // thread contexts associated with this process + std::vector<ThreadContext *> threadContexts; // number of CPUs (esxec contexts, really) assigned to this process. - unsigned int numCpus() { return execContexts.size(); } + unsigned int numCpus() { return threadContexts.size(); } // record of blocked context struct WaitRec { Addr waitChan; - ExecContext *waitingContext; + ThreadContext *waitingContext; - WaitRec(Addr chan, ExecContext *ctx) + WaitRec(Addr chan, ThreadContext *ctx) : waitChan(chan), waitingContext(ctx) { } }; @@ -143,12 +143,12 @@ class Process : public SimObject // override of virtual SimObject method: register statistics virtual void regStats(); - // register an execution context for this process. - // returns xc's cpu number (index into execContexts[]) - int registerExecContext(ExecContext *xc); + // register a thread context for this process. + // returns tc's cpu number (index into threadContexts[]) + int registerThreadContext(ThreadContext *tc); - void replaceExecContext(ExecContext *xc, int xcIndex); + void replaceThreadContext(ThreadContext *tc, int tcIndex); // map simulator fd sim_fd to target fd tgt_fd void dup_fd(int sim_fd, int tgt_fd); @@ -162,7 +162,7 @@ class Process : public SimObject // look up simulator fd for given target fd int sim_fd(int tgt_fd); - virtual void syscall(int64_t callnum, ExecContext *xc) = 0; + virtual void syscall(int64_t callnum, ThreadContext *tc) = 0; }; // @@ -184,7 +184,7 @@ class LiveProcess : public Process virtual void argsInit(int intSize, int pageSize); public: - virtual void syscall(int64_t callnum, ExecContext *xc); + virtual void syscall(int64_t callnum, ThreadContext *tc); virtual SyscallDesc* getDesc(int callnum) = 0; }; diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index 8ad298454..50d949f53 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -38,7 +38,7 @@ #include "arch/vtophys.hh" #include "cpu/base.hh" #include "cpu/sampler/sampler.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/quiesce_event.hh" #include "kern/kernel_stats.hh" #include "sim/param.hh" @@ -64,94 +64,94 @@ namespace AlphaPseudo bool doQuiesce; void - arm(ExecContext *xc) + arm(ThreadContext *tc) { - if (xc->getKernelStats()) - xc->getKernelStats()->arm(); + if (tc->getKernelStats()) + tc->getKernelStats()->arm(); } void - quiesce(ExecContext *xc) + quiesce(ThreadContext *tc) { if (!doQuiesce) return; - xc->suspend(); - if (xc->getKernelStats()) - xc->getKernelStats()->quiesce(); + tc->suspend(); + if (tc->getKernelStats()) + tc->getKernelStats()->quiesce(); } void - quiesceNs(ExecContext *xc, uint64_t ns) + quiesceNs(ThreadContext *tc, uint64_t ns) { if (!doQuiesce || ns == 0) return; - EndQuiesceEvent *quiesceEvent = xc->getQuiesceEvent(); + EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); if (quiesceEvent->scheduled()) quiesceEvent->reschedule(curTick + Clock::Int::ns * ns); else quiesceEvent->schedule(curTick + Clock::Int::ns * ns); - xc->suspend(); - if (xc->getKernelStats()) - xc->getKernelStats()->quiesce(); + tc->suspend(); + if (tc->getKernelStats()) + tc->getKernelStats()->quiesce(); } void - quiesceCycles(ExecContext *xc, uint64_t cycles) + quiesceCycles(ThreadContext *tc, uint64_t cycles) { if (!doQuiesce || cycles == 0) return; - EndQuiesceEvent *quiesceEvent = xc->getQuiesceEvent(); + EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); if (quiesceEvent->scheduled()) quiesceEvent->reschedule(curTick + - xc->getCpuPtr()->cycles(cycles)); + tc->getCpuPtr()->cycles(cycles)); else quiesceEvent->schedule(curTick + - xc->getCpuPtr()->cycles(cycles)); + tc->getCpuPtr()->cycles(cycles)); - xc->suspend(); - if (xc->getKernelStats()) - xc->getKernelStats()->quiesce(); + tc->suspend(); + if (tc->getKernelStats()) + tc->getKernelStats()->quiesce(); } uint64_t - quiesceTime(ExecContext *xc) + quiesceTime(ThreadContext *tc) { - return (xc->readLastActivate() - xc->readLastSuspend()) / Clock::Int::ns; + return (tc->readLastActivate() - tc->readLastSuspend()) / Clock::Int::ns; } void - ivlb(ExecContext *xc) + ivlb(ThreadContext *tc) { - if (xc->getKernelStats()) - xc->getKernelStats()->ivlb(); + if (tc->getKernelStats()) + tc->getKernelStats()->ivlb(); } void - ivle(ExecContext *xc) + ivle(ThreadContext *tc) { } void - m5exit_old(ExecContext *xc) + m5exit_old(ThreadContext *tc) { SimExit(curTick, "m5_exit_old instruction encountered"); } void - m5exit(ExecContext *xc, Tick delay) + m5exit(ThreadContext *tc, Tick delay) { Tick when = curTick + delay * Clock::Int::ns; SimExit(when, "m5_exit instruction encountered"); } void - resetstats(ExecContext *xc, Tick delay, Tick period) + resetstats(ThreadContext *tc, Tick delay, Tick period) { if (!doStatisticsInsts) return; @@ -165,7 +165,7 @@ namespace AlphaPseudo } void - dumpstats(ExecContext *xc, Tick delay, Tick period) + dumpstats(ThreadContext *tc, Tick delay, Tick period) { if (!doStatisticsInsts) return; @@ -179,19 +179,19 @@ namespace AlphaPseudo } void - addsymbol(ExecContext *xc, Addr addr, Addr symbolAddr) + addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr) { char symb[100]; - CopyStringOut(xc, symb, symbolAddr, 100); + CopyStringOut(tc, symb, symbolAddr, 100); std::string symbol(symb); DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr); - xc->getSystemPtr()->kernelSymtab->insert(addr,symbol); + tc->getSystemPtr()->kernelSymtab->insert(addr,symbol); } void - dumpresetstats(ExecContext *xc, Tick delay, Tick period) + dumpresetstats(ThreadContext *tc, Tick delay, Tick period) { if (!doStatisticsInsts) return; @@ -205,7 +205,7 @@ namespace AlphaPseudo } void - m5checkpoint(ExecContext *xc, Tick delay, Tick period) + m5checkpoint(ThreadContext *tc, Tick delay, Tick period) { if (!doCheckpointInsts) return; @@ -218,9 +218,9 @@ namespace AlphaPseudo } uint64_t - readfile(ExecContext *xc, Addr vaddr, uint64_t len, uint64_t offset) + readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset) { - const string &file = xc->getCpuPtr()->system->params()->readfile; + const string &file = tc->getCpuPtr()->system->params()->readfile; if (file.empty()) { return ULL(0); } @@ -247,7 +247,7 @@ namespace AlphaPseudo } close(fd); - CopyIn(xc, vaddr, buf, result); + CopyIn(tc, vaddr, buf, result); delete [] buf; return result; } @@ -279,12 +279,12 @@ namespace AlphaPseudo doCheckpointInsts = __checkpoint; } - void debugbreak(ExecContext *xc) + void debugbreak(ThreadContext *tc) { debug_break(); } - void switchcpu(ExecContext *xc) + void switchcpu(ThreadContext *tc) { if (SampCPU) SampCPU->switchCPUs(); diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh index 2252964cd..5e5b7d95f 100644 --- a/src/sim/pseudo_inst.hh +++ b/src/sim/pseudo_inst.hh @@ -28,7 +28,7 @@ * Authors: Nathan Binkert */ -class ExecContext; +class ThreadContext; //We need the "Tick" data type from here #include "sim/host.hh" @@ -44,21 +44,21 @@ namespace AlphaPseudo extern bool doCheckpointInsts; extern bool doQuiesce; - void arm(ExecContext *xc); - void quiesce(ExecContext *xc); - void quiesceNs(ExecContext *xc, uint64_t ns); - void quiesceCycles(ExecContext *xc, uint64_t cycles); - uint64_t quiesceTime(ExecContext *xc); - void ivlb(ExecContext *xc); - void ivle(ExecContext *xc); - void m5exit(ExecContext *xc, Tick delay); - void m5exit_old(ExecContext *xc); - void resetstats(ExecContext *xc, Tick delay, Tick period); - void dumpstats(ExecContext *xc, Tick delay, Tick period); - void dumpresetstats(ExecContext *xc, Tick delay, Tick period); - void m5checkpoint(ExecContext *xc, Tick delay, Tick period); - uint64_t readfile(ExecContext *xc, Addr vaddr, uint64_t len, uint64_t offset); - void debugbreak(ExecContext *xc); - void switchcpu(ExecContext *xc); - void addsymbol(ExecContext *xc, Addr addr, Addr symbolAddr); + void arm(ThreadContext *tc); + void quiesce(ThreadContext *tc); + void quiesceNs(ThreadContext *tc, uint64_t ns); + void quiesceCycles(ThreadContext *tc, uint64_t cycles); + uint64_t quiesceTime(ThreadContext *tc); + void ivlb(ThreadContext *tc); + void ivle(ThreadContext *tc); + void m5exit(ThreadContext *tc, Tick delay); + void m5exit_old(ThreadContext *tc); + void resetstats(ThreadContext *tc, Tick delay, Tick period); + void dumpstats(ThreadContext *tc, Tick delay, Tick period); + void dumpresetstats(ThreadContext *tc, Tick delay, Tick period); + void m5checkpoint(ThreadContext *tc, Tick delay, Tick period); + uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset); + void debugbreak(ThreadContext *tc); + void switchcpu(ThreadContext *tc); + void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr); } diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc index e37fea1b1..888c133c0 100644 --- a/src/sim/syscall_emul.cc +++ b/src/sim/syscall_emul.cc @@ -38,7 +38,7 @@ #include "sim/syscall_emul.hh" #include "base/chunk_generator.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "cpu/base.hh" #include "mem/page_table.hh" #include "sim/process.hh" @@ -49,26 +49,26 @@ using namespace std; using namespace TheISA; void -SyscallDesc::doSyscall(int callnum, Process *process, ExecContext *xc) +SyscallDesc::doSyscall(int callnum, Process *process, ThreadContext *tc) { DPRINTFR(SyscallVerbose, "%d: %s: syscall %s called w/arguments %d,%d,%d,%d\n", - curTick,xc->getCpuPtr()->name(), name, - xc->getSyscallArg(0),xc->getSyscallArg(1), - xc->getSyscallArg(2),xc->getSyscallArg(3)); + curTick,tc->getCpuPtr()->name(), name, + tc->getSyscallArg(0),tc->getSyscallArg(1), + tc->getSyscallArg(2),tc->getSyscallArg(3)); - SyscallReturn retval = (*funcPtr)(this, callnum, process, xc); + SyscallReturn retval = (*funcPtr)(this, callnum, process, tc); DPRINTFR(SyscallVerbose, "%d: %s: syscall %s returns %d\n", - curTick,xc->getCpuPtr()->name(), name, retval.value()); + curTick,tc->getCpuPtr()->name(), name, retval.value()); if (!(flags & SyscallDesc::SuppressReturnValue)) - xc->setSyscallReturn(retval); + tc->setSyscallReturn(retval); } SyscallReturn unimplementedFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { fatal("syscall %s (#%d) unimplemented.", desc->name, callnum); @@ -78,10 +78,10 @@ unimplementedFunc(SyscallDesc *desc, int callnum, Process *process, SyscallReturn ignoreFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { warn("ignoring syscall %s(%d, %d, ...)", desc->name, - xc->getSyscallArg(0), xc->getSyscallArg(1)); + tc->getSyscallArg(0), tc->getSyscallArg(1)); return 0; } @@ -89,28 +89,28 @@ ignoreFunc(SyscallDesc *desc, int callnum, Process *process, SyscallReturn exitFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - new SimExitEvent("target called exit()", xc->getSyscallArg(0) & 0xff); + new SimExitEvent("target called exit()", tc->getSyscallArg(0) & 0xff); return 1; } SyscallReturn -getpagesizeFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) +getpagesizeFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc) { return (int)VMPageSize; } SyscallReturn -obreakFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) +obreakFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc) { Addr junk; // change brk addr to first arg - Addr new_brk = xc->getSyscallArg(0); + Addr new_brk = tc->getSyscallArg(0); if (new_brk != 0) { for (ChunkGenerator gen(p->brk_point, new_brk - p->brk_point, VMPageSize); !gen.done(); gen.next()) { @@ -126,9 +126,9 @@ obreakFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) SyscallReturn -closeFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) +closeFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc) { - int target_fd = xc->getSyscallArg(0); + int target_fd = tc->getSyscallArg(0); int status = close(p->sim_fd(target_fd)); if (status >= 0) p->free_fd(target_fd); @@ -137,28 +137,28 @@ closeFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) SyscallReturn -readFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) +readFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc) { - int fd = p->sim_fd(xc->getSyscallArg(0)); - int nbytes = xc->getSyscallArg(2); - BufferArg bufArg(xc->getSyscallArg(1), nbytes); + int fd = p->sim_fd(tc->getSyscallArg(0)); + int nbytes = tc->getSyscallArg(2); + BufferArg bufArg(tc->getSyscallArg(1), nbytes); int bytes_read = read(fd, bufArg.bufferPtr(), nbytes); if (bytes_read != -1) - bufArg.copyOut(xc->getMemPort()); + bufArg.copyOut(tc->getMemPort()); return bytes_read; } SyscallReturn -writeFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) +writeFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc) { - int fd = p->sim_fd(xc->getSyscallArg(0)); - int nbytes = xc->getSyscallArg(2); - BufferArg bufArg(xc->getSyscallArg(1), nbytes); + int fd = p->sim_fd(tc->getSyscallArg(0)); + int nbytes = tc->getSyscallArg(2); + BufferArg bufArg(tc->getSyscallArg(1), nbytes); - bufArg.copyIn(xc->getMemPort()); + bufArg.copyIn(tc->getMemPort()); int bytes_written = write(fd, bufArg.bufferPtr(), nbytes); @@ -169,11 +169,11 @@ writeFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) SyscallReturn -lseekFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) +lseekFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc) { - int fd = p->sim_fd(xc->getSyscallArg(0)); - uint64_t offs = xc->getSyscallArg(1); - int whence = xc->getSyscallArg(2); + int fd = p->sim_fd(tc->getSyscallArg(0)); + uint64_t offs = tc->getSyscallArg(1); + int whence = tc->getSyscallArg(2); off_t result = lseek(fd, offs, whence); @@ -182,7 +182,7 @@ lseekFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) SyscallReturn -munmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) +munmapFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc) { // given that we don't really implement mmap, munmap is really easy return 0; @@ -192,24 +192,24 @@ munmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) const char *hostname = "m5.eecs.umich.edu"; SyscallReturn -gethostnameFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) +gethostnameFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc) { - int name_len = xc->getSyscallArg(1); - BufferArg name(xc->getSyscallArg(0), name_len); + int name_len = tc->getSyscallArg(1); + BufferArg name(tc->getSyscallArg(0), name_len); strncpy((char *)name.bufferPtr(), hostname, name_len); - name.copyOut(xc->getMemPort()); + name.copyOut(tc->getMemPort()); return 0; } SyscallReturn -unlinkFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) +unlinkFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc) { string path; - if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0))) + if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0))) return (TheISA::IntReg)-EFAULT; int result = unlink(path.c_str()); @@ -217,16 +217,16 @@ unlinkFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) } SyscallReturn -renameFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) +renameFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc) { string old_name; - if (!xc->getMemPort()->tryReadString(old_name, xc->getSyscallArg(0))) + if (!tc->getMemPort()->tryReadString(old_name, tc->getSyscallArg(0))) return -EFAULT; string new_name; - if (!xc->getMemPort()->tryReadString(new_name, xc->getSyscallArg(1))) + if (!tc->getMemPort()->tryReadString(new_name, tc->getSyscallArg(1))) return -EFAULT; int64_t result = rename(old_name.c_str(), new_name.c_str()); @@ -234,45 +234,45 @@ renameFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) } SyscallReturn -truncateFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) +truncateFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc) { string path; - if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0))) + if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0))) return -EFAULT; - off_t length = xc->getSyscallArg(1); + off_t length = tc->getSyscallArg(1); int result = truncate(path.c_str(), length); return (result == -1) ? -errno : result; } SyscallReturn -ftruncateFunc(SyscallDesc *desc, int num, Process *process, ExecContext *xc) +ftruncateFunc(SyscallDesc *desc, int num, Process *process, ThreadContext *tc) { - int fd = process->sim_fd(xc->getSyscallArg(0)); + int fd = process->sim_fd(tc->getSyscallArg(0)); if (fd < 0) return -EBADF; - off_t length = xc->getSyscallArg(1); + off_t length = tc->getSyscallArg(1); int result = ftruncate(fd, length); return (result == -1) ? -errno : result; } SyscallReturn -chownFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) +chownFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc) { string path; - if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0))) + if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0))) return -EFAULT; /* XXX endianess */ - uint32_t owner = xc->getSyscallArg(1); + uint32_t owner = tc->getSyscallArg(1); uid_t hostOwner = owner; - uint32_t group = xc->getSyscallArg(2); + uint32_t group = tc->getSyscallArg(2); gid_t hostGroup = group; int result = chown(path.c_str(), hostOwner, hostGroup); @@ -280,17 +280,17 @@ chownFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) } SyscallReturn -fchownFunc(SyscallDesc *desc, int num, Process *process, ExecContext *xc) +fchownFunc(SyscallDesc *desc, int num, Process *process, ThreadContext *tc) { - int fd = process->sim_fd(xc->getSyscallArg(0)); + int fd = process->sim_fd(tc->getSyscallArg(0)); if (fd < 0) return -EBADF; /* XXX endianess */ - uint32_t owner = xc->getSyscallArg(1); + uint32_t owner = tc->getSyscallArg(1); uid_t hostOwner = owner; - uint32_t group = xc->getSyscallArg(2); + uint32_t group = tc->getSyscallArg(2); gid_t hostGroup = group; int result = fchown(fd, hostOwner, hostGroup); @@ -300,14 +300,14 @@ fchownFunc(SyscallDesc *desc, int num, Process *process, ExecContext *xc) SyscallReturn fcntlFunc(SyscallDesc *desc, int num, Process *process, - ExecContext *xc) + ThreadContext *tc) { - int fd = xc->getSyscallArg(0); + int fd = tc->getSyscallArg(0); if (fd < 0 || process->sim_fd(fd) < 0) return -EBADF; - int cmd = xc->getSyscallArg(1); + int cmd = tc->getSyscallArg(1); switch (cmd) { case 0: // F_DUPFD // if we really wanted to support this, we'd need to do it @@ -342,7 +342,7 @@ fcntlFunc(SyscallDesc *desc, int num, Process *process, SyscallReturn pipePseudoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { int fds[2], sim_fds[2]; int pipe_retval = pipe(fds); @@ -357,99 +357,99 @@ pipePseudoFunc(SyscallDesc *desc, int callnum, Process *process, // Alpha Linux convention for pipe() is that fd[0] is returned as // the return value of the function, and fd[1] is returned in r20. - xc->setIntReg(SyscallPseudoReturnReg, sim_fds[1]); + tc->setIntReg(SyscallPseudoReturnReg, sim_fds[1]); return sim_fds[0]; } SyscallReturn getpidPseudoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { // Make up a PID. There's no interprocess communication in // fake_syscall mode, so there's no way for a process to know it's // not getting a unique value. - xc->setIntReg(SyscallPseudoReturnReg, 99); + tc->setIntReg(SyscallPseudoReturnReg, 99); return 100; } SyscallReturn getuidPseudoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { // Make up a UID and EUID... it shouldn't matter, and we want the // simulation to be deterministic. // EUID goes in r20. - xc->setIntReg(SyscallPseudoReturnReg, 100); //EUID + tc->setIntReg(SyscallPseudoReturnReg, 100); //EUID return 100; // UID } SyscallReturn getgidPseudoFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { // Get current group ID. EGID goes in r20. - xc->setIntReg(SyscallPseudoReturnReg, 100); //EGID + tc->setIntReg(SyscallPseudoReturnReg, 100); //EGID return 100; } SyscallReturn setuidFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { // can't fathom why a benchmark would call this. - warn("Ignoring call to setuid(%d)\n", xc->getSyscallArg(0)); + warn("Ignoring call to setuid(%d)\n", tc->getSyscallArg(0)); return 0; } SyscallReturn getpidFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { // Make up a PID. There's no interprocess communication in // fake_syscall mode, so there's no way for a process to know it's // not getting a unique value. - xc->setIntReg(SyscallPseudoReturnReg, 99); //PID + tc->setIntReg(SyscallPseudoReturnReg, 99); //PID return 100; } SyscallReturn getppidFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { return 99; } SyscallReturn getuidFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { return 100; // UID } SyscallReturn geteuidFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { return 100; // UID } SyscallReturn getgidFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { return 100; } SyscallReturn getegidFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { return 100; } diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh index b21e299e9..874eaf6a4 100644 --- a/src/sim/syscall_emul.hh +++ b/src/sim/syscall_emul.hh @@ -54,7 +54,7 @@ #include "base/misc.hh" #include "base/trace.hh" #include "cpu/base.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "mem/translating_port.hh" #include "mem/page_table.hh" #include "sim/process.hh" @@ -68,7 +68,7 @@ class SyscallDesc { /// Typedef for target syscall handler functions. typedef SyscallReturn (*FuncPtr)(SyscallDesc *, int num, - Process *, ExecContext *); + Process *, ThreadContext *); const char *name; //!< Syscall name (e.g., "open"). FuncPtr funcPtr; //!< Pointer to emulation function. @@ -78,7 +78,7 @@ class SyscallDesc { enum Flags { /// Don't set return regs according to funcPtr return value. /// Used for syscalls with non-standard return conventions - /// that explicitly set the ExecContext regs (e.g., + /// that explicitly set the ThreadContext regs (e.g., /// sigreturn). SuppressReturnValue = 1 }; @@ -90,7 +90,7 @@ class SyscallDesc { } /// Emulate the syscall. Public interface for calling through funcPtr. - void doSyscall(int callnum, Process *proc, ExecContext *xc); + void doSyscall(int callnum, Process *proc, ThreadContext *tc); }; @@ -172,129 +172,129 @@ class TypedBufferArg : public BaseBufferArg /// Handler for unimplemented syscalls that we haven't thought about. SyscallReturn unimplementedFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Handler for unimplemented syscalls that we never intend to /// implement (signal handling, etc.) and should not affect the correct /// behavior of the program. Print a warning only if the appropriate /// trace flag is enabled. Return success to the target program. SyscallReturn ignoreFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target exit() handler: terminate simulation. SyscallReturn exitFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target getpagesize() handler. SyscallReturn getpagesizeFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target obreak() handler: set brk address. SyscallReturn obreakFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target close() handler. SyscallReturn closeFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target read() handler. SyscallReturn readFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target write() handler. SyscallReturn writeFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target lseek() handler. SyscallReturn lseekFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target munmap() handler. SyscallReturn munmapFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target gethostname() handler. SyscallReturn gethostnameFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target unlink() handler. SyscallReturn unlinkFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target rename() handler. SyscallReturn renameFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target truncate() handler. SyscallReturn truncateFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target ftruncate() handler. SyscallReturn ftruncateFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target chown() handler. SyscallReturn chownFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target fchown() handler. SyscallReturn fchownFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target fnctl() handler. SyscallReturn fcntlFunc(SyscallDesc *desc, int num, - Process *process, ExecContext *xc); + Process *process, ThreadContext *tc); /// Target setuid() handler. SyscallReturn setuidFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target getpid() handler. SyscallReturn getpidFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target getuid() handler. SyscallReturn getuidFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target getgid() handler. SyscallReturn getgidFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target getppid() handler. SyscallReturn getppidFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target geteuid() handler. SyscallReturn geteuidFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target getegid() handler. SyscallReturn getegidFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Pseudo Funcs - These functions use a different return convension, /// returning a second value in a register other than the normal return register SyscallReturn pipePseudoFunc(SyscallDesc *desc, int num, - Process *process, ExecContext *xc); + Process *process, ThreadContext *tc); /// Target getpidPseudo() handler. SyscallReturn getpidPseudoFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target getuidPseudo() handler. SyscallReturn getuidPseudoFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// Target getgidPseudo() handler. SyscallReturn getgidPseudoFunc(SyscallDesc *desc, int num, - Process *p, ExecContext *xc); + Process *p, ThreadContext *tc); /// This struct is used to build an target-OS-dependent table that @@ -338,10 +338,10 @@ getElapsedTime(T1 &sec, T2 &usec) template <class OS> SyscallReturn ioctlFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - int fd = xc->getSyscallArg(0); - unsigned req = xc->getSyscallArg(1); + int fd = tc->getSyscallArg(0); + unsigned req = tc->getSyscallArg(1); DPRINTF(SyscallVerbose, "ioctl(%d, 0x%x, ...)\n", fd, req); @@ -363,7 +363,7 @@ ioctlFunc(SyscallDesc *desc, int callnum, Process *process, default: fatal("Unsupported ioctl call: ioctl(%d, 0x%x, ...) @ 0x%llx\n", - fd, req, xc->readPC()); + fd, req, tc->readPC()); } } @@ -371,11 +371,11 @@ ioctlFunc(SyscallDesc *desc, int callnum, Process *process, template <class OS> SyscallReturn openFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { std::string path; - if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0))) + if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0))) return -EFAULT; if (path == "/dev/sysdev0") { @@ -385,8 +385,8 @@ openFunc(SyscallDesc *desc, int callnum, Process *process, return -ENOENT; } - int tgtFlags = xc->getSyscallArg(1); - int mode = xc->getSyscallArg(2); + int tgtFlags = tc->getSyscallArg(1); + int mode = tc->getSyscallArg(2); int hostFlags = 0; // translate open flags @@ -418,14 +418,14 @@ openFunc(SyscallDesc *desc, int callnum, Process *process, template <class OS> SyscallReturn chmodFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { std::string path; - if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0))) + if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0))) return -EFAULT; - uint32_t mode = xc->getSyscallArg(1); + uint32_t mode = tc->getSyscallArg(1); mode_t hostMode = 0; // XXX translate mode flags via OS::something??? @@ -444,15 +444,15 @@ chmodFunc(SyscallDesc *desc, int callnum, Process *process, template <class OS> SyscallReturn fchmodFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - int fd = xc->getSyscallArg(0); + int fd = tc->getSyscallArg(0); if (fd < 0 || process->sim_fd(fd) < 0) { // doesn't map to any simulator fd: not a valid target fd return -EBADF; } - uint32_t mode = xc->getSyscallArg(1); + uint32_t mode = tc->getSyscallArg(1); mode_t hostMode = 0; // XXX translate mode flags via OS::someting??? @@ -471,11 +471,11 @@ fchmodFunc(SyscallDesc *desc, int callnum, Process *process, template <class OS> SyscallReturn statFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { std::string path; - if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0))) + if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0))) return -EFAULT; struct stat hostBuf; @@ -484,7 +484,7 @@ statFunc(SyscallDesc *desc, int callnum, Process *process, if (result < 0) return -errno; - OS::copyOutStatBuf(xc->getMemPort(), xc->getSyscallArg(1), &hostBuf); + OS::copyOutStatBuf(tc->getMemPort(), tc->getSyscallArg(1), &hostBuf); return 0; } @@ -494,9 +494,9 @@ statFunc(SyscallDesc *desc, int callnum, Process *process, template <class OS> SyscallReturn fstat64Func(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - int fd = xc->getSyscallArg(0); + int fd = tc->getSyscallArg(0); if (fd < 0 || process->sim_fd(fd) < 0) { // doesn't map to any simulator fd: not a valid target fd return -EBADF; @@ -513,7 +513,7 @@ fstat64Func(SyscallDesc *desc, int callnum, Process *process, if (result < 0) return -errno; - OS::copyOutStat64Buf(xc->getMemPort(), fd, xc->getSyscallArg(1), &hostBuf); + OS::copyOutStat64Buf(tc->getMemPort(), fd, tc->getSyscallArg(1), &hostBuf); return 0; } @@ -523,11 +523,11 @@ fstat64Func(SyscallDesc *desc, int callnum, Process *process, template <class OS> SyscallReturn lstatFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { std::string path; - if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0))) + if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0))) return -EFAULT; struct stat hostBuf; @@ -536,7 +536,7 @@ lstatFunc(SyscallDesc *desc, int callnum, Process *process, if (result < 0) return -errno; - OS::copyOutStatBuf(xc->getMemPort(), xc->getSyscallArg(1), &hostBuf); + OS::copyOutStatBuf(tc->getMemPort(), tc->getSyscallArg(1), &hostBuf); return 0; } @@ -545,11 +545,11 @@ lstatFunc(SyscallDesc *desc, int callnum, Process *process, template <class OS> SyscallReturn lstat64Func(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { std::string path; - if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0))) + if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0))) return -EFAULT; #if BSD_HOST @@ -563,7 +563,7 @@ lstat64Func(SyscallDesc *desc, int callnum, Process *process, if (result < 0) return -errno; - OS::copyOutStat64Buf(xc->getMemPort(), -1, xc->getSyscallArg(1), &hostBuf); + OS::copyOutStat64Buf(tc->getMemPort(), -1, tc->getSyscallArg(1), &hostBuf); return 0; } @@ -572,9 +572,9 @@ lstat64Func(SyscallDesc *desc, int callnum, Process *process, template <class OS> SyscallReturn fstatFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - int fd = process->sim_fd(xc->getSyscallArg(0)); + int fd = process->sim_fd(tc->getSyscallArg(0)); DPRINTF(SyscallVerbose, "fstat(%d, ...)\n", fd); @@ -587,7 +587,7 @@ fstatFunc(SyscallDesc *desc, int callnum, Process *process, if (result < 0) return -errno; - OS::copyOutStatBuf(xc->getMemPort(), xc->getSyscallArg(1), &hostBuf); + OS::copyOutStatBuf(tc->getMemPort(), tc->getSyscallArg(1), &hostBuf); return 0; } @@ -597,11 +597,11 @@ fstatFunc(SyscallDesc *desc, int callnum, Process *process, template <class OS> SyscallReturn statfsFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { std::string path; - if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0))) + if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0))) return -EFAULT; struct statfs hostBuf; @@ -610,7 +610,7 @@ statfsFunc(SyscallDesc *desc, int callnum, Process *process, if (result < 0) return -errno; - OS::copyOutStatfsBuf(xc->getMemPort(), xc->getSyscallArg(1), &hostBuf); + OS::copyOutStatfsBuf(tc->getMemPort(), tc->getSyscallArg(1), &hostBuf); return 0; } @@ -620,9 +620,9 @@ statfsFunc(SyscallDesc *desc, int callnum, Process *process, template <class OS> SyscallReturn fstatfsFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - int fd = process->sim_fd(xc->getSyscallArg(0)); + int fd = process->sim_fd(tc->getSyscallArg(0)); if (fd < 0) return -EBADF; @@ -633,7 +633,7 @@ fstatfsFunc(SyscallDesc *desc, int callnum, Process *process, if (result < 0) return -errno; - OS::copyOutStatfsBuf(xc->getMemPort(), xc->getSyscallArg(1), &hostBuf); + OS::copyOutStatfsBuf(tc->getMemPort(), tc->getSyscallArg(1), &hostBuf); return 0; } @@ -643,17 +643,17 @@ fstatfsFunc(SyscallDesc *desc, int callnum, Process *process, template <class OS> SyscallReturn writevFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - int fd = xc->getSyscallArg(0); + int fd = tc->getSyscallArg(0); if (fd < 0 || process->sim_fd(fd) < 0) { // doesn't map to any simulator fd: not a valid target fd return -EBADF; } - TranslatingPort *p = xc->getMemPort(); - uint64_t tiov_base = xc->getSyscallArg(1); - size_t count = xc->getSyscallArg(2); + TranslatingPort *p = tc->getMemPort(); + uint64_t tiov_base = tc->getSyscallArg(1); + size_t count = tc->getSyscallArg(2); struct iovec hiov[count]; for (int i = 0; i < count; ++i) { @@ -695,14 +695,14 @@ writevFunc(SyscallDesc *desc, int callnum, Process *process, /// anything else. template <class OS> SyscallReturn -mmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) +mmapFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc) { - Addr start = xc->getSyscallArg(0); - uint64_t length = xc->getSyscallArg(1); - // int prot = xc->getSyscallArg(2); - int flags = xc->getSyscallArg(3); - // int fd = p->sim_fd(xc->getSyscallArg(4)); - // int offset = xc->getSyscallArg(5); + Addr start = tc->getSyscallArg(0); + uint64_t length = tc->getSyscallArg(1); + // int prot = tc->getSyscallArg(2); + int flags = tc->getSyscallArg(3); + // int fd = p->sim_fd(tc->getSyscallArg(4)); + // int offset = tc->getSyscallArg(5); if ((start % TheISA::VMPageSize) != 0 || (length % TheISA::VMPageSize) != 0) { @@ -724,7 +724,7 @@ mmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) if (!(flags & OS::TGT_MAP_ANONYMOUS)) { warn("allowing mmap of file @ fd %d. " - "This will break if not /dev/zero.", xc->getSyscallArg(4)); + "This will break if not /dev/zero.", tc->getSyscallArg(4)); } return start; @@ -734,10 +734,10 @@ mmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc) template <class OS> SyscallReturn getrlimitFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - unsigned resource = xc->getSyscallArg(0); - TypedBufferArg<typename OS::rlimit> rlp(xc->getSyscallArg(1)); + unsigned resource = tc->getSyscallArg(0); + TypedBufferArg<typename OS::rlimit> rlp(tc->getSyscallArg(1)); switch (resource) { case OS::TGT_RLIMIT_STACK: @@ -754,7 +754,7 @@ getrlimitFunc(SyscallDesc *desc, int callnum, Process *process, break; } - rlp.copyOut(xc->getMemPort()); + rlp.copyOut(tc->getMemPort()); return 0; } @@ -762,16 +762,16 @@ getrlimitFunc(SyscallDesc *desc, int callnum, Process *process, template <class OS> SyscallReturn gettimeofdayFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - TypedBufferArg<typename OS::timeval> tp(xc->getSyscallArg(0)); + TypedBufferArg<typename OS::timeval> tp(tc->getSyscallArg(0)); getElapsedTime(tp->tv_sec, tp->tv_usec); tp->tv_sec += seconds_since_epoch; tp->tv_sec = htog(tp->tv_sec); tp->tv_usec = htog(tp->tv_usec); - tp.copyOut(xc->getMemPort()); + tp.copyOut(tc->getMemPort()); return 0; } @@ -781,15 +781,15 @@ gettimeofdayFunc(SyscallDesc *desc, int callnum, Process *process, template <class OS> SyscallReturn utimesFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { std::string path; - if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0))) + if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0))) return -EFAULT; - TypedBufferArg<typename OS::timeval [2]> tp(xc->getSyscallArg(1)); - tp.copyIn(xc->getMemPort()); + TypedBufferArg<typename OS::timeval [2]> tp(tc->getSyscallArg(1)); + tp.copyIn(tc->getMemPort()); struct timeval hostTimeval[2]; for (int i = 0; i < 2; ++i) @@ -808,10 +808,10 @@ utimesFunc(SyscallDesc *desc, int callnum, Process *process, template <class OS> SyscallReturn getrusageFunc(SyscallDesc *desc, int callnum, Process *process, - ExecContext *xc) + ThreadContext *tc) { - int who = xc->getSyscallArg(0); // THREAD, SELF, or CHILDREN - TypedBufferArg<typename OS::rusage> rup(xc->getSyscallArg(1)); + int who = tc->getSyscallArg(0); // THREAD, SELF, or CHILDREN + TypedBufferArg<typename OS::rusage> rup(tc->getSyscallArg(1)); if (who != OS::TGT_RUSAGE_SELF) { // don't really handle THREAD or CHILDREN, but just warn and @@ -841,7 +841,7 @@ getrusageFunc(SyscallDesc *desc, int callnum, Process *process, rup->ru_nvcsw = 0; rup->ru_nivcsw = 0; - rup.copyOut(xc->getMemPort()); + rup.copyOut(tc->getMemPort()); return 0; } diff --git a/src/sim/system.cc b/src/sim/system.cc index 89f39491e..e177aa84c 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -2,7 +2,7 @@ #include "base/loader/object_file.hh" #include "base/loader/symtab.hh" #include "base/trace.hh" -#include "cpu/exec_context.hh" +#include "cpu/thread_context.hh" #include "mem/mem_object.hh" #include "mem/physical.hh" #include "sim/builder.hh" @@ -115,26 +115,26 @@ int rgdb_wait = -1; #endif // FULL_SYSTEM int -System::registerExecContext(ExecContext *xc, int id) +System::registerThreadContext(ThreadContext *tc, int id) { if (id == -1) { - for (id = 0; id < execContexts.size(); id++) { - if (!execContexts[id]) + for (id = 0; id < threadContexts.size(); id++) { + if (!threadContexts[id]) break; } } - if (execContexts.size() <= id) - execContexts.resize(id + 1); + if (threadContexts.size() <= id) + threadContexts.resize(id + 1); - if (execContexts[id]) + if (threadContexts[id]) panic("Cannot have two CPUs with the same id (%d)\n", id); - execContexts[id] = xc; + threadContexts[id] = tc; numcpus++; #if FULL_SYSTEM - RemoteGDB *rgdb = new RemoteGDB(this, xc); + RemoteGDB *rgdb = new RemoteGDB(this, tc); GDBListener *gdbl = new GDBListener(rgdb, 7000 + id); gdbl->listen(); /** @@ -158,21 +158,21 @@ void System::startup() { int i; - for (i = 0; i < execContexts.size(); i++) - execContexts[i]->activate(0); + for (i = 0; i < threadContexts.size(); i++) + threadContexts[i]->activate(0); } void -System::replaceExecContext(ExecContext *xc, int id) +System::replaceThreadContext(ThreadContext *tc, int id) { - if (id >= execContexts.size()) { - panic("replaceExecContext: bad id, %d >= %d\n", - id, execContexts.size()); + if (id >= threadContexts.size()) { + panic("replaceThreadContext: bad id, %d >= %d\n", + id, threadContexts.size()); } - execContexts[id] = xc; + threadContexts[id] = tc; #if FULL_SYSTEM - remoteGDB[id]->replaceExecContext(xc); + remoteGDB[id]->replaceThreadContext(tc); #endif // FULL_SYSTEM } diff --git a/src/sim/system.hh b/src/sim/system.hh index 65cb0c95c..3a9fdc3d2 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -48,7 +48,7 @@ #endif class BaseCPU; -class ExecContext; +class ThreadContext; class ObjectFile; class PhysicalMemory; @@ -65,12 +65,12 @@ class System : public SimObject PhysicalMemory *physmem; PCEventQueue pcEventQueue; - std::vector<ExecContext *> execContexts; + std::vector<ThreadContext *> threadContexts; int numcpus; int getNumCPUs() { - if (numcpus != execContexts.size()) + if (numcpus != threadContexts.size()) panic("cpu array not fully populated!"); return numcpus; @@ -208,8 +208,8 @@ class System : public SimObject #endif // FULL_SYSTEM - int registerExecContext(ExecContext *xc, int xcIndex); - void replaceExecContext(ExecContext *xc, int xcIndex); + int registerThreadContext(ThreadContext *tc, int tcIndex); + void replaceThreadContext(ThreadContext *tc, int tcIndex); void regStats(); void serialize(std::ostream &os); diff --git a/src/sim/vptr.hh b/src/sim/vptr.hh index a0e74139f..bcc22f0ca 100644 --- a/src/sim/vptr.hh +++ b/src/sim/vptr.hh @@ -34,7 +34,7 @@ #include "arch/vtophys.hh" #include "arch/isa_traits.hh" -class ExecContext; +class ThreadContext; template <class T> class VPtr @@ -43,17 +43,17 @@ class VPtr typedef T Type; private: - ExecContext *xc; + ThreadContext *tc; Addr ptr; public: - ExecContext *GetXC() const { return xc; } + ThreadContext *GetTC() const { return tc; } Addr GetPointer() const { return ptr; } public: - explicit VPtr(ExecContext *_xc, Addr p = 0) : xc(_xc), ptr(p) { } + explicit VPtr(ThreadContext *_tc, Addr p = 0) : tc(_tc), ptr(p) { } template <class U> - VPtr(const VPtr<U> &vp) : xc(vp.GetXC()), ptr(vp.GetPointer()) {} + VPtr(const VPtr<U> &vp) : tc(vp.GetTC()), ptr(vp.GetPointer()) {} ~VPtr() {} bool operator!() const @@ -90,7 +90,7 @@ class VPtr template <class U> const VPtr<T> &operator=(const VPtr<U> &vp) { - xc = vp.GetXC(); + tc = vp.GetTC(); ptr = vp.GetPointer(); return *this; @@ -99,7 +99,7 @@ class VPtr operator T *() { panic("Needs to be rewritten\n"); -/* void *addr = vtomem(xc, ptr, sizeof(T)); +/* void *addr = vtomem(tc, ptr, sizeof(T)); return (T *)addr; */ } @@ -107,7 +107,7 @@ class VPtr T *operator->() { panic("Needs to be rewritten\n"); -/* void *addr = vtomem(xc, ptr, sizeof(T)); +/* void *addr = vtomem(tc, ptr, sizeof(T)); return (T *)addr; */ } @@ -115,7 +115,7 @@ class VPtr T &operator*() { panic("Needs to be rewritten\n"); -/* void *addr = vtomem(xc, ptr, sizeof(T)); +/* void *addr = vtomem(tc, ptr, sizeof(T)); return *(T *)addr; */ } |