diff options
| -rw-r--r-- | src/cpu/DummyChecker.py | 1 | ||||
| -rw-r--r-- | src/cpu/SConscript | 2 | ||||
| -rw-r--r-- | src/cpu/dummy_checker.cc (renamed from src/cpu/dummy_checker_builder.cc) | 20 | ||||
| -rw-r--r-- | src/cpu/dummy_checker.hh | 56 | ||||
| -rw-r--r-- | src/cpu/o3/O3Checker.py | 2 | ||||
| -rwxr-xr-x | src/cpu/o3/SConscript | 2 | ||||
| -rw-r--r-- | src/cpu/o3/checker.cc (renamed from src/cpu/o3/checker_builder.cc) | 19 | ||||
| -rw-r--r-- | src/cpu/o3/checker.hh | 61 |
8 files changed, 124 insertions, 39 deletions
diff --git a/src/cpu/DummyChecker.py b/src/cpu/DummyChecker.py index 3c276e1d2..e75f7057e 100644 --- a/src/cpu/DummyChecker.py +++ b/src/cpu/DummyChecker.py @@ -40,3 +40,4 @@ from BaseCPU import BaseCPU class DummyChecker(BaseCPU): type = 'DummyChecker' + cxx_header = 'cpu/dummy_checker.hh' diff --git a/src/cpu/SConscript b/src/cpu/SConscript index e1ba59b8b..913e58a8e 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -127,7 +127,7 @@ if env['TARGET_ISA'] == 'sparc': SimObject('DummyChecker.py') Source('checker/cpu.cc') -Source('dummy_checker_builder.cc') +Source('dummy_checker.cc') DebugFlag('Checker') DebugFlag('Activity') diff --git a/src/cpu/dummy_checker_builder.cc b/src/cpu/dummy_checker.cc index fd2c9f74b..6a0210e3b 100644 --- a/src/cpu/dummy_checker_builder.cc +++ b/src/cpu/dummy_checker.cc @@ -37,26 +37,8 @@ * Authors: Geoffrey Blake */ -#include <string> - -#include "cpu/checker/cpu.hh" -#include "cpu/inst_seq.hh" +#include "cpu/dummy_checker.hh" #include "params/DummyChecker.hh" -#include "sim/process.hh" -#include "sim/sim_object.hh" - -class MemObject; - -/** - * Specific non-templated derived class used for SimObject configuration. - */ -class DummyChecker : public CheckerCPU -{ - public: - DummyChecker(Params *p) - : CheckerCPU(p) - { } -}; //////////////////////////////////////////////////////////////////////// // diff --git a/src/cpu/dummy_checker.hh b/src/cpu/dummy_checker.hh new file mode 100644 index 000000000..59ca3f3af --- /dev/null +++ b/src/cpu/dummy_checker.hh @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Geoffrey Blake + */ + +#ifndef __CPU_DUMMY_CHECKER_HH__ +#define __CPU_DUMMY_CHECKER_HH__ + +#include "cpu/checker/cpu.hh" + +/** + * Specific non-templated derived class used for SimObject configuration. + */ +class DummyChecker : public CheckerCPU +{ + public: + DummyChecker(Params *p) + : CheckerCPU(p) + { } +}; + +#endif // __CPU_DUMMY_CHECKER_HH__ diff --git a/src/cpu/o3/O3Checker.py b/src/cpu/o3/O3Checker.py index 5021b5ea7..d2dc8e95b 100644 --- a/src/cpu/o3/O3Checker.py +++ b/src/cpu/o3/O3Checker.py @@ -31,6 +31,8 @@ from BaseCPU import BaseCPU class O3Checker(BaseCPU): type = 'O3Checker' + cxx_header = 'cpu/o3/checker.hh' + exitOnError = Param.Bool(False, "Exit on an error") updateOnError = Param.Bool(False, "Update the checker with the main CPU's state on an error") diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript index 8ca32c898..5e8e2ea66 100755 --- a/src/cpu/o3/SConscript +++ b/src/cpu/o3/SConscript @@ -79,4 +79,4 @@ if 'O3CPU' in env['CPU_MODELS']: 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ]) SimObject('O3Checker.py') - Source('checker_builder.cc') + Source('checker.cc') diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker.cc index 757b1a87f..c99428617 100644 --- a/src/cpu/o3/checker_builder.cc +++ b/src/cpu/o3/checker.cc @@ -40,32 +40,15 @@ * Authors: Kevin Lim */ -#include <string> - #include "cpu/checker/cpu_impl.hh" -#include "cpu/o3/dyn_inst.hh" -#include "cpu/o3/impl.hh" -#include "cpu/inst_seq.hh" +#include "cpu/o3/checker.hh" #include "params/O3Checker.hh" -#include "sim/process.hh" -#include "sim/sim_object.hh" class MemObject; template class Checker<O3CPUImpl>; -/** - * Specific non-templated derived class used for SimObject configuration. - */ -class O3Checker : public Checker<O3CPUImpl> -{ - public: - O3Checker(Params *p) - : Checker<O3CPUImpl>(p) - { } -}; - //////////////////////////////////////////////////////////////////////// // // CheckerCPU Simulation Object diff --git a/src/cpu/o3/checker.hh b/src/cpu/o3/checker.hh new file mode 100644 index 000000000..f9e2088c1 --- /dev/null +++ b/src/cpu/o3/checker.hh @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Kevin Lim + */ + +#ifndef __CPU_O3_CHECKER_HH__ +#define __CPU_O3_CHECKER_HH__ + +#include "cpu/checker/cpu.hh" +#include "cpu/o3/dyn_inst.hh" +#include "cpu/o3/impl.hh" + +/** + * Specific non-templated derived class used for SimObject configuration. + */ +class O3Checker : public Checker<O3CPUImpl> +{ + public: + O3Checker(Params *p) + : Checker<O3CPUImpl>(p) + { } +}; + +#endif // __CPU_O3_CHECKER_HH__ |