summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--src/cpu/SConscript11
-rw-r--r--src/cpu/base_dyn_inst_impl.hh (renamed from src/cpu/base_dyn_inst.cc)26
-rw-r--r--src/cpu/checker/cpu_impl.hh (renamed from src/cpu/checker/cpu.cc)14
-rw-r--r--src/cpu/o3/base_dyn_inst.cc40
-rw-r--r--src/cpu/o3/bpred_unit.cc4
-rw-r--r--src/cpu/o3/checker_builder.cc (renamed from src/cpu/checker/o3_builder.cc)5
-rw-r--r--src/cpu/ozone/bpred_unit.cc36
-rw-r--r--src/cpu/ozone/checker_builder.cc (renamed from src/cpu/checker/ozone_builder.cc)5
-rw-r--r--src/cpu/ozone/ozone_base_dyn_inst.cc39
-rw-r--r--src/cpu/ozone/simple_base_dyn_inst.cc39
10 files changed, 169 insertions, 50 deletions
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 608625ed4..ab3c1f1d2 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -122,11 +122,11 @@ if 'FastCPU' in env['CPU_MODELS']:
if 'AlphaO3CPU' in env['CPU_MODELS']:
sources += Split('''
- base_dyn_inst.cc
o3/2bit_local_pred.cc
o3/alpha_dyn_inst.cc
o3/alpha_cpu.cc
o3/alpha_cpu_builder.cc
+ o3/base_dyn_inst.cc
o3/bpred_unit.cc
o3/btb.cc
o3/commit.cc
@@ -149,7 +149,7 @@ if 'AlphaO3CPU' in env['CPU_MODELS']:
o3/tournament_pred.cc
''')
if 'CheckerCPU' in env['CPU_MODELS']:
- sources += Split('checker/o3_builder.cc')
+ sources += Split('o3/checker_builder.cc')
if 'OzoneSimpleCPU' in env['CPU_MODELS']:
sources += Split('''
@@ -161,18 +161,19 @@ if 'OzoneSimpleCPU' in env['CPU_MODELS']:
ozone/inst_queue.cc
ozone/rename_table.cc
''')
- if 'CheckerCPU' in env['CPU_MODELS']:
- sources += Split('checker/ozone_builder.cc')
if 'OzoneCPU' in env['CPU_MODELS']:
sources += Split('''
+ ozone/base_dyn_inst.cc
+ ozone/bpred_unit.cc
ozone/lsq_unit.cc
ozone/lw_back_end.cc
ozone/lw_lsq.cc
''')
+ if 'CheckerCPU' in env['CPU_MODELS']:
+ sources += Split('ozone/checker_builder.cc')
if 'CheckerCPU' in env['CPU_MODELS']:
- sources += Split('checker/cpu.cc')
checker_supports = False
for i in CheckerSupportedCPUList:
if i in env['CPU_MODELS']:
diff --git a/src/cpu/base_dyn_inst.cc b/src/cpu/base_dyn_inst_impl.hh
index 5e2a6392a..91424faad 100644
--- a/src/cpu/base_dyn_inst.cc
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -41,10 +41,6 @@
#include "mem/request.hh"
#include "cpu/base_dyn_inst.hh"
-#include "cpu/o3/alpha_impl.hh"
-#include "cpu/o3/alpha_cpu.hh"
-//#include "cpu/ozone/simple_impl.hh"
-//#include "cpu/ozone/ozone_impl.hh"
using namespace std;
using namespace TheISA;
@@ -301,25 +297,3 @@ BaseDynInst<Impl>::eaSrcsReady()
return true;
}
-
-// Forward declaration
-template class BaseDynInst<AlphaSimpleImpl>;
-
-template <>
-int
-BaseDynInst<AlphaSimpleImpl>::instcount = 0;
-/*
-// Forward declaration
-template class BaseDynInst<SimpleImpl>;
-
-template <>
-int
-BaseDynInst<SimpleImpl>::instcount = 0;
-
-// Forward declaration
-template class BaseDynInst<OzoneImpl>;
-
-template <>
-int
-BaseDynInst<OzoneImpl>::instcount = 0;
-*/
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu_impl.hh
index 45c57d276..5091c7c1a 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu_impl.hh
@@ -43,16 +43,10 @@
#include "sim/sim_object.hh"
#include "sim/stats.hh"
-#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/o3/alpha_impl.hh"
-
-//#include "cpu/ozone/dyn_inst.hh"
-//#include "cpu/ozone/ozone_impl.hh"
-//#include "cpu/ozone/simple_impl.hh"
-
#if FULL_SYSTEM
#include "sim/system.hh"
#include "arch/vtophys.hh"
+#include "kern/kernel_stats.hh"
#endif // FULL_SYSTEM
using namespace std;
@@ -826,9 +820,3 @@ Checker<DynInstPtr>::dumpInsts()
}
}
-
-//template
-//class Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >;
-// Manually instantiate checker
-template
-class Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >;
diff --git a/src/cpu/o3/base_dyn_inst.cc b/src/cpu/o3/base_dyn_inst.cc
new file mode 100644
index 000000000..1f7540d6a
--- /dev/null
+++ b/src/cpu/o3/base_dyn_inst.cc
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ */
+
+#include "cpu/base_dyn_inst_impl.hh"
+#include "cpu/o3/alpha_cpu.hh"
+#include "cpu/o3/alpha_impl.hh"
+
+// Explicit instantiation
+template class BaseDynInst<AlphaSimpleImpl>;
+
+template <>
+int
+BaseDynInst<AlphaSimpleImpl>::instcount = 0;
diff --git a/src/cpu/o3/bpred_unit.cc b/src/cpu/o3/bpred_unit.cc
index 294438704..c35c0a0aa 100644
--- a/src/cpu/o3/bpred_unit.cc
+++ b/src/cpu/o3/bpred_unit.cc
@@ -31,9 +31,5 @@
#include "cpu/o3/bpred_unit_impl.hh"
#include "cpu/o3/alpha_impl.hh"
#include "cpu/o3/alpha_dyn_inst.hh"
-//#include "cpu/ozone/ozone_impl.hh"
-//#include "cpu/ozone/simple_impl.hh"
template class BPredUnit<AlphaSimpleImpl>;
-//template class BPredUnit<OzoneImpl>;
-//template class BPredUnit<SimpleImpl>;
diff --git a/src/cpu/checker/o3_builder.cc b/src/cpu/o3/checker_builder.cc
index 534a5e28c..58c40d00c 100644
--- a/src/cpu/checker/o3_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -30,7 +30,7 @@
#include <string>
-#include "cpu/checker/cpu.hh"
+#include "cpu/checker/cpu_impl.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/alpha_dyn_inst.hh"
#include "cpu/o3/alpha_impl.hh"
@@ -40,6 +40,9 @@
class MemObject;
+template
+class Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >;
+
/**
* Specific non-templated derived class used for SimObject configuration.
*/
diff --git a/src/cpu/ozone/bpred_unit.cc b/src/cpu/ozone/bpred_unit.cc
new file mode 100644
index 000000000..835324ce1
--- /dev/null
+++ b/src/cpu/ozone/bpred_unit.cc
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ */
+
+#include "cpu/o3/bpred_unit_impl.hh"
+#include "cpu/ozone/ozone_impl.hh"
+#include "cpu/ozone/simple_impl.hh"
+
+template class BPredUnit<OzoneImpl>;
+template class BPredUnit<SimpleImpl>;
diff --git a/src/cpu/checker/ozone_builder.cc b/src/cpu/ozone/checker_builder.cc
index 3c43ab503..f6786f24b 100644
--- a/src/cpu/checker/ozone_builder.cc
+++ b/src/cpu/ozone/checker_builder.cc
@@ -30,7 +30,7 @@
#include <string>
-#include "cpu/checker/cpu.hh"
+#include "cpu/checker/cpu_impl.hh"
#include "cpu/inst_seq.hh"
#include "cpu/ozone/dyn_inst.hh"
#include "cpu/ozone/ozone_impl.hh"
@@ -39,6 +39,9 @@
#include "sim/process.hh"
#include "sim/sim_object.hh"
+template
+class Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >;
+
/**
* Specific non-templated derived class used for SimObject configuration.
*/
diff --git a/src/cpu/ozone/ozone_base_dyn_inst.cc b/src/cpu/ozone/ozone_base_dyn_inst.cc
new file mode 100644
index 000000000..5a3a69dff
--- /dev/null
+++ b/src/cpu/ozone/ozone_base_dyn_inst.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ */
+
+#include "cpu/base_dyn_inst_impl.hh"
+#include "cpu/ozone/ozone_impl.hh"
+
+// Explicit instantiation
+template class BaseDynInst<OzoneImpl>;
+
+template <>
+int
+BaseDynInst<OzoneImpl>::instcount = 0;
diff --git a/src/cpu/ozone/simple_base_dyn_inst.cc b/src/cpu/ozone/simple_base_dyn_inst.cc
new file mode 100644
index 000000000..fdaeaf57e
--- /dev/null
+++ b/src/cpu/ozone/simple_base_dyn_inst.cc
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ */
+
+#include "cpu/base_dyn_inst_impl.hh"
+#include "cpu/ozone/simple_impl.hh"
+
+// Explicit instantiation
+template class BaseDynInst<SimpleImpl>;
+
+template <>
+int
+BaseDynInst<SimpleImpl>::instcount = 0;
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-16 02:55:27 +0000