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@@ -10,3 +10,4 @@ cscope.out m5out src/doxygen ext/dramsim2/DRAMSim2 +ext/mcpat/regression/*/*.out diff --git a/ext/mcpat/regression/README b/ext/mcpat/regression/README new file mode 100644 index 000000000..5a6772fc5 --- /dev/null +++ b/ext/mcpat/regression/README @@ -0,0 +1,75 @@ +regression.py + +Copyright (c) 2010-2014 Advanced Micro Devices, Inc. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer; +redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution; +neither the name of the copyright holders nor the names of its +contributors may be used to endorse or promote products derived from +this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +Authors: Yasuko Eckert <yasuko.eckert@amd.com> + Joel Hestness <hestness@cs.wisc.edu> (while interning at AMD) + + +Introduction +============ + +This regression tester is for the McPAT power model. +This tester can compile and runs McPAT on the input contained in the +specified directory, and then compares the output to that of a golden run in +order to ensure that specific power and area calculations do not change. + +Nine tests are included in the initial version of this tester in the directories: + $GEM5/ext/mcpat/regression/test-* + +In each directory, you will find a regression test input file +(power_region0.xml) and the golden-run output (region0.out.bak). +The tester's output file is saved as region0.out, which is then checked against +region0.out.bak. + + +Options +======= +--help, -h Show a help message and exit +--build, -b Build McPAT before running tests +--cleanup, -c Clean up the specified regression directory +--force, -f Force run regression even if directory isn't set up +--maketest, -m Set up the specified test directory +--verbose, -v Print verbose output + + +How to Use +========== + +The regression tester must be invoked from the McPAT directory. + +% cd $GEM5/ext/mcpat + + +To run all regression tests: +% ./regression/regression.py ./regression/ + + +To run a particular regression test, specify its directory to the tester: +% ./regression/regression.py ./regression/test-0 + +Specify the "-v" option to see a diff of the regression output. diff --git a/ext/mcpat/regression/regression.py b/ext/mcpat/regression/regression.py new file mode 100755 index 000000000..aabfec75d --- /dev/null +++ b/ext/mcpat/regression/regression.py @@ -0,0 +1,241 @@ +#!/usr/bin/env python + +# Copyright (c) 2010-2013 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +SYNOPSIS + + ./regression/regression.py ./regression/ + +DESCRIPTION + + Runs regression tester for McPAT. + This tester can compile and runs McPAT on the input contained in the + specified directory, and then compares the output to that of a prior run in + order to ensure that specific power and area calculations do not change. + +AUTHORS + + Joel Hestness <hestness@cs.wisc.edu> (while interning at AMD) + Yasuko Eckert <yasuko.eckert@amd.com> +""" + +import os +import sys +import optparse +import re + +################################ +# Global Variables +################################ + +global mcpat_binary +mcpat_binary = "../../build/mcpat/mcpat" +global optionsparser + +################################ +# Global Functions +################################ + +def run_test(testdir): + test_passed = True + testfiles = os.listdir(testdir) + for testfile in testfiles: + # For each power_region file, run McPAT on it and check the + # output created against the regression + if re.match("power_region.*\.xml$", testfile): + # Get the region index of the test + fileparts = testfile.split(".") + region_index = fileparts[0][12:] + regression_test = os.path.join(testdir, testfile) + regression_output = os.path.join( + testdir, "region%s.out" % region_index) + regression_correct = os.path.join( + testdir, "region%s.out.ref" % region_index) + print "Running test: %s..." % regression_test + # Run McPAT on the input + os.system( + "%s -infile %s -print_level 10 > %s" % + (mcpat_binary, regression_test, regression_output) ) + if os.path.exists(regression_correct): + diff = os.popen( + "diff %s %s" % (regression_output, regression_correct), + "r").read() + if diff != "": + print "WARN: Differences found in %s" % regression_output + if options.verbose: + print diff + test_passed = False + else: + print "WARN: Regression test not set up: %s..." % regression_test + print "WARN: Not able to verify test" + test_passed = False + + if options.cleanup: + if options.verbose: + print "WARN: Cleaning (deleting) regression output file: "\ + "%s" % regression_output + os.system("rm -f %s" % regression_output) + + if test_passed: + print "PASSED: %s\n\n" % testdir + else: + print "FAILED: %s\n\n" % testdir + +def has_power_region_files(testdir): + files = os.listdir(testdir) + for file in files: + if "power_region" in file and ".xml" in file: + return True + +def is_valid_test_directory(testdir): + valid_regression = True + power_region_file_found = False + + files = os.listdir(testdir) + for file in files: + if "power_region" in file and ".xml" in file: + power_region_file_found = True + fileparts = file.split(".") + region_index = fileparts[0][12:] + regression_output = os.path.join( + testdir, "region%s.out.ref" % region_index) + if os.path.exists(regression_output): + if options.verbose: + print "Valid regression test: %s/%s" % (testdir, file) + else: + valid_regression = False + + return valid_regression and power_region_file_found + +################################ +# Execute here +################################ + +optionsparser = optparse.OptionParser( + formatter = optparse.TitledHelpFormatter(), + usage = globals()['__doc__']) +optionsparser.add_option( + "-b", "--build", action = "store_true", default = False, + help = "Build McPAT before running tests") +optionsparser.add_option( + "-c", "--cleanup", action = "store_true", default = False, + help = "Clean up the specified regression directory") +optionsparser.add_option( + "-f", "--force", action = "store_true", default = False, + help = "Force run regression even if directory isn't set up") +optionsparser.add_option( + "-m", "--maketest", action = "store_true", default = False, + help = "Set up the specified test directory") +optionsparser.add_option( + "-v", "--verbose", action = "store_true", default = False, + help = "Print verbose output") +(options, args) = optionsparser.parse_args() + +if not os.path.exists(mcpat_binary) and not options.build: + print "ERROR: McPAT binary does not exist: %s" % mcpat_binary + exit(0) + +if options.build: + print "Building McPAT..." + bin_dir = os.path.dirname(mcpat_binary) + directory = os.path.join(bin_dir, "../../ext/mcpat") + build_output = os.popen( + "cd %s; make clean; make -j 8 dbg 2>&1" % directory).read() + if "error" in build_output.lower(): + print "Error during build: %s" % build_output + exit(0) + +if len(args) < 1: + print "ERROR: Must specify regressions directory" + exit(0) + +# check params +rootdir = args[0]; +if not os.path.exists(rootdir): + print "ERROR: Regressions directory does not exist: %s" % rootdir + exit(0) + +if options.maketest: + # The specified rootdir must exist since we got here + # Check if directory has tests + list = os.listdir(rootdir) + found_test = False + for file in list: + if "power_region" in file and "out" not in file and "ref" not in file: + found_test = True + # Prepare to run the test in order to set it up + fileparts = file.split(".") + region_index = fileparts[0][12:] + regression_test = os.path.join(rootdir, file) + regression_output = os.path.join( + rootdir, "region%s.out.ref" % region_index) + if os.path.exists(regression_output): + print "WARN: Overwriting old regression output: " \ + "%s" % regression_output + # Run the test to set it up + print "Writing new regression output..." + os.system( + "%s -infile %s -print_level 10 > %s" % + (mcpat_binary, regression_test, regression_output)) + + if not found_test: + print "ERROR: Invalid test directory: %s" % rootdir + print "ERROR: Must contain XML file power_region*.xml" + + exit(0) + +found_test = False +if has_power_region_files(rootdir): + found_test = True + if is_valid_test_directory(rootdir) or options.force: + run_test(rootdir) + else: + print "WARN: Regression directory is not set up: %s" % rootdir +else: + folders = os.listdir(rootdir) + folders.sort() + for folder in folders: + testdir = os.path.join(rootdir, folder) + if os.path.isdir(testdir): + if has_power_region_files(testdir): + found_test = True + if is_valid_test_directory(testdir): + run_test(testdir) + else: + if options.force: + print "WARN: Regression directory is not set up: " \ + "%s" % testdir + print "WARN: Running test anyway: %s..." % testdir + run_test(testdir) + else: + print "Regression directory is not set up: %s" % testdir + else: + print "Not a valid test directory: %s" % testdir + +if not found_test: + print "No valid regressions found in %s" % rootdir diff --git a/ext/mcpat/regression/test-0/power_region0.xml b/ext/mcpat/regression/test-0/power_region0.xml new file mode 100644 index 000000000..bd21cc0e3 --- /dev/null +++ b/ext/mcpat/regression/test-0/power_region0.xml @@ -0,0 +1,404 @@ +<?xml version="1.0" ?> +<component id="root" name="root"> + <component id="system" name="system" type="System"> + <param name="core_tech_node" value="40"/> + <param name="target_core_clockrate" value="1700"/> + <param name="temperature" value="380"/> + <param name="interconnect_projection_type" value="1"/> + <param name="device_type" value="0"/> + <param name="longer_channel_device" value="0"/> + <param name="machine_bits" value="64"/> + <param name="virtual_address_width" value="64"/> + <param name="physical_address_width" value="36"/> + <param name="virtual_memory_page_size" value="4096"/> + <param name="wire_is_mat_type" value="2"/> + <param name="wire_os_mat_type" value="2"/> + <param name="delay_wt" value="100"/> + <param name="area_wt" value="0"/> + <param name="dynamic_power_wt" value="100"/> + <param name="leakage_power_wt" value="0"/> + <param name="cycle_time_wt" value="0"/> + <param name="delay_dev" value="10000"/> + <param name="area_dev" value="10000"/> + <param name="dynamic_power_dev" value="10000"/> + <param name="leakage_power_dev" value="10000"/> + <param name="cycle_time_dev" value="10000"/> + <param name="ed" value="2"/> + <param name="burst_len" value="1"/> + <param name="int_prefetch_w" value="1"/> + <param name="page_sz_bits" value="0"/> + <param name="rpters_in_htree" value="1"/> + <param name="ver_htree_wires_over_array" value="0"/> + <param name="nuca" value="0"/> + <param name="nuca_bank_count" value="0"/> + <param name="force_cache_config" value="0"/> + <param name="wt" value="0"/> + <param name="force_wiretype" value="0"/> + <param name="print_detail" value="1"/> + <param name="add_ecc_b_" value="1"/> + <param name="broadcast_addr_din_over_ver_htrees" value="0"/> + <stat name="total_cycles" value="150"/> + <component id="system.core0" name="core0" type="Core"> + <param name="clock_rate" value="1700"/> + <param name="opt_local" value="0"/> + <param name="instruction_length" value="32"/> + <param name="opcode_width" value="8"/> + <param name="x86" value="1"/> + <param name="micro_opcode_width" value="8"/> + <param name="machine_type" value="0"/> + <param name="number_hardware_threads" value="2"/> + <param name="fetch_width" value="1"/> + <param name="number_instruction_fetch_ports" value="1"/> + <param name="decode_width" value="2"/> + <param name="issue_width" value="2"/> + <param name="peak_issue_width" value="2"/> + <param name="commit_width" value="2"/> + <param name="fp_issue_width" value="2"/> + <param name="prediction_width" value="1"/> + <param name="int_pipelines" value="2"/> + <param name="fp_pipelines" value="1"/> + <param name="int_pipeline_depth" value="12"/> + <param name="fp_pipeline_depth" value="13"/> + <param name="ALU_per_core" value="2"/> + <param name="MUL_per_core" value="1"/> + <param name="FPU_per_core" value="1"/> + <param name="instruction_buffer_size" value="16"/> + <param name="instruction_window_scheme" value="0"/> + <param name="instruction_window_size" value="7"/> + <param name="fp_instruction_window_size" value="18"/> + <param name="ROB_size" value="56"/> + <param name="archi_Regs_IRF_size" value="30"/> + <param name="archi_Regs_FRF_size" value="48"/> + <param name="phy_Regs_IRF_size" value="34"/> + <param name="phy_Regs_FRF_size" value="40"/> + <param name="rename_scheme" value="0"/> + <param name="register_window_size" value="0"/> + <param name="register_window_throughput" value="4"/> + <param name="register_window_latency" value="4"/> + <param name="store_buffer_size" value="32"/> + <param name="load_buffer_size" value="22"/> + <param name="memory_ports" value="1"/> + <param name="RAS_size" value="16"/> + <param name="execu_wire_mat_type" value="2"/> + <param name="execu_bypass_base_width" value="1"/> + <param name="execu_bypass_base_height" value="1"/> + <param name="execu_bypass_start_wiring_level"value="3"/> + <param name="execu_bypass_route_over_perc" value="1"/> + <param name="globalCheckpoint" value="32"/> + <param name="perThreadState" value="8"/> + <param name="ROB_assoc" value="1"/> + <param name="ROB_nbanks" value="1"/> + <param name="ROB_tag_width" value="0"/> + <param name="scheduler_assoc" value="0"/> + <param name="scheduler_nbanks" value="1"/> + <param name="register_window_assoc" value="1"/> + <param name="register_window_nbanks" value="1"/> + <param name="register_window_tag_width" value="0"/> + <param name="register_window_rw_ports" value="1"/> + <param name="phy_Regs_IRF_assoc" value="1"/> + <param name="phy_Regs_IRF_nbanks" value="1"/> + <param name="phy_Regs_IRF_tag_width" value="0"/> + <param name="phy_Regs_IRF_rd_ports" value="1"/> + <param name="phy_Regs_IRF_wr_ports" value="1"/> + <param name="phy_Regs_FRF_assoc" value="1"/> + <param name="phy_Regs_FRF_nbanks" value="1"/> + <param name="phy_Regs_FRF_tag_width" value="0"/> + <param name="phy_Regs_FRF_rd_ports" value="1"/> + <param name="phy_Regs_FRF_wr_ports" value="1"/> + <param name="front_rat_nbanks" value="1"/> + <param name="front_rat_rw_ports" value="1"/> + <param name="retire_rat_nbanks" value="1"/> + <param name="retire_rat_rw_ports" value="0"/> + <param name="freelist_nbanks" value="1"/> + <param name="freelist_rw_ports" value="1"/> + <param name="load_buffer_assoc" value="0"/> + <param name="load_buffer_nbanks" value="1"/> + <param name="store_buffer_assoc" value="0"/> + <param name="store_buffer_nbanks" value="1"/> + <param name="instruction_buffer_assoc" value="1"/> + <param name="instruction_buffer_nbanks" value="1"/> + <param name="instruction_buffer_tag_width" value="0"/> + <stat name="total_instructions" value="100"/> + <stat name="int_instructions" value="80"/> + <stat name="fp_instructions" value="20"/> + <stat name="branch_instructions" value="25"/> + <stat name="branch_mispredictions" value="2"/> + <stat name="load_instructions" value="50"/> + <stat name="store_instructions" value="15"/> + <stat name="committed_instructions" value="100"/> + <stat name="committed_int_instructions" value="80"/> + <stat name="committed_fp_instructions" value="20"/> + <stat name="pipeline_duty_cycle" value="1"/> + <stat name="total_cycles" value="150"/> + <stat name="ROB_reads" value="100"/> + <stat name="ROB_writes" value="100"/> + <stat name="rename_reads" value="100"/> + <stat name="rename_writes" value="100"/> + <stat name="fp_rename_reads" value="100"/> + <stat name="fp_rename_writes" value="100"/> + <stat name="inst_window_reads" value="80"/> + <stat name="inst_window_writes" value="80"/> + <stat name="inst_window_wakeup_accesses" value="80"/> + <stat name="fp_inst_window_reads" value="20"/> + <stat name="fp_inst_window_writes" value="20"/> + <stat name="fp_inst_window_wakeup_accesses" value="20"/> + <stat name="int_regfile_reads" value="160"/> + <stat name="float_regfile_reads" value="40"/> + <stat name="int_regfile_writes" value="80"/> + <stat name="float_regfile_writes" value="20"/> + <stat name="function_calls" value="0"/> + <stat name="context_switches" value="0"/> + <stat name="ialu_accesses" value="70"/> + <stat name="fpu_accesses" value="20"/> + <stat name="mul_accesses" value="10"/> + <stat name="cdb_alu_accesses" value="70"/> + <stat name="cdb_mul_accesses" value="10"/> + <stat name="cdb_fpu_accesses" value="20"/> + <stat name="IFU_duty_cycle" value="1"/> + <stat name="LSU_duty_cycle" value="1"/> + <stat name="MemManU_I_duty_cycle" value="1"/> + <stat name="MemManU_D_duty_cycle" value="1"/> + <stat name="ALU_duty_cycle" value="1"/> + <stat name="MUL_duty_cycle" value="1"/> + <stat name="FPU_duty_cycle" value="1"/> + <stat name="ALU_cdb_duty_cycle" value="1"/> + <stat name="MUL_cdb_duty_cycle" value="1"/> + <stat name="FPU_cdb_duty_cycle" value="1"/> + <component id="system.core0.predictor" name="PBT" type="BranchPredictor"> + <param name="assoc" value="1"/> + <param name="nbanks" value="1"/> + <param name="local_l1_predictor_size" value="12"/> + <param name="local_l2_predictor_size" value="4"/> + <param name="local_predictor_entries" value="8192"/> + <param name="global_predictor_entries" value="8192"/> + <param name="global_predictor_bits" value="4"/> + <param name="chooser_predictor_entries" value="8192"/> + <param name="chooser_predictor_bits" value="4"/> + </component> + <component id="system.core0.itlb" name="itlb" type="InstructionTLB"> + <param name="number_entries" value="512"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="total_accesses" value="50"/> + <stat name="total_misses" value="0"/> + <stat name="conflicts" value="0"/> + </component> + <component id="system.core0.icache" name="Instruction Cache" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="device_type" value="0"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="read_accesses" value="50"/> + <stat name="read_misses" value="12"/> + <stat name="conflicts" value="1"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.core0.dtlb" name="dtlb" type="DataTLB"> + <param name="number_entries" value="512"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="read_accesses" value="65"/> + <stat name="read_misses" value="0"/> + <stat name="conflicts" value="0"/> + </component> + <component id="system.core0.dcache" name="Data Cache" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="8"/> + <param name="num_banks" value="1"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="miss_buffer_size" value="8"/> + <param name="fetch_buffer_size" value="8"/> + <param name="prefetch_buffer_size" value="8"/> + <param name="writeback_buffer_size" value="8"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="device_type" value="0"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="read_accesses" value="50"/> + <stat name="write_accesses" value="15"/> + <stat name="read_misses" value="12"/> + <stat name="write_misses" value="3"/> + <stat name="conflicts" value="1"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.core0.btargetbuf" name="btargetbuf" type="BranchTargetBuffer"> + <param name="size" value="8192"/> + <param name="block_size" value="4"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="1"/> + <param name="throughput" value="3"/> + <param name="rw_ports" value="1"/> + <stat name="read_accesses" value="25"/> + <stat name="write_accesses" value="25"/> + </component> + </component> + <component id="system.L20" name="L2 Cache" type="CacheUnit"> + <param name="level" value="2"/> + <param name="size" value="524288"/> + <param name="block_size" value="64"/> + <param name="assoc" value="16"/> + <param name="num_banks" value="1"/> + <param name="latency" value="8"/> + <param name="throughput" value="23"/> + <param name="miss_buffer_size" value="16"/> + <param name="fetch_buffer_size" value="16"/> + <param name="prefetch_buffer_size" value="16"/> + <param name="writeback_buffer_size" value="16"/> + <param name="clockrate" value="1700"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="device_type" value="0"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="1"/> + <param name="miss_buff_access_mode" value="0"/> + <param name="fetch_buff_access_mode" value="0"/> + <param name="prefetch_buff_access_mode" value="0"/> + <param name="writeback_buff_access_mode"value="0"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="read_accesses" value="15"/> + <stat name="write_accesses" value="5"/> + <stat name="read_misses" value="3"/> + <stat name="write_misses" value="1"/> + <stat name="conflicts" value="1"/> + <stat name="duty_cycle" value="1.0"/> + </component> + </component> +</component> diff --git a/ext/mcpat/regression/test-0/region0.out.ref b/ext/mcpat/regression/test-0/region0.out.ref new file mode 100644 index 000000000..3de30578f --- /dev/null +++ b/ext/mcpat/regression/test-0/region0.out.ref @@ -0,0 +1,595 @@ +McPAT (version 0.8 of Aug, 2010) is computing the target processor... + + +McPAT (version 0.8 of Aug, 2010) results (current print level is 5) +***************************************************************************************** + Technology 40 nm + Interconnect metal projection = conservative interconnect technology projection + Target Clock Rate (MHz) 1700 + +***************************************************************************************** + System: + Area = 15.1334 mm^2 + Peak Dynamic Power = 2.57757 W + Subthreshold Leakage Power = 5.86045 W + Gate Leakage Power = 0.233087 W + Runtime Dynamic Power = 1.55367 W + Runtime Dynamic Energy = 1.37089e-07 J + Total Runtime Energy = 6.74754e-07 J + + Core 0: + Area = 10.8081 mm^2 + Peak Dynamic Power = 2.45616 W + Subthreshold Leakage Power = 4.64481 W + Gate Leakage Power = 0.193831 W + Runtime Dynamic Power = 1.42385 W + Runtime Dynamic Energy = 1.25634e-07 J + Total Runtime Energy = 5.52573e-07 J + + Instruction Fetch Unit: + Area = 2.10081 mm^2 + Peak Dynamic Power = 0.33569 W + Subthreshold Leakage Power = 0.347428 W + Gate Leakage Power = 0.00868165 W + Runtime Dynamic Power = 0.220683 W + Runtime Dynamic Energy = 1.94721e-08 J + Total Runtime Energy = 5.08935e-08 J + + Instruction Cache: + Area = 0.970326 mm^2 + Peak Dynamic Power = 0.0549304 W + Subthreshold Leakage Power = 0.0678485 W + Gate Leakage Power = 0.00157419 W + Runtime Dynamic Power = 0.0505595 W + Runtime Dynamic Energy = 4.46113e-09 J + Total Runtime Energy = 1.05867e-08 J + + Data and Tag Arrays: + Area = 0.25887 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0622886 W + Gate Leakage Power = 0.00129234 W + Runtime Dynamic Power = 0.0464002 W + Runtime Dynamic Energy = 4.09413e-09 J + Total Runtime Energy = 9.70422e-09 J + + Miss Buffer: + Area = 0.262959 mm^2 + Peak Dynamic Power = 0.0192867 W + Subthreshold Leakage Power = 0.00194663 W + Gate Leakage Power = 9.86469e-05 W + Runtime Dynamic Power = 0.00146456 W + Runtime Dynamic Energy = 1.29226e-10 J + Total Runtime Energy = 3.09692e-10 J + + Fill Buffer: + Area = 0.224249 mm^2 + Peak Dynamic Power = 0.0178218 W + Subthreshold Leakage Power = 0.00180662 W + Gate Leakage Power = 9.16038e-05 W + Runtime Dynamic Power = 0.00134737 W + Runtime Dynamic Energy = 1.18886e-10 J + Total Runtime Energy = 2.86376e-10 J + + Prefetch Buffer: + Area = 0.224249 mm^2 + Peak Dynamic Power = 0.0178218 W + Subthreshold Leakage Power = 0.00180662 W + Gate Leakage Power = 9.16038e-05 W + Runtime Dynamic Power = 0.00134737 W + Runtime Dynamic Energy = 1.18886e-10 J + Total Runtime Energy = 2.86376e-10 J + + Branch Target Buffer: + Area = 0.526552 mm^2 + Peak Dynamic Power = 0.0433889 W + Subthreshold Leakage Power = 0.0869885 W + Gate Leakage Power = 0.00266245 W + Runtime Dynamic Power = 0.0237346 W + Runtime Dynamic Energy = 2.09423e-09 J + Total Runtime Energy = 1.00046e-08 J + + Branch Predictor: + Area = 0.594319 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.186556 W + Gate Leakage Power = 0.00424723 W + Runtime Dynamic Power = 0.0672658 W + Runtime Dynamic Energy = 5.93522e-09 J + Total Runtime Energy = 2.27708e-08 J + + Global Predictor: + Area = 0.129022 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0419609 W + Gate Leakage Power = 0.000962899 W + Runtime Dynamic Power = 0.0176358 W + Runtime Dynamic Energy = 1.5561e-09 J + Total Runtime Energy = 5.3435e-09 J + + Local Predictor, Level 1: + Area = 0.191924 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0589594 W + Gate Leakage Power = 0.00130932 W + Runtime Dynamic Power = 0.0261258 W + Runtime Dynamic Energy = 2.30522e-09 J + Total Runtime Energy = 7.62304e-09 J + + Local Predictor, Level 2: + Area = 0.129022 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0419609 W + Gate Leakage Power = 0.000962899 W + Runtime Dynamic Power = 0.00586825 W + Runtime Dynamic Energy = 5.17787e-10 J + Total Runtime Energy = 4.30518e-09 J + + Predictor Chooser: + Area = 0.129022 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0419609 W + Gate Leakage Power = 0.000962899 W + Runtime Dynamic Power = 0.0176358 W + Runtime Dynamic Energy = 1.5561e-09 J + Total Runtime Energy = 5.3435e-09 J + + RAS: + Area = 0.0153301 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0017144 W + Gate Leakage Power = 4.92127e-05 W + Runtime Dynamic Power = 0 W + Runtime Dynamic Energy = 0 J + Total Runtime Energy = 1.55613e-10 J + + Instruction Buffer: + Area = 0.0034347 mm^2 + Peak Dynamic Power = 0.011729 W + Subthreshold Leakage Power = 0.000650517 W + Gate Leakage Power = 1.85414e-05 W + Runtime Dynamic Power = 0.00390968 W + Runtime Dynamic Energy = 3.44972e-10 J + Total Runtime Energy = 4.04006e-10 J + + Instruction Opcode Decoder: + Area = 0.00289896 mm^2 + Peak Dynamic Power = 0.0752588 W + Subthreshold Leakage Power = 0.00253168 W + Gate Leakage Power = 8.37387e-05 W + Runtime Dynamic Power = 0.0250863 W + Runtime Dynamic Energy = 2.2135e-09 J + Total Runtime Energy = 2.44427e-09 J + + Instruction Operand Decoder: + Area = 0.000377341 mm^2 + Peak Dynamic Power = 0.0751236 W + Subthreshold Leakage Power = 0.00032028 W + Gate Leakage Power = 1.17596e-05 W + Runtime Dynamic Power = 0.0250412 W + Runtime Dynamic Energy = 2.20952e-09 J + Total Runtime Energy = 2.23881e-09 J + + Instruction Microcode Decoder: + Area = 0.00289896 mm^2 + Peak Dynamic Power = 0.0752588 W + Subthreshold Leakage Power = 0.00253168 W + Gate Leakage Power = 8.37387e-05 W + Runtime Dynamic Power = 0.0250863 W + Runtime Dynamic Energy = 2.2135e-09 J + Total Runtime Energy = 2.44427e-09 J + + Load/Store Unit: + Area = 1.69899 mm^2 + Peak Dynamic Power = 0.16674 W + Subthreshold Leakage Power = 0.0926715 W + Gate Leakage Power = 0.00259372 W + Runtime Dynamic Power = 0.142557 W + Runtime Dynamic Energy = 1.25786e-08 J + Total Runtime Energy = 2.09843e-08 J + + Data Cache: + Area = 1.58391 mm^2 + Peak Dynamic Power = 0.0928926 W + Subthreshold Leakage Power = 0.0789233 W + Gate Leakage Power = 0.00207502 W + Runtime Dynamic Power = 0.0922726 W + Runtime Dynamic Energy = 8.1417e-09 J + Total Runtime Energy = 1.52886e-08 J + + Data and Tag Arrays: + Area = 0.619642 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0607406 W + Gate Leakage Power = 0.00122316 W + Runtime Dynamic Power = 0.0861866 W + Runtime Dynamic Energy = 7.6047e-09 J + Total Runtime Energy = 1.30721e-08 J + + Miss Buffer: + Area = 0.270528 mm^2 + Peak Dynamic Power = 0.0245073 W + Subthreshold Leakage Power = 0.0048041 W + Gate Leakage Power = 0.000224896 W + Runtime Dynamic Power = 0.00214283 W + Runtime Dynamic Energy = 1.89073e-10 J + Total Runtime Energy = 6.32808e-10 J + + Fill Buffer: + Area = 0.231248 mm^2 + Peak Dynamic Power = 0.0227951 W + Subthreshold Leakage Power = 0.00445956 W + Gate Leakage Power = 0.000208987 W + Runtime Dynamic Power = 0.00197161 W + Runtime Dynamic Energy = 1.73965e-10 J + Total Runtime Energy = 5.85896e-10 J + + Prefetch Buffer: + Area = 0.231248 mm^2 + Peak Dynamic Power = 0.0227951 W + Subthreshold Leakage Power = 0.00445956 W + Gate Leakage Power = 0.000208987 W + Runtime Dynamic Power = 0.00157729 W + Runtime Dynamic Energy = 1.39172e-10 J + Total Runtime Energy = 5.51103e-10 J + + Writeback Buffer: + Area = 0.231248 mm^2 + Peak Dynamic Power = 0.0227951 W + Subthreshold Leakage Power = 0.00445956 W + Gate Leakage Power = 0.000208987 W + Runtime Dynamic Power = 0.000394322 W + Runtime Dynamic Energy = 3.47931e-11 J + Total Runtime Energy = 4.46724e-10 J + + Load Queue: + Area = 0.054217 mm^2 + Peak Dynamic Power = 0.0316525 W + Subthreshold Leakage Power = 0.00559768 W + Gate Leakage Power = 0.00022125 W + Runtime Dynamic Power = 0.0137161 W + Runtime Dynamic Energy = 1.21024e-09 J + Total Runtime Energy = 1.72368e-09 J + + Store Queue: + Area = 0.0608565 mm^2 + Peak Dynamic Power = 0.0421944 W + Subthreshold Leakage Power = 0.00815046 W + Gate Leakage Power = 0.000297452 W + Runtime Dynamic Power = 0.0365685 W + Runtime Dynamic Energy = 3.22663e-09 J + Total Runtime Energy = 3.97204e-09 J + + Memory Management Unit: + Area = 0.331371 mm^2 + Peak Dynamic Power = 0.318513 W + Subthreshold Leakage Power = 0.097099 W + Gate Leakage Power = 0.00441089 W + Runtime Dynamic Power = 0.122906 W + Runtime Dynamic Energy = 1.08447e-08 J + Total Runtime Energy = 1.98014e-08 J + + Instruction TLB: + Area = 0.131789 mm^2 + Peak Dynamic Power = 0.151159 W + Subthreshold Leakage Power = 0.0446376 W + Gate Leakage Power = 0.00203139 W + Runtime Dynamic Power = 0.0503864 W + Runtime Dynamic Energy = 4.44586e-09 J + Total Runtime Energy = 8.5637e-09 J + + Data TLB: + Area = 0.199582 mm^2 + Peak Dynamic Power = 0.167354 W + Subthreshold Leakage Power = 0.0524614 W + Gate Leakage Power = 0.00237949 W + Runtime Dynamic Power = 0.0725199 W + Runtime Dynamic Energy = 6.39881e-09 J + Total Runtime Energy = 1.12377e-08 J + + Execution Unit: + Area = 2.36584 mm^2 + Peak Dynamic Power = 1.52633 W + Subthreshold Leakage Power = 1.18035 W + Gate Leakage Power = 0.0498689 W + Runtime Dynamic Power = 0.59647 W + Runtime Dynamic Energy = 5.26297e-08 J + Total Runtime Energy = 1.61179e-07 J + + Int Bypass Data: + Area = 0.0024813 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.0288621 W + Runtime Dynamic Energy = 2.54666e-09 J + Total Runtime Energy = 2.54666e-09 J + + Int Bypass Tag: + Area = 0.000291384 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00338934 W + Runtime Dynamic Energy = 2.99059e-10 J + Total Runtime Energy = 2.99059e-10 J + + Mul Bypass Data: + Area = 0.00328459 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00545798 W + Runtime Dynamic Energy = 4.81587e-10 J + Total Runtime Energy = 4.81587e-10 J + + Mul Bypass Tag: + Area = 0.000366693 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.000609331 W + Runtime Dynamic Energy = 5.37645e-11 J + Total Runtime Energy = 5.37645e-11 J + + FP Bypass Data: + Area = 0.0039374 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.0130855 W + Runtime Dynamic Energy = 1.15461e-09 J + Total Runtime Energy = 1.15461e-09 J + + FP Bypass Tag: + Area = 0.000508858 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00169113 W + Runtime Dynamic Energy = 1.49218e-10 J + Total Runtime Energy = 1.49218e-10 J + + Register File Unit: + Area = 0.0603417 mm^2 + Peak Dynamic Power = 0.094149 W + Subthreshold Leakage Power = 0.00361325 W + Gate Leakage Power = 0.000100838 W + Runtime Dynamic Power = 0.0069439 W + Runtime Dynamic Energy = 6.12697e-10 J + Total Runtime Energy = 9.40411e-10 J + + Integer Register File: + Area = 0.0397387 mm^2 + Peak Dynamic Power = 0.0858804 W + Subthreshold Leakage Power = 0.00167327 W + Gate Leakage Power = 4.73072e-05 W + Runtime Dynamic Power = 0.00545273 W + Runtime Dynamic Energy = 4.81123e-10 J + Total Runtime Energy = 6.32938e-10 J + + FP Register File: + Area = 0.020603 mm^2 + Peak Dynamic Power = 0.00826856 W + Subthreshold Leakage Power = 0.00193998 W + Gate Leakage Power = 5.35312e-05 W + Runtime Dynamic Power = 0.00149118 W + Runtime Dynamic Energy = 1.31574e-10 J + Total Runtime Energy = 3.07472e-10 J + + Instruction Scheduler: + Area = 0.107117 mm^2 + Peak Dynamic Power = 0.107009 W + Subthreshold Leakage Power = 0.00250283 W + Gate Leakage Power = 7.07223e-05 W + Runtime Dynamic Power = 0.0156016 W + Runtime Dynamic Energy = 1.37661e-09 J + Total Runtime Energy = 1.60369e-09 J + + Integer Instruction Window: + Area = 0.0261741 mm^2 + Peak Dynamic Power = 0.0268581 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00358108 W + Runtime Dynamic Energy = 3.15977e-10 J + Total Runtime Energy = 3.15977e-10 J + + FP Instruction Window: + Area = 0.0232716 mm^2 + Peak Dynamic Power = 0.0133785 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.000891899 W + Runtime Dynamic Energy = 7.8697e-11 J + Total Runtime Energy = 7.8697e-11 J + + Reorder Buffer: + Area = 0.0576711 mm^2 + Peak Dynamic Power = 0.066772 W + Subthreshold Leakage Power = 0.00250283 W + Gate Leakage Power = 7.07223e-05 W + Runtime Dynamic Power = 0.0111287 W + Runtime Dynamic Energy = 9.81941e-10 J + Total Runtime Energy = 1.20902e-09 J + + Integer ALU(s): + Area = 0.138846 mm^2 + Peak Dynamic Power = 0.332578 W + Subthreshold Leakage Power = 0.201977 W + Gate Leakage Power = 0.00854828 W + Runtime Dynamic Power = 0.127022 W + Runtime Dynamic Energy = 1.12078e-08 J + Total Runtime Energy = 2.97836e-08 J + + Floating Point Unit(s): + Area = 1.8404 mm^2 + Peak Dynamic Power = 0.595559 W + Subthreshold Leakage Power = 0.669296 W + Gate Leakage Power = 0.0283266 W + Runtime Dynamic Power = 0.247009 W + Runtime Dynamic Energy = 2.17949e-08 J + Total Runtime Energy = 8.33498e-08 J + + Multiply/Divide Unit(s): + Area = 0.20827 mm^2 + Peak Dynamic Power = 0.39704 W + Subthreshold Leakage Power = 0.302965 W + Gate Leakage Power = 0.0128224 W + Runtime Dynamic Power = 0.146798 W + Runtime Dynamic Energy = 1.29528e-08 J + Total Runtime Energy = 4.08164e-08 J + + Undifferentiated Core: + Area = 3.88668 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 2.82694 W + Gate Leakage Power = 0.119645 W + Runtime Dynamic Power = 0 W + Runtime Dynamic Energy = 0 J + Total Runtime Energy = 2.59992e-07 J + + Rename Unit: + Area = 0.333151 mm^2 + Peak Dynamic Power = 0.10888 W + Subthreshold Leakage Power = 0.0255114 W + Gate Leakage Power = 0.000663381 W + Runtime Dynamic Power = 0.0713414 W + Runtime Dynamic Energy = 6.29483e-09 J + Total Runtime Energy = 8.60438e-09 J + + Int Front RAT: + Area = 0.129348 mm^2 + Peak Dynamic Power = 0.0382386 W + Subthreshold Leakage Power = 0.00828989 W + Gate Leakage Power = 0.000204367 W + Runtime Dynamic Power = 0.00761404 W + Runtime Dynamic Energy = 6.71827e-10 J + Total Runtime Energy = 1.42132e-09 J + + FP Front RAT: + Area = 0.166163 mm^2 + Peak Dynamic Power = 0.0432953 W + Subthreshold Leakage Power = 0.0126995 W + Gate Leakage Power = 0.000319816 W + Runtime Dynamic Power = 0.00862853 W + Runtime Dynamic Energy = 7.61341e-10 J + Total Runtime Energy = 1.9101e-09 J + + Integer Free List: + Area = 0.0120305 mm^2 + Peak Dynamic Power = 0.00394808 W + Subthreshold Leakage Power = 0.000639181 W + Gate Leakage Power = 2.0232e-05 W + Runtime Dynamic Power = 0.00203467 W + Runtime Dynamic Energy = 1.79529e-10 J + Total Runtime Energy = 2.37713e-10 J + + Int Retire RAT: + Area = 0.00606308 mm^2 + Peak Dynamic Power = 0.00325948 W + Subthreshold Leakage Power = 0.000496413 W + Gate Leakage Power = 1.45535e-05 W + Runtime Dynamic Power = 0.00108649 W + Runtime Dynamic Energy = 9.58669e-11 J + Total Runtime Energy = 1.40952e-10 J + + FP Retire RAT: + Area = 0.00751656 mm^2 + Peak Dynamic Power = 0.00404193 W + Subthreshold Leakage Power = 0.000709488 W + Gate Leakage Power = 1.94961e-05 W + Runtime Dynamic Power = 0.00134731 W + Runtime Dynamic Energy = 1.1888e-10 J + Total Runtime Energy = 1.83202e-10 J + + FP Free List: + Area = 0.0120305 mm^2 + Peak Dynamic Power = 0.00394808 W + Subthreshold Leakage Power = 0.000639181 W + Gate Leakage Power = 2.0232e-05 W + Runtime Dynamic Power = 0.00203467 W + Runtime Dynamic Energy = 1.79529e-10 J + Total Runtime Energy = 2.37713e-10 J + + Instruction Dependency Check?: + Area = 0 mm^2 + Peak Dynamic Power = 0.00607447 W + Subthreshold Leakage Power = 0.00101891 W + Gate Leakage Power = 3.23427e-05 W + Runtime Dynamic Power = 0.0242979 W + Runtime Dynamic Energy = 2.14393e-09 J + Total Runtime Energy = 2.23669e-09 J + + FP Dependency Check?: + Area = 0 mm^2 + Peak Dynamic Power = 0.00607447 W + Subthreshold Leakage Power = 0.00101891 W + Gate Leakage Power = 3.23427e-05 W + Runtime Dynamic Power = 0.0242979 W + Runtime Dynamic Energy = 2.14393e-09 J + Total Runtime Energy = 2.23669e-09 J + + Pipeline?: + Area = 0.0912321 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0748063 W + Gate Leakage Power = 0.00796757 W + Runtime Dynamic Power = 0.269895 W + Runtime Dynamic Energy = 2.38143e-08 J + Total Runtime Energy = 3.11178e-08 J + + L2 Cache: + Area = 4.32531 mm^2 + Peak Dynamic Power = 0.121415 W + Subthreshold Leakage Power = 1.21565 W + Gate Leakage Power = 0.0392567 W + Runtime Dynamic Power = 0.129821 W + Runtime Dynamic Energy = 1.14548e-08 J + Total Runtime Energy = 1.22181e-07 J + + Data and Tag Arrays: + Area = 3.33708 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 1.1905 W + Gate Leakage Power = 0.0381925 W + Runtime Dynamic Power = 0.127717 W + Runtime Dynamic Energy = 1.12691e-08 J + Total Runtime Energy = 1.19683e-07 J + + Miss Buffer: + Area = 0.281957 mm^2 + Peak Dynamic Power = 0.0322848 W + Subthreshold Leakage Power = 0.00670028 W + Gate Leakage Power = 0.000283174 W + Runtime Dynamic Power = 0.000747355 W + Runtime Dynamic Energy = 6.59431e-11 J + Total Runtime Energy = 6.8213e-10 J + + Fill Buffer: + Area = 0.235423 mm^2 + Peak Dynamic Power = 0.02971 W + Subthreshold Leakage Power = 0.00614777 W + Gate Leakage Power = 0.000260358 W + Runtime Dynamic Power = 0.000678694 W + Runtime Dynamic Energy = 5.98847e-11 J + Total Runtime Energy = 6.25308e-10 J + + Prefetch Buffer: + Area = 0.235423 mm^2 + Peak Dynamic Power = 0.02971 W + Subthreshold Leakage Power = 0.00614777 W + Gate Leakage Power = 0.000260358 W + Runtime Dynamic Power = 0.00050902 W + Runtime Dynamic Energy = 4.49136e-11 J + Total Runtime Energy = 6.10337e-10 J + + Writeback Buffer: + Area = 0.235423 mm^2 + Peak Dynamic Power = 0.02971 W + Subthreshold Leakage Power = 0.00614777 W + Gate Leakage Power = 0.000260358 W + Runtime Dynamic Power = 0.000169673 W + Runtime Dynamic Energy = 1.49712e-11 J + Total Runtime Energy = 5.80395e-10 J + diff --git a/ext/mcpat/regression/test-1/power_region0.xml b/ext/mcpat/regression/test-1/power_region0.xml new file mode 100644 index 000000000..390c71150 --- /dev/null +++ b/ext/mcpat/regression/test-1/power_region0.xml @@ -0,0 +1,811 @@ +<?xml version="1.0" ?> +<component id="root" name="root"> + <component id="system" name="system" type="System"> + <param name="core_tech_node" value="40"/> + <param name="target_core_clockrate" value="3000"/> + <param name="temperature" value="360"/> + <param name="interconnect_projection_type" value="0"/> + <param name="device_type" value="0"/> + <param name="machine_bits" value="64"/> + <param name="virtual_address_width" value="64"/> + <param name="physical_address_width" value="52"/> + <param name="virtual_memory_page_size" value="4096"/> + <param name="wire_is_mat_type" value="2"/> + <param name="wire_os_mat_type" value="2"/> + <param name="delay_wt" value="100"/> + <param name="area_wt" value="0"/> + <param name="dynamic_power_wt" value="100"/> + <param name="leakage_power_wt" value="0"/> + <param name="cycle_time_wt" value="0"/> + <param name="delay_dev" value="10000"/> + <param name="area_dev" value="10000"/> + <param name="dynamic_power_dev" value="10000"/> + <param name="leakage_power_dev" value="10000"/> + <param name="cycle_time_dev" value="10000"/> + <param name="ed" value="2"/> + <param name="burst_len" value="1"/> + <param name="int_prefetch_w" value="1"/> + <param name="page_sz_bits" value="0"/> + <param name="rpters_in_htree" value="1"/> + <param name="ver_htree_wires_over_array" value="0"/> + <param name="nuca" value="0"/> + <param name="nuca_bank_count" value="0"/> + <param name="force_cache_config" value="0"/> + <param name="wt" value="0"/> + <param name="force_wiretype" value="0"/> + <param name="print_detail" value="1"/> + <param name="add_ecc_b_" value="1"/> + <stat name="total_cycles" value="1856694"/> + <component id="system.core0" name="core0" type="Core"> + <param name="opt_local" value="0"/> + <param name="clock_rate" value="2000"/> + <param name="instruction_length" value="32"/> + <param name="opcode_width" value="6"/> + <param name="machine_type" value="1"/> + <param name="number_hardware_threads" value="1"/> + <param name="fetch_width" value="1"/> + <param name="number_instruction_fetch_ports" value="1"/> + <param name="decode_width" value="1"/> + <param name="issue_width" value="1"/> + <param name="peak_issue_width" value="1"/> + <param name="commit_width" value="1"/> + <param name="fp_issue_width" value="1"/> + <param name="prediction_width" value="1"/> + <param name="int_pipelines" value="1"/> + <param name="fp_pipelines" value="1"/> + <param name="int_pipeline_depth" value="7"/> + <param name="fp_pipeline_depth" value="10"/> + <param name="ALU_per_core" value="1"/> + <param name="FPU_per_core" value="1"/> + <param name="MUL_per_core" value="1"/> + <param name="instruction_buffer_size" value="16"/> + <param name="instruction_window_scheme" value="0"/> + <param name="instruction_window_size" value="0"/> + <param name="fp_instruction_window_size" value="0"/> + <param name="ROB_size" value="0"/> + <param name="archi_Regs_IRF_size" value="32"/> + <param name="archi_Regs_FRF_size" value="32"/> + <param name="phy_Regs_IRF_size" value="32"/> + <param name="phy_Regs_FRF_size" value="32"/> + <param name="rename_scheme" value="0"/> + <param name="register_window_size" value="0"/> + <param name="store_buffer_size" value="8"/> + <param name="load_buffer_size" value="0"/> + <param name="memory_ports" value="1"/> + <param name="RAS_size" value="32"/> + <param name="execu_wire_mat_type" value="2"/> + <param name="execu_bypass_base_width" value="1"/> + <param name="execu_bypass_base_height" value="1"/> + <param name="execu_bypass_start_wiring_level"value="3"/> + <param name="execu_bypass_route_over_perc" value="1"/> + <param name="globalCheckpoint" value="32"/> + <param name="perThreadState" value="8"/> + <param name="ROB_assoc" value="1"/> + <param name="ROB_nbanks" value="1"/> + <param name="ROB_tag_width" value="0"/> + <param name="scheduler_assoc" value="0"/> + <param name="scheduler_nbanks" value="1"/> + <param name="register_window_assoc" value="1"/> + <param name="register_window_nbanks" value="1"/> + <param name="register_window_tag_width" value="0"/> + <param name="register_window_rw_ports" value="1"/> + <param name="phy_Regs_IRF_assoc" value="1"/> + <param name="phy_Regs_IRF_nbanks" value="1"/> + <param name="phy_Regs_IRF_tag_width" value="0"/> + <param name="phy_Regs_IRF_rd_ports" value="1"/> + <param name="phy_Regs_IRF_wr_ports" value="1"/> + <param name="phy_Regs_FRF_assoc" value="1"/> + <param name="phy_Regs_FRF_nbanks" value="1"/> + <param name="phy_Regs_FRF_tag_width" value="0"/> + <param name="phy_Regs_FRF_rd_ports" value="1"/> + <param name="phy_Regs_FRF_wr_ports" value="1"/> + <param name="front_rat_nbanks" value="1"/> + <param name="front_rat_rw_ports" value="1"/> + <param name="retire_rat_nbanks" value="1"/> + <param name="retire_rat_rw_ports" value="0"/> + <param name="freelist_nbanks" value="1"/> + <param name="freelist_rw_ports" value="1"/> + <param name="load_buffer_assoc" value="0"/> + <param name="load_buffer_nbanks" value="1"/> + <param name="store_buffer_assoc" value="0"/> + <param name="store_buffer_nbanks" value="1"/> + <param name="instruction_buffer_assoc" value="1"/> + <param name="instruction_buffer_nbanks" value="1"/> + <param name="instruction_buffer_tag_width" value="0"/> + <stat name="total_instructions" value="332405"/> + <stat name="int_instructions" value="330557"/> + <stat name="fp_instructions" value="1649"/> + <stat name="branch_instructions" value="8263"/> + <stat name="branch_mispredictions" value="53"/> + <stat name="load_instructions" value="45636"/> + <stat name="store_instructions" value="44771"/> + <stat name="committed_instructions" value="332405"/> + <stat name="committed_int_instructions" value="330557"/> + <stat name="committed_fp_instructions" value="1649"/> + <stat name="total_cycles" value="9496951709"/> + <stat name="idle_cycles" value="0"/> + <stat name="busy_cycles" value="9496951709"/> + <stat name="ROB_reads" value="332405"/> + <stat name="ROB_writes" value="332405"/> + <stat name="rename_reads" value="960725"/> + <stat name="rename_writes" value="317221"/> + <stat name="fp_rename_reads" value="2772"/> + <stat name="fp_rename_writes" value="1288"/> + <stat name="inst_window_reads" value="330557"/> + <stat name="inst_window_writes" value="330557"/> + <stat name="inst_window_wakeup_accesses" value="330557"/> + <stat name="fp_inst_window_reads" value="1649"/> + <stat name="fp_inst_window_writes" value="1649"/> + <stat name="fp_inst_window_wakeup_accesses" value="1649"/> + <stat name="int_regfile_reads" value="960725"/> + <stat name="float_regfile_reads" value="2772"/> + <stat name="int_regfile_writes" value="317221"/> + <stat name="float_regfile_writes" value="1288"/> + <stat name="function_calls" value="5"/> + <stat name="context_switches" value="1"/> + <stat name="ialu_accesses" value="330157"/> + <stat name="fpu_accesses" value="1649"/> + <stat name="mul_accesses" value="200"/> + <stat name="cdb_alu_accesses" value="330157"/> + <stat name="cdb_mul_accesses" value="200"/> + <stat name="cdb_fpu_accesses" value="1649"/> + <stat name="IFU_duty_cycle" value="1"/> + <stat name="LSU_duty_cycle" value="1"/> + <stat name="MemManU_I_duty_cycle" value="1"/> + <stat name="MemManU_D_duty_cycle" value="1"/> + <stat name="ALU_duty_cycle" value="1"/> + <stat name="MUL_duty_cycle" value="1"/> + <stat name="FPU_duty_cycle" value="1"/> + <stat name="ALU_cdb_duty_cycle" value="1"/> + <stat name="MUL_cdb_duty_cycle" value="1"/> + <stat name="FPU_cdb_duty_cycle" value="1"/> + <component id="system.core0.bpred" name="bpred" type="BranchPredictor"> + <param name="assoc" value="1"/> + <param name="nbanks" value="1"/> + <param name="local_l1_predictor_size" value="10"/> + <param name="local_l2_predictor_size" value="3"/> + <param name="local_predictor_entries" value="1024"/> + <param name="global_predictor_entries" value="4096"/> + <param name="global_predictor_bits" value="2"/> + <param name="chooser_predictor_entries" value="4096"/> + <param name="chooser_predictor_bits" value="2"/> + </component> + <component id="system.core0.itlb" name="itlb" type="InstructionTLB"> + <param name="number_entries" value="64"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="total_accesses" value="8263"/> + <stat name="total_misses" value="5"/> + <stat name="conflicts" value="1"/> + </component> + <component id="system.core0.dtlb" name="dtlb" type="DataTLB"> + <param name="number_entries" value="64"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="read_accesses" value="108476"/> + <stat name="write_accesses" value="78"/> + <stat name="read_misses" value="7"/> + <stat name="write_misses" value="0"/> + <stat name="conflicts" value="7"/> + </component> + <component id="system.core0.btargetbuf" name="btargetbuf" type="BranchTargetBuffer"> + <param name="size" value="8192"/> + <param name="block_size" value="4"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="1"/> + <param name="throughput" value="3"/> + <param name="rw_ports" value="1"/> + <stat name="read_accesses" value="43"/> + <stat name="write_accesses" value="943"/> + </component> + </component> + <component id="system.core1" name="core1" type="Core"> + <param name="opt_local" value="0"/> + <param name="clock_rate" value="2000"/> + <param name="instruction_length" value="32"/> + <param name="opcode_width" value="6"/> + <param name="machine_type" value="1"/> + <param name="number_hardware_threads" value="1"/> + <param name="fetch_width" value="1"/> + <param name="number_instruction_fetch_ports" value="1"/> + <param name="decode_width" value="1"/> + <param name="issue_width" value="1"/> + <param name="peak_issue_width" value="1"/> + <param name="commit_width" value="1"/> + <param name="fp_issue_width" value="1"/> + <param name="prediction_width" value="1"/> + <param name="int_pipelines" value="1"/> + <param name="fp_pipelines" value="1"/> + <param name="int_pipeline_depth" value="7"/> + <param name="fp_pipeline_depth" value="10"/> + <param name="ALU_per_core" value="1"/> + <param name="FPU_per_core" value="1"/> + <param name="MUL_per_core" value="1"/> + <param name="instruction_buffer_size" value="16"/> + <param name="instruction_window_scheme" value="0"/> + <param name="instruction_window_size" value="0"/> + <param name="fp_instruction_window_size" value="0"/> + <param name="ROB_size" value="0"/> + <param name="archi_Regs_IRF_size" value="32"/> + <param name="archi_Regs_FRF_size" value="32"/> + <param name="phy_Regs_IRF_size" value="32"/> + <param name="phy_Regs_FRF_size" value="32"/> + <param name="rename_scheme" value="0"/> + <param name="register_window_size" value="0"/> + <param name="store_buffer_size" value="8"/> + <param name="load_buffer_size" value="0"/> + <param name="memory_ports" value="1"/> + <param name="RAS_size" value="32"/> + <param name="execu_wire_mat_type" value="2"/> + <param name="execu_bypass_base_width" value="1"/> + <param name="execu_bypass_base_height" value="1"/> + <param name="execu_bypass_start_wiring_level"value="3"/> + <param name="execu_bypass_route_over_perc" value="1"/> + <param name="globalCheckpoint" value="32"/> + <param name="perThreadState" value="8"/> + <param name="ROB_assoc" value="1"/> + <param name="ROB_nbanks" value="1"/> + <param name="ROB_tag_width" value="0"/> + <param name="scheduler_assoc" value="0"/> + <param name="scheduler_nbanks" value="1"/> + <param name="register_window_assoc" value="1"/> + <param name="register_window_nbanks" value="1"/> + <param name="register_window_tag_width" value="0"/> + <param name="register_window_rw_ports" value="1"/> + <param name="phy_Regs_IRF_assoc" value="1"/> + <param name="phy_Regs_IRF_nbanks" value="1"/> + <param name="phy_Regs_IRF_tag_width" value="0"/> + <param name="phy_Regs_IRF_rd_ports" value="1"/> + <param name="phy_Regs_IRF_wr_ports" value="1"/> + <param name="phy_Regs_FRF_assoc" value="1"/> + <param name="phy_Regs_FRF_nbanks" value="1"/> + <param name="phy_Regs_FRF_tag_width" value="0"/> + <param name="phy_Regs_FRF_rd_ports" value="1"/> + <param name="phy_Regs_FRF_wr_ports" value="1"/> + <param name="front_rat_nbanks" value="1"/> + <param name="front_rat_rw_ports" value="1"/> + <param name="retire_rat_nbanks" value="1"/> + <param name="retire_rat_rw_ports" value="0"/> + <param name="freelist_nbanks" value="1"/> + <param name="freelist_rw_ports" value="1"/> + <param name="load_buffer_assoc" value="0"/> + <param name="load_buffer_nbanks" value="1"/> + <param name="store_buffer_assoc" value="0"/> + <param name="store_buffer_nbanks" value="1"/> + <param name="instruction_buffer_assoc" value="1"/> + <param name="instruction_buffer_nbanks" value="1"/> + <param name="instruction_buffer_tag_width" value="0"/> + <stat name="total_instructions" value="4358"/> + <stat name="int_instructions" value="4336"/> + <stat name="fp_instructions" value="22"/> + <stat name="branch_instructions" value="1358"/> + <stat name="branch_mispredictions" value="14"/> + <stat name="load_instructions" value="715"/> + <stat name="store_instructions" value="406"/> + <stat name="committed_instructions" value="4358"/> + <stat name="committed_int_instructions" value="4336"/> + <stat name="committed_fp_instructions" value="22"/> + <stat name="total_cycles" value="9496737874"/> + <stat name="ROB_reads" value="4358"/> + <stat name="ROB_writes" value="4358"/> + <stat name="rename_reads" value="12614"/> + <stat name="rename_writes" value="4404"/> + <stat name="fp_rename_reads" value="22"/> + <stat name="fp_rename_writes" value="22"/> + <stat name="inst_window_reads" value="4336"/> + <stat name="inst_window_writes" value="4336"/> + <stat name="inst_window_wakeup_accesses" value="4336"/> + <stat name="fp_inst_window_reads" value="22"/> + <stat name="fp_inst_window_writes" value="22"/> + <stat name="fp_inst_window_wakeup_accesses" value="22"/> + <stat name="int_regfile_reads" value="12614"/> + <stat name="float_regfile_reads" value="44"/> + <stat name="int_regfile_writes" value="4404"/> + <stat name="float_regfile_writes" value="22"/> + <stat name="function_calls" value="3"/> + <stat name="context_switches" value="1"/> + <stat name="ialu_accesses" value="4236"/> + <stat name="fpu_accesses" value="22"/> + <stat name="mul_accesses" value="100"/> + <stat name="cdb_alu_accesses" value="4236"/> + <stat name="cdb_mul_accesses" value="100"/> + <stat name="cdb_fpu_accesses" value="22"/> + <stat name="IFU_duty_cycle" value="1"/> + <stat name="LSU_duty_cycle" value="1"/> + <stat name="MemManU_I_duty_cycle" value="1"/> + <stat name="MemManU_D_duty_cycle" value="1"/> + <stat name="ALU_duty_cycle" value="1"/> + <stat name="MUL_duty_cycle" value="1"/> + <stat name="FPU_duty_cycle" value="1"/> + <stat name="ALU_cdb_duty_cycle" value="1"/> + <stat name="MUL_cdb_duty_cycle" value="1"/> + <stat name="FPU_cdb_duty_cycle" value="1"/> + <component id="system.core1.bpred" name="bpred" type="BranchPredictor"> + <param name="assoc" value="1"/> + <param name="nbanks" value="1"/> + <param name="local_l1_predictor_size" value="10"/> + <param name="local_l2_predictor_size" value="3"/> + <param name="local_predictor_entries" value="1024"/> + <param name="global_predictor_entries" value="4096"/> + <param name="global_predictor_bits" value="2"/> + <param name="chooser_predictor_entries" value="4096"/> + <param name="chooser_predictor_bits" value="2"/> + </component> + <component id="system.core1.itlb" name="itlb" type="InstructionTLB"> + <param name="number_entries" value="64"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="total_accesses" value="253291"/> + <stat name="total_misses" value="6"/> + <stat name="conflicts" value="5"/> + </component> + <component id="system.core1.dtlb" name="dtlb" type="DataTLB"> + <param name="number_entries" value="64"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="read_accesses" value="91498"/> + <stat name="write_accesses" value="29"/> + <stat name="read_misses" value="3"/> + <stat name="write_misses" value="0"/> + <stat name="conflicts" value="3"/> + </component> + <component id="system.core1.btargetbuf" name="btargetbuf" type="BranchTargetBuffer"> + <param name="size" value="8192"/> + <param name="block_size" value="4"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="1"/> + <param name="throughput" value="3"/> + <param name="rw_ports" value="1"/> + <stat name="read_accesses" value="43"/> + <stat name="write_accesses" value="943"/> + </component> + </component> + <component id="system.mc" name="mc" type="MemoryController"> + <param name="mc_clock" value="800"/> + <param name="tech_type" value="2"/> + <param name="mc_type" value="0"/> + <param name="num_mcs" value="1"/> + <param name="type" value="0"/> + <param name="LVDS" value="1"/> + <param name="withPHY" value="1"/> + <param name="llc_line_length" value="64"/> + <param name="memory_channels_per_mc" value="2"/> + <param name="req_window_size_per_channel" value="128"/> + <param name="IO_buffer_size_per_channel" value="128"/> + <param name="databus_width" value="128"/> + <param name="addressbus_width" value="51"/> + <param name="opcode_width" value="16"/> + <param name="peak_transfer_rate" value="6400"/> + <param name="number_ranks" value="2"/> + <param name="reorder_buffer_assoc" value="0"/> + <param name="reorder_buffer_nbanks" value="1"/> + <param name="read_buffer_assoc" value="1"/> + <param name="read_buffer_nbanks" value="1"/> + <param name="read_buffer_tag_width" value="0"/> + <param name="write_buffer_assoc" value="1"/> + <param name="write_buffer_nbanks" value="1"/> + <param name="write_buffer_tag_width" value="0"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <stat name="memory_reads" value="274"/> + <stat name="memory_writes" value="86"/> + <stat name="duty_cycle" value="0.5"/> + </component> + <component id="system.l1_cntrl0" name="l1_cntrl0" type="CacheController"> + <component id="system.l1_cntrl0.L1DcacheMemory" name="L1DcacheMemory" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="2"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="device_type" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="47291"/> + <stat name="num_data_array_writes" value="51619"/> + <stat name="num_tag_array_reads" value="91498"/> + <stat name="num_tag_array_writes" value="17078"/> + <stat name="read_misses" value="156"/> + <stat name="write_misses" value="92"/> + <stat name="conflicts" value="148"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.l1_cntrl0.L1IcacheMemory" name="L1IcacheMemory" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="2"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="device_type" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="253831"/> + <stat name="num_data_array_writes" value="3497"/> + <stat name="num_tag_array_reads" value="253291"/> + <stat name="num_tag_array_writes" value="10845"/> + <stat name="read_misses" value="456"/> + <stat name="write_misses" value="92"/> + <stat name="conflicts" value="448"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.l1_cntrl0.L2cacheMemory" name="L2cacheMemory" type="CacheUnit"> + <param name="level" value="2"/> + <param name="size" value="2097152"/> + <param name="block_size" value="64"/> + <param name="assoc" value="16"/> + <param name="num_banks" value="1"/> + <param name="latency" value="10"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="device_type" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="1"/> + <param name="miss_buff_access_mode" value="0"/> + <param name="fetch_buff_access_mode" value="0"/> + <param name="prefetch_buff_access_mode" value="0"/> + <param name="writeback_buff_access_mode"value="0"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="274"/> + <stat name="num_data_array_writes" value="8086"/> + <stat name="num_tag_array_reads" value="3959"/> + <stat name="num_tag_array_writes" value="12046"/> + <stat name="read_misses" value="56"/> + <stat name="write_misses" value="32"/> + <stat name="conflicts" value="88"/> + <stat name="duty_cycle" value="1"/> + </component> + </component> + <component id="system.l1_cntrl1" name="l1_cntrl1" type="CacheController"> + <component id="system.l1_cntrl1.L1DcacheMemory" name="L1DcacheMemory" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="2"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="device_type" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="631"/> + <stat name="num_data_array_writes" value="527"/> + <stat name="num_tag_array_reads" value="6356"/> + <stat name="num_tag_array_writes" value="297"/> + <stat name="read_misses" value="36"/> + <stat name="write_misses" value="12"/> + <stat name="conflicts" value="48"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.l1_cntrl1.L1IcacheMemory" name="L1IcacheMemory" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="2"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="device_type" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="2879"/> + <stat name="num_data_array_writes" value="182"/> + <stat name="num_tag_array_reads" value="8263"/> + <stat name="num_tag_array_writes" value="551"/> + <stat name="read_misses" value="156"/> + <stat name="write_misses" value="92"/> + <stat name="conflicts" value="148"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.l1_cntrl1.L2cacheMemory" name="L2cacheMemory" type="CacheUnit"> + <param name="level" value="2"/> + <param name="size" value="2097152"/> + <param name="block_size" value="64"/> + <param name="assoc" value="16"/> + <param name="num_banks" value="1"/> + <param name="latency" value="10"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="device_type" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="1"/> + <param name="miss_buff_access_mode" value="0"/> + <param name="fetch_buff_access_mode" value="0"/> + <param name="prefetch_buff_access_mode" value="0"/> + <param name="writeback_buff_access_mode"value="0"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="3"/> + <stat name="num_data_array_writes" value="10"/> + <stat name="num_tag_array_reads" value="5210"/> + <stat name="num_tag_array_writes" value="13"/> + <stat name="read_misses" value="462"/> + <stat name="write_misses" value="0"/> + <stat name="conflicts" value="462"/> + <stat name="duty_cycle" value="1"/> + </component> + </component> + </component> +</component> diff --git a/ext/mcpat/regression/test-1/region0.out.ref b/ext/mcpat/regression/test-1/region0.out.ref new file mode 100644 index 000000000..790713a63 --- /dev/null +++ b/ext/mcpat/regression/test-1/region0.out.ref @@ -0,0 +1,1018 @@ +McPAT (version 0.8 of Aug, 2010) is computing the target processor... + + +McPAT (version 0.8 of Aug, 2010) results (current print level is 5) +***************************************************************************************** + Technology 40 nm + Interconnect metal projection = aggressive interconnect technology projection + Target Clock Rate (MHz) 3000 + +***************************************************************************************** + System: + Area = 49.2631 mm^2 + Peak Dynamic Power = 4.05637 W + Subthreshold Leakage Power = 7.51021 W + Gate Leakage Power = 0.474458 W + Runtime Dynamic Power = 0.775964 W + Runtime Dynamic Energy = 0.000480243 J + Total Runtime Energy = 0.00542193 J + + Core 0: + Area = 4.03988 mm^2 + Peak Dynamic Power = 1.13952 W + Subthreshold Leakage Power = 1.09948 W + Gate Leakage Power = 0.0880822 W + Runtime Dynamic Power = 0.382447 W + Runtime Dynamic Energy = 0.000236696 J + Total Runtime Energy = 0.000971678 J + + Instruction Fetch Unit: + Area = 0.646243 mm^2 + Peak Dynamic Power = 0.0998237 W + Subthreshold Leakage Power = 0.0641442 W + Gate Leakage Power = 0.00348734 W + Runtime Dynamic Power = 0.020159 W + Runtime Dynamic Energy = 1.24764e-05 J + Total Runtime Energy = 5.43334e-05 J + + Branch Target Buffer: + Area = 0.526882 mm^2 + Peak Dynamic Power = 0.05291 W + Subthreshold Leakage Power = 0.0468647 W + Gate Leakage Power = 0.00268178 W + Runtime Dynamic Power = 9.34726e-05 W + Runtime Dynamic Energy = 5.785e-08 J + Total Runtime Energy = 3.07221e-05 J + + Branch Predictor: + Area = 0.117913 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0166783 W + Gate Leakage Power = 0.000768254 W + Runtime Dynamic Power = 0.00746709 W + Runtime Dynamic Energy = 4.62137e-06 J + Total Runtime Energy = 1.5419e-05 J + + Global Predictor: + Area = 0.0375885 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.00584294 W + Gate Leakage Power = 0.000266459 W + Runtime Dynamic Power = 0.0026894 W + Runtime Dynamic Energy = 1.66447e-06 J + Total Runtime Energy = 5.44556e-06 J + + Local Predictor, Level 1: + Area = 0.0226899 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0029458 W + Gate Leakage Power = 0.000134 W + Runtime Dynamic Power = 0.00204006 W + Runtime Dynamic Energy = 1.26259e-06 J + Total Runtime Energy = 3.16867e-06 J + + Local Predictor, Level 2: + Area = 0.0111174 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.00161822 W + Gate Leakage Power = 7.85114e-05 W + Runtime Dynamic Power = 4.81956e-05 W + Runtime Dynamic Energy = 2.98282e-08 J + Total Runtime Energy = 1.07993e-06 J + + Predictor Chooser: + Area = 0.0375885 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.00584294 W + Gate Leakage Power = 0.000266459 W + Runtime Dynamic Power = 0.0026894 W + Runtime Dynamic Energy = 1.66447e-06 J + Total Runtime Energy = 5.44556e-06 J + + RAS: + Area = 0.00892889 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.000428398 W + Gate Leakage Power = 2.2826e-05 W + Runtime Dynamic Power = 3.36452e-08 W + Runtime Dynamic Energy = 2.08229e-11 J + Total Runtime Energy = 2.79282e-07 J + + Instruction Buffer: + Area = 0.000887187 mm^2 + Peak Dynamic Power = 0.00270456 W + Subthreshold Leakage Power = 8.79429e-05 W + Gate Leakage Power = 5.07123e-06 W + Runtime Dynamic Power = 0.000726299 W + Runtime Dynamic Energy = 4.49505e-07 J + Total Runtime Energy = 5.07071e-07 J + + Instruction Opcode Decoder: + Area = 0.000370909 mm^2 + Peak Dynamic Power = 0.022114 W + Subthreshold Leakage Power = 0.000341264 W + Gate Leakage Power = 2.1391e-05 W + Runtime Dynamic Power = 0.00593861 W + Runtime Dynamic Energy = 3.6754e-06 J + Total Runtime Energy = 3.89984e-06 J + + Instruction Operand Decoder: + Area = 0.00018867 mm^2 + Peak Dynamic Power = 0.0220952 W + Subthreshold Leakage Power = 0.000171916 W + Gate Leakage Power = 1.08411e-05 W + Runtime Dynamic Power = 0.00593357 W + Runtime Dynamic Energy = 3.67227e-06 J + Total Runtime Energy = 3.78538e-06 J + + Instruction Microcode Decoder: + Area = 0 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0 W + Runtime Dynamic Energy = 0 J + Total Runtime Energy = 0 J + + Load/Store Unit: + Area = 0.0429074 mm^2 + Peak Dynamic Power = 0.0147095 W + Subthreshold Leakage Power = 0.000986438 W + Gate Leakage Power = 8.4035e-05 W + Runtime Dynamic Power = 0.00214872 W + Runtime Dynamic Energy = 1.32984e-06 J + Total Runtime Energy = 1.99235e-06 J + + Store Queue: + Area = 0.0429074 mm^2 + Peak Dynamic Power = 0.0147095 W + Subthreshold Leakage Power = 0.000986438 W + Gate Leakage Power = 8.4035e-05 W + Runtime Dynamic Power = 0.00214872 W + Runtime Dynamic Energy = 1.32984e-06 J + Total Runtime Energy = 1.99235e-06 J + + Memory Management Unit: + Area = 0.0536541 mm^2 + Peak Dynamic Power = 0.0450214 W + Subthreshold Leakage Power = 0.00608426 W + Gate Leakage Power = 0.000426918 W + Runtime Dynamic Power = 0.00219981 W + Runtime Dynamic Energy = 1.36146e-06 J + Total Runtime Energy = 5.39121e-06 J + + Instruction TLB: + Area = 0.0183885 mm^2 + Peak Dynamic Power = 0.0215705 W + Subthreshold Leakage Power = 0.00282912 W + Gate Leakage Power = 0.000201432 W + Runtime Dynamic Power = 0.000144027 W + Runtime Dynamic Energy = 8.91382e-08 J + Total Runtime Energy = 1.96474e-06 J + + Data TLB: + Area = 0.0352657 mm^2 + Peak Dynamic Power = 0.0234509 W + Subthreshold Leakage Power = 0.00325513 W + Gate Leakage Power = 0.000225486 W + Runtime Dynamic Power = 0.00205578 W + Runtime Dynamic Energy = 1.27232e-06 J + Total Runtime Energy = 3.42647e-06 J + + Execution Unit: + Area = 2.14837 mm^2 + Peak Dynamic Power = 0.97997 W + Subthreshold Leakage Power = 0.576941 W + Gate Leakage Power = 0.0454688 W + Runtime Dynamic Power = 0.057217 W + Runtime Dynamic Energy = 3.54115e-05 J + Total Runtime Energy = 0.00042062 J + + Int Bypass Data: + Area = 0.0011767 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00909265 W + Runtime Dynamic Energy = 5.62742e-06 J + Total Runtime Energy = 5.62742e-06 J + + Int Bypass Tag: + Area = 0.000147088 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00113658 W + Runtime Dynamic Energy = 7.03428e-07 J + Total Runtime Energy = 7.03428e-07 J + + Mul Bypass Data: + Area = 0.00299957 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 1.40408e-05 W + Runtime Dynamic Energy = 8.68982e-09 J + Total Runtime Energy = 8.68982e-09 J + + Mul Bypass Tag: + Area = 0.000249964 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 1.17007e-06 W + Runtime Dynamic Energy = 7.24152e-10 J + Total Runtime Energy = 7.24152e-10 J + + FP Bypass Data: + Area = 0.0055603 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.000214596 W + Runtime Dynamic Energy = 1.32813e-07 J + Total Runtime Energy = 1.32813e-07 J + + FP Bypass Tag: + Area = 0.000504686 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 1.9478e-05 W + Runtime Dynamic Energy = 1.20549e-08 J + Total Runtime Energy = 1.20549e-08 J + + Register File Unit: + Area = 0.0196435 mm^2 + Peak Dynamic Power = 0.0336789 W + Subthreshold Leakage Power = 0.000856795 W + Gate Leakage Power = 4.5652e-05 W + Runtime Dynamic Power = 0.00398986 W + Runtime Dynamic Energy = 2.46931e-06 J + Total Runtime Energy = 3.02784e-06 J + + Integer Register File: + Area = 0.00982177 mm^2 + Peak Dynamic Power = 0.0249332 W + Subthreshold Leakage Power = 0.000428398 W + Gate Leakage Power = 2.2826e-05 W + Runtime Dynamic Power = 0.00397694 W + Runtime Dynamic Energy = 2.46132e-06 J + Total Runtime Energy = 2.74058e-06 J + + FP Register File: + Area = 0.00982177 mm^2 + Peak Dynamic Power = 0.00874563 W + Subthreshold Leakage Power = 0.000428398 W + Gate Leakage Power = 2.2826e-05 W + Runtime Dynamic Power = 1.29157e-05 W + Runtime Dynamic Energy = 7.99349e-09 J + Total Runtime Energy = 2.87255e-07 J + + Integer ALU(s): + Area = 0.0694232 mm^2 + Peak Dynamic Power = 0.157715 W + Subthreshold Leakage Power = 0.0542072 W + Gate Leakage Power = 0.00427414 W + Runtime Dynamic Power = 0.0420673 W + Runtime Dynamic Energy = 2.60354e-05 J + Total Runtime Energy = 6.22294e-05 J + + Floating Point Unit(s): + Area = 1.8404 mm^2 + Peak Dynamic Power = 0.473146 W + Subthreshold Leakage Power = 0.359256 W + Gate Leakage Power = 0.0283266 W + Runtime Dynamic Power = 0.000630328 W + Runtime Dynamic Energy = 3.90109e-07 J + Total Runtime Energy = 0.000240264 J + + Multiply/Divide Unit(s): + Area = 0.20827 mm^2 + Peak Dynamic Power = 0.31543 W + Subthreshold Leakage Power = 0.162622 W + Gate Leakage Power = 0.0128224 W + Runtime Dynamic Power = 5.09665e-05 W + Runtime Dynamic Energy = 3.1543e-08 J + Total Runtime Energy = 0.000108614 J + + Undifferentiated Core: + Area = 1.09115 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.425999 W + Gate Leakage Power = 0.0335892 W + Runtime Dynamic Power = 0 W + Runtime Dynamic Energy = 0 J + Total Runtime Energy = 0.000284438 J + + Pipeline?: + Area = 0.0575486 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0253286 W + Gate Leakage Power = 0.00502589 W + Runtime Dynamic Power = 0.300722 W + Runtime Dynamic Energy = 0.000186116 J + Total Runtime Energy = 0.000204903 J + + Core 1: + Area = 4.03988 mm^2 + Peak Dynamic Power = 1.13952 W + Subthreshold Leakage Power = 1.09948 W + Gate Leakage Power = 0.0880822 W + Runtime Dynamic Power = 0.308048 W + Runtime Dynamic Energy = 0.00019065 J + Total Runtime Energy = 0.000925632 J + + Instruction Fetch Unit: + Area = 0.646243 mm^2 + Peak Dynamic Power = 0.0998237 W + Subthreshold Leakage Power = 0.0641442 W + Gate Leakage Power = 0.00348734 W + Runtime Dynamic Power = 0.00038199 W + Runtime Dynamic Energy = 2.36413e-07 J + Total Runtime Energy = 4.20934e-05 J + + Branch Target Buffer: + Area = 0.526882 mm^2 + Peak Dynamic Power = 0.05291 W + Subthreshold Leakage Power = 0.0468647 W + Gate Leakage Power = 0.00268178 W + Runtime Dynamic Power = 9.34726e-05 W + Runtime Dynamic Energy = 5.785e-08 J + Total Runtime Energy = 3.07221e-05 J + + Branch Predictor: + Area = 0.117913 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0166783 W + Gate Leakage Power = 0.000768254 W + Runtime Dynamic Power = 0.000123345 W + Runtime Dynamic Energy = 7.63381e-08 J + Total Runtime Energy = 1.0874e-05 J + + Global Predictor: + Area = 0.0375885 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.00584294 W + Gate Leakage Power = 0.000266459 W + Runtime Dynamic Power = 4.13701e-05 W + Runtime Dynamic Energy = 2.56038e-08 J + Total Runtime Energy = 3.8067e-06 J + + Local Predictor, Level 1: + Area = 0.0226899 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0029458 W + Gate Leakage Power = 0.000134 W + Runtime Dynamic Power = 3.26641e-05 W + Runtime Dynamic Energy = 2.02158e-08 J + Total Runtime Energy = 1.9263e-06 J + + Local Predictor, Level 2: + Area = 0.0111174 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.00161822 W + Gate Leakage Power = 7.85114e-05 W + Runtime Dynamic Power = 7.92081e-06 W + Runtime Dynamic Energy = 4.90217e-09 J + Total Runtime Energy = 1.05501e-06 J + + Predictor Chooser: + Area = 0.0375885 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.00584294 W + Gate Leakage Power = 0.000266459 W + Runtime Dynamic Power = 4.13701e-05 W + Runtime Dynamic Energy = 2.56038e-08 J + Total Runtime Energy = 3.8067e-06 J + + RAS: + Area = 0.00892889 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.000428398 W + Gate Leakage Power = 2.2826e-05 W + Runtime Dynamic Power = 2.01871e-08 W + Runtime Dynamic Energy = 1.24938e-11 J + Total Runtime Energy = 2.79274e-07 J + + Instruction Buffer: + Area = 0.000887187 mm^2 + Peak Dynamic Power = 0.00270456 W + Subthreshold Leakage Power = 8.79429e-05 W + Gate Leakage Power = 5.07123e-06 W + Runtime Dynamic Power = 9.52215e-06 W + Runtime Dynamic Energy = 5.89324e-09 J + Total Runtime Energy = 6.34595e-08 J + + Instruction Opcode Decoder: + Area = 0.000370909 mm^2 + Peak Dynamic Power = 0.022114 W + Subthreshold Leakage Power = 0.000341264 W + Gate Leakage Power = 2.1391e-05 W + Runtime Dynamic Power = 7.78582e-05 W + Runtime Dynamic Energy = 4.81863e-08 J + Total Runtime Energy = 2.72633e-07 J + + Instruction Operand Decoder: + Area = 0.00018867 mm^2 + Peak Dynamic Power = 0.0220952 W + Subthreshold Leakage Power = 0.000171916 W + Gate Leakage Power = 1.08411e-05 W + Runtime Dynamic Power = 7.77921e-05 W + Runtime Dynamic Energy = 4.81454e-08 J + Total Runtime Energy = 1.61253e-07 J + + Instruction Microcode Decoder: + Area = 0 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0 W + Runtime Dynamic Energy = 0 J + Total Runtime Energy = 0 J + + Load/Store Unit: + Area = 0.0429074 mm^2 + Peak Dynamic Power = 0.0147095 W + Subthreshold Leakage Power = 0.000986438 W + Gate Leakage Power = 8.4035e-05 W + Runtime Dynamic Power = 2.6643e-05 W + Runtime Dynamic Energy = 1.64893e-08 J + Total Runtime Energy = 6.79003e-07 J + + Store Queue: + Area = 0.0429074 mm^2 + Peak Dynamic Power = 0.0147095 W + Subthreshold Leakage Power = 0.000986438 W + Gate Leakage Power = 8.4035e-05 W + Runtime Dynamic Power = 2.6643e-05 W + Runtime Dynamic Energy = 1.64893e-08 J + Total Runtime Energy = 6.79003e-07 J + + Memory Management Unit: + Area = 0.0536541 mm^2 + Peak Dynamic Power = 0.0450214 W + Subthreshold Leakage Power = 0.00608426 W + Gate Leakage Power = 0.000426918 W + Runtime Dynamic Power = 0.00614775 W + Runtime Dynamic Energy = 3.80483e-06 J + Total Runtime Energy = 7.83458e-06 J + + Instruction TLB: + Area = 0.0183885 mm^2 + Peak Dynamic Power = 0.0215705 W + Subthreshold Leakage Power = 0.00282912 W + Gate Leakage Power = 0.000201432 W + Runtime Dynamic Power = 0.00441402 W + Runtime Dynamic Energy = 2.73183e-06 J + Total Runtime Energy = 4.60743e-06 J + + Data TLB: + Area = 0.0352657 mm^2 + Peak Dynamic Power = 0.0234509 W + Subthreshold Leakage Power = 0.00325513 W + Gate Leakage Power = 0.000225486 W + Runtime Dynamic Power = 0.00173373 W + Runtime Dynamic Energy = 1.073e-06 J + Total Runtime Energy = 3.22715e-06 J + + Execution Unit: + Area = 2.14837 mm^2 + Peak Dynamic Power = 0.97997 W + Subthreshold Leakage Power = 0.576941 W + Gate Leakage Power = 0.0454688 W + Runtime Dynamic Power = 0.000768951 W + Runtime Dynamic Energy = 4.75902e-07 J + Total Runtime Energy = 0.000385684 J + + Int Bypass Data: + Area = 0.0011767 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.000116661 W + Runtime Dynamic Energy = 7.22013e-08 J + Total Runtime Energy = 7.22013e-08 J + + Int Bypass Tag: + Area = 0.000147088 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 1.45826e-05 W + Runtime Dynamic Energy = 9.02516e-09 J + Total Runtime Energy = 9.02516e-09 J + + Mul Bypass Data: + Area = 0.00299957 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 7.0204e-06 W + Runtime Dynamic Energy = 4.34491e-09 J + Total Runtime Energy = 4.34491e-09 J + + Mul Bypass Tag: + Area = 0.000249964 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 5.85033e-07 W + Runtime Dynamic Energy = 3.62076e-10 J + Total Runtime Energy = 3.62076e-10 J + + FP Bypass Data: + Area = 0.0055603 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 2.86301e-06 W + Runtime Dynamic Energy = 1.77191e-09 J + Total Runtime Energy = 1.77191e-09 J + + FP Bypass Tag: + Area = 0.000504686 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 2.59864e-07 W + Runtime Dynamic Energy = 1.60829e-10 J + Total Runtime Energy = 1.60829e-10 J + + Register File Unit: + Area = 0.0196435 mm^2 + Peak Dynamic Power = 0.0336789 W + Subthreshold Leakage Power = 0.000856795 W + Gate Leakage Power = 4.5652e-05 W + Runtime Dynamic Power = 5.33509e-05 W + Runtime Dynamic Energy = 3.30188e-08 J + Total Runtime Energy = 5.91542e-07 J + + Integer Register File: + Area = 0.00982177 mm^2 + Peak Dynamic Power = 0.0249332 W + Subthreshold Leakage Power = 0.000428398 W + Gate Leakage Power = 2.2826e-05 W + Runtime Dynamic Power = 5.31399e-05 W + Runtime Dynamic Energy = 3.28882e-08 J + Total Runtime Energy = 3.1215e-07 J + + FP Register File: + Area = 0.00982177 mm^2 + Peak Dynamic Power = 0.00874563 W + Subthreshold Leakage Power = 0.000428398 W + Gate Leakage Power = 2.2826e-05 W + Runtime Dynamic Power = 2.11025e-07 W + Runtime Dynamic Energy = 1.30603e-10 J + Total Runtime Energy = 2.79392e-07 J + + Integer ALU(s): + Area = 0.0694232 mm^2 + Peak Dynamic Power = 0.157715 W + Subthreshold Leakage Power = 0.0542072 W + Gate Leakage Power = 0.00427414 W + Runtime Dynamic Power = 0.000539735 W + Runtime Dynamic Energy = 3.34041e-07 J + Total Runtime Energy = 3.6528e-05 J + + Floating Point Unit(s): + Area = 1.8404 mm^2 + Peak Dynamic Power = 0.473146 W + Subthreshold Leakage Power = 0.359256 W + Gate Leakage Power = 0.0283266 W + Runtime Dynamic Power = 8.40947e-06 W + Runtime Dynamic Energy = 5.2046e-09 J + Total Runtime Energy = 0.000239879 J + + Multiply/Divide Unit(s): + Area = 0.20827 mm^2 + Peak Dynamic Power = 0.31543 W + Subthreshold Leakage Power = 0.162622 W + Gate Leakage Power = 0.0128224 W + Runtime Dynamic Power = 2.54832e-05 W + Runtime Dynamic Energy = 1.57715e-08 J + Total Runtime Energy = 0.000108598 J + + Undifferentiated Core: + Area = 1.09115 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.425999 W + Gate Leakage Power = 0.0335892 W + Runtime Dynamic Power = 0 W + Runtime Dynamic Energy = 0 J + Total Runtime Energy = 0.000284438 J + + Pipeline?: + Area = 0.0575486 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0253286 W + Gate Leakage Power = 0.00502589 W + Runtime Dynamic Power = 0.300722 W + Runtime Dynamic Energy = 0.000186116 J + Total Runtime Energy = 0.000204903 J + + Memory Controller: + Area = 10.9173 mm^2 + Peak Dynamic Power = 0.965899 W + Subthreshold Leakage Power = 0.418723 W + Gate Leakage Power = 0.0401924 W + Runtime Dynamic Power = 0.00330988 W + Runtime Dynamic Energy = 2.04848e-06 J + Total Runtime Energy = 0.00028607 J + + Front End: + Area = 1.294 mm^2 + Peak Dynamic Power = 0.315876 W + Subthreshold Leakage Power = 0.00544595 W + Gate Leakage Power = 0.00760632 W + Runtime Dynamic Power = 0.000502467 W + Runtime Dynamic Energy = 3.10976e-07 J + Total Runtime Energy = 8.389e-06 J + + Reorder Buffer: + Area = 0.807284 mm^2 + Peak Dynamic Power = 0.299616 W + Subthreshold Leakage Power = 0.00480834 W + Gate Leakage Power = 0.00729614 W + Runtime Dynamic Power = 0.000472543 W + Runtime Dynamic Energy = 2.92456e-07 J + Total Runtime Energy = 7.78389e-06 J + + Read Buffer: + Area = 0.243356 mm^2 + Peak Dynamic Power = 0.00813026 W + Subthreshold Leakage Power = 0.000318803 W + Gate Leakage Power = 0.00015509 W + Runtime Dynamic Power = 1.79972e-05 W + Runtime Dynamic Energy = 1.11385e-08 J + Total Runtime Energy = 3.0443e-07 J + + Write Buffer: + Area = 0.243356 mm^2 + Peak Dynamic Power = 0.00813026 W + Subthreshold Leakage Power = 0.000318803 W + Gate Leakage Power = 0.00015509 W + Runtime Dynamic Power = 1.19268e-05 W + Runtime Dynamic Energy = 7.38145e-09 J + Total Runtime Energy = 3.00673e-07 J + + Transaction Engine: + Area = 3.27456 mm^2 + Peak Dynamic Power = 0.650022 W + Subthreshold Leakage Power = 0.140627 W + Gate Leakage Power = 0.0110882 W + Runtime Dynamic Power = 0.000945261 W + Runtime Dynamic Energy = 5.8502e-07 J + Total Runtime Energy = 9.44812e-05 J + + Physical Interface (PHY): + Area = 6.34878 mm^2 + Peak Dynamic Power = 1.09577e-09 W + Subthreshold Leakage Power = 0.27265 W + Gate Leakage Power = 0.0214979 W + Runtime Dynamic Power = 0.00186216 W + Runtime Dynamic Energy = 1.15248e-06 J + Total Runtime Energy = 0.0001832 J + + Cache Controller: + Area = 15.133 mm^2 + Peak Dynamic Power = 0.405711 W + Subthreshold Leakage Power = 2.44626 W + Gate Leakage Power = 0.129051 W + Runtime Dynamic Power = 0.078717 W + Runtime Dynamic Energy = 4.87178e-05 J + Total Runtime Energy = 0.00164257 J + + L1DcacheMemory: + Area = 1.25506 mm^2 + Peak Dynamic Power = 0.135091 W + Subthreshold Leakage Power = 0.0389812 W + Gate Leakage Power = 0.00174265 W + Runtime Dynamic Power = 0.0126856 W + Runtime Dynamic Energy = 7.85111e-06 J + Total Runtime Energy = 3.3055e-05 J + + Data and Tag Arrays: + Area = 0.254127 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0348112 W + Gate Leakage Power = 0.00135065 W + Runtime Dynamic Power = 0.0126728 W + Runtime Dynamic Energy = 7.84319e-06 J + Total Runtime Energy = 3.02237e-05 J + + Miss Buffer: + Area = 0.290483 mm^2 + Peak Dynamic Power = 0.0363943 W + Subthreshold Leakage Power = 0.00111783 W + Gate Leakage Power = 0.000105058 W + Runtime Dynamic Power = 4.57482e-06 W + Runtime Dynamic Energy = 2.83135e-09 J + Total Runtime Energy = 7.59677e-07 J + + Fill Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 4.10795e-06 W + Runtime Dynamic Energy = 2.5424e-09 J + Total Runtime Energy = 6.91401e-07 J + + Prefetch Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 2.58404e-06 W + Runtime Dynamic Energy = 1.59925e-09 J + Total Runtime Energy = 6.90458e-07 J + + Writeback Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 1.52392e-06 W + Runtime Dynamic Energy = 9.4315e-10 J + Total Runtime Energy = 6.89802e-07 J + + L1IcacheMemory: + Area = 1.25506 mm^2 + Peak Dynamic Power = 0.135091 W + Subthreshold Leakage Power = 0.0389812 W + Gate Leakage Power = 0.00174265 W + Runtime Dynamic Power = 0.0267244 W + Runtime Dynamic Energy = 1.65397e-05 J + Total Runtime Energy = 4.17436e-05 J + + Data and Tag Arrays: + Area = 0.254127 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0348112 W + Gate Leakage Power = 0.00135065 W + Runtime Dynamic Power = 0.0266962 W + Runtime Dynamic Energy = 1.65222e-05 J + Total Runtime Energy = 3.89027e-05 J + + Miss Buffer: + Area = 0.290483 mm^2 + Peak Dynamic Power = 0.0363943 W + Subthreshold Leakage Power = 0.00111783 W + Gate Leakage Power = 0.000105058 W + Runtime Dynamic Power = 1.01089e-05 W + Runtime Dynamic Energy = 6.25637e-09 J + Total Runtime Energy = 7.63102e-07 J + + Fill Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 9.07725e-06 W + Runtime Dynamic Energy = 5.61789e-09 J + Total Runtime Energy = 6.94476e-07 J + + Prefetch Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 7.55333e-06 W + Runtime Dynamic Energy = 4.67474e-09 J + Total Runtime Energy = 6.93533e-07 J + + Writeback Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 1.52392e-06 W + Runtime Dynamic Energy = 9.4315e-10 J + Total Runtime Energy = 6.89802e-07 J + + L2cacheMemory: + Area = 12.6229 mm^2 + Peak Dynamic Power = 0.135528 W + Subthreshold Leakage Power = 2.3683 W + Gate Leakage Power = 0.125565 W + Runtime Dynamic Power = 0.039307 W + Runtime Dynamic Energy = 2.4327e-05 J + Total Runtime Energy = 0.00156777 J + + Data and Tag Arrays: + Area = 11.6149 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 2.36411 W + Gate Leakage Power = 0.125172 W + Runtime Dynamic Power = 0.0393024 W + Runtime Dynamic Energy = 2.43242e-05 J + Total Runtime Energy = 0.00156494 J + + Miss Buffer: + Area = 0.297582 mm^2 + Peak Dynamic Power = 0.0368312 W + Subthreshold Leakage Power = 0.00113039 W + Gate Leakage Power = 0.000106234 W + Runtime Dynamic Power = 1.64403e-06 W + Runtime Dynamic Energy = 1.01749e-09 J + Total Runtime Energy = 7.66362e-07 J + + Fill Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 1.45766e-06 W + Runtime Dynamic Energy = 9.02143e-10 J + Total Runtime Energy = 6.89761e-07 J + + Prefetch Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 9.27602e-07 W + Runtime Dynamic Energy = 5.74091e-10 J + Total Runtime Energy = 6.89433e-07 J + + Writeback Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 5.30058e-07 W + Runtime Dynamic Energy = 3.28052e-10 J + Total Runtime Energy = 6.89187e-07 J + + Cache Controller: + Area = 15.133 mm^2 + Peak Dynamic Power = 0.405711 W + Subthreshold Leakage Power = 2.44626 W + Gate Leakage Power = 0.129051 W + Runtime Dynamic Power = 0.00344278 W + Runtime Dynamic Energy = 2.13073e-06 J + Total Runtime Energy = 0.00159598 J + + L1DcacheMemory: + Area = 1.25506 mm^2 + Peak Dynamic Power = 0.135091 W + Subthreshold Leakage Power = 0.0389812 W + Gate Leakage Power = 0.00174265 W + Runtime Dynamic Power = 0.000196889 W + Runtime Dynamic Energy = 1.21854e-07 J + Total Runtime Energy = 2.53258e-05 J + + Data and Tag Arrays: + Area = 0.254127 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0348112 W + Gate Leakage Power = 0.00135065 W + Runtime Dynamic Power = 0.000194413 W + Runtime Dynamic Energy = 1.20322e-07 J + Total Runtime Energy = 2.25008e-05 J + + Miss Buffer: + Area = 0.290483 mm^2 + Peak Dynamic Power = 0.0363943 W + Subthreshold Leakage Power = 0.00111783 W + Gate Leakage Power = 0.000105058 W + Runtime Dynamic Power = 8.8545e-07 W + Runtime Dynamic Energy = 5.48003e-10 J + Total Runtime Energy = 7.57394e-07 J + + Fill Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 7.95088e-07 W + Runtime Dynamic Energy = 4.92078e-10 J + Total Runtime Energy = 6.89351e-07 J + + Prefetch Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 5.96316e-07 W + Runtime Dynamic Energy = 3.69059e-10 J + Total Runtime Energy = 6.89228e-07 J + + Writeback Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 1.98772e-07 W + Runtime Dynamic Energy = 1.2302e-10 J + Total Runtime Energy = 6.88982e-07 J + + L1IcacheMemory: + Area = 1.25506 mm^2 + Peak Dynamic Power = 0.135091 W + Subthreshold Leakage Power = 0.0389812 W + Gate Leakage Power = 0.00174265 W + Runtime Dynamic Power = 0.000394295 W + Runtime Dynamic Energy = 2.44029e-07 J + Total Runtime Energy = 2.54479e-05 J + + Data and Tag Arrays: + Area = 0.254127 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0348112 W + Gate Leakage Power = 0.00135065 W + Runtime Dynamic Power = 0.000381504 W + Runtime Dynamic Energy = 2.36112e-07 J + Total Runtime Energy = 2.26166e-05 J + + Miss Buffer: + Area = 0.290483 mm^2 + Peak Dynamic Power = 0.0363943 W + Subthreshold Leakage Power = 0.00111783 W + Gate Leakage Power = 0.000105058 W + Runtime Dynamic Power = 4.57482e-06 W + Runtime Dynamic Energy = 2.83135e-09 J + Total Runtime Energy = 7.59677e-07 J + + Fill Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 4.10795e-06 W + Runtime Dynamic Energy = 2.5424e-09 J + Total Runtime Energy = 6.91401e-07 J + + Prefetch Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 2.58404e-06 W + Runtime Dynamic Energy = 1.59925e-09 J + Total Runtime Energy = 6.90458e-07 J + + Writeback Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 1.52392e-06 W + Runtime Dynamic Energy = 9.4315e-10 J + Total Runtime Energy = 6.89802e-07 J + + L2cacheMemory: + Area = 12.6229 mm^2 + Peak Dynamic Power = 0.135528 W + Subthreshold Leakage Power = 2.3683 W + Gate Leakage Power = 0.125565 W + Runtime Dynamic Power = 0.00285159 W + Runtime Dynamic Energy = 1.76485e-06 J + Total Runtime Energy = 0.00154521 J + + Data and Tag Arrays: + Area = 11.6149 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 2.36411 W + Gate Leakage Power = 0.125172 W + Runtime Dynamic Power = 0.00282766 W + Runtime Dynamic Energy = 1.75003e-06 J + Total Runtime Energy = 0.00154236 J + + Miss Buffer: + Area = 0.297582 mm^2 + Peak Dynamic Power = 0.0368312 W + Subthreshold Leakage Power = 0.00113039 W + Gate Leakage Power = 0.000106234 W + Runtime Dynamic Power = 8.63117e-06 W + Runtime Dynamic Energy = 5.34181e-09 J + Total Runtime Energy = 7.70686e-07 J + + Fill Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 7.65272e-06 W + Runtime Dynamic Energy = 4.73625e-09 J + Total Runtime Energy = 6.93595e-07 J + + Prefetch Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 7.65272e-06 W + Runtime Dynamic Energy = 4.73625e-09 J + Total Runtime Energy = 6.93595e-07 J + + Writeback Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.032899 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 0 W + Runtime Dynamic Energy = 0 J + Total Runtime Energy = 6.88859e-07 J + diff --git a/ext/mcpat/regression/test-2/power_region0.xml b/ext/mcpat/regression/test-2/power_region0.xml new file mode 100644 index 000000000..2c8521afb --- /dev/null +++ b/ext/mcpat/regression/test-2/power_region0.xml @@ -0,0 +1,242 @@ +<?xml version="1.0" ?> +<component id="root" name="root"> + <component id="system" name="system" type="System"> + <param name="core_tech_node" value="40"/> + <param name="target_core_clockrate" value="1400"/> + <param name="temperature" value="360"/> + <param name="interconnect_projection_type" value="0"/> + <param name="device_type" value="0"/> + <param name="machine_bits" value="64"/> + <param name="virtual_address_width" value="64"/> + <param name="physical_address_width" value="52"/> + <param name="virtual_memory_page_size" value="4096"/> + <param name="wire_is_mat_type" value="2"/> + <param name="wire_os_mat_type" value="2"/> + <param name="delay_wt" value="100"/> + <param name="area_wt" value="0"/> + <param name="dynamic_power_wt" value="100"/> + <param name="leakage_power_wt" value="0"/> + <param name="cycle_time_wt" value="0"/> + <param name="delay_dev" value="10000"/> + <param name="area_dev" value="10000"/> + <param name="dynamic_power_dev" value="10000"/> + <param name="leakage_power_dev" value="10000"/> + <param name="cycle_time_dev" value="10000"/> + <param name="ed" value="2"/> + <param name="burst_len" value="1"/> + <param name="int_prefetch_w" value="1"/> + <param name="page_sz_bits" value="0"/> + <param name="rpters_in_htree" value="1"/> + <param name="ver_htree_wires_over_array" value="0"/> + <param name="nuca" value="0"/> + <param name="nuca_bank_count" value="0"/> + <param name="force_cache_config" value="0"/> + <param name="wt" value="0"/> + <param name="force_wiretype" value="0"/> + <param name="print_detail" value="1"/> + <param name="add_ecc_b_" value="1"/> + <stat name="total_cycles" value="566948"/> + <component id="system.l1_cntrl0" name="l1_cntrl0" type="CacheController"> + <component id="system.l1_cntrl0.L1DcacheMemory" name="L1DcacheMemory" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="2"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="clockrate" value="2000"/> + <param name="device_type" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="47291"/> + <stat name="num_data_array_writes" value="51619"/> + <stat name="num_tag_array_reads" value="91498"/> + <stat name="num_tag_array_writes" value="17078"/> + <stat name="read_misses" value="174"/> + <stat name="write_misses" value="12046"/> + <stat name="conflicts" value="12120"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.l1_cntrl0.L1IcacheMemory" name="L1IcacheMemory" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="2"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="clockrate" value="2000"/> + <param name="device_type" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="253831"/> + <stat name="num_data_array_writes" value="3497"/> + <stat name="num_tag_array_reads" value="253291"/> + <stat name="num_tag_array_writes" value="10845"/> + <stat name="read_misses" value="100"/> + <stat name="conflicts" value="99"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.l1_cntrl0.L2cacheMemory" name="L2cacheMemory" type="CacheUnit"> + <param name="level" value="2"/> + <param name="size" value="2097152"/> + <param name="block_size" value="64"/> + <param name="assoc" value="16"/> + <param name="num_banks" value="1"/> + <param name="latency" value="10"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="clockrate" value="2000"/> + <param name="device_type" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="1"/> + <param name="miss_buff_access_mode" value="0"/> + <param name="fetch_buff_access_mode" value="0"/> + <param name="prefetch_buff_access_mode" value="0"/> + <param name="writeback_buff_access_mode"value="0"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="3959"/> + <stat name="num_data_array_writes" value="8086"/> + <stat name="num_tag_array_reads" value="274"/> + <stat name="num_tag_array_writes" value="12046"/> + <stat name="read_misses" value="27"/> + <stat name="write_misses" value="1204"/> + <stat name="conflicts" value="1231"/> + <stat name="duty_cycle" value="1"/> + </component> + </component> + </component> +</component> diff --git a/ext/mcpat/regression/test-2/region0.out.ref b/ext/mcpat/regression/test-2/region0.out.ref new file mode 100644 index 000000000..dd6d62120 --- /dev/null +++ b/ext/mcpat/regression/test-2/region0.out.ref @@ -0,0 +1,190 @@ +McPAT (version 0.8 of Aug, 2010) is computing the target processor... + + +McPAT (version 0.8 of Aug, 2010) results (current print level is 5) +***************************************************************************************** + Technology 40 nm + Interconnect metal projection = aggressive interconnect technology projection + Target Clock Rate (MHz) 1400 + +***************************************************************************************** + System: + Area = 15.133 mm^2 + Peak Dynamic Power = 0.270474 W + Subthreshold Leakage Power = 2.44626 W + Gate Leakage Power = 0.129051 W + Runtime Dynamic Power = 0.123193 W + Runtime Dynamic Energy = 4.98884e-05 J + Total Runtime Energy = 0.00109279 J + + Cache Controller: + Area = 15.133 mm^2 + Peak Dynamic Power = 0.270474 W + Subthreshold Leakage Power = 2.44626 W + Gate Leakage Power = 0.129051 W + Runtime Dynamic Power = 0.123193 W + Runtime Dynamic Energy = 4.98884e-05 J + Total Runtime Energy = 0.00109279 J + + L1DcacheMemory: + Area = 1.25506 mm^2 + Peak Dynamic Power = 0.0900609 W + Subthreshold Leakage Power = 0.0389812 W + Gate Leakage Power = 0.00174265 W + Runtime Dynamic Power = 0.0203309 W + Runtime Dynamic Energy = 8.23325e-06 J + Total Runtime Energy = 2.47249e-05 J + + Data and Tag Arrays: + Area = 0.254127 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0348112 W + Gate Leakage Power = 0.00135065 W + Runtime Dynamic Power = 0.0193677 W + Runtime Dynamic Energy = 7.84319e-06 J + Total Runtime Energy = 2.24874e-05 J + + Miss Buffer: + Area = 0.290483 mm^2 + Peak Dynamic Power = 0.0242629 W + Subthreshold Leakage Power = 0.00111783 W + Gate Leakage Power = 0.000105058 W + Runtime Dynamic Power = 0.000344507 W + Runtime Dynamic Energy = 1.39512e-07 J + Total Runtime Energy = 6.34739e-07 J + + Fill Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.0219327 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 0.000309349 W + Runtime Dynamic Energy = 1.25275e-07 J + Total Runtime Energy = 5.76015e-07 J + + Prefetch Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.0219327 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 4.40481e-06 W + Runtime Dynamic Energy = 1.78378e-09 J + Total Runtime Energy = 4.52524e-07 J + + Writeback Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.0219327 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 0.000304944 W + Runtime Dynamic Energy = 1.23491e-07 J + Total Runtime Energy = 5.74231e-07 J + + L1IcacheMemory: + Area = 1.25506 mm^2 + Peak Dynamic Power = 0.0900609 W + Subthreshold Leakage Power = 0.0389812 W + Gate Leakage Power = 0.00174265 W + Runtime Dynamic Power = 0.0408072 W + Runtime Dynamic Energy = 1.65254e-05 J + Total Runtime Energy = 3.3017e-05 J + + Data and Tag Arrays: + Area = 0.254127 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0348112 W + Gate Leakage Power = 0.00135065 W + Runtime Dynamic Power = 0.0407993 W + Runtime Dynamic Energy = 1.65222e-05 J + Total Runtime Energy = 3.11664e-05 J + + Miss Buffer: + Area = 0.290483 mm^2 + Peak Dynamic Power = 0.0242629 W + Subthreshold Leakage Power = 0.00111783 W + Gate Leakage Power = 0.000105058 W + Runtime Dynamic Power = 2.8192e-06 W + Runtime Dynamic Energy = 1.14167e-09 J + Total Runtime Energy = 4.96368e-07 J + + Fill Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.0219327 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 2.5315e-06 W + Runtime Dynamic Energy = 1.02516e-09 J + Total Runtime Energy = 4.51765e-07 J + + Prefetch Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.0219327 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 2.5315e-06 W + Runtime Dynamic Energy = 1.02516e-09 J + Total Runtime Energy = 4.51765e-07 J + + Writeback Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.0219327 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 0 W + Runtime Dynamic Energy = 0 J + Total Runtime Energy = 4.5074e-07 J + + L2cacheMemory: + Area = 12.6229 mm^2 + Peak Dynamic Power = 0.0903521 W + Subthreshold Leakage Power = 2.3683 W + Gate Leakage Power = 0.125565 W + Runtime Dynamic Power = 0.0620546 W + Runtime Dynamic Energy = 2.51298e-05 J + Total Runtime Energy = 0.00103505 J + + Data and Tag Arrays: + Area = 11.6149 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 2.36411 W + Gate Leakage Power = 0.125172 W + Runtime Dynamic Power = 0.0619571 W + Runtime Dynamic Energy = 2.50903e-05 J + Total Runtime Energy = 0.00103316 J + + Miss Buffer: + Area = 0.297582 mm^2 + Peak Dynamic Power = 0.0245541 W + Subthreshold Leakage Power = 0.00113039 W + Gate Leakage Power = 0.000106234 W + Runtime Dynamic Power = 3.51471e-05 W + Runtime Dynamic Energy = 1.42333e-08 J + Total Runtime Energy = 5.1502e-07 J + + Fill Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.0219327 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 3.11627e-05 W + Runtime Dynamic Energy = 1.26198e-08 J + Total Runtime Energy = 4.6336e-07 J + + Prefetch Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.0219327 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 6.83505e-07 W + Runtime Dynamic Energy = 2.76794e-10 J + Total Runtime Energy = 4.51017e-07 J + + Writeback Buffer: + Area = 0.236817 mm^2 + Peak Dynamic Power = 0.0219327 W + Subthreshold Leakage Power = 0.00101739 W + Gate Leakage Power = 9.56483e-05 W + Runtime Dynamic Power = 3.04792e-05 W + Runtime Dynamic Energy = 1.2343e-08 J + Total Runtime Energy = 4.63083e-07 J + diff --git a/ext/mcpat/regression/test-3/power_region0.xml b/ext/mcpat/regression/test-3/power_region0.xml new file mode 100644 index 000000000..80c8c113c --- /dev/null +++ b/ext/mcpat/regression/test-3/power_region0.xml @@ -0,0 +1,71 @@ +<?xml version="1.0" ?> +<component id="root" name="root"> + <component id="system" name="system" type="System"> + <param name="core_tech_node" value="40"/> + <param name="target_core_clockrate" value="1000"/> + <param name="temperature" value="360"/> + <param name="interconnect_projection_type" value="0"/> + <param name="device_type" value="0"/> + <param name="machine_bits" value="64"/> + <param name="virtual_address_width" value="64"/> + <param name="physical_address_width" value="52"/> + <param name="virtual_memory_page_size" value="4096"/> + <param name="wire_is_mat_type" value="2"/> + <param name="wire_os_mat_type" value="2"/> + <param name="delay_wt" value="100"/> + <param name="area_wt" value="0"/> + <param name="dynamic_power_wt" value="100"/> + <param name="leakage_power_wt" value="0"/> + <param name="cycle_time_wt" value="0"/> + <param name="delay_dev" value="10000"/> + <param name="area_dev" value="10000"/> + <param name="dynamic_power_dev" value="10000"/> + <param name="leakage_power_dev" value="10000"/> + <param name="cycle_time_dev" value="10000"/> + <param name="ed" value="2"/> + <param name="burst_len" value="1"/> + <param name="int_prefetch_w" value="1"/> + <param name="page_sz_bits" value="0"/> + <param name="rpters_in_htree" value="1"/> + <param name="ver_htree_wires_over_array" value="0"/> + <param name="nuca" value="0"/> + <param name="nuca_bank_count" value="0"/> + <param name="force_cache_config" value="0"/> + <param name="wt" value="0"/> + <param name="force_wiretype" value="0"/> + <param name="print_detail" value="1"/> + <param name="add_ecc_b_" value="1"/> + <stat name="total_cycles" value="1856694"/> + <component id="system.mc" name="mc" type="MemoryController"> + <param name="mc_clock" value="800"/> + <param name="tech_type" value="0"/> + <param name="mc_type" value="0"/> + <param name="num_mcs" value="1"/> + <param name="type" value="0"/> + <param name="LVDS" value="1"/> + <param name="withPHY" value="0"/> + <param name="llc_line_length" value="64"/> + <param name="memory_channels_per_mc" value="2"/> + <param name="req_window_size_per_channel" value="128"/> + <param name="IO_buffer_size_per_channel" value="128"/> + <param name="databus_width" value="128"/> + <param name="addressbus_width" value="51"/> + <param name="opcode_width" value="16"/> + <param name="peak_transfer_rate" value="6400"/> + <param name="number_ranks" value="2"/> + <param name="reorder_buffer_assoc" value="0"/> + <param name="reorder_buffer_nbanks" value="1"/> + <param name="read_buffer_assoc" value="1"/> + <param name="read_buffer_nbanks" value="1"/> + <param name="read_buffer_tag_width" value="0"/> + <param name="write_buffer_assoc" value="1"/> + <param name="write_buffer_nbanks" value="1"/> + <param name="write_buffer_tag_width" value="0"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <stat name="memory_reads" value="5454"/> + <stat name="memory_writes" value="2424"/> + <stat name="duty_cycle" value="0.5"/> + </component> + </component> +</component> diff --git a/ext/mcpat/regression/test-3/region0.out.ref b/ext/mcpat/regression/test-3/region0.out.ref new file mode 100644 index 000000000..64cfc03bb --- /dev/null +++ b/ext/mcpat/regression/test-3/region0.out.ref @@ -0,0 +1,82 @@ +McPAT (version 0.8 of Aug, 2010) is computing the target processor... + + +McPAT (version 0.8 of Aug, 2010) results (current print level is 5) +***************************************************************************************** + Technology 40 nm + Interconnect metal projection = aggressive interconnect technology projection + Target Clock Rate (MHz) 1000 + +***************************************************************************************** + System: + Area = 10.1619 mm^2 + Peak Dynamic Power = 0.802936 W + Subthreshold Leakage Power = 0.435736 W + Gate Leakage Power = 0.0339261 W + Runtime Dynamic Power = 0.0198915 W + Runtime Dynamic Energy = 3.69324e-05 J + Total Runtime Energy = 0.00090895 J + + Memory Controller: + Area = 10.1619 mm^2 + Peak Dynamic Power = 0.802936 W + Subthreshold Leakage Power = 0.435736 W + Gate Leakage Power = 0.0339261 W + Runtime Dynamic Power = 0.0198915 W + Runtime Dynamic Energy = 3.69324e-05 J + Total Runtime Energy = 0.00090895 J + + Front End: + Area = 0.538603 mm^2 + Peak Dynamic Power = 0.152914 W + Subthreshold Leakage Power = 0.0224588 W + Gate Leakage Power = 0.00133997 W + Runtime Dynamic Power = 0.00210718 W + Runtime Dynamic Energy = 3.91238e-06 J + Total Runtime Energy = 4.80994e-05 J + + Reorder Buffer: + Area = 0.242439 mm^2 + Peak Dynamic Power = 0.116672 W + Subthreshold Leakage Power = 0.0135852 W + Gate Leakage Power = 0.000923575 W + Runtime Dynamic Power = 0.00165964 W + Runtime Dynamic Energy = 3.08145e-06 J + Total Runtime Energy = 3.00199e-05 J + + Read Buffer: + Area = 0.148082 mm^2 + Peak Dynamic Power = 0.018121 W + Subthreshold Leakage Power = 0.00443679 W + Gate Leakage Power = 0.000208199 W + Runtime Dynamic Power = 0.00026615 W + Runtime Dynamic Energy = 4.9416e-07 J + Total Runtime Energy = 9.11848e-06 J + + Write Buffer: + Area = 0.148082 mm^2 + Peak Dynamic Power = 0.018121 W + Subthreshold Leakage Power = 0.00443679 W + Gate Leakage Power = 0.000208199 W + Runtime Dynamic Power = 0.000181383 W + Runtime Dynamic Energy = 3.36773e-07 J + Total Runtime Energy = 8.9611e-06 J + + Transaction Engine: + Area = 3.27456 mm^2 + Peak Dynamic Power = 0.650022 W + Subthreshold Leakage Power = 0.140627 W + Gate Leakage Power = 0.0110882 W + Runtime Dynamic Power = 0.00689515 W + Runtime Dynamic Energy = 1.28022e-05 J + Total Runtime Energy = 0.000294491 J + + Physical Interface (PHY): + Area = 6.34878 mm^2 + Peak Dynamic Power = 1.09577e-09 W + Subthreshold Leakage Power = 0.27265 W + Gate Leakage Power = 0.0214979 W + Runtime Dynamic Power = 0.0108891 W + Runtime Dynamic Energy = 2.02178e-05 J + Total Runtime Energy = 0.00056636 J + diff --git a/ext/mcpat/regression/test-4/power_region0.xml b/ext/mcpat/regression/test-4/power_region0.xml new file mode 100644 index 000000000..5ea50d389 --- /dev/null +++ b/ext/mcpat/regression/test-4/power_region0.xml @@ -0,0 +1,208 @@ +<?xml version="1.0" ?> +<component id="root" name="root"> + <component id="system" name="system" type="System"> + <param name="core_tech_node" value="40"/> + <param name="target_core_clockrate" value="2400"/> + <param name="temperature" value="360"/> + <param name="interconnect_projection_type" value="0"/> + <param name="device_type" value="0"/> + <param name="machine_bits" value="64"/> + <param name="virtual_address_width" value="64"/> + <param name="physical_address_width" value="52"/> + <param name="virtual_memory_page_size" value="4096"/> + <param name="wire_is_mat_type" value="2"/> + <param name="wire_os_mat_type" value="2"/> + <param name="delay_wt" value="100"/> + <param name="area_wt" value="0"/> + <param name="dynamic_power_wt" value="100"/> + <param name="leakage_power_wt" value="0"/> + <param name="cycle_time_wt" value="0"/> + <param name="delay_dev" value="10000"/> + <param name="area_dev" value="10000"/> + <param name="dynamic_power_dev" value="10000"/> + <param name="leakage_power_dev" value="10000"/> + <param name="cycle_time_dev" value="10000"/> + <param name="ed" value="2"/> + <param name="burst_len" value="1"/> + <param name="int_prefetch_w" value="1"/> + <param name="page_sz_bits" value="0"/> + <param name="rpters_in_htree" value="1"/> + <param name="ver_htree_wires_over_array" value="0"/> + <param name="nuca" value="0"/> + <param name="nuca_bank_count" value="0"/> + <param name="force_cache_config" value="0"/> + <param name="wt" value="0"/> + <param name="force_wiretype" value="0"/> + <param name="print_detail" value="1"/> + <param name="add_ecc_b_" value="1"/> + <stat name="total_cycles" value="1856694"/> + <component id="system.core0" name="core0" type="Core"> + <param name="opt_local" value="0"/> + <param name="clock_rate" value="2000"/> + <param name="instruction_length" value="32"/> + <param name="opcode_width" value="6"/> + <param name="machine_type" value="1"/> + <param name="number_hardware_threads" value="1"/> + <param name="fetch_width" value="1"/> + <param name="number_instruction_fetch_ports" value="1"/> + <param name="decode_width" value="1"/> + <param name="issue_width" value="1"/> + <param name="peak_issue_width" value="1"/> + <param name="commit_width" value="1"/> + <param name="fp_issue_width" value="1"/> + <param name="prediction_width" value="1"/> + <param name="int_pipelines" value="1"/> + <param name="fp_pipelines" value="1"/> + <param name="int_pipeline_depth" value="7"/> + <param name="fp_pipeline_depth" value="10"/> + <param name="ALU_per_core" value="1"/> + <param name="FPU_per_core" value="1"/> + <param name="MUL_per_core" value="1"/> + <param name="instruction_buffer_size" value="16"/> + <param name="instruction_window_scheme" value="0"/> + <param name="instruction_window_size" value="0"/> + <param name="fp_instruction_window_size" value="0"/> + <param name="ROB_size" value="0"/> + <param name="archi_Regs_IRF_size" value="32"/> + <param name="archi_Regs_FRF_size" value="32"/> + <param name="phy_Regs_IRF_size" value="32"/> + <param name="phy_Regs_FRF_size" value="32"/> + <param name="rename_scheme" value="0"/> + <param name="register_window_size" value="0"/> + <param name="store_buffer_size" value="8"/> + <param name="load_buffer_size" value="0"/> + <param name="memory_ports" value="1"/> + <param name="RAS_size" value="32"/> + <param name="execu_wire_mat_type" value="2"/> + <param name="execu_bypass_base_width" value="1"/> + <param name="execu_bypass_base_height" value="1"/> + <param name="execu_bypass_start_wiring_level"value="3"/> + <param name="execu_bypass_route_over_perc" value="1"/> + <param name="globalCheckpoint" value="32"/> + <param name="perThreadState" value="8"/> + <param name="ROB_assoc" value="1"/> + <param name="ROB_nbanks" value="1"/> + <param name="ROB_tag_width" value="0"/> + <param name="scheduler_assoc" value="0"/> + <param name="scheduler_nbanks" value="1"/> + <param name="register_window_assoc" value="1"/> + <param name="register_window_nbanks" value="1"/> + <param name="register_window_tag_width" value="0"/> + <param name="register_window_rw_ports" value="1"/> + <param name="phy_Regs_IRF_assoc" value="1"/> + <param name="phy_Regs_IRF_nbanks" value="1"/> + <param name="phy_Regs_IRF_tag_width" value="0"/> + <param name="phy_Regs_IRF_rd_ports" value="1"/> + <param name="phy_Regs_IRF_wr_ports" value="1"/> + <param name="phy_Regs_FRF_assoc" value="1"/> + <param name="phy_Regs_FRF_nbanks" value="1"/> + <param name="phy_Regs_FRF_tag_width" value="0"/> + <param name="phy_Regs_FRF_rd_ports" value="1"/> + <param name="phy_Regs_FRF_wr_ports" value="1"/> + <param name="front_rat_nbanks" value="1"/> + <param name="front_rat_rw_ports" value="1"/> + <param name="retire_rat_nbanks" value="1"/> + <param name="retire_rat_rw_ports" value="0"/> + <param name="freelist_nbanks" value="1"/> + <param name="freelist_rw_ports" value="1"/> + <param name="load_buffer_assoc" value="0"/> + <param name="load_buffer_nbanks" value="1"/> + <param name="store_buffer_assoc" value="0"/> + <param name="store_buffer_nbanks" value="1"/> + <param name="instruction_buffer_assoc" value="1"/> + <param name="instruction_buffer_nbanks" value="1"/> + <param name="instruction_buffer_tag_width" value="0"/> + <stat name="total_instructions" value="332405"/> + <stat name="int_instructions" value="330557"/> + <stat name="fp_instructions" value="1649"/> + <stat name="branch_instructions" value="32405"/> + <stat name="branch_mispredictions" value="4132"/> + <stat name="load_instructions" value="45636"/> + <stat name="store_instructions" value="44771"/> + <stat name="committed_instructions" value="332405"/> + <stat name="committed_int_instructions" value="330557"/> + <stat name="committed_fp_instructions" value="1649"/> + <stat name="total_cycles" value="9496951709"/> + <stat name="idle_cycles" value="103"/> + <stat name="busy_cycles" value="9496951606"/> + <stat name="ROB_reads" value="332405"/> + <stat name="ROB_writes" value="332405"/> + <stat name="rename_reads" value="960725"/> + <stat name="rename_writes" value="317221"/> + <stat name="fp_rename_reads" value="2772"/> + <stat name="fp_rename_writes" value="1288"/> + <stat name="inst_window_reads" value="330557"/> + <stat name="inst_window_writes" value="330557"/> + <stat name="inst_window_wakeup_accesses" value="330557"/> + <stat name="fp_inst_window_reads" value="1649"/> + <stat name="fp_inst_window_writes" value="1649"/> + <stat name="fp_inst_window_wakeup_accesses" value="1649"/> + <stat name="int_regfile_reads" value="960725"/> + <stat name="float_regfile_reads" value="2772"/> + <stat name="int_regfile_writes" value="317221"/> + <stat name="float_regfile_writes" value="1288"/> + <stat name="function_calls" value="2546"/> + <stat name="context_switches" value="3"/> + <stat name="ialu_accesses" value="330157"/> + <stat name="fpu_accesses" value="1649"/> + <stat name="mul_accesses" value="400"/> + <stat name="cdb_alu_accesses" value="330157"/> + <stat name="cdb_mul_accesses" value="400"/> + <stat name="cdb_fpu_accesses" value="1649"/> + <stat name="IFU_duty_cycle" value="1"/> + <stat name="LSU_duty_cycle" value="1"/> + <stat name="MemManU_I_duty_cycle" value="1"/> + <stat name="MemManU_D_duty_cycle" value="1"/> + <stat name="ALU_duty_cycle" value="1"/> + <stat name="MUL_duty_cycle" value="1"/> + <stat name="FPU_duty_cycle" value="1"/> + <stat name="ALU_cdb_duty_cycle" value="1"/> + <stat name="MUL_cdb_duty_cycle" value="1"/> + <stat name="FPU_cdb_duty_cycle" value="1"/> + <component id="system.core0.bpred" name="bpred" type="BranchPredictor"> + <param name="assoc" value="1"/> + <param name="nbanks" value="1"/> + <param name="local_l1_predictor_size" value="10"/> + <param name="local_l2_predictor_size" value="3"/> + <param name="local_predictor_entries" value="1024"/> + <param name="global_predictor_entries" value="4096"/> + <param name="global_predictor_bits" value="2"/> + <param name="chooser_predictor_entries" value="4096"/> + <param name="chooser_predictor_bits" value="2"/> + </component> + <component id="system.core0.itlb" name="itlb" type="InstructionTLB"> + <param name="number_entries" value="64"/> + <param name="latency" value="2"/> + <param name="throughput" value="2"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="total_accesses" value="72"/> + <stat name="total_misses" value="36"/> + <stat name="conflicts" value="0"/> + </component> + <component id="system.core0.dtlb" name="dtlb" type="DataTLB"> + <param name="number_entries" value="64"/> + <param name="latency" value="2"/> + <param name="throughput" value="2"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="read_accesses" value="534"/> + <stat name="write_accesses" value="0"/> + <stat name="read_misses" value="25"/> + <stat name="write_misses" value="0"/> + <stat name="conflicts" value="0"/> + </component> + <component id="system.core0.btargetbuf" name="btargetbuf" type="BranchTargetBuffer"> + <param name="size" value="8192"/> + <param name="block_size" value="4"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="1"/> + <param name="throughput" value="3"/> + <param name="rw_ports" value="1"/> + <stat name="read_accesses" value="43"/> + <stat name="write_accesses" value="943"/> + </component> + </component> + </component> +</component> diff --git a/ext/mcpat/regression/test-4/region0.out.ref b/ext/mcpat/regression/test-4/region0.out.ref new file mode 100644 index 000000000..305020db9 --- /dev/null +++ b/ext/mcpat/regression/test-4/region0.out.ref @@ -0,0 +1,316 @@ +McPAT (version 0.8 of Aug, 2010) is computing the target processor... + + +McPAT (version 0.8 of Aug, 2010) results (current print level is 5) +***************************************************************************************** + Technology 40 nm + Interconnect metal projection = aggressive interconnect technology projection + Target Clock Rate (MHz) 2400 + +***************************************************************************************** + System: + Area = 4.03988 mm^2 + Peak Dynamic Power = 1.13952 W + Subthreshold Leakage Power = 1.09948 W + Gate Leakage Power = 0.0880822 W + Runtime Dynamic Power = 0.304667 W + Runtime Dynamic Energy = 0.000235697 J + Total Runtime Energy = 0.00115442 J + + Core 0: + Area = 4.03988 mm^2 + Peak Dynamic Power = 1.13952 W + Subthreshold Leakage Power = 1.09948 W + Gate Leakage Power = 0.0880822 W + Runtime Dynamic Power = 0.304667 W + Runtime Dynamic Energy = 0.000235697 J + Total Runtime Energy = 0.00115442 J + + Instruction Fetch Unit: + Area = 0.646243 mm^2 + Peak Dynamic Power = 0.0998237 W + Subthreshold Leakage Power = 0.0641442 W + Gate Leakage Power = 0.00348734 W + Runtime Dynamic Power = 0.0165339 W + Runtime Dynamic Energy = 1.2791e-05 J + Total Runtime Energy = 6.51122e-05 J + + Branch Target Buffer: + Area = 0.526882 mm^2 + Peak Dynamic Power = 0.05291 W + Subthreshold Leakage Power = 0.0468647 W + Gate Leakage Power = 0.00268178 W + Runtime Dynamic Power = 7.47781e-05 W + Runtime Dynamic Energy = 5.785e-08 J + Total Runtime Energy = 3.83881e-05 J + + Branch Predictor: + Area = 0.117913 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0166783 W + Gate Leakage Power = 0.000768254 W + Runtime Dynamic Power = 0.00638034 W + Runtime Dynamic Energy = 4.93598e-06 J + Total Runtime Energy = 1.8433e-05 J + + Global Predictor: + Area = 0.0375885 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.00584294 W + Gate Leakage Power = 0.000266459 W + Runtime Dynamic Power = 0.00224596 W + Runtime Dynamic Energy = 1.73753e-06 J + Total Runtime Energy = 6.4639e-06 J + + Local Predictor, Level 1: + Area = 0.0226899 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0029458 W + Gate Leakage Power = 0.000134 W + Runtime Dynamic Power = 0.00172351 W + Runtime Dynamic Energy = 1.33334e-06 J + Total Runtime Energy = 3.71595e-06 J + + Local Predictor, Level 2: + Area = 0.0111174 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.00161822 W + Gate Leakage Power = 7.85114e-05 W + Runtime Dynamic Power = 0.000151207 W + Runtime Dynamic Energy = 1.16977e-07 J + Total Runtime Energy = 1.42961e-06 J + + Predictor Chooser: + Area = 0.0375885 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.00584294 W + Gate Leakage Power = 0.000266459 W + Runtime Dynamic Power = 0.00224596 W + Runtime Dynamic Energy = 1.73753e-06 J + Total Runtime Energy = 6.4639e-06 J + + RAS: + Area = 0.00892889 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.000428398 W + Gate Leakage Power = 2.2826e-05 W + Runtime Dynamic Power = 1.37057e-05 W + Runtime Dynamic Energy = 1.0603e-08 J + Total Runtime Energy = 3.5968e-07 J + + Instruction Buffer: + Area = 0.000887187 mm^2 + Peak Dynamic Power = 0.00270456 W + Subthreshold Leakage Power = 8.79429e-05 W + Gate Leakage Power = 5.07123e-06 W + Runtime Dynamic Power = 0.000581039 W + Runtime Dynamic Energy = 4.49505e-07 J + Total Runtime Energy = 5.21463e-07 J + + Instruction Opcode Decoder: + Area = 0.000370909 mm^2 + Peak Dynamic Power = 0.022114 W + Subthreshold Leakage Power = 0.000341264 W + Gate Leakage Power = 2.1391e-05 W + Runtime Dynamic Power = 0.00475089 W + Runtime Dynamic Energy = 3.6754e-06 J + Total Runtime Energy = 3.95595e-06 J + + Instruction Operand Decoder: + Area = 0.00018867 mm^2 + Peak Dynamic Power = 0.0220952 W + Subthreshold Leakage Power = 0.000171916 W + Gate Leakage Power = 1.08411e-05 W + Runtime Dynamic Power = 0.00474686 W + Runtime Dynamic Energy = 3.67227e-06 J + Total Runtime Energy = 3.81366e-06 J + + Instruction Microcode Decoder: + Area = 0 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0 W + Runtime Dynamic Energy = 0 J + Total Runtime Energy = 0 J + + Load/Store Unit: + Area = 0.0429074 mm^2 + Peak Dynamic Power = 0.0147095 W + Subthreshold Leakage Power = 0.000986438 W + Gate Leakage Power = 8.4035e-05 W + Runtime Dynamic Power = 0.00171897 W + Runtime Dynamic Energy = 1.32984e-06 J + Total Runtime Energy = 2.15798e-06 J + + Store Queue: + Area = 0.0429074 mm^2 + Peak Dynamic Power = 0.0147095 W + Subthreshold Leakage Power = 0.000986438 W + Gate Leakage Power = 8.4035e-05 W + Runtime Dynamic Power = 0.00171897 W + Runtime Dynamic Energy = 1.32984e-06 J + Total Runtime Energy = 2.15798e-06 J + + Memory Management Unit: + Area = 0.0536541 mm^2 + Peak Dynamic Power = 0.0450214 W + Subthreshold Leakage Power = 0.00608426 W + Gate Leakage Power = 0.000426918 W + Runtime Dynamic Power = 9.42932e-06 W + Runtime Dynamic Energy = 7.29474e-09 J + Total Runtime Energy = 5.04449e-06 J + + Instruction TLB: + Area = 0.0183885 mm^2 + Peak Dynamic Power = 0.0215705 W + Subthreshold Leakage Power = 0.00282912 W + Gate Leakage Power = 0.000201432 W + Runtime Dynamic Power = 1.18848e-06 W + Runtime Dynamic Energy = 9.19436e-10 J + Total Runtime Energy = 2.34543e-06 J + + Data TLB: + Area = 0.0352657 mm^2 + Peak Dynamic Power = 0.0234509 W + Subthreshold Leakage Power = 0.00325513 W + Gate Leakage Power = 0.000225486 W + Runtime Dynamic Power = 8.24084e-06 W + Runtime Dynamic Energy = 6.3753e-09 J + Total Runtime Energy = 2.69906e-06 J + + Execution Unit: + Area = 2.14837 mm^2 + Peak Dynamic Power = 0.97997 W + Subthreshold Leakage Power = 0.576941 W + Gate Leakage Power = 0.0454688 W + Runtime Dynamic Power = 0.0458266 W + Runtime Dynamic Energy = 3.54525e-05 J + Total Runtime Energy = 0.000516963 J + + Int Bypass Data: + Area = 0.0011767 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00727412 W + Runtime Dynamic Energy = 5.62742e-06 J + Total Runtime Energy = 5.62742e-06 J + + Int Bypass Tag: + Area = 0.000147088 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.000909265 W + Runtime Dynamic Energy = 7.03428e-07 J + Total Runtime Energy = 7.03428e-07 J + + Mul Bypass Data: + Area = 0.00299957 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 2.24653e-05 W + Runtime Dynamic Energy = 1.73796e-08 J + Total Runtime Energy = 1.73796e-08 J + + Mul Bypass Tag: + Area = 0.000249964 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 1.87211e-06 W + Runtime Dynamic Energy = 1.4483e-09 J + Total Runtime Energy = 1.4483e-09 J + + FP Bypass Data: + Area = 0.0055603 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.000171677 W + Runtime Dynamic Energy = 1.32813e-07 J + Total Runtime Energy = 1.32813e-07 J + + FP Bypass Tag: + Area = 0.000504686 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 1.55824e-05 W + Runtime Dynamic Energy = 1.20549e-08 J + Total Runtime Energy = 1.20549e-08 J + + Register File Unit: + Area = 0.0196435 mm^2 + Peak Dynamic Power = 0.0336789 W + Subthreshold Leakage Power = 0.000856795 W + Gate Leakage Power = 4.5652e-05 W + Runtime Dynamic Power = 0.00319189 W + Runtime Dynamic Energy = 2.46931e-06 J + Total Runtime Energy = 3.16747e-06 J + + Integer Register File: + Area = 0.00982177 mm^2 + Peak Dynamic Power = 0.0249332 W + Subthreshold Leakage Power = 0.000428398 W + Gate Leakage Power = 2.2826e-05 W + Runtime Dynamic Power = 0.00318155 W + Runtime Dynamic Energy = 2.46132e-06 J + Total Runtime Energy = 2.8104e-06 J + + FP Register File: + Area = 0.00982177 mm^2 + Peak Dynamic Power = 0.00874563 W + Subthreshold Leakage Power = 0.000428398 W + Gate Leakage Power = 2.2826e-05 W + Runtime Dynamic Power = 1.03325e-05 W + Runtime Dynamic Energy = 7.99349e-09 J + Total Runtime Energy = 3.5707e-07 J + + Integer ALU(s): + Area = 0.0694232 mm^2 + Peak Dynamic Power = 0.157715 W + Subthreshold Leakage Power = 0.0542072 W + Gate Leakage Power = 0.00427414 W + Runtime Dynamic Power = 0.0336539 W + Runtime Dynamic Energy = 2.60354e-05 J + Total Runtime Energy = 7.12779e-05 J + + Floating Point Unit(s): + Area = 1.8404 mm^2 + Peak Dynamic Power = 0.473146 W + Subthreshold Leakage Power = 0.359256 W + Gate Leakage Power = 0.0283266 W + Runtime Dynamic Power = 0.000504262 W + Runtime Dynamic Energy = 3.90109e-07 J + Total Runtime Energy = 0.000300233 J + + Multiply/Divide Unit(s): + Area = 0.20827 mm^2 + Peak Dynamic Power = 0.31543 W + Subthreshold Leakage Power = 0.162622 W + Gate Leakage Power = 0.0128224 W + Runtime Dynamic Power = 8.15463e-05 W + Runtime Dynamic Energy = 6.30861e-08 J + Total Runtime Energy = 0.000135791 J + + Undifferentiated Core: + Area = 1.09115 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.425999 W + Gate Leakage Power = 0.0335892 W + Runtime Dynamic Power = 0 W + Runtime Dynamic Energy = 0 J + Total Runtime Energy = 0.000355548 J + + Pipeline?: + Area = 0.0575486 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0253286 W + Gate Leakage Power = 0.00502589 W + Runtime Dynamic Power = 0.240578 W + Runtime Dynamic Energy = 0.000186116 J + Total Runtime Energy = 0.000209599 J + diff --git a/ext/mcpat/regression/test-5/power_region0.xml b/ext/mcpat/regression/test-5/power_region0.xml new file mode 100644 index 000000000..26c57ed29 --- /dev/null +++ b/ext/mcpat/regression/test-5/power_region0.xml @@ -0,0 +1,338 @@ +<?xml version="1.0" ?> +<component id="root" name="root"> + <component id="system" name="system" type="System"> + <param name="core_tech_node" value="40"/> + <param name="target_core_clockrate" value="1700"/> + <param name="temperature" value="380"/> + <param name="interconnect_projection_type" value="1"/> + <param name="device_type" value="0"/> + <param name="longer_channel_device" value="0"/> + <param name="machine_bits" value="64"/> + <param name="virtual_address_width" value="64"/> + <param name="physical_address_width" value="36"/> + <param name="virtual_memory_page_size" value="4096"/> + <param name="wire_is_mat_type" value="2"/> + <param name="wire_os_mat_type" value="2"/> + <param name="delay_wt" value="100"/> + <param name="area_wt" value="0"/> + <param name="dynamic_power_wt" value="100"/> + <param name="leakage_power_wt" value="0"/> + <param name="cycle_time_wt" value="0"/> + <param name="delay_dev" value="10000"/> + <param name="area_dev" value="10000"/> + <param name="dynamic_power_dev" value="10000"/> + <param name="leakage_power_dev" value="10000"/> + <param name="cycle_time_dev" value="10000"/> + <param name="ed" value="2"/> + <param name="burst_len" value="1"/> + <param name="int_prefetch_w" value="1"/> + <param name="page_sz_bits" value="0"/> + <param name="rpters_in_htree" value="1"/> + <param name="ver_htree_wires_over_array" value="0"/> + <param name="nuca" value="0"/> + <param name="nuca_bank_count" value="0"/> + <param name="force_cache_config" value="0"/> + <param name="wt" value="0"/> + <param name="force_wiretype" value="0"/> + <param name="print_detail" value="1"/> + <param name="add_ecc_b_" value="1"/> + <stat name="total_cycles" value="150"/> + <component id="system.core0" name="core0" type="Core"> + <param name="clock_rate" value="1700"/> + <param name="opt_local" value="0"/> + <param name="instruction_length" value="32"/> + <param name="opcode_width" value="8"/> + <param name="x86" value="1"/> + <param name="micro_opcode_width" value="8"/> + <param name="machine_type" value="0"/> + <param name="number_hardware_threads" value="2"/> + <param name="fetch_width" value="1"/> + <param name="number_instruction_fetch_ports" value="1"/> + <param name="decode_width" value="2"/> + <param name="issue_width" value="2"/> + <param name="peak_issue_width" value="2"/> + <param name="commit_width" value="2"/> + <param name="fp_issue_width" value="2"/> + <param name="prediction_width" value="1"/> + <param name="int_pipelines" value="2"/> + <param name="fp_pipelines" value="1"/> + <param name="int_pipeline_depth" value="12"/> + <param name="fp_pipeline_depth" value="13"/> + <param name="ALU_per_core" value="2"/> + <param name="MUL_per_core" value="1"/> + <param name="FPU_per_core" value="1"/> + <param name="instruction_buffer_size" value="16"/> + <param name="instruction_window_scheme" value="0"/> + <param name="instruction_window_size" value="7"/> + <param name="fp_instruction_window_size" value="18"/> + <param name="ROB_size" value="56"/> + <param name="archi_Regs_IRF_size" value="30"/> + <param name="archi_Regs_FRF_size" value="48"/> + <param name="phy_Regs_IRF_size" value="34"/> + <param name="phy_Regs_FRF_size" value="40"/> + <param name="rename_scheme" value="0"/> + <param name="register_window_size" value="0"/> + <param name="store_buffer_size" value="32"/> + <param name="load_buffer_size" value="22"/> + <param name="memory_ports" value="1"/> + <param name="RAS_size" value="16"/> + <param name="execu_wire_mat_type" value="2"/> + <param name="execu_bypass_base_width" value="1"/> + <param name="execu_bypass_base_height" value="1"/> + <param name="execu_bypass_start_wiring_level"value="3"/> + <param name="execu_bypass_route_over_perc" value="1"/> + <param name="globalCheckpoint" value="32"/> + <param name="perThreadState" value="8"/> + <param name="ROB_assoc" value="1"/> + <param name="ROB_nbanks" value="1"/> + <param name="ROB_tag_width" value="0"/> + <param name="scheduler_assoc" value="0"/> + <param name="scheduler_nbanks" value="1"/> + <param name="register_window_assoc" value="1"/> + <param name="register_window_nbanks" value="1"/> + <param name="register_window_tag_width" value="0"/> + <param name="register_window_rw_ports" value="1"/> + <param name="phy_Regs_IRF_assoc" value="1"/> + <param name="phy_Regs_IRF_nbanks" value="1"/> + <param name="phy_Regs_IRF_tag_width" value="0"/> + <param name="phy_Regs_IRF_rd_ports" value="1"/> + <param name="phy_Regs_IRF_wr_ports" value="1"/> + <param name="phy_Regs_FRF_assoc" value="1"/> + <param name="phy_Regs_FRF_nbanks" value="1"/> + <param name="phy_Regs_FRF_tag_width" value="0"/> + <param name="phy_Regs_FRF_rd_ports" value="1"/> + <param name="phy_Regs_FRF_wr_ports" value="1"/> + <param name="front_rat_nbanks" value="1"/> + <param name="front_rat_rw_ports" value="1"/> + <param name="retire_rat_nbanks" value="1"/> + <param name="retire_rat_rw_ports" value="0"/> + <param name="freelist_nbanks" value="1"/> + <param name="freelist_rw_ports" value="1"/> + <param name="load_buffer_assoc" value="0"/> + <param name="load_buffer_nbanks" value="1"/> + <param name="store_buffer_assoc" value="0"/> + <param name="store_buffer_nbanks" value="1"/> + <param name="instruction_buffer_assoc" value="1"/> + <param name="instruction_buffer_nbanks" value="1"/> + <param name="instruction_buffer_tag_width" value="0"/> + <stat name="total_instructions" value="100"/> + <stat name="int_instructions" value="50"/> + <stat name="fp_instructions" value="50"/> + <stat name="branch_instructions" value="20"/> + <stat name="branch_mispredictions" value="2"/> + <stat name="load_instructions" value="50"/> + <stat name="store_instructions" value="15"/> + <stat name="committed_instructions" value="100"/> + <stat name="committed_int_instructions" value="50"/> + <stat name="committed_fp_instructions" value="50"/> + <stat name="pipeline_duty_cycle" value="1"/> + <stat name="total_cycles" value="150"/> + <stat name="idle_cycles" value="30"/> + <stat name="busy_cycles" value="120"/> + <stat name="ROB_reads" value="100"/> + <stat name="ROB_writes" value="100"/> + <stat name="rename_reads" value="100"/> + <stat name="rename_writes" value="50"/> + <stat name="fp_rename_reads" value="100"/> + <stat name="fp_rename_writes" value="50"/> + <stat name="inst_window_reads" value="50"/> + <stat name="inst_window_writes" value="50"/> + <stat name="inst_window_wakeup_accesses" value="50"/> + <stat name="fp_inst_window_reads" value="50"/> + <stat name="fp_inst_window_writes" value="50"/> + <stat name="fp_inst_window_wakeup_accesses" value="50"/> + <stat name="int_regfile_reads" value="100"/> + <stat name="float_regfile_reads" value="100"/> + <stat name="int_regfile_writes" value="50"/> + <stat name="float_regfile_writes" value="50"/> + <stat name="function_calls" value="0"/> + <stat name="context_switches" value="0"/> + <stat name="ialu_accesses" value="15"/> + <stat name="fpu_accesses" value="15"/> + <stat name="mul_accesses" value="15"/> + <stat name="cdb_alu_accesses" value="15"/> + <stat name="cdb_mul_accesses" value="15"/> + <stat name="cdb_fpu_accesses" value="15"/> + <stat name="IFU_duty_cycle" value="1"/> + <stat name="LSU_duty_cycle" value="1"/> + <stat name="MemManU_I_duty_cycle" value="1"/> + <stat name="MemManU_D_duty_cycle" value="1"/> + <stat name="ALU_duty_cycle" value="1"/> + <stat name="MUL_duty_cycle" value="1"/> + <stat name="FPU_duty_cycle" value="1"/> + <stat name="ALU_cdb_duty_cycle" value="1"/> + <stat name="MUL_cdb_duty_cycle" value="1"/> + <stat name="FPU_cdb_duty_cycle" value="1"/> + <component id="system.core0.predictor" name="PBT" type="BranchPredictor"> + <param name="assoc" value="1"/> + <param name="nbanks" value="1"/> + <param name="local_l1_predictor_size" value="12"/> + <param name="local_l2_predictor_size" value="4"/> + <param name="local_predictor_entries" value="8192"/> + <param name="global_predictor_entries" value="8192"/> + <param name="global_predictor_bits" value="4"/> + <param name="chooser_predictor_entries" value="8192"/> + <param name="chooser_predictor_bits" value="4"/> + </component> + <component id="system.core0.itlb" name="itlb" type="InstructionTLB"> + <param name="number_entries" value="512"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="total_accesses" value="50"/> + <stat name="total_misses" value="3"/> + <stat name="conflicts" value="3"/> + </component> + <component id="system.core0.icache" name="Instruction Cache" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="0"/> + <param name="device_type" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="read_accesses" value="50"/> + <stat name="read_misses" value="12"/> + <stat name="conflicts" value="1"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.core0.dtlb" name="dtlb" type="DataTLB"> + <param name="number_entries" value="512"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="read_accesses" value="65"/> + <stat name="read_misses" value="1"/> + <stat name="conflicts" value="1"/> + </component> + <component id="system.core0.dcache" name="Data Cache" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="8"/> + <param name="num_banks" value="1"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="miss_buffer_size" value="8"/> + <param name="fetch_buffer_size" value="8"/> + <param name="prefetch_buffer_size" value="8"/> + <param name="writeback_buffer_size" value="8"/> + <param name="device_type" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="read_accesses" value="50"/> + <stat name="write_accesses" value="15"/> + <stat name="read_misses" value="12"/> + <stat name="write_misses" value="3"/> + <stat name="conflicts" value="1"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.core0.btargetbuf" name="btargetbuf" type="BranchTargetBuffer"> + <param name="size" value="8192"/> + <param name="block_size" value="4"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="1"/> + <param name="throughput" value="3"/> + <param name="rw_ports" value="1"/> + <stat name="read_accesses" value="20"/> + <stat name="write_accesses" value="20"/> + </component> + </component> + </component> +</component> diff --git a/ext/mcpat/regression/test-5/region0.out.ref b/ext/mcpat/regression/test-5/region0.out.ref new file mode 100644 index 000000000..bbaa937ab --- /dev/null +++ b/ext/mcpat/regression/test-5/region0.out.ref @@ -0,0 +1,541 @@ +McPAT (version 0.8 of Aug, 2010) is computing the target processor... + + +McPAT (version 0.8 of Aug, 2010) results (current print level is 5) +***************************************************************************************** + Technology 40 nm + Interconnect metal projection = conservative interconnect technology projection + Target Clock Rate (MHz) 1700 + +***************************************************************************************** + System: + Area = 10.8081 mm^2 + Peak Dynamic Power = 2.45616 W + Subthreshold Leakage Power = 4.64481 W + Gate Leakage Power = 0.193831 W + Runtime Dynamic Power = 1.32073 W + Runtime Dynamic Energy = 1.16535e-07 J + Total Runtime Energy = 5.43474e-07 J + + Core 0: + Area = 10.8081 mm^2 + Peak Dynamic Power = 2.45616 W + Subthreshold Leakage Power = 4.64481 W + Gate Leakage Power = 0.193831 W + Runtime Dynamic Power = 1.32073 W + Runtime Dynamic Energy = 1.16535e-07 J + Total Runtime Energy = 5.43474e-07 J + + Instruction Fetch Unit: + Area = 2.10081 mm^2 + Peak Dynamic Power = 0.33569 W + Subthreshold Leakage Power = 0.347428 W + Gate Leakage Power = 0.00868165 W + Runtime Dynamic Power = 0.213414 W + Runtime Dynamic Energy = 1.88306e-08 J + Total Runtime Energy = 5.0252e-08 J + + Instruction Cache: + Area = 0.970326 mm^2 + Peak Dynamic Power = 0.0549304 W + Subthreshold Leakage Power = 0.0678485 W + Gate Leakage Power = 0.00157419 W + Runtime Dynamic Power = 0.0505595 W + Runtime Dynamic Energy = 4.46113e-09 J + Total Runtime Energy = 1.05867e-08 J + + Data and Tag Arrays: + Area = 0.25887 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0622886 W + Gate Leakage Power = 0.00129234 W + Runtime Dynamic Power = 0.0464002 W + Runtime Dynamic Energy = 4.09413e-09 J + Total Runtime Energy = 9.70422e-09 J + + Miss Buffer: + Area = 0.262959 mm^2 + Peak Dynamic Power = 0.0192867 W + Subthreshold Leakage Power = 0.00194663 W + Gate Leakage Power = 9.86469e-05 W + Runtime Dynamic Power = 0.00146456 W + Runtime Dynamic Energy = 1.29226e-10 J + Total Runtime Energy = 3.09692e-10 J + + Fill Buffer: + Area = 0.224249 mm^2 + Peak Dynamic Power = 0.0178218 W + Subthreshold Leakage Power = 0.00180662 W + Gate Leakage Power = 9.16038e-05 W + Runtime Dynamic Power = 0.00134737 W + Runtime Dynamic Energy = 1.18886e-10 J + Total Runtime Energy = 2.86376e-10 J + + Prefetch Buffer: + Area = 0.224249 mm^2 + Peak Dynamic Power = 0.0178218 W + Subthreshold Leakage Power = 0.00180662 W + Gate Leakage Power = 9.16038e-05 W + Runtime Dynamic Power = 0.00134737 W + Runtime Dynamic Energy = 1.18886e-10 J + Total Runtime Energy = 2.86376e-10 J + + Branch Target Buffer: + Area = 0.526552 mm^2 + Peak Dynamic Power = 0.0433889 W + Subthreshold Leakage Power = 0.0869885 W + Gate Leakage Power = 0.00266245 W + Runtime Dynamic Power = 0.0189877 W + Runtime Dynamic Energy = 1.67538e-09 J + Total Runtime Energy = 9.58576e-09 J + + Branch Predictor: + Area = 0.594319 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.186556 W + Gate Leakage Power = 0.00424723 W + Runtime Dynamic Power = 0.0647432 W + Runtime Dynamic Energy = 5.71264e-09 J + Total Runtime Energy = 2.25483e-08 J + + Global Predictor: + Area = 0.129022 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0419609 W + Gate Leakage Power = 0.000962899 W + Runtime Dynamic Power = 0.0172467 W + Runtime Dynamic Energy = 1.52177e-09 J + Total Runtime Energy = 5.30916e-09 J + + Local Predictor, Level 1: + Area = 0.191924 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0589594 W + Gate Leakage Power = 0.00130932 W + Runtime Dynamic Power = 0.0255552 W + Runtime Dynamic Energy = 2.25487e-09 J + Total Runtime Energy = 7.5727e-09 J + + Local Predictor, Level 2: + Area = 0.129022 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0419609 W + Gate Leakage Power = 0.000962899 W + Runtime Dynamic Power = 0.0046946 W + Runtime Dynamic Energy = 4.1423e-10 J + Total Runtime Energy = 4.20162e-09 J + + Predictor Chooser: + Area = 0.129022 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0419609 W + Gate Leakage Power = 0.000962899 W + Runtime Dynamic Power = 0.0172467 W + Runtime Dynamic Energy = 1.52177e-09 J + Total Runtime Energy = 5.30916e-09 J + + RAS: + Area = 0.0153301 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0017144 W + Gate Leakage Power = 4.92127e-05 W + Runtime Dynamic Power = 0 W + Runtime Dynamic Energy = 0 J + Total Runtime Energy = 1.55613e-10 J + + Instruction Buffer: + Area = 0.0034347 mm^2 + Peak Dynamic Power = 0.011729 W + Subthreshold Leakage Power = 0.000650517 W + Gate Leakage Power = 1.85414e-05 W + Runtime Dynamic Power = 0.00390968 W + Runtime Dynamic Energy = 3.44972e-10 J + Total Runtime Energy = 4.04006e-10 J + + Instruction Opcode Decoder: + Area = 0.00289896 mm^2 + Peak Dynamic Power = 0.0752588 W + Subthreshold Leakage Power = 0.00253168 W + Gate Leakage Power = 8.37387e-05 W + Runtime Dynamic Power = 0.0250863 W + Runtime Dynamic Energy = 2.2135e-09 J + Total Runtime Energy = 2.44427e-09 J + + Instruction Operand Decoder: + Area = 0.000377341 mm^2 + Peak Dynamic Power = 0.0751236 W + Subthreshold Leakage Power = 0.00032028 W + Gate Leakage Power = 1.17596e-05 W + Runtime Dynamic Power = 0.0250412 W + Runtime Dynamic Energy = 2.20952e-09 J + Total Runtime Energy = 2.23881e-09 J + + Instruction Microcode Decoder: + Area = 0.00289896 mm^2 + Peak Dynamic Power = 0.0752588 W + Subthreshold Leakage Power = 0.00253168 W + Gate Leakage Power = 8.37387e-05 W + Runtime Dynamic Power = 0.0250863 W + Runtime Dynamic Energy = 2.2135e-09 J + Total Runtime Energy = 2.44427e-09 J + + Load/Store Unit: + Area = 1.69899 mm^2 + Peak Dynamic Power = 0.16674 W + Subthreshold Leakage Power = 0.0926715 W + Gate Leakage Power = 0.00259372 W + Runtime Dynamic Power = 0.142557 W + Runtime Dynamic Energy = 1.25786e-08 J + Total Runtime Energy = 2.09843e-08 J + + Data Cache: + Area = 1.58391 mm^2 + Peak Dynamic Power = 0.0928926 W + Subthreshold Leakage Power = 0.0789233 W + Gate Leakage Power = 0.00207502 W + Runtime Dynamic Power = 0.0922726 W + Runtime Dynamic Energy = 8.1417e-09 J + Total Runtime Energy = 1.52886e-08 J + + Data and Tag Arrays: + Area = 0.619642 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0607406 W + Gate Leakage Power = 0.00122316 W + Runtime Dynamic Power = 0.0861866 W + Runtime Dynamic Energy = 7.6047e-09 J + Total Runtime Energy = 1.30721e-08 J + + Miss Buffer: + Area = 0.270528 mm^2 + Peak Dynamic Power = 0.0245073 W + Subthreshold Leakage Power = 0.0048041 W + Gate Leakage Power = 0.000224896 W + Runtime Dynamic Power = 0.00214283 W + Runtime Dynamic Energy = 1.89073e-10 J + Total Runtime Energy = 6.32808e-10 J + + Fill Buffer: + Area = 0.231248 mm^2 + Peak Dynamic Power = 0.0227951 W + Subthreshold Leakage Power = 0.00445956 W + Gate Leakage Power = 0.000208987 W + Runtime Dynamic Power = 0.00197161 W + Runtime Dynamic Energy = 1.73965e-10 J + Total Runtime Energy = 5.85896e-10 J + + Prefetch Buffer: + Area = 0.231248 mm^2 + Peak Dynamic Power = 0.0227951 W + Subthreshold Leakage Power = 0.00445956 W + Gate Leakage Power = 0.000208987 W + Runtime Dynamic Power = 0.00157729 W + Runtime Dynamic Energy = 1.39172e-10 J + Total Runtime Energy = 5.51103e-10 J + + Writeback Buffer: + Area = 0.231248 mm^2 + Peak Dynamic Power = 0.0227951 W + Subthreshold Leakage Power = 0.00445956 W + Gate Leakage Power = 0.000208987 W + Runtime Dynamic Power = 0.000394322 W + Runtime Dynamic Energy = 3.47931e-11 J + Total Runtime Energy = 4.46724e-10 J + + Load Queue: + Area = 0.054217 mm^2 + Peak Dynamic Power = 0.0316525 W + Subthreshold Leakage Power = 0.00559768 W + Gate Leakage Power = 0.00022125 W + Runtime Dynamic Power = 0.0137161 W + Runtime Dynamic Energy = 1.21024e-09 J + Total Runtime Energy = 1.72368e-09 J + + Store Queue: + Area = 0.0608565 mm^2 + Peak Dynamic Power = 0.0421944 W + Subthreshold Leakage Power = 0.00815046 W + Gate Leakage Power = 0.000297452 W + Runtime Dynamic Power = 0.0365685 W + Runtime Dynamic Energy = 3.22663e-09 J + Total Runtime Energy = 3.97204e-09 J + + Memory Management Unit: + Area = 0.331371 mm^2 + Peak Dynamic Power = 0.318513 W + Subthreshold Leakage Power = 0.097099 W + Gate Leakage Power = 0.00441089 W + Runtime Dynamic Power = 0.123948 W + Runtime Dynamic Energy = 1.09366e-08 J + Total Runtime Energy = 1.98933e-08 J + + Instruction TLB: + Area = 0.131789 mm^2 + Peak Dynamic Power = 0.151159 W + Subthreshold Leakage Power = 0.0446376 W + Gate Leakage Power = 0.00203139 W + Runtime Dynamic Power = 0.0511229 W + Runtime Dynamic Energy = 4.51085e-09 J + Total Runtime Energy = 8.62869e-09 J + + Data TLB: + Area = 0.199582 mm^2 + Peak Dynamic Power = 0.167354 W + Subthreshold Leakage Power = 0.0524614 W + Gate Leakage Power = 0.00237949 W + Runtime Dynamic Power = 0.072825 W + Runtime Dynamic Energy = 6.42574e-09 J + Total Runtime Energy = 1.12646e-08 J + + Execution Unit: + Area = 2.36584 mm^2 + Peak Dynamic Power = 1.52633 W + Subthreshold Leakage Power = 1.18035 W + Gate Leakage Power = 0.0498689 W + Runtime Dynamic Power = 0.517033 W + Runtime Dynamic Energy = 4.56205e-08 J + Total Runtime Energy = 1.5417e-07 J + + Int Bypass Data: + Area = 0.0024813 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00618474 W + Runtime Dynamic Energy = 5.45712e-10 J + Total Runtime Energy = 5.45712e-10 J + + Int Bypass Tag: + Area = 0.000291384 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.000726287 W + Runtime Dynamic Energy = 6.40842e-11 J + Total Runtime Energy = 6.40842e-11 J + + Mul Bypass Data: + Area = 0.00328459 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00818697 W + Runtime Dynamic Energy = 7.2238e-10 J + Total Runtime Energy = 7.2238e-10 J + + Mul Bypass Tag: + Area = 0.000366693 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.000913997 W + Runtime Dynamic Energy = 8.06468e-11 J + Total Runtime Energy = 8.06468e-11 J + + FP Bypass Data: + Area = 0.0039374 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00981414 W + Runtime Dynamic Energy = 8.65954e-10 J + Total Runtime Energy = 8.65954e-10 J + + FP Bypass Tag: + Area = 0.000508858 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00126835 W + Runtime Dynamic Energy = 1.11913e-10 J + Total Runtime Energy = 1.11913e-10 J + + Register File Unit: + Area = 0.0603417 mm^2 + Peak Dynamic Power = 0.094149 W + Subthreshold Leakage Power = 0.00361325 W + Gate Leakage Power = 0.000100838 W + Runtime Dynamic Power = 0.00713589 W + Runtime Dynamic Energy = 6.29638e-10 J + Total Runtime Energy = 9.57351e-10 J + + Integer Register File: + Area = 0.0397387 mm^2 + Peak Dynamic Power = 0.0858804 W + Subthreshold Leakage Power = 0.00167327 W + Gate Leakage Power = 4.73072e-05 W + Runtime Dynamic Power = 0.00340795 W + Runtime Dynamic Energy = 3.00702e-10 J + Total Runtime Energy = 4.52517e-10 J + + FP Register File: + Area = 0.020603 mm^2 + Peak Dynamic Power = 0.00826856 W + Subthreshold Leakage Power = 0.00193998 W + Gate Leakage Power = 5.35312e-05 W + Runtime Dynamic Power = 0.00372794 W + Runtime Dynamic Energy = 3.28936e-10 J + Total Runtime Energy = 5.04834e-10 J + + Instruction Scheduler: + Area = 0.107117 mm^2 + Peak Dynamic Power = 0.107009 W + Subthreshold Leakage Power = 0.00250283 W + Gate Leakage Power = 7.07223e-05 W + Runtime Dynamic Power = 0.0155966 W + Runtime Dynamic Energy = 1.37617e-09 J + Total Runtime Energy = 1.60325e-09 J + + Integer Instruction Window: + Area = 0.0261741 mm^2 + Peak Dynamic Power = 0.0268581 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00223817 W + Runtime Dynamic Energy = 1.97486e-10 J + Total Runtime Energy = 1.97486e-10 J + + FP Instruction Window: + Area = 0.0232716 mm^2 + Peak Dynamic Power = 0.0133785 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00222975 W + Runtime Dynamic Energy = 1.96742e-10 J + Total Runtime Energy = 1.96742e-10 J + + Reorder Buffer: + Area = 0.0576711 mm^2 + Peak Dynamic Power = 0.066772 W + Subthreshold Leakage Power = 0.00250283 W + Gate Leakage Power = 7.07223e-05 W + Runtime Dynamic Power = 0.0111287 W + Runtime Dynamic Energy = 9.81941e-10 J + Total Runtime Energy = 1.20902e-09 J + + Integer ALU(s): + Area = 0.138846 mm^2 + Peak Dynamic Power = 0.332578 W + Subthreshold Leakage Power = 0.201977 W + Gate Leakage Power = 0.00854828 W + Runtime Dynamic Power = 0.0778676 W + Runtime Dynamic Energy = 6.87067e-09 J + Total Runtime Energy = 2.54464e-08 J + + Floating Point Unit(s): + Area = 1.8404 mm^2 + Peak Dynamic Power = 0.595559 W + Subthreshold Leakage Power = 0.669296 W + Gate Leakage Power = 0.0283266 W + Runtime Dynamic Power = 0.233603 W + Runtime Dynamic Energy = 2.0612e-08 J + Total Runtime Energy = 8.21669e-08 J + + Multiply/Divide Unit(s): + Area = 0.20827 mm^2 + Peak Dynamic Power = 0.39704 W + Subthreshold Leakage Power = 0.302965 W + Gate Leakage Power = 0.0128224 W + Runtime Dynamic Power = 0.155735 W + Runtime Dynamic Energy = 1.37413e-08 J + Total Runtime Energy = 4.1605e-08 J + + Undifferentiated Core: + Area = 3.88668 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 2.82694 W + Gate Leakage Power = 0.119645 W + Runtime Dynamic Power = 0 W + Runtime Dynamic Energy = 0 J + Total Runtime Energy = 2.59992e-07 J + + Rename Unit: + Area = 0.333151 mm^2 + Peak Dynamic Power = 0.10888 W + Subthreshold Leakage Power = 0.0255114 W + Gate Leakage Power = 0.000663381 W + Runtime Dynamic Power = 0.0538848 W + Runtime Dynamic Energy = 4.75454e-09 J + Total Runtime Energy = 7.06408e-09 J + + Int Front RAT: + Area = 0.129348 mm^2 + Peak Dynamic Power = 0.0382386 W + Subthreshold Leakage Power = 0.00828989 W + Gate Leakage Power = 0.000204367 W + Runtime Dynamic Power = 0.0063731 W + Runtime Dynamic Energy = 5.62332e-10 J + Total Runtime Energy = 1.31183e-09 J + + FP Front RAT: + Area = 0.166163 mm^2 + Peak Dynamic Power = 0.0432953 W + Subthreshold Leakage Power = 0.0126995 W + Gate Leakage Power = 0.000319816 W + Runtime Dynamic Power = 0.00721588 W + Runtime Dynamic Energy = 6.36696e-10 J + Total Runtime Energy = 1.78546e-09 J + + Integer Free List: + Area = 0.0120305 mm^2 + Peak Dynamic Power = 0.00394808 W + Subthreshold Leakage Power = 0.000639181 W + Gate Leakage Power = 2.0232e-05 W + Runtime Dynamic Power = 0.00131603 W + Runtime Dynamic Energy = 1.1612e-10 J + Total Runtime Energy = 1.74304e-10 J + + Int Retire RAT: + Area = 0.00606308 mm^2 + Peak Dynamic Power = 0.00325948 W + Subthreshold Leakage Power = 0.000496413 W + Gate Leakage Power = 1.45535e-05 W + Runtime Dynamic Power = 0.000543246 W + Runtime Dynamic Energy = 4.79335e-11 J + Total Runtime Energy = 9.30188e-11 J + + FP Retire RAT: + Area = 0.00751656 mm^2 + Peak Dynamic Power = 0.00404193 W + Subthreshold Leakage Power = 0.000709488 W + Gate Leakage Power = 1.94961e-05 W + Runtime Dynamic Power = 0.000673654 W + Runtime Dynamic Energy = 5.94401e-11 J + Total Runtime Energy = 1.23762e-10 J + + FP Free List: + Area = 0.0120305 mm^2 + Peak Dynamic Power = 0.00394808 W + Subthreshold Leakage Power = 0.000639181 W + Gate Leakage Power = 2.0232e-05 W + Runtime Dynamic Power = 0.00131603 W + Runtime Dynamic Energy = 1.1612e-10 J + Total Runtime Energy = 1.74304e-10 J + + Instruction Dependency Check?: + Area = 0 mm^2 + Peak Dynamic Power = 0.00607447 W + Subthreshold Leakage Power = 0.00101891 W + Gate Leakage Power = 3.23427e-05 W + Runtime Dynamic Power = 0.0242979 W + Runtime Dynamic Energy = 2.14393e-09 J + Total Runtime Energy = 2.23669e-09 J + + FP Dependency Check?: + Area = 0 mm^2 + Peak Dynamic Power = 0.00607447 W + Subthreshold Leakage Power = 0.00101891 W + Gate Leakage Power = 3.23427e-05 W + Runtime Dynamic Power = 0.0121489 W + Runtime Dynamic Energy = 1.07197e-09 J + Total Runtime Energy = 1.16472e-09 J + + Pipeline?: + Area = 0.0912321 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0748063 W + Gate Leakage Power = 0.00796757 W + Runtime Dynamic Power = 0.269895 W + Runtime Dynamic Energy = 2.38143e-08 J + Total Runtime Energy = 3.11178e-08 J + diff --git a/ext/mcpat/regression/test-6/power_region0.xml b/ext/mcpat/regression/test-6/power_region0.xml new file mode 100644 index 000000000..9b21cdd72 --- /dev/null +++ b/ext/mcpat/regression/test-6/power_region0.xml @@ -0,0 +1,401 @@ +<?xml version="1.0" ?> +<component id="root" name="root"> + <component id="system" name="system" type="System"> + <param name="core_tech_node" value="40"/> + <param name="target_core_clockrate" value="1700"/> + <param name="temperature" value="380"/> + <param name="interconnect_projection_type" value="1"/> + <param name="device_type" value="0"/> + <param name="longer_channel_device" value="0"/> + <param name="machine_bits" value="64"/> + <param name="virtual_address_width" value="64"/> + <param name="physical_address_width" value="36"/> + <param name="virtual_memory_page_size" value="4096"/> + <param name="wire_is_mat_type" value="2"/> + <param name="wire_os_mat_type" value="2"/> + <param name="delay_wt" value="100"/> + <param name="area_wt" value="0"/> + <param name="dynamic_power_wt" value="100"/> + <param name="leakage_power_wt" value="0"/> + <param name="cycle_time_wt" value="0"/> + <param name="delay_dev" value="10000"/> + <param name="area_dev" value="10000"/> + <param name="dynamic_power_dev" value="10000"/> + <param name="leakage_power_dev" value="10000"/> + <param name="cycle_time_dev" value="10000"/> + <param name="ed" value="2"/> + <param name="burst_len" value="1"/> + <param name="int_prefetch_w" value="1"/> + <param name="page_sz_bits" value="0"/> + <param name="rpters_in_htree" value="1"/> + <param name="ver_htree_wires_over_array" value="0"/> + <param name="nuca" value="0"/> + <param name="nuca_bank_count" value="0"/> + <param name="force_cache_config" value="0"/> + <param name="wt" value="0"/> + <param name="force_wiretype" value="0"/> + <param name="print_detail" value="1"/> + <param name="add_ecc_b_" value="1"/> + <stat name="total_cycles" value="150"/> + <component id="system.core0" name="core0" type="Core"> + <param name="clock_rate" value="1700"/> + <param name="opt_local" value="0"/> + <param name="instruction_length" value="32"/> + <param name="opcode_width" value="8"/> + <param name="x86" value="1"/> + <param name="micro_opcode_width" value="8"/> + <param name="machine_type" value="0"/> + <param name="number_hardware_threads" value="2"/> + <param name="fetch_width" value="1"/> + <param name="number_instruction_fetch_ports" value="1"/> + <param name="decode_width" value="2"/> + <param name="issue_width" value="2"/> + <param name="peak_issue_width" value="2"/> + <param name="commit_width" value="2"/> + <param name="fp_issue_width" value="2"/> + <param name="prediction_width" value="1"/> + <param name="int_pipelines" value="2"/> + <param name="fp_pipelines" value="1"/> + <param name="int_pipeline_depth" value="12"/> + <param name="fp_pipeline_depth" value="13"/> + <param name="ALU_per_core" value="2"/> + <param name="MUL_per_core" value="1"/> + <param name="FPU_per_core" value="1"/> + <param name="instruction_buffer_size" value="16"/> + <param name="instruction_window_scheme" value="0"/> + <param name="instruction_window_size" value="7"/> + <param name="fp_instruction_window_size" value="18"/> + <param name="ROB_size" value="56"/> + <param name="archi_Regs_IRF_size" value="30"/> + <param name="archi_Regs_FRF_size" value="48"/> + <param name="phy_Regs_IRF_size" value="34"/> + <param name="phy_Regs_FRF_size" value="40"/> + <param name="rename_scheme" value="0"/> + <param name="register_window_size" value="0"/> + <param name="store_buffer_size" value="32"/> + <param name="load_buffer_size" value="22"/> + <param name="memory_ports" value="1"/> + <param name="RAS_size" value="16"/> + <param name="execu_wire_mat_type" value="2"/> + <param name="execu_bypass_base_width" value="1"/> + <param name="execu_bypass_base_height" value="1"/> + <param name="execu_bypass_start_wiring_level"value="3"/> + <param name="execu_bypass_route_over_perc" value="1"/> + <param name="globalCheckpoint" value="32"/> + <param name="perThreadState" value="8"/> + <param name="ROB_assoc" value="1"/> + <param name="ROB_nbanks" value="1"/> + <param name="ROB_tag_width" value="0"/> + <param name="scheduler_assoc" value="0"/> + <param name="scheduler_nbanks" value="1"/> + <param name="register_window_assoc" value="1"/> + <param name="register_window_nbanks" value="1"/> + <param name="register_window_tag_width" value="0"/> + <param name="register_window_rw_ports" value="1"/> + <param name="phy_Regs_IRF_assoc" value="1"/> + <param name="phy_Regs_IRF_nbanks" value="1"/> + <param name="phy_Regs_IRF_tag_width" value="0"/> + <param name="phy_Regs_IRF_rd_ports" value="1"/> + <param name="phy_Regs_IRF_wr_ports" value="1"/> + <param name="phy_Regs_FRF_assoc" value="1"/> + <param name="phy_Regs_FRF_nbanks" value="1"/> + <param name="phy_Regs_FRF_tag_width" value="0"/> + <param name="phy_Regs_FRF_rd_ports" value="1"/> + <param name="phy_Regs_FRF_wr_ports" value="1"/> + <param name="front_rat_nbanks" value="1"/> + <param name="front_rat_rw_ports" value="1"/> + <param name="retire_rat_nbanks" value="1"/> + <param name="retire_rat_rw_ports" value="0"/> + <param name="freelist_nbanks" value="1"/> + <param name="freelist_rw_ports" value="1"/> + <param name="load_buffer_assoc" value="0"/> + <param name="load_buffer_nbanks" value="1"/> + <param name="store_buffer_assoc" value="0"/> + <param name="store_buffer_nbanks" value="1"/> + <param name="instruction_buffer_assoc" value="1"/> + <param name="instruction_buffer_nbanks" value="1"/> + <param name="instruction_buffer_tag_width" value="0"/> + <stat name="total_instructions" value="100"/> + <stat name="int_instructions" value="50"/> + <stat name="fp_instructions" value="50"/> + <stat name="branch_instructions" value="20"/> + <stat name="branch_mispredictions" value="2"/> + <stat name="load_instructions" value="50"/> + <stat name="store_instructions" value="15"/> + <stat name="committed_instructions" value="100"/> + <stat name="committed_int_instructions" value="50"/> + <stat name="committed_fp_instructions" value="50"/> + <stat name="pipeline_duty_cycle" value="1"/> + <stat name="total_cycles" value="150"/> + <stat name="idle_cycles" value="30"/> + <stat name="busy_cycles" value="120"/> + <stat name="ROB_reads" value="100"/> + <stat name="ROB_writes" value="100"/> + <stat name="rename_reads" value="100"/> + <stat name="rename_writes" value="50"/> + <stat name="fp_rename_reads" value="100"/> + <stat name="fp_rename_writes" value="50"/> + <stat name="inst_window_reads" value="50"/> + <stat name="inst_window_writes" value="50"/> + <stat name="inst_window_wakeup_accesses" value="50"/> + <stat name="fp_inst_window_reads" value="50"/> + <stat name="fp_inst_window_writes" value="50"/> + <stat name="fp_inst_window_wakeup_accesses" value="50"/> + <stat name="int_regfile_reads" value="100"/> + <stat name="float_regfile_reads" value="100"/> + <stat name="int_regfile_writes" value="50"/> + <stat name="float_regfile_writes" value="50"/> + <stat name="function_calls" value="5"/> + <stat name="context_switches" value="0"/> + <stat name="ialu_accesses" value="15"/> + <stat name="fpu_accesses" value="15"/> + <stat name="mul_accesses" value="15"/> + <stat name="cdb_alu_accesses" value="15"/> + <stat name="cdb_mul_accesses" value="15"/> + <stat name="cdb_fpu_accesses" value="15"/> + <stat name="IFU_duty_cycle" value="1"/> + <stat name="LSU_duty_cycle" value="1"/> + <stat name="MemManU_I_duty_cycle" value="1"/> + <stat name="MemManU_D_duty_cycle" value="1"/> + <stat name="ALU_duty_cycle" value="1"/> + <stat name="MUL_duty_cycle" value="1"/> + <stat name="FPU_duty_cycle" value="1"/> + <stat name="ALU_cdb_duty_cycle" value="1"/> + <stat name="MUL_cdb_duty_cycle" value="1"/> + <stat name="FPU_cdb_duty_cycle" value="1"/> + <component id="system.core0.predictor" name="PBT" type="BranchPredictor"> + <param name="assoc" value="1"/> + <param name="nbanks" value="1"/> + <param name="local_l1_predictor_size" value="12"/> + <param name="local_l2_predictor_size" value="4"/> + <param name="local_predictor_entries" value="8192"/> + <param name="global_predictor_entries" value="8192"/> + <param name="global_predictor_bits" value="4"/> + <param name="chooser_predictor_entries" value="8192"/> + <param name="chooser_predictor_bits" value="4"/> + </component> + <component id="system.core0.itlb" name="itlb" type="InstructionTLB"> + <param name="number_entries" value="512"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="total_accesses" value="50"/> + <stat name="total_misses" value="10"/> + <stat name="conflicts" value="10"/> + </component> + <component id="system.core0.icache" name="Instruction Cache" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="read_accesses" value="50"/> + <stat name="read_misses" value="12"/> + <stat name="conflicts" value="1"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.core0.dtlb" name="dtlb" type="DataTLB"> + <param name="number_entries" value="512"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="read_accesses" value="65"/> + <stat name="read_misses" value="40"/> + <stat name="conflicts" value="40"/> + </component> + <component id="system.core0.dcache" name="Data Cache" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="8"/> + <param name="num_banks" value="1"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="miss_buffer_size" value="8"/> + <param name="fetch_buffer_size" value="8"/> + <param name="prefetch_buffer_size" value="8"/> + <param name="writeback_buffer_size" value="8"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="read_accesses" value="50"/> + <stat name="write_accesses" value="15"/> + <stat name="read_misses" value="12"/> + <stat name="write_misses" value="3"/> + <stat name="conflicts" value="1"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.core0.btargetbuf" name="btargetbuf" type="BranchTargetBuffer"> + <param name="size" value="8192"/> + <param name="block_size" value="4"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="1"/> + <param name="throughput" value="3"/> + <param name="rw_ports" value="1"/> + <stat name="read_accesses" value="20"/> + <stat name="write_accesses" value="20"/> + </component> + </component> + <component id="system.L20" name="L2 Cache" type="CacheUnit"> + <param name="level" value="2"/> + <param name="size" value="524288"/> + <param name="block_size" value="64"/> + <param name="assoc" value="16"/> + <param name="num_banks" value="1"/> + <param name="latency" value="8"/> + <param name="throughput" value="23"/> + <param name="miss_buffer_size" value="16"/> + <param name="fetch_buffer_size" value="16"/> + <param name="prefetch_buffer_size" value="16"/> + <param name="writeback_buffer_size" value="16"/> + <param name="clockrate" value="1700"/> + <param name="device_type" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="1"/> + <param name="miss_buff_access_mode" value="0"/> + <param name="fetch_buff_access_mode" value="0"/> + <param name="prefetch_buff_access_mode" value="0"/> + <param name="writeback_buff_access_mode"value="0"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="read_accesses" value="52"/> + <stat name="write_accesses" value="3"/> + <stat name="read_misses" value="35"/> + <stat name="write_misses" value="3"/> + <stat name="conflicts" value="38"/> + <stat name="duty_cycle" value="1.0"/> + </component> + </component> +</component> diff --git a/ext/mcpat/regression/test-6/region0.out.ref b/ext/mcpat/regression/test-6/region0.out.ref new file mode 100644 index 000000000..0970fb8ae --- /dev/null +++ b/ext/mcpat/regression/test-6/region0.out.ref @@ -0,0 +1,595 @@ +McPAT (version 0.8 of Aug, 2010) is computing the target processor... + + +McPAT (version 0.8 of Aug, 2010) results (current print level is 5) +***************************************************************************************** + Technology 40 nm + Interconnect metal projection = conservative interconnect technology projection + Target Clock Rate (MHz) 1700 + +***************************************************************************************** + System: + Area = 15.1334 mm^2 + Peak Dynamic Power = 2.57757 W + Subthreshold Leakage Power = 5.86045 W + Gate Leakage Power = 0.233087 W + Runtime Dynamic Power = 1.94298 W + Runtime Dynamic Energy = 1.71439e-07 J + Total Runtime Energy = 7.09105e-07 J + + Core 0: + Area = 10.8081 mm^2 + Peak Dynamic Power = 2.45616 W + Subthreshold Leakage Power = 4.64481 W + Gate Leakage Power = 0.193831 W + Runtime Dynamic Power = 1.33452 W + Runtime Dynamic Energy = 1.17752e-07 J + Total Runtime Energy = 5.44691e-07 J + + Instruction Fetch Unit: + Area = 2.10081 mm^2 + Peak Dynamic Power = 0.33569 W + Subthreshold Leakage Power = 0.347428 W + Gate Leakage Power = 0.00868165 W + Runtime Dynamic Power = 0.213589 W + Runtime Dynamic Energy = 1.88461e-08 J + Total Runtime Energy = 5.02675e-08 J + + Instruction Cache: + Area = 0.970326 mm^2 + Peak Dynamic Power = 0.0549304 W + Subthreshold Leakage Power = 0.0678485 W + Gate Leakage Power = 0.00157419 W + Runtime Dynamic Power = 0.0505595 W + Runtime Dynamic Energy = 4.46113e-09 J + Total Runtime Energy = 1.05867e-08 J + + Data and Tag Arrays: + Area = 0.25887 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0622886 W + Gate Leakage Power = 0.00129234 W + Runtime Dynamic Power = 0.0464002 W + Runtime Dynamic Energy = 4.09413e-09 J + Total Runtime Energy = 9.70422e-09 J + + Miss Buffer: + Area = 0.262959 mm^2 + Peak Dynamic Power = 0.0192867 W + Subthreshold Leakage Power = 0.00194663 W + Gate Leakage Power = 9.86469e-05 W + Runtime Dynamic Power = 0.00146456 W + Runtime Dynamic Energy = 1.29226e-10 J + Total Runtime Energy = 3.09692e-10 J + + Fill Buffer: + Area = 0.224249 mm^2 + Peak Dynamic Power = 0.0178218 W + Subthreshold Leakage Power = 0.00180662 W + Gate Leakage Power = 9.16038e-05 W + Runtime Dynamic Power = 0.00134737 W + Runtime Dynamic Energy = 1.18886e-10 J + Total Runtime Energy = 2.86376e-10 J + + Prefetch Buffer: + Area = 0.224249 mm^2 + Peak Dynamic Power = 0.0178218 W + Subthreshold Leakage Power = 0.00180662 W + Gate Leakage Power = 9.16038e-05 W + Runtime Dynamic Power = 0.00134737 W + Runtime Dynamic Energy = 1.18886e-10 J + Total Runtime Energy = 2.86376e-10 J + + Branch Target Buffer: + Area = 0.526552 mm^2 + Peak Dynamic Power = 0.0433889 W + Subthreshold Leakage Power = 0.0869885 W + Gate Leakage Power = 0.00266245 W + Runtime Dynamic Power = 0.0189877 W + Runtime Dynamic Energy = 1.67538e-09 J + Total Runtime Energy = 9.58576e-09 J + + Branch Predictor: + Area = 0.594319 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.186556 W + Gate Leakage Power = 0.00424723 W + Runtime Dynamic Power = 0.0649181 W + Runtime Dynamic Energy = 5.72807e-09 J + Total Runtime Energy = 2.25637e-08 J + + Global Predictor: + Area = 0.129022 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0419609 W + Gate Leakage Power = 0.000962899 W + Runtime Dynamic Power = 0.0172467 W + Runtime Dynamic Energy = 1.52177e-09 J + Total Runtime Energy = 5.30916e-09 J + + Local Predictor, Level 1: + Area = 0.191924 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0589594 W + Gate Leakage Power = 0.00130932 W + Runtime Dynamic Power = 0.0255552 W + Runtime Dynamic Energy = 2.25487e-09 J + Total Runtime Energy = 7.5727e-09 J + + Local Predictor, Level 2: + Area = 0.129022 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0419609 W + Gate Leakage Power = 0.000962899 W + Runtime Dynamic Power = 0.0046946 W + Runtime Dynamic Energy = 4.1423e-10 J + Total Runtime Energy = 4.20162e-09 J + + Predictor Chooser: + Area = 0.129022 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0419609 W + Gate Leakage Power = 0.000962899 W + Runtime Dynamic Power = 0.0172467 W + Runtime Dynamic Energy = 1.52177e-09 J + Total Runtime Energy = 5.30916e-09 J + + RAS: + Area = 0.0153301 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0017144 W + Gate Leakage Power = 4.92127e-05 W + Runtime Dynamic Power = 0.000174881 W + Runtime Dynamic Energy = 1.54306e-11 J + Total Runtime Energy = 1.71043e-10 J + + Instruction Buffer: + Area = 0.0034347 mm^2 + Peak Dynamic Power = 0.011729 W + Subthreshold Leakage Power = 0.000650517 W + Gate Leakage Power = 1.85414e-05 W + Runtime Dynamic Power = 0.00390968 W + Runtime Dynamic Energy = 3.44972e-10 J + Total Runtime Energy = 4.04006e-10 J + + Instruction Opcode Decoder: + Area = 0.00289896 mm^2 + Peak Dynamic Power = 0.0752588 W + Subthreshold Leakage Power = 0.00253168 W + Gate Leakage Power = 8.37387e-05 W + Runtime Dynamic Power = 0.0250863 W + Runtime Dynamic Energy = 2.2135e-09 J + Total Runtime Energy = 2.44427e-09 J + + Instruction Operand Decoder: + Area = 0.000377341 mm^2 + Peak Dynamic Power = 0.0751236 W + Subthreshold Leakage Power = 0.00032028 W + Gate Leakage Power = 1.17596e-05 W + Runtime Dynamic Power = 0.0250412 W + Runtime Dynamic Energy = 2.20952e-09 J + Total Runtime Energy = 2.23881e-09 J + + Instruction Microcode Decoder: + Area = 0.00289896 mm^2 + Peak Dynamic Power = 0.0752588 W + Subthreshold Leakage Power = 0.00253168 W + Gate Leakage Power = 8.37387e-05 W + Runtime Dynamic Power = 0.0250863 W + Runtime Dynamic Energy = 2.2135e-09 J + Total Runtime Energy = 2.44427e-09 J + + Load/Store Unit: + Area = 1.69899 mm^2 + Peak Dynamic Power = 0.16674 W + Subthreshold Leakage Power = 0.0926715 W + Gate Leakage Power = 0.00259372 W + Runtime Dynamic Power = 0.142557 W + Runtime Dynamic Energy = 1.25786e-08 J + Total Runtime Energy = 2.09843e-08 J + + Data Cache: + Area = 1.58391 mm^2 + Peak Dynamic Power = 0.0928926 W + Subthreshold Leakage Power = 0.0789233 W + Gate Leakage Power = 0.00207502 W + Runtime Dynamic Power = 0.0922726 W + Runtime Dynamic Energy = 8.1417e-09 J + Total Runtime Energy = 1.52886e-08 J + + Data and Tag Arrays: + Area = 0.619642 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0607406 W + Gate Leakage Power = 0.00122316 W + Runtime Dynamic Power = 0.0861866 W + Runtime Dynamic Energy = 7.6047e-09 J + Total Runtime Energy = 1.30721e-08 J + + Miss Buffer: + Area = 0.270528 mm^2 + Peak Dynamic Power = 0.0245073 W + Subthreshold Leakage Power = 0.0048041 W + Gate Leakage Power = 0.000224896 W + Runtime Dynamic Power = 0.00214283 W + Runtime Dynamic Energy = 1.89073e-10 J + Total Runtime Energy = 6.32808e-10 J + + Fill Buffer: + Area = 0.231248 mm^2 + Peak Dynamic Power = 0.0227951 W + Subthreshold Leakage Power = 0.00445956 W + Gate Leakage Power = 0.000208987 W + Runtime Dynamic Power = 0.00197161 W + Runtime Dynamic Energy = 1.73965e-10 J + Total Runtime Energy = 5.85896e-10 J + + Prefetch Buffer: + Area = 0.231248 mm^2 + Peak Dynamic Power = 0.0227951 W + Subthreshold Leakage Power = 0.00445956 W + Gate Leakage Power = 0.000208987 W + Runtime Dynamic Power = 0.00157729 W + Runtime Dynamic Energy = 1.39172e-10 J + Total Runtime Energy = 5.51103e-10 J + + Writeback Buffer: + Area = 0.231248 mm^2 + Peak Dynamic Power = 0.0227951 W + Subthreshold Leakage Power = 0.00445956 W + Gate Leakage Power = 0.000208987 W + Runtime Dynamic Power = 0.000394322 W + Runtime Dynamic Energy = 3.47931e-11 J + Total Runtime Energy = 4.46724e-10 J + + Load Queue: + Area = 0.054217 mm^2 + Peak Dynamic Power = 0.0316525 W + Subthreshold Leakage Power = 0.00559768 W + Gate Leakage Power = 0.00022125 W + Runtime Dynamic Power = 0.0137161 W + Runtime Dynamic Energy = 1.21024e-09 J + Total Runtime Energy = 1.72368e-09 J + + Store Queue: + Area = 0.0608565 mm^2 + Peak Dynamic Power = 0.0421944 W + Subthreshold Leakage Power = 0.00815046 W + Gate Leakage Power = 0.000297452 W + Runtime Dynamic Power = 0.0365685 W + Runtime Dynamic Energy = 3.22663e-09 J + Total Runtime Energy = 3.97204e-09 J + + Memory Management Unit: + Area = 0.331371 mm^2 + Peak Dynamic Power = 0.318513 W + Subthreshold Leakage Power = 0.097099 W + Gate Leakage Power = 0.00441089 W + Runtime Dynamic Power = 0.137566 W + Runtime Dynamic Energy = 1.21382e-08 J + Total Runtime Energy = 2.10949e-08 J + + Instruction TLB: + Area = 0.131789 mm^2 + Peak Dynamic Power = 0.151159 W + Subthreshold Leakage Power = 0.0446376 W + Gate Leakage Power = 0.00203139 W + Runtime Dynamic Power = 0.0528415 W + Runtime Dynamic Energy = 4.66249e-09 J + Total Runtime Energy = 8.78034e-09 J + + Data TLB: + Area = 0.199582 mm^2 + Peak Dynamic Power = 0.167354 W + Subthreshold Leakage Power = 0.0524614 W + Gate Leakage Power = 0.00237949 W + Runtime Dynamic Power = 0.0847243 W + Runtime Dynamic Energy = 7.47567e-09 J + Total Runtime Energy = 1.23146e-08 J + + Execution Unit: + Area = 2.36584 mm^2 + Peak Dynamic Power = 1.52633 W + Subthreshold Leakage Power = 1.18035 W + Gate Leakage Power = 0.0498689 W + Runtime Dynamic Power = 0.517033 W + Runtime Dynamic Energy = 4.56205e-08 J + Total Runtime Energy = 1.5417e-07 J + + Int Bypass Data: + Area = 0.0024813 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00618474 W + Runtime Dynamic Energy = 5.45712e-10 J + Total Runtime Energy = 5.45712e-10 J + + Int Bypass Tag: + Area = 0.000291384 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.000726287 W + Runtime Dynamic Energy = 6.40842e-11 J + Total Runtime Energy = 6.40842e-11 J + + Mul Bypass Data: + Area = 0.00328459 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00818697 W + Runtime Dynamic Energy = 7.2238e-10 J + Total Runtime Energy = 7.2238e-10 J + + Mul Bypass Tag: + Area = 0.000366693 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.000913997 W + Runtime Dynamic Energy = 8.06468e-11 J + Total Runtime Energy = 8.06468e-11 J + + FP Bypass Data: + Area = 0.0039374 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00981414 W + Runtime Dynamic Energy = 8.65954e-10 J + Total Runtime Energy = 8.65954e-10 J + + FP Bypass Tag: + Area = 0.000508858 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00126835 W + Runtime Dynamic Energy = 1.11913e-10 J + Total Runtime Energy = 1.11913e-10 J + + Register File Unit: + Area = 0.0603417 mm^2 + Peak Dynamic Power = 0.094149 W + Subthreshold Leakage Power = 0.00361325 W + Gate Leakage Power = 0.000100838 W + Runtime Dynamic Power = 0.00713589 W + Runtime Dynamic Energy = 6.29638e-10 J + Total Runtime Energy = 9.57351e-10 J + + Integer Register File: + Area = 0.0397387 mm^2 + Peak Dynamic Power = 0.0858804 W + Subthreshold Leakage Power = 0.00167327 W + Gate Leakage Power = 4.73072e-05 W + Runtime Dynamic Power = 0.00340795 W + Runtime Dynamic Energy = 3.00702e-10 J + Total Runtime Energy = 4.52517e-10 J + + FP Register File: + Area = 0.020603 mm^2 + Peak Dynamic Power = 0.00826856 W + Subthreshold Leakage Power = 0.00193998 W + Gate Leakage Power = 5.35312e-05 W + Runtime Dynamic Power = 0.00372794 W + Runtime Dynamic Energy = 3.28936e-10 J + Total Runtime Energy = 5.04834e-10 J + + Instruction Scheduler: + Area = 0.107117 mm^2 + Peak Dynamic Power = 0.107009 W + Subthreshold Leakage Power = 0.00250283 W + Gate Leakage Power = 7.07223e-05 W + Runtime Dynamic Power = 0.0155966 W + Runtime Dynamic Energy = 1.37617e-09 J + Total Runtime Energy = 1.60325e-09 J + + Integer Instruction Window: + Area = 0.0261741 mm^2 + Peak Dynamic Power = 0.0268581 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00223817 W + Runtime Dynamic Energy = 1.97486e-10 J + Total Runtime Energy = 1.97486e-10 J + + FP Instruction Window: + Area = 0.0232716 mm^2 + Peak Dynamic Power = 0.0133785 W + Subthreshold Leakage Power = 0 W + Gate Leakage Power = 0 W + Runtime Dynamic Power = 0.00222975 W + Runtime Dynamic Energy = 1.96742e-10 J + Total Runtime Energy = 1.96742e-10 J + + Reorder Buffer: + Area = 0.0576711 mm^2 + Peak Dynamic Power = 0.066772 W + Subthreshold Leakage Power = 0.00250283 W + Gate Leakage Power = 7.07223e-05 W + Runtime Dynamic Power = 0.0111287 W + Runtime Dynamic Energy = 9.81941e-10 J + Total Runtime Energy = 1.20902e-09 J + + Integer ALU(s): + Area = 0.138846 mm^2 + Peak Dynamic Power = 0.332578 W + Subthreshold Leakage Power = 0.201977 W + Gate Leakage Power = 0.00854828 W + Runtime Dynamic Power = 0.0778676 W + Runtime Dynamic Energy = 6.87067e-09 J + Total Runtime Energy = 2.54464e-08 J + + Floating Point Unit(s): + Area = 1.8404 mm^2 + Peak Dynamic Power = 0.595559 W + Subthreshold Leakage Power = 0.669296 W + Gate Leakage Power = 0.0283266 W + Runtime Dynamic Power = 0.233603 W + Runtime Dynamic Energy = 2.0612e-08 J + Total Runtime Energy = 8.21669e-08 J + + Multiply/Divide Unit(s): + Area = 0.20827 mm^2 + Peak Dynamic Power = 0.39704 W + Subthreshold Leakage Power = 0.302965 W + Gate Leakage Power = 0.0128224 W + Runtime Dynamic Power = 0.155735 W + Runtime Dynamic Energy = 1.37413e-08 J + Total Runtime Energy = 4.1605e-08 J + + Undifferentiated Core: + Area = 3.88668 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 2.82694 W + Gate Leakage Power = 0.119645 W + Runtime Dynamic Power = 0 W + Runtime Dynamic Energy = 0 J + Total Runtime Energy = 2.59992e-07 J + + Rename Unit: + Area = 0.333151 mm^2 + Peak Dynamic Power = 0.10888 W + Subthreshold Leakage Power = 0.0255114 W + Gate Leakage Power = 0.000663381 W + Runtime Dynamic Power = 0.0538848 W + Runtime Dynamic Energy = 4.75454e-09 J + Total Runtime Energy = 7.06408e-09 J + + Int Front RAT: + Area = 0.129348 mm^2 + Peak Dynamic Power = 0.0382386 W + Subthreshold Leakage Power = 0.00828989 W + Gate Leakage Power = 0.000204367 W + Runtime Dynamic Power = 0.0063731 W + Runtime Dynamic Energy = 5.62332e-10 J + Total Runtime Energy = 1.31183e-09 J + + FP Front RAT: + Area = 0.166163 mm^2 + Peak Dynamic Power = 0.0432953 W + Subthreshold Leakage Power = 0.0126995 W + Gate Leakage Power = 0.000319816 W + Runtime Dynamic Power = 0.00721588 W + Runtime Dynamic Energy = 6.36696e-10 J + Total Runtime Energy = 1.78546e-09 J + + Integer Free List: + Area = 0.0120305 mm^2 + Peak Dynamic Power = 0.00394808 W + Subthreshold Leakage Power = 0.000639181 W + Gate Leakage Power = 2.0232e-05 W + Runtime Dynamic Power = 0.00131603 W + Runtime Dynamic Energy = 1.1612e-10 J + Total Runtime Energy = 1.74304e-10 J + + Int Retire RAT: + Area = 0.00606308 mm^2 + Peak Dynamic Power = 0.00325948 W + Subthreshold Leakage Power = 0.000496413 W + Gate Leakage Power = 1.45535e-05 W + Runtime Dynamic Power = 0.000543246 W + Runtime Dynamic Energy = 4.79335e-11 J + Total Runtime Energy = 9.30188e-11 J + + FP Retire RAT: + Area = 0.00751656 mm^2 + Peak Dynamic Power = 0.00404193 W + Subthreshold Leakage Power = 0.000709488 W + Gate Leakage Power = 1.94961e-05 W + Runtime Dynamic Power = 0.000673654 W + Runtime Dynamic Energy = 5.94401e-11 J + Total Runtime Energy = 1.23762e-10 J + + FP Free List: + Area = 0.0120305 mm^2 + Peak Dynamic Power = 0.00394808 W + Subthreshold Leakage Power = 0.000639181 W + Gate Leakage Power = 2.0232e-05 W + Runtime Dynamic Power = 0.00131603 W + Runtime Dynamic Energy = 1.1612e-10 J + Total Runtime Energy = 1.74304e-10 J + + Instruction Dependency Check?: + Area = 0 mm^2 + Peak Dynamic Power = 0.00607447 W + Subthreshold Leakage Power = 0.00101891 W + Gate Leakage Power = 3.23427e-05 W + Runtime Dynamic Power = 0.0242979 W + Runtime Dynamic Energy = 2.14393e-09 J + Total Runtime Energy = 2.23669e-09 J + + FP Dependency Check?: + Area = 0 mm^2 + Peak Dynamic Power = 0.00607447 W + Subthreshold Leakage Power = 0.00101891 W + Gate Leakage Power = 3.23427e-05 W + Runtime Dynamic Power = 0.0121489 W + Runtime Dynamic Energy = 1.07197e-09 J + Total Runtime Energy = 1.16472e-09 J + + Pipeline?: + Area = 0.0912321 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 0.0748063 W + Gate Leakage Power = 0.00796757 W + Runtime Dynamic Power = 0.269895 W + Runtime Dynamic Energy = 2.38143e-08 J + Total Runtime Energy = 3.11178e-08 J + + L2 Cache: + Area = 4.32531 mm^2 + Peak Dynamic Power = 0.121415 W + Subthreshold Leakage Power = 1.21565 W + Gate Leakage Power = 0.0392567 W + Runtime Dynamic Power = 0.608456 W + Runtime Dynamic Energy = 5.36873e-08 J + Total Runtime Energy = 1.64414e-07 J + + Data and Tag Arrays: + Area = 3.33708 mm^2 + Peak Dynamic Power = 0 W + Subthreshold Leakage Power = 1.1905 W + Gate Leakage Power = 0.0381925 W + Runtime Dynamic Power = 0.588461 W + Runtime Dynamic Energy = 5.1923e-08 J + Total Runtime Energy = 1.60337e-07 J + + Miss Buffer: + Area = 0.281957 mm^2 + Peak Dynamic Power = 0.0322848 W + Subthreshold Leakage Power = 0.00670028 W + Gate Leakage Power = 0.000283174 W + Runtime Dynamic Power = 0.00709987 W + Runtime Dynamic Energy = 6.26459e-10 J + Total Runtime Energy = 1.24265e-09 J + + Fill Buffer: + Area = 0.235423 mm^2 + Peak Dynamic Power = 0.02971 W + Subthreshold Leakage Power = 0.00614777 W + Gate Leakage Power = 0.000260358 W + Runtime Dynamic Power = 0.00644759 W + Runtime Dynamic Energy = 5.68905e-10 J + Total Runtime Energy = 1.13433e-09 J + + Prefetch Buffer: + Area = 0.235423 mm^2 + Peak Dynamic Power = 0.02971 W + Subthreshold Leakage Power = 0.00614777 W + Gate Leakage Power = 0.000260358 W + Runtime Dynamic Power = 0.00593857 W + Runtime Dynamic Energy = 5.23992e-10 J + Total Runtime Energy = 1.08941e-09 J + + Writeback Buffer: + Area = 0.235423 mm^2 + Peak Dynamic Power = 0.02971 W + Subthreshold Leakage Power = 0.00614777 W + Gate Leakage Power = 0.000260358 W + Runtime Dynamic Power = 0.00050902 W + Runtime Dynamic Energy = 4.49136e-11 J + Total Runtime Energy = 6.10337e-10 J + diff --git a/ext/mcpat/regression/test-7/power_region0.xml b/ext/mcpat/regression/test-7/power_region0.xml new file mode 100644 index 000000000..ad69e748e --- /dev/null +++ b/ext/mcpat/regression/test-7/power_region0.xml @@ -0,0 +1,68 @@ +<?xml version="1.0" ?> +<component id="root" name="root"> + <component id="system" name="system" type="System"> + <param name="core_tech_node" value="40"/> + <param name="target_core_clockrate" value="1700"/> + <param name="temperature" value="380"/> + <param name="interconnect_projection_type" value="1"/> + <param name="device_type" value="0"/> + <param name="longer_channel_device" value="0"/> + <param name="machine_bits" value="64"/> + <param name="virtual_address_width" value="64"/> + <param name="physical_address_width" value="36"/> + <param name="virtual_memory_page_size" value="4096"/> + <param name="wire_is_mat_type" value="2"/> + <param name="wire_os_mat_type" value="2"/> + <param name="delay_wt" value="100"/> + <param name="area_wt" value="0"/> + <param name="dynamic_power_wt" value="100"/> + <param name="leakage_power_wt" value="0"/> + <param name="cycle_time_wt" value="0"/> + <param name="delay_dev" value="10000"/> + <param name="area_dev" value="10000"/> + <param name="dynamic_power_dev" value="10000"/> + <param name="leakage_power_dev" value="10000"/> + <param name="cycle_time_dev" value="10000"/> + <param name="ed" value="2"/> + <param name="burst_len" value="1"/> + <param name="int_prefetch_w" value="1"/> + <param name="page_sz_bits" value="0"/> + <param name="rpters_in_htree" value="1"/> + <param name="ver_htree_wires_over_array" value="0"/> + <param name="nuca" value="0"/> + <param name="nuca_bank_count" value="0"/> + <param name="force_cache_config" value="0"/> + <param name="wt" value="0"/> + <param name="force_wiretype" value="0"/> + <param name="print_detail" value="1"/> + <param name="add_ecc_b_" value="1"/> + <stat name="total_cycles" value="15"/> + <component id="system.NoC0" name="noc0" type="OnChipNetwork"> + <param name="clockrate" value="1700"/> + <param name="type" value="0"/> + <param name="horizontal_nodes" value="1"/> + <param name="vertical_nodes" value="1"/> + <param name="has_global_link" value="0"/> + <param name="link_len" value="1"/> + <param name="link_throughput" value="1"/> + <param name="link_latency" value="1"/> + <param name="input_ports" value="1"/> + <param name="output_ports" value="1"/> + <param name="global_linked_ports" value="1"/> + <param name="flit_bits" value="256"/> + <param name="chip_coverage" value="1"/> + <param name="link_routing_over_percentage" value="0.5"/> + <param name="has_global_link" value="0"/> + <param name="virtual_channel_per_port" value="2"/> + <param name="input_buffer_entries_per_vc" value="16"/> + <param name="M_traffic_pattern" value="1"/> + <param name="link_base_width" value="1"/> + <param name="link_base_height" value="1"/> + <param name="link_start_wiring_level" value="3"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <stat name="total_accesses" value="5"/> + <stat name="duty_cycle" value="1"/> + </component> + </component> +</component> diff --git a/ext/mcpat/regression/test-7/region0.out.ref b/ext/mcpat/regression/test-7/region0.out.ref new file mode 100644 index 000000000..f8acf4c46 --- /dev/null +++ b/ext/mcpat/regression/test-7/region0.out.ref @@ -0,0 +1,37 @@ +McPAT (version 0.8 of Aug, 2010) is computing the target processor... + + +McPAT (version 0.8 of Aug, 2010) results (current print level is 5) +***************************************************************************************** + Technology 40 nm + Interconnect metal projection = conservative interconnect technology projection + Target Clock Rate (MHz) 1700 + +***************************************************************************************** + System: + Area = 4.5263e-05 mm^2 + Peak Dynamic Power = 0.00021451 W + Subthreshold Leakage Power = 1.40646e-05 W + Gate Leakage Power = 5.95257e-07 W + Runtime Dynamic Power = 7.15034e-05 W + Runtime Dynamic Energy = 6.30912e-13 J + Total Runtime Energy = 7.60264e-13 J + + On-Chip Network: + Area = 4.5263e-05 mm^2 + Peak Dynamic Power = 0.00021451 W + Subthreshold Leakage Power = 1.40646e-05 W + Gate Leakage Power = 5.95257e-07 W + Runtime Dynamic Power = 7.15034e-05 W + Runtime Dynamic Energy = 6.30912e-13 J + Total Runtime Energy = 7.60264e-13 J + + Link: + Area = 4.5263e-05 mm^2 + Peak Dynamic Power = 0.00021451 W + Subthreshold Leakage Power = 1.40646e-05 W + Gate Leakage Power = 5.95257e-07 W + Runtime Dynamic Power = 7.15034e-05 W + Runtime Dynamic Energy = 6.30912e-13 J + Total Runtime Energy = 7.60264e-13 J + diff --git a/ext/mcpat/regression/test-8/power_region0.xml b/ext/mcpat/regression/test-8/power_region0.xml new file mode 100644 index 000000000..13b895d7c --- /dev/null +++ b/ext/mcpat/regression/test-8/power_region0.xml @@ -0,0 +1,64 @@ +<?xml version="1.0" ?> +<component id="root" name="root"> + <component id="system" name="system" type="System"> + <param name="core_tech_node" value="40"/> + <param name="target_core_clockrate" value="1700"/> + <param name="temperature" value="380"/> + <param name="interconnect_projection_type" value="1"/> + <param name="device_type" value="0"/> + <param name="longer_channel_device" value="0"/> + <param name="machine_bits" value="64"/> + <param name="virtual_address_width" value="64"/> + <param name="physical_address_width" value="36"/> + <param name="virtual_memory_page_size" value="4096"/> + <param name="wire_is_mat_type" value="2"/> + <param name="wire_os_mat_type" value="2"/> + <param name="delay_wt" value="100"/> + <param name="area_wt" value="0"/> + <param name="dynamic_power_wt" value="100"/> + <param name="leakage_power_wt" value="0"/> + <param name="cycle_time_wt" value="0"/> + <param name="delay_dev" value="10000"/> + <param name="area_dev" value="10000"/> + <param name="dynamic_power_dev" value="10000"/> + <param name="leakage_power_dev" value="10000"/> + <param name="cycle_time_dev" value="10000"/> + <param name="ed" value="2"/> + <param name="burst_len" value="1"/> + <param name="int_prefetch_w" value="1"/> + <param name="page_sz_bits" value="0"/> + <param name="rpters_in_htree" value="1"/> + <param name="ver_htree_wires_over_array" value="0"/> + <param name="nuca" value="0"/> + <param name="nuca_bank_count" value="0"/> + <param name="force_cache_config" value="0"/> + <param name="wt" value="0"/> + <param name="force_wiretype" value="0"/> + <param name="print_detail" value="1"/> + <param name="add_ecc_b_" value="1"/> + <stat name="total_cycles" value="15"/> + <component id="system.tol2bus" name="bus" type="BusInterconnect"> + <param name="clockrate" value="1700"/> + <param name="link_throughput" value="1"/> + <param name="link_latency" value="1"/> + <param name="total_nodes" value="2"/> + <param name="input_ports" value="2"/> + <param name="output_ports" value="2"/> + <param name="global_linked_ports" value="1"/> + <param name="flit_bits" value="256"/> + <param name="chip_coverage" value="1"/> + <param name="pipelinable" value="1"/> + <param name="link_routing_over_percentage" value="0.5"/> + <param name="virtual_channel_per_port" value="1"/> + <param name="M_traffic_pattern" value="1"/> + <param name="link_len" value="1"/> + <param name="link_base_width" value="1"/> + <param name="link_base_height" value="1"/> + <param name="link_start_wiring_level" value="3"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <stat name="total_accesses" value="5"/> + <stat name="duty_cycle" value="1"/> + </component> + </component> +</component> diff --git a/ext/mcpat/regression/test-8/region0.out.ref b/ext/mcpat/regression/test-8/region0.out.ref new file mode 100644 index 000000000..e2fd36f99 --- /dev/null +++ b/ext/mcpat/regression/test-8/region0.out.ref @@ -0,0 +1,37 @@ +McPAT (version 0.8 of Aug, 2010) is computing the target processor... + + +McPAT (version 0.8 of Aug, 2010) results (current print level is 5) +***************************************************************************************** + Technology 40 nm + Interconnect metal projection = conservative interconnect technology projection + Target Clock Rate (MHz) 1700 + +***************************************************************************************** + System: + Area = 1.13158e-05 mm^2 + Peak Dynamic Power = 5.36275e-05 W + Subthreshold Leakage Power = 3.51615e-06 W + Gate Leakage Power = 1.48814e-07 W + Runtime Dynamic Power = 1.78758e-05 W + Runtime Dynamic Energy = 1.57728e-13 J + Total Runtime Energy = 1.90066e-13 J + + Bus Interconnect: + Area = 1.13158e-05 mm^2 + Peak Dynamic Power = 5.36275e-05 W + Subthreshold Leakage Power = 3.51615e-06 W + Gate Leakage Power = 1.48814e-07 W + Runtime Dynamic Power = 1.78758e-05 W + Runtime Dynamic Energy = 1.57728e-13 J + Total Runtime Energy = 1.90066e-13 J + + Link: + Area = 1.13158e-05 mm^2 + Peak Dynamic Power = 5.36275e-05 W + Subthreshold Leakage Power = 3.51615e-06 W + Gate Leakage Power = 1.48814e-07 W + Runtime Dynamic Power = 1.78758e-05 W + Runtime Dynamic Energy = 1.57728e-13 J + Total Runtime Energy = 1.90066e-13 J + diff --git a/ext/mcpat/regression/verify_output.py b/ext/mcpat/regression/verify_output.py new file mode 100644 index 000000000..c37663c8f --- /dev/null +++ b/ext/mcpat/regression/verify_output.py @@ -0,0 +1,238 @@ +#!/usr/bin/env python + +# Copyright (c) 2010-2013 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +SYNOPSIS + + ./regression/verify_output.py <McPAT output> + +DESCRIPTION + + Verify the output from McPAT. In particular, ensure that the values in the + file sum up hierarchically. + +AUTHORS + + Joel Hestness <hestness@cs.wisc.edu> (while interning at AMD) + Yasuko Eckert <yasuko.eckert@amd.com> + +""" + +import os +import sys +import optparse +import re + +root = None +curr_node = None + +optionsparser = optparse.OptionParser( + formatter = optparse.TitledHelpFormatter(), + usage = globals()['__doc__']) +optionsparser.add_option( + "-v", "--verbose", action = "store_true", default = False, + help = "verbose output") +(options, args) = optionsparser.parse_args() + +def warning(msg): + global options + if options.verbose: + print "WARNING: %s" %(msg) + +def toNumber(value): + try: + to_return = float(value) + except: + warning("Value, %s, is not a number" % value) + to_return = value + + return to_return + +def withinTolerance(reference, calculated, tolerance = 0.001): + if tolerance > 1: + warning("Tolernance is too large: %s" % tolerance) + upper_bound = reference * (1 + tolerance) + lower_bound = reference * (1 - tolerance) + return calculated <= upper_bound and calculated >= lower_bound + +class Component: + def __init__(self): + self.parent = None + self.name = None + self.area = None + self.peak_dynamic_power = None + self.subthreshold_leakage = None + self.gate_leakage = None + self.runtime_dynamic_power = None + self.runtime_dynamic_energy = None + self.total_runtime_energy = None + self.children = [] + self.hierarchy_level = None + + def print_data(self): + print "%s:" % self.name + print " Area = %s" % self.area + print " Peak Dynamic Power = %s" % self.peak_dynamic_power + print " Subthreshold Leakage = %s" % self.subthreshold_leakage + print " Gate Leakage = %s" % self.gate_leakage + print " Runtime Dynamic Power = %s" % self.runtime_dynamic_power + print " Runtime Dynamic Energy = %s" % self.runtime_dynamic_energy + print " Total Runtime Energy = %s" % self.total_runtime_energy + + def set_name_and_level(self, name_string): + self.name = name_string.lstrip().rstrip(":") + self.hierarchy_level = (len(re.match(r"\s*", name_string).group()) - 2) / 4 + + def verify_values(self): + if len(self.children) == 0: + return + temp_node = Component() + temp_node.area = 0 + temp_node.peak_dynamic_power = 0 + temp_node.subthreshold_leakage = 0 + temp_node.gate_leakage = 0 + temp_node.runtime_dynamic_power = 0 + temp_node.runtime_dynamic_energy = 0 + temp_node.total_runtime_energy = 0 + for child in self.children: + if child != self: + temp_node.area += child.area + temp_node.peak_dynamic_power += child.peak_dynamic_power + temp_node.subthreshold_leakage += child.subthreshold_leakage + temp_node.gate_leakage += child.gate_leakage + temp_node.runtime_dynamic_power += child.runtime_dynamic_power + temp_node.runtime_dynamic_energy += child.runtime_dynamic_energy + temp_node.total_runtime_energy += child.total_runtime_energy + child.verify_values() + + if not withinTolerance(self.area, temp_node.area): + print "WRONG: %s.area = %s != %s" % \ + (self.name, self.area, temp_node.area) + + if not withinTolerance( + self.peak_dynamic_power, temp_node.peak_dynamic_power): + print "WRONG: %s.peak_dynamic_power = %s != %s" % \ + (self.name, self.peak_dynamic_power, + temp_node.peak_dynamic_power) + + if not withinTolerance( + self.subthreshold_leakage, temp_node.subthreshold_leakage): + print "WRONG: %s.subthreshold_leakage = %s != %s" % \ + (self.name, self.subthreshold_leakage, + temp_node.subthreshold_leakage) + + if not withinTolerance(self.gate_leakage, temp_node.gate_leakage): + print "WRONG: %s.gate_leakage = %s != %s" % \ + (self.name, self.gate_leakage, temp_node.gate_leakage) + + if not withinTolerance( + self.runtime_dynamic_power, temp_node.runtime_dynamic_power): + print "WRONG: %s.runtime_dynamic_power = %s != %s" % \ + (self.name, self.runtime_dynamic_power, + temp_node.runtime_dynamic_power) + + if not withinTolerance( + self.runtime_dynamic_energy, temp_node.runtime_dynamic_energy): + print "WRONG: %s.runtime_dynamic_energy = %s != %s" % \ + (self.name, self.runtime_dynamic_energy, + temp_node.runtime_dynamic_energy) + + if not withinTolerance( + self.total_runtime_energy, temp_node.total_runtime_energy): + print "WRONG: %s.total_runtime_energy = %s != %s" % \ + (self.name, self.total_runtime_energy, + temp_node.total_runtime_energy) + +if len(args) < 1: + print "ERROR: Must specify a McPAT output file to verify" + exit(0) + +# check params +mcpat_output = args[0]; +if not os.path.exists(mcpat_output): + print "ERROR: Output file does not exist: %s" % mcpat_output + exit(0) + +output_file_handle = open(mcpat_output, 'r') +for line in output_file_handle: + line = line.rstrip() + if ":" in line: + # Start a new component + new_node = Component() + if root is None: + root = new_node + curr_node = new_node + else: + if ((curr_node.area is None) or + (curr_node.peak_dynamic_power is None) or + (curr_node.subthreshold_leakage is None) or + (curr_node.gate_leakage is None) or + (curr_node.runtime_dynamic_power is None) or + (curr_node.runtime_dynamic_energy is None) or + (curr_node.total_runtime_energy is None)): + print "ERROR: Some value is not specified for %s" % curr_node.name + curr_node.print_data() + exit(0) + + new_node.set_name_and_level(line) + while ( + (new_node.hierarchy_level <= curr_node.hierarchy_level) and + not curr_node is root): + curr_node = curr_node.parent + new_node.parent = curr_node + curr_node.children.append(new_node) + curr_node = new_node + + elif line is not "": + tokens = line.split() + if "Area" in line: + curr_node.area = toNumber(tokens[2]) + elif "Peak Dynamic Power" in line: + curr_node.peak_dynamic_power = toNumber(tokens[4]) + elif "Peak Dynamic" in line: + curr_node.peak_dynamic_power = toNumber(tokens[3]) + elif "Subthreshold Leakage Power" in line: + curr_node.subthreshold_leakage = toNumber(tokens[4]) + elif "Subthreshold Leakage" in line: + curr_node.subthreshold_leakage = toNumber(tokens[3]) + elif "Gate Leakage Power" in line: + curr_node.gate_leakage = toNumber(tokens[4]) + elif "Gate Leakage" in line: + curr_node.gate_leakage = toNumber(tokens[3]) + elif "Runtime Dynamic Power" in line: + curr_node.runtime_dynamic_power = toNumber(tokens[4]) + elif "Runtime Dynamic Energy" in line: + curr_node.runtime_dynamic_energy = toNumber(tokens[4]) + elif "Total Runtime Energy" in line: + curr_node.total_runtime_energy = toNumber(tokens[4]) + else: + warning("ERROR: Line not matched: %s" % line) + +curr_node = root + +curr_node.verify_values() |