diff options
| -rw-r--r-- | configs/common/FSConfig.py | 27 | ||||
| -rw-r--r-- | src/dev/arm/RealView.py | 9 |
2 files changed, 24 insertions, 12 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index a89c2a571..cc921229e 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -246,19 +246,30 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, if dtb_filename: self.dtb_filename = binary(dtb_filename) self.machine_type = machine_type - if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): - print "The currently selected ARM platforms doesn't support" - print " the amount of DRAM you've selected. Please try" - print " another platform" - sys.exit(1) - # Ensure that writes to the UART actually go out early in the boot boot_flags = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 'mem=%s root=/dev/sda1' % mdesc.mem() - self.mem_ranges = [AddrRange(self.realview.mem_start_addr, - size = mdesc.mem())] + self.mem_ranges = [] + size_remain = long(Addr(mdesc.mem())) + for region in self.realview._mem_regions: + if size_remain > long(region[1]): + self.mem_ranges.append(AddrRange(region[0], size=region[1])) + size_remain = size_remain - long(region[1]) + else: + self.mem_ranges.append(AddrRange(region[0], size=size_remain)) + size_remain = 0 + break + warn("Memory size specified spans more than one region. Creating" \ + " another memory controller for that range.") + + if size_remain > 0: + fatal("The currently selected ARM platforms doesn't support" \ + " the amount of DRAM you've selected. Please try" \ + " another platform") + + self.realview.setupBootLoader(self.membus, self, binary) self.gic_cpu_addr = self.realview.gic.cpu_addr self.flags_addr = self.realview.realview_io.pio_addr + 0x30 diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index ee5993a88..672b17c87 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -184,8 +184,7 @@ class RealView(Platform): pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access" " be compatible with the pci-generic-host or the legacy host bridge?") - mem_start_addr = Param.Addr(0, "Start address of main memory") - max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") + _mem_regions = [(Addr(0), Addr('256MB'))] def attachPciDevices(self): pass @@ -444,8 +443,7 @@ class RealViewEB(RealView): self.smcreg_fake.clk_domain = clkdomain class VExpress_EMM(RealView): - mem_start_addr = '2GB' - max_mem_size = '2GB' + _mem_regions = [(Addr('2GB'), Addr('2GB'))] pci_cfg_base = 0x30000000 uart = Pl011(pio_addr=0x1c090000, int_num=37) realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \ @@ -602,6 +600,9 @@ class VExpress_EMM(RealView): class VExpress_EMM64(VExpress_EMM): pci_io_base = 0x2f000000 pci_cfg_gen_offsets = True + # Three memory regions are specified totalling 512GB + _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), + (Addr('512GB'), Addr('480GB'))] def setupBootLoader(self, mem_bus, cur_sys, loc): self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) self.nvmem.port = mem_bus.master |