diff options
| -rw-r--r-- | dev/sinic.cc | 30 | ||||
| -rw-r--r-- | dev/sinic.hh | 7 |
2 files changed, 31 insertions, 6 deletions
diff --git a/dev/sinic.cc b/dev/sinic.cc index f03841ecd..ef2350d11 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -335,10 +335,21 @@ Fault Device::read(MemReqPtr &req, uint8_t *data) { assert(config.command & PCI_CMD_MSE); + Fault fault = readBar(req, data); - //The mask is to give you only the offset into the device register file - Addr daddr = req->paddr & 0xfff; + if (fault == Machine_Check_Fault) { + panic("address does not map to a BAR pa=%#x va=%#x size=%d", + req->paddr, req->vaddr, req->size); + + return Machine_Check_Fault; + } + return fault; +} + +Fault +Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) +{ if (!regValid(daddr)) panic("invalid register: da=%#x pa=%#x va=%#x size=%d", daddr, req->paddr, req->vaddr, req->size); @@ -414,10 +425,21 @@ Fault Device::write(MemReqPtr &req, const uint8_t *data) { assert(config.command & PCI_CMD_MSE); + Fault fault = writeBar(req, data); - //The mask is to give you only the offset into the device register file - Addr daddr = req->paddr & 0xfff; + if (fault == Machine_Check_Fault) { + panic("address does not map to a BAR pa=%#x va=%#x size=%d", + req->paddr, req->vaddr, req->size); + + return Machine_Check_Fault; + } + return fault; +} + +Fault +Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) +{ if (!regValid(daddr)) panic("invalid address: da=%#x pa=%#x va=%#x size=%d", daddr, req->paddr, req->vaddr, req->size); diff --git a/dev/sinic.hh b/dev/sinic.hh index 4a772d4c5..b9089cd53 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -259,10 +259,13 @@ class Device : public Base * Memory Interface */ public: - void prepareRead(); - Fault iprRead(Addr daddr, uint64_t &result); virtual Fault read(MemReqPtr &req, uint8_t *data); virtual Fault write(MemReqPtr &req, const uint8_t *data); + + void prepareRead(); + Fault iprRead(Addr daddr, uint64_t &result); + Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); + Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); Tick cacheAccess(MemReqPtr &req); /** |