summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--src/arch/alpha/AlphaISA.py4
-rw-r--r--src/arch/alpha/isa.cc2
-rw-r--r--src/arch/alpha/isa.hh10
-rw-r--r--src/arch/mips/MipsISA.py3
-rw-r--r--src/arch/mips/isa.cc3
-rw-r--r--src/arch/mips/isa.hh7
-rw-r--r--src/arch/power/isa.hh6
-rw-r--r--src/arch/sparc/isa.hh8
-rw-r--r--src/arch/x86/isa.hh6
-rw-r--r--src/cpu/checker/thread_context.hh1
-rw-r--r--src/cpu/inorder/thread_context.hh3
-rwxr-xr-xsrc/cpu/o3/thread_context.hh1
-rwxr-xr-xsrc/cpu/o3/thread_context_impl.hh7
-rw-r--r--src/cpu/simple_thread.hh8
-rw-r--r--src/cpu/thread_context.hh4
15 files changed, 68 insertions, 5 deletions
diff --git a/src/arch/alpha/AlphaISA.py b/src/arch/alpha/AlphaISA.py
index 64c9e4733..d85354704 100644
--- a/src/arch/alpha/AlphaISA.py
+++ b/src/arch/alpha/AlphaISA.py
@@ -35,9 +35,13 @@
#
# Authors: Andreas Sandberg
+from m5.params import *
+from m5.proxy import *
from m5.SimObject import SimObject
class AlphaISA(SimObject):
type = 'AlphaISA'
cxx_class = 'AlphaISA::ISA'
cxx_header = "arch/alpha/isa.hh"
+
+ system = Param.System(Parent.any, "System this ISA object belongs to")
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index 9cfd840d9..95dfdedd6 100644
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -40,7 +40,7 @@ namespace AlphaISA
{
ISA::ISA(Params *p)
- : SimObject(p)
+ : SimObject(p), system(p->system)
{
clear();
initializeIprTable();
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index d30499066..35a26c108 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -39,6 +39,7 @@
#include "arch/alpha/types.hh"
#include "base/types.hh"
#include "sim/sim_object.hh"
+#include "sim/system.hh"
struct AlphaISAParams;
class BaseCPU;
@@ -55,6 +56,9 @@ namespace AlphaISA
typedef AlphaISAParams Params;
protected:
+ // Parent system
+ System *system;
+
uint64_t fpcr; // floating point condition codes
uint64_t uniq; // process-unique register
bool lock_flag; // lock flag for LL/SC
@@ -110,6 +114,12 @@ namespace AlphaISA
return reg;
}
+ int
+ flattenMiscIndex(int reg)
+ {
+ return reg;
+ }
+
const Params *params() const;
ISA(Params *p);
diff --git a/src/arch/mips/MipsISA.py b/src/arch/mips/MipsISA.py
index bc969a906..22602ff0c 100644
--- a/src/arch/mips/MipsISA.py
+++ b/src/arch/mips/MipsISA.py
@@ -37,11 +37,14 @@
from m5.SimObject import SimObject
from m5.params import *
+from m5.proxy import *
class MipsISA(SimObject):
type = 'MipsISA'
cxx_class = 'MipsISA::ISA'
cxx_header = "arch/mips/isa.hh"
+ system = Param.System(Parent.any, "System this ISA object belongs to")
+
num_threads = Param.UInt8(1, "Maximum number this ISA can handle")
num_vpes = Param.UInt8(1, "Maximum number of vpes this ISA can handle")
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 891ed5e2f..164f10d5d 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -89,8 +89,7 @@ ISA::miscRegNames[NumMiscRegs] =
};
ISA::ISA(Params *p)
- : SimObject(p),
- numThreads(p->num_threads), numVpes(p->num_vpes)
+ : SimObject(p), numThreads(p->num_threads), numVpes(p->num_vpes)
{
miscRegFile.resize(NumMiscRegs);
bankType.resize(NumMiscRegs);
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index c601cfc1e..eddf75272 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -184,6 +184,13 @@ namespace MipsISA
{
return reg;
}
+
+ int
+ flattenMiscIndex(int reg)
+ {
+ return reg;
+ }
+
};
}
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 7b59b2ad1..028142b50 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -105,6 +105,12 @@ class ISA : public SimObject
return reg;
}
+ int
+ flattenMiscIndex(int reg)
+ {
+ return reg;
+ }
+
void startup(ThreadContext *tc) {}
/// Explicitly import the otherwise hidden startup
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index e6f023bc0..31cb09c7e 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -177,7 +177,6 @@ class ISA : public SimObject
using SimObject::startup;
protected:
-
bool isHyperPriv() { return hpstate.hpriv; }
bool isPriv() { return hpstate.hpriv || pstate.priv; }
bool isNonPriv() { return !isPriv(); }
@@ -213,6 +212,13 @@ class ISA : public SimObject
return reg;
}
+ int
+ flattenMiscIndex(int reg)
+ {
+ return reg;
+ }
+
+
typedef SparcISAParams Params;
const Params *params() const;
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 5f36fd7ad..14c8e98c9 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -91,6 +91,12 @@ namespace X86ISA
return reg;
}
+ int
+ flattenMiscIndex(int reg)
+ {
+ return reg;
+ }
+
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
void startup(ThreadContext *tc);
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index c06e03fc6..5c695c750 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -300,6 +300,7 @@ class CheckerThreadContext : public ThreadContext
int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); }
int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); }
int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); }
+ int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); }
unsigned readStCondFailures()
{ return actualTC->readStCondFailures(); }
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 5e1c65f8f..b1a361027 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -273,6 +273,9 @@ class InOrderThreadContext : public ThreadContext
int flattenCCIndex(int reg)
{ return cpu->isa[thread->threadId()]->flattenCCIndex(reg); }
+ int flattenMiscIndex(int reg)
+ { return cpu->isa[thread->threadId()]->flattenMiscIndex(reg); }
+
void activateContext(Cycles delay)
{ cpu->activateContext(thread->threadId(), delay); }
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 88cf75f4f..27f8e9561 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -244,6 +244,7 @@ class O3ThreadContext : public ThreadContext
virtual int flattenIntIndex(int reg);
virtual int flattenFloatIndex(int reg);
virtual int flattenCCIndex(int reg);
+ virtual int flattenMiscIndex(int reg);
/** Returns the number of consecutive store conditional failures. */
// @todo: Figure out where these store cond failures should go.
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index c818260f4..43e903135 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -292,6 +292,13 @@ O3ThreadContext<Impl>::flattenCCIndex(int reg)
}
template <class Impl>
+int
+O3ThreadContext<Impl>::flattenMiscIndex(int reg)
+{
+ return cpu->isa[thread->threadId()]->flattenMiscIndex(reg);
+}
+
+template <class Impl>
void
O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index fa0d20b0a..c5fae4e8e 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -415,6 +415,12 @@ class SimpleThread : public ThreadState
return isa->flattenCCIndex(reg);
}
+ int
+ flattenMiscIndex(int reg)
+ {
+ return isa->flattenMiscIndex(reg);
+ }
+
unsigned readStCondFailures() { return storeCondFailures; }
void setStCondFailures(unsigned sc_failures)
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index be18f680f..efd3cc800 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -235,6 +235,7 @@ class ThreadContext
virtual int flattenIntIndex(int reg) = 0;
virtual int flattenFloatIndex(int reg) = 0;
virtual int flattenCCIndex(int reg) = 0;
+ virtual int flattenMiscIndex(int reg) = 0;
virtual uint64_t
readRegOtherThread(int misc_reg, ThreadID tid)
@@ -451,6 +452,9 @@ class ProxyThreadContext : public ThreadContext
int flattenCCIndex(int reg)
{ return actualTC->flattenCCIndex(reg); }
+ int flattenMiscIndex(int reg)
+ { return actualTC->flattenMiscIndex(reg); }
+
unsigned readStCondFailures()
{ return actualTC->readStCondFailures(); }
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 07:38:22 +0000