diff options
| -rw-r--r-- | src/arch/x86/isa.cc | 25 | ||||
| -rw-r--r-- | src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py | 3 |
2 files changed, 14 insertions, 14 deletions
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc index eaedfbee3..9dd7fbb52 100644 --- a/src/arch/x86/isa.cc +++ b/src/arch/x86/isa.cc @@ -145,7 +145,7 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc) if (miscReg == MISCREG_FSW) { MiscReg fsw = regVal[MISCREG_FSW]; MiscReg top = regVal[MISCREG_X87_TOP]; - return (fsw & (~(7ULL << 11))) + (top << 11); + return insertBits(fsw, 11, 13, top); } return readMiscRegNoEffect(miscReg); @@ -159,41 +159,38 @@ ISA::setMiscRegNoEffect(int miscReg, MiscReg val) // attempt to write to them directly. assert(isValidMiscReg(miscReg)); - HandyM5Reg m5Reg = readMiscRegNoEffect(MISCREG_M5_REG); + HandyM5Reg m5Reg = regVal[MISCREG_M5_REG]; + int reg_width = 64; switch (miscReg) { - case MISCREG_FSW: - val &= (1ULL << 16) - 1; - regVal[miscReg] = val; - miscReg = MISCREG_X87_TOP; - val <<= 11; case MISCREG_X87_TOP: - val &= (1ULL << 3) - 1; + reg_width = 3; break; case MISCREG_FTW: - val &= (1ULL << 8) - 1; + reg_width = 8; break; + case MISCREG_FSW: case MISCREG_FCW: case MISCREG_FOP: - val &= (1ULL << 16) - 1; + reg_width = 16; break; case MISCREG_MXCSR: - val &= (1ULL << 32) - 1; + reg_width = 32; break; case MISCREG_FISEG: case MISCREG_FOSEG: if (m5Reg.submode != SixtyFourBitMode) - val &= (1ULL << 16) - 1; + reg_width = 16; break; case MISCREG_FIOFF: case MISCREG_FOOFF: if (m5Reg.submode != SixtyFourBitMode) - val &= (1ULL << 32) - 1; + reg_width = 32; break; default: break; } - regVal[miscReg] = val; + regVal[miscReg] = val & mask(reg_width); } void diff --git a/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py index 20ecff43a..ffc490715 100644 --- a/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py +++ b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py @@ -63,6 +63,9 @@ fnstenvTemplate = """ # FSW includes TOP when read rdval t1, fsw st t1, seg, %(mode)s, "DISPLACEMENT + 4", dataSize=2 + srli t1, t1, 11, dataSize=2 + andi t1, t1, 0x7, dataSize=2 + wrval "InstRegIndex(MISCREG_X87_TOP)", t1 rdval t1, ftw st t1, seg, %(mode)s, "DISPLACEMENT + 8", dataSize=2 |