diff options
502 files changed, 20237 insertions, 4167 deletions
diff --git a/.hgtags b/.hgtags new file mode 100644 index 000000000..43760085a --- /dev/null +++ b/.hgtags @@ -0,0 +1,16 @@ +6b99127531fd692ff0f202e327d0826ed2bfcf5f m5_1.0_beta1 +1a40e60270c11ec24f11c783e70367e2740cdc56 m5_1.0_beta1 +069849384988e553b6edae71ecaf1fb6e918d738 m5_1.0_beta2 +4cfa92eca35d532b339507f1c631e1986d87b258 m5_1.0_tutorial +ffe1942d845c67fb3fd04692420c9433638eba13 m5_1.0_web +af8bf5e4e85ba1a773183cc3f6c43bcdf0ce146a m5_1.1 +1c0eeb0dae9b6a2a5479faf3ab52fb1ed0ce703f m5_1.1 +c486924ed90eb6805e8cf44ddee5ad5435c79051 m5_1.1 +01e679b66ca9474f10f8f96d391693adf76fc73a m5_1.1 +2608cd7def85c9fdc84251295c8023fab990d530 m5_1.1 +cdd48642d9bf584bd445b40abec9e7f934a5900b m5_1.1 +8d690c7c2efced99f7991b7ace56d769bae7cfdd m5_2.0_beta1 +d83885ad2b41777c97b94882aa8f07e761e55ac1 m5_2.0_beta1_patch1 +1906dcace7c27b2153bfb95ca1218660e1cc1f70 m5_2.0_beta2 +b174ae14f007ba0c341f8df77d36f57f48369cc8 m5_2.0_beta2 +91a9ac67662aa3a79315ade29b17a85961fecd88 m5_2.0_beta3 @@ -20,6 +20,7 @@ Steven K. Reinhardt * ISA parsing * SWIG intergration * New memory system +* New Caches * Simple CPU * Instruction tracing * PC sampling @@ -1,4 +1,4 @@ -This is release 2.0_beta (patch 1) of the M5 simulator. +This is release 2.0_beta4 of the M5 simulator. For detailed information about building the simulator and getting started please refer to http://www.m5sim.org. @@ -29,7 +29,6 @@ The basic source release includes these subdirectories: - src: source code of the m5 simulator - tests: regression tests - ext: less-common external packages needed to build m5 - - system/alpha: source for Alpha console and PALcode To run full-system simulations, you will need compiled console, PALcode, and kernel binaries and one or more disk images. These files @@ -40,4 +39,4 @@ M5 supports Linux 2.4/2.6, FreeBSD, and the proprietary Compaq/HP Tru64 version of Unix. We are able to distribute Linux and FreeBSD bootdisks, but we are unable to distribute bootable disk images of Tru64 Unix. If you have a Tru64 license and are interested in -obtaining disk images, contact us at m5-dev@eecs.umich.edu. +obtaining disk images, contact us at m5-users@m5sim.org diff --git a/RELEASE_NOTES b/RELEASE_NOTES index e91f5432d..103bc0b7a 100644 --- a/RELEASE_NOTES +++ b/RELEASE_NOTES @@ -1,17 +1,30 @@ Outstanding issues for 2.0 release: -------------------- -1. Fix multi-level coherence/dma issues -2. Fix O3 CPU bug in SE 40.perlbmk fails -3. Fix O3 processing nacks/coherence messages -4. Better statistics for the caches. -5. Clean up more SimObject parameter stuff -6. Checkpoint/switchover testing -7. FS mode doesn't work under Cygwin -8. memtest regression crashes under Cygwin -9. Make repository public -10. Testing -11. Validation -12. Testing +1. Fix O3 CPU bug in SE 40.perlbmk fails +2. Fix O3 processing nacks/coherence messages +3. Better statistics for the caches. +4. FS mode doesn't work under Cygwin +5. memtest regression crashes under Cygwin +6. Make repository public +7. Testing +8. Validation +9. Testing + +Nov XX, 2007: m5_2.0_beta4 +-------------------- +New Features +1. New cache +2. Ability to include compiled code with EXTRAS= +3. Python creation of params structures for initialization +4. Ability to remotely debug in SE + +Bug fixes: +1. Fix SE serialization +2. SPARC_FS booting with TimingSimpleCPU +3. Rename cycles() to ticks() +4. Various SPARC ISA fixes +5. Draining code for checkpointing +6. Various performance improvements May 16, 2007: m5_2.0_beta3 -------------------- diff --git a/build_opts/X86_FS b/build_opts/X86_FS new file mode 100644 index 000000000..7cc6847f2 --- /dev/null +++ b/build_opts/X86_FS @@ -0,0 +1,3 @@ +TARGET_ISA = 'x86' +CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU' +FULL_SYSTEM = 1 diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 2ab214dc5..78be4fc3a 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -118,6 +118,25 @@ def makeSparcSystem(mem_mode, mdesc = None): return self +def makeX86System(mem_mode, mdesc = None): + self = X86System() + if not mdesc: + # generic system + mdesc = SysConfig() + self.readfile = mdesc.script() + + # Physical memory + self.membus = Bus(bus_id=0) + self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) + self.physmem.port = self.membus.port + + # Platform + self.opteron = Opteron() + + self.intrctrl = IntrControl() + + return self + def makeDualRoot(testSystem, driveSystem, dumpfile): self = Root() diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index c65597367..6b585d8c3 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -192,7 +192,7 @@ def run(options, root, testsys, cpu_class): sim_ticks = when exit_cause = "maximum %d checkpoints dropped" % max_checkpoints while num_checkpoints < max_checkpoints and \ - exit_event.getCause() != "user interrupt received": + exit_event.getCause() == "simulate() limit reached": if (sim_ticks + period) > maxtick: exit_event = m5.simulate(maxtick - sim_ticks) exit_cause = exit_event.getCause() @@ -206,7 +206,7 @@ def run(options, root, testsys, cpu_class): m5.checkpoint(root, joinpath(cptdir, "cpt.%d")) num_checkpoints += 1 - if exit_event.getCause() == "user interrupt received": + if exit_event.getCause() != "simulate() limit reached": exit_cause = exit_event.getCause(); diff --git a/configs/example/fs.py b/configs/example/fs.py index 3a57fe5b8..74ee875a3 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -99,6 +99,8 @@ if m5.build_env['TARGET_ISA'] == "alpha": test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) elif m5.build_env['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0]) +elif m5.build_env['TARGET_ISA'] == "x86": + test_sys = makeX86System(test_mem_mode, bm[0]) else: m5.panic("incapable of building non-alpha or non-sparc full system!") @@ -117,16 +119,19 @@ if options.l2cache: test_sys.l2.mem_side = test_sys.membus.port test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] + +if options.caches: + test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] + test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] + test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)], + cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]) + test_sys.iocache.cpu_side = test_sys.iobus.port + test_sys.iocache.mem_side = test_sys.membus.port + for i in xrange(np): if options.caches: test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) - test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] - test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] - test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)], - cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]) - test_sys.iocache.cpu_side = test_sys.iobus.port - test_sys.iocache.mem_side = test_sys.membus.port if options.l2cache: test_sys.cpu[i].connectMemPorts(test_sys.tol2bus) else: @@ -140,6 +145,8 @@ if len(bm) == 2: drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) elif m5.build_env['TARGET_ISA'] == 'sparc': drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) + elif m5.build.env['TARGET_ISA'] == 'x86': + drive_sys = makeX86System(drive_mem_mode, bm[1]) drive_sys.cpu = DriveCPUClass(cpu_id=0) drive_sys.cpu.connectMemPorts(drive_sys.membus) if options.fastmem: diff --git a/src/SConscript b/src/SConscript index a2df88c06..e66a725d3 100644 --- a/src/SConscript +++ b/src/SConscript @@ -135,6 +135,38 @@ Export('SwigSource') ######################################################################## # +# Trace Flags +# +all_flags = {} +trace_flags = [] +def TraceFlag(name, desc=''): + if name in all_flags: + raise AttributeError, "Flag %s already specified" % name + flag = (name, (), desc) + trace_flags.append(flag) + all_flags[name] = () + +def CompoundFlag(name, flags, desc=''): + if name in all_flags: + raise AttributeError, "Flag %s already specified" % name + + compound = tuple(flags) + for flag in compound: + if flag not in all_flags: + raise AttributeError, "Trace flag %s not found" % flag + if all_flags[flag]: + raise AttributeError, \ + "Compound flag can't point to another compound flag" + + flag = (name, compound, desc) + trace_flags.append(flag) + all_flags[name] = compound + +Export('TraceFlag') +Export('CompoundFlag') + +######################################################################## +# # Set some compiler variables # @@ -307,6 +339,15 @@ for source,package in swig_sources: env.Command('swig/init.cc', swig_modules, generate.makeSwigInit) Source('swig/init.cc') +# Generate traceflags.py +flags = [ Value(f) for f in trace_flags ] +env.Command('base/traceflags.py', flags, generate.traceFlagsPy) +PySource('m5', 'base/traceflags.py') + +env.Command('base/traceflags.hh', flags, generate.traceFlagsHH) +env.Command('base/traceflags.cc', flags, generate.traceFlagsCC) +Source('base/traceflags.cc') + # Build the zip file py_compiled = [] py_zip_depends = [] diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript index 04bac3996..ca20cf585 100644 --- a/src/arch/alpha/SConscript +++ b/src/arch/alpha/SConscript @@ -75,3 +75,5 @@ if env['TARGET_ISA'] == 'alpha': for f in isa_desc_files: if not f.path.endswith('.hh'): Source(f) + + TraceFlag('Context') diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc index 7d4de902a..20591b357 100644 --- a/src/arch/alpha/faults.cc +++ b/src/arch/alpha/faults.cc @@ -177,25 +177,12 @@ void ItbFault::invoke(ThreadContext * tc) void ItbPageFault::invoke(ThreadContext * tc) { Process *p = tc->getProcessPtr(); - Addr physaddr; - bool success = p->pTable->translate(pc, physaddr); + TlbEntry entry; + bool success = p->pTable->lookup(pc, entry); if(!success) { panic("Tried to execute unmapped address %#x.\n", pc); } else { VAddr vaddr(pc); - VAddr paddr(physaddr); - - TlbEntry entry; - entry.tag = vaddr.vpn(); - entry.ppn = paddr.vpn(); - entry.xre = 15; //This can be read in all modes. - entry.xwe = 1; //This can be written only in kernel mode. - entry.asn = p->M5_pid; //Address space number. - entry.asma = false; //Only match on this ASN. - entry.fonr = false; //Don't fault on read. - entry.fonw = false; //Don't fault on write. - entry.valid = true; //This entry is valid. - tc->getITBPtr()->insert(vaddr.page(), entry); } } @@ -203,28 +190,15 @@ void ItbPageFault::invoke(ThreadContext * tc) void NDtbMissFault::invoke(ThreadContext * tc) { Process *p = tc->getProcessPtr(); - Addr physaddr; - bool success = p->pTable->translate(vaddr, physaddr); + TlbEntry entry; + bool success = p->pTable->lookup(vaddr, entry); if(!success) { p->checkAndAllocNextPage(vaddr); - success = p->pTable->translate(vaddr, physaddr); + success = p->pTable->lookup(vaddr, entry); } if(!success) { panic("Tried to access unmapped address %#x.\n", (Addr)vaddr); } else { - VAddr paddr(physaddr); - - TlbEntry entry; - entry.tag = vaddr.vpn(); - entry.ppn = paddr.vpn(); - entry.xre = 15; //This can be read in all modes. - entry.xwe = 15; //This can be written in all modes. - entry.asn = p->M5_pid; //Address space number. - entry.asma = false; //Only match on this ASN. - entry.fonr = false; //Don't fault on read. - entry.fonw = false; //Don't fault on write. - entry.valid = true; //This entry is valid. - tc->getDTBPtr()->insert(vaddr.page(), entry); } } diff --git a/src/arch/alpha/kernel_stats.cc b/src/arch/alpha/kernel_stats.cc index 13dc95af7..a004d5f25 100644 --- a/src/arch/alpha/kernel_stats.cc +++ b/src/arch/alpha/kernel_stats.cc @@ -33,6 +33,7 @@ #include <stack> #include <string> +#include "arch/alpha/linux/threadinfo.hh" #include "arch/alpha/kernel_stats.hh" #include "arch/alpha/osfpal.hh" #include "base/trace.hh" @@ -137,8 +138,9 @@ Statistics::changeMode(cpu_mode newmode, ThreadContext *tc) if (newmode == themode) return; - DPRINTF(Context, "old mode=%-8s new mode=%-8s\n", - modestr[themode], modestr[newmode]); + DPRINTF(Context, "old mode=%s new mode=%s pid=%d\n", + modestr[themode], modestr[newmode], + Linux::ThreadInfo(tc).curTaskPID()); _modeGood[newmode]++; _modeTicks[themode] += curTick - lastModeTick; @@ -165,6 +167,10 @@ Statistics::context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc) _swap_context++; changeMode(newpcbb == idleProcess ? idle : kernel, tc); + + DPRINTF(Context, "Context Switch old pid=%d new pid=%d\n", + Linux::ThreadInfo(tc, oldpcbb).curTaskPID(), + Linux::ThreadInfo(tc, newpcbb).curTaskPID()); } void diff --git a/src/arch/alpha/linux/hwrpb.hh b/src/arch/alpha/linux/hwrpb.hh deleted file mode 100644 index 869ce026b..000000000 --- a/src/arch/alpha/linux/hwrpb.hh +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright 1990 Hewlett-Packard Development Company, L.P. - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, copy, - * modify, merge, publish, distribute, sublicense, and/or sell copies - * of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS - * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN - * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ - -#ifndef __ARCH_ALPHA_LINUX_HWRPB_HH__ -#define __ARCH_ALPHA_LINUX_HWRPB_HH__ - -#include "arch/alpha/linux/aligned.hh" - -namespace Linux { - struct pcb_struct { - uint64_ta rpb_ksp; - uint64_ta rpb_usp; - uint64_ta rpb_ptbr; - uint32_t rpb_cc; - uint32_t rpb_psn; - uint64_ta rpb_unique; - uint64_ta rpb_fen; - uint64_ta res1, res2; - }; -} -#endif // __ARCH_ALPHA_LINUX_HWRPB_HH__ diff --git a/src/arch/alpha/linux/process.cc b/src/arch/alpha/linux/process.cc index b638aa927..ec47992bd 100644 --- a/src/arch/alpha/linux/process.cc +++ b/src/arch/alpha/linux/process.cc @@ -568,23 +568,9 @@ SyscallDesc AlphaLinuxProcess::syscallDescs[] = { /* 441 */ SyscallDesc("keyctl", unimplementedFunc) }; -AlphaLinuxProcess::AlphaLinuxProcess(const std::string &name, - ObjectFile *objFile, - System *system, - int stdin_fd, - int stdout_fd, - int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, - uint64_t _euid, - uint64_t _gid, - uint64_t _egid, - uint64_t _pid, - uint64_t _ppid) - : AlphaLiveProcess(name, objFile, system, stdin_fd, stdout_fd, - stderr_fd, argv, envp, cwd, _uid, _euid, _gid, _egid, _pid, _ppid), +AlphaLinuxProcess::AlphaLinuxProcess(LiveProcessParams * params, + ObjectFile *objFile) + : AlphaLiveProcess(params, objFile), Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)) { //init_regs->intRegFile[0] = 0; diff --git a/src/arch/alpha/linux/process.hh b/src/arch/alpha/linux/process.hh index cb22f521b..8d7c24e37 100644 --- a/src/arch/alpha/linux/process.hh +++ b/src/arch/alpha/linux/process.hh @@ -40,16 +40,7 @@ class AlphaLinuxProcess : public AlphaLiveProcess { public: /// Constructor. - AlphaLinuxProcess(const std::string &name, - ObjectFile *objFile, - System *system, - int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid); + AlphaLinuxProcess(LiveProcessParams * params, ObjectFile *objFile); virtual SyscallDesc* getDesc(int callnum); diff --git a/src/arch/alpha/linux/thread_info.hh b/src/arch/alpha/linux/thread_info.hh deleted file mode 100644 index 78257da56..000000000 --- a/src/arch/alpha/linux/thread_info.hh +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Nathan Binkert - */ - -#ifndef __ARCH_ALPHA_LINUX_THREAD_INFO_H__ -#define __ARCH_ALPHA_LINUX_THREAD_INFO_H__ - -#include "arch/alpha/linux/hwrpb.hh" - -namespace Linux { - struct thread_info { - struct pcb_struct pcb; - Addr_a task; - }; -} - -#endif // __ARCH_ALPHA_LINUX_THREAD_INFO_H__ diff --git a/src/arch/alpha/linux/threadinfo.hh b/src/arch/alpha/linux/threadinfo.hh index b9ffe02ae..b0c8284be 100644 --- a/src/arch/alpha/linux/threadinfo.hh +++ b/src/arch/alpha/linux/threadinfo.hh @@ -32,9 +32,8 @@ #ifndef __ARCH_ALPHA_LINUX_LINUX_TREADNIFO_HH__ #define __ARCH_ALPHA_LINUX_LINUX_TREADNIFO_HH__ -#include "arch/alpha/linux/thread_info.hh" #include "cpu/thread_context.hh" -#include "kern/linux/sched.hh" +#include "sim/system.hh" #include "sim/vptr.hh" namespace Linux { @@ -43,47 +42,108 @@ class ThreadInfo { private: ThreadContext *tc; + System *sys; + Addr pcbb; + + template <typename T> + bool + get_data(const char *symbol, T &data) + { + Addr addr = 0; + if (!sys->kernelSymtab->findAddress(symbol, addr)) + return false; + + CopyOut(tc, &data, addr, sizeof(T)); + + data = TheISA::gtoh(data); + + return true; + } public: - ThreadInfo(ThreadContext *_tc) : tc(_tc) {} - ~ThreadInfo() {} + ThreadInfo(ThreadContext *_tc, Addr _pcbb = 0) + : tc(_tc), sys(tc->getSystemPtr()), pcbb(_pcbb) + { - inline VPtr<thread_info> + } + ~ThreadInfo() + {} + + inline Addr curThreadInfo() { - Addr current; - - /* Each kernel stack is only 2 pages, the start of which is the - * thread_info struct. So we can get the address by masking off - * the lower 14 bits. - */ - current = tc->readIntReg(TheISA::StackPointerReg) & ~ULL(0x3fff); - return VPtr<thread_info>(tc, current); + Addr addr = pcbb; + Addr sp; + + if (!addr) + addr = tc->readMiscRegNoEffect(TheISA::IPR_PALtemp23); + + FunctionalPort *p = tc->getPhysPort(); + p->readBlob(addr, (uint8_t *)&sp, sizeof(Addr)); + + return sp & ~ULL(0x3fff); } - inline VPtr<task_struct> - curTaskInfo() + inline Addr + curTaskInfo(Addr thread_info = 0) { - Addr task = curThreadInfo()->task; - return VPtr<task_struct>(tc, task); + int32_t offset; + if (!get_data("thread_info_task", offset)) + return 0; + + if (!thread_info) + thread_info = curThreadInfo(); + + Addr addr; + CopyOut(tc, &addr, thread_info + offset, sizeof(addr)); + + return addr; } - std::string - curTaskName() + int32_t + curTaskPID(Addr thread_info = 0) { - return curTaskInfo()->name; + Addr offset; + if (!get_data("task_struct_pid", offset)) + return -1; + + int32_t pid; + CopyOut(tc, &pid, curTaskInfo(thread_info) + offset, sizeof(pid)); + + return pid; } - int32_t - curTaskPID() + int64_t + curTaskStart(Addr thread_info = 0) { - return curTaskInfo()->pid; + Addr offset; + if (!get_data("task_struct_start_time", offset)) + return -1; + + int64_t data; + // start_time is actually of type timespec, but if we just + // grab the first long, we'll get the seconds out of it + CopyOut(tc, &data, curTaskInfo(thread_info) + offset, sizeof(data)); + + return data; } - uint64_t - curTaskStart() + std::string + curTaskName(Addr thread_info = 0) { - return curTaskInfo()->start; + int32_t offset; + int32_t size; + + if (!get_data("task_struct_comm", offset)) + return "FailureIn_curTaskName"; + + if (!get_data("task_struct_comm_size", size)) + return "FailureIn_curTaskName"; + + char buffer[size + 1]; + CopyStringOut(tc, buffer, curTaskInfo(thread_info) + offset, size); + + return buffer; } }; diff --git a/src/arch/alpha/pagetable.hh b/src/arch/alpha/pagetable.hh index 4375f24f1..8ce5b4e5d 100644 --- a/src/arch/alpha/pagetable.hh +++ b/src/arch/alpha/pagetable.hh @@ -92,10 +92,21 @@ namespace AlphaISA { // ITB/DTB table entry struct TlbEntry { - Addr pageStart; //Construct an entry that maps to physical address addr. - TlbEntry(Addr addr) : pageStart(addr) - {} + TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr) + { + VAddr vaddr(_vaddr); + VAddr paddr(_paddr); + tag = vaddr.vpn(); + ppn = paddr.vpn(); + xre = 15; + xwe = 15; + asn = _asn; + asma = false; + fonr = false; + fonw = false; + valid = true; + } TlbEntry() {} @@ -109,6 +120,11 @@ namespace AlphaISA { bool fonw; // fault on write bool valid; // valid page table entry + Addr pageStart() + { + return ppn << PageShift; + } + void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); }; diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh index 4887de856..7a6bb3c02 100644 --- a/src/arch/alpha/predecoder.hh +++ b/src/arch/alpha/predecoder.hh @@ -65,6 +65,9 @@ namespace AlphaISA { } + void reset() + {} + //Use this to give data to the predecoder. This should be used //when there is control flow. void moreBytes(Addr pc, Addr fetchPC, MachInst inst) diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc index a9848ebb5..c2d23ecdd 100644 --- a/src/arch/alpha/process.cc +++ b/src/arch/alpha/process.cc @@ -40,14 +40,9 @@ using namespace AlphaISA; using namespace std; -AlphaLiveProcess::AlphaLiveProcess(const std::string &nm, ObjectFile *objFile, - System *_system, int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid) - : LiveProcess(nm, objFile, _system, stdin_fd, stdout_fd, stderr_fd, - argv, envp, cwd, _uid, _euid, _gid, _egid, _pid, _ppid) +AlphaLiveProcess::AlphaLiveProcess(LiveProcessParams * params, + ObjectFile *objFile) + : LiveProcess(params, objFile) { brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); brk_point = roundUp(brk_point, VMPageSize); @@ -68,6 +63,9 @@ AlphaLiveProcess::AlphaLiveProcess(const std::string &nm, ObjectFile *objFile, void AlphaLiveProcess::startup() { + if (checkpointRestored) + return; + argsInit(MachineBytes, VMPageSize); threadContexts[0]->setIntReg(GlobalPointerReg, objFile->globalPointer()); diff --git a/src/arch/alpha/process.hh b/src/arch/alpha/process.hh index 8eede502a..c66b97d23 100644 --- a/src/arch/alpha/process.hh +++ b/src/arch/alpha/process.hh @@ -43,14 +43,7 @@ class System; class AlphaLiveProcess : public LiveProcess { protected: - AlphaLiveProcess(const std::string &nm, ObjectFile *objFile, - System *_system, int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid); + AlphaLiveProcess(LiveProcessParams * params, ObjectFile *objFile); void startup(); }; diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index b93707181..792a518fb 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -192,6 +192,11 @@ namespace AlphaISA return reg; } + static inline int flattenFloatIndex(ThreadContext * tc, int reg) + { + return reg; + } + void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); diff --git a/src/arch/alpha/tru64/process.cc b/src/arch/alpha/tru64/process.cc index a1f02b16c..6823d820a 100644 --- a/src/arch/alpha/tru64/process.cc +++ b/src/arch/alpha/tru64/process.cc @@ -573,20 +573,9 @@ AlphaTru64Process::getDesc(int callnum) } -AlphaTru64Process::AlphaTru64Process(const std::string &name, - ObjectFile *objFile, - System *system, - int stdin_fd, - int stdout_fd, - int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid) - : AlphaLiveProcess(name, objFile, system, stdin_fd, stdout_fd, - stderr_fd, argv, envp, cwd, _uid, _euid, _gid, _egid, _pid, _ppid), +AlphaTru64Process::AlphaTru64Process(LiveProcessParams * params, + ObjectFile *objFile) + : AlphaLiveProcess(params, objFile), Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)), Num_Mach_Syscall_Descs(sizeof(machSyscallDescs) / sizeof(SyscallDesc)) { diff --git a/src/arch/alpha/tru64/process.hh b/src/arch/alpha/tru64/process.hh index f5643c0b9..16bc499c6 100644 --- a/src/arch/alpha/tru64/process.hh +++ b/src/arch/alpha/tru64/process.hh @@ -39,16 +39,8 @@ class AlphaTru64Process : public AlphaLiveProcess { public: /// Constructor. - AlphaTru64Process(const std::string &name, - ObjectFile *objFile, - System *system, - int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid); + AlphaTru64Process(LiveProcessParams * params, + ObjectFile *objFile); /// Array of syscall descriptors, indexed by call number. static SyscallDesc syscallDescs[]; diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index e1d2146eb..f4be39eca 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -43,6 +43,8 @@ if env['TARGET_ISA'] == 'mips': SimObject('MipsTLB.py') + TraceFlag('MipsPRA') + if env['FULL_SYSTEM']: #Insert Full-System Files Here pass diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc index 283088cb2..425ef9ac3 100644 --- a/src/arch/mips/linux/process.cc +++ b/src/arch/mips/linux/process.cc @@ -405,23 +405,9 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = { }; -MipsLinuxProcess::MipsLinuxProcess(const std::string &name, - ObjectFile *objFile, - System *system, - int stdin_fd, - int stdout_fd, - int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, - uint64_t _euid, - uint64_t _gid, - uint64_t _egid, - uint64_t _pid, - uint64_t _ppid) - : MipsLiveProcess(name, objFile, system, stdin_fd, stdout_fd, stderr_fd, - argv, envp, cwd, _uid, _euid, _gid, _egid, _pid, _ppid), +MipsLinuxProcess::MipsLinuxProcess(LiveProcessParams * params, + ObjectFile *objFile) + : MipsLiveProcess(params, objFile), Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)) { } diff --git a/src/arch/mips/linux/process.hh b/src/arch/mips/linux/process.hh index d18c96188..a1e738d61 100644 --- a/src/arch/mips/linux/process.hh +++ b/src/arch/mips/linux/process.hh @@ -38,16 +38,7 @@ class MipsLinuxProcess : public MipsLiveProcess { public: /// Constructor. - MipsLinuxProcess(const std::string &name, - ObjectFile *objFile, - System *system, - int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid); + MipsLinuxProcess(LiveProcessParams * params, ObjectFile *objFile); void startup(); diff --git a/src/arch/mips/predecoder.hh b/src/arch/mips/predecoder.hh index e310dded4..17da15f3f 100644 --- a/src/arch/mips/predecoder.hh +++ b/src/arch/mips/predecoder.hh @@ -64,6 +64,9 @@ namespace MipsISA { } + void reset() + {} + //Use this to give data to the predecoder. This should be used //when there is control flow. void moreBytes(Addr pc, Addr fetchPC, MachInst inst) diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc index d1e6e27bf..d330b1913 100644 --- a/src/arch/mips/process.cc +++ b/src/arch/mips/process.cc @@ -41,14 +41,9 @@ using namespace std; using namespace MipsISA; -MipsLiveProcess::MipsLiveProcess(const std::string &nm, ObjectFile *objFile, - System *_system, int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid) - : LiveProcess(nm, objFile, _system, stdin_fd, stdout_fd, stderr_fd, - argv, envp, cwd, _uid, _euid, _gid, _egid, _pid, _ppid) +MipsLiveProcess::MipsLiveProcess(LiveProcessParams * params, + ObjectFile *objFile) + : LiveProcess(params, objFile) { // Set up stack. On MIPS, stack starts at the top of kuseg // user address space. MIPS stack grows down from here @@ -68,5 +63,8 @@ MipsLiveProcess::MipsLiveProcess(const std::string &nm, ObjectFile *objFile, void MipsLiveProcess::startup() { + if (checkpointRestored) + return; + argsInit(MachineBytes, VMPageSize); } diff --git a/src/arch/mips/process.hh b/src/arch/mips/process.hh index b6249f76d..350a5bed9 100644 --- a/src/arch/mips/process.hh +++ b/src/arch/mips/process.hh @@ -44,14 +44,7 @@ class System; class MipsLiveProcess : public LiveProcess { protected: - MipsLiveProcess(const std::string &nm, ObjectFile *objFile, - System *_system, int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid); + MipsLiveProcess(LiveProcessParams * params, ObjectFile *objFile); virtual void startup(); diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc index 02e9c92bb..82f284ec4 100755 --- a/src/arch/mips/regfile/misc_regfile.cc +++ b/src/arch/mips/regfile/misc_regfile.cc @@ -304,7 +304,7 @@ MiscRegFile::scheduleCP0Update(int delay) //schedule UPDATE CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0); - cp0_event->schedule(curTick + cpu->cycles(delay)); + cp0_event->schedule(curTick + cpu->ticks(delay)); } } @@ -364,9 +364,9 @@ void MiscRegFile::CP0Event::scheduleEvent(int delay) { if (squashed()) - reschedule(curTick + cpu->cycles(delay)); + reschedule(curTick + cpu->ticks(delay)); else if (!scheduled()) - schedule(curTick + cpu->cycles(delay)); + schedule(curTick + cpu->ticks(delay)); } void diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh index b83bb576b..4be8d399c 100644 --- a/src/arch/mips/regfile/regfile.hh +++ b/src/arch/mips/regfile/regfile.hh @@ -187,6 +187,11 @@ namespace MipsISA return reg; } + static inline int flattenFloatIndex(ThreadContext * tc, int reg) + { + return reg; + } + void copyRegs(ThreadContext *src, ThreadContext *dest); diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc index b644ae18d..a911e3c0b 100644 --- a/src/arch/mips/tlb.cc +++ b/src/arch/mips/tlb.cc @@ -54,13 +54,13 @@ namespace MipsISA { void TlbEntry::serialize(std::ostream &os) { - SERIALIZE_SCALAR(pageStart); + SERIALIZE_SCALAR(_pageStart); } void TlbEntry::unserialize(Checkpoint *cp, const std::string §ion) { - UNSERIALIZE_SCALAR(pageStart); + UNSERIALIZE_SCALAR(_pageStart); } }; diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh index 78b4af94d..cff805bef 100644 --- a/src/arch/mips/tlb.hh +++ b/src/arch/mips/tlb.hh @@ -39,9 +39,14 @@ namespace MipsISA { struct TlbEntry { - Addr pageStart; + Addr _pageStart; TlbEntry() {} - TlbEntry(Addr paddr) : pageStart(paddr) {} + TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {} + + Addr pageStart() + { + return _pageStart; + } void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index 81e96a8d6..a86c00250 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -44,6 +44,7 @@ if env['TARGET_ISA'] == 'sparc': Source('utility.cc') SimObject('SparcTLB.py') + TraceFlag('Sparc') if env['FULL_SYSTEM']: SimObject('SparcSystem.py') diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 07d332b58..e201cef95 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -623,64 +623,32 @@ void PowerOnReset::invoke(ThreadContext * tc) void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc) { Process *p = tc->getProcessPtr(); - Addr paddr; - bool success = p->pTable->translate(vaddr, paddr); + TlbEntry entry; + bool success = p->pTable->lookup(vaddr, entry); if(!success) { panic("Tried to execute unmapped address %#x.\n", vaddr); } else { - - uint64_t entry = 0; - entry |= 0ULL << 1; // Not writable - entry |= 0ULL << 2; // Available in nonpriveleged mode - entry |= 0ULL << 3; // No side effects - entry |= 1ULL << 4; // Virtually cachable - entry |= 1ULL << 5; // Physically cachable - entry |= 0ULL << 6; // Not locked - entry |= mbits(paddr, 39, 13); // Physical address - entry |= 0ULL << 48; // size = 8k - entry |= 0uLL << 59; // Endianness not inverted - entry |= 0ULL << 60; // Not no fault only - entry |= 0ULL << 61; // size = 8k - entry |= 1ULL << 63; // valid - PageTableEntry PTE(entry); - Addr alignedVaddr = p->pTable->pageAlign(vaddr); tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/, - p->M5_pid /*context id*/, false, PTE); + p->M5_pid /*context id*/, false, entry.pte); } } void FastDataAccessMMUMiss::invoke(ThreadContext *tc) { Process *p = tc->getProcessPtr(); - Addr paddr; - bool success = p->pTable->translate(vaddr, paddr); + TlbEntry entry; + bool success = p->pTable->lookup(vaddr, entry); if(!success) { p->checkAndAllocNextPage(vaddr); - success = p->pTable->translate(vaddr, paddr); + success = p->pTable->lookup(vaddr, entry); } if(!success) { panic("Tried to access unmapped address %#x.\n", vaddr); } else { - - uint64_t entry = 0; - entry |= 1ULL << 1; // Writable - entry |= 0ULL << 2; // Available in nonpriveleged mode - entry |= 0ULL << 3; // No side effects - entry |= 1ULL << 4; // Virtually cachable - entry |= 1ULL << 5; // Physically cachable - entry |= 0ULL << 6; // Not locked - entry |= mbits(paddr, 39, 13); // Physical address - entry |= 0ULL << 48; // size = 8k - entry |= 0uLL << 59; // Endianness not inverted - entry |= 0ULL << 60; // Not no fault only - entry |= 0ULL << 61; // size = 8k - entry |= 1ULL << 63; // valid - PageTableEntry PTE(entry); - Addr alignedVaddr = p->pTable->pageAlign(vaddr); tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/, - p->M5_pid /*context id*/, false, PTE); + p->M5_pid /*context id*/, false, entry.pte); } } diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 14c652606..c35b231ff 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -45,116 +45,49 @@ decode OP default Unknown::unknown() 0x1: decode COND2 { //Branch Always - 0x8: decode A - { - 0x0: bpa(19, {{ - NNPC = xc->readPC() + disp; - }}); - 0x1: bpa(19, {{ - NPC = xc->readPC() + disp; - NNPC = NPC + 4; - }}, ',a'); - } + 0x8: bpa(19, annul_code={{ + NPC = xc->readPC() + disp; + NNPC = NPC + 4; + }}); //Branch Never - 0x0: decode A - { - 0x0: bpn(19, {{ - NNPC = NNPC;//Don't do anything - }}); - 0x1: bpn(19, {{ - NNPC = NPC + 8; - NPC = NPC + 4; - }}, ',a'); - } + 0x0: bpn(19, {{;}}, + annul_code={{ + NNPC = NPC + 8; + NPC = NPC + 4; + }}); default: decode BPCC { - 0x0: bpcci(19, {{ - if(passesCondition(Ccr<3:0>, COND2)) - NNPC = xc->readPC() + disp; - else - handle_annul - }}); - 0x2: bpccx(19, {{ - if(passesCondition(Ccr<7:4>, COND2)) - NNPC = xc->readPC() + disp; - else - handle_annul - }}); + 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}}); + 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}}); } } //bicc 0x2: decode COND2 { //Branch Always - 0x8: decode A - { - 0x0: ba(22, {{ - NNPC = xc->readPC() + disp; - }}); - 0x1: ba(22, {{ - NPC = xc->readPC() + disp; - NNPC = NPC + 4; - }}, ',a'); - } + 0x8: ba(22, annul_code={{ + NPC = xc->readPC() + disp; + NNPC = NPC + 4; + }}); //Branch Never - 0x0: decode A - { - 0x0: bn(22, {{ - NNPC = NNPC;//Don't do anything - }}); - 0x1: bn(22, {{ - NNPC = NPC + 8; - NPC = NPC + 4; - }}, ',a'); - } - default: bicc(22, {{ - if(passesCondition(Ccr<3:0>, COND2)) - NNPC = xc->readPC() + disp; - else - handle_annul - }}); + 0x0: bn(22, {{;}}, + annul_code={{ + NNPC = NPC + 8; + NPC = NPC + 4; + }}); + default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}}); } } 0x3: decode RCOND2 { format BranchSplit { - 0x1: bpreq({{ - if(Rs1.sdw == 0) - NNPC = xc->readPC() + disp; - else - handle_annul - }}); - 0x2: bprle({{ - if(Rs1.sdw <= 0) - NNPC = xc->readPC() + disp; - else - handle_annul - }}); - 0x3: bprl({{ - if(Rs1.sdw < 0) - NNPC = xc->readPC() + disp; - else - handle_annul - }}); - 0x5: bprne({{ - if(Rs1.sdw != 0) - NNPC = xc->readPC() + disp; - else - handle_annul - }}); - 0x6: bprg({{ - if(Rs1.sdw > 0) - NNPC = xc->readPC() + disp; - else - handle_annul - }}); - 0x7: bprge({{ - if(Rs1.sdw >= 0) - NNPC = xc->readPC() + disp; - else - handle_annul - }}); + 0x1: bpreq(test={{Rs1.sdw == 0}}); + 0x2: bprle(test={{Rs1.sdw <= 0}}); + 0x3: bprl(test={{Rs1.sdw < 0}}); + 0x5: bprne(test={{Rs1.sdw != 0}}); + 0x6: bprg(test={{Rs1.sdw > 0}}); + 0x7: bprge(test={{Rs1.sdw >= 0}}); } } //SETHI (or NOP if rd == 0 and imm == 0) @@ -163,52 +96,25 @@ decode OP default Unknown::unknown() 0x5: decode COND2 { format BranchN { //Branch Always - 0x8: decode A - { - 0x0: fbpa(22, {{ - NNPC = xc->readPC() + disp; - }}); - 0x1: fbpa(22, {{ - NPC = xc->readPC() + disp; - NNPC = NPC + 4; - }}, ',a'); - } + 0x8: fbpa(22, annul_code={{ + NPC = xc->readPC() + disp; + NNPC = NPC + 4; + }}); //Branch Never - 0x0: decode A - { - 0x0: fbpn(22, {{ - NNPC = NNPC;//Don't do anything - }}); - 0x1: fbpn(22, {{ - NNPC = NPC + 8; - NPC = NPC + 4; - }}, ',a'); - } + 0x0: fbpn(22, {{;}}, + annul_code={{ + NNPC = NPC + 8; + NPC = NPC + 4; + }}); default: decode BPCC { - 0x0: fbpfcc0(19, {{ - if(passesFpCondition(Fsr<11:10>, COND2)) - NNPC = xc->readPC() + disp; - else - handle_annul - }}); - 0x1: fbpfcc1(19, {{ - if(passesFpCondition(Fsr<33:32>, COND2)) - NNPC = xc->readPC() + disp; - else - handle_annul - }}); - 0x2: fbpfcc2(19, {{ - if(passesFpCondition(Fsr<35:34>, COND2)) - NNPC = xc->readPC() + disp; - else - handle_annul - }}); - 0x3: fbpfcc3(19, {{ - if(passesFpCondition(Fsr<37:36>, COND2)) - NNPC = xc->readPC() + disp; - else - handle_annul - }}); + 0x0: fbpfcc0(19, test= + {{passesFpCondition(Fsr<11:10>, COND2)}}); + 0x1: fbpfcc1(19, test= + {{passesFpCondition(Fsr<33:32>, COND2)}}); + 0x2: fbpfcc2(19, test= + {{passesFpCondition(Fsr<35:34>, COND2)}}); + 0x3: fbpfcc3(19, test= + {{passesFpCondition(Fsr<37:36>, COND2)}}); } } } @@ -216,33 +122,18 @@ decode OP default Unknown::unknown() 0x6: decode COND2 { format BranchN { //Branch Always - 0x8: decode A - { - 0x0: fba(22, {{ - NNPC = xc->readPC() + disp; - }}); - 0x1: fba(22, {{ - NPC = xc->readPC() + disp; - NNPC = NPC + 4; - }}, ',a'); - } + 0x8: fba(22, annul_code={{ + NPC = xc->readPC() + disp; + NNPC = NPC + 4; + }}); //Branch Never - 0x0: decode A - { - 0x0: fbn(22, {{ - NNPC = NNPC;//Don't do anything - }}); - 0x1: fbn(22, {{ - NNPC = NPC + 8; - NPC = NPC + 4; - }}, ',a'); - } - default: fbfcc(22, {{ - if(passesFpCondition(Fsr<11:10>, COND2)) - NNPC = xc->readPC() + disp; - else - handle_annul - }}); + 0x0: fbn(22, {{;}}, + annul_code={{ + NNPC = NPC + 8; + NPC = NPC + 4; + }}); + default: fbfcc(22, test= + {{passesFpCondition(Fsr<11:10>, COND2)}}); } } } @@ -302,37 +193,23 @@ decode OP default Unknown::unknown() } format IntOpCc { 0x10: addcc({{ - int64_t resTemp, val2 = Rs2_or_imm13; - Rd = resTemp = Rs1 + val2;}}, - {{(Rs1<31:0> + val2<31:0>)<32:>}}, - {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, - {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, - {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - ); + int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; + Rd = res = op1 + op2; + }}); 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 0x14: subcc({{ - int64_t val2 = Rs2_or_imm13; - Rd = Rs1 - val2;}}, - {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, - {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, - {{(~(Rs1<63:1> + (~val2)<63:1> + - (Rs1 | ~val2)<0:>))<63:>}}, - {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} - ); + int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; + Rd = res = op1 - op2; + }}, sub=True); 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 0x18: addccc({{ - int64_t resTemp, val2 = Rs2_or_imm13; - int64_t carryin = Ccr<0:0>; - Rd = resTemp = Rs1 + val2 + carryin;}}, - {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, - {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, - {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}}, - {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - ); + int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; + Rd = res = op1 + op2 + Ccr<0:>; + }}); 0x1A: IntOpCcRes::umulcc({{ uint64_t resTemp; Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; @@ -342,107 +219,80 @@ decode OP default Unknown::unknown() Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); Y = resTemp<63:32>;}}); 0x1C: subccc({{ - int64_t resTemp, val2 = Rs2_or_imm13; - int64_t carryin = Ccr<0:0>; - Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, - {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}}, - {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, - {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}}, - {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} - ); + int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; + Rd = res = op1 - op2 - Ccr<0:>; + }}, sub=True); 0x1D: IntOpCcRes::udivxcc({{ if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); - 0x1E: udivcc({{ - uint32_t resTemp, val2 = Rs2_or_imm13.udw; - int32_t overflow = 0; - if(val2 == 0) fault = new DivisionByZero; - else - { - resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; - overflow = (resTemp<63:32> != 0); - if(overflow) Rd = resTemp = 0xFFFFFFFF; - else Rd = resTemp; - } }}, - {{0}}, - {{overflow}}, - {{0}}, - {{0}} - ); - 0x1F: sdivcc({{ - int64_t val2 = Rs2_or_imm13.sdw<31:0>; - bool overflow = false, underflow = false; - if(val2 == 0) fault = new DivisionByZero; - else - { - Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; - overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); - underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); - if(overflow) Rd = 0x7FFFFFFF; - else if(underflow) Rd = ULL(0xFFFFFFFF80000000); - } }}, - {{0}}, - {{overflow || underflow}}, - {{0}}, - {{0}} - ); + 0x1E: IntOpCcRes::udivcc({{ + uint32_t resTemp, val2 = Rs2_or_imm13.udw; + int32_t overflow = 0; + if(val2 == 0) fault = new DivisionByZero; + else + { + resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; + overflow = (resTemp<63:32> != 0); + if(overflow) Rd = resTemp = 0xFFFFFFFF; + else Rd = resTemp; + } + }}, iv={{overflow}}); + 0x1F: IntOpCcRes::sdivcc({{ + int64_t val2 = Rs2_or_imm13.sdw<31:0>; + bool overflow = false, underflow = false; + if(val2 == 0) fault = new DivisionByZero; + else + { + Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; + overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); + underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); + if(overflow) Rd = 0x7FFFFFFF; + else if(underflow) Rd = ULL(0xFFFFFFFF80000000); + } + }}, iv={{overflow || underflow}}); 0x20: taddcc({{ - int64_t resTemp, val2 = Rs2_or_imm13; - Rd = resTemp = Rs1 + val2; - int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, - {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, - {{overflow}}, - {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, - {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - ); + int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; + Rd = res = Rs1 + op2; + }}, iv={{ + (op1 & mask(2)) || (op2 & mask(2)) || + findOverflow(32, res, op1, op2) + }}); 0x21: tsubcc({{ - int64_t resTemp, val2 = Rs2_or_imm13; - Rd = resTemp = Rs1 + val2; - int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, - {{(Rs1<31:0> + val2<31:0>)<32:0>}}, - {{overflow}}, - {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, - {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - ); + int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; + Rd = res = Rs1 - op2; + }}, iv={{ + (op1 & mask(2)) || (op2 & mask(2)) || + findOverflow(32, res, op1, ~op2) + }}, sub=True); 0x22: taddcctv({{ - int64_t val2 = Rs2_or_imm13; - Rd = Rs1 + val2; - int32_t overflow = Rs1<1:0> || val2<1:0> || - (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); - if(overflow) fault = new TagOverflow;}}, - {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, - {{overflow}}, - {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, - {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}} - ); + int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; + Rd = res = op1 + op2; + bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || + findOverflow(32, res, op1, op2); + if(overflow) fault = new TagOverflow; + }}, iv={{overflow}}); 0x23: tsubcctv({{ - int64_t resTemp, val2 = Rs2_or_imm13; - Rd = resTemp = Rs1 + val2; - int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); - if(overflow) fault = new TagOverflow;}}, - {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, - {{overflow}}, - {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, - {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} - ); + int64_t res, op1 = Rs1, op2 = Rs2_or_imm13; + Rd = res = op1 - op2; + bool overflow = (op1 & mask(2)) || (op2 & mask(2)) || + findOverflow(32, res, op1, ~op2); + if(overflow) fault = new TagOverflow; + }}, iv={{overflow}}, sub=True); 0x24: mulscc({{ - int32_t savedLSB = Rs1<0:>; + int32_t savedLSB = Rs1<0:>; - //Step 1 - int64_t multiplicand = Rs2_or_imm13; - //Step 2 - int32_t partialP = Rs1<31:1> | - ((Ccr<3:3> ^ Ccr<1:1>) << 31); - //Step 3 - int32_t added = Y<0:> ? multiplicand : 0; - Rd = partialP + added; - //Steps 4 & 5 - Y = Y<31:1> | (savedLSB << 31);}}, - {{((partialP<31:0> + added<31:0>)<32:0>)}}, - {{partialP<31:> == added<31:> && added<31:> != Rd<31:>}}, - {{((partialP >> 1) + (added >> 1) + (partialP & added & 0x1))<63:>}}, - {{partialP<63:> == added<63:> && partialP<63:> != Rd<63:>}} - ); + //Step 1 + int64_t multiplicand = Rs2_or_imm13; + //Step 2 + int32_t partialP = Rs1<31:1> | + ((Ccr<3:3> ^ Ccr<1:1>) << 31); + //Step 3 + int32_t added = Y<0:> ? multiplicand : 0; + int64_t res, op1 = partialP, op2 = added; + Rd = res = partialP + added; + //Steps 4 & 5 + Y = Y<31:1> | (savedLSB << 31); + }}); } format IntOp { @@ -463,7 +313,7 @@ decode OP default Unknown::unknown() //1 should cause an illegal instruction exception 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 0x03: NoPriv::rdasi({{Rd = Asi;}}); - 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); + 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 0x05: NoPriv::rdpc({{ if(Pstate<3:>) Rd = (xc->readPC())<31:0>; @@ -479,7 +329,7 @@ decode OP default Unknown::unknown() 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); } 0x10: Priv::rdpcr({{Rd = Pcr;}}); - 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); + 0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); //0x12 should cause an illegal instruction exception 0x13: NoPriv::rdgsr({{ fault = checkFpEnableFault(xc); @@ -490,7 +340,7 @@ decode OP default Unknown::unknown() //0x14-0x15 should cause an illegal instruction exception 0x16: Priv::rdsoftint({{Rd = Softint;}}); 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); - 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); + 0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 0x1A: Priv::rdstrand_sts_reg({{ if(Pstate<2:> && !Hpstate<2:>) @@ -504,11 +354,7 @@ decode OP default Unknown::unknown() } 0x29: decode RS1 { 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); - 0x01: HPriv::rdhprhtstate({{ - if(Tl == 0) - return new IllegalInstruction; - Rd = Htstate; - }}); + 0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true); //0x02 should cause an illegal instruction exception 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); //0x04 should cause an illegal instruction exception @@ -518,26 +364,10 @@ decode OP default Unknown::unknown() 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); } 0x2A: decode RS1 { - 0x00: Priv::rdprtpc({{ - if(Tl == 0) - return new IllegalInstruction; - Rd = Tpc; - }}); - 0x01: Priv::rdprtnpc({{ - if(Tl == 0) - return new IllegalInstruction; - Rd = Tnpc; - }}); - 0x02: Priv::rdprtstate({{ - if(Tl == 0) - return new IllegalInstruction; - Rd = Tstate; - }}); - 0x03: Priv::rdprtt({{ - if(Tl == 0) - return new IllegalInstruction; - Rd = Tt; - }}); + 0x00: Priv::rdprtpc({{Rd = Tpc;}}, checkTl=true); + 0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, checkTl=true); + 0x02: Priv::rdprtstate({{Rd = Tstate;}}, checkTl=true); + 0x03: Priv::rdprtt({{Rd = Tt;}}, checkTl=true); 0x04: Priv::rdprtick({{Rd = Tick;}}); 0x05: Priv::rdprtba({{Rd = Tba;}}); 0x06: Priv::rdprpstate({{Rd = Pstate;}}); @@ -605,7 +435,7 @@ decode OP default Unknown::unknown() //0x07-0x0E should cause an illegal instruction exception 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); - 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); + 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); //0x12 should cause an illegal instruction exception 0x13: NoPriv::wrgsr({{ if(Fprs<2:> == 0 || Pstate<4:> == 0) @@ -653,30 +483,14 @@ decode OP default Unknown::unknown() }}); } 0x32: decode RD { - 0x00: Priv::wrprtpc({{ - if(Tl == 0) - return new IllegalInstruction; - else - Tpc = Rs1 ^ Rs2_or_imm13; - }}); - 0x01: Priv::wrprtnpc({{ - if(Tl == 0) - return new IllegalInstruction; - else - Tnpc = Rs1 ^ Rs2_or_imm13; - }}); - 0x02: Priv::wrprtstate({{ - if(Tl == 0) - return new IllegalInstruction; - else - Tstate = Rs1 ^ Rs2_or_imm13; - }}); - 0x03: Priv::wrprtt({{ - if(Tl == 0) - return new IllegalInstruction; - else - Tt = Rs1 ^ Rs2_or_imm13; - }}); + 0x00: Priv::wrprtpc( + {{Tpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); + 0x01: Priv::wrprtnpc( + {{Tnpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); + 0x02: Priv::wrprtstate( + {{Tstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); + 0x03: Priv::wrprtt( + {{Tt = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); @@ -704,11 +518,8 @@ decode OP default Unknown::unknown() } 0x33: decode RD { 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); - 0x01: HPriv::wrhprhtstate({{ - if(Tl == 0) - return new IllegalInstruction; - Htstate = Rs1 ^ Rs2_or_imm13; - }}); + 0x01: HPriv::wrhprhtstate( + {{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true); //0x02 should cause an illegal instruction exception 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); //0x04 should cause an illegal instruction exception @@ -718,44 +529,14 @@ decode OP default Unknown::unknown() } 0x34: decode OPF{ format FpBasic{ - 0x01: fmovs({{ - Frds.uw = Frs2s.uw; - //fsr.ftt = fsr.cexc = 0 - Fsr &= ~(7 << 14); - Fsr &= ~(0x1F); - }}); - 0x02: fmovd({{ - Frd.udw = Frs2.udw; - //fsr.ftt = fsr.cexc = 0 - Fsr &= ~(7 << 14); - Fsr &= ~(0x1F); - }}); + 0x01: fmovs({{Frds.uw = Frs2s.uw;}}); + 0x02: fmovd({{Frd.udw = Frs2.udw;}}); 0x03: FpUnimpl::fmovq(); - 0x05: fnegs({{ - Frds.uw = Frs2s.uw ^ (1UL << 31); - //fsr.ftt = fsr.cexc = 0 - Fsr &= ~(7 << 14); - Fsr &= ~(0x1F); - }}); - 0x06: fnegd({{ - Frd.udw = Frs2.udw ^ (1ULL << 63); - //fsr.ftt = fsr.cexc = 0 - Fsr &= ~(7 << 14); - Fsr &= ~(0x1F); - }}); + 0x05: fnegs({{Frds.uw = Frs2s.uw ^ (1UL << 31);}}); + 0x06: fnegd({{Frd.udw = Frs2.udw ^ (1ULL << 63);}}); 0x07: FpUnimpl::fnegq(); - 0x09: fabss({{ - Frds.uw = ((1UL << 31) - 1) & Frs2s.uw; - //fsr.ftt = fsr.cexc = 0 - Fsr &= ~(7 << 14); - Fsr &= ~(0x1F); - }}); - 0x0A: fabsd({{ - Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; - //fsr.ftt = fsr.cexc = 0 - Fsr &= ~(7 << 14); - Fsr &= ~(0x1F); - }}); + 0x09: fabss({{Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;}}); + 0x0A: fabsd({{Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;}}); 0x0B: FpUnimpl::fabsq(); 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); @@ -774,28 +555,16 @@ decode OP default Unknown::unknown() 0x4F: FpUnimpl::fdivq(); 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 0x6E: FpUnimpl::fdmulq(); - 0x81: fstox({{ - Frd.sdw = static_cast<int64_t>(Frs2s.sf); - }}); - 0x82: fdtox({{ - Frd.sdw = static_cast<int64_t>(Frs2.df); - }}); + 0x81: fstox({{Frd.sdw = static_cast<int64_t>(Frs2s.sf);}}); + 0x82: fdtox({{Frd.sdw = static_cast<int64_t>(Frs2.df);}}); 0x83: FpUnimpl::fqtox(); - 0x84: fxtos({{ - Frds.sf = static_cast<float>(Frs2.sdw); - }}); - 0x88: fxtod({{ - Frd.df = static_cast<double>(Frs2.sdw); - }}); + 0x84: fxtos({{Frds.sf = static_cast<float>(Frs2.sdw);}}); + 0x88: fxtod({{Frd.df = static_cast<double>(Frs2.sdw);}}); 0x8C: FpUnimpl::fxtoq(); - 0xC4: fitos({{ - Frds.sf = static_cast<float>(Frs2s.sw); - }}); + 0xC4: fitos({{Frds.sf = static_cast<float>(Frs2s.sw);}}); 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 0xC7: FpUnimpl::fqtos(); - 0xC8: fitod({{ - Frd.df = static_cast<double>(Frs2s.sw); - }}); + 0xC8: fitod({{Frd.df = static_cast<double>(Frs2s.sw);}}); 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 0xCB: FpUnimpl::fqtod(); 0xCC: FpUnimpl::fitoq(); @@ -1280,9 +1049,6 @@ decode OP default Unknown::unknown() }}); 0x3E: decode FCN { 0x0: Priv::done({{ - if(Tl == 0) - return new IllegalInstruction; - Cwp = Tstate<4:0>; Pstate = Tstate<20:8>; Asi = Tstate<31:24>; @@ -1292,10 +1058,8 @@ decode OP default Unknown::unknown() NPC = Tnpc; NNPC = Tnpc + 4; Tl = Tl - 1; - }}); + }}, checkTl=true); 0x1: Priv::retry({{ - if(Tl == 0) - return new IllegalInstruction; Cwp = Tstate<4:0>; Pstate = Tstate<20:8>; Asi = Tstate<31:24>; @@ -1305,7 +1069,7 @@ decode OP default Unknown::unknown() NPC = Tpc; NNPC = Tnpc; Tl = Tl - 1; - }}); + }}, checkTl=true); } } } @@ -1352,76 +1116,75 @@ decode OP default Unknown::unknown() Rd.uw = tmp; }}, MEM_SWAP); format LoadAlt { - 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); - 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); - 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); + 0x10: lduwa({{Rd = Mem.uw;}}); + 0x11: lduba({{Rd = Mem.ub;}}); + 0x12: lduha({{Rd = Mem.uhw;}}); 0x13: decode EXT_ASI { //ASI_LDTD_AIUP 0x22: TwinLoad::ldtx_aiup( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTD_AIUS 0x23: TwinLoad::ldtx_aius( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_QUAD_LDD 0x24: TwinLoad::ldtx_quad_ldd( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_REAL 0x26: TwinLoad::ldtx_real( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_N 0x27: TwinLoad::ldtx_n( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_AIUP_L 0x2A: TwinLoad::ldtx_aiup_l( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_AIUS_L 0x2B: TwinLoad::ldtx_aius_l( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_L 0x2C: TwinLoad::ldtx_l( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_REAL_L 0x2E: TwinLoad::ldtx_real_l( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_N_L 0x2F: TwinLoad::ldtx_n_l( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_P 0xE2: TwinLoad::ldtx_p( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_S 0xE3: TwinLoad::ldtx_s( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_PL 0xEA: TwinLoad::ldtx_pl( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); //ASI_LDTX_SL 0xEB: TwinLoad::ldtx_sl( {{RdLow.udw = (Mem.tudw).a; - RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); + RdHigh.udw = (Mem.tudw).b;}}); default: ldtwa({{ RdLow = (Mem.tuw).a; - RdHigh = (Mem.tuw).b; - }}, {{EXT_ASI}}); + RdHigh = (Mem.tuw).b;}}); } } format StoreAlt { - 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); - 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); - 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); + 0x14: stwa({{Mem.uw = Rd;}}); + 0x15: stba({{Mem.ub = Rd;}}); + 0x16: stha({{Mem.uhw = Rd;}}); 0x17: sttwa({{ //This temporary needs to be here so that the parser //will correctly identify this instruction as a store. @@ -1431,25 +1194,25 @@ decode OP default Unknown::unknown() temp.a = RdLow<31:0>; temp.b = RdHigh<31:0>; Mem.tuw = temp; - }}, {{EXT_ASI}}); + }}); } format LoadAlt { - 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); - 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); - 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); - 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); + 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); + 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); + 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); + 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); } 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, {{ uint8_t tmp = mem_data; Rd.ub = tmp; - }}, {{EXT_ASI}}, MEM_SWAP); - 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); + }}, MEM_SWAP); + 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}); 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, {{ uint32_t tmp = mem_data; Rd.uw = tmp; - }}, {{EXT_ASI}}, MEM_SWAP); + }}, MEM_SWAP); format Trap { 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); @@ -1483,7 +1246,7 @@ decode OP default Unknown::unknown() 0x26: stqf({{fault = new FpDisabled;}}); 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 0x2D: Nop::prefetch({{ }}); - 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}}); + 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}); 0x32: ldqfa({{fault = new FpDisabled;}}); format LoadAlt { 0x33: decode EXT_ASI { @@ -1535,7 +1298,7 @@ decode OP default Unknown::unknown() //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x1F: FailUnimpl::ldblockf_aiusl(); //ASI_BLOCK_PRIMARY - 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}}); + 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); //ASI_BLOCK_SECONDARY 0xF1: FailUnimpl::ldblockf_s(); //ASI_BLOCK_PRIMARY_LITTLE @@ -1618,7 +1381,7 @@ decode OP default Unknown::unknown() //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x1F: FailUnimpl::stblockf_aiusl(); //ASI_BLOCK_PRIMARY - 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}}); + 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); //ASI_BLOCK_SECONDARY 0xF1: FailUnimpl::stblockf_s(); //ASI_BLOCK_PRIMARY_LITTLE @@ -1655,11 +1418,11 @@ decode OP default Unknown::unknown() {{ uint32_t tmp = mem_data; Rd.uw = tmp; - }}, {{EXT_ASI}}, MEM_SWAP_COND); + }}, MEM_SWAP_COND); 0x3D: Nop::prefetcha({{ }}); 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); Mem.udw = Rd.udw; }}, - {{ Rd.udw = mem_data; }}, {{EXT_ASI}}, MEM_SWAP_COND); + {{ Rd.udw = mem_data; }}, MEM_SWAP_COND); } } } diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa index 5b0868132..cad759b3e 100644 --- a/src/arch/sparc/isa/formats/basic.isa +++ b/src/arch/sparc/isa/formats/basic.isa @@ -56,6 +56,20 @@ def template BasicDeclare {{ }; }}; +// Basic instruction class declaration template. +def template BasicDeclareWithMnemonic {{ + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + // Constructor. + %(class_name)s(const char * mnemonic, ExtMachInst machInst); + %(BasicExecDeclare)s + }; +}}; + // Basic instruction class constructor template. def template BasicConstructor {{ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) @@ -65,6 +79,16 @@ def template BasicConstructor {{ } }}; +// Basic instruction class constructor template. +def template BasicConstructorWithMnemonic {{ + inline %(class_name)s::%(class_name)s(const char * mnemonic, + ExtMachInst machInst) + : %(base_class)s(mnemonic, machInst, %(op_class)s) + { + %(constructor)s; + } +}}; + // Basic instruction class execute method template. def template BasicExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, diff --git a/src/arch/sparc/isa/formats/branch.isa b/src/arch/sparc/isa/formats/branch.isa index f5ab940bb..faaee8842 100644 --- a/src/arch/sparc/isa/formats/branch.isa +++ b/src/arch/sparc/isa/formats/branch.isa @@ -183,7 +183,7 @@ output decoder {{ } }}; -def template BranchExecute {{ +def template JumpExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { @@ -206,65 +206,135 @@ def template BranchExecute {{ } }}; -let {{ - handle_annul = ''' - { - if(A) - { - NNPC = NPC + 8; - NPC = NPC + 4; - } - else +def template BranchExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const { - NPC = NPC; - NNPC = NNPC; + //Attempt to execute the instruction + Fault fault = NoFault; + + %(op_decl)s; + %(op_rd)s; + + if (%(cond)s) { + %(code)s; + } else { + %(fail)s; + } + + if(fault == NoFault) + { + //Write the resulting state to the execution context + %(op_wb)s; + } + + return fault; } - }''' +}}; + +def template BranchDecode {{ + if (A) + return new %(class_name)sAnnul("%(mnemonic)s,a", machInst); + else + return new %(class_name)s("%(mnemonic)s", machInst); }}; // Primary format for branch instructions: def format Branch(code, *opt_flags) {{ - (usesImm, code, immCode, - rString, iString) = splitOutImm(code) - iop = InstObjParams(name, Name, 'Branch', code, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) + (usesImm, code, immCode, + rString, iString) = splitOutImm(code) + iop = InstObjParams(name, Name, 'Branch', code, opt_flags) + header_output = BasicDeclare.subst(iop) + decoder_output = BasicConstructor.subst(iop) + exec_output = JumpExecute.subst(iop) + if usesImm: + imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString, + immCode, opt_flags) + header_output += BasicDeclare.subst(imm_iop) + decoder_output += BasicConstructor.subst(imm_iop) + exec_output += JumpExecute.subst(imm_iop) + decode_block = ROrImmDecode.subst(iop) + else: + decode_block = BasicDecode.subst(iop) +}}; + +let {{ + def doBranch(name, Name, base, cond, + code, annul_code, fail, annul_fail, opt_flags): + iop = InstObjParams(name, Name, base, + {"code": code, + "fail": fail, + "cond": cond + }, + opt_flags) + header_output = BasicDeclareWithMnemonic.subst(iop) + decoder_output = BasicConstructorWithMnemonic.subst(iop) exec_output = BranchExecute.subst(iop) - if usesImm: - imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString, - immCode, opt_flags) - header_output += BasicDeclare.subst(imm_iop) - decoder_output += BasicConstructor.subst(imm_iop) - exec_output += BranchExecute.subst(imm_iop) - decode_block = ROrImmDecode.subst(iop) + if annul_code == "None": + decode_block = BasicDecodeWithMnemonic.subst(iop) else: - decode_block = BasicDecode.subst(iop) + decode_block = BranchDecode.subst(iop) + + if annul_code != "None": + iop = InstObjParams(name + ',a', Name + 'Annul', base, + {"code": annul_code, + "fail": annul_fail, + "cond": cond + }, + opt_flags) + header_output += BasicDeclareWithMnemonic.subst(iop) + decoder_output += BasicConstructorWithMnemonic.subst(iop) + exec_output += BranchExecute.subst(iop) + return (header_output, decoder_output, exec_output, decode_block) + + def doCondBranch(name, Name, base, cond, code, opt_flags): + return doBranch(name, Name, base, cond, code, code, + 'NPC = NPC; NNPC = NNPC;', + 'NNPC = NPC + 8; NPC = NPC + 4', + opt_flags) + + def doUncondBranch(name, Name, base, code, annul_code, opt_flags): + return doBranch(name, Name, base, "true", code, annul_code, + ";", ";", opt_flags) + + default_branch_code = "NNPC = xc->readPC() + disp;" }}; -// Primary format for branch instructions: -def format BranchN(bits, code, *opt_flags) {{ - code = re.sub(r'handle_annul', handle_annul, code) - new_opt_flags = [] - for flag in opt_flags: - if flag == ',a': - name += ',a' - Name += 'Annul' - else: - new_opt_flags += flag - iop = InstObjParams(name, Name, "BranchNBits<%d>" % bits, code, new_opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = BranchExecute.subst(iop) - decode_block = BasicDecode.subst(iop) +// Format for branch instructions with n bit displacements: +def format BranchN(bits, code=default_branch_code, + test=None, annul_code=None, *opt_flags) {{ + if code == "default_branch_code": + code = default_branch_code + if test != "None": + (header_output, + decoder_output, + exec_output, + decode_block) = doCondBranch(name, Name, + "BranchNBits<%d>" % bits, test, code, opt_flags) + else: + (header_output, + decoder_output, + exec_output, + decode_block) = doUncondBranch(name, Name, + "BranchNBits<%d>" % bits, code, annul_code, opt_flags) }}; -// Primary format for branch instructions: -def format BranchSplit(code, *opt_flags) {{ - code = re.sub(r'handle_annul', handle_annul, code) - iop = InstObjParams(name, Name, 'BranchSplit', code, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = BranchExecute.subst(iop) - decode_block = BasicDecode.subst(iop) +// Format for branch instructions with split displacements: +def format BranchSplit(code=default_branch_code, + test=None, annul_code=None, *opt_flags) {{ + if code == "default_branch_code": + code = default_branch_code + if test != "None": + (header_output, + decoder_output, + exec_output, + decode_block) = doCondBranch(name, Name, + "BranchSplit", test, code, opt_flags) + else: + (header_output, + decoder_output, + exec_output, + decode_block) = doUncondBranch(name, Name, + "BranchSplit", code, annul_code, opt_flags) }}; diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa index f877b8790..55af7e5b3 100644 --- a/src/arch/sparc/isa/formats/integerop.isa +++ b/src/arch/sparc/isa/formats/integerop.isa @@ -287,10 +287,10 @@ let {{ _iz = ((Rd & 0xFFFFFFFF) == 0); _xn = (Rd >> 63) & 1; _xz = (Rd == 0); - _iv = %(ivValue)s & 1; - _ic = %(icValue)s & 1; - _xv = %(xvValue)s & 1; - _xc = %(xcValue)s & 1; + _iv = %(iv)s & 1; + _ic = %(ic)s & 1; + _xv = %(xv)s & 1; + _xc = %(xc)s & 1; Ccr = _ic << 0 | _iv << 1 | _iz << 2 | _in << 3 | _xc << 4 | _xv << 5 | _xz << 6 | _xn << 7; @@ -305,6 +305,15 @@ let {{ DPRINTF(Sparc, "xv = %%d\\n", _xv); DPRINTF(Sparc, "xc = %%d\\n", _xc); ''' + + default_ic = "findCarry(32, res, op1, op2)" + default_iv = "findOverflow(32, res, op1, op2)" + default_xc = "findCarry(64, res, op1, op2)" + default_xv = "findOverflow(64, res, op1, op2)" + default_sub_ic = "!findCarry(32, res, op1, ~op2)" + default_sub_iv = "findOverflow(32, res, op1, ~op2)" + default_sub_xc = "!findCarry(64, res, op1, ~op2)" + default_sub_xv = "findOverflow(64, res, op1, ~op2)" }}; // Primary format for integer operate instructions: @@ -318,7 +327,24 @@ def format IntOp(code, *opt_flags) {{ }}; // Primary format for integer operate instructions: -def format IntOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ +def format IntOpCc(code, ic=default_ic, iv=default_iv, + xc=default_xc, xv=default_xv, + sub=False, *opt_flags) {{ + + if sub == "False": + (def_ic, def_iv, def_xc, def_xv) = \ + (default_ic, default_iv, default_xc, default_xv) + else: + (def_ic, def_iv, def_xc, def_xv) = \ + (default_sub_ic, default_sub_iv, default_sub_xc, default_sub_xv) + if ic == "default_ic": + ic = def_ic + if iv == "default_iv": + iv = def_iv + if xc == "default_xc": + xc = def_xc + if xv == "default_xv": + xv = def_xv ccCode = calcCcCode % vars() (header_output, decoder_output, @@ -328,11 +354,8 @@ def format IntOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{ }}; // Primary format for integer operate instructions: -def format IntOpCcRes(code, *opt_flags) {{ - ccCode = calcCcCode % {"icValue":"0", - "ivValue":"0", - "xcValue":"0", - "xvValue":"0"} +def format IntOpCcRes(code, ic=0, iv=0, xc=0, xv=0, *opt_flags) {{ + ccCode = calcCcCode % {"ic" : ic, "iv" : iv, "xc" : xc, "xv" : xv} (header_output, decoder_output, exec_output, diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa index aa6c4cdea..e3c043cf3 100644 --- a/src/arch/sparc/isa/formats/mem/basicmem.isa +++ b/src/arch/sparc/isa/formats/mem/basicmem.isa @@ -72,22 +72,22 @@ let {{ return (header_output, decoder_output, exec_output, decode_block) }}; -def format LoadAlt(code, asi, *opt_flags) {{ +def format LoadAlt(code, *opt_flags) {{ code = filterDoubles(code) (header_output, decoder_output, exec_output, decode_block) = doMemFormat(code, LoadFuncs, - AlternateASIPrivFaultCheck, name, Name, asi, opt_flags) + AlternateASIPrivFaultCheck, name, Name, "EXT_ASI", opt_flags) }}; -def format StoreAlt(code, asi, *opt_flags) {{ +def format StoreAlt(code, *opt_flags) {{ code = filterDoubles(code) (header_output, decoder_output, exec_output, decode_block) = doMemFormat(code, StoreFuncs, - AlternateASIPrivFaultCheck, name, Name, asi, opt_flags) + AlternateASIPrivFaultCheck, name, Name, "EXT_ASI", opt_flags) }}; def format Load(code, *opt_flags) {{ @@ -108,12 +108,12 @@ def format Store(code, *opt_flags) {{ StoreFuncs, '', name, Name, 0, opt_flags) }}; -def format TwinLoad(code, asi, *opt_flags) {{ +def format TwinLoad(code, *opt_flags) {{ (header_output, decoder_output, exec_output, decode_block) = doMemFormat(code, LoadFuncs, AlternateASIPrivFaultCheck + TwinAlignmentFaultCheck, - name, Name, asi, opt_flags) + name, Name, "EXT_ASI", opt_flags) }}; diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index 5d36e5e41..020dc326f 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -273,7 +273,7 @@ def template BlockMemMicroConstructor {{ let {{ - def doBlockMemFormat(code, faultCode, execute, name, Name, asi, opt_flags): + def doBlockMemFormat(code, faultCode, execute, name, Name, opt_flags): # XXX Need to take care of pstate.hpriv as well. The lower ASIs # are split into ones that are available in priv and hpriv, and # those that are only available in hpriv @@ -313,12 +313,12 @@ let {{ makeMicroName(name + "Imm", microPc), makeMicroName(Name, microPc), makeMicroName(Name + "Imm", microPc), - asi, opt_flags); + "EXT_ASI", opt_flags); faultCode = '' return (header_output, decoder_output, exec_output, decode_block) }}; -def format BlockLoad(code, asi, *opt_flags) {{ +def format BlockLoad(code, *opt_flags) {{ code = filterDoubles(code) # We need to make sure to check the highest priority fault last. # That way, if other faults have been detected, they'll be overwritten @@ -328,10 +328,10 @@ def format BlockLoad(code, asi, *opt_flags) {{ decoder_output, exec_output, decode_block) = doBlockMemFormat(code, faultCode, - LoadFuncs, name, Name, asi, opt_flags) + LoadFuncs, name, Name, opt_flags) }}; -def format BlockStore(code, asi, *opt_flags) {{ +def format BlockStore(code, *opt_flags) {{ code = filterDoubles(code) # We need to make sure to check the highest priority fault last. # That way, if other faults have been detected, they'll be overwritten @@ -341,5 +341,5 @@ def format BlockStore(code, asi, *opt_flags) {{ decoder_output, exec_output, decode_block) = doBlockMemFormat(code, faultCode, - StoreFuncs, name, Name, asi, opt_flags) + StoreFuncs, name, Name, opt_flags) }}; diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa index dde327f5c..2ebe9aa15 100644 --- a/src/arch/sparc/isa/formats/mem/swap.isa +++ b/src/arch/sparc/isa/formats/mem/swap.isa @@ -142,9 +142,9 @@ def format Swap(code, postacc_code, mem_flags, *opt_flags) {{ ["IsStoreConditional"], postacc_code) }}; -def format SwapAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{ +def format SwapAlt(code, postacc_code, mem_flags, *opt_flags) {{ mem_flags = makeList(mem_flags) - mem_flags.append(asi) + mem_flags.append("EXT_ASI") flags = string.join(mem_flags, '|') (header_output, decoder_output, @@ -155,7 +155,7 @@ def format SwapAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{ let {{ - def doCasFormat(code, execute, faultCode, name, Name, asi, opt_flags, postacc_code = ''): + def doCasFormat(code, execute, faultCode, name, Name, mem_flags, opt_flags, postacc_code = ''): addrCalcReg = 'EA = Rs1;' iop = InstObjParams(name, Name, 'Mem', {"code": code, "postacc_code" : postacc_code, @@ -167,15 +167,15 @@ let {{ microParams = {"code": code, "postacc_code" : postacc_code, "ea_code" : addrCalcReg, "fault_check" : faultCode, "EA_trunc" : TruncateEA} - exec_output = doSplitExecute(execute, name, Name, asi, + exec_output = doSplitExecute(execute, name, Name, mem_flags, ["IsStoreConditional"], microParams); return (header_output, decoder_output, exec_output, decode_block) }}; -def format CasAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{ +def format CasAlt(code, postacc_code, mem_flags, *opt_flags) {{ mem_flags = makeList(mem_flags) - mem_flags.append(asi) + mem_flags.append("EXT_ASI") flags = string.join(mem_flags, '|') (header_output, decoder_output, diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa index 36403afb4..795a22958 100644 --- a/src/arch/sparc/isa/formats/priv.isa +++ b/src/arch/sparc/isa/formats/priv.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2006 The Regents of The University of Michigan +// Copyright (c) 2006-2007 The Regents of The University of Michigan // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -207,6 +207,9 @@ def template PrivExecute {{ if(%(check)s) return new PrivilegedAction; + if(%(tlCheck)s) + return new IllegalInstruction; + Fault fault = NoFault; %(code)s; %(op_wb)s; @@ -215,7 +218,7 @@ def template PrivExecute {{ }}; let {{ - def doPrivFormat(code, checkCode, name, Name, opt_flags): + def doPrivFormat(code, checkCode, name, Name, tlCheck, opt_flags): (usesImm, code, immCode, rString, iString) = splitOutImm(code) #If these are rd, rdpr, rdhpr, wr, wrpr, or wrhpr instructions, @@ -236,7 +239,8 @@ let {{ regBase = 'WrPriv' break iop = InstObjParams(name, Name, regBase, - {"code": code, "check": checkCode, "reg_name": regName}, + {"code": code, "check": checkCode, + "tlCheck": tlCheck, "reg_name": regName}, opt_flags) header_output = BasicDeclare.subst(iop) if regName == '': @@ -246,7 +250,8 @@ let {{ exec_output = PrivExecute.subst(iop) if usesImm: imm_iop = InstObjParams(name, Name + 'Imm', regBase + 'Imm', - {"code": immCode, "check": checkCode, "reg_name": regName}, + {"code": immCode, "check": checkCode, + "tlCheck": tlCheck, "reg_name": regName}, opt_flags) header_output += BasicDeclare.subst(imm_iop) if regName == '': @@ -260,34 +265,39 @@ let {{ return (header_output, decoder_output, exec_output, decode_block) }}; -def format Priv(code, *opt_flags) {{ - checkCode = "!(Pstate<2:> || Hpstate<2:>)" +def format Priv(code, extraCond=true, checkTl=false, *opt_flags) {{ + checkCode = "(%s) && !(Pstate<2:> || Hpstate<2:>)" % extraCond + if checkTl != "false": + tlCheck = "Tl == 0" + else: + tlCheck = "false" (header_output, decoder_output, exec_output, decode_block) = doPrivFormat(code, - checkCode, name, Name, opt_flags) + checkCode, name, Name, tlCheck, opt_flags) }}; -def format NoPriv(code, *opt_flags) {{ +def format NoPriv(code, checkTl=false, *opt_flags) {{ #Instructions which use this format don't really check for #any particular mode, but the disassembly is performed #using the control registers actual name checkCode = "false" + if checkTl != "false": + tlCheck = "Tl == 0" + else: + tlCheck = "false" (header_output, decoder_output, exec_output, decode_block) = doPrivFormat(code, - checkCode, name, Name, opt_flags) -}}; - -def format PrivCheck(code, extraCheckCode, *opt_flags) {{ - checkCode = "(%s) && !(Pstate<2:> || Hpstate<2:>)" % extraCheckCode - (header_output, decoder_output, - exec_output, decode_block) = doPrivFormat(code, - checkCode, name, Name, opt_flags) + checkCode, name, Name, tlCheck, opt_flags) }}; -def format HPriv(code, *opt_flags) {{ +def format HPriv(code, checkTl=false, *opt_flags) {{ checkCode = "!Hpstate<2:2>" + if checkTl != "false": + tlCheck = "Tl == 0" + else: + tlCheck = "false" (header_output, decoder_output, exec_output, decode_block) = doPrivFormat(code, - checkCode, name, Name, opt_flags) + checkCode, name, Name, tlCheck, opt_flags) }}; diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index e9cd660b5..135bd58c3 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -41,6 +41,7 @@ output header {{ #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" #include "arch/sparc/regfile.hh" +#include "base/condcodes.hh" #include "base/misc.hh" #include "cpu/static_inst.hh" #include "mem/packet.hh" diff --git a/src/arch/sparc/linux/process.cc b/src/arch/sparc/linux/process.cc index 9e3f74075..f4ec28c00 100644 --- a/src/arch/sparc/linux/process.cc +++ b/src/arch/sparc/linux/process.cc @@ -72,21 +72,9 @@ SparcLinuxProcess::SparcLinuxProcess() : assert(Num_Syscall_Descs <= 299); } -Sparc32LinuxProcess::Sparc32LinuxProcess(const std::string &name, - ObjectFile *objFile, - System * system, - int stdin_fd, - int stdout_fd, - int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid) - : Sparc32LiveProcess(name, objFile, system, - stdin_fd, stdout_fd, stderr_fd, argv, envp, cwd, - _uid, _euid, _gid, _egid, _pid, _ppid) +Sparc32LinuxProcess::Sparc32LinuxProcess(LiveProcessParams * params, + ObjectFile *objFile) + : Sparc32LiveProcess(params, objFile) {} void Sparc32LinuxProcess::handleTrap(int trapNum, ThreadContext *tc) @@ -101,21 +89,9 @@ void Sparc32LinuxProcess::handleTrap(int trapNum, ThreadContext *tc) } } -Sparc64LinuxProcess::Sparc64LinuxProcess(const std::string &name, - ObjectFile *objFile, - System * system, - int stdin_fd, - int stdout_fd, - int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid) - : Sparc64LiveProcess(name, objFile, system, - stdin_fd, stdout_fd, stderr_fd, argv, envp, cwd, - _uid, _euid, _gid, _egid, _pid, _ppid) +Sparc64LinuxProcess::Sparc64LinuxProcess(LiveProcessParams * params, + ObjectFile *objFile) + : Sparc64LiveProcess(params, objFile) {} void Sparc64LinuxProcess::handleTrap(int trapNum, ThreadContext *tc) diff --git a/src/arch/sparc/linux/process.hh b/src/arch/sparc/linux/process.hh index 6c7f30a43..06eee9235 100644 --- a/src/arch/sparc/linux/process.hh +++ b/src/arch/sparc/linux/process.hh @@ -65,16 +65,7 @@ class Sparc32LinuxProcess : public SparcLinuxProcess, public Sparc32LiveProcess { public: /// Constructor. - Sparc32LinuxProcess(const std::string &name, - ObjectFile *objFile, - System * system, - int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid); + Sparc32LinuxProcess(LiveProcessParams * params, ObjectFile *objFile); SyscallDesc* getDesc(int callnum) { @@ -89,16 +80,7 @@ class Sparc64LinuxProcess : public SparcLinuxProcess, public Sparc64LiveProcess { public: /// Constructor. - Sparc64LinuxProcess(const std::string &name, - ObjectFile *objFile, - System * system, - int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid); + Sparc64LinuxProcess(LiveProcessParams * params, ObjectFile *objFile); SyscallDesc* getDesc(int callnum) { diff --git a/src/arch/sparc/pagetable.hh b/src/arch/sparc/pagetable.hh index 961870579..bf7f34b60 100644 --- a/src/arch/sparc/pagetable.hh +++ b/src/arch/sparc/pagetable.hh @@ -190,16 +190,43 @@ struct TlbRange { struct TlbEntry { - Addr pageStart; + TlbEntry(Addr asn, Addr vaddr, Addr paddr) + { + uint64_t entry = 0; + entry |= 1ULL << 1; // Writable + entry |= 0ULL << 2; // Available in nonpriveleged mode + entry |= 0ULL << 3; // No side effects + entry |= 1ULL << 4; // Virtually cachable + entry |= 1ULL << 5; // Physically cachable + entry |= 0ULL << 6; // Not locked + entry |= mbits(paddr, 39, 13); // Physical address + entry |= 0ULL << 48; // size = 8k + entry |= 0uLL << 59; // Endianness not inverted + entry |= 0ULL << 60; // Not no fault only + entry |= 0ULL << 61; // size = 8k + entry |= 1ULL << 63; // valid + pte = PageTableEntry(entry); + + range.va = vaddr; + range.size = 8*(1<<10); + range.contextId = asn; + range.partitionId = 0; + range.real = false; + + valid = true; + } TlbEntry() {} - TlbEntry(Addr addr) : pageStart(addr) - {} TlbRange range; PageTableEntry pte; bool used; bool valid; + Addr pageStart() + { + return pte.paddr(); + } + void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh index d990c3256..13ce5c1b6 100644 --- a/src/arch/sparc/predecoder.hh +++ b/src/arch/sparc/predecoder.hh @@ -65,6 +65,9 @@ namespace SparcISA { } + void reset() + {} + //Use this to give data to the predecoder. This should be used //when there is control flow. void moreBytes(Addr pc, Addr fetchPC, MachInst inst) diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 29b1a244b..ffe430ac7 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -47,14 +47,9 @@ using namespace std; using namespace SparcISA; -SparcLiveProcess::SparcLiveProcess(const std::string &nm, ObjectFile *objFile, - System *_system, int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid) - : LiveProcess(nm, objFile, _system, stdin_fd, stdout_fd, stderr_fd, - argv, envp, cwd, _uid, _euid, _gid, _egid, _pid, _ppid) +SparcLiveProcess::SparcLiveProcess(LiveProcessParams * params, + ObjectFile *objFile) + : LiveProcess(params, objFile) { // XXX all the below need to be updated for SPARC - Ali @@ -73,8 +68,39 @@ void SparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc) { switch(trapNum) { + case 0x01: //Software breakpoint + warn("Software breakpoint encountered at pc %#x.\n", tc->readPC()); + break; + case 0x02: //Division by zero + warn("Software signaled a division by zero at pc %#x.\n", + tc->readPC()); + break; case 0x03: //Flush window trap - warn("Ignoring request to flush register windows.\n"); + flushWindows(tc); + break; + case 0x04: //Clean windows + warn("Ignoring process request for clean register " + "windows at pc %#x.\n", tc->readPC()); + break; + case 0x05: //Range check + warn("Software signaled a range check at pc %#x.\n", + tc->readPC()); + break; + case 0x06: //Fix alignment + warn("Ignoring process request for os assisted unaligned accesses " + "at pc %#x.\n", tc->readPC()); + break; + case 0x07: //Integer overflow + warn("Software signaled an integer overflow at pc %#x.\n", + tc->readPC()); + break; + case 0x32: //Get integer condition codes + warn("Ignoring process request to get the integer condition codes " + "at pc %#x.\n", tc->readPC()); + break; + case 0x33: //Set integer condition codes + warn("Ignoring process request to set the integer condition codes " + "at pc %#x.\n", tc->readPC()); break; default: panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); @@ -84,6 +110,9 @@ void SparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc) void Sparc32LiveProcess::startup() { + if (checkpointRestored) + return; + argsInit(32 / 8, VMPageSize); //From the SPARC ABI @@ -636,3 +665,73 @@ Sparc32LiveProcess::argsInit(int intSize, int pageSize) // num_processes++; } + +void Sparc32LiveProcess::flushWindows(ThreadContext *tc) +{ + IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); + IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); + IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); + MiscReg CWP = tc->readMiscReg(MISCREG_CWP); + MiscReg origCWP = CWP; + CWP = (CWP + Cansave + 2) % NWindows; + while(NWindows - 2 - Cansave != 0) + { + if (Otherwin) { + panic("Otherwin non-zero.\n"); + } else { + tc->setMiscReg(MISCREG_CWP, CWP); + //Do the stores + IntReg sp = tc->readIntReg(StackPointerReg); + for (int index = 16; index < 32; index++) { + IntReg regVal = tc->readIntReg(index); + regVal = htog(regVal); + if (!tc->getMemPort()->tryWriteBlob( + sp + (index - 16) * 4, (uint8_t *)®Val, 4)) { + warn("Failed to save register to the stack when " + "flushing windows.\n"); + } + } + Canrestore--; + Cansave++; + CWP = (CWP + 1) % NWindows; + } + } + tc->setIntReg(NumIntArchRegs + 3, Cansave); + tc->setIntReg(NumIntArchRegs + 4, Canrestore); + tc->setMiscReg(MISCREG_CWP, origCWP); +} + +void Sparc64LiveProcess::flushWindows(ThreadContext *tc) +{ + IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); + IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); + IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); + MiscReg CWP = tc->readMiscReg(MISCREG_CWP); + MiscReg origCWP = CWP; + CWP = (CWP + Cansave + 2) % NWindows; + while(NWindows - 2 - Cansave != 0) + { + if (Otherwin) { + panic("Otherwin non-zero.\n"); + } else { + tc->setMiscReg(MISCREG_CWP, CWP); + //Do the stores + IntReg sp = tc->readIntReg(StackPointerReg); + for (int index = 16; index < 32; index++) { + IntReg regVal = tc->readIntReg(index); + regVal = htog(regVal); + if (!tc->getMemPort()->tryWriteBlob( + sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) { + warn("Failed to save register to the stack when " + "flushing windows.\n"); + } + } + Canrestore--; + Cansave++; + CWP = (CWP + 1) % NWindows; + } + } + tc->setIntReg(NumIntArchRegs + 3, Cansave); + tc->setIntReg(NumIntArchRegs + 4, Canrestore); + tc->setMiscReg(MISCREG_CWP, origCWP); +} diff --git a/src/arch/sparc/process.hh b/src/arch/sparc/process.hh index 2512441c6..dd8eae316 100644 --- a/src/arch/sparc/process.hh +++ b/src/arch/sparc/process.hh @@ -46,14 +46,7 @@ class SparcLiveProcess : public LiveProcess //The locations of the fill and spill handlers Addr fillStart, spillStart; - SparcLiveProcess(const std::string &nm, ObjectFile *objFile, - System *_system, int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid); + SparcLiveProcess(LiveProcessParams * params, ObjectFile *objFile); public: @@ -66,6 +59,7 @@ class SparcLiveProcess : public LiveProcess Addr readSpillStart() { return spillStart; } + virtual void flushWindows(ThreadContext *tc) = 0; }; struct M5_32_auxv_t @@ -89,18 +83,8 @@ class Sparc32LiveProcess : public SparcLiveProcess std::vector<M5_32_auxv_t> auxv; - Sparc32LiveProcess(const std::string &nm, ObjectFile *objFile, - System *_system, int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid) : - SparcLiveProcess(nm, objFile, _system, - stdin_fd, stdout_fd, stderr_fd, - argv, envp, cwd, - _uid, _euid, _gid, _egid, _pid, _ppid) + Sparc32LiveProcess(LiveProcessParams * params, ObjectFile *objFile) : + SparcLiveProcess(params, objFile) { // Set up stack. On SPARC Linux, stack goes from the top of memory // downward, less the hole for the kernel address space. @@ -116,6 +100,7 @@ class Sparc32LiveProcess : public SparcLiveProcess void argsInit(int intSize, int pageSize); + void flushWindows(ThreadContext *tc); }; struct M5_64_auxv_t @@ -141,18 +126,8 @@ class Sparc64LiveProcess : public SparcLiveProcess std::vector<M5_64_auxv_t> auxv; - Sparc64LiveProcess(const std::string &nm, ObjectFile *objFile, - System *_system, int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid) : - SparcLiveProcess(nm, objFile, _system, - stdin_fd, stdout_fd, stderr_fd, - argv, envp, cwd, - _uid, _euid, _gid, _egid, _pid, _ppid) + Sparc64LiveProcess(LiveProcessParams * params, ObjectFile *objFile) : + SparcLiveProcess(params, objFile) { // Set up stack. On SPARC Linux, stack goes from the top of memory // downward, less the hole for the kernel address space. @@ -169,6 +144,7 @@ class Sparc64LiveProcess : public SparcLiveProcess void argsInit(int intSize, int pageSize); + void flushWindows(ThreadContext *tc); }; #endif // __SPARC_PROCESS_HH__ diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index f3e253f7e..c03f69fc5 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -122,6 +122,12 @@ namespace SparcISA int flattenIntIndex(ThreadContext * tc, int reg); + static inline int + flattenFloatIndex(ThreadContext * tc, int reg) + { + return reg; + } + void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc index 85b0c03a3..67cc5b0d1 100644 --- a/src/arch/sparc/remote_gdb.cc +++ b/src/arch/sparc/remote_gdb.cc @@ -130,8 +130,10 @@ #include "config/full_system.hh" #include "cpu/thread_context.hh" #include "cpu/static_inst.hh" +#include "mem/page_table.hh" #include "mem/physical.hh" #include "mem/port.hh" +#include "sim/process.hh" #include "sim/system.hh" using namespace std; @@ -150,11 +152,20 @@ bool RemoteGDB::acc(Addr va, size_t len) { //@Todo In NetBSD, this function checks if all addresses - //from va to va + len have valid page mape entries. Not + //from va to va + len have valid page map entries. Not //sure how this will work for other OSes or in general. +#if FULL_SYSTEM if (va) return true; return false; +#else + TlbEntry entry; + //Check to make sure the first byte is mapped into the processes address + //space. + if (context->getProcessPtr()->pTable->lookup(va, entry)) + return true; + return false; +#endif } /////////////////////////////////////////////////////////// diff --git a/src/arch/sparc/remote_gdb.hh b/src/arch/sparc/remote_gdb.hh index dbdf810c4..47e29ac02 100644 --- a/src/arch/sparc/remote_gdb.hh +++ b/src/arch/sparc/remote_gdb.hh @@ -55,7 +55,7 @@ namespace SparcISA /*RegState contains data in same format as tstate */ Reg32Y = 64, Reg32Psr = 65, Reg32Tbr = 66, Reg32Pc = 67, Reg32Npc = 68, Reg32Fsr = 69, Reg32Csr = 70, - NumGDBRegs = RegY + NumGDBRegs }; public: diff --git a/src/arch/sparc/solaris/process.cc b/src/arch/sparc/solaris/process.cc index f9876bf00..40d172690 100644 --- a/src/arch/sparc/solaris/process.cc +++ b/src/arch/sparc/solaris/process.cc @@ -321,24 +321,9 @@ SyscallDesc SparcSolarisProcess::syscallDescs[] = { /* 255 */ SyscallDesc("umount2", unimplementedFunc) }; -SparcSolarisProcess::SparcSolarisProcess(const std::string &name, - ObjectFile *objFile, - System * system, - int stdin_fd, - int stdout_fd, - int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, - uint64_t _euid, - uint64_t _gid, - uint64_t _egid, - uint64_t _pid, - uint64_t _ppid) - : SparcLiveProcess(name, objFile, system, - stdin_fd, stdout_fd, stderr_fd, argv, envp, cwd, - _uid, _euid, _gid, _egid, _pid, _ppid), +SparcSolarisProcess::SparcSolarisProcess(LiveProcessParams * params, + ObjectFile *objFile) + : Sparc64LiveProcess(params, objFile), Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)) { // The sparc syscall table must be <= 284 entries because that is all there diff --git a/src/arch/sparc/solaris/process.hh b/src/arch/sparc/solaris/process.hh index f65a60656..2cf56f6ba 100644 --- a/src/arch/sparc/solaris/process.hh +++ b/src/arch/sparc/solaris/process.hh @@ -38,20 +38,11 @@ namespace SparcISA { /// A process with emulated SPARC/Solaris syscalls. -class SparcSolarisProcess : public SparcLiveProcess +class SparcSolarisProcess : public Sparc64LiveProcess { public: /// Constructor. - SparcSolarisProcess(const std::string &name, - ObjectFile *objFile, - System * system, - int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid); + SparcSolarisProcess(LiveProcessParams * params, ObjectFile *objFile); virtual SyscallDesc* getDesc(int callnum); @@ -66,4 +57,4 @@ class SparcSolarisProcess : public SparcLiveProcess } // namespace SparcISA -#endif // __ALPHA_SOLARIS_PROCESS_HH__ +#endif // __SPARC_SOLARIS_PROCESS_HH__ diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 093e0356b..b6880ff94 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -1033,7 +1033,7 @@ doMmuReadError: (uint32_t)asi, va); } pkt->makeAtomicResponse(); - return tc->getCpuPtr()->cycles(1); + return tc->getCpuPtr()->ticks(1); } Tick @@ -1280,7 +1280,7 @@ doMmuWriteError: (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); } pkt->makeAtomicResponse(); - return tc->getCpuPtr()->cycles(1); + return tc->getCpuPtr()->ticks(1); } #endif diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 48e97a531..fe733813c 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -85,7 +85,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) if (!(tick_cmpr & ~mask(63)) && time > 0) { if (tickCompare->scheduled()) tickCompare->deschedule(); - tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); + tickCompare->schedule(time * tc->getCpuPtr()->ticks(1)); } panic("writing to TICK compare register %#X\n", val); break; @@ -101,7 +101,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) if (!(stick_cmpr & ~mask(63)) && time > 0) { if (sTickCompare->scheduled()) sTickCompare->deschedule(); - sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick); + sTickCompare->schedule(time * tc->getCpuPtr()->ticks(1) + curTick); } DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); break; @@ -171,7 +171,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) if (!(hstick_cmpr & ~mask(63)) && time > 0) { if (hSTickCompare->scheduled()) hSTickCompare->deschedule(); - hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1)); + hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->ticks(1)); } DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); break; @@ -315,7 +315,7 @@ MiscRegFile::processSTickCompare(ThreadContext *tc) setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); } } else - sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); + sTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick); } void @@ -341,6 +341,6 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc) } // Need to do something to cause interrupt to happen here !!! @todo } else - hSTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); + hSTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick); } diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 31e38abe1..68a18d4c0 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -88,22 +88,33 @@ Import('*') if env['TARGET_ISA'] == 'x86': Source('emulenv.cc') Source('floatregfile.cc') + Source('faults.cc') + Source('insts/microfpop.cc') Source('insts/microldstop.cc') + Source('insts/microop.cc') Source('insts/microregop.cc') Source('insts/static_inst.cc') Source('intregfile.cc') Source('miscregfile.cc') + Source('pagetable.cc') Source('predecoder.cc') Source('predecoder_tables.cc') Source('regfile.cc') Source('remote_gdb.cc') Source('tlb.cc') + Source('utility.cc') SimObject('X86TLB.py') + TraceFlag('Predecoder') + TraceFlag('X86') if env['FULL_SYSTEM']: + SimObject('X86System.py') + # Full-system sources - pass + Source('system.cc') + Source('stacktrace.cc') + Source('vtophys.cc') else: Source('process.cc') @@ -112,72 +123,221 @@ if env['TARGET_ISA'] == 'x86': Source('linux/syscalls.cc') python_files = ( - '__init__.py', - 'arithmetic/__init__.py', - 'arithmetic/add_and_subtract.py', - 'arithmetic/increment_and_decrement.py', - 'arithmetic/multiply_and_divide.py', - 'cache_and_memory_management.py', - 'compare_and_test/__init__.py', - 'compare_and_test/bit_scan.py', - 'compare_and_test/bit_test.py', - 'compare_and_test/bounds.py', - 'compare_and_test/compare.py', - 'compare_and_test/set_byte_on_condition.py', - 'compare_and_test/test.py', - 'control_transfer/__init__.py', - 'control_transfer/call.py', - 'control_transfer/conditional_jump.py', - 'control_transfer/interrupts_and_exceptions.py', - 'control_transfer/jump.py', - 'control_transfer/loop.py', - 'control_transfer/xreturn.py', - 'data_conversion/__init__.py', - 'data_conversion/ascii_adjust.py', - 'data_conversion/bcd_adjust.py', - 'data_conversion/endian_conversion.py', - 'data_conversion/extract_sign_mask.py', - 'data_conversion/sign_extension.py', - 'data_conversion/translate.py', - 'data_transfer/__init__.py', - 'data_transfer/conditional_move.py', - 'data_transfer/move.py', - 'data_transfer/stack_operations.py', - 'data_transfer/xchg.py', - 'flags/__init__.py', - 'flags/load_and_store.py', - 'flags/push_and_pop.py', - 'flags/set_and_clear.py', - 'input_output/__init__.py', - 'input_output/general_io.py', - 'input_output/string_io.py', - 'load_effective_address.py', - 'load_segment_registers.py', - 'logical.py', - 'no_operation.py', - 'processor_information.py', - 'rotate_and_shift/__init__.py', - 'rotate_and_shift/rotate.py', - 'rotate_and_shift/shift.py', - 'semaphores.py', - 'string/__init__.py', - 'string/compare_strings.py', - 'string/load_string.py', - 'string/move_string.py', - 'string/scan_string.py', - 'string/store_string.py', - 'system/__init__.py', - 'system/undefined_operation.py', - 'system_calls.py', - 'sse/__init__.py', - 'sse/move.py', - 'sse/convert.py', - 'sse/add_and_subtract.py', - 'sse/multiply_and_divide.py', - 'sse/logical.py', - 'sse/compare.py', - 'sse/square_root.py' - ) + '__init__.py', + 'general_purpose/__init__.py', + 'general_purpose/arithmetic/__init__.py', + 'general_purpose/arithmetic/add_and_subtract.py', + 'general_purpose/arithmetic/increment_and_decrement.py', + 'general_purpose/arithmetic/multiply_and_divide.py', + 'general_purpose/cache_and_memory_management.py', + 'general_purpose/compare_and_test/__init__.py', + 'general_purpose/compare_and_test/bit_scan.py', + 'general_purpose/compare_and_test/bit_test.py', + 'general_purpose/compare_and_test/bounds.py', + 'general_purpose/compare_and_test/compare.py', + 'general_purpose/compare_and_test/set_byte_on_condition.py', + 'general_purpose/compare_and_test/test.py', + 'general_purpose/control_transfer/__init__.py', + 'general_purpose/control_transfer/call.py', + 'general_purpose/control_transfer/conditional_jump.py', + 'general_purpose/control_transfer/interrupts_and_exceptions.py', + 'general_purpose/control_transfer/jump.py', + 'general_purpose/control_transfer/loop.py', + 'general_purpose/control_transfer/xreturn.py', + 'general_purpose/data_conversion/__init__.py', + 'general_purpose/data_conversion/ascii_adjust.py', + 'general_purpose/data_conversion/bcd_adjust.py', + 'general_purpose/data_conversion/endian_conversion.py', + 'general_purpose/data_conversion/extract_sign_mask.py', + 'general_purpose/data_conversion/sign_extension.py', + 'general_purpose/data_conversion/translate.py', + 'general_purpose/data_transfer/__init__.py', + 'general_purpose/data_transfer/conditional_move.py', + 'general_purpose/data_transfer/move.py', + 'general_purpose/data_transfer/stack_operations.py', + 'general_purpose/data_transfer/xchg.py', + 'general_purpose/flags/__init__.py', + 'general_purpose/flags/load_and_store.py', + 'general_purpose/flags/push_and_pop.py', + 'general_purpose/flags/set_and_clear.py', + 'general_purpose/input_output/__init__.py', + 'general_purpose/input_output/general_io.py', + 'general_purpose/input_output/string_io.py', + 'general_purpose/load_effective_address.py', + 'general_purpose/load_segment_registers.py', + 'general_purpose/logical.py', + 'general_purpose/no_operation.py', + 'general_purpose/processor_information.py', + 'general_purpose/rotate_and_shift/__init__.py', + 'general_purpose/rotate_and_shift/rotate.py', + 'general_purpose/rotate_and_shift/shift.py', + 'general_purpose/semaphores.py', + 'general_purpose/string/__init__.py', + 'general_purpose/string/compare_strings.py', + 'general_purpose/string/load_string.py', + 'general_purpose/string/move_string.py', + 'general_purpose/string/scan_string.py', + 'general_purpose/string/store_string.py', + 'general_purpose/system_calls.py', + 'system/__init__.py', + 'system/halt.py', + 'system/undefined_operation.py', + 'system/msrs.py', + 'simd128/__init__.py', + 'simd128/integer/__init__.py', + 'simd128/integer/data_transfer/__init__.py', + 'simd128/integer/data_transfer/move.py', + 'simd128/integer/data_transfer/move_non_temporal.py', + 'simd128/integer/data_transfer/move_mask.py', + 'simd128/integer/data_conversion/__init__.py', + 'simd128/integer/data_conversion/convert_mmx_integer_to_floating_point.py', + 'simd128/integer/data_conversion/convert_integer_to_floating_point.py', + 'simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py', + 'simd128/integer/data_reordering/__init__.py', + 'simd128/integer/data_reordering/unpack_and_interleave.py', + 'simd128/integer/data_reordering/pack_with_saturation.py', + 'simd128/integer/data_reordering/extract_and_insert.py', + 'simd128/integer/data_reordering/shuffle.py', + 'simd128/integer/arithmetic/__init__.py', + 'simd128/integer/arithmetic/subtraction.py', + 'simd128/integer/arithmetic/addition.py', + 'simd128/integer/arithmetic/multiplication.py', + 'simd128/integer/arithmetic/multiply_add.py', + 'simd128/integer/arithmetic/average.py', + 'simd128/integer/arithmetic/sum_of_absolute_differences.py', + 'simd128/integer/shift/__init__.py', + 'simd128/integer/shift/right_arithmetic_shift.py', + 'simd128/integer/shift/left_logical_shift.py', + 'simd128/integer/shift/right_logical_shift.py', + 'simd128/integer/compare/__init__.py', + 'simd128/integer/compare/compare_and_write_mask.py', + 'simd128/integer/compare/compare_and_write_minimum_or_maximum.py', + 'simd128/integer/logical/__init__.py', + 'simd128/integer/logical/pand.py', + 'simd128/integer/logical/por.py', + 'simd128/integer/logical/exclusive_or.py', + 'simd128/integer/save_and_restore_state/__init__.py', + 'simd128/integer/save_and_restore_state/save_and_restore_state.py', + 'simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py', + 'simd128/floating_point/__init__.py', + 'simd128/floating_point/data_transfer/__init__.py', + 'simd128/floating_point/data_transfer/move_mask.py', + 'simd128/floating_point/data_transfer/move.py', + 'simd128/floating_point/data_transfer/move_with_duplication.py', + 'simd128/floating_point/data_transfer/move_non_temporal.py', + 'simd128/floating_point/data_conversion/__init__.py', + 'simd128/floating_point/data_conversion/convert_floating_point_to_floating_point.py', + 'simd128/floating_point/data_conversion/convert_floating_point_to_xmm_integer.py', + 'simd128/floating_point/data_conversion/convert_floating_point_to_mmx_integer.py', + 'simd128/floating_point/data_conversion/convert_floating_point_to_gpr_integer.py', + 'simd128/floating_point/data_reordering/__init__.py', + 'simd128/floating_point/data_reordering/unpack_and_interleave.py', + 'simd128/floating_point/data_reordering/shuffle.py', + 'simd128/floating_point/arithmetic/__init__.py', + 'simd128/floating_point/arithmetic/subtraction.py', + 'simd128/floating_point/arithmetic/addition.py', + 'simd128/floating_point/arithmetic/horizontal_subtraction.py', + 'simd128/floating_point/arithmetic/horizontal_addition.py', + 'simd128/floating_point/arithmetic/square_root.py', + 'simd128/floating_point/arithmetic/simultaneous_addition_and_subtraction.py', + 'simd128/floating_point/arithmetic/multiplication.py', + 'simd128/floating_point/arithmetic/division.py', + 'simd128/floating_point/arithmetic/reciprocal_square_root.py', + 'simd128/floating_point/arithmetic/reciprocal_estimation.py', + 'simd128/floating_point/compare/__init__.py', + 'simd128/floating_point/compare/compare_and_write_mask.py', + 'simd128/floating_point/compare/compare_and_write_rflags.py', + 'simd128/floating_point/compare/compare_and_write_minimum_or_maximum.py', + 'simd128/floating_point/logical/__init__.py', + 'simd128/floating_point/logical/andp.py', + 'simd128/floating_point/logical/orp.py', + 'simd128/floating_point/logical/exclusive_or.py', + 'simd64/__init__.py', + 'simd64/integer/__init__.py', + 'simd64/integer/data_transfer/__init__.py', + 'simd64/integer/data_transfer/move_mask.py', + 'simd64/integer/data_transfer/move.py', + 'simd64/integer/data_transfer/move_non_temporal.py', + 'simd64/integer/exit_media_state.py', + 'simd64/integer/data_reordering/__init__.py', + 'simd64/integer/data_reordering/unpack_and_interleave.py', + 'simd64/integer/data_reordering/pack_with_saturation.py', + 'simd64/integer/data_reordering/extract_and_insert.py', + 'simd64/integer/data_reordering/shuffle_and_swap.py', + 'simd64/integer/data_conversion.py', + 'simd64/integer/arithmetic/__init__.py', + 'simd64/integer/arithmetic/subtraction.py', + 'simd64/integer/arithmetic/addition.py', + 'simd64/integer/arithmetic/multiplication.py', + 'simd64/integer/arithmetic/multiply_add.py', + 'simd64/integer/arithmetic/average.py', + 'simd64/integer/arithmetic/sum_of_absolute_differences.py', + 'simd64/integer/shift/__init__.py', + 'simd64/integer/shift/right_arithmetic_shift.py', + 'simd64/integer/shift/left_logical_shift.py', + 'simd64/integer/shift/right_logical_shift.py', + 'simd64/integer/compare/__init__.py', + 'simd64/integer/compare/compare_and_write_mask.py', + 'simd64/integer/compare/compare_and_write_minimum_or_maximum.py', + 'simd64/integer/logical/__init__.py', + 'simd64/integer/logical/pand.py', + 'simd64/integer/logical/por.py', + 'simd64/integer/logical/exclusive_or.py', + 'simd64/integer/save_and_restore_state.py', + 'simd64/floating_point/__init__.py', + 'simd64/floating_point/arithmetic/__init__.py', + 'simd64/floating_point/arithmetic/subtraction.py', + 'simd64/floating_point/arithmetic/addition.py', + 'simd64/floating_point/arithmetic/reciprocal_estimation.py', + 'simd64/floating_point/arithmetic/multiplication.py', + 'simd64/floating_point/arithmetic/accumulation.py', + 'simd64/floating_point/arithmetic/reciprocal_square_root.py', + 'simd64/floating_point/data_conversion.py', + 'simd64/floating_point/compare/__init__.py', + 'simd64/floating_point/compare/compare_and_write_mask.py', + 'simd64/floating_point/compare/compare_and_write_minimum_or_maximum.py', + 'x87/__init__.py', + 'x87/data_transfer_and_conversion/__init__.py', + 'x87/data_transfer_and_conversion/convert_and_load_or_store_integer.py', + 'x87/data_transfer_and_conversion/load_or_store_floating_point.py', + 'x87/data_transfer_and_conversion/exchange.py', + 'x87/data_transfer_and_conversion/convert_and_load_or_store_bcd.py', + 'x87/data_transfer_and_conversion/conditional_move.py', + 'x87/data_transfer_and_conversion/extract.py', + 'x87/load_constants/__init__.py', + 'x87/load_constants/load_0_1_or_pi.py', + 'x87/load_constants/load_logarithm.py', + 'x87/arithmetic/__init__.py', + 'x87/arithmetic/subtraction.py', + 'x87/arithmetic/addition.py', + 'x87/arithmetic/partial_remainder.py', + 'x87/arithmetic/multiplication.py', + 'x87/arithmetic/division.py', + 'x87/arithmetic/change_sign.py', + 'x87/arithmetic/round.py', + 'x87/arithmetic/square_root.py', + 'x87/transcendental_functions/__init__.py', + 'x87/transcendental_functions/trigonometric_functions.py', + 'x87/transcendental_functions/logarithmic_functions.py', + 'x87/compare_and_test/__init__.py', + 'x87/compare_and_test/classify.py', + 'x87/compare_and_test/test.py', + 'x87/compare_and_test/floating_point_ordered_compare.py', + 'x87/compare_and_test/floating_point_unordered_compare.py', + 'x87/compare_and_test/integer_compare.py', + 'x87/stack_management/__init__.py', + 'x87/stack_management/stack_control.py', + 'x87/stack_management/clear_state.py', + 'x87/control/__init__.py', + 'x87/control/clear_exceptions.py', + 'x87/control/initialize.py', + 'x87/control/wait_for_exceptions.py', + 'x87/control/save_x87_status_word.py', + 'x87/control/save_and_restore_x87_control_word.py', + 'x87/control/save_and_restore_x87_environment.py', + 'x87/no_operation.py' + ) + # Add in files generated by the ISA description. isa_desc_files = env.ISADesc('isa/main.isa') diff --git a/src/arch/x86/isa/insts/control_transfer/loop.py b/src/arch/x86/X86System.py index d742f217f..329c72aaf 100644 --- a/src/arch/x86/isa/insts/control_transfer/loop.py +++ b/src/arch/x86/X86System.py @@ -53,8 +53,8 @@ # # Authors: Gabe Black -microcode = "" -#let {{ -# class LOOPcc(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; +from m5.params import * +from System import System + +class X86System(System): + type = 'X86System' diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index f16408e63..ce4db4f4c 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -58,18 +58,18 @@ from m5.params import * class X86TLB(SimObject): type = 'X86TLB' abstract = True - #size = Param.Int("TLB size") + size = Param.Int("TLB size") class X86DTB(X86TLB): type = 'X86DTB' cxx_namespace = 'X86ISA' cxx_class = 'DTB' - #size = 64 + size = 64 class X86ITB(X86TLB): type = 'X86ITB' cxx_namespace = 'X86ISA' cxx_class = 'ITB' - #size = 64 + size = 64 diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc new file mode 100644 index 000000000..13341f1de --- /dev/null +++ b/src/arch/x86/faults.cc @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2003-2007 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/x86/faults.hh" +#include "base/trace.hh" +#include "config/full_system.hh" +#include "cpu/thread_context.hh" +#if !FULL_SYSTEM +#include "arch/x86/isa_traits.hh" +#include "mem/page_table.hh" +#include "sim/process.hh" +#endif + +namespace X86ISA +{ +#if FULL_SYSTEM + void X86Trap::invoke(ThreadContext * tc) + { + panic("X86 faults are not implemented!"); + } + + void X86Abort::invoke(ThreadContext * tc) + { + panic("X86 faults are not implemented!"); + } + + void X86Interrupt::invoke(ThreadContext * tc) + { + panic("X86 faults are not implemented!"); + } +#else // !FULL_SYSTEM + void FakeITLBFault::invoke(ThreadContext * tc) + { + DPRINTF(TLB, "Invoking an ITLB fault for address %#x at pc %#x.\n", + vaddr, tc->readPC()); + Process *p = tc->getProcessPtr(); + TlbEntry entry; + bool success = p->pTable->lookup(vaddr, entry); + if(!success) { + panic("Tried to execute unmapped address %#x.\n", vaddr); + } else { + Addr alignedVaddr = p->pTable->pageAlign(vaddr); + DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, + entry.pageStart()); + tc->getITBPtr()->insert(alignedVaddr, entry); + } + } + + void FakeDTLBFault::invoke(ThreadContext * tc) + { + DPRINTF(TLB, "Invoking an DTLB fault for address %#x at pc %#x.\n", + vaddr, tc->readPC()); + Process *p = tc->getProcessPtr(); + TlbEntry entry; + bool success = p->pTable->lookup(vaddr, entry); + if(!success) { + p->checkAndAllocNextPage(vaddr); + success = p->pTable->lookup(vaddr, entry); + } + if(!success) { + panic("Tried to access unmapped address %#x.\n", vaddr); + } else { + Addr alignedVaddr = p->pTable->pageAlign(vaddr); + DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, + entry.pageStart()); + tc->getDTBPtr()->insert(alignedVaddr, entry); + } + } +#endif +} // namespace X86ISA + diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh index 936d0357c..5a573754a 100644 --- a/src/arch/x86/faults.hh +++ b/src/arch/x86/faults.hh @@ -63,20 +63,90 @@ namespace X86ISA { - class X86Fault : public FaultBase + // Base class for all x86 "faults" where faults is in the m5 sense + class X86FaultBase : public FaultBase { protected: + const char * faultName; + const char * mnem; + uint64_t errorCode; + + X86FaultBase(const char * _faultName, const char * _mnem, + uint64_t _errorCode = 0) : + faultName(_faultName), mnem(_mnem), errorCode(_errorCode) + { + } + const char * name() const { - return "generic_x86_fault"; + return faultName; } - void invoke(ThreadContext * tc) + virtual bool isBenign() + { + return true; + } + + virtual const char * mnemonic() const { - panic("X86 faults are not implemented!"); + return mnem; } }; + // Base class for x86 faults which behave as if the underlying instruction + // didn't happen. + class X86Fault : public X86FaultBase + { + protected: + X86Fault(const char * name, const char * mnem, + uint64_t _errorCode = 0) : + X86FaultBase(name, mnem, _errorCode) + {} + }; + + // Base class for x86 traps which behave as if the underlying instruction + // completed. + class X86Trap : public X86FaultBase + { + protected: + X86Trap(const char * name, const char * mnem, + uint64_t _errorCode = 0) : + X86FaultBase(name, mnem, _errorCode) + {} + +#if FULL_SYSTEM + void invoke(ThreadContext * tc); +#endif + }; + + // Base class for x86 aborts which seem to be catastrophic failures. + class X86Abort : public X86FaultBase + { + protected: + X86Abort(const char * name, const char * mnem, + uint64_t _errorCode = 0) : + X86FaultBase(name, mnem, _errorCode) + {} + +#if FULL_SYSTEM + void invoke(ThreadContext * tc); +#endif + }; + + // Base class for x86 interrupts. + class X86Interrupt : public X86FaultBase + { + protected: + X86Interrupt(const char * name, const char * mnem, + uint64_t _errorCode = 0) : + X86FaultBase(name, mnem, _errorCode) + {} + +#if FULL_SYSTEM + void invoke(ThreadContext * tc); +#endif + }; + class UnimpInstFault : public FaultBase { public: @@ -95,6 +165,249 @@ namespace X86ISA { panic("Machine check fault not implemented in x86!\n"); } + + // Below is a summary of the interrupt/exception information in the + // architecture manuals. + + // Class | Type | vector | Cause | mnem + //------------------------------------------------------------------------ + //Contrib Fault 0 Divide-by-Zero-Error #DE + //Benign Either 1 Debug #DB + //Benign Interrupt 2 Non-Maskable-Interrupt #NMI + //Benign Trap 3 Breakpoint #BP + //Benign Trap 4 Overflow #OF + //Benign Fault 5 Bound-Range #BR + //Benign Fault 6 Invalid-Opcode #UD + //Benign Fault 7 Device-Not-Available #NM + //Benign Abort 8 Double-Fault #DF + // 9 Coprocessor-Segment-Overrun + //Contrib Fault 10 Invalid-TSS #TS + //Contrib Fault 11 Segment-Not-Present #NP + //Contrib Fault 12 Stack #SS + //Contrib Fault 13 General-Protection #GP + //Either Fault 14 Page-Fault #PF + // 15 Reserved + //Benign Fault 16 x87 Floating-Point Exception Pending #MF + //Benign Fault 17 Alignment-Check #AC + //Benign Abort 18 Machine-Check #MC + //Benign Fault 19 SIMD Floating-Point #XF + // 20-29 Reserved + //Contrib ? 30 Security Exception #SX + // 31 Reserved + //Benign Interrupt 0-255 External Interrupts #INTR + //Benign Interrupt 0-255 Software Interrupts INTn + + class DivideByZero : public X86Fault + { + public: + DivideByZero() : + X86Fault("Divide-by-Zero-Error", "#DE") + {} + }; + + class DebugException : public X86FaultBase + { + public: + DebugException() : + X86FaultBase("Debug", "#DB") + {} + }; + + class NonMaskableInterrupt : public X86Interrupt + { + public: + NonMaskableInterrupt() : + X86Interrupt("Non-Maskable-Interrupt", "#NMI") + {} + }; + + class Breakpoint : public X86Trap + { + public: + Breakpoint() : + X86Trap("Breakpoint", "#BP") + {} + }; + + class OverflowTrap : public X86Trap + { + public: + OverflowTrap() : + X86Trap("Overflow", "#OF") + {} + }; + + class BoundRange : public X86Fault + { + public: + BoundRange() : + X86Fault("Bound-Range", "#BR") + {} + }; + + class InvalidOpcode : public X86Fault + { + public: + InvalidOpcode() : + X86Fault("Invalid-Opcode", "#UD") + {} + }; + + class DeviceNotAvailable : public X86Fault + { + public: + DeviceNotAvailable() : + X86Fault("Device-Not-Available", "#NM") + {} + }; + + class DoubleFault : public X86Abort + { + public: + DoubleFault() : + X86Abort("Double-Fault", "#DF") + {} + }; + + class InvalidTSS : public X86Fault + { + public: + InvalidTSS() : + X86Fault("Invalid-TSS", "#TS") + {} + }; + + class SegmentNotPresent : public X86Fault + { + public: + SegmentNotPresent() : + X86Fault("Segment-Not-Present", "#NP") + {} + }; + + class StackFault : public X86Fault + { + public: + StackFault() : + X86Fault("Stack", "#SS") + {} + }; + + class GeneralProtection : public X86Fault + { + public: + GeneralProtection(uint64_t _errorCode) : + X86Fault("General-Protection", "#GP", _errorCode) + {} + }; + + class PageFault : public X86Fault + { + public: + PageFault() : + X86Fault("Page-Fault", "#PF") + {} + }; + + class X87FpExceptionPending : public X86Fault + { + public: + X87FpExceptionPending() : + X86Fault("x87 Floating-Point Exception Pending", "#MF") + {} + }; + + class AlignmentCheck : X86Fault + { + public: + AlignmentCheck() : + X86Fault("Alignment-Check", "#AC") + {} + }; + + class MachineCheck : X86Abort + { + public: + MachineCheck() : + X86Abort("Machine-Check", "#MC") + {} + }; + + class SIMDFloatingPointFault : X86Fault + { + public: + SIMDFloatingPointFault() : + X86Fault("SIMD Floating-Point", "#XF") + {} + }; + + class SecurityException : X86FaultBase + { + public: + SecurityException() : + X86FaultBase("Security Exception", "#SX") + {} + }; + + class ExternalInterrupt : X86Interrupt + { + public: + ExternalInterrupt() : + X86Interrupt("External Interrupt", "#INTR") + {} + }; + + class SoftwareInterrupt : X86Interrupt + { + public: + SoftwareInterrupt() : + X86Interrupt("Software Interrupt", "INTn") + {} + }; + + // These faults aren't part of the ISA definition. They trigger filling + // the tlb on a miss and are to take the place of a hardware table walker. + class FakeITLBFault : public X86Fault + { +#if !FULL_SYSTEM + protected: + Addr vaddr; + public: + FakeITLBFault(Addr _vaddr) : + X86Fault("fake instruction tlb fault", "itlb"), + vaddr(_vaddr) +#else + public: + FakeITLBFault() : + X86Fault("fake instruction tlb fault", "itlb") +#endif + {} + +#if !FULL_SYSTEM + void invoke(ThreadContext * tc); +#endif + }; + + class FakeDTLBFault : public X86Fault + { +#if !FULL_SYSTEM + protected: + Addr vaddr; + public: + FakeDTLBFault(Addr _vaddr) : + X86Fault("fake data tlb fault", "dtlb"), + vaddr(_vaddr) +#else + public: + FakeDTLBFault() : + X86Fault("fake data tlb fault", "dtlb") +#endif + {} + +#if !FULL_SYSTEM + void invoke(ThreadContext * tc); +#endif + }; }; #endif // __ARCH_X86_FAULTS_HH__ diff --git a/src/arch/x86/floatregfile.hh b/src/arch/x86/floatregfile.hh index 14dda443f..b77ddb0eb 100644 --- a/src/arch/x86/floatregfile.hh +++ b/src/arch/x86/floatregfile.hh @@ -101,8 +101,9 @@ namespace X86ISA std::string getFloatRegName(RegIndex); //Each 128 bit xmm register is broken into two effective 64 bit registers. - const int NumFloatArchRegs = NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs; - const int NumFloatRegs = NumFloatArchRegs; + const int NumFloatRegs = + NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs; + const int NumFloatArchRegs = NumFloatRegs + 8; class FloatRegFile { diff --git a/src/arch/x86/floatregs.hh b/src/arch/x86/floatregs.hh index b9d6a5c43..dc9867c42 100644 --- a/src/arch/x86/floatregs.hh +++ b/src/arch/x86/floatregs.hh @@ -162,6 +162,12 @@ namespace X86ISA { return (FloatRegIndex)(FLOATREG_MICROFP_BASE + index); } + + static inline FloatRegIndex + FLOATREG_STACK(int index, int top) + { + return (FloatRegIndex)(NUM_FLOATREGS + ((top + index + 8) % 8)); + } }; #endif // __ARCH_X86_FLOATREGS_HH__ diff --git a/src/arch/x86/insts/microfpop.cc b/src/arch/x86/insts/microfpop.cc new file mode 100644 index 000000000..c25495da9 --- /dev/null +++ b/src/arch/x86/insts/microfpop.cc @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/x86/insts/microfpop.hh" +#include "arch/x86/miscregs.hh" +#include <string> + +namespace X86ISA +{ + /* + uint64_t FpOp::genFlags(uint64_t oldFlags, uint64_t flagMask, + uint64_t _dest, uint64_t _src1, uint64_t _src2, + bool subtract) const + { + } + */ + + std::string FpOp::generateDisassembly(Addr pc, + const SymbolTable *symtab) const + { + std::stringstream response; + + printMnemonic(response, instMnem, mnemonic); + printDestReg(response, 0, dataSize); + response << ", "; + printSrcReg(response, 0, dataSize); + response << ", "; + printSrcReg(response, 1, dataSize); + return response.str(); + } +} diff --git a/src/arch/x86/insts/microfpop.hh b/src/arch/x86/insts/microfpop.hh new file mode 100644 index 000000000..2e01cadbc --- /dev/null +++ b/src/arch/x86/insts/microfpop.hh @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_X86_INSTS_MICROFPOP_HH__ +#define __ARCH_X86_INSTS_MICROFPOP_HH__ + +#include "arch/x86/insts/microop.hh" + +namespace X86ISA +{ + + /** + * Base classes for FpOps which provides a generateDisassembly method. + */ + class FpOp : public X86MicroopBase + { + protected: + const RegIndex src1; + const RegIndex src2; + const RegIndex dest; + const uint8_t dataSize; + const int8_t spm; + + // Constructor + FpOp(ExtMachInst _machInst, + const char *mnem, const char *_instMnem, + bool isMicro, bool isDelayed, + bool isFirst, bool isLast, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + uint8_t _dataSize, int8_t _spm, + OpClass __opClass) : + X86MicroopBase(_machInst, mnem, _instMnem, + isMicro, isDelayed, isFirst, isLast, + __opClass), + src1(_src1), src2(_src2), dest(_dest), + dataSize(_dataSize), spm(_spm) + {} +/* + //Figure out what the condition code flags should be. + uint64_t genFlags(uint64_t oldFlags, uint64_t flagMask, + uint64_t _dest, uint64_t _src1, uint64_t _src2, + bool subtract = false) const; + bool checkCondition(uint64_t flags) const;*/ + + std::string generateDisassembly(Addr pc, + const SymbolTable *symtab) const; + }; +} + +#endif //__ARCH_X86_INSTS_MICROFPOP_HH__ diff --git a/src/arch/x86/insts/microop.cc b/src/arch/x86/insts/microop.cc new file mode 100644 index 000000000..494c0b303 --- /dev/null +++ b/src/arch/x86/insts/microop.cc @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/x86/insts/microop.hh" +#include "arch/x86/miscregs.hh" + +namespace X86ISA +{ + + bool X86MicroopBase::checkCondition(uint64_t flags, int condition) const + { + CCFlagBits ccflags = flags; + switch(condition) + { + case ConditionTests::True: + return true; + case ConditionTests::ECF: + return ccflags.ecf; + case ConditionTests::EZF: + return ccflags.ezf; + case ConditionTests::SZnZF: + return !(!ccflags.ezf & ccflags.zf); + case ConditionTests::MSTRZ: + panic("This condition is not implemented!"); + case ConditionTests::STRZ: + panic("This condition is not implemented!"); + case ConditionTests::MSTRC: + panic("This condition is not implemented!"); + case ConditionTests::STRZnEZF: + return !ccflags.ezf & ccflags.zf; + //And no interrupts or debug traps are waiting + case ConditionTests::OF: + return ccflags.of; + case ConditionTests::CF: + return ccflags.cf; + case ConditionTests::ZF: + return ccflags.zf; + case ConditionTests::CvZF: + return ccflags.cf | ccflags.zf; + case ConditionTests::SF: + return ccflags.sf; + case ConditionTests::PF: + return ccflags.pf; + case ConditionTests::SxOF: + return ccflags.sf ^ ccflags.of; + case ConditionTests::SxOvZF: + return ccflags.sf ^ ccflags.of | ccflags.zf; + case ConditionTests::False: + return false; + case ConditionTests::NotECF: + return !ccflags.ecf; + case ConditionTests::NotEZF: + return !ccflags.ezf; + case ConditionTests::NotSZnZF: + return !ccflags.ezf & ccflags.zf; + case ConditionTests::NotMSTRZ: + panic("This condition is not implemented!"); + case ConditionTests::NotSTRZ: + panic("This condition is not implemented!"); + case ConditionTests::NotMSTRC: + panic("This condition is not implemented!"); + case ConditionTests::STRnZnEZF: + return !ccflags.ezf & !ccflags.zf; + //And no interrupts or debug traps are waiting + case ConditionTests::NotOF: + return !ccflags.of; + case ConditionTests::NotCF: + return !ccflags.cf; + case ConditionTests::NotZF: + return !ccflags.zf; + case ConditionTests::NotCvZF: + return !(ccflags.cf | ccflags.zf); + case ConditionTests::NotSF: + return !ccflags.sf; + case ConditionTests::NotPF: + return !ccflags.pf; + case ConditionTests::NotSxOF: + return !(ccflags.sf ^ ccflags.of); + case ConditionTests::NotSxOvZF: + return !(ccflags.sf ^ ccflags.of | ccflags.zf); + } + panic("Unknown condition: %d\n", condition); + return true; + } +} diff --git a/src/arch/x86/insts/microop.hh b/src/arch/x86/insts/microop.hh index 45e1cb5c8..535bcb817 100644 --- a/src/arch/x86/insts/microop.hh +++ b/src/arch/x86/insts/microop.hh @@ -62,6 +62,47 @@ namespace X86ISA { + namespace ConditionTests + { + enum CondTest { + True, + NotFalse = True, + ECF, + EZF, + SZnZF, + MSTRZ, + STRZ, + MSTRC, + STRZnEZF, + OF, + CF, + ZF, + CvZF, + SF, + PF, + SxOF, + SxOvZF, + + False, + NotTrue = False, + NotECF, + NotEZF, + NotSZnZF, + NotMSTRZ, + NotSTRZ, + NotMSTRC, + STRnZnEZF, + NotOF, + NotCF, + NotZF, + NotCvZF, + NotSF, + NotPF, + NotSxOF, + NotSxOvZF + }; + } + //A class which is the base of all x86 micro ops. It provides a function to //set necessary flags appropriately. class X86MicroopBase : public X86StaticInst @@ -94,6 +135,8 @@ namespace X86ISA return ss.str(); } + + bool checkCondition(uint64_t flags, int condition) const; }; } diff --git a/src/arch/x86/insts/microregop.cc b/src/arch/x86/insts/microregop.cc index ad48a4bc1..080926627 100644 --- a/src/arch/x86/insts/microregop.cc +++ b/src/arch/x86/insts/microregop.cc @@ -66,7 +66,7 @@ namespace X86ISA uint64_t _dest, uint64_t _src1, uint64_t _src2, bool subtract) const { - DPRINTF(Sparc, "flagMask = %#x\n", flagMask); + DPRINTF(X86, "flagMask = %#x\n", flagMask); uint64_t flags = oldFlags & ~flagMask; if(flagMask & (ECFBit | CFBit)) { @@ -93,82 +93,6 @@ namespace X86ISA return flags; } - bool RegOpBase::checkCondition(uint64_t flags) const - { - CCFlagBits ccflags = flags; - switch(ext) - { - case ConditionTests::True: - return true; - case ConditionTests::ECF: - return ccflags.ECF; - case ConditionTests::EZF: - return ccflags.EZF; - case ConditionTests::SZnZF: - return !(!ccflags.EZF & ccflags.ZF); - case ConditionTests::MSTRZ: - panic("This condition is not implemented!"); - case ConditionTests::STRZ: - panic("This condition is not implemented!"); - case ConditionTests::MSTRC: - panic("This condition is not implemented!"); - case ConditionTests::STRZnEZF: - return !ccflags.EZF & ccflags.ZF; - //And no interrupts or debug traps are waiting - case ConditionTests::OF: - return ccflags.OF; - case ConditionTests::CF: - return ccflags.CF; - case ConditionTests::ZF: - return ccflags.ZF; - case ConditionTests::CvZF: - return ccflags.CF | ccflags.ZF; - case ConditionTests::SF: - return ccflags.SF; - case ConditionTests::PF: - return ccflags.PF; - case ConditionTests::SxOF: - return ccflags.SF ^ ccflags.OF; - case ConditionTests::SxOvZF: - return ccflags.SF ^ ccflags.OF | ccflags.ZF; - case ConditionTests::False: - return false; - case ConditionTests::NotECF: - return !ccflags.ECF; - case ConditionTests::NotEZF: - return !ccflags.EZF; - case ConditionTests::NotSZnZF: - return !ccflags.EZF & ccflags.ZF; - case ConditionTests::NotMSTRZ: - panic("This condition is not implemented!"); - case ConditionTests::NotSTRZ: - panic("This condition is not implemented!"); - case ConditionTests::NotMSTRC: - panic("This condition is not implemented!"); - case ConditionTests::STRnZnEZF: - return !ccflags.EZF & !ccflags.ZF; - //And no interrupts or debug traps are waiting - case ConditionTests::NotOF: - return !ccflags.OF; - case ConditionTests::NotCF: - return !ccflags.CF; - case ConditionTests::NotZF: - return !ccflags.ZF; - case ConditionTests::NotCvZF: - return !(ccflags.CF | ccflags.ZF); - case ConditionTests::NotSF: - return !ccflags.SF; - case ConditionTests::NotPF: - return !ccflags.PF; - case ConditionTests::NotSxOF: - return !(ccflags.SF ^ ccflags.OF); - case ConditionTests::NotSxOvZF: - return !(ccflags.SF ^ ccflags.OF | ccflags.ZF); - } - panic("Unknown condition: %d\n", ext); - return true; - } - std::string RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const { diff --git a/src/arch/x86/insts/microregop.hh b/src/arch/x86/insts/microregop.hh index f6bebb763..d805adb33 100644 --- a/src/arch/x86/insts/microregop.hh +++ b/src/arch/x86/insts/microregop.hh @@ -62,47 +62,6 @@ namespace X86ISA { - namespace ConditionTests - { - enum CondTest { - True, - NotFalse = True, - ECF, - EZF, - SZnZF, - MSTRZ, - STRZ, - MSTRC, - STRZnEZF, - OF, - CF, - ZF, - CvZF, - SF, - PF, - SxOF, - SxOvZF, - - False, - NotTrue = False, - NotECF, - NotEZF, - NotSZnZF, - NotMSTRZ, - NotSTRZ, - NotMSTRC, - STRnZnEZF, - NotOF, - NotCF, - NotZF, - NotCvZF, - NotSF, - NotPF, - NotSxOF, - NotSxOvZF - }; - } - /** * Base classes for RegOps which provides a generateDisassembly method. */ @@ -136,7 +95,6 @@ namespace X86ISA uint64_t genFlags(uint64_t oldFlags, uint64_t flagMask, uint64_t _dest, uint64_t _src1, uint64_t _src2, bool subtract = false) const; - bool checkCondition(uint64_t flags) const; }; class RegOp : public RegOpBase diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc index 4f6ec5390..510295157 100644 --- a/src/arch/x86/insts/static_inst.cc +++ b/src/arch/x86/insts/static_inst.cc @@ -198,13 +198,18 @@ namespace X86ISA return; } fpindex -= NumMMXRegs; - if(fpindex < NumXMMRegs) { + if(fpindex < NumXMMRegs * 2) { ccprintf(os, "%%xmm%d_%s", fpindex / 2, (fpindex % 2) ? "high": "low"); return; } - fpindex -= NumXMMRegs; - ccprintf(os, "%%ufp%d", fpindex); + fpindex -= NumXMMRegs * 2; + if(fpindex < NumMicroFpRegs) { + ccprintf(os, "%%ufp%d", fpindex); + return; + } + fpindex -= NumMicroFpRegs; + ccprintf(os, "%%st(%d)", fpindex); } else { switch (reg - Ctrl_Base_DepTag) { default: diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh index 3f33b8d85..cf9109e22 100644 --- a/src/arch/x86/interrupts.hh +++ b/src/arch/x86/interrupts.hh @@ -58,10 +58,73 @@ #ifndef __ARCH_X86_INTERRUPTS_HH__ #define __ARCH_X86_INTERRUPTS_HH__ -#error X86 is not yet supported! +#include "arch/x86/faults.hh" +#include "cpu/thread_context.hh" namespace X86ISA { + +class Interrupts +{ + public: + Interrupts() + { + clear_all(); + } + + int InterruptLevel(uint64_t softint) + { + panic("Interrupts::InterruptLevel unimplemented!\n"); + return 0; + } + + void post(int int_num, int index) + { + panic("Interrupts::post unimplemented!\n"); + } + + void clear(int int_num, int index) + { + warn("Interrupts::clear unimplemented!\n"); + } + + void clear_all() + { + warn("Interrupts::clear_all unimplemented!\n"); + } + + bool check_interrupts(ThreadContext * tc) const + { + return false; + } + + Fault getInterrupt(ThreadContext * tc) + { + return NoFault; + } + + void updateIntrInfo(ThreadContext * tc) + { + panic("Interrupts::updateIntrInfo unimplemented!\n"); + } + + uint64_t get_vec(int int_num) + { + panic("Interrupts::get_vec unimplemented!\n"); + return 0; + } + + void serialize(std::ostream & os) + { + panic("Interrupts::serialize unimplemented!\n"); + } + + void unserialize(Checkpoint * cp, const std::string & section) + { + panic("Interrupts::unserialize unimplemented!\n"); + } +}; + }; #endif // __ARCH_X86_INTERRUPTS_HH__ diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index ecb92947f..62b8c8d59 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -59,15 +59,15 @@ // 0x1: decode OPCODE_OP_TOP5 { - format WarnUnimpl { + format Inst { 0x00: decode OPCODE_OP_BOTTOM3 { 0x6: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: push_ES(); + 0x0: UD2(); + default: WarnUnimpl::push_ES(); } 0x7: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: pop_ES(); + 0x0: UD2(); + default: WarnUnimpl::pop_ES(); } default: MultiInst::ADD(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], @@ -76,8 +76,8 @@ } 0x01: decode OPCODE_OP_BOTTOM3 { 0x6: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: push_CS(); + 0x0: UD2(); + default: WarnUnimpl::push_CS(); } //Any time this is seen, it should generate a two byte opcode 0x7: M5InternalError::error( @@ -89,12 +89,12 @@ } 0x02: decode OPCODE_OP_BOTTOM3 { 0x6: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: push_SS(); + 0x0: UD2(); + default: WarnUnimpl::push_SS(); } 0x7: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: pop_SS(); + 0x0: UD2(); + default: WarnUnimpl::pop_SS(); } default: MultiInst::ADC(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], @@ -103,12 +103,12 @@ } 0x03: decode OPCODE_OP_BOTTOM3 { 0x6: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: push_DS(); + 0x0: UD2(); + default: WarnUnimpl::push_DS(); } 0x7: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: pop_DS(); + 0x0: UD2(); + default: WarnUnimpl::pop_DS(); } default: MultiInst::SBB(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], @@ -119,8 +119,8 @@ 0x6: M5InternalError::error( {{"Tried to execute the ES segment override prefix!"}}); 0x7: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: daa(); + 0x0: UD2(); + default: WarnUnimpl::daa(); } default: MultiInst::AND(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], @@ -130,7 +130,10 @@ 0x05: decode OPCODE_OP_BOTTOM3 { 0x6: M5InternalError::error( {{"Tried to execute the CS segment override prefix!"}}); - 0x7: das(); + 0x7: decode MODE_SUBMODE { + 0x0: UD2(); + default: WarnUnimpl::das(); + } default: MultiInst::SUB(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], [Gb,Eb], [Gv,Ev], @@ -140,8 +143,8 @@ 0x6: M5InternalError::error( {{"Tried to execute the SS segment override prefix!"}}); 0x7: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: aaa(); + 0x0: UD2(); + default: WarnUnimpl::aaa(); } default: MultiInst::XOR(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], @@ -152,47 +155,45 @@ 0x6: M5InternalError::error( {{"Tried to execute the DS segment override prefix!"}}); 0x7: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: aas(); + 0x0: UD2(); + default: WarnUnimpl::aas(); } default: MultiInst::CMP(OPCODE_OP_BOTTOM3, [Eb,Gb], [Ev,Gv], [Gb,Eb], [Gv,Ev], [rAb,Ib], [rAv,Iz]); } - format Inst { - 0x08: decode MODE_SUBMODE { - 0x0: M5InternalError::error ( - {{"Tried to execute an REX prefix!"}}); - default: INC(Bv); - } - 0x09: decode MODE_SUBMODE { - 0x0: M5InternalError::error ( - {{"Tried to execute an REX prefix!"}}); - default: DEC(Bv); - } - 0x0A: PUSH(Bv); - 0x0B: POP(Bv); + 0x08: decode MODE_SUBMODE { + 0x0: M5InternalError::error ( + {{"Tried to execute an REX prefix!"}}); + default: INC(Bv); + } + 0x09: decode MODE_SUBMODE { + 0x0: M5InternalError::error ( + {{"Tried to execute an REX prefix!"}}); + default: DEC(Bv); } + 0x0A: PUSH(Bv); + 0x0B: POP(Bv); 0x0C: decode OPCODE_OP_BOTTOM3 { 0x0: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: Inst::PUSHA(); + 0x0: UD2(); + default: PUSHA(); } 0x1: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: Inst::POPA(); + 0x0: UD2(); + default: POPA(); } 0x2: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: bound_Gv_Ma(); + 0x0: UD2(); + default: BOUND(Gv,Mv); } 0x3: decode MODE_SUBMODE { //The second operand should really be of size "d", but it's //set to "v" in order to have a consistent register size. //This shouldn't affect behavior. - 0x0: Inst::MOVSXD(Gv,Ev); - default: arpl_Ew_Gw(); + 0x0: MOVSXD(Gv,Ev); + default: WarnUnimpl::arpl_Ew_Gw(); } 0x4: M5InternalError::error( {{"Tried to execute the FS segment override prefix!"}}); @@ -204,41 +205,62 @@ {{"Tried to execute the DS address size override prefix!"}}); } 0x0D: decode OPCODE_OP_BOTTOM3 { - 0x0: Inst::PUSH(Iz); - 0x1: Inst::IMUL(Gv,Ev,Iz); - 0x2: Inst::PUSH(Ib); - 0x3: Inst::IMUL(Gv,Ev,Ib); - 0x4: ins_Yb_Dx(); - 0x5: ins_Yz_Dx(); - 0x6: outs_Dx_Xb(); - 0x7: outs_Dx_Xz(); + 0x0: PUSH(Iz); + 0x1: IMUL(Gv,Ev,Iz); + 0x2: PUSH(Ib); + 0x3: IMUL(Gv,Ev,Ib); + 0x4: StringInst::INS(Yb,rD); + 0x5: StringInst::INS(Yz,rD); + 0x6: StringInst::OUTS(rD,Xb); + 0x7: StringInst::OUTS(rD,Xz); } - format Inst { - 0x0E: decode OPCODE_OP_BOTTOM3 { - 0x0: JO(Jb); - 0x1: JNO(Jb); - 0x2: JB(Jb); - 0x3: JNB(Jb); - 0x4: JZ(Jb); - 0x5: JNZ(Jb); - 0x6: JBE(Jb); - 0x7: JNBE(Jb); - } - 0x0F: decode OPCODE_OP_BOTTOM3 { - 0x0: JS(Jb); - 0x1: JNS(Jb); - 0x2: JP(Jb); - 0x3: JNP(Jb); - 0x4: JL(Jb); - 0x5: JNL(Jb); - 0x6: JLE(Jb); - 0x7: JNLE(Jb); - } + 0x0E: decode OPCODE_OP_BOTTOM3 { + 0x0: JO(Jb); + 0x1: JNO(Jb); + 0x2: JB(Jb); + 0x3: JNB(Jb); + 0x4: JZ(Jb); + 0x5: JNZ(Jb); + 0x6: JBE(Jb); + 0x7: JNBE(Jb); + } + 0x0F: decode OPCODE_OP_BOTTOM3 { + 0x0: JS(Jb); + 0x1: JNS(Jb); + 0x2: JP(Jb); + 0x3: JNP(Jb); + 0x4: JL(Jb); + 0x5: JNL(Jb); + 0x6: JLE(Jb); + 0x7: JNLE(Jb); } - format Inst { - 0x10: decode OPCODE_OP_BOTTOM3 { - //0x0: group1_Eb_Ib(); - 0x0: decode MODRM_REG { + 0x10: decode OPCODE_OP_BOTTOM3 { + //0x0: group1_Eb_Ib(); + 0x0: decode MODRM_REG { + 0x0: ADD(Eb,Ib); + 0x1: OR(Eb,Ib); + 0x2: ADC(Eb,Ib); + 0x3: SBB(Eb,Ib); + 0x4: AND(Eb,Ib); + 0x5: SUB(Eb,Ib); + 0x6: XOR(Eb,Ib); + 0x7: CMP(Eb,Ib); + } + //0x1: group1_Ev_Iz(); + 0x1: decode MODRM_REG { + 0x0: ADD(Ev,Iz); + 0x1: OR(Ev,Iz); + 0x2: ADC(Ev,Iz); + 0x3: SBB(Ev,Iz); + 0x4: AND(Ev,Iz); + 0x5: SUB(Ev,Iz); + 0x6: XOR(Ev,Iz); + 0x7: CMP(Ev,Iz); + } + 0x2: decode MODE_SUBMODE { + 0x0: UD2(); + //default: group1_Eb_Ib(); + default: decode MODRM_REG { 0x0: ADD(Eb,Ib); 0x1: OR(Eb,Ib); 0x2: ADC(Eb,Ib); @@ -248,313 +270,290 @@ 0x6: XOR(Eb,Ib); 0x7: CMP(Eb,Ib); } - //0x1: group1_Ev_Iz(); - 0x1: decode MODRM_REG { - 0x0: ADD(Ev,Iz); - 0x1: OR(Ev,Iz); - 0x2: ADC(Ev,Iz); - 0x3: SBB(Ev,Iz); - 0x4: AND(Ev,Iz); - 0x5: SUB(Ev,Iz); - 0x6: XOR(Ev,Iz); - 0x7: CMP(Ev,Iz); - } - 0x2: decode MODE_SUBMODE { - 0x0: UD2(); - //default: group1_Eb_Ib(); - default: decode MODRM_REG { - 0x0: ADD(Eb,Ib); - 0x1: OR(Eb,Ib); - 0x2: ADC(Eb,Ib); - 0x3: SBB(Eb,Ib); - 0x4: AND(Eb,Ib); - 0x5: SUB(Eb,Ib); - 0x6: XOR(Eb,Ib); - 0x7: CMP(Eb,Ib); - } - } - //0x3: group1_Ev_Ib(); - 0x3: decode MODRM_REG { - 0x0: ADD(Ev,Ib); - 0x1: OR(Ev,Ib); - 0x2: ADC(Ev,Ib); - 0x3: SBB(Ev,Ib); - 0x4: AND(Ev,Ib); - 0x5: SUB(Ev,Ib); - 0x6: XOR(Ev,Ib); - 0x7: CMP(Ev,Ib); - } - 0x4: TEST(Eb,Gb); - 0x5: TEST(Ev,Gv); - 0x6: XCHG(Eb,Gb); - 0x7: XCHG(Ev,Gv); } + //0x3: group1_Ev_Ib(); + 0x3: decode MODRM_REG { + 0x0: ADD(Ev,Ib); + 0x1: OR(Ev,Ib); + 0x2: ADC(Ev,Ib); + 0x3: SBB(Ev,Ib); + 0x4: AND(Ev,Ib); + 0x5: SUB(Ev,Ib); + 0x6: XOR(Ev,Ib); + 0x7: CMP(Ev,Ib); + } + 0x4: TEST(Eb,Gb); + 0x5: TEST(Ev,Gv); + 0x6: XCHG(Eb,Gb); + 0x7: XCHG(Ev,Gv); } 0x11: decode OPCODE_OP_BOTTOM3 { - 0x0: Inst::MOV(Eb,Gb); - 0x1: Inst::MOV(Ev,Gv); - 0x2: Inst::MOV(Gb,Eb); - 0x3: Inst::MOV(Gv,Ev); - 0x4: mov_MwRv_Sw(); //What to do with this one? - 0x5: Inst::LEA(Gv,M); - 0x6: mov_Sw_MwRv(); - 0x7: group10_Ev(); //Make sure this is Ev + 0x0: MOV(Eb,Gb); + 0x1: MOV(Ev,Gv); + 0x2: MOV(Gb,Eb); + 0x3: MOV(Gv,Ev); + 0x4: WarnUnimpl::mov_MwRv_Sw(); //What to do with this one? + 0x5: LEA(Gv,M); + 0x6: WarnUnimpl::mov_Sw_MwRv(); + //0x7: group10_Ev(); + 0x7: decode MODRM_REG { + 0x0: POP(Ev); + default: UD2(); + } } 0x12: decode OPCODE_OP_BOTTOM3 { - 0x0: Inst::NOP(); //XXX repe makes this a "pause" - default: xchg_B_rAX(); + 0x0: NOP(); //XXX repe makes this a "pause" + default: XCHG(Bv,rAv); } 0x13: decode OPCODE_OP_BOTTOM3 { - 0x0: Inst::CDQE(rAv); - 0x1: Inst::CQO(rAv,rDv); + 0x0: CDQE(rAv); + 0x1: CQO(rAv,rDv); 0x2: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: call_far_Ap(); - } - 0x3: fwait(); //aka wait - 0x4: pushf_Fv(); - 0x5: popf_Fv(); - //Both of these should be illegal only if CPUID.AHF64=0, - //according to sandpile.org + 0x0: UD2(); + default: WarnUnimpl::call_far_Ap(); + } + 0x3: WarnUnimpl::fwait(); //aka wait + 0x4: PUSHF(); + 0x5: POPF(); + //The 64 bit versions of both of these should be illegal only + //if CPUID says it isn't supported. For now, we'll just assume + //that it's supported. 0x6: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: sahf(); + 0x0: SAHF_64(); + default: SAHF(); } 0x7: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: lahf(); + 0x0: LAHF_64(); + default: LAHF(); } } 0x14: decode OPCODE_OP_BOTTOM3 { - 0x0: mov_Al_Ob(); - 0x1: mov_rAX_Ov(); - 0x2: mov_Ob_Al(); - 0x3: mov_Ov_rAX(); - 0x4: movs_Yb_Xb(); - 0x5: movs_Yv_Xv(); - 0x6: StringInst::CMPS(Yb,Xb); - 0x7: StringInst::CMPS(Yv,Xv); + 0x0: MOV(rAb, Ob); + 0x1: MOV(rAv, Ov); + 0x2: MOV(Ob, rAb); + 0x3: MOV(Ov, rAv); + 0x4: StringInst::MOVS(Yb,Xb); + 0x5: StringInst::MOVS(Yv,Xv); + 0x6: StringTestInst::CMPS(Yb,Xb); + 0x7: StringTestInst::CMPS(Yv,Xv); } 0x15: decode OPCODE_OP_BOTTOM3 { - 0x0: Inst::TEST(rAb,Ib); - 0x1: Inst::TEST(rAv,Iz); - 0x2: stos_Yb_Al(); - 0x3: stos_Yv_rAX(); - 0x4: lods_Al_Xb(); - 0x5: lods_rAX_Xv(); - 0x6: StringInst::SCAS(Yb); - 0x7: StringInst::SCAS(Yv); + 0x0: TEST(rAb,Ib); + 0x1: TEST(rAv,Iz); + 0x2: StringInst::STOS(Yb); + 0x3: StringInst::STOS(Yv); + 0x4: StringInst::LODS(Xb); + 0x5: StringInst::LODS(Xv); + 0x6: StringTestInst::SCAS(Yb); + 0x7: StringTestInst::SCAS(Yv); } - format Inst { - 0x16: MOV(Bb,Ib); - 0x17: MOV(Bv,Iv); - 0x18: decode OPCODE_OP_BOTTOM3 { - //0x0: group2_Eb_Ib(); - 0x0: decode MODRM_REG { - 0x0: ROL(Eb,Ib); - 0x1: ROR(Eb,Ib); - 0x2: RCL(Eb,Ib); - 0x3: RCR(Eb,Ib); - 0x4: SAL(Eb,Ib); - 0x5: SHR(Eb,Ib); - 0x6: SAL(Eb,Ib); - 0x7: SAR(Eb,Ib); - } - //0x1: group2_Ev_Ib(); - 0x1: decode MODRM_REG { - 0x0: ROL(Ev,Ib); - 0x1: ROR(Ev,Ib); - 0x2: RCL(Ev,Ib); - 0x3: RCR(Ev,Ib); - 0x4: SAL(Ev,Ib); - 0x5: SHR(Ev,Ib); - 0x6: SAL(Ev,Ib); - 0x7: SAR(Ev,Ib); - } - 0x2: RET_NEAR(Iw); - 0x3: RET_NEAR(); - 0x4: decode MODE_SUBMODE { - 0x0: UD2(); - default: WarnUnimpl::les_Gz_Mp(); - } - 0x5: decode MODE_SUBMODE { - 0x0: UD2(); - default: WarnUnimpl::lds_Gz_Mp(); - } - //0x6: group12_Eb_Ib(); - 0x6: decode MODRM_REG { - 0x0: MOV(Eb,Ib); - default: UD2(); - } - //0x7: group12_Ev_Iz(); - 0x7: decode MODRM_REG { - 0x0: MOV(Ev,Iz); - default: UD2(); - } + 0x16: MOV(Bb,Ib); + 0x17: MOV(Bv,Iv); + 0x18: decode OPCODE_OP_BOTTOM3 { + //0x0: group2_Eb_Ib(); + 0x0: decode MODRM_REG { + 0x0: ROL(Eb,Ib); + 0x1: ROR(Eb,Ib); + 0x2: RCL(Eb,Ib); + 0x3: RCR(Eb,Ib); + 0x4: SAL(Eb,Ib); + 0x5: SHR(Eb,Ib); + 0x6: SAL(Eb,Ib); + 0x7: SAR(Eb,Ib); + } + //0x1: group2_Ev_Ib(); + 0x1: decode MODRM_REG { + 0x0: ROL(Ev,Ib); + 0x1: ROR(Ev,Ib); + 0x2: RCL(Ev,Ib); + 0x3: RCR(Ev,Ib); + 0x4: SAL(Ev,Ib); + 0x5: SHR(Ev,Ib); + 0x6: SAL(Ev,Ib); + 0x7: SAR(Ev,Ib); + } + 0x2: RET_NEAR(Iw); + 0x3: RET_NEAR(); + 0x4: decode MODE_SUBMODE { + 0x0: UD2(); + default: WarnUnimpl::les_Gz_Mp(); + } + 0x5: decode MODE_SUBMODE { + 0x0: UD2(); + default: WarnUnimpl::lds_Gz_Mp(); + } + //0x6: group12_Eb_Ib(); + 0x6: decode MODRM_REG { + 0x0: MOV(Eb,Ib); + default: UD2(); + } + //0x7: group12_Ev_Iz(); + 0x7: decode MODRM_REG { + 0x0: MOV(Ev,Iz); + default: UD2(); } } - 0x19: decode OPCODE_OP_BOTTOM3 { - 0x0: enter_Iw_Ib(); - 0x1: Inst::LEAVE(); - 0x2: ret_far_Iw(); - 0x3: ret_far(); - 0x4: int3(); - 0x5: int_Ib(); - 0x6: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: into(); + format WarnUnimpl { + 0x19: decode OPCODE_OP_BOTTOM3 { + // The second parameter here should be of size b, but + // immediate sizes are determined elsewhere and this would + // confuse the instruction type specialization code. + 0x0: Inst::ENTER(Iw,Iw); + 0x1: Inst::LEAVE(); + 0x2: ret_far_Iw(); + 0x3: ret_far(); + 0x4: int3(); + 0x5: int_Ib(); + 0x6: decode MODE_SUBMODE { + 0x0: Inst::UD2(); + default: into(); + } + 0x7: iret(); } - 0x7: iret(); } 0x1A: decode OPCODE_OP_BOTTOM3 { - format Inst { - //0x0: group2_Eb_1(); - 0x0: decode MODRM_REG { - 0x0: ROL_1(Eb); - 0x1: ROR_1(Eb); - 0x2: RCL_1(Eb); - 0x3: RCR_1(Eb); - 0x4: SAL_1(Eb); - 0x5: SHR_1(Eb); - 0x6: SAL_1(Eb); - 0x7: SAR_1(Eb); - } - //0x1: group2_Ev_1(); - 0x1: decode MODRM_REG { - 0x0: ROL_1(Ev); - 0x1: ROR_1(Ev); - 0x2: RCL_1(Ev); - 0x3: RCR_1(Ev); - 0x4: SAL_1(Ev); - 0x5: SHR_1(Ev); - 0x6: SAL_1(Ev); - 0x7: SAR_1(Ev); - } - //0x2: group2_Eb_Cl(); - 0x2: decode MODRM_REG { - 0x0: ROL(Eb,rCb); - 0x1: ROR(Eb,rCb); - 0x2: RCL(Eb,rCb); - 0x3: RCR(Eb,rCb); - 0x4: SAL(Eb,rCb); - 0x5: SHR(Eb,rCb); - 0x6: SAL(Eb,rCb); - 0x7: SAR(Eb,rCb); - } - //The second operand should have size "b", but to have - //consistent register sizes it's "v". This shouldn't have - //any affect on functionality. - //0x3: group2_Ev_Cl(); - 0x3: decode MODRM_REG { - 0x0: ROL(Ev,rCv); - 0x1: ROR(Ev,rCv); - 0x2: RCL(Ev,rCv); - 0x3: RCR(Ev,rCv); - 0x4: SAL(Ev,rCv); - 0x5: SHR(Ev,rCv); - 0x6: SAL(Ev,rCv); - 0x7: SAR(Ev,rCv); - } + //0x0: group2_Eb_1(); + 0x0: decode MODRM_REG { + 0x0: ROL_1(Eb); + 0x1: ROR_1(Eb); + 0x2: RCL_1(Eb); + 0x3: RCR_1(Eb); + 0x4: SAL_1(Eb); + 0x5: SHR_1(Eb); + 0x6: SAL_1(Eb); + 0x7: SAR_1(Eb); + } + //0x1: group2_Ev_1(); + 0x1: decode MODRM_REG { + 0x0: ROL_1(Ev); + 0x1: ROR_1(Ev); + 0x2: RCL_1(Ev); + 0x3: RCR_1(Ev); + 0x4: SAL_1(Ev); + 0x5: SHR_1(Ev); + 0x6: SAL_1(Ev); + 0x7: SAR_1(Ev); + } + //0x2: group2_Eb_Cl(); + 0x2: decode MODRM_REG { + 0x0: ROL(Eb,rCb); + 0x1: ROR(Eb,rCb); + 0x2: RCL(Eb,rCb); + 0x3: RCR(Eb,rCb); + 0x4: SAL(Eb,rCb); + 0x5: SHR(Eb,rCb); + 0x6: SAL(Eb,rCb); + 0x7: SAR(Eb,rCb); + } + //The second operand should have size "b", but to have + //consistent register sizes it's "v". This shouldn't have + //any affect on functionality. + //0x3: group2_Ev_Cl(); + 0x3: decode MODRM_REG { + 0x0: ROL(Ev,rCv); + 0x1: ROR(Ev,rCv); + 0x2: RCL(Ev,rCv); + 0x3: RCR(Ev,rCv); + 0x4: SAL(Ev,rCv); + 0x5: SHR(Ev,rCv); + 0x6: SAL(Ev,rCv); + 0x7: SAR(Ev,rCv); } 0x4: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: aam_Ib(); + 0x0: UD2(); + default: WarnUnimpl::aam_Ib(); } 0x5: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: aad_Ib(); + 0x0: UD2(); + default: WarnUnimpl::aad_Ib(); } 0x6: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: salc(); + 0x0: UD2(); + default: SALC(rAb); } - 0x7: xlat(); + 0x7: XLAT(); } ##include "x87.isa" 0x1C: decode OPCODE_OP_BOTTOM3 { - 0x0: loopne_Jb(); - 0x1: loope_Jb(); - 0x2: loop_Jb(); - 0x3: jcxz_or_jecx_or_jrcx(); - 0x4: in_Al_Ib(); - 0x5: in_eAX_Ib(); - 0x6: out_Ib_Al(); - 0x7: out_Ib_eAX(); + 0x0: LOOPNE(Jb); + 0x1: LOOPE(Jb); + 0x2: LOOP(Jb); + 0x3: JRCX(Jb); + 0x4: IN(rAb,Ib); + 0x5: IN(rAv,Iv); + 0x6: OUT(Ib,rAb); + 0x7: OUT(Iv,rAv); } 0x1D: decode OPCODE_OP_BOTTOM3 { - 0x0: Inst::CALL_NEAR(Jz); - 0x1: Inst::JMP(Jz); + 0x0: CALL_NEAR(Jz); + 0x1: JMP(Jz); 0x2: decode MODE_SUBMODE { - 0x0: Inst::UD2(); - default: jmp_far_Ap(); - } - 0x3: Inst::JMP(Jb); - 0x4: in_Al_Dx(); - 0x5: in_eAX_Dx(); - 0x6: out_Dx_Al(); - 0x7: out_Dx_eAX(); + 0x0: UD2(); + default: WarnUnimpl::jmp_far_Ap(); + } + 0x3: JMP(Jb); + 0x4: IN(rAb,rD); + 0x5: IN(rAv,rD); + 0x6: OUT(rD,rAb); + 0x7: OUT(rD,rAv); } 0x1E: decode OPCODE_OP_BOTTOM3 { 0x0: M5InternalError::error( {{"Tried to execute the lock prefix!"}}); - 0x1: int1(); + 0x1: WarnUnimpl::int1(); 0x2: M5InternalError::error( {{"Tried to execute the repne prefix!"}}); 0x3: M5InternalError::error( {{"Tried to execute the rep/repe prefix!"}}); - 0x4: hlt(); - 0x5: cmc(); - format Inst { - //0x6: group3_Eb(); - 0x6: decode MODRM_REG { - 0x0: TEST(Eb,Iz); - 0x1: TEST(Eb,Iz); - 0x2: NOT(Eb); - 0x3: NEG(Eb); - 0x4: MUL_B(Eb); - 0x5: IMUL_B(Eb); - //This should be Eb, but it access the entire word value ax. - 0x6: DIV_B(Ew); - 0x7: IDIV(Eb); - } - //0x7: group3_Ev(); - 0x7: decode MODRM_REG { - 0x0: TEST(Ev,Iz); - 0x1: TEST(Ev,Iz); - 0x2: NOT(Ev); - 0x3: NEG(Ev); - 0x4: MUL(Ev); - 0x5: IMUL(Ev); - 0x6: DIV(Ev); - 0x7: IDIV(Ev); - } + 0x4: HLT(); + 0x5: CMC(); + //0x6: group3_Eb(); + 0x6: decode MODRM_REG { + 0x0: TEST(Eb,Iz); + 0x1: TEST(Eb,Iz); + 0x2: NOT(Eb); + 0x3: NEG(Eb); + 0x4: MUL_B(Eb); + 0x5: IMUL_B(Eb); + //This should be Eb, but it access the entire word value ax. + 0x6: DIV_B(Ew); + 0x7: IDIV(Eb); + } + //0x7: group3_Ev(); + 0x7: decode MODRM_REG { + 0x0: TEST(Ev,Iz); + 0x1: TEST(Ev,Iz); + 0x2: NOT(Ev); + 0x3: NEG(Ev); + 0x4: MUL(Ev); + 0x5: IMUL(Ev); + 0x6: DIV(Ev); + 0x7: IDIV(Ev); } } 0x1F: decode OPCODE_OP_BOTTOM3 { - format Inst { - 0x0: CLC(); - 0x1: STC(); - 0x2: WarnUnimpl::cli(); - 0x3: WarnUnimpl::sti(); - 0x4: CLD(); - 0x5: STD(); - //0x6: group4(); - 0x6: decode MODRM_REG { - 0x0: INC(Eb); - 0x1: DEC(Eb); - default: UD2(); - } - //0x7: group5(); - 0x7: decode MODRM_REG { - 0x0: INC(Ev); - 0x1: DEC(Ev); - 0x2: CALL_NEAR(Ev); - 0x3: WarnUnimpl::call_far_Mp(); - 0x4: JMP(Ev); - 0x5: WarnUnimpl::jmp_far_Mp(); - 0x6: PUSH(Ev); - 0x7: UD2(); - } + 0x0: CLC(); + 0x1: STC(); + 0x2: WarnUnimpl::cli(); + 0x3: WarnUnimpl::sti(); + 0x4: CLD(); + 0x5: STD(); + //0x6: group4(); + 0x6: decode MODRM_REG { + 0x0: INC(Eb); + 0x1: DEC(Eb); + default: UD2(); + } + //0x7: group5(); + 0x7: decode MODRM_REG { + 0x0: INC(Ev); + 0x1: DEC(Ev); + 0x2: CALL_NEAR(Ev); + 0x3: WarnUnimpl::call_far_Mp(); + 0x4: JMP(Ev); + 0x5: WarnUnimpl::jmp_far_Mp(); + 0x6: PUSH(Ev); + 0x7: UD2(); } } } diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index eae994706..0482fdf23 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -211,9 +211,9 @@ default: Inst::UD2(); } 0x06: decode OPCODE_OP_BOTTOM3 { - 0x0: wrmsr(); + 0x0: Inst::WRMSR(); 0x1: rdtsc(); - 0x2: rdmsr(); + 0x2: Inst::RDMSR(); 0x3: rdpmc(); 0x4: sysenter(); 0x5: sysexit(); diff --git a/src/arch/x86/isa/decoder/x87.isa b/src/arch/x86/isa/decoder/x87.isa index bab687acd..9a6473141 100644 --- a/src/arch/x86/isa/decoder/x87.isa +++ b/src/arch/x86/isa/decoder/x87.isa @@ -53,294 +53,296 @@ // // Authors: Gabe Black -0x1B: decode OPCODE_OP_BOTTOM3 { - //0x0: esc0(); - 0x0: decode MODRM_REG { - 0x0: fadd(); - 0x1: fmul(); - 0x2: fcom(); - 0x3: fcomp(); - 0x4: fsub(); - 0x5: fsubr(); - 0x6: fdiv(); - 0x7: fdivr(); - } - //0x1: esc1(); - 0x1: decode MODRM_REG { - 0x0: fld(); - 0x1: decode MODRM_MOD { - 0x3: fxch(); - default: Inst::UD2(); - } - 0x2: decode MODRM_MOD { - 0x3: decode MODRM_RM { - 0x0: fnop(); +format WarnUnimpl { + 0x1B: decode OPCODE_OP_BOTTOM3 { + //0x0: esc0(); + 0x0: decode MODRM_REG { + 0x0: fadd(); + 0x1: fmul(); + 0x2: fcom(); + 0x3: fcomp(); + 0x4: fsub(); + 0x5: fsubr(); + 0x6: fdiv(); + 0x7: fdivr(); + } + //0x1: esc1(); + 0x1: decode MODRM_REG { + 0x0: fld(); + 0x1: decode MODRM_MOD { + 0x3: fxch(); default: Inst::UD2(); } - default: fst(); - } - 0x3: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: fstp(); - } - 0x4: decode MODRM_MOD { - 0x3: decode MODRM_RM { - 0x0: fchs(); - 0x1: fabs(); - 0x4: ftst(); - 0x5: fxam(); - default: Inst::UD2(); + 0x2: decode MODRM_MOD { + 0x3: decode MODRM_RM { + 0x0: fnop(); + default: Inst::UD2(); + } + default: fst(); } - default: fldenv(); - } - 0x5: decode MODRM_MOD { - 0x3: decode MODRM_RM { - 0x0: fld1(); - 0x1: fldl2t(); - 0x2: fldl2e(); - 0x3: fldpi(); - 0x4: fldlg2(); - 0x5: fldln2(); - 0x6: fldz(); - } - default: fldcw_Mw(); - } - 0x6: decode MODRM_MOD { - 0x3: decode MODRM_RM { - 0x0: f2xm1(); - 0x1: fyl2x(); - 0x2: fptan(); - 0x3: fpatan(); - 0x4: fxtract(); - 0x5: fprem1(); - 0x6: fdecstp(); - 0x7: fincstp(); - } - default: fnstenv(); - } - 0x7: decode MODRM_MOD { - 0x3: decode MODRM_RM { - 0x0: fprem(); - 0x1: fyl2xp1(); - 0x2: fsqrt(); - 0x3: fsincos(); - 0x4: frndint(); - 0x5: fscale(); - 0x6: fsin(); - 0x7: fcos(); - } - default: fnstcw_Mw(); - } - } - //0x2: esc2(); - 0x2: decode MODRM_REG { - 0x0: decode MODRM_MOD { - 0x3: fcmovb(); - default: fiadd(); - } - 0x1: decode MODRM_MOD { - 0x3: fcmove(); - default: fimul(); - } - 0x2: decode MODRM_MOD { - 0x3: fcmovbe(); - default: ficom(); - } - 0x3: decode MODRM_MOD { - 0x3: fcmovu(); - default: ficomp(); - } - 0x4: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: fisub(); - } - 0x5: decode MODRM_MOD { - 0x3: decode MODRM_RM { - 0x1: fucompp(); - default: Inst::UD2(); + 0x3: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: fstp(); + } + 0x4: decode MODRM_MOD { + 0x3: decode MODRM_RM { + 0x0: fchs(); + 0x1: fabs(); + 0x4: ftst(); + 0x5: fxam(); + default: Inst::UD2(); + } + default: fldenv(); + } + 0x5: decode MODRM_MOD { + 0x3: decode MODRM_RM { + 0x0: fld1(); + 0x1: fldl2t(); + 0x2: fldl2e(); + 0x3: fldpi(); + 0x4: fldlg2(); + 0x5: fldln2(); + 0x6: fldz(); + } + default: fldcw_Mw(); + } + 0x6: decode MODRM_MOD { + 0x3: decode MODRM_RM { + 0x0: f2xm1(); + 0x1: fyl2x(); + 0x2: fptan(); + 0x3: fpatan(); + 0x4: fxtract(); + 0x5: fprem1(); + 0x6: fdecstp(); + 0x7: fincstp(); + } + default: fnstenv(); + } + 0x7: decode MODRM_MOD { + 0x3: decode MODRM_RM { + 0x0: fprem(); + 0x1: fyl2xp1(); + 0x2: fsqrt(); + 0x3: fsincos(); + 0x4: frndint(); + 0x5: fscale(); + 0x6: fsin(); + 0x7: fcos(); + } + default: fnstcw_Mw(); } - default: fisubr(); - } - 0x6: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: fidiv(); - } - 0x7: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: fidivr(); - } - } - //0x3: esc3(); - 0x3: decode MODRM_REG { - 0x0: decode MODRM_MOD { - 0x3: fcmovnb(); - default: fild(); - } - 0x1: decode MODRM_MOD { - 0x3: fcmovne(); - default: fisttp(); - } - 0x2: decode MODRM_MOD { - 0x3: fcmovnbe(); - default: fist(); } - 0x3: decode MODRM_MOD { - 0x3: fcmovnu(); - default: fistp(); + //0x2: esc2(); + 0x2: decode MODRM_REG { + 0x0: decode MODRM_MOD { + 0x3: fcmovb(); + default: fiadd(); + } + 0x1: decode MODRM_MOD { + 0x3: fcmove(); + default: fimul(); + } + 0x2: decode MODRM_MOD { + 0x3: fcmovbe(); + default: ficom(); + } + 0x3: decode MODRM_MOD { + 0x3: fcmovu(); + default: ficomp(); + } + 0x4: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: fisub(); + } + 0x5: decode MODRM_MOD { + 0x3: decode MODRM_RM { + 0x1: fucompp(); + default: Inst::UD2(); + } + default: fisubr(); + } + 0x6: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: fidiv(); + } + 0x7: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: fidivr(); + } } - 0x4: decode MODRM_MOD { - 0x3: decode MODRM_RM { - 0x2: fnclex(); - 0x3: fninit(); + //0x3: esc3(); + 0x3: decode MODRM_REG { + 0x0: decode MODRM_MOD { + 0x3: fcmovnb(); + default: fild(); + } + 0x1: decode MODRM_MOD { + 0x3: fcmovne(); + default: fisttp(); + } + 0x2: decode MODRM_MOD { + 0x3: fcmovnbe(); + default: fist(); + } + 0x3: decode MODRM_MOD { + 0x3: fcmovnu(); + default: fistp(); + } + 0x4: decode MODRM_MOD { + 0x3: decode MODRM_RM { + 0x2: fnclex(); + 0x3: fninit(); + default: Inst::UD2(); + } default: Inst::UD2(); } - default: Inst::UD2(); - } - 0x5: decode MODRM_MOD { - 0x3: fucomi(); - default: fld(); - } - 0x6: decode MODRM_MOD { - 0x3: fcomi(); - default: Inst::UD2(); - } - 0x7: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: fstp(); - } - } - //0x4: esc4(); - 0x4: decode MODRM_REG { - 0x0: fadd(); - 0x1: fmul(); - 0x2: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: fcom(); - } - 0x3: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: fcomp(); - } - 0x4: decode MODRM_MOD { - 0x3: fsubr(); - default: fsub(); - } - 0x5: decode MODRM_MOD { - 0x3: fsub(); - default: fsubr(); - } - 0x6: decode MODRM_MOD { - 0x3: fdivr(); - default: fdiv(); - } - 0x7: decode MODRM_MOD { - 0x3: fdiv(); - default: fdivr(); - } - } - //0x5: esc5(); - 0x5: decode MODRM_REG { - 0x0: decode MODRM_MOD { - 0x3: ffree(); - default: fld(); - } - 0x1: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: fisttp(); - } - 0x2: fst(); - 0x3: fstp(); - 0x4: decode MODRM_MOD { - 0x3: fucom(); - default: frstor(); - } - 0x5: decode MODRM_MOD { - 0x3: fucomp(); - default: Inst::UD2(); - } - 0x6: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: fnsave(); - } - 0x7: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: fnstsw(); - } - } - //0x6: esc6(); - 0x6: decode MODRM_REG { - 0x0: decode MODRM_MOD { - 0x3: faddp(); - default: fiadd(); - } - 0x1: decode MODRM_MOD { - 0x3: fmulp(); - default: fimul(); - } - 0x2: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: ficom(); - } - 0x3: decode MODRM_MOD { - 0x3: decode MODRM_RM { - 0x1: fcompp(); + 0x5: decode MODRM_MOD { + 0x3: fucomi(); + default: fld(); + } + 0x6: decode MODRM_MOD { + 0x3: fcomi(); default: Inst::UD2(); } - default: ficomp(); - } - 0x4: decode MODRM_MOD { - 0x3: fsubrp(); - default: fisub(); - } - 0x5: decode MODRM_MOD { - 0x3: fsubp(); - default: fisubr(); - } - 0x6: decode MODRM_MOD { - 0x3: fdivrp(); - default: fidiv(); - } - 0x7: decode MODRM_MOD { - 0x3: fdivp(); - default: fidivr(); - } - } - //0x7: esc7(); - 0x7: decode MODRM_REG { - 0x0: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: fild(); - } - 0x1: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: fisttp(); - } - 0x2: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: fist(); + 0x7: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: fstp(); + } } - 0x3: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: fistp(); + //0x4: esc4(); + 0x4: decode MODRM_REG { + 0x0: fadd(); + 0x1: fmul(); + 0x2: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: fcom(); + } + 0x3: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: fcomp(); + } + 0x4: decode MODRM_MOD { + 0x3: fsubr(); + default: fsub(); + } + 0x5: decode MODRM_MOD { + 0x3: fsub(); + default: fsubr(); + } + 0x6: decode MODRM_MOD { + 0x3: fdivr(); + default: fdiv(); + } + 0x7: decode MODRM_MOD { + 0x3: fdiv(); + default: fdivr(); + } } - 0x4: decode MODRM_MOD { - 0x3: decode MODRM_RM { - 0x0: fnstsw(); + //0x5: esc5(); + 0x5: decode MODRM_REG { + 0x0: decode MODRM_MOD { + 0x3: ffree(); + default: Inst::FLD(Mq); + } + 0x1: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: fisttp(); + } + 0x2: Inst::FST(Mq); + 0x3: Inst::FSTP(Mq); + 0x4: decode MODRM_MOD { + 0x3: fucom(); + default: frstor(); + } + 0x5: decode MODRM_MOD { + 0x3: fucomp(); default: Inst::UD2(); } - default: fbld(); - } - 0x5: decode MODRM_MOD { - 0x3: fucomip(); - default: fild(); + 0x6: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: fnsave(); + } + 0x7: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: fnstsw(); + } } - 0x6: decode MODRM_MOD { - 0x3: fcomip(); - default: fbstp(); + //0x6: esc6(); + 0x6: decode MODRM_REG { + 0x0: decode MODRM_MOD { + 0x3: faddp(); + default: fiadd(); + } + 0x1: decode MODRM_MOD { + 0x3: fmulp(); + default: fimul(); + } + 0x2: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: ficom(); + } + 0x3: decode MODRM_MOD { + 0x3: decode MODRM_RM { + 0x1: fcompp(); + default: Inst::UD2(); + } + default: ficomp(); + } + 0x4: decode MODRM_MOD { + 0x3: fsubrp(); + default: fisub(); + } + 0x5: decode MODRM_MOD { + 0x3: fsubp(); + default: fisubr(); + } + 0x6: decode MODRM_MOD { + 0x3: fdivrp(); + default: fidiv(); + } + 0x7: decode MODRM_MOD { + 0x3: fdivp(); + default: fidivr(); + } } - 0x7: decode MODRM_MOD { - 0x3: Inst::UD2(); - default: fistp(); + //0x7: esc7(); + 0x7: decode MODRM_REG { + 0x0: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: fild(); + } + 0x1: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: fisttp(); + } + 0x2: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: fist(); + } + 0x3: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: fistp(); + } + 0x4: decode MODRM_MOD { + 0x3: decode MODRM_RM { + 0x0: fnstsw(); + default: Inst::UD2(); + } + default: fbld(); + } + 0x5: decode MODRM_MOD { + 0x3: fucomip(); + default: fild(); + } + 0x6: decode MODRM_MOD { + 0x3: fcomip(); + default: fbstp(); + } + 0x7: decode MODRM_MOD { + 0x3: Inst::UD2(); + default: fistp(); + } } } } diff --git a/src/arch/x86/isa/formats/basic.isa b/src/arch/x86/isa/formats/basic.isa index ea224d638..7aea7085f 100644 --- a/src/arch/x86/isa/formats/basic.isa +++ b/src/arch/x86/isa/formats/basic.isa @@ -147,12 +147,3 @@ def template BasicDecode {{ def template BasicDecodeWithMnemonic {{ return new %(class_name)s("%(mnemonic)s", machInst); }}; - -// The most basic instruction format... used only for a few misc. insts -def format BasicOperate(code, *flags) {{ - iop = InstObjParams(name, Name, 'SparcStaticInst', code, flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) -}}; diff --git a/src/arch/x86/isa/formats/string.isa b/src/arch/x86/isa/formats/string.isa index cd182ff62..cb3ebc496 100644 --- a/src/arch/x86/isa/formats/string.isa +++ b/src/arch/x86/isa/formats/string.isa @@ -61,7 +61,7 @@ // ////////////////////////////////////////////////////////////////////////// -def format StringInst(*opTypeSet) {{ +def format StringTestInst(*opTypeSet) {{ allBlocks = OutputBlocks() regBlocks = specializeInst(Name, list(opTypeSet), EmulEnv()) @@ -86,3 +86,29 @@ def format StringInst(*opTypeSet) {{ (header_output, decoder_output, decode_block, exec_output) = allBlocks.makeList() }}; + +def format StringInst(*opTypeSet) {{ + allBlocks = OutputBlocks() + + regBlocks = specializeInst(Name, list(opTypeSet), EmulEnv()) + eBlocks = specializeInst(Name + "_E", list(opTypeSet), EmulEnv()) + + for blocks in (regBlocks, eBlocks): + allBlocks.header_output += blocks.header_output + allBlocks.decoder_output += blocks.decoder_output + allBlocks.exec_output += blocks.exec_output + + allBlocks.decode_block = ''' + if (LEGACY_REP) { + %s + } else if (LEGACY_REPNE) { + // The repne prefix is illegal + return new MicroFault(machInst, "illprefix", new InvalidOpcode, 0); + } else { + %s + } + ''' % (eBlocks.decode_block, regBlocks.decode_block) + + (header_output, decoder_output, + decode_block, exec_output) = allBlocks.makeList() +}}; diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa index 9629a54e3..6724ea9b0 100644 --- a/src/arch/x86/isa/includes.isa +++ b/src/arch/x86/isa/includes.isa @@ -97,6 +97,7 @@ output header {{ #include <iostream> #include "arch/x86/emulenv.hh" +#include "arch/x86/insts/microfpop.hh" #include "arch/x86/insts/microldstop.hh" #include "arch/x86/insts/microregop.hh" #include "arch/x86/insts/static_inst.hh" @@ -144,6 +145,7 @@ output exec {{ #include <cmath> #include "arch/x86/miscregs.hh" +#include "arch/x86/tlb.hh" #include "base/bigint.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" diff --git a/src/arch/x86/isa/insts/__init__.py b/src/arch/x86/isa/insts/__init__.py index e261a00db..0ef617a87 100644 --- a/src/arch/x86/isa/insts/__init__.py +++ b/src/arch/x86/isa/insts/__init__.py @@ -53,25 +53,11 @@ # # Authors: Gabe Black -categories = ["arithmetic", - "cache_and_memory_management", - "compare_and_test", - "control_transfer", - "data_conversion", - "data_transfer", - "flags", - "input_output", - "load_effective_address", - "load_segment_registers", - "logical", - "no_operation", - "processor_information", - "rotate_and_shift", - "semaphores", - "sse", - "string", - "system_calls", - "system"] +categories = ["general_purpose", + "simd128", + "simd64", + "system", + "x87"] microcode = ''' # X86 microcode diff --git a/src/arch/x86/isa/insts/flags/load_and_store.py b/src/arch/x86/isa/insts/flags/load_and_store.py deleted file mode 100644 index c6f279a25..000000000 --- a/src/arch/x86/isa/insts/flags/load_and_store.py +++ /dev/null @@ -1,62 +0,0 @@ -# Copyright (c) 2007 The Hewlett-Packard Development Company -# All rights reserved. -# -# Redistribution and use of this software in source and binary forms, -# with or without modification, are permitted provided that the -# following conditions are met: -# -# The software must be used only for Non-Commercial Use which means any -# use which is NOT directed to receiving any direct monetary -# compensation for, or commercial advantage from such use. Illustrative -# examples of non-commercial use are academic research, personal study, -# teaching, education and corporate research & development. -# Illustrative examples of commercial use are distributing products for -# commercial advantage and providing services using the software for -# commercial advantage. -# -# If you wish to use this software or functionality therein that may be -# covered by patents for commercial use, please contact: -# Director of Intellectual Property Licensing -# Office of Strategy and Technology -# Hewlett-Packard Company -# 1501 Page Mill Road -# Palo Alto, California 94304 -# -# Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. Redistributions -# in binary form must reproduce the above copyright notice, this list of -# conditions and the following disclaimer in the documentation and/or -# other materials provided with the distribution. Neither the name of -# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. No right of -# sublicense is granted herewith. Derivatives of the software and -# output created using the software may be prepared, but only for -# Non-Commercial Uses. Derivatives of the software may be shared with -# others provided: (i) the others agree to abide by the list of -# conditions herein which includes the Non-Commercial Use restrictions; -# and (ii) such Derivatives of the software include the above copyright -# notice to acknowledge the contribution from this software where -# applicable, this list of conditions and the disclaimer below. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Gabe Black - -microcode = "" -#let {{ -# class LAHF(Inst): -# "GenFault ${new UnimpInstFault}" -# class SAHF(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; diff --git a/src/arch/x86/isa/insts/flags/push_and_pop.py b/src/arch/x86/isa/insts/flags/push_and_pop.py deleted file mode 100644 index dbb6c34c4..000000000 --- a/src/arch/x86/isa/insts/flags/push_and_pop.py +++ /dev/null @@ -1,70 +0,0 @@ -# Copyright (c) 2007 The Hewlett-Packard Development Company -# All rights reserved. -# -# Redistribution and use of this software in source and binary forms, -# with or without modification, are permitted provided that the -# following conditions are met: -# -# The software must be used only for Non-Commercial Use which means any -# use which is NOT directed to receiving any direct monetary -# compensation for, or commercial advantage from such use. Illustrative -# examples of non-commercial use are academic research, personal study, -# teaching, education and corporate research & development. -# Illustrative examples of commercial use are distributing products for -# commercial advantage and providing services using the software for -# commercial advantage. -# -# If you wish to use this software or functionality therein that may be -# covered by patents for commercial use, please contact: -# Director of Intellectual Property Licensing -# Office of Strategy and Technology -# Hewlett-Packard Company -# 1501 Page Mill Road -# Palo Alto, California 94304 -# -# Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. Redistributions -# in binary form must reproduce the above copyright notice, this list of -# conditions and the following disclaimer in the documentation and/or -# other materials provided with the distribution. Neither the name of -# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. No right of -# sublicense is granted herewith. Derivatives of the software and -# output created using the software may be prepared, but only for -# Non-Commercial Uses. Derivatives of the software may be shared with -# others provided: (i) the others agree to abide by the list of -# conditions herein which includes the Non-Commercial Use restrictions; -# and (ii) such Derivatives of the software include the above copyright -# notice to acknowledge the contribution from this software where -# applicable, this list of conditions and the disclaimer below. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Gabe Black - -microcode = "" -#let {{ -# class POPF(Inst): -# "GenFault ${new UnimpInstFault}" -# class POPFD(Inst): -# "GenFault ${new UnimpInstFault}" -# class POPFQ(Inst): -# "GenFault ${new UnimpInstFault}" -# class PUSHF(Inst): -# "GenFault ${new UnimpInstFault}" -# class PUSHFD(Inst): -# "GenFault ${new UnimpInstFault}" -# class pushfq(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; diff --git a/src/arch/x86/isa/insts/general_purpose/__init__.py b/src/arch/x86/isa/insts/general_purpose/__init__.py new file mode 100644 index 000000000..4f77cb233 --- /dev/null +++ b/src/arch/x86/isa/insts/general_purpose/__init__.py @@ -0,0 +1,79 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["arithmetic", + "cache_and_memory_management", + "compare_and_test", + "control_transfer", + "data_conversion", + "data_transfer", + "flags", + "input_output", + "load_effective_address", + "load_segment_registers", + "logical", + "no_operation", + "processor_information", + "rotate_and_shift", + "semaphores", + "string", + "system_calls"] + +microcode = ''' +# Microcode for general purpose instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/arithmetic/__init__.py b/src/arch/x86/isa/insts/general_purpose/arithmetic/__init__.py index c7e6b8c5f..c7e6b8c5f 100644 --- a/src/arch/x86/isa/insts/arithmetic/__init__.py +++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/__init__.py diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py index 87fbb796c..e58fc00d7 100644 --- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py +++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py @@ -68,7 +68,7 @@ def macroop ADD_R_I def macroop ADD_M_I { limm t2, imm - ld t1, seg, sib, disp + ldst t1, seg, sib, disp add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -77,14 +77,14 @@ def macroop ADD_P_I { rdip t7 limm t2, imm - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; def macroop ADD_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -92,7 +92,7 @@ def macroop ADD_M_R def macroop ADD_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; @@ -137,7 +137,7 @@ def macroop SUB_R_P def macroop SUB_M_I { limm t2, imm - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -146,14 +146,14 @@ def macroop SUB_P_I { rdip t7 limm t2, imm - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; def macroop SUB_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -161,7 +161,7 @@ def macroop SUB_M_R def macroop SUB_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; @@ -180,7 +180,7 @@ def macroop ADC_R_I def macroop ADC_M_I { limm t2, imm - ld t1, seg, sib, disp + ldst t1, seg, sib, disp adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -189,14 +189,14 @@ def macroop ADC_P_I { rdip t7 limm t2, imm - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; def macroop ADC_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -204,7 +204,7 @@ def macroop ADC_M_R def macroop ADC_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; @@ -249,7 +249,7 @@ def macroop SBB_R_P def macroop SBB_M_I { limm t2, imm - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -258,14 +258,14 @@ def macroop SBB_P_I { rdip t7 limm t2, imm - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; def macroop SBB_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, sib, disp }; @@ -273,7 +273,7 @@ def macroop SBB_M_R def macroop SBB_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) st t1, seg, riprel, disp }; @@ -285,7 +285,7 @@ def macroop NEG_R def macroop NEG_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF) st t1, seg, sib, disp }; @@ -293,7 +293,7 @@ def macroop NEG_M def macroop NEG_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF) st t1, seg, riprel, disp }; diff --git a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py index 2a8024eee..7afd24992 100644 --- a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py +++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py @@ -61,7 +61,7 @@ def macroop INC_R def macroop INC_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) st t1, seg, sib, disp }; @@ -69,7 +69,7 @@ def macroop INC_M def macroop INC_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) st t1, seg, riprel, disp }; @@ -81,7 +81,7 @@ def macroop DEC_R def macroop DEC_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) st t1, seg, sib, disp }; @@ -89,7 +89,7 @@ def macroop DEC_M def macroop DEC_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF) st t1, seg, riprel, disp }; diff --git a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py b/src/arch/x86/isa/insts/general_purpose/arithmetic/multiply_and_divide.py index a9b53acac..a9b53acac 100644 --- a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py +++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/multiply_and_divide.py diff --git a/src/arch/x86/isa/insts/cache_and_memory_management.py b/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py index b5fc43fcd..b5fc43fcd 100644 --- a/src/arch/x86/isa/insts/cache_and_memory_management.py +++ b/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py diff --git a/src/arch/x86/isa/insts/compare_and_test/__init__.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/__init__.py index 56f33585a..56f33585a 100644 --- a/src/arch/x86/isa/insts/compare_and_test/__init__.py +++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/__init__.py diff --git a/src/arch/x86/isa/insts/compare_and_test/bit_scan.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py index f04520296..f04520296 100644 --- a/src/arch/x86/isa/insts/compare_and_test/bit_scan.py +++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py diff --git a/src/arch/x86/isa/insts/compare_and_test/bit_test.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py index e950f008a..e950f008a 100644 --- a/src/arch/x86/isa/insts/compare_and_test/bit_test.py +++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py diff --git a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bounds.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bounds.py new file mode 100644 index 000000000..2df5cf746 --- /dev/null +++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bounds.py @@ -0,0 +1,69 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop BOUND_R_M { + ld t1, seg, sib, disp, dataSize="env.dataSize * 2" + srli t2, t1, "env.dataSize * 8" + sub t1, t1, reg, flags=(ECF,) + fault "new BoundRange", flags=(CECF,) + sub t2, reg, t2, flags=(ECF,) + fault "new BoundRange", flags=(CECF,) +}; + +def macroop BOUND_R_P { + fault "new UnimpInstFault" +}; +''' diff --git a/src/arch/x86/isa/insts/compare_and_test/compare.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/compare.py index 76c75a442..76c75a442 100644 --- a/src/arch/x86/isa/insts/compare_and_test/compare.py +++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/compare.py diff --git a/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/set_byte_on_condition.py index 81091905c..fab42dffd 100644 --- a/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py +++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/set_byte_on_condition.py @@ -54,6 +54,11 @@ # Authors: Gabe Black microcode = ''' +def macroop SALC_R +{ + sbb reg, reg, reg, dataSize=1 +}; + def macroop SETZ_R { movi reg, reg, 1, flags=(CZF,) diff --git a/src/arch/x86/isa/insts/compare_and_test/test.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/test.py index 2b4bf7b9a..2b4bf7b9a 100644 --- a/src/arch/x86/isa/insts/compare_and_test/test.py +++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/test.py diff --git a/src/arch/x86/isa/insts/control_transfer/__init__.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/__init__.py index 6694b857c..6694b857c 100644 --- a/src/arch/x86/isa/insts/control_transfer/__init__.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/__init__.py diff --git a/src/arch/x86/isa/insts/control_transfer/call.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py index 504e9ab0a..45a7822fb 100644 --- a/src/arch/x86/isa/insts/control_transfer/call.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/call.py @@ -61,8 +61,8 @@ def macroop CALL_NEAR_I limm t1, imm rdip t7 - subi rsp, rsp, dsz - st t7, ss, [0, t0, rsp] + # Check target of call + stupd t7, ss, [0, t0, rsp], "-env.dataSize" wrip t7, t1 }; @@ -72,8 +72,8 @@ def macroop CALL_NEAR_R .adjust_env oszIn64Override rdip t1 - subi rsp, rsp, dsz - st t1, ss, [0, t0, rsp] + # Check target of call + stupd t1, ss, [0, t0, rsp], "-env.dataSize" wripi reg, 0 }; @@ -84,8 +84,8 @@ def macroop CALL_NEAR_M rdip t7 ld t1, seg, sib, disp - subi rsp, rsp, dsz - st t7, ss, [0, t0, rsp] + # Check target of call + stupd t7, ss, [0, t0, rsp], "-env.dataSize" wripi t1, 0 }; @@ -96,8 +96,8 @@ def macroop CALL_NEAR_P rdip t7 ld t1, seg, riprel, disp - subi rsp, rsp, dsz - st t7, ss, [0, t0, rsp] + # Check target of call + stupd t7, ss, [0, t0, rsp], "-env.dataSize" wripi t1, 0 }; ''' diff --git a/src/arch/x86/isa/insts/control_transfer/conditional_jump.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py index b04ca97d6..c2856e630 100644 --- a/src/arch/x86/isa/insts/control_transfer/conditional_jump.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py @@ -213,4 +213,11 @@ def macroop JNO_I limm t2, imm wrip t1, t2, flags=(nCOF,) }; + +def macroop JRCX_I +{ + rdip t1 + add t0, t0, rcx, flags=(EZF,), dataSize=asz + wripi t1, imm, flags=(CEZF,) +}; ''' diff --git a/src/arch/x86/isa/insts/control_transfer/interrupts_and_exceptions.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py index 7039b4b5c..7039b4b5c 100644 --- a/src/arch/x86/isa/insts/control_transfer/interrupts_and_exceptions.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py diff --git a/src/arch/x86/isa/insts/control_transfer/jump.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py index bb3ae4213..bb3ae4213 100644 --- a/src/arch/x86/isa/insts/control_transfer/jump.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/loop.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/loop.py new file mode 100644 index 000000000..c5674db7f --- /dev/null +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/loop.py @@ -0,0 +1,74 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop LOOP_I { + rdip t1 + subi rcx, rcx, 1, flags=(EZF,), dataSize=asz + wripi t1, imm, flags=(nCEZF,) +}; + +def macroop LOOPNE_I { + rdip t1 + subi rcx, rcx, 1, flags=(EZF,), dataSize=asz + wripi t1, imm, flags=(CSTRnZnEZF,) +}; + +def macroop LOOPE_I { + rdip t1 + subi rcx, rcx, 1, flags=(EZF,), dataSize=asz + wripi t1, imm, flags=(CSTRZnEZF,) +}; +''' diff --git a/src/arch/x86/isa/insts/control_transfer/xreturn.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py index 1efddf1d2..8993f5ac4 100644 --- a/src/arch/x86/isa/insts/control_transfer/xreturn.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/xreturn.py @@ -60,6 +60,7 @@ def macroop RET_NEAR .adjust_env oszIn64Override ld t1, ss, [1, t0, rsp] + # Check address of return addi rsp, rsp, dsz wripi t1, 0 }; @@ -71,6 +72,7 @@ def macroop RET_NEAR_I limm t2, imm ld t1, ss, [1, t0, rsp] + # Check address of return addi rsp, rsp, dsz add rsp, rsp, t2 wripi t1, 0 diff --git a/src/arch/x86/isa/insts/data_conversion/__init__.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/__init__.py index b3a40b8a0..b3a40b8a0 100644 --- a/src/arch/x86/isa/insts/data_conversion/__init__.py +++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/__init__.py diff --git a/src/arch/x86/isa/insts/data_conversion/ascii_adjust.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/ascii_adjust.py index a1e322e56..a1e322e56 100644 --- a/src/arch/x86/isa/insts/data_conversion/ascii_adjust.py +++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/ascii_adjust.py diff --git a/src/arch/x86/isa/insts/data_conversion/bcd_adjust.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/bcd_adjust.py index 213724768..213724768 100644 --- a/src/arch/x86/isa/insts/data_conversion/bcd_adjust.py +++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/bcd_adjust.py diff --git a/src/arch/x86/isa/insts/data_conversion/endian_conversion.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py index b98d09816..b98d09816 100644 --- a/src/arch/x86/isa/insts/data_conversion/endian_conversion.py +++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py diff --git a/src/arch/x86/isa/insts/data_conversion/extract_sign_mask.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/extract_sign_mask.py index 1e0810594..1e0810594 100644 --- a/src/arch/x86/isa/insts/data_conversion/extract_sign_mask.py +++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/extract_sign_mask.py diff --git a/src/arch/x86/isa/insts/data_conversion/sign_extension.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py index 9a7c226af..9a7c226af 100644 --- a/src/arch/x86/isa/insts/data_conversion/sign_extension.py +++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/sign_extension.py diff --git a/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py new file mode 100644 index 000000000..c2ccb9d19 --- /dev/null +++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py @@ -0,0 +1,64 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop XLAT { + zext t1, rax, 8 + # Here, t1 can be used directly. The value of al is supposed to be treated + # as unsigned. Since we zero extended it from 8 bits above and the address + # size has to be at least 16 bits, t1 will not be sign extended. + ld rax, seg, [1, rbx, t1], dataSize=1 +}; +''' diff --git a/src/arch/x86/isa/insts/data_transfer/__init__.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/__init__.py index 365f95eaa..365f95eaa 100644 --- a/src/arch/x86/isa/insts/data_transfer/__init__.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/__init__.py diff --git a/src/arch/x86/isa/insts/data_transfer/conditional_move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py index 1a60c5b61..1a60c5b61 100644 --- a/src/arch/x86/isa/insts/data_transfer/conditional_move.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py diff --git a/src/arch/x86/isa/insts/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py index a248f5656..04f9ea12a 100644 --- a/src/arch/x86/isa/insts/data_transfer/move.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py @@ -59,6 +59,16 @@ microcode = ''' # Regular moves # +def macroop MOV_R_MI { + limm t1, imm + ld reg, seg, [1, t0, t1] +}; + +def macroop MOV_MI_R { + limm t1, imm + st reg, seg, [1, t0, t1] +}; + def macroop MOV_R_R { mov reg, reg, regm }; diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py index 9e6807039..5884d68c2 100644 --- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py @@ -58,8 +58,9 @@ def macroop POP_R { # Make the default data size of pops 64 bits in 64 bit mode .adjust_env oszIn64Override - ld reg, ss, [1, t0, rsp] + ld t1, ss, [1, t0, rsp] addi rsp, rsp, dsz + mov reg, reg, t1 }; def macroop POP_M { @@ -67,6 +68,7 @@ def macroop POP_M { .adjust_env oszIn64Override ld t1, ss, [1, t0, rsp] + cda seg, sib, disp addi rsp, rsp, dsz st t1, seg, sib, disp }; @@ -77,6 +79,7 @@ def macroop POP_P { rdip t7 ld t1, ss, [1, t0, rsp] + cda seg, sib, disp addi rsp, rsp, dsz st t1, seg, riprel, disp }; @@ -85,10 +88,7 @@ def macroop PUSH_R { # Make the default data size of pops 64 bits in 64 bit mode .adjust_env oszIn64Override - # This needs to work slightly differently from the other versions of push - # because the -original- version of the stack pointer is what gets pushed - st reg, ss, [1, t0, rsp], "-env.dataSize" - subi rsp, rsp, dsz + stupd reg, ss, [1, t0, rsp], "-env.dataSize" }; def macroop PUSH_I { @@ -96,8 +96,7 @@ def macroop PUSH_I { .adjust_env oszIn64Override limm t1, imm - subi rsp, rsp, dsz - st t1, ss, [1, t0, rsp] + stupd t1, ss, [1, t0, rsp], "-env.dataSize" }; def macroop PUSH_M { @@ -105,8 +104,7 @@ def macroop PUSH_M { .adjust_env oszIn64Override ld t1, seg, sib, disp - subi rsp, rsp, dsz - st t1, ss, [1, t0, rsp] + stupd t1, ss, [1, t0, rsp], "-env.dataSize" }; def macroop PUSH_P { @@ -115,30 +113,36 @@ def macroop PUSH_P { rdip t7 ld t1, seg, riprel, disp - subi rsp, rsp, dsz - st t1, ss, [1, t0, rsp] + stupd t1, ss, [1, t0, rsp], "-env.dataSize" }; def macroop PUSHA { - st rax, ss, [1, t0, rsp], "-0 * env.dataSize" - st rcx, ss, [1, t0, rsp], "-1 * env.dataSize" - st rdx, ss, [1, t0, rsp], "-2 * env.dataSize" - st rbx, ss, [1, t0, rsp], "-3 * env.dataSize" - st rsp, ss, [1, t0, rsp], "-4 * env.dataSize" - st rbp, ss, [1, t0, rsp], "-5 * env.dataSize" - st rsi, ss, [1, t0, rsp], "-6 * env.dataSize" - st rdi, ss, [1, t0, rsp], "-7 * env.dataSize" - subi rsp, rsp, "8 * env.dataSize" + # Check all the stack addresses. We'll assume that if the beginning and + # end are ok, then the stuff in the middle should be as well. + cda ss, [1, t0, rsp], "-env.dataSize" + cda ss, [1, t0, rsp], "-8 * env.dataSize" + stupd rax, ss, [1, t0, rsp], "-env.dataSize" + stupd rcx, ss, [1, t0, rsp], "-env.dataSize" + stupd rdx, ss, [1, t0, rsp], "-env.dataSize" + stupd rbx, ss, [1, t0, rsp], "-env.dataSize" + stupd rsp, ss, [1, t0, rsp], "-env.dataSize" + stupd rbp, ss, [1, t0, rsp], "-env.dataSize" + stupd rsi, ss, [1, t0, rsp], "-env.dataSize" + stupd rdi, ss, [1, t0, rsp], "-env.dataSize" }; def macroop POPA { - ld rdi, ss, [1, t0, rsp], "0 * env.dataSize" + # Check all the stack addresses. We'll assume that if the beginning and + # end are ok, then the stuff in the middle should be as well. + ld t1, ss, [1, t0, rsp], "0 * env.dataSize" + ld t2, ss, [1, t0, rsp], "7 * env.dataSize" + mov rdi, rdi, t1 ld rsi, ss, [1, t0, rsp], "1 * env.dataSize" ld rbp, ss, [1, t0, rsp], "2 * env.dataSize" ld rbx, ss, [1, t0, rsp], "4 * env.dataSize" ld rdx, ss, [1, t0, rsp], "5 * env.dataSize" ld rcx, ss, [1, t0, rsp], "6 * env.dataSize" - ld rax, ss, [1, t0, rsp], "7 * env.dataSize" + mov rax, rax, t2 addi rsp, rsp, "8 * env.dataSize" }; @@ -146,12 +150,53 @@ def macroop LEAVE { # Make the default data size of pops 64 bits in 64 bit mode .adjust_env oszIn64Override - mov rsp, rsp, rbp - ld rbp, ss, [1, t0, rsp] + mov t1, t1, rbp + ld rbp, ss, [1, t0, t1] + mov rsp, rsp, t1 addi rsp, rsp, dsz }; + +def macroop ENTER_I_I { + # This needs to check all the addresses it writes to before it actually + # writes any values. + + # Pull the different components out of the immediate + limm t1, imm + zext t2, t1, 16, dataSize=2 + srl t1, t1, 16 + zext t1, t1, 6 + # t1 is now the masked nesting level, and t2 is the amount of storage. + + # Push rbp. + stupd rbp, ss, [1, t0, rsp], "-env.dataSize" + + # Save the stack pointer for later + mov t6, t6, rsp + + # If the nesting level is zero, skip all this stuff. + subi t0, t1, t0, flags=(EZF,), dataSize=2 + bri t0, label("skipLoop"), flags=(CEZF,) + + # If the level was 1, only push the saved rbp + subi t0, t1, 1, flags=(EZF,) + bri t0, label("bottomOfLoop"), flags=(CEZF,) + + limm t4, "ULL(-1)", dataSize=8 +topOfLoop: + ld t5, ss, [dsz, t4, rbp] + stupd t5, ss, [1, t0, rsp], "-env.dataSize" + + # If we're not done yet, loop + subi t4, t4, 1, dataSize=8 + add t0, t4, t1, flags=(EZF,) + bri t0, label("topOfLoop"), flags=(nCEZF,) + +bottomOfLoop: + # Push the old rbp onto the stack + stupd t6, ss, [1, t0, rsp], "-env.dataSize" + +skipLoop: + sub rsp, rsp, t2 + mov rbp, rbp, t6 +}; ''' -#let {{ -# class ENTER(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; diff --git a/src/arch/x86/isa/insts/data_transfer/xchg.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py index 9478c71fc..3f243f5d8 100644 --- a/src/arch/x86/isa/insts/data_transfer/xchg.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py @@ -68,7 +68,7 @@ def macroop XCHG_R_R def macroop XCHG_R_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp st reg, seg, sib, disp mov reg, reg, t1 }; @@ -76,14 +76,14 @@ def macroop XCHG_R_M def macroop XCHG_R_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp st reg, seg, riprel, disp mov reg, reg, t1 }; def macroop XCHG_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp st reg, seg, sib, disp mov reg, reg, t1 }; @@ -91,7 +91,7 @@ def macroop XCHG_M_R def macroop XCHG_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp st reg, seg, riprel, disp mov reg, reg, t1 }; diff --git a/src/arch/x86/isa/insts/flags/__init__.py b/src/arch/x86/isa/insts/general_purpose/flags/__init__.py index 92a8e6a2d..92a8e6a2d 100644 --- a/src/arch/x86/isa/insts/flags/__init__.py +++ b/src/arch/x86/isa/insts/general_purpose/flags/__init__.py diff --git a/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py b/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py new file mode 100644 index 000000000..0915bf819 --- /dev/null +++ b/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py @@ -0,0 +1,80 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop SAHF { + # This will fold to ah since this never executes in 64 bit mode. + ruflags rsp, dataSize=1 +}; + +# This is allows the instruction to write to ah in 64 bit mode. +def macroop SAHF_64 { + ruflags t1 + slli t1, t1, 8 + mov t1, t1, rax, dataSize=1 + mov rax, rax, t1, dataSize=2 +}; + +def macroop LAHF { + # This will fold to ah since this never executes in 64 bit mode. + wruflags rsp, t0, dataSize=1 +}; + +# This is allows the instruction to read from ah in 64 bit mode. +def macroop LAHF_64 { + srli t1, rax, 8, dataSize=2 + wruflags t1, t0, dataSize=1 +}; +''' diff --git a/src/arch/x86/isa/insts/general_purpose/flags/push_and_pop.py b/src/arch/x86/isa/insts/general_purpose/flags/push_and_pop.py new file mode 100644 index 000000000..fe60350c1 --- /dev/null +++ b/src/arch/x86/isa/insts/general_purpose/flags/push_and_pop.py @@ -0,0 +1,73 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop PUSHF { + .adjust_env oszIn64Override + + # This should really read the whole flags register, not just user flags. + ruflags t1 + stupd t1, ss, [1, t0, rsp], "-env.dataSize" +}; + +def macroop POPF { + .adjust_env oszIn64Override + + ld t1, ss, [1, t0, rsp] + addi rsp, rsp, dsz + # This should really write the whole flags register, not just user flags. + wruflags t1, t0 +}; +''' diff --git a/src/arch/x86/isa/insts/flags/set_and_clear.py b/src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py index 4c655e0b2..4c655e0b2 100644 --- a/src/arch/x86/isa/insts/flags/set_and_clear.py +++ b/src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py diff --git a/src/arch/x86/isa/insts/input_output/__init__.py b/src/arch/x86/isa/insts/general_purpose/input_output/__init__.py index 54fb3d9b0..54fb3d9b0 100644 --- a/src/arch/x86/isa/insts/input_output/__init__.py +++ b/src/arch/x86/isa/insts/general_purpose/input_output/__init__.py diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py new file mode 100644 index 000000000..c01a11035 --- /dev/null +++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py @@ -0,0 +1,80 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' + def macroop IN_R_I { + .adjust_imm trimImm(8) + limm t1, "IntAddrPrefixIO" + ld reg, intseg, [1, t1, t0], imm, addressSize=2 + }; + + def macroop IN_R_R { + limm t1, "IntAddrPrefixIO" + zext t2, regm, 16, dataSize=2 + ld reg, intseg, [1, t1, t2], addressSize=8 + }; + + def macroop OUT_I_R { + .adjust_imm trimImm(8) + limm t1, "IntAddrPrefixIO" + st reg, intseg, [1, t1, t0], imm, addressSize=8 + }; + + def macroop OUT_R_R { + limm t1, "IntAddrPrefixIO" + zext t2, reg, 16, dataSize=2 + st regm, intseg, [1, t1, t2], addressSize=8 + }; +''' diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py new file mode 100644 index 000000000..a8acbbc39 --- /dev/null +++ b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py @@ -0,0 +1,128 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop INS_M_R { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + + limm t1, "IntAddrPrefixIO" + zext t2, reg, 16, dataSize=2 + + ld t6, intseg, [1, t1, t2], addressSize=8 + st t6, es, [1, t0, rdi] + + add rdi, rdi, t3, dataSize=asz +}; + +def macroop INS_E_M_R { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + + limm t1, "IntAddrPrefixIO" + zext t2, reg, 16, dataSize=2 + +topOfLoop: + ld t6, intseg, [1, t1, t2], addressSize=8 + st t6, es, [1, t0, rdi] + + subi rcx, rcx, 1, flags=(EZF,), dataSize=asz + add rdi, rdi, t3, dataSize=asz + bri t0, label("topOfLoop"), flags=(nCEZF,) + fault "NoFault" +}; + +def macroop OUTS_R_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + + limm t1, "IntAddrPrefixIO" + zext t2, reg, 16, dataSize=2 + + ld t6, ds, [1, t0, rsi] + st t6, intseg, [1, t1, t2], addressSize=8 + + add rsi, rsi, t3, dataSize=asz +}; + +def macroop OUTS_E_R_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + + limm t1, "IntAddrPrefixIO" + zext t2, reg, 16, dataSize=2 + +topOfLoop: + ld t6, ds, [1, t0, rsi] + st t6, intseg, [1, t1, t2], addressSize=8 + + subi rcx, rcx, 1, flags=(EZF,), dataSize=asz + add rsi, rsi, t3, dataSize=asz + bri t0, label("topOfLoop"), flags=(nCEZF,) + fault "NoFault" +}; +''' diff --git a/src/arch/x86/isa/insts/load_effective_address.py b/src/arch/x86/isa/insts/general_purpose/load_effective_address.py index 0c4e0f7df..0c4e0f7df 100644 --- a/src/arch/x86/isa/insts/load_effective_address.py +++ b/src/arch/x86/isa/insts/general_purpose/load_effective_address.py diff --git a/src/arch/x86/isa/insts/load_segment_registers.py b/src/arch/x86/isa/insts/general_purpose/load_segment_registers.py index 8aec4b99e..8aec4b99e 100644 --- a/src/arch/x86/isa/insts/load_segment_registers.py +++ b/src/arch/x86/isa/insts/general_purpose/load_segment_registers.py diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/general_purpose/logical.py index 2137ae82f..a8b7c6a45 100644 --- a/src/arch/x86/isa/insts/logical.py +++ b/src/arch/x86/isa/insts/general_purpose/logical.py @@ -62,7 +62,7 @@ def macroop OR_R_R def macroop OR_M_I { limm t2, imm - ld t1, seg, sib, disp + ldst t1, seg, sib, disp or t1, t1, t2, flags=(OF,SF,ZF,PF,CF) st t1, seg, sib, disp }; @@ -71,14 +71,14 @@ def macroop OR_P_I { limm t2, imm rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp or t1, t1, t2, flags=(OF,SF,ZF,PF,CF) st t1, seg, riprel, disp }; def macroop OR_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp or t1, t1, reg, flags=(OF,SF,ZF,PF,CF) st t1, seg, sib, disp }; @@ -86,7 +86,7 @@ def macroop OR_M_R def macroop OR_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp or t1, t1, reg, flags=(OF,SF,ZF,PF,CF) st t1, seg, riprel, disp }; @@ -124,7 +124,7 @@ def macroop XOR_R_I def macroop XOR_M_I { limm t2, imm - ld t1, seg, sib, disp + ldst t1, seg, sib, disp xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF) st t1, seg, sib, disp }; @@ -133,14 +133,14 @@ def macroop XOR_P_I { limm t2, imm rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF) st t1, seg, riprel, disp }; def macroop XOR_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF) st t1, seg, sib, disp }; @@ -148,7 +148,7 @@ def macroop XOR_M_R def macroop XOR_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF) st t1, seg, riprel, disp }; @@ -192,7 +192,7 @@ def macroop AND_R_I def macroop AND_M_I { - ld t2, seg, sib, disp + ldst t2, seg, sib, disp limm t1, imm and t2, t2, t1, flags=(OF,SF,ZF,PF,CF) st t2, seg, sib, disp @@ -201,7 +201,7 @@ def macroop AND_M_I def macroop AND_P_I { rdip t7 - ld t2, seg, riprel, disp + ldst t2, seg, riprel, disp limm t1, imm and t2, t2, t1, flags=(OF,SF,ZF,PF,CF) st t2, seg, riprel, disp @@ -209,7 +209,7 @@ def macroop AND_P_I def macroop AND_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp and t1, t1, reg, flags=(OF,SF,ZF,PF,CF) st t1, seg, sib, disp }; @@ -217,7 +217,7 @@ def macroop AND_M_R def macroop AND_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp and t1, t1, reg, flags=(OF,SF,ZF,PF,CF) st t1, seg, riprel, disp }; @@ -231,7 +231,7 @@ def macroop NOT_R def macroop NOT_M { limm t1, -1 - ld t2, seg, sib, disp + ldst t2, seg, sib, disp xor t2, t2, t1 st t2, seg, sib, disp }; @@ -240,7 +240,7 @@ def macroop NOT_P { limm t1, -1 rdip t7 - ld t2, seg, riprel, disp + ldst t2, seg, riprel, disp xor t2, t2, t1 st t2, seg, riprel, disp }; diff --git a/src/arch/x86/isa/insts/no_operation.py b/src/arch/x86/isa/insts/general_purpose/no_operation.py index 306ee2797..306ee2797 100644 --- a/src/arch/x86/isa/insts/no_operation.py +++ b/src/arch/x86/isa/insts/general_purpose/no_operation.py diff --git a/src/arch/x86/isa/insts/processor_information.py b/src/arch/x86/isa/insts/general_purpose/processor_information.py index 6070169ac..6070169ac 100644 --- a/src/arch/x86/isa/insts/processor_information.py +++ b/src/arch/x86/isa/insts/general_purpose/processor_information.py diff --git a/src/arch/x86/isa/insts/rotate_and_shift/__init__.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/__init__.py index c6c019f0d..c6c019f0d 100644 --- a/src/arch/x86/isa/insts/rotate_and_shift/__init__.py +++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/__init__.py diff --git a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py index a13df3a64..b5ae9560e 100644 --- a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py +++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py @@ -61,7 +61,7 @@ def macroop ROL_R_I def macroop ROL_M_I { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp roli t1, t1, imm st t1, seg, sib, disp }; @@ -69,7 +69,7 @@ def macroop ROL_M_I def macroop ROL_P_I { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp roli t1, t1, imm st t1, seg, riprel, disp }; @@ -81,7 +81,7 @@ def macroop ROL_1_R def macroop ROL_1_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp roli t1, t1, 1 st t1, seg, sib, disp }; @@ -89,7 +89,7 @@ def macroop ROL_1_M def macroop ROL_1_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp roli t1, t1, 1 st t1, seg, riprel, disp }; @@ -101,7 +101,7 @@ def macroop ROL_R_R def macroop ROL_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rol t1, t1, reg st t1, seg, sib, disp }; @@ -109,7 +109,7 @@ def macroop ROL_M_R def macroop ROL_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rol t1, t1, reg st t1, seg, riprel, disp }; @@ -121,7 +121,7 @@ def macroop ROR_R_I def macroop ROR_M_I { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rori t1, t1, imm st t1, seg, sib, disp }; @@ -129,7 +129,7 @@ def macroop ROR_M_I def macroop ROR_P_I { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rori t1, t1, imm st t1, seg, riprel, disp }; @@ -141,7 +141,7 @@ def macroop ROR_1_R def macroop ROR_1_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rori t1, t1, 1 st t1, seg, sib, disp }; @@ -149,7 +149,7 @@ def macroop ROR_1_M def macroop ROR_1_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rori t1, t1, 1 st t1, seg, riprel, disp }; @@ -161,7 +161,7 @@ def macroop ROR_R_R def macroop ROR_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp ror t1, t1, reg st t1, seg, sib, disp }; @@ -169,7 +169,7 @@ def macroop ROR_M_R def macroop ROR_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp ror t1, t1, reg st t1, seg, riprel, disp }; @@ -181,7 +181,7 @@ def macroop RCL_R_I def macroop RCL_M_I { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rcli t1, t1, imm st t1, seg, sib, disp }; @@ -189,7 +189,7 @@ def macroop RCL_M_I def macroop RCL_P_I { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rcli t1, t1, imm st t1, seg, riprel, disp }; @@ -201,7 +201,7 @@ def macroop RCL_1_R def macroop RCL_1_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rcli t1, t1, 1 st t1, seg, sib, disp }; @@ -209,7 +209,7 @@ def macroop RCL_1_M def macroop RCL_1_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rcli t1, t1, 1 st t1, seg, riprel, disp }; @@ -221,7 +221,7 @@ def macroop RCL_R_R def macroop RCL_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rcl t1, t1, reg st t1, seg, sib, disp }; @@ -229,7 +229,7 @@ def macroop RCL_M_R def macroop RCL_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rcl t1, t1, reg st t1, seg, riprel, disp }; @@ -241,7 +241,7 @@ def macroop RCR_R_I def macroop RCR_M_I { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rcri t1, t1, imm st t1, seg, sib, disp }; @@ -249,7 +249,7 @@ def macroop RCR_M_I def macroop RCR_P_I { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rcri t1, t1, imm st t1, seg, riprel, disp }; @@ -261,7 +261,7 @@ def macroop RCR_1_R def macroop RCR_1_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rcri t1, t1, 1 st t1, seg, sib, disp }; @@ -269,7 +269,7 @@ def macroop RCR_1_M def macroop RCR_1_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rcri t1, t1, 1 st t1, seg, riprel, disp }; @@ -281,7 +281,7 @@ def macroop RCR_R_R def macroop RCR_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp rcr t1, t1, reg st t1, seg, sib, disp }; @@ -289,7 +289,7 @@ def macroop RCR_M_R def macroop RCR_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp rcr t1, t1, reg st t1, seg, riprel, disp }; diff --git a/src/arch/x86/isa/insts/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py index 6c688cca3..ed7d761b8 100644 --- a/src/arch/x86/isa/insts/rotate_and_shift/shift.py +++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py @@ -61,7 +61,7 @@ def macroop SAL_R_I def macroop SAL_M_I { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp slli t1, t1, imm, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -69,7 +69,7 @@ def macroop SAL_M_I def macroop SAL_P_I { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp slli t1, t1, imm, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -81,7 +81,7 @@ def macroop SAL_1_R def macroop SAL_1_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp slli t1, t1, 1, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -89,7 +89,7 @@ def macroop SAL_1_M def macroop SAL_1_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp slli t1, t1, 1, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -101,7 +101,7 @@ def macroop SAL_R_R def macroop SAL_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sll t1, t1, reg, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -109,7 +109,7 @@ def macroop SAL_M_R def macroop SAL_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sll t1, t1, reg, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -121,7 +121,7 @@ def macroop SHR_R_I def macroop SHR_M_I { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp srli t1, t1, imm, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -129,7 +129,7 @@ def macroop SHR_M_I def macroop SHR_P_I { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp srli t1, t1, imm, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -141,7 +141,7 @@ def macroop SHR_1_R def macroop SHR_1_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp srli t1, t1, 1, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -149,7 +149,7 @@ def macroop SHR_1_M def macroop SHR_1_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp srli t1, t1, 1, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -161,7 +161,7 @@ def macroop SHR_R_R def macroop SHR_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp srl t1, t1, reg, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -169,7 +169,7 @@ def macroop SHR_M_R def macroop SHR_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp srl t1, t1, reg, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -181,7 +181,7 @@ def macroop SAR_R_I def macroop SAR_M_I { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp srai t1, t1, imm, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -189,7 +189,7 @@ def macroop SAR_M_I def macroop SAR_P_I { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp srai t1, t1, imm, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -201,7 +201,7 @@ def macroop SAR_1_R def macroop SAR_1_M { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp srai t1, t1, 1, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -209,7 +209,7 @@ def macroop SAR_1_M def macroop SAR_1_P { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp srai t1, t1, 1, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; @@ -221,7 +221,7 @@ def macroop SAR_R_R def macroop SAR_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sra t1, t1, reg, flags=(SF,ZF,PF) st t1, seg, sib, disp }; @@ -229,7 +229,7 @@ def macroop SAR_M_R def macroop SAR_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sra t1, t1, reg, flags=(SF,ZF,PF) st t1, seg, riprel, disp }; diff --git a/src/arch/x86/isa/insts/semaphores.py b/src/arch/x86/isa/insts/general_purpose/semaphores.py index 800f1b325..27a31dbd9 100644 --- a/src/arch/x86/isa/insts/semaphores.py +++ b/src/arch/x86/isa/insts/general_purpose/semaphores.py @@ -61,7 +61,7 @@ def macroop CMPXCHG_R_R { }; def macroop CMPXCHG_M_R { - ld t1, seg, sib, disp + ldst t1, seg, sib, disp sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF) mov t1, t1, reg, flags=(CZF,) @@ -71,7 +71,7 @@ def macroop CMPXCHG_M_R { def macroop CMPXCHG_P_R { rdip t7 - ld t1, seg, riprel, disp + ldst t1, seg, riprel, disp sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF) mov t1, t1, reg, flags=(CZF,) diff --git a/src/arch/x86/isa/insts/string/__init__.py b/src/arch/x86/isa/insts/general_purpose/string/__init__.py index f43a8d3e5..f43a8d3e5 100644 --- a/src/arch/x86/isa/insts/string/__init__.py +++ b/src/arch/x86/isa/insts/general_purpose/string/__init__.py diff --git a/src/arch/x86/isa/insts/string/compare_strings.py b/src/arch/x86/isa/insts/general_purpose/string/compare_strings.py index 71b8511b4..71b8511b4 100644 --- a/src/arch/x86/isa/insts/string/compare_strings.py +++ b/src/arch/x86/isa/insts/general_purpose/string/compare_strings.py diff --git a/src/arch/x86/isa/insts/general_purpose/string/load_string.py b/src/arch/x86/isa/insts/general_purpose/string/load_string.py new file mode 100644 index 000000000..61525c2f2 --- /dev/null +++ b/src/arch/x86/isa/insts/general_purpose/string/load_string.py @@ -0,0 +1,84 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop LODS_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + + ld rax, seg, [1, t0, rdi] + + add rdi, rdi, t3, dataSize=asz +}; + +def macroop LODS_E_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + +topOfLoop: + ld rax, seg, [1, t0, rdi] + + subi rcx, rcx, 1, flags=(EZF,), dataSize=asz + add rdi, rdi, t3, dataSize=asz + bri t0, label("topOfLoop"), flags=(nCEZF,) + fault "NoFault" +}; +''' diff --git a/src/arch/x86/isa/insts/general_purpose/string/move_string.py b/src/arch/x86/isa/insts/general_purpose/string/move_string.py new file mode 100644 index 000000000..b64acfdc2 --- /dev/null +++ b/src/arch/x86/isa/insts/general_purpose/string/move_string.py @@ -0,0 +1,88 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop MOVS_M_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + + ld t1, seg, [1, t0, rsi] + st t1, es, [1, t0, rdi] + + add rdi, rdi, t3, dataSize=asz + add rsi, rsi, t3, dataSize=asz +}; + +def macroop MOVS_E_M_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + +topOfLoop: + ld t1, seg, [1, t0, rsi] + st t1, es, [1, t0, rdi] + + subi rcx, rcx, 1, flags=(EZF,), dataSize=asz + add rdi, rdi, t3, dataSize=asz + add rsi, rsi, t3, dataSize=asz + bri t0, label("topOfLoop"), flags=(nCEZF,) + fault "NoFault" +}; +''' diff --git a/src/arch/x86/isa/insts/string/scan_string.py b/src/arch/x86/isa/insts/general_purpose/string/scan_string.py index b038cc00a..b038cc00a 100644 --- a/src/arch/x86/isa/insts/string/scan_string.py +++ b/src/arch/x86/isa/insts/general_purpose/string/scan_string.py diff --git a/src/arch/x86/isa/insts/general_purpose/string/store_string.py b/src/arch/x86/isa/insts/general_purpose/string/store_string.py new file mode 100644 index 000000000..a8d558929 --- /dev/null +++ b/src/arch/x86/isa/insts/general_purpose/string/store_string.py @@ -0,0 +1,84 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop STOS_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + + st rax, es, [1, t0, rdi] + + add rdi, rdi, t3, dataSize=asz +}; + +def macroop STOS_E_M { + # Find the constant we need to either add or subtract from rdi + ruflag t0, 10 + movi t3, t3, dsz, flags=(CEZF,), dataSize=asz + subi t4, t0, dsz, dataSize=asz + mov t3, t3, t4, flags=(nCEZF,), dataSize=asz + +topOfLoop: + st rax, es, [1, t0, rdi] + + subi rcx, rcx, 1, flags=(EZF,), dataSize=asz + add rdi, rdi, t3, dataSize=asz + bri t0, label("topOfLoop"), flags=(nCEZF,) + fault "NoFault" +}; +''' diff --git a/src/arch/x86/isa/insts/system_calls.py b/src/arch/x86/isa/insts/general_purpose/system_calls.py index e056bea84..e056bea84 100644 --- a/src/arch/x86/isa/insts/system_calls.py +++ b/src/arch/x86/isa/insts/general_purpose/system_calls.py diff --git a/src/arch/x86/isa/insts/input_output/general_io.py b/src/arch/x86/isa/insts/input_output/general_io.py deleted file mode 100644 index f9aa9d6e4..000000000 --- a/src/arch/x86/isa/insts/input_output/general_io.py +++ /dev/null @@ -1,62 +0,0 @@ -# Copyright (c) 2007 The Hewlett-Packard Development Company -# All rights reserved. -# -# Redistribution and use of this software in source and binary forms, -# with or without modification, are permitted provided that the -# following conditions are met: -# -# The software must be used only for Non-Commercial Use which means any -# use which is NOT directed to receiving any direct monetary -# compensation for, or commercial advantage from such use. Illustrative -# examples of non-commercial use are academic research, personal study, -# teaching, education and corporate research & development. -# Illustrative examples of commercial use are distributing products for -# commercial advantage and providing services using the software for -# commercial advantage. -# -# If you wish to use this software or functionality therein that may be -# covered by patents for commercial use, please contact: -# Director of Intellectual Property Licensing -# Office of Strategy and Technology -# Hewlett-Packard Company -# 1501 Page Mill Road -# Palo Alto, California 94304 -# -# Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. Redistributions -# in binary form must reproduce the above copyright notice, this list of -# conditions and the following disclaimer in the documentation and/or -# other materials provided with the distribution. Neither the name of -# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. No right of -# sublicense is granted herewith. Derivatives of the software and -# output created using the software may be prepared, but only for -# Non-Commercial Uses. Derivatives of the software may be shared with -# others provided: (i) the others agree to abide by the list of -# conditions herein which includes the Non-Commercial Use restrictions; -# and (ii) such Derivatives of the software include the above copyright -# notice to acknowledge the contribution from this software where -# applicable, this list of conditions and the disclaimer below. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Gabe Black - -microcode = "" -#let {{ -# class IN(Inst): -# "GenFault ${new UnimpInstFault}" -# class OUT(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; diff --git a/src/arch/x86/isa/insts/input_output/string_io.py b/src/arch/x86/isa/insts/input_output/string_io.py deleted file mode 100644 index a35ba772f..000000000 --- a/src/arch/x86/isa/insts/input_output/string_io.py +++ /dev/null @@ -1,78 +0,0 @@ -# Copyright (c) 2007 The Hewlett-Packard Development Company -# All rights reserved. -# -# Redistribution and use of this software in source and binary forms, -# with or without modification, are permitted provided that the -# following conditions are met: -# -# The software must be used only for Non-Commercial Use which means any -# use which is NOT directed to receiving any direct monetary -# compensation for, or commercial advantage from such use. Illustrative -# examples of non-commercial use are academic research, personal study, -# teaching, education and corporate research & development. -# Illustrative examples of commercial use are distributing products for -# commercial advantage and providing services using the software for -# commercial advantage. -# -# If you wish to use this software or functionality therein that may be -# covered by patents for commercial use, please contact: -# Director of Intellectual Property Licensing -# Office of Strategy and Technology -# Hewlett-Packard Company -# 1501 Page Mill Road -# Palo Alto, California 94304 -# -# Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. Redistributions -# in binary form must reproduce the above copyright notice, this list of -# conditions and the following disclaimer in the documentation and/or -# other materials provided with the distribution. Neither the name of -# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. No right of -# sublicense is granted herewith. Derivatives of the software and -# output created using the software may be prepared, but only for -# Non-Commercial Uses. Derivatives of the software may be shared with -# others provided: (i) the others agree to abide by the list of -# conditions herein which includes the Non-Commercial Use restrictions; -# and (ii) such Derivatives of the software include the above copyright -# notice to acknowledge the contribution from this software where -# applicable, this list of conditions and the disclaimer below. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Gabe Black - -microcode = "" -#let {{ -# class INS(Inst): -# "GenFault ${new UnimpInstFault}" -# class INSB(Inst): -# "GenFault ${new UnimpInstFault}" -# class INSW(Inst): -# "GenFault ${new UnimpInstFault}" -# class INSD(Inst): -# "GenFault ${new UnimpInstFault}" -# class INSQ(Inst): -# "GenFault ${new UnimpInstFault}" -# class OUTS(Inst): -# "GenFault ${new UnimpInstFault}" -# class OUTSB(Inst): -# "GenFault ${new UnimpInstFault}" -# class OUTSW(Inst): -# "GenFault ${new UnimpInstFault}" -# class OUTSD(Inst): -# "GenFault ${new UnimpInstFault}" -# class OUTSQ(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; diff --git a/src/arch/x86/isa/insts/simd128/__init__.py b/src/arch/x86/isa/insts/simd128/__init__.py new file mode 100644 index 000000000..a3513651b --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/__init__.py @@ -0,0 +1,64 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["integer", + "floating_point"] + +microcode = ''' +# SSE instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/sse/__init__.py b/src/arch/x86/isa/insts/simd128/floating_point/__init__.py index 7985a124f..2a95f58ef 100644 --- a/src/arch/x86/isa/insts/sse/__init__.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/__init__.py @@ -53,13 +53,12 @@ # # Authors: Gabe Black -categories = ["move", - "convert", - "add_and_subtract", - "multiply_and_divide", - "logical", +categories = ["data_transfer", + "data_conversion", + "data_reordering", + "arithmetic", "compare", - "square_root"] + "logical"] microcode = ''' # SSE instructions diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/__init__.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/__init__.py new file mode 100644 index 000000000..b7024613f --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/__init__.py @@ -0,0 +1,72 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["addition", + "horizontal_addition", + "subtraction", + "horizontal_subtraction", + "simultaneous_addition_and_subtraction", + "multiplication", + "division", + "square_root", + "reciprocal_square_root", + "reciprocal_estimation"] + +microcode = ''' +# SSE instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/sse/add_and_subtract.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/addition.py index 5e8919106..c1764ff12 100644 --- a/src/arch/x86/isa/insts/sse/add_and_subtract.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/addition.py @@ -54,6 +54,10 @@ # Authors: Gabe Black microcode = ''' +# ADDPS +# ADDPD +# ADDSS + def macroop ADDSD_R_R { addfp xmml, xmml, xmmlm }; @@ -68,19 +72,4 @@ def macroop ADDSD_R_P { ldfp ufp1, seg, riprel, disp addfp xmml, xmml, ufp1 }; - -def macroop SUBSD_R_R { - subfp xmml, xmml, xmmlm -}; - -def macroop SUBSD_R_M { - ldfp ufp1, seg, sib, disp - subfp xmml, xmml, ufp1 -}; - -def macroop SUBSD_R_P { - rdip t7 - ldfp ufp1, seg, riprel, disp - subfp xmml, xmml, ufp1 -}; ''' diff --git a/src/arch/x86/isa/insts/sse/multiply_and_divide.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/division.py index d555c6e1a..31f336696 100644 --- a/src/arch/x86/isa/insts/sse/multiply_and_divide.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/division.py @@ -54,20 +54,9 @@ # Authors: Gabe Black microcode = ''' -def macroop MULSD_R_R { - mulfp xmml, xmml, xmmlm -}; - -def macroop MULSD_R_M { - ldfp ufp1, seg, sib, disp - mulfp xmml, xmml, ufp1 -}; - -def macroop MULSD_R_P { - rdip t7 - ldfp ufp1, seg, riprel, disp - mulfp xmml, xmml, ufp1 -}; +# DIVPS +# DIVPD +# DIVSS def macroop DIVSD_R_R { divfp xmml, xmml, xmmlm diff --git a/src/arch/x86/isa/insts/data_conversion/translate.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py index bb286b976..8b307d3da 100644 --- a/src/arch/x86/isa/insts/data_conversion/translate.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py @@ -53,8 +53,7 @@ # # Authors: Gabe Black -microcode = "" -#let {{ -# class XLAT(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; +microcode = ''' +# HADDPS +# HADDPD +''' diff --git a/src/arch/x86/isa/insts/compare_and_test/bounds.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_subtraction.py index 4b6cc8f71..f6c027118 100644 --- a/src/arch/x86/isa/insts/compare_and_test/bounds.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_subtraction.py @@ -53,8 +53,7 @@ # # Authors: Gabe Black -microcode = "" -#let {{ -# class BOUND(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; +microcode = ''' +# HSUBPS +# HSUBPD +''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/multiplication.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/multiplication.py new file mode 100644 index 000000000..1a53eb27f --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/multiplication.py @@ -0,0 +1,75 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# MULPS +# MULPD +# MULSS + +def macroop MULSD_R_R { + mulfp xmml, xmml, xmmlm +}; + +def macroop MULSD_R_M { + ldfp ufp1, seg, sib, disp + mulfp xmml, xmml, ufp1 +}; + +def macroop MULSD_R_P { + rdip t7 + ldfp ufp1, seg, riprel, disp + mulfp xmml, xmml, ufp1 +}; +''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/reciprocal_estimation.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/reciprocal_estimation.py new file mode 100644 index 000000000..bb1f67f21 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/reciprocal_estimation.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# RCPPS +# RCPSS +''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/reciprocal_square_root.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/reciprocal_square_root.py new file mode 100644 index 000000000..7e2b55b20 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/reciprocal_square_root.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# RSQRTPS +# RSQRTPD +''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/simultaneous_addition_and_subtraction.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/simultaneous_addition_and_subtraction.py new file mode 100644 index 000000000..b1364fa2c --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/simultaneous_addition_and_subtraction.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# ADDSUBPS +# ADDSUBPD +''' diff --git a/src/arch/x86/isa/insts/sse/square_root.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/square_root.py index 473292386..4f67aee88 100644 --- a/src/arch/x86/isa/insts/sse/square_root.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/square_root.py @@ -54,6 +54,10 @@ # Authors: Gabe Black microcode = ''' +# SQRTPS +# SQRTPD +# SQRTSS + def macroop SQRTSD_R_R { sqrtfp xmml, xmml, xmmlm }; diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/subtraction.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/subtraction.py new file mode 100644 index 000000000..4f73fa899 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/subtraction.py @@ -0,0 +1,75 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# SUBPS +# SUBPD +# SUBSS + +def macroop SUBSD_R_R { + subfp xmml, xmml, xmmlm +}; + +def macroop SUBSD_R_M { + ldfp ufp1, seg, sib, disp + subfp xmml, xmml, ufp1 +}; + +def macroop SUBSD_R_P { + rdip t7 + ldfp ufp1, seg, riprel, disp + subfp xmml, xmml, ufp1 +}; +''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/compare/__init__.py b/src/arch/x86/isa/insts/simd128/floating_point/compare/__init__.py new file mode 100644 index 000000000..a119be6e7 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/compare/__init__.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["compare_and_write_mask", + "compare_and_write_minimum_or_maximum", + "compare_and_write_rflags"] + +microcode = ''' +# SSE instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_mask.py b/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_mask.py new file mode 100644 index 000000000..705f64093 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_mask.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# CMPPS +# CMPPD +# CMPSS +# CMPSD +''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_minimum_or_maximum.py b/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_minimum_or_maximum.py new file mode 100644 index 000000000..8ef363333 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_minimum_or_maximum.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# MAXPS +# MAXPD +# MAXSS +# MAXSD +# MINPS +# MINPD +# MINSS +# MINSD +''' diff --git a/src/arch/x86/isa/insts/sse/compare.py b/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_rflags.py index 8721dffa7..e05018495 100644 --- a/src/arch/x86/isa/insts/sse/compare.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_rflags.py @@ -54,6 +54,10 @@ # Authors: Gabe Black microcode = ''' +# COMISS +# COMISD +# UCOMISS + def macroop UCOMISD_R_R { compfp xmml, xmmlm }; diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/__init__.py b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/__init__.py new file mode 100644 index 000000000..880a543f8 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/__init__.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["convert_floating_point_to_floating_point", + "convert_floating_point_to_xmm_integer", + "convert_floating_point_to_mmx_integer", + "convert_floating_point_to_gpr_integer"] + +microcode = ''' +# SSE instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_floating_point.py b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_floating_point.py new file mode 100644 index 000000000..2de33efa2 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_floating_point.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# CVTPS2PD +# CVTPD2PS +# CVTSS2SD +# CVTSD2SS +''' diff --git a/src/arch/x86/isa/insts/sse/convert.py b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_gpr_integer.py index 070df84cc..8d5f4e659 100644 --- a/src/arch/x86/isa/insts/sse/convert.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_gpr_integer.py @@ -54,20 +54,9 @@ # Authors: Gabe Black microcode = ''' -def macroop CVTSI2SD_R_R { - cvtf_i2d xmml, regm -}; - -def macroop CVTSI2SD_R_M { - ld t1, seg, sib, disp - cvtf_i2d xmml, t1 -}; - -def macroop CVTSI2SD_R_P { - rdip t7 - ld t1, seg, riprel, disp - cvtf_i2d xmml, t1 -}; +# CVTSS2SI +# CVTSD2SI +# CVTTSS2SI def macroop CVTTSD2SI_R_R { cvtf_d2i reg, xmmlm diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_mmx_integer.py b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_mmx_integer.py new file mode 100644 index 000000000..af579a46f --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_mmx_integer.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# CVTPS2PI +# CVTPD2PI +# CVTTPS2PI +# CVTTPD2PI +''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_xmm_integer.py b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_xmm_integer.py new file mode 100644 index 000000000..683e2808d --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_xmm_integer.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# CVTPS2DQ +# CVTPD2DQ +# CVTTPS2DQ +# CVTTPD2DQ +''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_reordering/__init__.py b/src/arch/x86/isa/insts/simd128/floating_point/data_reordering/__init__.py new file mode 100644 index 000000000..df528c3f9 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_reordering/__init__.py @@ -0,0 +1,64 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["unpack_and_interleave", + "shuffle"] + +microcode = ''' +# SSE instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_reordering/shuffle.py b/src/arch/x86/isa/insts/simd128/floating_point/data_reordering/shuffle.py new file mode 100644 index 000000000..868d72b06 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_reordering/shuffle.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# SHUFPS +# SHUFPD +''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_reordering/unpack_and_interleave.py b/src/arch/x86/isa/insts/simd128/floating_point/data_reordering/unpack_and_interleave.py new file mode 100644 index 000000000..93112f7d6 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_reordering/unpack_and_interleave.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# UNPCKHPS +# UNPCKHPD +# UNPCKLPS +# UNPCKLPD +''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/__init__.py b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/__init__.py new file mode 100644 index 000000000..a128ffc30 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/__init__.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["move", + "move_with_duplication", + "move_non_temporal", + "move_mask"] + +microcode = ''' +# SSE instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/sse/move.py b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py index c03658c7c..76279fc70 100644 --- a/src/arch/x86/isa/insts/sse/move.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move.py @@ -54,76 +54,92 @@ # Authors: Gabe Black microcode = ''' -def macroop MOVLPD_R_M { +def macroop MOVAPS_R_M { + # Check low address. + ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8 ldfp xmml, seg, sib, disp, dataSize=8 }; -def macroop MOVLPD_R_P { +def macroop MOVAPS_R_P { rdip t7 + # Check low address. + ldfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8 ldfp xmml, seg, riprel, disp, dataSize=8 }; -def macroop MOVLPD_M_R { +def macroop MOVAPS_M_R { + # Check low address. + stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8 stfp xmml, seg, sib, disp, dataSize=8 }; -def macroop MOVLPD_P_R { +def macroop MOVAPS_P_R { rdip t7 + # Check low address. + stfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8 stfp xmml, seg, riprel, disp, dataSize=8 }; -def macroop MOVLPD_R_R { - movfp xmml, xmml, xmmlm, dataSize=8 +def macroop MOVAPS_R_R { + # Check low address. + movfp xmml, xmmlm, dataSize=8 + movfp xmmh, xmmhm, dataSize=8 }; -def macroop MOVSD_R_M { - # Zero xmmh +# MOVAPD +# MOVUPS +# MOVUPD +# MOVHPS +# MOVHPD +# MOVLPS + +def macroop MOVLPD_R_M { ldfp xmml, seg, sib, disp, dataSize=8 }; -def macroop MOVSD_R_P { +def macroop MOVLPD_R_P { rdip t7 - # Zero xmmh ldfp xmml, seg, riprel, disp, dataSize=8 }; -def macroop MOVSD_M_R { +def macroop MOVLPD_M_R { stfp xmml, seg, sib, disp, dataSize=8 }; -def macroop MOVSD_P_R { +def macroop MOVLPD_P_R { rdip t7 stfp xmml, seg, riprel, disp, dataSize=8 }; -def macroop MOVSD_R_R { - movfp xmml, xmml, xmmlm, dataSize=8 +def macroop MOVLPD_R_R { + movfp xmml, xmmlm, dataSize=8 }; -def macroop MOVAPS_R_M { - ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8 +# MOVHLPS +# MOVLHPS +# MOVSS + +def macroop MOVSD_R_M { + # Zero xmmh ldfp xmml, seg, sib, disp, dataSize=8 }; -def macroop MOVAPS_R_P { +def macroop MOVSD_R_P { rdip t7 - ldfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8 + # Zero xmmh ldfp xmml, seg, riprel, disp, dataSize=8 }; -def macroop MOVAPS_M_R { - stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8 +def macroop MOVSD_M_R { stfp xmml, seg, sib, disp, dataSize=8 }; -def macroop MOVAPS_P_R { +def macroop MOVSD_P_R { rdip t7 - stfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8 stfp xmml, seg, riprel, disp, dataSize=8 }; -def macroop MOVAPS_R_R { - movfp xmml, xmml, xmmlm, dataSize=8 - movfp xmmh, xmmh, xmmhm, dataSize=8 +def macroop MOVSD_R_R { + movfp xmml, xmmlm, dataSize=8 }; ''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move_mask.py b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move_mask.py new file mode 100644 index 000000000..abd1c7327 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move_mask.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# MOVMSKPS +# MOVMSKPD +''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move_non_temporal.py b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move_non_temporal.py new file mode 100644 index 000000000..6aacf500d --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move_non_temporal.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# MOVNTPS +# MOVNTPD +''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move_with_duplication.py b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move_with_duplication.py new file mode 100644 index 000000000..096708393 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/move_with_duplication.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# MOVDDUP +# MOVSLDUP +# MOVSHDUP +''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/logical/__init__.py b/src/arch/x86/isa/insts/simd128/floating_point/logical/__init__.py new file mode 100644 index 000000000..7e16f269b --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/logical/__init__.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["andp", + "orp", + "exclusive_or"] + +microcode = ''' +# SSE instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd128/floating_point/logical/andp.py b/src/arch/x86/isa/insts/simd128/floating_point/logical/andp.py new file mode 100644 index 000000000..8d7d3ba25 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/logical/andp.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# ANDPS +# ANDPD +# ANDNPS +# ANDNPD +''' diff --git a/src/arch/x86/isa/insts/sse/logical.py b/src/arch/x86/isa/insts/simd128/floating_point/logical/exclusive_or.py index a2dbec40a..974771e98 100644 --- a/src/arch/x86/isa/insts/sse/logical.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/logical/exclusive_or.py @@ -54,6 +54,8 @@ # Authors: Gabe Black microcode = ''' +# XORPS + def macroop XORPD_R_R { xorfp xmml, xmml, xmmlm xorfp xmmh, xmmh, xmmhm diff --git a/src/arch/x86/isa/insts/simd128/floating_point/logical/orp.py b/src/arch/x86/isa/insts/simd128/floating_point/logical/orp.py new file mode 100644 index 000000000..fba71c899 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/floating_point/logical/orp.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# ORPS +# ORPD +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/__init__.py b/src/arch/x86/isa/insts/simd128/integer/__init__.py new file mode 100644 index 000000000..4abb798d3 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/__init__.py @@ -0,0 +1,70 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["data_transfer", + "data_conversion", + "data_reordering", + "arithmetic", + "shift", + "compare", + "logical", + "save_and_restore_state"] + +microcode = ''' +# 128 bit multimedia and scientific instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd128/integer/arithmetic/__init__.py b/src/arch/x86/isa/insts/simd128/integer/arithmetic/__init__.py new file mode 100644 index 000000000..70aa56b9d --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/__init__.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["addition", + "subtraction", + "multiplication", + "multiply_add", + "average", + "sum_of_absolute_differences"] + +microcode = ''' +# 128 bit multimedia and scientific instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd128/integer/arithmetic/addition.py b/src/arch/x86/isa/insts/simd128/integer/arithmetic/addition.py new file mode 100644 index 000000000..235a4fc7b --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/addition.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PADDB +# PADDW +# PADDD +# PADDQ +# PADDSB +# PADDSW +# PADDUSB +# PADDUSW +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/arithmetic/average.py b/src/arch/x86/isa/insts/simd128/integer/arithmetic/average.py new file mode 100644 index 000000000..9bda3371f --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/average.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PAVGB +# PAVGW +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py b/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py new file mode 100644 index 000000000..3e7345a9f --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PMULHW +# PMULLW +# PMULHUW +# PMULUDQ +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiply_add.py b/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiply_add.py new file mode 100644 index 000000000..40b38867b --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiply_add.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PMADDWD +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/arithmetic/subtraction.py b/src/arch/x86/isa/insts/simd128/integer/arithmetic/subtraction.py new file mode 100644 index 000000000..44781eb55 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/subtraction.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PSUBB +# PSUBW +# PSUBD +# PSUBQ +# PSUBSB +# PSUBSW +# PSUBUSB +# PSUBUSW +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/arithmetic/sum_of_absolute_differences.py b/src/arch/x86/isa/insts/simd128/integer/arithmetic/sum_of_absolute_differences.py new file mode 100644 index 000000000..df1ca2301 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/sum_of_absolute_differences.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PSADBW +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/compare/__init__.py b/src/arch/x86/isa/insts/simd128/integer/compare/__init__.py new file mode 100644 index 000000000..91a6944b9 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/compare/__init__.py @@ -0,0 +1,64 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["compare_and_write_mask", + "compare_and_write_minimum_or_maximum"] + +microcode = ''' +# 128 bit multimedia and scientific instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_mask.py b/src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_mask.py new file mode 100644 index 000000000..59380c6a7 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_mask.py @@ -0,0 +1,63 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PCMPEQB +# PCMPEQW +# PCMPEQD +# PCMPGTB +# PCMPGTW +# PCMPGTD +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_minimum_or_maximum.py b/src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_minimum_or_maximum.py new file mode 100644 index 000000000..79b1aca4c --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_minimum_or_maximum.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PMAXUB +# PMINUB +# PMAXSW +# PMINSW +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/data_conversion/__init__.py b/src/arch/x86/isa/insts/simd128/integer/data_conversion/__init__.py new file mode 100644 index 000000000..ce7585ac4 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/data_conversion/__init__.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["convert_integer_to_floating_point", + "convert_mmx_integer_to_floating_point", + "convert_gpr_integer_to_floating_point"] + +microcode = ''' +# 128 bit multimedia and scientific conversion instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py b/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py new file mode 100644 index 000000000..b667055dc --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py @@ -0,0 +1,73 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# CVTSI2SS + +def macroop CVTSI2SD_R_R { + cvtf_i2d xmml, regm +}; + +def macroop CVTSI2SD_R_M { + ld t1, seg, sib, disp + cvtf_i2d xmml, t1 +}; + +def macroop CVTSI2SD_R_P { + rdip t7 + ld t1, seg, riprel, disp + cvtf_i2d xmml, t1 +}; +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_integer_to_floating_point.py b/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_integer_to_floating_point.py new file mode 100644 index 000000000..41e8549b5 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_integer_to_floating_point.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# CVTDQ2PS +# CVTDQ2PD +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_mmx_integer_to_floating_point.py b/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_mmx_integer_to_floating_point.py new file mode 100644 index 000000000..aeaea26cd --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_mmx_integer_to_floating_point.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# CVTPI2PS +# CVTPI2PD +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/data_reordering/__init__.py b/src/arch/x86/isa/insts/simd128/integer/data_reordering/__init__.py new file mode 100644 index 000000000..997da31c4 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/data_reordering/__init__.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["pack_with_saturation", + "unpack_and_interleave", + "extract_and_insert", + "shuffle"] + +microcode = ''' +# 128 bit multimedia and scientific instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd128/integer/data_reordering/extract_and_insert.py b/src/arch/x86/isa/insts/simd128/integer/data_reordering/extract_and_insert.py new file mode 100644 index 000000000..80f7a3e71 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/data_reordering/extract_and_insert.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PEXTRW +# PINSRW +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/data_reordering/pack_with_saturation.py b/src/arch/x86/isa/insts/simd128/integer/data_reordering/pack_with_saturation.py new file mode 100644 index 000000000..859d2bc7e --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/data_reordering/pack_with_saturation.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PACKSSDW +# PACKSSWB +# PACKUSWB +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/data_reordering/shuffle.py b/src/arch/x86/isa/insts/simd128/integer/data_reordering/shuffle.py new file mode 100644 index 000000000..9f66c3f05 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/data_reordering/shuffle.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PSHUFD +# PSHUFHW +# PSHUFLW +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/data_reordering/unpack_and_interleave.py b/src/arch/x86/isa/insts/simd128/integer/data_reordering/unpack_and_interleave.py new file mode 100644 index 000000000..e8c22ea9f --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/data_reordering/unpack_and_interleave.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PUNPCKHBW +# PUNPCKHWD +# PUNPCKHDQ +# PUNPCKHQDQ +# PUNPCKLBW +# PUNPCKLWD +# PUNPCKLDQ +# PUNPCKLQDQ +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/data_transfer/__init__.py b/src/arch/x86/isa/insts/simd128/integer/data_transfer/__init__.py new file mode 100644 index 000000000..bb51fee6b --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/data_transfer/__init__.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["move", + "move_non_temporal", + "move_mask"] + +microcode = ''' +# 128 bit multimedia and scientific data transfer instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py b/src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py new file mode 100644 index 000000000..4bee18c19 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py @@ -0,0 +1,64 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# MOVD +# MOVQ +# MOVDQA +# MOVDQU +# MOVDQ2Q +# MOVQ2DQ +# LDDQU +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/data_transfer/move_mask.py b/src/arch/x86/isa/insts/simd128/integer/data_transfer/move_mask.py new file mode 100644 index 000000000..558391c6a --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/data_transfer/move_mask.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PMOVMSKB +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/data_transfer/move_non_temporal.py b/src/arch/x86/isa/insts/simd128/integer/data_transfer/move_non_temporal.py new file mode 100644 index 000000000..413dddb84 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/data_transfer/move_non_temporal.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# MOVNTDQ +# MASKMOVDQU +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/logical/__init__.py b/src/arch/x86/isa/insts/simd128/integer/logical/__init__.py new file mode 100644 index 000000000..3db9eb04d --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/logical/__init__.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["pand", + "por", + "exclusive_or"] + +microcode = ''' +# 128 bit multimedia and scientific instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd128/integer/logical/exclusive_or.py b/src/arch/x86/isa/insts/simd128/integer/logical/exclusive_or.py new file mode 100644 index 000000000..336796e23 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/logical/exclusive_or.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PXOR +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/logical/pand.py b/src/arch/x86/isa/insts/simd128/integer/logical/pand.py new file mode 100644 index 000000000..055b7c5f6 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/logical/pand.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PAND +# PANDN +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/logical/por.py b/src/arch/x86/isa/insts/simd128/integer/logical/por.py new file mode 100644 index 000000000..addb28a60 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/logical/por.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# POR +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/__init__.py b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/__init__.py new file mode 100644 index 000000000..b87f25d6c --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/__init__.py @@ -0,0 +1,64 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["save_and_restore_state", + "save_and_restore_control_and_status"] + +microcode = ''' +# 128 bit multimedia and scientific instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py new file mode 100644 index 000000000..687391b47 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# STMXCSR +# LDMXCSR +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py new file mode 100644 index 000000000..30ab5fcb8 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FXSAVE +# FXRESTORE +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/__init__.py b/src/arch/x86/isa/insts/simd128/integer/shift/__init__.py new file mode 100644 index 000000000..2cd7bb423 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/shift/__init__.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["left_logical_shift", + "right_logical_shift", + "right_arithmetic_shift"] + +microcode = ''' +# 128 bit multimedia and scientific instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py new file mode 100644 index 000000000..18d6feb24 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PSLLW +# PSLLD +# PSLLQ +# PSLLDQ +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py new file mode 100644 index 000000000..63750e292 --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PSRAW +# PSRAD +''' diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py new file mode 100644 index 000000000..fc6fb180b --- /dev/null +++ b/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PSRLW +# PSRLD +# PSRLQ +# PSRLDQ +''' diff --git a/src/arch/x86/isa/insts/simd64/__init__.py b/src/arch/x86/isa/insts/simd64/__init__.py new file mode 100644 index 000000000..442c99e66 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/__init__.py @@ -0,0 +1,64 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["integer", + "floating_point"] + +microcode = ''' +# 64 bit multimedia instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd64/floating_point/__init__.py b/src/arch/x86/isa/insts/simd64/floating_point/__init__.py new file mode 100644 index 000000000..baa9678c3 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/floating_point/__init__.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["data_conversion", + "arithmetic", + "compare"] + +microcode = ''' +# 64 bit multimedia instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/__init__.py b/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/__init__.py new file mode 100644 index 000000000..9f5f7160a --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/__init__.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["addition", + "subtraction", + "multiplication", + "accumulation", + "reciprocal_estimation", + "reciprocal_square_root"] + +microcode = ''' +# 64 bit multimedia instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/accumulation.py b/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/accumulation.py new file mode 100644 index 000000000..8de532b25 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/accumulation.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PFACC +# PFNACC +# PFPNACC +''' diff --git a/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/addition.py b/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/addition.py new file mode 100644 index 000000000..26e7041ca --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/addition.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PFADD +''' diff --git a/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/multiplication.py b/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/multiplication.py new file mode 100644 index 000000000..54047ec7c --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/multiplication.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PFMUL +''' diff --git a/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/reciprocal_estimation.py b/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/reciprocal_estimation.py new file mode 100644 index 000000000..8a7910864 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/reciprocal_estimation.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PFRCP +# PFRCPIT1 +# PFRCPIT2 +''' diff --git a/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/reciprocal_square_root.py b/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/reciprocal_square_root.py new file mode 100644 index 000000000..0e207c559 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/reciprocal_square_root.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PFRSQRT +# PFRSQIT1 +''' diff --git a/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/subtraction.py b/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/subtraction.py new file mode 100644 index 000000000..6e4c1804d --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/floating_point/arithmetic/subtraction.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PFSUB +# PFSUBR +''' diff --git a/src/arch/x86/isa/insts/simd64/floating_point/compare/__init__.py b/src/arch/x86/isa/insts/simd64/floating_point/compare/__init__.py new file mode 100644 index 000000000..2a908d228 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/floating_point/compare/__init__.py @@ -0,0 +1,64 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["compare_and_write_mask", + "compare_and_write_minimum_or_maximum"] + +microcode = ''' +# 64 bit multimedia instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd64/floating_point/compare/compare_and_write_mask.py b/src/arch/x86/isa/insts/simd64/floating_point/compare/compare_and_write_mask.py new file mode 100644 index 000000000..0601acb40 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/floating_point/compare/compare_and_write_mask.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PFCMPEQ +# PFCMPGT +# PFCMPGE +''' diff --git a/src/arch/x86/isa/insts/simd64/floating_point/compare/compare_and_write_minimum_or_maximum.py b/src/arch/x86/isa/insts/simd64/floating_point/compare/compare_and_write_minimum_or_maximum.py new file mode 100644 index 000000000..c304346f1 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/floating_point/compare/compare_and_write_minimum_or_maximum.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PFMAX +# PFMIN +''' diff --git a/src/arch/x86/isa/insts/simd64/floating_point/data_conversion.py b/src/arch/x86/isa/insts/simd64/floating_point/data_conversion.py new file mode 100644 index 000000000..6c942065d --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/floating_point/data_conversion.py @@ -0,0 +1,63 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# CVTPS2PI +# CVTTPS2PI +# CVTPD2PI +# CVTTPD2PI +# PF2IW +# PF2ID +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/__init__.py b/src/arch/x86/isa/insts/simd64/integer/__init__.py new file mode 100644 index 000000000..46ab57476 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/__init__.py @@ -0,0 +1,71 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["exit_media_state", + "data_transfer", + "data_conversion", + "data_reordering", + "arithmetic", + "shift", + "compare", + "logical", + "save_and_restore_state"] + +microcode = ''' +# 64 bit multimedia instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd64/integer/arithmetic/__init__.py b/src/arch/x86/isa/insts/simd64/integer/arithmetic/__init__.py new file mode 100644 index 000000000..f8474b9e5 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/arithmetic/__init__.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["addition", + "subtraction", + "multiplication", + "multiply_add", + "average", + "sum_of_absolute_differences"] + +microcode = ''' +# 64 bit multimedia instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd64/integer/arithmetic/addition.py b/src/arch/x86/isa/insts/simd64/integer/arithmetic/addition.py new file mode 100644 index 000000000..235a4fc7b --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/arithmetic/addition.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PADDB +# PADDW +# PADDD +# PADDQ +# PADDSB +# PADDSW +# PADDUSB +# PADDUSW +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/arithmetic/average.py b/src/arch/x86/isa/insts/simd64/integer/arithmetic/average.py new file mode 100644 index 000000000..af1b39097 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/arithmetic/average.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PAVGB +# PAVGW +# PAVGUSB +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiplication.py b/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiplication.py new file mode 100644 index 000000000..8382bc439 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiplication.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PMULHW +# PMULLW +# PMULHRW +# PMULHUW +# PMULUDQ +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiply_add.py b/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiply_add.py new file mode 100644 index 000000000..40b38867b --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiply_add.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PMADDWD +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/arithmetic/subtraction.py b/src/arch/x86/isa/insts/simd64/integer/arithmetic/subtraction.py new file mode 100644 index 000000000..44781eb55 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/arithmetic/subtraction.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PSUBB +# PSUBW +# PSUBD +# PSUBQ +# PSUBSB +# PSUBSW +# PSUBUSB +# PSUBUSW +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/arithmetic/sum_of_absolute_differences.py b/src/arch/x86/isa/insts/simd64/integer/arithmetic/sum_of_absolute_differences.py new file mode 100644 index 000000000..df1ca2301 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/arithmetic/sum_of_absolute_differences.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PSADBW +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/compare/__init__.py b/src/arch/x86/isa/insts/simd64/integer/compare/__init__.py new file mode 100644 index 000000000..2a908d228 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/compare/__init__.py @@ -0,0 +1,64 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["compare_and_write_mask", + "compare_and_write_minimum_or_maximum"] + +microcode = ''' +# 64 bit multimedia instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd64/integer/compare/compare_and_write_mask.py b/src/arch/x86/isa/insts/simd64/integer/compare/compare_and_write_mask.py new file mode 100644 index 000000000..59380c6a7 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/compare/compare_and_write_mask.py @@ -0,0 +1,63 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PCMPEQB +# PCMPEQW +# PCMPEQD +# PCMPGTB +# PCMPGTW +# PCMPGTD +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/compare/compare_and_write_minimum_or_maximum.py b/src/arch/x86/isa/insts/simd64/integer/compare/compare_and_write_minimum_or_maximum.py new file mode 100644 index 000000000..79b1aca4c --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/compare/compare_and_write_minimum_or_maximum.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PMAXUB +# PMINUB +# PMAXSW +# PMINSW +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/data_conversion.py b/src/arch/x86/isa/insts/simd64/integer/data_conversion.py new file mode 100644 index 000000000..f41049171 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/data_conversion.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# CVTPI2PS +# CVTPI2PD +# PI2FW +# PI2FD +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/data_reordering/__init__.py b/src/arch/x86/isa/insts/simd64/integer/data_reordering/__init__.py new file mode 100644 index 000000000..adb95deb2 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/data_reordering/__init__.py @@ -0,0 +1,66 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["pack_with_saturation", + "unpack_and_interleave", + "extract_and_insert", + "shuffle_and_swap"] + +microcode = ''' +# 64 bit multimedia instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd64/integer/data_reordering/extract_and_insert.py b/src/arch/x86/isa/insts/simd64/integer/data_reordering/extract_and_insert.py new file mode 100644 index 000000000..80f7a3e71 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/data_reordering/extract_and_insert.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PEXTRW +# PINSRW +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/data_reordering/pack_with_saturation.py b/src/arch/x86/isa/insts/simd64/integer/data_reordering/pack_with_saturation.py new file mode 100644 index 000000000..859d2bc7e --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/data_reordering/pack_with_saturation.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PACKSSDW +# PACKSSWB +# PACKUSWB +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/data_reordering/shuffle_and_swap.py b/src/arch/x86/isa/insts/simd64/integer/data_reordering/shuffle_and_swap.py new file mode 100644 index 000000000..8f95f0f48 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/data_reordering/shuffle_and_swap.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PSHUFW +# PSWAPD +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/data_reordering/unpack_and_interleave.py b/src/arch/x86/isa/insts/simd64/integer/data_reordering/unpack_and_interleave.py new file mode 100644 index 000000000..1f4c617dd --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/data_reordering/unpack_and_interleave.py @@ -0,0 +1,63 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PUNPCKHBW +# PUNPCKHWD +# PUNPCKHDQ +# PUNPCKLBW +# PUNPCKLWD +# PUNPCKLDQ +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/data_transfer/__init__.py b/src/arch/x86/isa/insts/simd64/integer/data_transfer/__init__.py new file mode 100644 index 000000000..43e11cf02 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/data_transfer/__init__.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["move", + "move_non_temporal", + "move_mask"] + +microcode = ''' +# 64 bit multimedia instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py new file mode 100644 index 000000000..e60273022 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# MOVD +# MOVQ +# MOVDQ2Q +# MOVQ2DQ +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_mask.py b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_mask.py new file mode 100644 index 000000000..558391c6a --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_mask.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PMOVMSKB +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_non_temporal.py b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_non_temporal.py new file mode 100644 index 000000000..edd55d35a --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/data_transfer/move_non_temporal.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# MOVNTQ +# MASKMOVQ +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/exit_media_state.py b/src/arch/x86/isa/insts/simd64/integer/exit_media_state.py new file mode 100644 index 000000000..139532564 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/exit_media_state.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# EMMS +# FEMMS +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/logical/__init__.py b/src/arch/x86/isa/insts/simd64/integer/logical/__init__.py new file mode 100644 index 000000000..d1ea4948e --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/logical/__init__.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["pand", + "por", + "exclusive_or"] + +microcode = ''' +# 64 bit multimedia instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd64/integer/logical/exclusive_or.py b/src/arch/x86/isa/insts/simd64/integer/logical/exclusive_or.py new file mode 100644 index 000000000..336796e23 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/logical/exclusive_or.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PXOR +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/logical/pand.py b/src/arch/x86/isa/insts/simd64/integer/logical/pand.py new file mode 100644 index 000000000..055b7c5f6 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/logical/pand.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PAND +# PANDN +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/logical/por.py b/src/arch/x86/isa/insts/simd64/integer/logical/por.py new file mode 100644 index 000000000..addb28a60 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/logical/por.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# POR +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/save_and_restore_state.py b/src/arch/x86/isa/insts/simd64/integer/save_and_restore_state.py new file mode 100644 index 000000000..595147c25 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/save_and_restore_state.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FSAVE +# FNSAVE +# FRSTOR +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/shift/__init__.py b/src/arch/x86/isa/insts/simd64/integer/shift/__init__.py new file mode 100644 index 000000000..a9bc519f9 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/shift/__init__.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["left_logical_shift", + "right_logical_shift", + "right_arithmetic_shift"] + +microcode = ''' +# 64 bit multimedia instructions +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/simd64/integer/shift/left_logical_shift.py b/src/arch/x86/isa/insts/simd64/integer/shift/left_logical_shift.py new file mode 100644 index 000000000..4687cab8d --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/shift/left_logical_shift.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PSLLW +# PSLLD +# PSLLQ +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/shift/right_arithmetic_shift.py b/src/arch/x86/isa/insts/simd64/integer/shift/right_arithmetic_shift.py new file mode 100644 index 000000000..63750e292 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/shift/right_arithmetic_shift.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PSRAW +# PSRAD +''' diff --git a/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py b/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py new file mode 100644 index 000000000..1f870dc32 --- /dev/null +++ b/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# PSRLW +# PSRLD +# PSRLQ +''' diff --git a/src/arch/x86/isa/insts/string/load_string.py b/src/arch/x86/isa/insts/string/load_string.py deleted file mode 100644 index 0f749a273..000000000 --- a/src/arch/x86/isa/insts/string/load_string.py +++ /dev/null @@ -1,68 +0,0 @@ -# Copyright (c) 2007 The Hewlett-Packard Development Company -# All rights reserved. -# -# Redistribution and use of this software in source and binary forms, -# with or without modification, are permitted provided that the -# following conditions are met: -# -# The software must be used only for Non-Commercial Use which means any -# use which is NOT directed to receiving any direct monetary -# compensation for, or commercial advantage from such use. Illustrative -# examples of non-commercial use are academic research, personal study, -# teaching, education and corporate research & development. -# Illustrative examples of commercial use are distributing products for -# commercial advantage and providing services using the software for -# commercial advantage. -# -# If you wish to use this software or functionality therein that may be -# covered by patents for commercial use, please contact: -# Director of Intellectual Property Licensing -# Office of Strategy and Technology -# Hewlett-Packard Company -# 1501 Page Mill Road -# Palo Alto, California 94304 -# -# Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. Redistributions -# in binary form must reproduce the above copyright notice, this list of -# conditions and the following disclaimer in the documentation and/or -# other materials provided with the distribution. Neither the name of -# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. No right of -# sublicense is granted herewith. Derivatives of the software and -# output created using the software may be prepared, but only for -# Non-Commercial Uses. Derivatives of the software may be shared with -# others provided: (i) the others agree to abide by the list of -# conditions herein which includes the Non-Commercial Use restrictions; -# and (ii) such Derivatives of the software include the above copyright -# notice to acknowledge the contribution from this software where -# applicable, this list of conditions and the disclaimer below. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Gabe Black - -microcode = "" -#let {{ -# class LODS(Inst): -# "GenFault ${new UnimpInstFault}" -# class LODSB(Inst): -# "GenFault ${new UnimpInstFault}" -# class LODSW(Inst): -# "GenFault ${new UnimpInstFault}" -# class LODSD(Inst): -# "GenFault ${new UnimpInstFault}" -# class LODSQ(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; diff --git a/src/arch/x86/isa/insts/string/move_string.py b/src/arch/x86/isa/insts/string/move_string.py deleted file mode 100644 index 0a855b384..000000000 --- a/src/arch/x86/isa/insts/string/move_string.py +++ /dev/null @@ -1,68 +0,0 @@ -# Copyright (c) 2007 The Hewlett-Packard Development Company -# All rights reserved. -# -# Redistribution and use of this software in source and binary forms, -# with or without modification, are permitted provided that the -# following conditions are met: -# -# The software must be used only for Non-Commercial Use which means any -# use which is NOT directed to receiving any direct monetary -# compensation for, or commercial advantage from such use. Illustrative -# examples of non-commercial use are academic research, personal study, -# teaching, education and corporate research & development. -# Illustrative examples of commercial use are distributing products for -# commercial advantage and providing services using the software for -# commercial advantage. -# -# If you wish to use this software or functionality therein that may be -# covered by patents for commercial use, please contact: -# Director of Intellectual Property Licensing -# Office of Strategy and Technology -# Hewlett-Packard Company -# 1501 Page Mill Road -# Palo Alto, California 94304 -# -# Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. Redistributions -# in binary form must reproduce the above copyright notice, this list of -# conditions and the following disclaimer in the documentation and/or -# other materials provided with the distribution. Neither the name of -# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. No right of -# sublicense is granted herewith. Derivatives of the software and -# output created using the software may be prepared, but only for -# Non-Commercial Uses. Derivatives of the software may be shared with -# others provided: (i) the others agree to abide by the list of -# conditions herein which includes the Non-Commercial Use restrictions; -# and (ii) such Derivatives of the software include the above copyright -# notice to acknowledge the contribution from this software where -# applicable, this list of conditions and the disclaimer below. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Gabe Black - -microcode = "" -#let {{ -# class MOVS(Inst): -# "GenFault ${new UnimpInstFault}" -# class MOVSB(Inst): -# "GenFault ${new UnimpInstFault}" -# class MOVSW(Inst): -# "GenFault ${new UnimpInstFault}" -# class MOVSD(Inst): -# "GenFault ${new UnimpInstFault}" -# class MOVSQ(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; diff --git a/src/arch/x86/isa/insts/string/store_string.py b/src/arch/x86/isa/insts/string/store_string.py deleted file mode 100644 index 08a126c1f..000000000 --- a/src/arch/x86/isa/insts/string/store_string.py +++ /dev/null @@ -1,68 +0,0 @@ -# Copyright (c) 2007 The Hewlett-Packard Development Company -# All rights reserved. -# -# Redistribution and use of this software in source and binary forms, -# with or without modification, are permitted provided that the -# following conditions are met: -# -# The software must be used only for Non-Commercial Use which means any -# use which is NOT directed to receiving any direct monetary -# compensation for, or commercial advantage from such use. Illustrative -# examples of non-commercial use are academic research, personal study, -# teaching, education and corporate research & development. -# Illustrative examples of commercial use are distributing products for -# commercial advantage and providing services using the software for -# commercial advantage. -# -# If you wish to use this software or functionality therein that may be -# covered by patents for commercial use, please contact: -# Director of Intellectual Property Licensing -# Office of Strategy and Technology -# Hewlett-Packard Company -# 1501 Page Mill Road -# Palo Alto, California 94304 -# -# Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. Redistributions -# in binary form must reproduce the above copyright notice, this list of -# conditions and the following disclaimer in the documentation and/or -# other materials provided with the distribution. Neither the name of -# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. No right of -# sublicense is granted herewith. Derivatives of the software and -# output created using the software may be prepared, but only for -# Non-Commercial Uses. Derivatives of the software may be shared with -# others provided: (i) the others agree to abide by the list of -# conditions herein which includes the Non-Commercial Use restrictions; -# and (ii) such Derivatives of the software include the above copyright -# notice to acknowledge the contribution from this software where -# applicable, this list of conditions and the disclaimer below. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Gabe Black - -microcode = "" -#let {{ -# class STOS(Inst): -# "Add 0 0 0" -# class STOSB(Inst): -# "Add 0 0 0" -# class STOSW(Inst): -# "Add 0 0 0" -# class STOSD(Inst): -# "Add 0 0 0" -# class STOSQ(Inst): -# "Add 0 0 0" -#}}; diff --git a/src/arch/x86/isa/insts/system/__init__.py b/src/arch/x86/isa/insts/system/__init__.py index 72e3bdf0a..422438b1c 100644 --- a/src/arch/x86/isa/insts/system/__init__.py +++ b/src/arch/x86/isa/insts/system/__init__.py @@ -53,7 +53,9 @@ # # Authors: Gabe Black -categories = ["undefined_operation"] +categories = ["halt", + "undefined_operation", + "msrs"] microcode = "" for category in categories: diff --git a/src/arch/x86/isa/insts/system/halt.py b/src/arch/x86/isa/insts/system/halt.py new file mode 100644 index 000000000..d1284e81b --- /dev/null +++ b/src/arch/x86/isa/insts/system/halt.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop HLT { + halt +}; +''' diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py new file mode 100644 index 000000000..ea576510b --- /dev/null +++ b/src/arch/x86/isa/insts/system/msrs.py @@ -0,0 +1,74 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop WRMSR +{ + limm t1, "IntAddrPrefixMSR >> 3" + ld t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4 + mov rax, rax, t2, dataSize=4 + srli t2, t2, 32, dataSize=8 + mov rdx, rdx, t2, dataSize=4 +}; + +def macroop RDMSR +{ + limm t1, "IntAddrPrefixMSR >> 3" + mov t2, t2, rdx, dataSize=4 + slli t2, t2, 32, dataSize=8 + mov t2, t2, rax, dataSize=4 + st t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4 +}; +''' diff --git a/src/arch/x86/isa/insts/system/undefined_operation.py b/src/arch/x86/isa/insts/system/undefined_operation.py index e5544b6e7..9f129522b 100644 --- a/src/arch/x86/isa/insts/system/undefined_operation.py +++ b/src/arch/x86/isa/insts/system/undefined_operation.py @@ -56,6 +56,6 @@ microcode = ''' def macroop UD2 { - fault "new X86Fault" + fault "new InvalidOpcode()" }; ''' diff --git a/src/arch/x86/isa/insts/x87/__init__.py b/src/arch/x86/isa/insts/x87/__init__.py new file mode 100644 index 000000000..d8fa67b46 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/__init__.py @@ -0,0 +1,70 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["data_transfer_and_conversion", + "load_constants", + "arithmetic", + "transcendental_functions", + "compare_and_test", + "stack_management", + "no_operation", + "control"] + +microcode = ''' +# X86 microcode +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/x87/arithmetic/__init__.py b/src/arch/x86/isa/insts/x87/arithmetic/__init__.py new file mode 100644 index 000000000..986a267c1 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/arithmetic/__init__.py @@ -0,0 +1,70 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["addition", + "subtraction", + "multiplication", + "division", + "change_sign", + "round", + "partial_remainder", + "square_root"] + +microcode = ''' +# X86 microcode +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/x87/arithmetic/addition.py b/src/arch/x86/isa/insts/x87/arithmetic/addition.py new file mode 100644 index 000000000..cd58cd216 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/arithmetic/addition.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FADD +# FADDP +# FIADD +''' diff --git a/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py b/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py new file mode 100644 index 000000000..52afd45f4 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/arithmetic/change_sign.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FABS +# FCHS +''' diff --git a/src/arch/x86/isa/insts/x87/arithmetic/division.py b/src/arch/x86/isa/insts/x87/arithmetic/division.py new file mode 100644 index 000000000..6c365f77d --- /dev/null +++ b/src/arch/x86/isa/insts/x87/arithmetic/division.py @@ -0,0 +1,63 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FDIV +# FDIVP +# FIDIV +# FDIVR +# FDIVRP +# FIDIVR +''' diff --git a/src/arch/x86/isa/insts/x87/arithmetic/multiplication.py b/src/arch/x86/isa/insts/x87/arithmetic/multiplication.py new file mode 100644 index 000000000..aea9bde73 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/arithmetic/multiplication.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FMUL +# FMULP +# FIMUL +''' diff --git a/src/arch/x86/isa/insts/x87/arithmetic/partial_remainder.py b/src/arch/x86/isa/insts/x87/arithmetic/partial_remainder.py new file mode 100644 index 000000000..a5ee85fa6 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/arithmetic/partial_remainder.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FPREM +# FPREM1 +''' diff --git a/src/arch/x86/isa/insts/x87/arithmetic/round.py b/src/arch/x86/isa/insts/x87/arithmetic/round.py new file mode 100644 index 000000000..7824cbe7b --- /dev/null +++ b/src/arch/x86/isa/insts/x87/arithmetic/round.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FRNDINT +''' diff --git a/src/arch/x86/isa/insts/x87/arithmetic/square_root.py b/src/arch/x86/isa/insts/x87/arithmetic/square_root.py new file mode 100644 index 000000000..01f23e2a2 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/arithmetic/square_root.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FSQRT +''' diff --git a/src/arch/x86/isa/insts/x87/arithmetic/subtraction.py b/src/arch/x86/isa/insts/x87/arithmetic/subtraction.py new file mode 100644 index 000000000..06008e79b --- /dev/null +++ b/src/arch/x86/isa/insts/x87/arithmetic/subtraction.py @@ -0,0 +1,63 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FSUB +# FSUBP +# FISUB +# FSUBR +# FSUBRP +# FISUBR +''' diff --git a/src/arch/x86/isa/insts/x87/compare_and_test/__init__.py b/src/arch/x86/isa/insts/x87/compare_and_test/__init__.py new file mode 100644 index 000000000..d77ff8635 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/compare_and_test/__init__.py @@ -0,0 +1,67 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["floating_point_ordered_compare", + "floating_point_unordered_compare", + "integer_compare", + "test", + "classify"] + +microcode = ''' +# X86 microcode +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/x87/compare_and_test/classify.py b/src/arch/x86/isa/insts/x87/compare_and_test/classify.py new file mode 100644 index 000000000..61e1c36b4 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/compare_and_test/classify.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FXAM +''' diff --git a/src/arch/x86/isa/insts/x87/compare_and_test/floating_point_ordered_compare.py b/src/arch/x86/isa/insts/x87/compare_and_test/floating_point_ordered_compare.py new file mode 100644 index 000000000..d75b6a4ed --- /dev/null +++ b/src/arch/x86/isa/insts/x87/compare_and_test/floating_point_ordered_compare.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FCOM +# FCOMP +# FCOMPP +# FCOMI +# FCOMIP +''' diff --git a/src/arch/x86/isa/insts/x87/compare_and_test/floating_point_unordered_compare.py b/src/arch/x86/isa/insts/x87/compare_and_test/floating_point_unordered_compare.py new file mode 100644 index 000000000..50abaa57d --- /dev/null +++ b/src/arch/x86/isa/insts/x87/compare_and_test/floating_point_unordered_compare.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FUCOM +# FUCOMP +# FUCOMPP +# FUCOMI +# FUCOMIP +''' diff --git a/src/arch/x86/isa/insts/x87/compare_and_test/integer_compare.py b/src/arch/x86/isa/insts/x87/compare_and_test/integer_compare.py new file mode 100644 index 000000000..476c7b2cc --- /dev/null +++ b/src/arch/x86/isa/insts/x87/compare_and_test/integer_compare.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FICOM +# FICOMP +''' diff --git a/src/arch/x86/isa/insts/x87/compare_and_test/test.py b/src/arch/x86/isa/insts/x87/compare_and_test/test.py new file mode 100644 index 000000000..17a8e5c9d --- /dev/null +++ b/src/arch/x86/isa/insts/x87/compare_and_test/test.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FTST +''' diff --git a/src/arch/x86/isa/insts/x87/control/__init__.py b/src/arch/x86/isa/insts/x87/control/__init__.py new file mode 100644 index 000000000..83bb78eaa --- /dev/null +++ b/src/arch/x86/isa/insts/x87/control/__init__.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["initialize", + "wait_for_exceptions", + "clear_exceptions", + "save_and_restore_x87_control_word", + "save_x87_status_word", + "save_and_restore_x87_environment"] + +microcode = ''' +# X86 microcode +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/x87/control/clear_exceptions.py b/src/arch/x86/isa/insts/x87/control/clear_exceptions.py new file mode 100644 index 000000000..da64cf640 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/control/clear_exceptions.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FCLEX +# FNCLEX +''' diff --git a/src/arch/x86/isa/insts/x87/control/initialize.py b/src/arch/x86/isa/insts/x87/control/initialize.py new file mode 100644 index 000000000..6b75131b5 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/control/initialize.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FINIT +# FNINIT +''' diff --git a/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_control_word.py b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_control_word.py new file mode 100644 index 000000000..593862163 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_control_word.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FLDCW +# FSTCW +# FNSTCW +''' diff --git a/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py new file mode 100644 index 000000000..95f8a3640 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FLDENV +# FNSTENV +# FSTENV +''' diff --git a/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py b/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py new file mode 100644 index 000000000..792f3b955 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FSTSW +# FNSTSW +''' diff --git a/src/arch/x86/isa/insts/x87/control/wait_for_exceptions.py b/src/arch/x86/isa/insts/x87/control/wait_for_exceptions.py new file mode 100644 index 000000000..8569ef9f1 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/control/wait_for_exceptions.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FWAIT +''' diff --git a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/__init__.py b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/__init__.py new file mode 100644 index 000000000..b1ec33c0c --- /dev/null +++ b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/__init__.py @@ -0,0 +1,68 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["load_or_store_floating_point", + "convert_and_load_or_store_integer", + "convert_and_load_or_store_bcd", + "conditional_move", + "exchange", + "extract"] + +microcode = ''' +# X86 microcode +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/conditional_move.py b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/conditional_move.py new file mode 100644 index 000000000..1231f8eaf --- /dev/null +++ b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/conditional_move.py @@ -0,0 +1,65 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FCMOVB +# FCMOVBE +# FCMOVE +# FCMOVNB +# FCMOVNBE +# FCMOVNE +# FCMOVNU +# FCMOVU +''' diff --git a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/convert_and_load_or_store_bcd.py b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/convert_and_load_or_store_bcd.py new file mode 100644 index 000000000..f346ce568 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/convert_and_load_or_store_bcd.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FBLD +# FBSTP +''' diff --git a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/convert_and_load_or_store_integer.py b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/convert_and_load_or_store_integer.py new file mode 100644 index 000000000..f1c84e938 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/convert_and_load_or_store_integer.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FILD +# FIST +# FISTP +# FISTTP +''' diff --git a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/exchange.py b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/exchange.py new file mode 100644 index 000000000..fd02a00e4 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/exchange.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FXCH +''' diff --git a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/extract.py b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/extract.py new file mode 100644 index 000000000..a3ad2baec --- /dev/null +++ b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/extract.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FXTRACT +''' diff --git a/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py new file mode 100644 index 000000000..2a4c3f0ed --- /dev/null +++ b/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/load_or_store_floating_point.py @@ -0,0 +1,87 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop FLD_M { + ldfp ufp1, seg, sib, disp + movfp st(-1), ufp1, spm=-1 +}; + +def macroop FLD_P { + rdip t7 + ldfp ufp1, seg, riprel, disp + movfp st(-1), ufp1, spm=-1 +}; + +def macroop FST_M { + stfp st(0), seg, sib, disp +}; + +def macroop FST_P { + rdip t7 + stfp st(0), seg, riprel, disp +}; + +def macroop FSTP_M { + movfp ufp1, st(0), spm=1 + stfp ufp1, seg, sib, disp +}; + +def macroop FSTP_P { + movfp ufp1, st(0), spm=1 + rdip t7 + stfp ufp1, seg, riprel, disp +}; +''' diff --git a/src/arch/x86/isa/insts/x87/load_constants/__init__.py b/src/arch/x86/isa/insts/x87/load_constants/__init__.py new file mode 100644 index 000000000..d8a08b3dc --- /dev/null +++ b/src/arch/x86/isa/insts/x87/load_constants/__init__.py @@ -0,0 +1,64 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["load_0_1_or_pi", + "load_logarithm"] + +microcode = ''' +# X86 microcode +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/x87/load_constants/load_0_1_or_pi.py b/src/arch/x86/isa/insts/x87/load_constants/load_0_1_or_pi.py new file mode 100644 index 000000000..65165580f --- /dev/null +++ b/src/arch/x86/isa/insts/x87/load_constants/load_0_1_or_pi.py @@ -0,0 +1,60 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FLDZ +# FLD1 +# FLDPI +''' diff --git a/src/arch/x86/isa/insts/x87/load_constants/load_logarithm.py b/src/arch/x86/isa/insts/x87/load_constants/load_logarithm.py new file mode 100644 index 000000000..eb0ecd953 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/load_constants/load_logarithm.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FLDL2E +# FLDL2T +# FLDLG2 +# FLDLN2 +''' diff --git a/src/arch/x86/isa/insts/x87/no_operation.py b/src/arch/x86/isa/insts/x87/no_operation.py new file mode 100644 index 000000000..a62147334 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/no_operation.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FNOP +''' diff --git a/src/arch/x86/isa/insts/x87/stack_management/__init__.py b/src/arch/x86/isa/insts/x87/stack_management/__init__.py new file mode 100644 index 000000000..d2237fa8f --- /dev/null +++ b/src/arch/x86/isa/insts/x87/stack_management/__init__.py @@ -0,0 +1,64 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["stack_control", + "clear_state"] + +microcode = ''' +# X86 microcode +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/x87/stack_management/clear_state.py b/src/arch/x86/isa/insts/x87/stack_management/clear_state.py new file mode 100644 index 000000000..65e870e02 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/stack_management/clear_state.py @@ -0,0 +1,58 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FFREE +''' diff --git a/src/arch/x86/isa/insts/x87/stack_management/stack_control.py b/src/arch/x86/isa/insts/x87/stack_management/stack_control.py new file mode 100644 index 000000000..6a68f8adc --- /dev/null +++ b/src/arch/x86/isa/insts/x87/stack_management/stack_control.py @@ -0,0 +1,59 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FDECSTP +# FINCSTP +''' diff --git a/src/arch/x86/isa/insts/x87/transcendental_functions/__init__.py b/src/arch/x86/isa/insts/x87/transcendental_functions/__init__.py new file mode 100644 index 000000000..fc683c1a1 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/transcendental_functions/__init__.py @@ -0,0 +1,64 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +categories = ["trigonometric_functions", + "logarithmic_functions"] + +microcode = ''' +# X86 microcode +''' +for category in categories: + exec "import %s as cat" % category + microcode += cat.microcode diff --git a/src/arch/x86/isa/insts/x87/transcendental_functions/logarithmic_functions.py b/src/arch/x86/isa/insts/x87/transcendental_functions/logarithmic_functions.py new file mode 100644 index 000000000..f7026ae4d --- /dev/null +++ b/src/arch/x86/isa/insts/x87/transcendental_functions/logarithmic_functions.py @@ -0,0 +1,61 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# F2XM1 +# FSCALE +# FYL2X +# FYL2XP1 +''' diff --git a/src/arch/x86/isa/insts/x87/transcendental_functions/trigonometric_functions.py b/src/arch/x86/isa/insts/x87/transcendental_functions/trigonometric_functions.py new file mode 100644 index 000000000..41d6cf856 --- /dev/null +++ b/src/arch/x86/isa/insts/x87/transcendental_functions/trigonometric_functions.py @@ -0,0 +1,62 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +# FSIN +# FCOS +# FSINCOS +# FPTAN +# FPATAN +''' diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index c9c33f981..4818b926c 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -142,6 +142,8 @@ def template MacroConstructor {{ : %(base_class)s("%(mnemonic)s", machInst, %(num_microops)s) { %(adjust_env)s; + %(adjust_imm)s; + %(adjust_disp)s; %(do_modrm)s; %(constructor)s; //alloc_microops is the code that sets up the microops @@ -159,14 +161,30 @@ let {{ self.microops.append(microop) def setAdjustEnv(self, val): self.adjust_env = val + def adjustImm(self, val): + self.adjust_imm += val + def adjustDisp(self, val): + self.adjust_disp += val def __init__(self, name): super(X86Macroop, self).__init__(name) self.directives = { - "adjust_env" : self.setAdjustEnv + "adjust_env" : self.setAdjustEnv, + "adjust_imm" : self.adjustImm, + "adjust_disp" : self.adjustDisp } self.declared = False self.adjust_env = "" self.doModRM = "" + self.adjust_imm = ''' + uint64_t adjustedImm = IMMEDIATE; + //This is to pacify gcc in case the immediate isn't used. + adjustedImm = adjustedImm; + ''' + self.adjust_disp = ''' + uint64_t adjustedDisp = DISPLACEMENT; + //This is to pacify gcc in case the displacement isn't used. + adjustedDisp = adjustedDisp; + ''' def getAllocator(self, env): return "new X86Macroop::%s(machInst, %s)" % (self.name, env.getAllocator()) def getDeclaration(self): @@ -198,6 +216,8 @@ let {{ {"code" : "", "num_microops" : numMicroops, "alloc_microops" : allocMicroops, "adjust_env" : self.adjust_env, + "adjust_imm" : self.adjust_imm, + "adjust_disp" : self.adjust_disp, "do_modrm" : self.doModRM}) return MacroConstructor.subst(iop); }}; diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 579909506..0c43d4c13 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -88,8 +88,8 @@ let {{ "regm" : "env.regm", "xmmlm" : "FLOATREG_XMM_LOW(env.regm)", "xmmhm" : "FLOATREG_XMM_HIGH(env.regm)", - "imm" : "IMMEDIATE", - "disp" : "DISPLACEMENT", + "imm" : "adjustedImm", + "disp" : "adjustedDisp", "seg" : "env.seg", "scale" : "env.scale", "index" : "env.index", @@ -106,6 +106,10 @@ let {{ assembler.symbols["riprel"] = \ ["1", assembler.symbols["t0"], assembler.symbols["t7"]] + # This segment selects an internal address space mapped to MSRs, + # CPUID info, etc. + assembler.symbols["intseg"] = "NUM_SEGMENTREGS" + for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'): assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper() @@ -131,10 +135,20 @@ let {{ env.dataSize = 8; ''' + def trimImm(width): + return "adjustedImm = adjustedImm & mask(%s);" % width + + assembler.symbols["trimImm"] = trimImm + def labeler(labelStr): return "label_%s" % labelStr assembler.symbols["label"] = labeler + def stack_index(index): + return "(NUM_FLOATREGS + (((%s) + 8) %% 8))" % index + + assembler.symbols["st"] = stack_index + macroopDict = assembler.assemble(microcode) }}; diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa index 9722f182e..75658a26c 100644 --- a/src/arch/x86/isa/microops/base.isa +++ b/src/arch/x86/isa/microops/base.isa @@ -92,11 +92,3 @@ let {{ return 'new %s(machInst, %s)' % \ (self.className, mnemonic, self.microFlagsText(microFlags)) }}; - -////////////////////////////////////////////////////////////////////////// -// -// FpOp Microop templates -// -////////////////////////////////////////////////////////////////////////// - -//TODO Actually write an fp microop base class. diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa new file mode 100644 index 000000000..2919aa277 --- /dev/null +++ b/src/arch/x86/isa/microops/fpop.isa @@ -0,0 +1,341 @@ +// Copyright (c) 2007 The Hewlett-Packard Development Company +// All rights reserved. +// +// Redistribution and use of this software in source and binary forms, +// with or without modification, are permitted provided that the +// following conditions are met: +// +// The software must be used only for Non-Commercial Use which means any +// use which is NOT directed to receiving any direct monetary +// compensation for, or commercial advantage from such use. Illustrative +// examples of non-commercial use are academic research, personal study, +// teaching, education and corporate research & development. +// Illustrative examples of commercial use are distributing products for +// commercial advantage and providing services using the software for +// commercial advantage. +// +// If you wish to use this software or functionality therein that may be +// covered by patents for commercial use, please contact: +// Director of Intellectual Property Licensing +// Office of Strategy and Technology +// Hewlett-Packard Company +// 1501 Page Mill Road +// Palo Alto, California 94304 +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. Redistributions +// in binary form must reproduce the above copyright notice, this list of +// conditions and the following disclaimer in the documentation and/or +// other materials provided with the distribution. Neither the name of +// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. No right of +// sublicense is granted herewith. Derivatives of the software and +// output created using the software may be prepared, but only for +// Non-Commercial Uses. Derivatives of the software may be shared with +// others provided: (i) the others agree to abide by the list of +// conditions herein which includes the Non-Commercial Use restrictions; +// and (ii) such Derivatives of the software include the above copyright +// notice to acknowledge the contribution from this software where +// applicable, this list of conditions and the disclaimer below. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +////////////////////////////////////////////////////////////////////////// +// +// FpOp Microop templates +// +////////////////////////////////////////////////////////////////////////// + +def template MicroFpOpExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord *traceData) const + { + Fault fault = NoFault; + + DPRINTF(X86, "The data size is %d\n", dataSize); + %(op_decl)s; + %(op_rd)s; + + if(%(cond_check)s) + { + %(code)s; + %(flag_code)s; + %(top_code)s; + } + else + { + %(else_code)s; + } + + //Write the resulting state to the execution context + if(fault == NoFault) + { + %(op_wb)s; + } + return fault; + } +}}; + +def template MicroFpOpDeclare {{ + class %(class_name)s : public %(base_class)s + { + protected: + void buildMe(); + + public: + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + uint8_t _dataSize, int8_t _spm); + + %(class_name)s(ExtMachInst _machInst, + const char * instMnem, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + uint8_t _dataSize, int8_t _spm); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroFpOpConstructor {{ + + inline void %(class_name)s::buildMe() + { + %(constructor)s; + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + uint8_t _dataSize, int8_t _spm) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + false, false, false, false, + _src1, _src2, _dest, _dataSize, _spm, + %(op_class)s) + { + buildMe(); + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + RegIndex _src1, RegIndex _src2, RegIndex _dest, + uint8_t _dataSize, int8_t _spm) : + %(base_class)s(machInst, "%(mnemonic)s", instMnem, + isMicro, isDelayed, isFirst, isLast, + _src1, _src2, _dest, _dataSize, _spm, + %(op_class)s) + { + buildMe(); + } +}}; + +let {{ + # Make these empty strings so that concatenating onto + # them will always work. + header_output = "" + decoder_output = "" + exec_output = "" + + class FpOpMeta(type): + def buildCppClasses(self, name, Name, suffix, \ + code, flag_code, cond_check, else_code): + + # Globals to stick the output in + global header_output + global decoder_output + global exec_output + + # Stick all the code together so it can be searched at once + allCode = "|".join((code, flag_code, cond_check, else_code)) + + # If there's something optional to do with flags, generate + # a version without it and fix up this version to use it. + if flag_code is not "" or cond_check is not "true": + self.buildCppClasses(name, Name, suffix, + code, "", "true", else_code) + suffix = "Flags" + suffix + + base = "X86ISA::FpOp" + + # Get everything ready for the substitution + iop_top = InstObjParams(name, Name + suffix + "Top", base, + {"code" : code, + "flag_code" : flag_code, + "cond_check" : cond_check, + "else_code" : else_code, + "top_code" : "TOP = (TOP + spm + 8) % 8;"}) + iop = InstObjParams(name, Name + suffix, base, + {"code" : code, + "flag_code" : flag_code, + "cond_check" : cond_check, + "else_code" : else_code, + "top_code" : ";"}) + + # Generate the actual code (finally!) + header_output += MicroFpOpDeclare.subst(iop_top) + decoder_output += MicroFpOpConstructor.subst(iop_top) + exec_output += MicroFpOpExecute.subst(iop_top) + header_output += MicroFpOpDeclare.subst(iop) + decoder_output += MicroFpOpConstructor.subst(iop) + exec_output += MicroFpOpExecute.subst(iop) + + + def __new__(mcls, Name, bases, dict): + abstract = False + name = Name.lower() + if "abstract" in dict: + abstract = dict['abstract'] + del dict['abstract'] + + cls = super(FpOpMeta, mcls).__new__(mcls, Name, bases, dict) + if not abstract: + cls.className = Name + cls.mnemonic = name + code = cls.code + flag_code = cls.flag_code + cond_check = cls.cond_check + else_code = cls.else_code + + # Set up the C++ classes + mcls.buildCppClasses(cls, name, Name, "", + code, flag_code, cond_check, else_code) + + # Hook into the microassembler dict + global microopClasses + microopClasses[name] = cls + + return cls + + + class FpOp(X86Microop): + __metaclass__ = FpOpMeta + # This class itself doesn't act as a microop + abstract = True + + # Default template parameter values + flag_code = "" + cond_check = "true" + else_code = ";" + + def __init__(self, dest, src1, src2, spm=0, \ + SetStatus=False, dataSize="env.dataSize"): + self.dest = dest + self.src1 = src1 + self.src2 = src2 + self.spm = spm + self.dataSize = dataSize + if SetStatus: + self.className += "Flags" + if spm: + self.className += "Top" + + def getAllocator(self, *microFlags): + return '''new %(class_name)s(machInst, mnemonic + %(flags)s, %(src1)s, %(src2)s, %(dest)s, + %(dataSize)s, %(spm)d)''' % { + "class_name" : self.className, + "flags" : self.microFlagsText(microFlags), + "src1" : self.src1, "src2" : self.src2, + "dest" : self.dest, + "dataSize" : self.dataSize, + "spm" : self.spm} + + class Movfp(FpOp): + def __init__(self, dest, src1, flags=0, spm=0, \ + SetStatus=False, dataSize="env.dataSize"): + super(Movfp, self).__init__(dest, src1, flags, \ + spm, SetStatus, dataSize) + code = 'FpDestReg.uqw = FpSrcReg1.uqw;' + else_code = 'FpDestReg.uqw = FpDestReg.uqw;' + cond_check = "checkCondition(ccFlagBits, src2)" + + class Xorfp(FpOp): + code = 'FpDestReg.uqw = FpSrcReg1.uqw ^ FpSrcReg2.uqw;' + + class Sqrtfp(FpOp): + code = 'FpDestReg = sqrt(FpSrcReg2);' + + # Conversion microops + class ConvOp(FpOp): + abstract = True + def __init__(self, dest, src1): + super(ConvOp, self).__init__(dest, src1, "(int)FLOATREG_MICROFP0") + + # These probably shouldn't look at the ExtMachInst directly to figure + # out what size to use and should instead delegate that to the macroop's + # constructor. That would be more efficient, and it would make the + # microops a little more modular. + class cvtf_i2d(ConvOp): + code = ''' + X86IntReg intReg = SSrcReg1; + if (REX_W) + FpDestReg = intReg.SR; + else + FpDestReg = intReg.SE; + ''' + + class cvtf_i2d_hi(ConvOp): + code = 'FpDestReg = bits(SSrcReg1, 63, 32);' + + class cvtf_d2i(ConvOp): + code = ''' + int64_t intSrcReg1 = static_cast<int64_t>(FpSrcReg1); + if (REX_W) + SDestReg = intSrcReg1; + else + SDestReg = merge(SDestReg, intSrcReg1, 4); + ''' + + # These need to consider size at some point. They'll always use doubles + # for the moment. + class addfp(FpOp): + code = 'FpDestReg = FpSrcReg1 + FpSrcReg2;' + + class mulfp(FpOp): + code = 'FpDestReg = FpSrcReg1 * FpSrcReg2;' + + class divfp(FpOp): + code = 'FpDestReg = FpSrcReg1 / FpSrcReg2;' + + class subfp(FpOp): + code = 'FpDestReg = FpSrcReg1 - FpSrcReg2;' + + class Compfp(FpOp): + def __init__(self, src1, src2, spm=0, setStatus=False, \ + dataSize="env.dataSize"): + super(Compfp, self).__init__("(int)FLOATREG_MICROFP0", \ + src1, src2, spm, setStatus, dataSize) + # This class sets the condition codes in rflags according to the + # rules for comparing floating point. + code = ''' + // ZF PF CF + // Unordered 1 1 1 + // Greater than 0 0 0 + // Less than 0 0 1 + // Equal 1 0 0 + // OF = SF = AF = 0 + ccFlagBits = ccFlagBits & ~(OFBit | SFBit | AFBit | + ZFBit | PFBit | CFBit); + if (isnan(FpSrcReg1) || isnan(FpSrcReg2)) + ccFlagBits = ccFlagBits | (ZFBit | PFBit | CFBit); + else if(FpSrcReg1 < FpSrcReg2) + ccFlagBits = ccFlagBits | CFBit; + else if(FpSrcReg1 == FpSrcReg2) + ccFlagBits = ccFlagBits | ZFBit; + ''' +}}; diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 1bdc1d37a..61adde8d1 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -123,7 +123,7 @@ def template MicroLoadExecute {{ %(ea_code)s; DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); - fault = read(xc, EA, Mem, 0); + fault = read(xc, EA, Mem, (%(mem_flags)s) | (1 << segment)); if(fault == NoFault) { @@ -150,7 +150,7 @@ def template MicroLoadInitiateAcc {{ %(ea_code)s; DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); - fault = read(xc, EA, Mem, 0); + fault = read(xc, EA, Mem, (%(mem_flags)s) | (1 << segment)); return fault; } @@ -197,7 +197,7 @@ def template MicroStoreExecute {{ if(fault == NoFault) { - fault = write(xc, Mem, EA, 0); + fault = write(xc, Mem, EA, (%(mem_flags)s) | (1 << segment)); if(fault == NoFault) { %(op_wb)s; @@ -224,7 +224,7 @@ def template MicroStoreInitiateAcc {{ if(fault == NoFault) { - fault = write(xc, Mem, EA, 0); + fault = write(xc, Mem, EA, (%(mem_flags)s) | (1 << segment)); if(fault == NoFault) { %(op_wb)s; @@ -325,13 +325,13 @@ def template MicroLdStOpConstructor {{ let {{ class LdStOp(X86Microop): - def __init__(self, data, segment, addr, disp, dataSize): + def __init__(self, data, segment, addr, disp, dataSize, addressSize): self.data = data [self.scale, self.index, self.base] = addr self.disp = disp self.segment = segment self.dataSize = dataSize - self.addressSize = "env.addressSize" + self.addressSize = addressSize def getAllocator(self, *microFlags): allocator = '''new %(class_name)s(machInst, mnemonic @@ -358,7 +358,7 @@ let {{ calculateEA = "EA = SegBase + scale * Index + Base + disp;" - def defineMicroLoadOp(mnemonic, code): + def defineMicroLoadOp(mnemonic, code, mem_flags=0): global header_output global decoder_output global exec_output @@ -368,7 +368,9 @@ let {{ # Build up the all register version of this micro op iop = InstObjParams(name, Name, 'X86ISA::LdStOp', - {"code": code, "ea_code": calculateEA}) + {"code": code, + "ea_code": calculateEA, + "mem_flags": mem_flags}) header_output += MicroLdStOpDeclare.subst(iop) decoder_output += MicroLdStOpConstructor.subst(iop) exec_output += MicroLoadExecute.subst(iop) @@ -376,19 +378,20 @@ let {{ exec_output += MicroLoadCompleteAcc.subst(iop) class LoadOp(LdStOp): - def __init__(self, data, segment, addr, - disp = 0, dataSize="env.dataSize"): + def __init__(self, data, segment, addr, disp = 0, + dataSize="env.dataSize", addressSize="env.addressSize"): super(LoadOp, self).__init__(data, segment, - addr, disp, dataSize) + addr, disp, dataSize, addressSize) self.className = Name self.mnemonic = name microopClasses[name] = LoadOp defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);') + defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', 'StoreCheck') defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;') - def defineMicroStoreOp(mnemonic, code): + def defineMicroStoreOp(mnemonic, code, mem_flags=0): global header_output global decoder_output global exec_output @@ -398,7 +401,9 @@ let {{ # Build up the all register version of this micro op iop = InstObjParams(name, Name, 'X86ISA::LdStOp', - {"code": code, "ea_code": calculateEA}) + {"code": code, + "ea_code": calculateEA, + "mem_flags": mem_flags}) header_output += MicroLdStOpDeclare.subst(iop) decoder_output += MicroLdStOpConstructor.subst(iop) exec_output += MicroStoreExecute.subst(iop) @@ -406,10 +411,10 @@ let {{ exec_output += MicroStoreCompleteAcc.subst(iop) class StoreOp(LdStOp): - def __init__(self, data, segment, addr, - disp = 0, dataSize="env.dataSize"): + def __init__(self, data, segment, addr, disp = 0, + dataSize="env.dataSize", addressSize="env.addressSize"): super(StoreOp, self).__init__(data, segment, - addr, disp, dataSize) + addr, disp, dataSize, addressSize) self.className = Name self.mnemonic = name @@ -417,21 +422,50 @@ let {{ defineMicroStoreOp('St', 'Mem = Data;') defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;') + defineMicroStoreOp('Stupd', ''' + Mem = Data; + Base = merge(Base, EA - SegBase, addressSize); + '''); + iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp', - {"code": "Data = merge(Data, EA, dataSize);", "ea_code": calculateEA}) + {"code": "Data = merge(Data, EA, dataSize);", + "ea_code": calculateEA, + "mem_flags": 0}) header_output += MicroLeaDeclare.subst(iop) decoder_output += MicroLdStOpConstructor.subst(iop) exec_output += MicroLeaExecute.subst(iop) class LeaOp(LdStOp): - def __init__(self, data, segment, addr, - disp = 0, dataSize="env.dataSize"): + def __init__(self, data, segment, addr, disp = 0, + dataSize="env.dataSize", addressSize="env.addressSize"): super(LeaOp, self).__init__(data, segment, - addr, disp, dataSize) + addr, disp, dataSize, addressSize) self.className = "Lea" self.mnemonic = "lea" microopClasses["lea"] = LeaOp + + + iop = InstObjParams("cda", "Cda", 'X86ISA::LdStOp', + {"code": ''' + Addr paddr; + fault = xc->translateDataWriteAddr(EA, paddr, + dataSize, (1 << segment)); + ''', + "ea_code": calculateEA}) + header_output += MicroLeaDeclare.subst(iop) + decoder_output += MicroLdStOpConstructor.subst(iop) + exec_output += MicroLeaExecute.subst(iop) + + class CdaOp(LdStOp): + def __init__(self, segment, addr, disp = 0, + dataSize="env.dataSize", addressSize="env.addressSize"): + super(CdaOp, self).__init__("NUM_INTREGS", segment, + addr, disp, dataSize, addressSize) + self.className = "Cda" + self.mnemonic = "cda" + + microopClasses["cda"] = CdaOp }}; diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa index c357c1d6c..6686444fd 100644 --- a/src/arch/x86/isa/microops/limmop.isa +++ b/src/arch/x86/isa/microops/limmop.isa @@ -148,6 +148,8 @@ let {{ self.className = "Limm" self.mnemonic = "limm" self.dest = dest + if isinstance(imm, (int, long)): + imm = "ULL(%d)" % imm self.imm = imm self.dataSize = dataSize diff --git a/src/arch/x86/isa/microops/microops.isa b/src/arch/x86/isa/microops/microops.isa index 50c9ac498..53f34d3f2 100644 --- a/src/arch/x86/isa/microops/microops.isa +++ b/src/arch/x86/isa/microops/microops.isa @@ -56,6 +56,9 @@ //Common microop stuff ##include "base.isa" +//Floating point definitions +##include "fpop.isa" + //Register microop definitions ##include "regop.isa" diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 98743e603..892c44487 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -439,10 +439,11 @@ let {{ abstract = True flag_code = ''' //Don't have genFlags handle the OF or CF bits - uint64_t mask = CFBit | OFBit; + uint64_t mask = CFBit | ECFBit | OFBit; ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); //If a logic microop wants to set these, it wants to set them to 0. ccFlagBits &= ~(CFBit & ext); + ccFlagBits &= ~(ECFBit & ext); ccFlagBits &= ~(OFBit & ext); ''' @@ -458,7 +459,7 @@ let {{ class CondRegOp(RegOp): abstract = True - cond_check = "checkCondition(ccFlagBits)" + cond_check = "checkCondition(ccFlagBits, ext)" class RdRegOp(RegOp): abstract = True @@ -481,13 +482,13 @@ let {{ class Adc(FlagRegOp): code = ''' CCFlagBits flags = ccFlagBits; - DestReg = merge(DestReg, psrc1 + op2 + flags.CF, dataSize); + DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); ''' class Sbb(SubRegOp): code = ''' CCFlagBits flags = ccFlagBits; - DestReg = merge(DestReg, psrc1 - op2 - flags.CF, dataSize); + DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); ''' class And(LogicRegOp): @@ -732,7 +733,7 @@ let {{ if(shiftAmt) { CCFlagBits flags = ccFlagBits; - uint64_t top = flags.CF << (dataSize * 8 - shiftAmt); + uint64_t top = flags.cf << (dataSize * 8 - shiftAmt); if(shiftAmt > 1) top |= psrc1 << (dataSize * 8 - shiftAmt - 1); uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); @@ -803,7 +804,7 @@ let {{ { CCFlagBits flags = ccFlagBits; uint64_t top = psrc1 << shiftAmt; - uint64_t bottom = flags.CF << (shiftAmt - 1); + uint64_t bottom = flags.cf << (shiftAmt - 1); if(shiftAmt > 1) bottom |= bits(psrc1, dataSize * 8 - 1, @@ -834,7 +835,7 @@ let {{ ''' class Wrip(WrRegOp, CondRegOp): - code = 'RIP = psrc1 + op2' + code = 'RIP = psrc1 + sop2' else_code="RIP = RIP;" class Br(WrRegOp, CondRegOp): @@ -852,7 +853,7 @@ let {{ class Ruflag(RegOp): code = ''' - int flag = bits(ccFlagBits, imm8 + 0*psrc1); + int flag = bits(ccFlagBits, imm8); DestReg = merge(DestReg, flag, dataSize); ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : (ccFlagBits & ~EZFBit); @@ -873,67 +874,4 @@ let {{ class Zext(RegOp): code = 'DestReg = bits(psrc1, imm8-1, 0);' - - class Compfp(WrRegOp): - # This class sets the condition codes in rflags according to the - # rules for comparing floating point. - code = ''' - // ZF PF CF - // Unordered 1 1 1 - // Greater than 0 0 0 - // Less than 0 0 1 - // Equal 1 0 0 - // OF = SF = AF = 0 - ccFlagBits = ccFlagBits & ~(OFBit | SFBit | AFBit | - ZFBit | PFBit | CFBit); - if (isnan(FpSrcReg1) || isnan(FpSrcReg2)) - ccFlagBits = ccFlagBits | (ZFBit | PFBit | CFBit); - else if(FpSrcReg1 < FpSrcReg2) - ccFlagBits = ccFlagBits | CFBit; - else if(FpSrcReg1 == FpSrcReg2) - ccFlagBits = ccFlagBits | ZFBit; - ''' - - class Xorfp(RegOp): - code = 'FpDestReg.uqw = FpSrcReg1.uqw ^ FpSrcReg2.uqw;' - - class Sqrtfp(RegOp): - code = 'FpDestReg = sqrt(FpSrcReg2);' - - class Movfp(CondRegOp): - code = 'FpDestReg.uqw = FpSrcReg2.uqw;' - else_code = 'FpDestReg.uqw = FpDestReg.uqw;' - - # Conversion microops - class ConvOp(RegOp): - abstract = True - def __init__(self, dest, src1): - super(ConvOp, self).__init__(dest, src1, "NUM_INTREGS") - - #FIXME This needs to always use 32 bits unless REX.W is present - class cvtf_i2d(ConvOp): - code = 'FpDestReg = spsrc1;' - - class cvtf_i2d_hi(ConvOp): - code = 'FpDestReg = bits(SrcReg1, 63, 32);' - - class cvtf_d2i(ConvOp): - code = ''' - int64_t intSrcReg1 = static_cast<int64_t>(FpSrcReg1); - DestReg = merge(DestReg, intSrcReg1, dataSize); - ''' - - # These need to consider size at some point. They'll always use doubles - # for the moment. - class addfp(RegOp): - code = 'FpDestReg = FpSrcReg1 + FpSrcReg2;' - - class mulfp(RegOp): - code = 'FpDestReg = FpSrcReg1 * FpSrcReg2;' - - class divfp(RegOp): - code = 'FpDestReg = FpSrcReg1 / FpSrcReg2;' - - class subfp(RegOp): - code = 'FpDestReg = FpSrcReg1 - FpSrcReg2;' }}; diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa index 5c9e8dda9..3ca59f033 100644 --- a/src/arch/x86/isa/microops/specop.isa +++ b/src/arch/x86/isa/microops/specop.isa @@ -60,57 +60,135 @@ ////////////////////////////////////////////////////////////////////////// output header {{ - class MicroFault : public X86ISA::X86MicroopBase + class MicroFaultBase : public X86ISA::X86MicroopBase { protected: Fault fault; - void buildMe(); + uint8_t cc; public: - MicroFault(ExtMachInst _machInst, const char * instMnem, + MicroFaultBase(ExtMachInst _machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - Fault _fault); - - MicroFault(ExtMachInst _machInst, const char * instMnem, - Fault _fault); + Fault _fault, uint8_t _cc); - %(BasicExecDeclare)s + MicroFaultBase(ExtMachInst _machInst, const char * instMnem, + Fault _fault, uint8_t _cc); std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; + + class MicroHalt : public X86ISA::X86MicroopBase + { + public: + MicroHalt(ExtMachInst _machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast) : + X86MicroopBase(_machInst, "halt", instMnem, + isMicro, isDelayed, isFirst, isLast, No_OpClass) + { + } + + MicroHalt(ExtMachInst _machInst, const char * instMnem) : + X86MicroopBase(_machInst, "halt", instMnem, + false, false, false, false, No_OpClass) + { + } + + %(BasicExecDeclare)s + }; }}; -output decoder {{ - Fault MicroFault::execute(%(CPU_exec_context)s *xc, +def template MicroFaultDeclare {{ + class %(class_name)s : public %(base_class)s + { + private: + void buildMe(); + public: + %(class_name)s(ExtMachInst _machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + Fault _fault, uint8_t _cc); + + %(class_name)s(ExtMachInst _machInst, const char * instMnem, + Fault _fault, uint8_t _cc); + + %(BasicExecDeclare)s + }; +}}; + +def template MicroFaultExecute {{ + Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - //Return the fault we were constructed with - return fault; + %(op_decl)s; + %(op_rd)s; + if (%(cond_test)s) { + //Return the fault we were constructed with + return fault; + } else { + return NoFault; + } } }}; +output exec {{ + Fault + MicroHalt::execute(%(CPU_exec_context)s *xc, + Trace::InstRecord * traceData) const + { + xc->tcBase()->suspend(); + return NoFault; + } +}}; + output decoder {{ - inline MicroFault::MicroFault( - ExtMachInst machInst, const char * instMnem, Fault _fault) : + inline MicroFaultBase::MicroFaultBase( + ExtMachInst machInst, const char * instMnem, + Fault _fault, uint8_t _cc) : X86MicroopBase(machInst, "fault", instMnem, - false, false, false, false, No_OpClass), fault(_fault) + false, false, false, false, No_OpClass), + fault(_fault), cc(_cc) { } - inline MicroFault::MicroFault( + inline MicroFaultBase::MicroFaultBase( ExtMachInst machInst, const char * instMnem, bool isMicro, bool isDelayed, bool isFirst, bool isLast, - Fault _fault) : + Fault _fault, uint8_t _cc) : X86MicroopBase(machInst, "fault", instMnem, isMicro, isDelayed, isFirst, isLast, No_OpClass), - fault(_fault) + fault(_fault), cc(_cc) + { + } +}}; + +def template MicroFaultConstructor {{ + + inline void %(class_name)s::buildMe() + { + %(constructor)s; + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + Fault _fault, uint8_t _cc) : + %(base_class)s(machInst, instMnem, _fault, _cc) + { + buildMe(); + } + + inline %(class_name)s::%(class_name)s( + ExtMachInst machInst, const char * instMnem, + bool isMicro, bool isDelayed, bool isFirst, bool isLast, + Fault _fault, uint8_t _cc) : + %(base_class)s(machInst, instMnem, + isMicro, isDelayed, isFirst, isLast, _fault, _cc) { + buildMe(); } }}; output decoder {{ - std::string MicroFault::generateDisassembly(Addr pc, + std::string MicroFaultBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const { std::stringstream response; @@ -127,14 +205,47 @@ output decoder {{ let {{ class Fault(X86Microop): - def __init__(self, fault): + className = "MicroFault" + def __init__(self, fault, flags=None): self.fault = fault + if flags: + if not isinstance(flags, (list, tuple)): + raise Exception, "flags must be a list or tuple of flags" + self.cond = " | ".join(flags) + self.className += "Flags" + else: + self.cond = "0" def getAllocator(self, *microFlags): - allocator = '''new MicroFault(machInst, mnemonic - %(flags)s, %(fault)s)''' % { + allocator = '''new %(class_name)s(machInst, mnemonic + %(flags)s, %(fault)s, %(cc)s)''' % { + "class_name" : self.className, "flags" : self.microFlagsText(microFlags), - "fault" : self.fault} + "fault" : self.fault, + "cc" : self.cond} return allocator + + iop = InstObjParams("fault", "MicroFault", "MicroFaultBase", + {"code": "", + "cond_test": "checkCondition(ccFlagBits, cc)"}) + exec_output = MicroFaultExecute.subst(iop) + header_output = MicroFaultDeclare.subst(iop) + decoder_output = MicroFaultConstructor.subst(iop) + iop = InstObjParams("fault", "MicroFaultFlags", "MicroFaultBase", + {"code": "", + "cond_test": "true"}) + exec_output += MicroFaultExecute.subst(iop) + header_output += MicroFaultDeclare.subst(iop) + decoder_output += MicroFaultConstructor.subst(iop) microopClasses["fault"] = Fault + + class Halt(X86Microop): + def __init__(self): + pass + + def getAllocator(self, *microFlags): + return "new MicroHalt(machInst, mnemonic %s)" % \ + self.microFlagsText(microFlags) + + microopClasses["halt"] = Halt }}; diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 7b0427b44..8c0eacca2 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -96,10 +96,13 @@ def operand_types {{ def operands {{ 'SrcReg1': ('IntReg', 'uqw', 'INTREG_FOLDED(src1, foldOBit)', 'IsInteger', 1), + 'SSrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 1), 'SrcReg2': ('IntReg', 'uqw', 'INTREG_FOLDED(src2, foldOBit)', 'IsInteger', 2), + 'SSrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 1), 'Index': ('IntReg', 'uqw', 'INTREG_FOLDED(index, foldABit)', 'IsInteger', 3), 'Base': ('IntReg', 'uqw', 'INTREG_FOLDED(base, foldABit)', 'IsInteger', 4), 'DestReg': ('IntReg', 'uqw', 'INTREG_FOLDED(dest, foldOBit)', 'IsInteger', 5), + 'SDestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 5), 'Data': ('IntReg', 'uqw', 'INTREG_FOLDED(data, foldOBit)', 'IsInteger', 6), 'ProdLow': ('IntReg', 'uqw', 'INTREG_IMPLICIT(0)', 'IsInteger', 7), 'ProdHi': ('IntReg', 'uqw', 'INTREG_IMPLICIT(1)', 'IsInteger', 8), @@ -115,6 +118,9 @@ def operands {{ 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51), 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52), 'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60), + # The TOP register should needs to be more protected so that later + # instructions don't map their indexes with an old value. + 'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 61), 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70), 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) }}; diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa index 59e9577d9..cf6b6ff86 100644 --- a/src/arch/x86/isa/specialize.isa +++ b/src/arch/x86/isa/specialize.isa @@ -172,6 +172,9 @@ let {{ elif opType.tag in ("I", "J"): # Immediates Name += "_I" + elif opType.tag == "O": + # Immediate containing a memory offset + Name += "_MI" elif opType.tag in ("PR", "R", "VR"): # Non register modrm settings should cause an error env.addReg(ModRMRMIndex) diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh index 602c99390..762f9b172 100644 --- a/src/arch/x86/isa_traits.hh +++ b/src/arch/x86/isa_traits.hh @@ -61,6 +61,7 @@ #include "arch/x86/intregs.hh" #include "arch/x86/types.hh" #include "arch/x86/x86_traits.hh" +#include "sim/host.hh" class StaticInstPtr; @@ -89,7 +90,11 @@ namespace X86ISA //mmx/x87 registers 8 + //xmm registers - 16 + 16 * 2 + + //The microcode fp registers + 8 + + //The indices that are mapped over the fp stack + 8 }; // semantically meaningful register indices @@ -124,12 +129,14 @@ namespace X86ISA const int LogVMPageSize = 12; const int VMPageSize = (1 << LogVMPageSize); - const int PageShift = 13; + const int PageShift = 12; const int PageBytes = 1ULL << PageShift; const int BranchPredAddrShiftAmt = 0; StaticInstPtr decodeInst(ExtMachInst); + + const Addr LoadAddrMask = ULL(-1); }; #endif // __ARCH_X86_ISATRAITS_HH__ diff --git a/src/arch/x86/kernel_stats.hh b/src/arch/x86/kernel_stats.hh index 8cd80073e..7679cb305 100644 --- a/src/arch/x86/kernel_stats.hh +++ b/src/arch/x86/kernel_stats.hh @@ -58,10 +58,33 @@ #ifndef __ARCH_X86_KERNELSTATS_HH__ #define __ARCH_X86_KERNELSTATS_HH__ -#error X86 is not yet supported! +#include "kern/kernel_stats.hh" -namespace X86ISA +namespace X86ISA { +namespace Kernel { + +enum cpu_mode { + ring0, + ring1, + ring2, + ring3, + kernel = ring0, + user = ring3, + idle, + //What is this next one for? + cpu_mode_num +}; + +extern const char *modestr[]; + +class Statistics : public ::Kernel::Statistics { + public: + Statistics(System * system) : ::Kernel::Statistics(system) + {} }; +} +} + #endif // __ARCH_X86_KERNELSTATS_HH__ diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc index 9ef591a1c..8beaf150b 100644 --- a/src/arch/x86/linux/process.cc +++ b/src/arch/x86/linux/process.cc @@ -77,21 +77,9 @@ X86LinuxProcess::getDesc(int callnum) return &syscallDescs[callnum]; } -X86LinuxProcess::X86LinuxProcess(const std::string &name, - ObjectFile *objFile, - System * system, - int stdin_fd, - int stdout_fd, - int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid) - : X86LiveProcess(name, objFile, system, - stdin_fd, stdout_fd, stderr_fd, argv, envp, cwd, - _uid, _euid, _gid, _egid, _pid, _ppid), +X86LinuxProcess::X86LinuxProcess(LiveProcessParams * params, + ObjectFile *objFile) + : X86LiveProcess(params, objFile), Num_Syscall_Descs(273) {} diff --git a/src/arch/x86/linux/process.hh b/src/arch/x86/linux/process.hh index 7e7236f0d..e224374d4 100644 --- a/src/arch/x86/linux/process.hh +++ b/src/arch/x86/linux/process.hh @@ -70,16 +70,7 @@ class X86LinuxProcess : public X86LiveProcess { public: /// Constructor. - X86LinuxProcess(const std::string &name, - ObjectFile *objFile, - System * system, - int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid); + X86LinuxProcess(LiveProcessParams * params, ObjectFile *objFile); /// Array of syscall descriptors, indexed by call number. static SyscallDesc syscallDescs[]; diff --git a/src/arch/x86/linux/syscalls.cc b/src/arch/x86/linux/syscalls.cc index 11fae96bb..c6b2fbb66 100644 --- a/src/arch/x86/linux/syscalls.cc +++ b/src/arch/x86/linux/syscalls.cc @@ -203,12 +203,12 @@ SyscallDesc X86LinuxProcess::syscallDescs[] = { /* 79 */ SyscallDesc("getcwd", unimplementedFunc), /* 80 */ SyscallDesc("chdir", unimplementedFunc), /* 81 */ SyscallDesc("fchdir", unimplementedFunc), - /* 82 */ SyscallDesc("rename", unimplementedFunc), + /* 82 */ SyscallDesc("rename", renameFunc), /* 83 */ SyscallDesc("mkdir", unimplementedFunc), /* 84 */ SyscallDesc("rmdir", unimplementedFunc), /* 85 */ SyscallDesc("creat", unimplementedFunc), /* 86 */ SyscallDesc("link", unimplementedFunc), - /* 87 */ SyscallDesc("unlink", unimplementedFunc), + /* 87 */ SyscallDesc("unlink", unlinkFunc), /* 88 */ SyscallDesc("symlink", unimplementedFunc), /* 89 */ SyscallDesc("readlink", unimplementedFunc), /* 90 */ SyscallDesc("chmod", unimplementedFunc), diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh index 01499e7ad..a516a2018 100644 --- a/src/arch/x86/miscregs.hh +++ b/src/arch/x86/miscregs.hh @@ -61,6 +61,12 @@ #include "arch/x86/x86_traits.hh" #include "base/bitunion.hh" +//These get defined in some system headers (at least termbits.h). That confuses +//things here significantly. +#undef CR0 +#undef CR2 +#undef CR3 + namespace X86ISA { enum CondFlagBit { @@ -111,6 +117,139 @@ namespace X86ISA // Flags register MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, + /* + * Model Specific Registers + */ + // Time stamp counter + MISCREG_TSC, + + MISCREG_MTRRCAP, + + MISCREG_SYSENTER_CS, + MISCREG_SYSENTER_ESP, + MISCREG_SYSENTER_EIP, + + MISCREG_MCG_CAP, + MISCREG_MCG_STATUS, + MISCREG_MCG_CTL, + + MISCREG_DEBUG_CTL_MSR, + + MISCREG_LAST_BRANCH_FROM_IP, + MISCREG_LAST_BRANCH_TO_IP, + MISCREG_LAST_EXCEPTION_FROM_IP, + MISCREG_LAST_EXCEPTION_TO_IP, + + MISCREG_MTRR_PHYS_BASE_BASE, + MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, + MISCREG_MTRR_PHYS_BASE_1, + MISCREG_MTRR_PHYS_BASE_2, + MISCREG_MTRR_PHYS_BASE_3, + MISCREG_MTRR_PHYS_BASE_4, + MISCREG_MTRR_PHYS_BASE_5, + MISCREG_MTRR_PHYS_BASE_6, + MISCREG_MTRR_PHYS_BASE_7, + + MISCREG_MTRR_PHYS_MASK_BASE, + MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, + MISCREG_MTRR_PHYS_MASK_1, + MISCREG_MTRR_PHYS_MASK_2, + MISCREG_MTRR_PHYS_MASK_3, + MISCREG_MTRR_PHYS_MASK_4, + MISCREG_MTRR_PHYS_MASK_5, + MISCREG_MTRR_PHYS_MASK_6, + MISCREG_MTRR_PHYS_MASK_7, + + MISCREG_MTRR_FIX_64K_00000, + MISCREG_MTRR_FIX_16K_80000, + MISCREG_MTRR_FIX_16K_A0000, + MISCREG_MTRR_FIX_4K_C0000, + MISCREG_MTRR_FIX_4K_C8000, + MISCREG_MTRR_FIX_4K_D0000, + MISCREG_MTRR_FIX_4K_D8000, + MISCREG_MTRR_FIX_4K_E0000, + MISCREG_MTRR_FIX_4K_E8000, + MISCREG_MTRR_FIX_4K_F0000, + MISCREG_MTRR_FIX_4K_F8000, + + MISCREG_PAT, + + MISCREG_DEF_TYPE, + + MISCREG_MC_CTL_BASE, + MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE, + MISCREG_MC1_CTL, + MISCREG_MC2_CTL, + MISCREG_MC3_CTL, + MISCREG_MC4_CTL, + + MISCREG_MC_STATUS_BASE, + MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, + MISCREG_MC1_STATUS, + MISCREG_MC2_STATUS, + MISCREG_MC3_STATUS, + MISCREG_MC4_STATUS, + + MISCREG_MC_ADDR_BASE, + MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE, + MISCREG_MC1_ADDR, + MISCREG_MC2_ADDR, + MISCREG_MC3_ADDR, + MISCREG_MC4_ADDR, + + MISCREG_MC_MISC_BASE, + MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, + MISCREG_MC1_MISC, + MISCREG_MC2_MISC, + MISCREG_MC3_MISC, + MISCREG_MC4_MISC, + + // Extended feature enable register + MISCREG_EFER, + + MISCREG_STAR, + MISCREG_LSTAR, + MISCREG_CSTAR, + + MISCREG_SF_MASK, + + MISCREG_KERNEL_GS_BASE, + + MISCREG_TSC_AUX, + + MISCREG_PERF_EVT_SEL_BASE, + MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, + MISCREG_PERF_EVT_SEL1, + MISCREG_PERF_EVT_SEL2, + MISCREG_PERF_EVT_SEL3, + + MISCREG_PERF_EVT_CTR_BASE, + MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, + MISCREG_PERF_EVT_CTR1, + MISCREG_PERF_EVT_CTR2, + MISCREG_PERF_EVT_CTR3, + + MISCREG_SYSCFG, + + MISCREG_IORR_BASE_BASE, + MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE, + MISCREG_IORR_BASE1, + + MISCREG_IORR_MASK_BASE, + MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE, + MISCREG_IORR_MASK1, + + MISCREG_TOP_MEM, + MISCREG_TOP_MEM2, + + MISCREG_VM_CR, + MISCREG_IGNNE, + MISCREG_SMM_CTL, + MISCREG_VM_HSAVE_PA, + + /* + * Segment registers + */ // Segment selectors MISCREG_SEG_SEL_BASE, MISCREG_ES = MISCREG_SEG_SEL_BASE, @@ -171,9 +310,12 @@ namespace X86ISA MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE, MISCREG_TR_ATTR, + // Floating point control registers + MISCREG_X87_TOP = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments, + //XXX Add "Model-Specific Registers" - NUM_MISCREGS = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments + NUM_MISCREGS }; static inline MiscRegIndex @@ -189,6 +331,66 @@ namespace X86ISA } static inline MiscRegIndex + MISCREG_MTRR_PHYS_BASE(int index) + { + return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index); + } + + static inline MiscRegIndex + MISCREG_MTRR_PHYS_MASK(int index) + { + return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index); + } + + static inline MiscRegIndex + MISCREG_MC_CTL(int index) + { + return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index); + } + + static inline MiscRegIndex + MISCREG_MC_STATUS(int index) + { + return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index); + } + + static inline MiscRegIndex + MISCREG_MC_ADDR(int index) + { + return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index); + } + + static inline MiscRegIndex + MISCREG_MC_MISC(int index) + { + return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index); + } + + static inline MiscRegIndex + MISCREG_PERF_EVT_SEL(int index) + { + return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index); + } + + static inline MiscRegIndex + MISCREG_PERF_EVT_CTR(int index) + { + return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index); + } + + static inline MiscRegIndex + MISCREG_IORR_BASE(int index) + { + return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index); + } + + static inline MiscRegIndex + MISCREG_IORR_MASK(int index) + { + return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index); + } + + static inline MiscRegIndex MISCREG_SEG_SEL(int index) { return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index); @@ -241,54 +443,54 @@ namespace X86ISA * plus two flags, EZF and ECF, which are only visible to microcode. */ BitUnion64(CCFlagBits) - Bitfield<11> OF; - Bitfield<7> SF; - Bitfield<6> ZF; - Bitfield<5> EZF; - Bitfield<4> AF; - Bitfield<3> ECF; - Bitfield<2> PF; - Bitfield<0> CF; + Bitfield<11> of; + Bitfield<7> sf; + Bitfield<6> zf; + Bitfield<5> ezf; + Bitfield<4> af; + Bitfield<3> ecf; + Bitfield<2> pf; + Bitfield<0> cf; EndBitUnion(CCFlagBits) /** * RFLAGS */ BitUnion64(RFLAGS) - Bitfield<21> ID; // ID Flag - Bitfield<20> VIP; // Virtual Interrupt Pending - Bitfield<19> VIF; // Virtual Interrupt Flag - Bitfield<18> AC; // Alignment Check - Bitfield<17> VM; // Virtual-8086 Mode - Bitfield<16> RF; // Resume Flag - Bitfield<14> NT; // Nested Task - Bitfield<13, 12> IOPL; // I/O Privilege Level - Bitfield<11> OF; // Overflow Flag - Bitfield<10> DF; // Direction Flag - Bitfield<9> IF; // Interrupt Flag - Bitfield<8> TF; // Trap Flag - Bitfield<7> SF; // Sign Flag - Bitfield<6> ZF; // Zero Flag - Bitfield<4> AF; // Auxiliary Flag - Bitfield<2> PF; // Parity Flag - Bitfield<0> CF; // Carry Flag + Bitfield<21> id; // ID Flag + Bitfield<20> vip; // Virtual Interrupt Pending + Bitfield<19> vif; // Virtual Interrupt Flag + Bitfield<18> ac; // Alignment Check + Bitfield<17> vm; // Virtual-8086 Mode + Bitfield<16> rf; // Resume Flag + Bitfield<14> nt; // Nested Task + Bitfield<13, 12> iopl; // I/O Privilege Level + Bitfield<11> of; // Overflow Flag + Bitfield<10> df; // Direction Flag + Bitfield<9> intf; // Interrupt Flag + Bitfield<8> tf; // Trap Flag + Bitfield<7> sf; // Sign Flag + Bitfield<6> zf; // Zero Flag + Bitfield<4> af; // Auxiliary Flag + Bitfield<2> pf; // Parity Flag + Bitfield<0> cf; // Carry Flag EndBitUnion(RFLAGS) /** * Control registers */ BitUnion64(CR0) - Bitfield<31> PG; // Paging - Bitfield<30> CD; // Cache Disable - Bitfield<29> NW; // Not Writethrough - Bitfield<18> AM; // Alignment Mask - Bitfield<16> WP; // Write Protect - Bitfield<5> NE; // Numeric Error - Bitfield<4> ET; // Extension Type - Bitfield<3> TS; // Task Switched - Bitfield<2> EM; // Emulation - Bitfield<1> MP; // Monitor Coprocessor - Bitfield<0> PE; // Protection Enabled + Bitfield<31> pg; // Paging + Bitfield<30> cd; // Cache Disable + Bitfield<29> nw; // Not Writethrough + Bitfield<18> am; // Alignment Mask + Bitfield<16> wp; // Write Protect + Bitfield<5> ne; // Numeric Error + Bitfield<4> et; // Extension Type + Bitfield<3> ts; // Task Switched + Bitfield<2> em; // Emulation + Bitfield<1> mp; // Monitor Coprocessor + Bitfield<0> pe; // Protection Enabled EndBitUnion(CR0) // Page Fault Virtual Address @@ -297,42 +499,217 @@ namespace X86ISA EndBitUnion(CR2) BitUnion64(CR3) - Bitfield<51, 12> longPDTB; // Long Mode Page-Directory-Table + Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table // Base Address - Bitfield<31, 12> PDTB; // Non-PAE Addressing Page-Directory-Table + Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table // Base Address - Bitfield<31, 5> PAEPDTB; // PAE Addressing Page-Directory-Table + Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table // Base Address - Bitfield<4> PCD; // Page-Level Cache Disable - Bitfield<3> PWT; // Page-Level Writethrough + Bitfield<4> pcd; // Page-Level Cache Disable + Bitfield<3> pwt; // Page-Level Writethrough EndBitUnion(CR3) BitUnion64(CR4) - Bitfield<10> OSXMMEXCPT; // Operating System Unmasked + Bitfield<10> osxmmexcpt; // Operating System Unmasked // Exception Support - Bitfield<9> OSFXSR; // Operating System FXSave/FSRSTOR Support - Bitfield<8> PCE; // Performance-Monitoring Counter Enable - Bitfield<7> PGE; // Page-Global Enable - Bitfield<6> MCE; // Machine Check Enable - Bitfield<5> PAE; // Physical-Address Extension - Bitfield<4> PSE; // Page Size Extensions - Bitfield<3> DE; // Debugging Extensions - Bitfield<2> TSD; // Time Stamp Disable - Bitfield<1> PVI; // Protected-Mode Virtual Interrupts - Bitfield<0> VME; // Virtual-8086 Mode Extensions + Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support + Bitfield<8> pce; // Performance-Monitoring Counter Enable + Bitfield<7> pge; // Page-Global Enable + Bitfield<6> mce; // Machine Check Enable + Bitfield<5> pae; // Physical-Address Extension + Bitfield<4> pse; // Page Size Extensions + Bitfield<3> de; // Debugging Extensions + Bitfield<2> tsd; // Time Stamp Disable + Bitfield<1> pvi; // Protected-Mode Virtual Interrupts + Bitfield<0> vme; // Virtual-8086 Mode Extensions EndBitUnion(CR4) BitUnion64(CR8) - Bitfield<3, 0> TPR; // Task Priority Register - EndBitUnion(CR4) + Bitfield<3, 0> tpr; // Task Priority Register + EndBitUnion(CR8) + + // MTRR capabilities + BitUnion64(MTRRcap) + Bitfield<7, 0> vcnt; // Variable-Range Register Count + Bitfield<8> fix; // Fixed-Range Registers + Bitfield<10> wc; // Write-Combining + EndBitUnion(MTRRcap) + + /** + * SYSENTER configuration registers + */ + BitUnion64(SysenterCS) + Bitfield<15, 0> targetCS; + EndBitUnion(SysenterCS) + + BitUnion64(SysenterESP) + Bitfield<31, 0> targetESP; + EndBitUnion(SysenterESP) + + BitUnion64(SysenterEIP) + Bitfield<31, 0> targetEIP; + EndBitUnion(SysenterEIP) + + /** + * Global machine check registers + */ + BitUnion64(McgCap) + Bitfield<7, 0> count; // Number of error reporting register banks + Bitfield<8> MCGCP; // MCG_CTL register present. + EndBitUnion(McgCap) + + BitUnion64(McgStatus) + Bitfield<0> ripv; // Restart-IP valid + Bitfield<1> eipv; // Error-IP valid + Bitfield<2> mcip; // Machine check in-progress + EndBitUnion(McgStatus) + + BitUnion64(DebugCtlMsr) + Bitfield<0> lbr; // Last-branch record + Bitfield<1> btf; // Branch single step + Bitfield<2> pb0; // Performance monitoring pin control 0 + Bitfield<3> pb1; // Performance monitoring pin control 1 + Bitfield<4> pb2; // Performance monitoring pin control 2 + Bitfield<5> pb3; // Performance monitoring pin control 3 + /*uint64_t pb(int index) + { + return bits(__data, index + 2); + }*/ + EndBitUnion(DebugCtlMsr) + + BitUnion64(MtrrPhysBase) + Bitfield<7, 0> type; // Default memory type + Bitfield<51, 12> physbase; // Range physical base address + EndBitUnion(MtrrPhysBase) + + BitUnion64(MtrrPhysMask) + Bitfield<11> valid; // MTRR pair enable + Bitfield<51, 12> physmask; // Range physical mask + EndBitUnion(MtrrPhysMask) + + BitUnion64(MtrrFixed) + /*uint64_t type(int index) + { + return bits(__data, index * 8 + 7, index * 8); + }*/ + EndBitUnion(MtrrFixed) + + BitUnion64(Pat) + /*uint64_t pa(int index) + { + return bits(__data, index * 8 + 2, index * 8); + }*/ + EndBitUnion(Pat) + + BitUnion64(MtrrDefType) + Bitfield<7, 0> type; // Default type + Bitfield<10> fe; // Fixed range enable + Bitfield<11> e; // MTRR enable + EndBitUnion(MtrrDefType) + + /** + * Machine check + */ + BitUnion64(McStatus) + Bitfield<15,0> mcaErrorCode; + Bitfield<31,16> modelSpecificCode; + Bitfield<56,32> otherInfo; + Bitfield<57> pcc; // Processor-context corrupt + Bitfield<58> addrv; // Error-address register valid + Bitfield<59> miscv; // Miscellaneous-error register valid + Bitfield<60> en; // Error condition enabled + Bitfield<61> uc; // Uncorrected error + Bitfield<62> over; // Status register overflow + Bitfield<63> val; // Valid + EndBitUnion(McStatus) + + BitUnion64(McCtl) + /*uint64_t en(int index) + { + return bits(__data, index); + }*/ + EndBitUnion(McCtl) + + // Extended feature enable register + BitUnion64(Efer) + Bitfield<0> sce; // System call extensions + Bitfield<8> lme; // Long mode enable + Bitfield<10> lma; // Long mode active + Bitfield<11> nxe; // No-execute enable + Bitfield<12> svme; // Secure virtual machine enable + Bitfield<14> ffxsr; // Fast fxsave/fxrstor + EndBitUnion(Efer) + + BitUnion64(Star) + Bitfield<31,0> targetEip; + Bitfield<47,32> syscallCsAndSs; + Bitfield<63,48> sysretCsAndSs; + EndBitUnion(Star) + + BitUnion64(SfMask) + Bitfield<31,0> mask; + EndBitUnion(SfMask) + + BitUnion64(PerfEvtSel) + Bitfield<7,0> eventMask; + Bitfield<15,8> unitMask; + Bitfield<16> usr; // User mode + Bitfield<17> os; // Operating-system mode + Bitfield<18> e; // Edge detect + Bitfield<19> pc; // Pin control + Bitfield<20> intEn; // Interrupt enable + Bitfield<22> en; // Counter enable + Bitfield<23> inv; // Invert mask + Bitfield<31,24> counterMask; + EndBitUnion(PerfEvtSel) + + BitUnion32(Syscfg) + Bitfield<18> mfde; // MtrrFixDramEn + Bitfield<19> mfdm; // MtrrFixDramModEn + Bitfield<20> mvdm; // MtrrVarDramEn + Bitfield<21> tom2; // MtrrTom2En + EndBitUnion(Syscfg) + + BitUnion64(IorrBase) + Bitfield<3> wr; // WrMem Enable + Bitfield<4> rd; // RdMem Enable + Bitfield<51,12> physbase; // Range physical base address + EndBitUnion(IorrBase) + + BitUnion64(IorrMask) + Bitfield<11> v; // I/O register pair enable (valid) + Bitfield<51,12> physmask; // Range physical mask + EndBitUnion(IorrMask) + + BitUnion64(Tom) + Bitfield<51,23> physAddr; // Top of memory physical address + EndBitUnion(Tom) + + BitUnion64(VmCrMsr) + Bitfield<0> dpd; + Bitfield<1> rInit; + Bitfield<2> disA20M; + EndBitUnion(VmCrMsr) + + BitUnion64(IgnneMsr) + Bitfield<0> ignne; + EndBitUnion(IgnneMsr) + + BitUnion64(SmmCtlMsr) + Bitfield<0> dismiss; + Bitfield<1> enter; + Bitfield<2> smiCycle; + Bitfield<3> exit; + Bitfield<4> rsmCycle; + EndBitUnion(SmmCtlMsr) /** * Segment Selector */ BitUnion64(SegSelector) - Bitfield<15, 3> SI; // Selector Index - Bitfield<2> TI; // Table Indicator - Bitfield<1, 0> RPL; // Requestor Privilege Level + Bitfield<15, 3> si; // Selector Index + Bitfield<2> ti; // Table Indicator + Bitfield<1, 0> rpl; // Requestor Privilege Level EndBitUnion(SegSelector) /** @@ -342,39 +719,48 @@ namespace X86ISA BitUnion64(SegDescriptor) Bitfield<63, 56> baseHigh; Bitfield<39, 16> baseLow; - Bitfield<55> G; // Granularity - Bitfield<54> D; // Default Operand Size - Bitfield<54> B; // Default Operand Size - Bitfield<53> L; // Long Attribute Bit - Bitfield<52> AVL; // Available To Software + Bitfield<55> g; // Granularity + Bitfield<54> d; // Default Operand Size + Bitfield<54> b; // Default Operand Size + Bitfield<53> l; // Long Attribute Bit + Bitfield<52> avl; // Available To Software Bitfield<51, 48> limitHigh; Bitfield<15, 0> limitLow; - Bitfield<47> P; // Present - Bitfield<46, 45> DPL; // Descriptor Privilege-Level - Bitfield<44> S; // System + Bitfield<47> p; // Present + Bitfield<46, 45> dpl; // Descriptor Privilege-Level + Bitfield<44> s; // System SubBitUnion(type, 43, 40) // Specifies whether this descriptor is for code or data. Bitfield<43> codeOrData; // These bit fields are for code segments - Bitfield<42> C; // Conforming - Bitfield<41> R; // Readable + Bitfield<42> c; // Conforming + Bitfield<41> r; // Readable // These bit fields are for data segments - Bitfield<42> E; // Expand-Down - Bitfield<41> W; // Writable + Bitfield<42> e; // Expand-Down + Bitfield<41> w; // Writable // This is used for both code and data segments. - Bitfield<40> A; // Accessed + Bitfield<40> a; // Accessed EndSubBitUnion(type) EndBitUnion(SegDescriptor) + BitUnion64(SegAttr) + Bitfield<0> writable; + Bitfield<1> readable; + Bitfield<2> expandDown; + Bitfield<4, 3> dpl; + Bitfield<5> defaultSize; + Bitfield<6> longMode; + EndBitUnion(SegAttr) + BitUnion64(GateDescriptor) Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset Bitfield<15, 0> offsetLow; // Target Code-Segment Offset Bitfield<31, 16> selector; // Target Code-Segment Selector - Bitfield<47> P; // Present - Bitfield<46, 45> DPL; // Descriptor Privilege-Level + Bitfield<47> p; // Present + Bitfield<46, 45> dpl; // Descriptor Privilege-Level Bitfield<43, 40> type; Bitfield<36, 32> count; // Parameter Count EndBitUnion(GateDescriptor) diff --git a/src/arch/x86/mmaped_ipr.hh b/src/arch/x86/mmaped_ipr.hh index a33a3f4f0..9184ec4dc 100644 --- a/src/arch/x86/mmaped_ipr.hh +++ b/src/arch/x86/mmaped_ipr.hh @@ -65,6 +65,7 @@ */ #include "config/full_system.hh" +#include "cpu/base.hh" #include "cpu/thread_context.hh" #include "mem/packet.hh" @@ -75,7 +76,10 @@ namespace X86ISA { #if !FULL_SYSTEM panic("Shouldn't have a memory mapped register in SE\n"); +#else + pkt->set(xc->readMiscReg(pkt->getAddr() / sizeof(MiscReg))); #endif + return xc->getCpuPtr()->ticks(1); } inline Tick @@ -83,7 +87,11 @@ namespace X86ISA { #if !FULL_SYSTEM panic("Shouldn't have a memory mapped register in SE\n"); +#else + xc->setMiscReg(pkt->getAddr() / sizeof(MiscReg), + gtoh(pkt->get<uint64_t>())); #endif + return xc->getCpuPtr()->ticks(1); } }; diff --git a/src/arch/x86/pagetable.cc b/src/arch/x86/pagetable.cc new file mode 100644 index 000000000..e16d6e659 --- /dev/null +++ b/src/arch/x86/pagetable.cc @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/x86/isa_traits.hh" +#include "arch/x86/pagetable.hh" +#include "sim/serialize.hh" + +namespace X86ISA +{ + +TlbEntry::TlbEntry(Addr asn, Addr _vaddr, Addr _paddr) : + paddr(_paddr), vaddr(_vaddr), size(PageBytes), writable(true), user(true), + uncacheable(false), global(false), patBit(0), noExec(false) +{} + +void +TlbEntry::serialize(std::ostream &os) +{ +} + +void +TlbEntry::unserialize(Checkpoint *cp, const std::string §ion) +{ +} + +} diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh index 8ca179c86..cc614168c 100644 --- a/src/arch/x86/pagetable.hh +++ b/src/arch/x86/pagetable.hh @@ -58,9 +58,14 @@ #ifndef __ARCH_X86_PAGETABLE_HH__ #define __ARCH_X86_PAGETABLE_HH__ +#include <iostream> +#include <string> + #include "sim/host.hh" #include "base/misc.hh" +class Checkpoint; + namespace X86ISA { struct VAddr @@ -68,8 +73,43 @@ namespace X86ISA VAddr(Addr a) { panic("not implemented yet."); } }; - class PageTableEntry + struct TlbEntry { + // The base of the physical page. + Addr paddr; + + // The beginning of the virtual page this entry maps. + Addr vaddr; + // The size of the page this entry represents. + Addr size; + + // Read permission is always available, assuming it isn't blocked by + // other mechanisms. + bool writable; + // Whether this page is accesible without being in supervisor mode. + bool user; + // Whether to use write through or write back. M5 ignores this and + // lets the caches handle the writeback policy. + //bool pwt; + // Whether the page is cacheable or not. + bool uncacheable; + // Whether or not to kick this page out on a write to CR3. + bool global; + // A bit used to form an index into the PAT table. + bool patBit; + // Whether or not memory on this page can be executed. + bool noExec; + + TlbEntry(Addr asn, Addr _vaddr, Addr _paddr); + TlbEntry() {} + + Addr pageStart() + { + return paddr; + } + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); }; } diff --git a/src/arch/x86/predecoder.cc b/src/arch/x86/predecoder.cc index 7f8bc7abc..ace4a6b94 100644 --- a/src/arch/x86/predecoder.cc +++ b/src/arch/x86/predecoder.cc @@ -62,13 +62,15 @@ namespace X86ISA { - void Predecoder::reset() + void Predecoder::doReset() { origPC = basePC + offset; DPRINTF(Predecoder, "Setting origPC to %#x\n", origPC); emi.rex = 0; emi.legacy = 0; emi.opcode.num = 0; + emi.opcode.op = 0; + emi.opcode.prefixA = emi.opcode.prefixB = 0; immediateCollected = 0; emi.immediate = 0; @@ -96,7 +98,7 @@ namespace X86ISA switch(state) { case ResetState: - reset(); + doReset(); state = PrefixState; case PrefixState: state = doPrefixState(nextByte); diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh index 450ebd79b..6e41e8134 100644 --- a/src/arch/x86/predecoder.hh +++ b/src/arch/x86/predecoder.hh @@ -134,7 +134,7 @@ namespace X86ISA outOfBytes = true; } - void reset(); + void doReset(); //State machine state protected: @@ -182,6 +182,11 @@ namespace X86ISA emi.mode.submode = SixtyFourBitMode; } + void reset() + { + state = ResetState; + } + ThreadContext * getTC() { return tc; diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index 79422998d..c6246c76b 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -109,14 +109,9 @@ M5_64_auxv_t::M5_64_auxv_t(int64_t type, int64_t val) a_val = TheISA::htog(val); } -X86LiveProcess::X86LiveProcess(const std::string &nm, ObjectFile *objFile, - System *_system, int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid) - : LiveProcess(nm, objFile, _system, stdin_fd, stdout_fd, stderr_fd, - argv, envp, cwd, _uid, _euid, _gid, _egid, _pid, _ppid) +X86LiveProcess::X86LiveProcess(LiveProcessParams * params, + ObjectFile *objFile) + : LiveProcess(params, objFile) { brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); brk_point = roundUp(brk_point, VMPageSize); @@ -131,7 +126,7 @@ X86LiveProcess::X86LiveProcess(const std::string &nm, ObjectFile *objFile, // Set up region for mmaps. This was determined empirically and may not // always be correct. - mmap_start = mmap_end = 0x2aaaaaaab000; + mmap_start = mmap_end = (Addr)0x2aaaaaaab000ULL; } void X86LiveProcess::handleTrap(int trapNum, ThreadContext *tc) @@ -146,9 +141,64 @@ void X86LiveProcess::handleTrap(int trapNum, ThreadContext *tc) void X86LiveProcess::startup() { + if (checkpointRestored) + return; + argsInit(sizeof(IntReg), VMPageSize); - for(int i = 0; i < NUM_SEGMENTREGS; i++) - threadContexts[0]->setMiscRegNoEffect(MISCREG_ES_BASE + i, 0); + + for (int i = 0; i < threadContexts.size(); i++) { + ThreadContext * tc = threadContexts[i]; + + SegAttr dataAttr = 0; + dataAttr.writable = 1; + dataAttr.readable = 1; + dataAttr.expandDown = 0; + dataAttr.dpl = 3; + dataAttr.defaultSize = 0; + dataAttr.longMode = 1; + + //Initialize the segment registers. + for(int seg = 0; seg < NUM_SEGMENTREGS; seg++) { + tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); + tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); + } + + SegAttr csAttr = 0; + csAttr.writable = 0; + csAttr.readable = 1; + csAttr.expandDown = 0; + csAttr.dpl = 3; + csAttr.defaultSize = 0; + csAttr.longMode = 1; + + tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr); + + //Set up the registers that describe the operating mode. + CR0 cr0 = 0; + cr0.pg = 1; // Turn on paging. + cr0.cd = 0; // Don't disable caching. + cr0.nw = 0; // This is bit is defined to be ignored. + cr0.am = 0; // No alignment checking + cr0.wp = 0; // Supervisor mode can write read only pages + cr0.ne = 1; + cr0.et = 1; // This should always be 1 + cr0.ts = 0; // We don't do task switching, so causing fp exceptions + // would be pointless. + cr0.em = 0; // Allow x87 instructions to execute natively. + cr0.mp = 1; // This doesn't really matter, but the manual suggests + // setting it to one. + cr0.pe = 1; // We're definitely in protected mode. + tc->setMiscReg(MISCREG_CR0, cr0); + + Efer efer = 0; + efer.sce = 1; // Enable system call extensions. + efer.lme = 1; // Enable long mode. + efer.lma = 1; // Activate long mode. + efer.nxe = 1; // Enable nx support. + efer.svme = 0; // Disable svm support for now. It isn't implemented. + efer.ffxsr = 1; // Turn on fast fxsave and fxrstor. + tc->setMiscReg(MISCREG_EFER, efer); + } } void diff --git a/src/arch/x86/process.hh b/src/arch/x86/process.hh index a2fa258c8..5def9e13d 100644 --- a/src/arch/x86/process.hh +++ b/src/arch/x86/process.hh @@ -84,15 +84,7 @@ namespace X86ISA protected: std::vector<M5_64_auxv_t> auxv; - X86LiveProcess(const std::string &nm, ObjectFile *objFile, - System *_system, - int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid); + X86LiveProcess(LiveProcessParams * params, ObjectFile *objFile); void startup(); diff --git a/src/arch/x86/regfile.cc b/src/arch/x86/regfile.cc index 96283cada..c27ab08ba 100644 --- a/src/arch/x86/regfile.cc +++ b/src/arch/x86/regfile.cc @@ -85,6 +85,7 @@ * Authors: Gabe Black */ +#include "arch/x86/floatregs.hh" #include "arch/x86/regfile.hh" #include "base/trace.hh" #include "sim/serialize.hh" @@ -218,6 +219,15 @@ int X86ISA::flattenIntIndex(ThreadContext * tc, int reg) return (reg & ~(1 << 6)); } +int X86ISA::flattenFloatIndex(ThreadContext * tc, int reg) +{ + if (reg >= NUM_FLOATREGS) { + int top = tc->readMiscRegNoEffect(MISCREG_X87_TOP); + reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top); + } + return reg; +} + void RegFile::serialize(std::ostream &os) { intRegFile.serialize(os); diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh index d4425b04c..650181aca 100644 --- a/src/arch/x86/regfile.hh +++ b/src/arch/x86/regfile.hh @@ -149,6 +149,8 @@ namespace X86ISA int flattenIntIndex(ThreadContext * tc, int reg); + int flattenFloatIndex(ThreadContext * tc, int reg); + void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); diff --git a/src/arch/x86/stacktrace.cc b/src/arch/x86/stacktrace.cc new file mode 100644 index 000000000..300e8dcd0 --- /dev/null +++ b/src/arch/x86/stacktrace.cc @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +#include <string> + +#include "arch/x86/isa_traits.hh" +#include "arch/x86/stacktrace.hh" +#include "arch/x86/vtophys.hh" +#include "base/bitfield.hh" +#include "base/trace.hh" +#include "cpu/base.hh" +#include "cpu/thread_context.hh" +#include "sim/system.hh" + +using namespace std; +namespace X86ISA +{ + ProcessInfo::ProcessInfo(ThreadContext *_tc) + : tc(_tc) + { + Addr addr = 0; + + VirtualPort *vp; + + vp = tc->getVirtPort(); + + if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr)) + panic("thread info not compiled into kernel\n"); + thread_info_size = vp->readGtoH<int32_t>(addr); + + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr)) + panic("thread info not compiled into kernel\n"); + task_struct_size = vp->readGtoH<int32_t>(addr); + + if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr)) + panic("thread info not compiled into kernel\n"); + task_off = vp->readGtoH<int32_t>(addr); + + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr)) + panic("thread info not compiled into kernel\n"); + pid_off = vp->readGtoH<int32_t>(addr); + + if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr)) + panic("thread info not compiled into kernel\n"); + name_off = vp->readGtoH<int32_t>(addr); + + tc->delVirtPort(vp); + } + + Addr + ProcessInfo::task(Addr ksp) const + { + Addr base = ksp & ~0x3fff; + if (base == ULL(0xfffffc0000000000)) + return 0; + + Addr tsk; + + VirtualPort *vp; + + vp = tc->getVirtPort(); + tsk = vp->readGtoH<Addr>(base + task_off); + tc->delVirtPort(vp); + + return tsk; + } + + int + ProcessInfo::pid(Addr ksp) const + { + Addr task = this->task(ksp); + if (!task) + return -1; + + uint16_t pd; + + VirtualPort *vp; + + vp = tc->getVirtPort(); + pd = vp->readGtoH<uint16_t>(task + pid_off); + tc->delVirtPort(vp); + + return pd; + } + + string + ProcessInfo::name(Addr ksp) const + { + Addr task = this->task(ksp); + if (!task) + return "console"; + + char comm[256]; + CopyStringOut(tc, comm, task + name_off, sizeof(comm)); + if (!comm[0]) + return "startup"; + + return comm; + } + + StackTrace::StackTrace() + : tc(0), stack(64) + { + } + + StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst) + : tc(0), stack(64) + { + trace(_tc, inst); + } + + StackTrace::~StackTrace() + { + } + + void + StackTrace::trace(ThreadContext *_tc, bool is_call) + { + } + + bool + StackTrace::isEntry(Addr addr) + { + return false; + } + + bool + StackTrace::decodeStack(MachInst inst, int &disp) + { + disp = 0; + return true; + } + + bool + StackTrace::decodeSave(MachInst inst, int ®, int &disp) + { + reg = 0; + disp = 0; + return true; + } + + /* + * Decode the function prologue for the function we're in, and note + * which registers are stored where, and how large the stack frame is. + */ + bool + StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, + int &size, Addr &ra) + { + size = 0; + ra = 0; + + for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) { + MachInst inst; + CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst)); + + int reg, disp; + if (decodeStack(inst, disp)) { + if (size) { + // panic("decoding frame size again"); + return true; + } + size += disp; + } else if (decodeSave(inst, reg, disp)) { + if (!ra && reg == ReturnAddressReg) { + CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr)); + if (!ra) { + // panic("no return address value pc=%#x\n", pc); + return false; + } + } + } + } + + return true; + } + +#if TRACING_ON + void + StackTrace::dump() + { + StringWrap name(tc->getCpuPtr()->name()); + SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; + + DPRINTFN("------ Stack ------\n"); + + string symbol; + for (int i = 0, size = stack.size(); i < size; ++i) { + Addr addr = stack[size - i - 1]; + if (addr == user) + symbol = "user"; + else if (addr == console) + symbol = "console"; + else if (addr == unknown) + symbol = "unknown"; + else + symtab->findSymbol(addr, symbol); + + DPRINTFN("%#x: %s\n", addr, symbol); + } + } +#endif +} diff --git a/src/arch/x86/system.cc b/src/arch/x86/system.cc new file mode 100644 index 000000000..0b770fc83 --- /dev/null +++ b/src/arch/x86/system.cc @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/x86/system.hh" +#include "arch/vtophys.hh" +#include "base/remote_gdb.hh" +#include "base/loader/object_file.hh" +#include "base/loader/symtab.hh" +#include "base/trace.hh" +#include "mem/physical.hh" +#include "params/X86System.hh" +#include "sim/byteswap.hh" + + +using namespace BigEndianGuest; + +X86System::X86System(Params *p) + : System(p) +{ +} + +X86System::~X86System() +{ +} + +void +X86System::serialize(std::ostream &os) +{ + System::serialize(os); +} + + +void +X86System::unserialize(Checkpoint *cp, const std::string §ion) +{ + System::unserialize(cp,section); +} + +X86System * +X86SystemParams::create() +{ + return new X86System(this); +} diff --git a/src/arch/x86/system.hh b/src/arch/x86/system.hh new file mode 100644 index 000000000..ce44651c6 --- /dev/null +++ b/src/arch/x86/system.hh @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_X86_SYSTEM_HH__ +#define __ARCH_X86_SYSTEM_HH__ + +#include <string> +#include <vector> + +#include "base/loader/symtab.hh" +#include "cpu/pc_event.hh" +#include "kern/system_events.hh" +#include "params/X86System.hh" +#include "sim/sim_object.hh" +#include "sim/system.hh" + +class X86System : public System +{ + public: + typedef X86SystemParams Params; + X86System(Params *p); + ~X86System(); + +/** + * Serialization stuff + */ + public: + virtual void serialize(std::ostream &os); + virtual void unserialize(Checkpoint *cp, const std::string §ion); + + protected: + const Params *params() const { return (const Params *)_params; } + + virtual Addr fixFuncEventAddr(Addr addr) + { + //XXX This may eventually have to do something useful. + return addr; + } +}; + +#endif + diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index d2db8cb0b..6afee6d72 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -57,25 +57,509 @@ #include <cstring> +#include "config/full_system.hh" + +#include "arch/x86/pagetable.hh" #include "arch/x86/tlb.hh" -#include "params/X86DTB.hh" -#include "params/X86ITB.hh" -#include "sim/serialize.hh" +#include "arch/x86/x86_traits.hh" +#include "base/bitfield.hh" +#include "base/trace.hh" +#include "cpu/thread_context.hh" +#include "cpu/base.hh" +#include "mem/packet_access.hh" +#include "mem/request.hh" +#include "sim/system.hh" namespace X86ISA { - void - TlbEntry::serialize(std::ostream &os) - { - SERIALIZE_SCALAR(pageStart); + +TLB::TLB(const Params *p) : SimObject(p), size(p->size) +{ + tlb = new TlbEntry[size]; + std::memset(tlb, 0, sizeof(TlbEntry) * size); + + for (int x = 0; x < size; x++) + freeList.push_back(&tlb[x]); +} + +void +TLB::insert(Addr vpn, TlbEntry &entry) +{ + //TODO Deal with conflicting entries + + TlbEntry *newEntry = NULL; + if (!freeList.empty()) { + newEntry = freeList.front(); + freeList.pop_front(); + } else { + newEntry = entryList.back(); + entryList.pop_back(); + } + *newEntry = entry; + newEntry->vaddr = vpn; + entryList.push_front(newEntry); +} + +TlbEntry * +TLB::lookup(Addr va, bool update_lru) +{ + //TODO make this smarter at some point + EntryList::iterator entry; + for (entry = entryList.begin(); entry != entryList.end(); entry++) { + if ((*entry)->vaddr <= va && (*entry)->vaddr + (*entry)->size > va) { + DPRINTF(TLB, "Matched vaddr %#x to entry starting at %#x " + "with size %#x.\n", va, (*entry)->vaddr, (*entry)->size); + TlbEntry *e = *entry; + if (update_lru) { + entryList.erase(entry); + entryList.push_front(e); + } + return e; + } + } + return NULL; +} + +void +TLB::invalidateAll() +{ +} + +void +TLB::invalidateNonGlobal() +{ +} + +void +TLB::demapPage(Addr va) +{ +} + +template<class TlbFault> +Fault +TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute) +{ + Addr vaddr = req->getVaddr(); + DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); + uint32_t flags = req->getFlags(); + bool storeCheck = flags & StoreCheck; + + int seg = flags & mask(3); + + //XXX Junk code to surpress the warning + if (storeCheck); + + // If this is true, we're dealing with a request to read an internal + // value. + if (seg == NUM_SEGMENTREGS) { + Addr prefix = vaddr & IntAddrPrefixMask; + if (prefix == IntAddrPrefixCPUID) { + panic("CPUID memory space not yet implemented!\n"); + } else if (prefix == IntAddrPrefixMSR) { + req->setMmapedIpr(true); + Addr regNum = 0; + switch (vaddr & ~IntAddrPrefixMask) { + case 0x10: + regNum = MISCREG_TSC; + break; + case 0xFE: + regNum = MISCREG_MTRRCAP; + break; + case 0x174: + regNum = MISCREG_SYSENTER_CS; + break; + case 0x175: + regNum = MISCREG_SYSENTER_ESP; + break; + case 0x176: + regNum = MISCREG_SYSENTER_EIP; + break; + case 0x179: + regNum = MISCREG_MCG_CAP; + break; + case 0x17A: + regNum = MISCREG_MCG_STATUS; + break; + case 0x17B: + regNum = MISCREG_MCG_CTL; + break; + case 0x1D9: + regNum = MISCREG_DEBUG_CTL_MSR; + break; + case 0x1DB: + regNum = MISCREG_LAST_BRANCH_FROM_IP; + break; + case 0x1DC: + regNum = MISCREG_LAST_BRANCH_TO_IP; + break; + case 0x1DD: + regNum = MISCREG_LAST_EXCEPTION_FROM_IP; + break; + case 0x1DE: + regNum = MISCREG_LAST_EXCEPTION_TO_IP; + break; + case 0x200: + regNum = MISCREG_MTRR_PHYS_BASE_0; + break; + case 0x201: + regNum = MISCREG_MTRR_PHYS_MASK_0; + break; + case 0x202: + regNum = MISCREG_MTRR_PHYS_BASE_1; + break; + case 0x203: + regNum = MISCREG_MTRR_PHYS_MASK_1; + break; + case 0x204: + regNum = MISCREG_MTRR_PHYS_BASE_2; + break; + case 0x205: + regNum = MISCREG_MTRR_PHYS_MASK_2; + break; + case 0x206: + regNum = MISCREG_MTRR_PHYS_BASE_3; + break; + case 0x207: + regNum = MISCREG_MTRR_PHYS_MASK_3; + break; + case 0x208: + regNum = MISCREG_MTRR_PHYS_BASE_4; + break; + case 0x209: + regNum = MISCREG_MTRR_PHYS_MASK_4; + break; + case 0x20A: + regNum = MISCREG_MTRR_PHYS_BASE_5; + break; + case 0x20B: + regNum = MISCREG_MTRR_PHYS_MASK_5; + break; + case 0x20C: + regNum = MISCREG_MTRR_PHYS_BASE_6; + break; + case 0x20D: + regNum = MISCREG_MTRR_PHYS_MASK_6; + break; + case 0x20E: + regNum = MISCREG_MTRR_PHYS_BASE_7; + break; + case 0x20F: + regNum = MISCREG_MTRR_PHYS_MASK_7; + break; + case 0x250: + regNum = MISCREG_MTRR_FIX_64K_00000; + break; + case 0x258: + regNum = MISCREG_MTRR_FIX_16K_80000; + break; + case 0x259: + regNum = MISCREG_MTRR_FIX_16K_A0000; + break; + case 0x268: + regNum = MISCREG_MTRR_FIX_4K_C0000; + break; + case 0x269: + regNum = MISCREG_MTRR_FIX_4K_C8000; + break; + case 0x26A: + regNum = MISCREG_MTRR_FIX_4K_D0000; + break; + case 0x26B: + regNum = MISCREG_MTRR_FIX_4K_D8000; + break; + case 0x26C: + regNum = MISCREG_MTRR_FIX_4K_E0000; + break; + case 0x26D: + regNum = MISCREG_MTRR_FIX_4K_E8000; + break; + case 0x26E: + regNum = MISCREG_MTRR_FIX_4K_F0000; + break; + case 0x26F: + regNum = MISCREG_MTRR_FIX_4K_F8000; + break; + case 0x277: + regNum = MISCREG_PAT; + break; + case 0x2FF: + regNum = MISCREG_DEF_TYPE; + break; + case 0x400: + regNum = MISCREG_MC0_CTL; + break; + case 0x404: + regNum = MISCREG_MC1_CTL; + break; + case 0x408: + regNum = MISCREG_MC2_CTL; + break; + case 0x40C: + regNum = MISCREG_MC3_CTL; + break; + case 0x410: + regNum = MISCREG_MC4_CTL; + break; + case 0x401: + regNum = MISCREG_MC0_STATUS; + break; + case 0x405: + regNum = MISCREG_MC1_STATUS; + break; + case 0x409: + regNum = MISCREG_MC2_STATUS; + break; + case 0x40D: + regNum = MISCREG_MC3_STATUS; + break; + case 0x411: + regNum = MISCREG_MC4_STATUS; + break; + case 0x402: + regNum = MISCREG_MC0_ADDR; + break; + case 0x406: + regNum = MISCREG_MC1_ADDR; + break; + case 0x40A: + regNum = MISCREG_MC2_ADDR; + break; + case 0x40E: + regNum = MISCREG_MC3_ADDR; + break; + case 0x412: + regNum = MISCREG_MC4_ADDR; + break; + case 0x403: + regNum = MISCREG_MC0_MISC; + break; + case 0x407: + regNum = MISCREG_MC1_MISC; + break; + case 0x40B: + regNum = MISCREG_MC2_MISC; + break; + case 0x40F: + regNum = MISCREG_MC3_MISC; + break; + case 0x413: + regNum = MISCREG_MC4_MISC; + break; + case 0xC0000080: + regNum = MISCREG_EFER; + break; + case 0xC0000081: + regNum = MISCREG_STAR; + break; + case 0xC0000082: + regNum = MISCREG_LSTAR; + break; + case 0xC0000083: + regNum = MISCREG_CSTAR; + break; + case 0xC0000084: + regNum = MISCREG_SF_MASK; + break; + case 0xC0000100: + regNum = MISCREG_FS_BASE; + break; + case 0xC0000101: + regNum = MISCREG_GS_BASE; + break; + case 0xC0000102: + regNum = MISCREG_KERNEL_GS_BASE; + break; + case 0xC0000103: + regNum = MISCREG_TSC_AUX; + break; + case 0xC0010000: + regNum = MISCREG_PERF_EVT_SEL0; + break; + case 0xC0010001: + regNum = MISCREG_PERF_EVT_SEL1; + break; + case 0xC0010002: + regNum = MISCREG_PERF_EVT_SEL2; + break; + case 0xC0010003: + regNum = MISCREG_PERF_EVT_SEL3; + break; + case 0xC0010004: + regNum = MISCREG_PERF_EVT_CTR0; + break; + case 0xC0010005: + regNum = MISCREG_PERF_EVT_CTR1; + break; + case 0xC0010006: + regNum = MISCREG_PERF_EVT_CTR2; + break; + case 0xC0010007: + regNum = MISCREG_PERF_EVT_CTR3; + break; + case 0xC0010010: + regNum = MISCREG_SYSCFG; + break; + case 0xC0010016: + regNum = MISCREG_IORR_BASE0; + break; + case 0xC0010017: + regNum = MISCREG_IORR_BASE1; + break; + case 0xC0010018: + regNum = MISCREG_IORR_MASK0; + break; + case 0xC0010019: + regNum = MISCREG_IORR_MASK1; + break; + case 0xC001001A: + regNum = MISCREG_TOP_MEM; + break; + case 0xC001001D: + regNum = MISCREG_TOP_MEM2; + break; + case 0xC0010114: + regNum = MISCREG_VM_CR; + break; + case 0xC0010115: + regNum = MISCREG_IGNNE; + break; + case 0xC0010116: + regNum = MISCREG_SMM_CTL; + break; + case 0xC0010117: + regNum = MISCREG_VM_HSAVE_PA; + break; + default: + return new GeneralProtection(0); + } + //The index is multiplied by the size of a MiscReg so that + //any memory dependence calculations will not see these as + //overlapping. + req->setPaddr(regNum * sizeof(MiscReg)); + return NoFault; + } else { + panic("Access to unrecognized internal address space %#x.\n", + prefix); + } } - void - TlbEntry::unserialize(Checkpoint *cp, const std::string §ion) - { - UNSERIALIZE_SCALAR(pageStart); + // Get cr0. This will tell us how to do translation. We'll assume it was + // verified to be correct and consistent when set. + CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); + + // If protected mode has been enabled... + if (cr0.pe) { + Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); + SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR); + // If we're not in 64-bit mode, do protection/limit checks + if (!efer.lma || !csAttr.longMode) { + SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); + if (!attr.writable && write) + return new GeneralProtection(0); + if (!attr.readable && !write && !execute) + return new GeneralProtection(0); + Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); + Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); + if (!attr.expandDown) { + // We don't have to worry about the access going around the + // end of memory because accesses will be broken up into + // pieces at boundaries aligned on sizes smaller than an + // entire address space. We do have to worry about the limit + // being less than the base. + if (limit < base) { + if (limit < vaddr + req->getSize() && vaddr < base) + return new GeneralProtection(0); + } else { + if (limit < vaddr + req->getSize()) + return new GeneralProtection(0); + } + } else { + if (limit < base) { + if (vaddr <= limit || vaddr + req->getSize() >= base) + return new GeneralProtection(0); + } else { + if (vaddr <= limit && vaddr + req->getSize() >= base) + return new GeneralProtection(0); + } + } + } + // If paging is enabled, do the translation. + if (cr0.pg) { + // The vaddr already has the segment base applied. + TlbEntry *entry = lookup(vaddr); + if (!entry) { +#if FULL_SYSTEM + return new TlbFault(); +#else + return new TlbFault(vaddr); +#endif + } else { + // Do paging protection checks. + Addr paddr = entry->paddr | (vaddr & mask(12)); + req->setPaddr(paddr); + } + } else { + //Use the address which already has segmentation applied. + req->setPaddr(vaddr); + } + } else { + // Real mode + req->setPaddr(vaddr); } + return NoFault; }; +Fault +DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) +{ + return TLB::translate<FakeDTLBFault>(req, tc, write, false); +} + +Fault +ITB::translate(RequestPtr &req, ThreadContext *tc) +{ + return TLB::translate<FakeITLBFault>(req, tc, false, true); +} + +#if FULL_SYSTEM + +Tick +DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) +{ + return tc->getCpuPtr()->ticks(1); +} + +Tick +DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) +{ + return tc->getCpuPtr()->ticks(1); +} + +#endif + +void +TLB::serialize(std::ostream &os) +{ +} + +void +TLB::unserialize(Checkpoint *cp, const std::string §ion) +{ +} + +void +DTB::serialize(std::ostream &os) +{ + TLB::serialize(os); +} + +void +DTB::unserialize(Checkpoint *cp, const std::string §ion) +{ + TLB::unserialize(cp, section); +} + +/* end namespace X86ISA */ } + X86ISA::ITB * X86ITBParams::create() { diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index 354443794..12739379c 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -58,38 +58,96 @@ #ifndef __ARCH_X86_TLB_HH__ #define __ARCH_X86_TLB_HH__ -#include <iostream> +#include <list> -#include "sim/host.hh" -#include "sim/tlb.hh" +#include "arch/x86/pagetable.hh" +#include "arch/x86/segmentregs.hh" +#include "config/full_system.hh" +#include "mem/request.hh" +#include "params/X86DTB.hh" +#include "params/X86ITB.hh" +#include "sim/faults.hh" +#include "sim/sim_object.hh" -class Checkpoint; +class ThreadContext; +class Packet; namespace X86ISA { - struct TlbEntry + static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS; + + class TLB : public SimObject { - Addr pageStart; - TlbEntry() {} - TlbEntry(Addr paddr) : pageStart(paddr) {} +#if !FULL_SYSTEM + protected: + friend class FakeITLBFault; + friend class FakeDTLBFault; +#endif + public: + typedef X86TLBParams Params; + TLB(const Params *p); + + void dumpAll(); + + TlbEntry *lookup(Addr va, bool update_lru = true); + + protected: + int size; + + TlbEntry * tlb; + + typedef std::list<TlbEntry *> EntryList; + EntryList freeList; + EntryList entryList; + + void insert(Addr vpn, TlbEntry &entry); - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); + void invalidateAll(); + + void invalidateNonGlobal(); + + void demapPage(Addr va); + + template<class TlbFault> + Fault translate(RequestPtr &req, ThreadContext *tc, + bool write, bool execute); + + public: + // Checkpointing + virtual void serialize(std::ostream &os); + virtual void unserialize(Checkpoint *cp, const std::string §ion); }; - class ITB : public GenericTLB + class ITB : public TLB { public: - ITB(const Params *p) : GenericTLB(p) - {} + typedef X86ITBParams Params; + ITB(const Params *p) : TLB(p) + { + } + + Fault translate(RequestPtr &req, ThreadContext *tc); + + friend class DTB; }; - class DTB : public GenericTLB + class DTB : public TLB { public: - DTB(const Params *p) : GenericTLB(p) - {} + typedef X86DTBParams Params; + DTB(const Params *p) : TLB(p) + { + } + Fault translate(RequestPtr &req, ThreadContext *tc, bool write); +#if FULL_SYSTEM + Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); + Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); +#endif + + // Checkpointing + virtual void serialize(std::ostream &os); + virtual void unserialize(Checkpoint *cp, const std::string §ion); }; -}; +} #endif // __ARCH_X86_TLB_HH__ diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh index c2c60e7cc..fd33b8383 100644 --- a/src/arch/x86/types.hh +++ b/src/arch/x86/types.hh @@ -257,7 +257,7 @@ namespace X86ISA typedef int RegContextVal; - typedef uint8_t RegIndex; + typedef uint16_t RegIndex; }; #endif // __ARCH_X86_TYPES_HH__ diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc new file mode 100644 index 000000000..0eee0c93e --- /dev/null +++ b/src/arch/x86/utility.cc @@ -0,0 +1,272 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/x86/intregs.hh" +#include "arch/x86/miscregs.hh" +#include "arch/x86/segmentregs.hh" +#include "arch/x86/utility.hh" +#include "arch/x86/x86_traits.hh" + +namespace X86ISA { + +uint64_t getArgument(ThreadContext *tc, int number, bool fp) { +#if FULL_SYSTEM + panic("getArgument() not implemented for x86!\n"); +#else + panic("getArgument() only implemented for FULL_SYSTEM\n"); + M5_DUMMY_RETURN +#endif +} + +# if FULL_SYSTEM +void initCPU(ThreadContext *tc, int cpuId) +{ + // The otherwise unmodified integer registers should be set to 0. + for (int index = 0; index < NUM_INTREGS; index++) { + tc->setIntReg(index, 0); + } + + // These next two loops zero internal microcode and implicit registers. + // They aren't specified by the ISA but are used internally by M5's + // implementation. + for (int index = 0; index < NumMicroIntRegs; index++) { + tc->setIntReg(INTREG_MICRO(index), 0); + } + + for (int index = 0; index < NumImplicitIntRegs; index++) { + tc->setIntReg(INTREG_IMPLICIT(index), 0); + } + + // Set integer register EAX to 0 to indicate that the optional BIST + // passed. No BIST actually runs, but software may still check this + // register for errors. + tc->setIntReg(INTREG_RAX, 0); + + //The following values are dictated by the architecture for after a RESET# + tc->setMiscReg(MISCREG_CR0, 0x0000000060000010); + tc->setMiscReg(MISCREG_CR2, 0); + tc->setMiscReg(MISCREG_CR3, 0); + tc->setMiscReg(MISCREG_CR4, 0); + tc->setMiscReg(MISCREG_CR8, 0); + + tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002); + + tc->setMiscReg(MISCREG_EFER, 0); + + SegAttr dataAttr = 0; + dataAttr.writable = 1; + dataAttr.readable = 1; + dataAttr.expandDown = 0; + dataAttr.dpl = 0; + dataAttr.defaultSize = 0; + + for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) { + tc->setMiscReg(MISCREG_SEG_SEL(seg), 0); + tc->setMiscReg(MISCREG_SEG_BASE(seg), 0); + tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff); + tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr); + } + + SegAttr codeAttr = 0; + codeAttr.writable = 0; + codeAttr.readable = 1; + codeAttr.expandDown = 0; + codeAttr.dpl = 0; + codeAttr.defaultSize = 0; + + tc->setMiscReg(MISCREG_CS, 0xf000); + tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000); + // This has the base value pre-added. + tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff); + tc->setMiscReg(MISCREG_CS_ATTR, codeAttr); + + tc->setPC(0x000000000000fff0 + + tc->readMiscReg(MISCREG_CS_BASE)); + tc->setNextPC(tc->readPC() + sizeof(MachInst)); + + tc->setMiscReg(MISCREG_GDTR_BASE, 0); + tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff); + + tc->setMiscReg(MISCREG_IDTR_BASE, 0); + tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); + + tc->setMiscReg(MISCREG_LDTR, 0); + tc->setMiscReg(MISCREG_LDTR_BASE, 0); + tc->setMiscReg(MISCREG_LDTR_LIMIT, 0xffff); + tc->setMiscReg(MISCREG_LDTR_ATTR, 0); + + tc->setMiscReg(MISCREG_TR, 0); + tc->setMiscReg(MISCREG_TR_BASE, 0); + tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff); + tc->setMiscReg(MISCREG_TR_ATTR, 0); + + // This value should be the family/model/stepping of the processor. + // (page 418). It should be consistent with the value from CPUID, but the + // actual value probably doesn't matter much. + tc->setIntReg(INTREG_RDX, 0); + + // TODO initialize x87, 64 bit, and 128 bit media state + + tc->setMiscReg(MISCREG_MTRRCAP, 0x0508); + for (int i = 0; i < 8; i++) { + tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0); + tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0); + } + tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0); + tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0); + tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0); + tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0); + tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0); + tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0); + tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0); + tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0); + tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0); + tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0); + tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0); + + tc->setMiscReg(MISCREG_DEF_TYPE, 0); + + tc->setMiscReg(MISCREG_MCG_CAP, 0x104); + tc->setMiscReg(MISCREG_MCG_STATUS, 0); + tc->setMiscReg(MISCREG_MCG_CTL, 0); + + for (int i = 0; i < 5; i++) { + tc->setMiscReg(MISCREG_MC_CTL(i), 0); + tc->setMiscReg(MISCREG_MC_STATUS(i), 0); + tc->setMiscReg(MISCREG_MC_ADDR(i), 0); + tc->setMiscReg(MISCREG_MC_MISC(i), 0); + } + + tc->setMiscReg(MISCREG_DR0, 0); + tc->setMiscReg(MISCREG_DR1, 0); + tc->setMiscReg(MISCREG_DR2, 0); + tc->setMiscReg(MISCREG_DR3, 0); + + tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0); + tc->setMiscReg(MISCREG_DR7, 0x0000000000000400); + + tc->setMiscReg(MISCREG_TSC, 0); + tc->setMiscReg(MISCREG_TSC_AUX, 0); + + for (int i = 0; i < 4; i++) { + tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0); + tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0); + } + + tc->setMiscReg(MISCREG_STAR, 0); + tc->setMiscReg(MISCREG_LSTAR, 0); + tc->setMiscReg(MISCREG_CSTAR, 0); + + tc->setMiscReg(MISCREG_SF_MASK, 0); + + tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0); + + tc->setMiscReg(MISCREG_SYSENTER_CS, 0); + tc->setMiscReg(MISCREG_SYSENTER_ESP, 0); + tc->setMiscReg(MISCREG_SYSENTER_EIP, 0); + + tc->setMiscReg(MISCREG_PAT, 0x0007040600070406); + + tc->setMiscReg(MISCREG_SYSCFG, 0x20601); + + tc->setMiscReg(MISCREG_IORR_BASE0, 0); + tc->setMiscReg(MISCREG_IORR_BASE1, 0); + + tc->setMiscReg(MISCREG_IORR_MASK0, 0); + tc->setMiscReg(MISCREG_IORR_MASK1, 0); + + tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000); + tc->setMiscReg(MISCREG_TOP_MEM2, 0x0); + + tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0); + tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0); + tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0); + tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0); + tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0); + + // Invalidate the caches (this should already be done for us) + + // TODO Turn on the APIC. This should be handled elsewhere but it isn't + // currently being handled at all. + + // TODO Set the SMRAM base address (SMBASE) to 0x00030000 + + tc->setMiscReg(MISCREG_VM_CR, 0); + tc->setMiscReg(MISCREG_IGNNE, 0); + tc->setMiscReg(MISCREG_SMM_CTL, 0); + tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0); +} + +#endif + +void startupCPU(ThreadContext *tc, int cpuId) +{ + if (cpuId == 0) { + // This is the boot strap processor (BSP). Initialize it to look like + // the boot loader has just turned control over to the 64 bit OS. + + // Enable paging, turn on long mode, etc. + + tc->activate(0); + } else { + // This is an application processor (AP). It should be initialized to + // look like only the BIOS POST has run on it and put then put it into + // a halted state. + } +} + +} //namespace X86_ISA diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh index 3f3f1cca3..477a76e0b 100644 --- a/src/arch/x86/utility.hh +++ b/src/arch/x86/utility.hh @@ -61,6 +61,7 @@ #include "arch/x86/types.hh" #include "base/hashmap.hh" #include "base/misc.hh" +#include "config/full_system.hh" #include "cpu/thread_context.hh" #include "sim/host.hh" @@ -87,6 +88,8 @@ namespace __hash_namespace { namespace X86ISA { + uint64_t getArgument(ThreadContext *tc, int number, bool fp); + static inline bool inUserMode(ThreadContext *tc) { @@ -138,15 +141,13 @@ namespace X86ISA template <class TC> void zeroRegisters(TC *tc); - inline void initCPU(ThreadContext *tc, int cpuId) - { - panic("initCPU not implemented!\n"); - } +#if FULL_SYSTEM - inline void startupCPU(ThreadContext *tc, int cpuId) - { - tc->activate(0); - } + void initCPU(ThreadContext *tc, int cpuId); + +#endif + + void startupCPU(ThreadContext *tc, int cpuId); }; #endif // __ARCH_X86_UTILITY_HH__ diff --git a/src/arch/x86/vtophys.cc b/src/arch/x86/vtophys.cc new file mode 100644 index 000000000..bac2748a4 --- /dev/null +++ b/src/arch/x86/vtophys.cc @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use of this software in source and binary forms, + * with or without modification, are permitted provided that the + * following conditions are met: + * + * The software must be used only for Non-Commercial Use which means any + * use which is NOT directed to receiving any direct monetary + * compensation for, or commercial advantage from such use. Illustrative + * examples of non-commercial use are academic research, personal study, + * teaching, education and corporate research & development. + * Illustrative examples of commercial use are distributing products for + * commercial advantage and providing services using the software for + * commercial advantage. + * + * If you wish to use this software or functionality therein that may be + * covered by patents for commercial use, please contact: + * Director of Intellectual Property Licensing + * Office of Strategy and Technology + * Hewlett-Packard Company + * 1501 Page Mill Road + * Palo Alto, California 94304 + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. Redistributions + * in binary form must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. Neither the name of + * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. No right of + * sublicense is granted herewith. Derivatives of the software and + * output created using the software may be prepared, but only for + * Non-Commercial Uses. Derivatives of the software may be shared with + * others provided: (i) the others agree to abide by the list of + * conditions herein which includes the Non-Commercial Use restrictions; + * and (ii) such Derivatives of the software include the above copyright + * notice to acknowledge the contribution from this software where + * applicable, this list of conditions and the disclaimer below. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include <string> + +#include "arch/x86/vtophys.hh" + +using namespace std; + +namespace X86ISA +{ + Addr vtophys(Addr vaddr) + { + return vaddr; + } + + Addr vtophys(ThreadContext *tc, Addr addr) + { + return addr; + } +} diff --git a/src/arch/x86/vtophys.hh b/src/arch/x86/vtophys.hh index 00d0f9499..be5e2700f 100644 --- a/src/arch/x86/vtophys.hh +++ b/src/arch/x86/vtophys.hh @@ -68,9 +68,6 @@ class FunctionalPort; namespace X86ISA { -PageTableEntry -kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, X86ISA::VAddr vaddr); - Addr vtophys(Addr vaddr); Addr vtophys(ThreadContext *tc, Addr vaddr); diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh index 33ec13372..dd9258db0 100644 --- a/src/arch/x86/x86_traits.hh +++ b/src/arch/x86/x86_traits.hh @@ -55,6 +55,8 @@ * Authors: Gabe Black */ +#include "sim/host.hh" + #ifndef __ARCH_X86_X86TRAITS_HH__ #define __ARCH_X86_X86TRAITS_HH__ @@ -80,6 +82,11 @@ namespace X86ISA const int NumSegments = 6; const int NumSysSegments = 4; + + const Addr IntAddrPrefixMask = ULL(0xffffffff00000000); + const Addr IntAddrPrefixCPUID = ULL(0x100000000); + const Addr IntAddrPrefixMSR = ULL(0x200000000); + const Addr IntAddrPrefixIO = ULL(0x300000000); } #endif //__ARCH_X86_X86TRAITS_HH__ diff --git a/src/base/SConscript b/src/base/SConscript index ca68bfb60..c31db894d 100644 --- a/src/base/SConscript +++ b/src/base/SConscript @@ -30,27 +30,6 @@ Import('*') -def make_cc(target, source, env): - assert(len(source) == 1) - assert(len(target) == 1) - - traceflags = {} - execfile(str(source[0]), traceflags) - func = traceflags['gen_cc'] - func(str(target[0])) - -def make_hh(target, source, env): - assert(len(source) == 1) - assert(len(target) == 1) - - traceflags = {} - execfile(str(source[0]), traceflags) - func = traceflags['gen_hh'] - func(str(target[0])) - -env.Command('traceflags.hh', 'traceflags.py', make_hh) -env.Command('traceflags.cc', 'traceflags.py', make_cc) - Source('annotate.cc') Source('bigint.cc') Source('circlebuf.cc') @@ -70,6 +49,7 @@ Source('misc.cc') Source('output.cc') Source('pollevent.cc') Source('random.cc') +Source('random_mt.cc') Source('range.cc') Source('remote_gdb.cc') Source('sat_counter.cc') @@ -78,7 +58,6 @@ Source('statistics.cc') Source('str.cc') Source('time.cc') Source('trace.cc') -Source('traceflags.cc') Source('userinfo.cc') Source('compression/lzss_compression.cc') @@ -100,4 +79,16 @@ if env['USE_MYSQL']: Source('mysql.cc') Source('stats/mysql.cc') -PySource('m5', 'traceflags.py') +TraceFlag('Annotate') +TraceFlag('GDBAcc') +TraceFlag('GDBExtra') +TraceFlag('GDBMisc') +TraceFlag('GDBRead') +TraceFlag('GDBRecv') +TraceFlag('GDBSend') +TraceFlag('GDBWrite') +TraceFlag('SQL') +TraceFlag('StatEvents') + +CompoundFlag('GDBAll', [ 'GDBMisc', 'GDBAcc', 'GDBRead', 'GDBWrite', 'GDBSend', + 'GDBRecv', 'GDBExtra' ]) diff --git a/src/base/bitunion.hh b/src/base/bitunion.hh index c02ca6155..7f7b06966 100644 --- a/src/base/bitunion.hh +++ b/src/base/bitunion.hh @@ -193,7 +193,7 @@ namespace BitfieldBackend class BitUnionOperators : public Base { public: - BitUnionOperators(Type & _data) + BitUnionOperators(Type const & _data) { Base::__data = _data; } @@ -206,20 +206,20 @@ namespace BitfieldBackend } Type - operator=(const Type & _data) + operator=(Type const & _data) { Base::__data = _data; return _data; } bool - operator<(const Base & base) const + operator<(Base const & base) const { return Base::__data < base.__data; } bool - operator==(const Base & base) const + operator==(Base const & base) const { return Base::__data == base.__data; } diff --git a/src/base/condcodes.hh b/src/base/condcodes.hh index efff12dc8..986e8d310 100644 --- a/src/base/condcodes.hh +++ b/src/base/condcodes.hh @@ -54,7 +54,7 @@ inline bool findOverflow(int width, uint64_t dest, uint64_t src1, uint64_t src2) { int shift = width - 1; - return ((src1 ^ ~src2) & (src1 ^ dest)) & (1 << shift); + return ((src1 ^ ~src2) & (src1 ^ dest)) & (1ULL << shift); } /** @@ -63,7 +63,7 @@ findOverflow(int width, uint64_t dest, uint64_t src1, uint64_t src2) { inline bool findParity(int width, uint64_t dest) { - dest &= width; + dest &= mask(width); dest ^= (dest >> 32); dest ^= (dest >> 16); dest ^= (dest >> 8); diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc index ecce175b2..23df1c5ba 100644 --- a/src/base/loader/elf_object.cc +++ b/src/base/loader/elf_object.cc @@ -176,7 +176,7 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data) if(phdr.p_offset <= e_phoff && phdr.p_offset + phdr.p_filesz > e_phoff) { - result->_programHeaderTable = phdr.p_vaddr + e_phoff; + result->_programHeaderTable = phdr.p_paddr + e_phoff; break; } } @@ -216,50 +216,76 @@ ElfObject::ElfObject(const string &_filename, int _fd, entry = ehdr.e_entry; - // initialize segment sizes to 0 in case they're not present text.size = data.size = bss.size = 0; + int secIdx = 1; + Elf_Scn *section; + GElf_Shdr shdr; + + // The first address of some important sections. + Addr textSecStart = 0; + Addr dataSecStart = 0; + Addr bssSecStart = 0; + + // Get the first section + section = elf_getscn(elf, secIdx); + + // Find the beginning of the most interesting sections. + while (section != NULL) { + gelf_getshdr(section, &shdr); + char * secName = elf_strptr(elf, ehdr.e_shstrndx, shdr.sh_name); + + if (!strcmp(".text", secName)) { + textSecStart = shdr.sh_addr; + } else if (!strcmp(".data", secName)) { + dataSecStart = shdr.sh_addr; + } else if (!strcmp(".bss", secName)) { + bssSecStart = shdr.sh_addr; + } + + section = elf_getscn(elf, ++secIdx); + } + + // Go through all the segments in the program, record them, and scrape + // out information about the text, data, and bss areas needed by other + // code. for (int i = 0; i < ehdr.e_phnum; ++i) { GElf_Phdr phdr; if (gelf_getphdr(elf, i, &phdr) == 0) { - panic("gelf_getphdr failed for section %d", i); + panic("gelf_getphdr failed for segment %d.", i); } // for now we don't care about non-loadable segments if (!(phdr.p_type & PT_LOAD)) continue; - // the headers don't explicitly distinguish text from data, - // but empirically the text segment comes first. - if (text.size == 0) { // haven't seen text segment yet - text.baseAddr = phdr.p_vaddr; - text.size = phdr.p_filesz; - text.fileImage = fileData + phdr.p_offset; - // if there's any padding at the end that's not in the - // file, call it the bss. This happens in the "text" - // segment if there's only one loadable segment (as for - // kernel images). + // Check to see if this segment contains the bss section. + if (phdr.p_paddr <= bssSecStart && + phdr.p_paddr + phdr.p_memsz > bssSecStart && + phdr.p_memsz - phdr.p_filesz > 0) { + bss.baseAddr = phdr.p_paddr + phdr.p_filesz; bss.size = phdr.p_memsz - phdr.p_filesz; - bss.baseAddr = phdr.p_vaddr + phdr.p_filesz; bss.fileImage = NULL; - } else if (data.size == 0) { // have text, this must be data - data.baseAddr = phdr.p_vaddr; + } + + // Check to see if this is the text or data segment + if (phdr.p_vaddr <= textSecStart && + phdr.p_vaddr + phdr.p_filesz > textSecStart) { + text.baseAddr = phdr.p_paddr; + text.size = phdr.p_filesz; + text.fileImage = fileData + phdr.p_offset; + } else if (phdr.p_vaddr <= dataSecStart && + phdr.p_vaddr + phdr.p_filesz > dataSecStart) { + data.baseAddr = phdr.p_paddr; data.size = phdr.p_filesz; data.fileImage = fileData + phdr.p_offset; - // if there's any padding at the end that's not in the - // file, call it the bss. Warn if this happens for both - // the text & data segments (should only have one bss). - if (phdr.p_memsz - phdr.p_filesz > 0 && bss.size != 0) { - warn("Two implied bss segments in file!\n"); - } - bss.size = phdr.p_memsz - phdr.p_filesz; - bss.baseAddr = phdr.p_vaddr + phdr.p_filesz; - bss.fileImage = NULL; } else { - warn("More than two loadable segments in ELF object."); - warn("Ignoring segment @ 0x%x length 0x%x.", - phdr.p_vaddr, phdr.p_filesz); + Segment extra; + extra.baseAddr = phdr.p_paddr; + extra.size = phdr.p_filesz; + extra.fileImage = fileData + phdr.p_offset; + extraSegments.push_back(extra); } } @@ -343,6 +369,22 @@ ElfObject::loadLocalSymbols(SymbolTable *symtab, Addr addrMask) return loadSomeSymbols(symtab, STB_LOCAL); } +bool +ElfObject::loadSections(Port *memPort, Addr addrMask) +{ + if (!ObjectFile::loadSections(memPort, addrMask)) + return false; + + vector<Segment>::iterator extraIt; + for (extraIt = extraSegments.begin(); + extraIt != extraSegments.end(); extraIt++) { + if (!loadSection(&(*extraIt), memPort, addrMask)) { + return false; + } + } + return true; +} + void ElfObject::getSections() { diff --git a/src/base/loader/elf_object.hh b/src/base/loader/elf_object.hh index 3e7c85874..5c5f6907d 100644 --- a/src/base/loader/elf_object.hh +++ b/src/base/loader/elf_object.hh @@ -33,11 +33,15 @@ #include "base/loader/object_file.hh" #include <set> +#include <vector> class ElfObject : public ObjectFile { protected: + //The global definition of a "Section" is closest to elf's segments. + typedef ObjectFile::Section Segment; + //These values are provided to a linux process by the kernel, so we //need to keep them around. Addr _programHeaderTable; @@ -55,9 +59,13 @@ class ElfObject : public ObjectFile void getSections(); bool sectionExists(std::string sec); + std::vector<Segment> extraSegments; + public: virtual ~ElfObject() {} + bool loadSections(Port *memPort, + Addr addrMask = std::numeric_limits<Addr>::max()); virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr addrMask = std::numeric_limits<Addr>::max()); virtual bool loadLocalSymbols(SymbolTable *symtab, Addr addrMask = diff --git a/src/base/random.cc b/src/base/random.cc index 8a2e3c1c0..7daa90b9c 100644 --- a/src/base/random.cc +++ b/src/base/random.cc @@ -29,60 +29,88 @@ * Ali Saidi */ -#ifdef __SUNPRO_CC -#include <stdlib.h> -#include <math.h> -#endif - -#include <cstdlib> -#include <cmath> - #include "base/fenv.hh" +#include "base/intmath.hh" +#include "base/misc.hh" #include "base/random.hh" +#include "sim/serialize.hh" using namespace std; -uint32_t -getInt32() +Random::Random() { - return mrand48() & 0xffffffff; + // default random seed taken from original source + init(5489); } -double -getDouble() +Random::Random(uint32_t s) { - return drand48(); + init(s); } -double -m5round(double r) +Random::Random(uint32_t init_key[], int key_length) { -#if defined(__sun) - double val; - int oldrnd = m5_fegetround(); - m5_fesetround(M5_FE_TONEAREST); - val = rint(r); - m5_fesetround(oldrnd); - return val; -#else - return round(r); -#endif + init(init_key, key_length); } -int64_t -getUniform(int64_t min, int64_t max) +Random::~Random() { - double r; - r = drand48() * (max-min) + min; +} - return (int64_t)m5round(r); +// To preserve the uniform random distribution between min and max, +// and allow all numbers to be represented, we generate a uniform +// random number to the nearest power of two greater than max. If +// this number doesn't fall between 0 and max, we try again. Anything +// else would skew the distribution. +uint32_t +Random::genrand(uint32_t max) +{ + int log = ceilLog2(max); + int shift = (sizeof(uint32_t) * 8 - log); + uint32_t random; + + do { + random = genrand() >> shift; + } while (random > max); + + return random; } uint64_t -getUniformPos(uint64_t min, uint64_t max) +Random::genrand(uint64_t max) +{ + int log = ceilLog2(max); + int shift = (sizeof(uint64_t) * 8 - log); + uint64_t random; + + do { + random = (uint64_t)genrand() << 32 | (uint64_t)genrand(); + random = random >> shift; + } while (random > max); + + return random; +} + +void +Random::serialize(const string &base, ostream &os) { - double r; - r = drand48() * (max-min) + min; + int length = N; + paramOut(os, base + ".mti", mti); + paramOut(os, base + ".length", length); + arrayParamOut(os, base + ".data", mt, length); +} - return (uint64_t)m5round(r); +void +Random::unserialize(const string &base, Checkpoint *cp, const string §ion) +{ + int length; + + paramIn(cp, section, base + ".mti", mti); + paramIn(cp, section, base + ".length", length); + if (length != N) + panic("cant unserialize random number data. length != %d\n", length); + + arrayParamIn(cp, section, base + ".data", mt, length); } + +Random random_mt; diff --git a/src/base/random.hh b/src/base/random.hh index 0cd88728d..401ba086f 100644 --- a/src/base/random.hh +++ b/src/base/random.hh @@ -32,99 +32,211 @@ #ifndef __BASE_RANDOM_HH__ #define __BASE_RANDOM_HH__ -#include "sim/host.hh" - -uint32_t getUInt32(); -double getDouble(); -double m5random(double r); -uint64_t getUniformPos(uint64_t min, uint64_t max); -int64_t getUniform(int64_t min, int64_t max); - -template <typename T> -struct Random; - -template<> struct Random<int8_t> -{ - static int8_t get() - { return getUInt32() & (int8_t)-1; } - - static int8_t uniform(int8_t min, int8_t max) - { return getUniform(min, max); } -}; - -template<> struct Random<uint8_t> -{ - static uint8_t get() - { return getUInt32() & (uint8_t)-1; } - - static uint8_t uniform(uint8_t min, uint8_t max) - { return getUniformPos(min, max); } -}; - -template<> struct Random<int16_t> -{ - static int16_t get() - { return getUInt32() & (int16_t)-1; } - - static int16_t uniform(int16_t min, int16_t max) - { return getUniform(min, max); } -}; - -template<> struct Random<uint16_t> -{ - static uint16_t get() - { return getUInt32() & (uint16_t)-1; } - - static uint16_t uniform(uint16_t min, uint16_t max) - { return getUniformPos(min, max); } -}; - -template<> struct Random<int32_t> -{ - static int32_t get() - { return (int32_t)getUInt32(); } - - static int32_t uniform(int32_t min, int32_t max) - { return getUniform(min, max); } -}; - -template<> struct Random<uint32_t> -{ - static uint32_t get() - { return (uint32_t)getUInt32(); } - - static uint32_t uniform(uint32_t min, uint32_t max) - { return getUniformPos(min, max); } -}; +#include <ios> +#include <string> -template<> struct Random<int64_t> -{ - static int64_t get() - { return (int64_t)getUInt32() << 32 || (uint64_t)getUInt32(); } - - static int64_t uniform(int64_t min, int64_t max) - { return getUniform(min, max); } -}; - -template<> struct Random<uint64_t> -{ - static uint64_t get() - { return (uint64_t)getUInt32() << 32 || (uint64_t)getUInt32(); } +#include "base/range.hh" +#include "sim/host.hh" - static uint64_t uniform(uint64_t min, uint64_t max) - { return getUniformPos(min, max); } -}; +class Checkpoint; -template<> struct Random<float> +class Random { - static float get() - { return getDouble(); } + protected: + static const int N = 624; + static const int M = 397; + static const uint32_t MATRIX_A = (uint32_t)0x9908b0df; + static const uint32_t UPPER_MASK = (uint32_t)0x80000000; + static const uint32_t LOWER_MASK = (uint32_t)0x7fffffff; + + uint32_t mt[N]; + int mti; + + uint32_t genrand(); + uint32_t genrand(uint32_t max); + uint64_t genrand(uint64_t max); + + void + _random(int8_t &value) + { + value = genrand() & (int8_t)-1; + } + + void + _random(int16_t &value) + { + value = genrand() & (int16_t)-1; + } + + void + _random(int32_t &value) + { + value = (int32_t)genrand(); + } + + void + _random(int64_t &value) + { + value = (int64_t)genrand() << 32 | (int64_t)genrand(); + } + + void + _random(uint8_t &value) + { + value = genrand() & (uint8_t)-1; + } + + void + _random(uint16_t &value) + { + value = genrand() & (uint16_t)-1; + } + + void + _random(uint32_t &value) + { + value = genrand(); + } + + void + _random(uint64_t &value) + { + value = (uint64_t)genrand() << 32 | (uint64_t)genrand(); + } + + // [0,1] + void + _random(float &value) + { + // ieee floats have 23 bits of mantissa + value = (genrand() >> 9) / 8388608.0; + } + + // [0,1] + void + _random(double &value) + { + double number = genrand() * 2097152.0 + (genrand() >> 11); + value = number / 9007199254740992.0; + } + + + // Range based versions of the random number generator + int8_t + _random(int8_t min, int8_t max) + { + uint32_t diff = max - min; + return static_cast<int8_t>(min + genrand(diff)); + } + + int16_t + _random(int16_t min, int16_t max) + { + uint32_t diff = max - min; + return static_cast<int16_t>(min + genrand(diff)); + } + + int32_t + _random(int32_t min, int32_t max) + { + uint32_t diff = max - min; + return static_cast<int32_t>(min + genrand(diff)); + } + + int64_t + _random(int64_t min, int64_t max) + { + uint64_t diff = max - min; + return static_cast<int64_t>(min + genrand(diff)); + } + + uint8_t + _random(uint8_t min, uint8_t max) + { + uint32_t diff = max - min; + return static_cast<uint8_t>(min + genrand(diff)); + } + + uint16_t + _random(uint16_t min, uint16_t max) + { + uint32_t diff = max - min; + return static_cast<uint16_t>(min + genrand(diff)); + } + + uint32_t + _random(uint32_t min, uint32_t max) + { + uint32_t diff = max - min; + return static_cast<uint32_t>(min + genrand(diff)); + } + + uint64_t + _random(uint64_t min, uint64_t max) + { + uint64_t diff = max - min; + return static_cast<uint64_t>(min + genrand(diff)); + } + + public: + Random(); + Random(uint32_t s); + Random(uint32_t init_key[], int key_length); + ~Random(); + + void init(uint32_t s); + void init(uint32_t init_key[], int key_length); + + template <typename T> + T + random() + { + T value; + _random(value); + return value; + } + + template <typename T> + T + random(T min, T max) + { + return _random(min, max); + } + + template <typename T> + T + random(const Range<T> &range) + { + return _random(range.start, range.end); + } + + // [0,1] + double + gen_real1() + { + return genrand() / 4294967296.0; + } + + // [0,1) + double + gen_real2() + { + return genrand() / 4294967295.0; + } + + // (0,1) + double + gen_real3() + { + return ((double)genrand() + 0.5) / 4294967296.0; + } + + public: + void serialize(const std::string &base, std::ostream &os); + void unserialize(const std::string &base, Checkpoint *cp, + const std::string §ion); }; -template<> struct Random<double> -{ - static double get() - { return getDouble(); } -}; +extern Random random_mt; #endif // __BASE_RANDOM_HH__ diff --git a/src/base/random_mt.cc b/src/base/random_mt.cc new file mode 100644 index 000000000..1492240ee --- /dev/null +++ b/src/base/random_mt.cc @@ -0,0 +1,149 @@ +/* + * A C-program for MT19937, with initialization improved 2002/1/26. + * Coded by Takuji Nishimura and Makoto Matsumoto. + * + * Before using, initialize the state by using init_genrand(seed) + * or init_by_array(init_key, key_length). + * + * Copyright (C) 1997 - 2002, Makoto Matsumoto and Takuji Nishimura, + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * 3. The names of its contributors may not be used to endorse or + * promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * Any feedback is very welcome. + * http://www.math.sci.hiroshima-u.ac.jp/~m-mat/MT/emt.html + * email: m-mat @ math.sci.hiroshima-u.ac.jp (remove space) + */ + +#include "base/random.hh" + +/* initializes mt[N] with a seed */ +void +Random::init(uint32_t s) +{ + mti = N + 1; + mt[0] = s & (uint32_t)0xffffffff; + + for (mti = 1; mti < N; mti++) { + mt[mti] = 1812433253UL * (mt[mti-1] ^ (mt[mti-1] >> 30)) + mti; + /* See Knuth TAOCP Vol2. 3rd Ed. P.106 for multiplier. */ + /* In the previous versions, MSBs of the seed affect */ + /* only MSBs of the array mt[]. */ + /* 2002/01/09 modified by Makoto Matsumoto */ + mt[mti] &= (uint32_t)0xffffffff; + /* for >32 bit machines */ + } +} + +/* initialize by an array with array-length */ +/* init_key is the array for initializing keys */ +/* key_length is its length */ +/* slight change for C++, 2004/2/26 */ +void +Random::init(uint32_t init_key[], int key_length) +{ + int i = 1; + int j = 0; + int k = (N > key_length) ? N : key_length; + + init(19650218); + + for (; k; k--) { + mt[i] = (mt[i] ^ ((mt[i-1] ^ (mt[i-1] >> 30)) * (uint32_t)1664525)) + + init_key[j] + j; /* non linear */ + + mt[i] &= 0xffffffffUL; /* for WORDSIZE > 32 machines */ + + i++; + j++; + + if (i >= N) { + mt[0] = mt[N - 1]; + i = 1; + } + + if (j >= key_length) + j = 0; + } + + for (k = N - 1; k; k--) { + /* non linear */ + mt[i] = (mt[i] ^ ((mt[i - 1] ^ (mt[i - 1] >> 30)) * 1566083941UL)) - i; + + /* for WORDSIZE > 32 machines */ + mt[i] &= (uint32_t)0xffffffff; + i++; + + if (i >= N) { + mt[0] = mt[N - 1]; + i = 1; + } + } + + /* MSB is 1; assuring non-zero initial array */ + mt[0] = (uint32_t)0x80000000; +} + +/* generates a random number on [0,0xffffffff]-interval */ +uint32_t +Random::genrand() +{ + uint32_t y; + static uint32_t mag01[2] = { 0, MATRIX_A}; + + if (mti >= N) { /* generate N words at one time */ + int kk; + + for (kk = 0; kk < N - M; kk++) { + y = mt[kk] & UPPER_MASK | mt[kk+1] & LOWER_MASK; + mt[kk] = mt[kk + M] ^ (y >> 1) ^ mag01[y & 0x1UL]; + } + for (; kk < N - 1; kk++) { + y = mt[kk] & UPPER_MASK | mt[kk+1] & LOWER_MASK; + mt[kk] = mt[kk + (M - N)] ^ (y >> 1) ^ mag01[y & 0x1UL]; + } + + y = mt[N - 1] & UPPER_MASK | mt[0] & LOWER_MASK; + mt[N - 1] = mt[M - 1] ^ (y >> 1) ^ mag01[y & 0x1UL]; + + mti = 0; + } + + y = mt[mti++]; + + /* Tempering */ + y ^= (y >> 11); + y ^= (y << 7) & (uint32_t)0x9d2c5680; + y ^= (y << 15) & (uint32_t)0xefc60000; + y ^= (y >> 18); + + return y; +} diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc index b28beba89..d5095e7f9 100644 --- a/src/base/remote_gdb.cc +++ b/src/base/remote_gdb.cc @@ -461,8 +461,6 @@ BaseRemoteGDB::read(Addr vaddr, size_t size, char *data) port->readBlob(vaddr, (uint8_t*)data, size); #if FULL_SYSTEM context->delVirtPort(port); -#else - delete port; #endif #if TRACING_ON diff --git a/src/base/statistics.hh b/src/base/statistics.hh index 8d3f53d4c..3a859d364 100644 --- a/src/base/statistics.hh +++ b/src/base/statistics.hh @@ -2030,6 +2030,39 @@ class ConstNode : public Node virtual std::string str() const { return to_string(vresult[0]); } }; +template <class T> +class ConstVectorNode : public Node +{ + private: + VResult vresult; + + public: + ConstVectorNode(const T &s) : vresult(s.begin(), s.end()) {} + const VResult &result() const { return vresult; } + virtual Result total() const + { + int size = this->size(); + Result tmp = 0; + for (int i = 0; i < size; i++) + { + tmp += vresult[i]; + } + return tmp; + } + virtual size_t size() const { return vresult.size(); } + virtual std::string str() const + { + int size = this->size(); + std::string tmp = "("; + for (int i = 0; i < size; i++) + { + tmp += csprintf("%s ",to_string(vresult[i])); + } + tmp += ")"; + return tmp; + } +}; + template <class Op> struct OpString; @@ -2888,6 +2921,13 @@ constant(T val) return NodePtr(new ConstNode<T>(val)); } +template <typename T> +inline Temp +constantVector(T val) +{ + return NodePtr(new ConstVectorNode<T>(val)); +} + inline Temp sum(Temp val) { diff --git a/src/base/traceflags.py b/src/base/traceflags.py index 8573eb9bf..15d921efe 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -68,15 +68,6 @@ baseFlags = [ 'DiskImageRead', 'DiskImageWrite', 'DynInst', - 'Ethernet', - 'EthernetCksum', - 'EthernetDMA', - 'EthernetData', - 'EthernetDesc', - 'EthernetEEPROM', - 'EthernetIntr', - 'EthernetPIO', - 'EthernetSM', 'Event', 'ExecEnable', 'ExecCPSeq', diff --git a/src/cpu/SConscript b/src/cpu/SConscript index b686c0d95..6b43c6c16 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -136,6 +136,7 @@ if env['TARGET_ISA'] == 'x86': if env['USE_CHECKER']: Source('checker/cpu.cc') + TraceFlag('Checker') checker_supports = False for i in CheckerSupportedCPUList: if i in env['CPU_MODELS']: @@ -146,3 +147,26 @@ if env['USE_CHECKER']: print i, print ", please set USE_CHECKER=False or use one of those CPU models" Exit(1) + +TraceFlag('Activity') +TraceFlag('Commit') +TraceFlag('Decode') +TraceFlag('DynInst') +TraceFlag('ExecEnable') +TraceFlag('ExecCPSeq') +TraceFlag('ExecEffAddr') +TraceFlag('ExecFetchSeq') +TraceFlag('ExecOpClass') +TraceFlag('ExecRegDelta') +TraceFlag('ExecResult') +TraceFlag('ExecSpeculative') +TraceFlag('ExecSymbol') +TraceFlag('ExecThread') +TraceFlag('ExecTicks') +TraceFlag('Fetch') +TraceFlag('IntrControl') +TraceFlag('PCEvent') +TraceFlag('Quiesce') + +CompoundFlag('Exec', [ 'ExecEnable', 'ExecTicks', 'ExecOpClass', 'ExecThread', + 'ExecEffAddr', 'ExecResult', 'ExecSymbol' ]) diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 7b31eb766..25bd3f893 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -74,7 +74,7 @@ CPUProgressEvent::process() { Counter temp = cpu->totalInstructions(); #ifndef NDEBUG - double ipc = double(temp - lastNumInst) / (interval / cpu->cycles(1)); + double ipc = double(temp - lastNumInst) / (interval / cpu->ticks(1)); DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n", cpu->name(), temp - lastNumInst, ipc); @@ -223,7 +223,7 @@ BaseCPU::startup() if (params->progress_interval) { new CPUProgressEvent(&mainEventQueue, - cycles(params->progress_interval), + ticks(params->progress_interval), this); } } diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 76f6e4684..3c3e91523 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -82,8 +82,9 @@ class BaseCPU : public MemObject public: // Tick currentTick; inline Tick frequency() const { return Clock::Frequency / clock; } - inline Tick cycles(int numCycles) const { return clock * numCycles; } + inline Tick ticks(int numCycles) const { return clock * numCycles; } inline Tick curCycle() const { return curTick / clock; } + inline Tick tickToCycles(Tick val) const { return val / clock; } // @todo remove me after debugging with legion done Tick instCount() { return instCnt; } diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 0f2a90bf6..74b250207 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -102,6 +102,9 @@ class BaseDynInst : public FastAlloc, public RefCounted template <class T> Fault read(Addr addr, T &data, unsigned flags); + Fault translateDataReadAddr(Addr vaddr, Addr &paddr, + int size, unsigned flags); + /** * Does a write to a given address. * @param data The data to be written. @@ -114,6 +117,9 @@ class BaseDynInst : public FastAlloc, public RefCounted Fault write(T data, Addr addr, unsigned flags, uint64_t *res); + Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, + int size, unsigned flags); + void prefetch(Addr addr, unsigned flags); void writeHint(Addr addr, int size, unsigned flags); Fault copySrcTranslate(Addr src); @@ -838,6 +844,29 @@ class BaseDynInst : public FastAlloc, public RefCounted }; template<class Impl> +Fault +BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr, + int size, unsigned flags) +{ + if (traceData) { + traceData->setAddr(vaddr); + } + + reqMade = true; + Request *req = new Request(); + req->setVirt(asid, vaddr, size, flags, PC); + req->setThreadContext(thread->readCpuId(), threadNumber); + + fault = cpu->translateDataReadReq(req, thread); + + if (fault == NoFault) + paddr = req->getPaddr(); + + delete req; + return fault; +} + +template<class Impl> template<class T> inline Fault BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) @@ -889,6 +918,29 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) } template<class Impl> +Fault +BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr, + int size, unsigned flags) +{ + if (traceData) { + traceData->setAddr(vaddr); + } + + reqMade = true; + Request *req = new Request(); + req->setVirt(asid, vaddr, size, flags, PC); + req->setThreadContext(thread->readCpuId(), threadNumber); + + fault = cpu->translateDataWriteReq(req, thread); + + if (fault == NoFault) + paddr = req->getPaddr(); + + delete req; + return fault; +} + +template<class Impl> template<class T> inline Fault BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) diff --git a/src/cpu/memtest/SConscript b/src/cpu/memtest/SConscript index 1f6621a4c..7832632e4 100644 --- a/src/cpu/memtest/SConscript +++ b/src/cpu/memtest/SConscript @@ -34,3 +34,5 @@ if 'O3CPU' in env['CPU_MODELS']: SimObject('MemTest.py') Source('memtest.cc') + + TraceFlag('MemTest') diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc index 583fd5f8d..f8c8a0547 100644 --- a/src/cpu/memtest/memtest.cc +++ b/src/cpu/memtest/memtest.cc @@ -270,7 +270,7 @@ void MemTest::tick() { if (!tickEvent.scheduled()) - tickEvent.schedule(curTick + cycles(1)); + tickEvent.schedule(curTick + ticks(1)); if (++noResponseCycles >= 500000) { cerr << name() << ": deadlocked at cycle " << curTick << endl; diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh index fa168c70b..1c918df33 100644 --- a/src/cpu/memtest/memtest.hh +++ b/src/cpu/memtest/memtest.hh @@ -55,7 +55,7 @@ class MemTest : public MemObject // register statistics virtual void regStats(); - inline Tick cycles(int numCycles) const { return numCycles; } + inline Tick ticks(int numCycles) const { return numCycles; } // main simulation loop (one cycle) void tick(); diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript index ad61ad228..2de106d8b 100755 --- a/src/cpu/o3/SConscript +++ b/src/cpu/o3/SConscript @@ -32,6 +32,16 @@ import sys Import('*') +if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: + Source('2bit_local_pred.cc') + Source('btb.cc') + Source('ras.cc') + Source('tournament_pred.cc') + + TraceFlag('CommitRate') + TraceFlag('IEW') + TraceFlag('IQ') + if 'O3CPU' in env['CPU_MODELS']: SimObject('FUPool.py') SimObject('FuncUnitConfig.py') @@ -56,6 +66,21 @@ if 'O3CPU' in env['CPU_MODELS']: Source('scoreboard.cc') Source('store_set.cc') + TraceFlag('FreeList') + TraceFlag('LSQ') + TraceFlag('LSQUnit') + TraceFlag('MemDepUnit') + TraceFlag('O3CPU') + TraceFlag('ROB') + TraceFlag('Rename') + TraceFlag('Scoreboard') + TraceFlag('StoreSet') + TraceFlag('Writeback') + + CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', + 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', + 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ]) + if env['TARGET_ISA'] == 'alpha': Source('alpha/cpu.cc') Source('alpha/cpu_builder.cc') @@ -77,10 +102,3 @@ if 'O3CPU' in env['CPU_MODELS']: if env['USE_CHECKER']: SimObject('O3Checker.py') Source('checker_builder.cc') - -if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: - Source('2bit_local_pred.cc') - Source('btb.cc') - Source('ras.cc') - Source('tournament_pred.cc') - diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc index 1aa3d1618..f569c048b 100644 --- a/src/cpu/o3/alpha/cpu_builder.cc +++ b/src/cpu/o3/alpha/cpu_builder.cc @@ -80,8 +80,8 @@ DerivO3CPUParams::create() params->itb = itb; params->dtb = dtb; -#if FULL_SYSTEM params->system = system; +#if FULL_SYSTEM params->profile = profile; params->do_quiesce = do_quiesce; diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc index 0799b9cb5..b9afb3f9f 100644 --- a/src/cpu/o3/checker_builder.cc +++ b/src/cpu/o3/checker_builder.cc @@ -88,9 +88,9 @@ O3CheckerParams::create() params->itb = itb; params->dtb = dtb; -#if FULL_SYSTEM params->system = system; params->cpu_id = cpu_id; +#if FULL_SYSTEM params->profile = profile; #else params->process = workload; diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index f263383ae..89df257e9 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -325,7 +325,7 @@ DefaultCommit<Impl>::initStage() cpu->activateStage(O3CPU::CommitIdx); cpu->activityThisCycle(); - trapLatency = cpu->cycles(trapLatency); + trapLatency = cpu->ticks(trapLatency); } template <class Impl> @@ -910,25 +910,21 @@ DefaultCommit<Impl>::commitInsts() microPC[tid] = nextMicroPC[tid]; nextMicroPC[tid] = microPC[tid] + 1; -#if FULL_SYSTEM int count = 0; Addr oldpc; + // Debug statement. Checks to make sure we're not + // currently updating state while handling PC events. + assert(!thread[tid]->inSyscall && !thread[tid]->trapPending); do { - // Debug statement. Checks to make sure we're not - // currently updating state while handling PC events. - if (count == 0) - assert(!thread[tid]->inSyscall && - !thread[tid]->trapPending); oldpc = PC[tid]; - cpu->system->pcEventQueue.service( - thread[tid]->getTC()); + cpu->system->pcEventQueue.service(thread[tid]->getTC()); count++; } while (oldpc != PC[tid]); if (count > 1) { - DPRINTF(Commit, "PC skip function event, stopping commit\n"); + DPRINTF(Commit, + "PC skip function event, stopping commit\n"); break; } -#endif } else { DPRINTF(Commit, "Unable to commit head instruction PC:%#x " "[tid:%i] [sn:%i].\n", diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 98e200944..3842d27bd 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -464,7 +464,7 @@ FullO3CPU<Impl>::tick() lastRunningCycle = curTick; timesIdled++; } else { - tickEvent.schedule(nextCycle(curTick + cycles(1))); + tickEvent.schedule(nextCycle(curTick + ticks(1))); DPRINTF(O3CPU, "Scheduling next tick!\n"); } } @@ -558,7 +558,7 @@ FullO3CPU<Impl>::activateContext(int tid, int delay) // Needs to set each stage to running as well. if (delay){ DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate " - "on cycle %d\n", tid, curTick + cycles(delay)); + "on cycle %d\n", tid, curTick + ticks(delay)); scheduleActivateThreadEvent(tid, delay); } else { activateThread(tid); @@ -585,7 +585,7 @@ FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay) // Schedule removal of thread data from CPU if (delay){ DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate " - "on cycle %d\n", tid, curTick + cycles(delay)); + "on cycle %d\n", tid, curTick + ticks(delay)); scheduleDeallocateContextEvent(tid, remove, delay); return false; } else { @@ -1409,7 +1409,8 @@ FullO3CPU<Impl>::wakeCPU() DPRINTF(Activity, "Waking up CPU\n"); - idleCycles += (curTick - 1) - lastRunningCycle; + idleCycles += tickToCycles((curTick - 1) - lastRunningCycle); + numCycles += tickToCycles((curTick - 1) - lastRunningCycle); tickEvent.schedule(nextCycle()); } diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index d97a2080d..162e377e1 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -146,9 +146,9 @@ class FullO3CPU : public BaseO3CPU void scheduleTickEvent(int delay) { if (tickEvent.squashed()) - tickEvent.reschedule(nextCycle(curTick + cycles(delay))); + tickEvent.reschedule(nextCycle(curTick + ticks(delay))); else if (!tickEvent.scheduled()) - tickEvent.schedule(nextCycle(curTick + cycles(delay))); + tickEvent.schedule(nextCycle(curTick + ticks(delay))); } /** Unschedule tick event, regardless of its current state. */ @@ -187,10 +187,10 @@ class FullO3CPU : public BaseO3CPU // Schedule thread to activate, regardless of its current state. if (activateThreadEvent[tid].squashed()) activateThreadEvent[tid]. - reschedule(nextCycle(curTick + cycles(delay))); + reschedule(nextCycle(curTick + ticks(delay))); else if (!activateThreadEvent[tid].scheduled()) activateThreadEvent[tid]. - schedule(nextCycle(curTick + cycles(delay))); + schedule(nextCycle(curTick + ticks(delay))); } /** Unschedule actiavte thread event, regardless of its current state. */ @@ -238,10 +238,10 @@ class FullO3CPU : public BaseO3CPU // Schedule thread to activate, regardless of its current state. if (deallocateContextEvent[tid].squashed()) deallocateContextEvent[tid]. - reschedule(nextCycle(curTick + cycles(delay))); + reschedule(nextCycle(curTick + ticks(delay))); else if (!deallocateContextEvent[tid].scheduled()) deallocateContextEvent[tid]. - schedule(nextCycle(curTick + cycles(delay))); + schedule(nextCycle(curTick + ticks(delay))); } /** Unschedule thread deallocation in CPU */ diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index 47f019ebe..aea62f12d 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -752,7 +752,7 @@ InstructionQueue<Impl>::scheduleReadyInsts() FUCompletion *execution = new FUCompletion(issuing_inst, idx, this); - execution->schedule(curTick + cpu->cycles(issue_latency - 1)); + execution->schedule(curTick + cpu->ticks(issue_latency - 1)); // @todo: Enforce that issue_latency == 1 or op_latency if (issue_latency > 1) { diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index d78de2c87..49c885753 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -959,9 +959,11 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) if (src_reg < TheISA::FP_Base_DepTag) { flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); + } else if (src_reg < TheISA::Ctrl_Base_DepTag) { + src_reg = src_reg - TheISA::FP_Base_DepTag; + flat_src_reg = TheISA::flattenFloatIndex(inst->tcBase(), src_reg); + flat_src_reg += TheISA::NumIntRegs; } else { - // Floating point and Miscellaneous registers need their indexes - // adjusted to account for the expanded number of flattened int regs. flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg); } diff --git a/src/cpu/o3/sparc/cpu_builder.cc b/src/cpu/o3/sparc/cpu_builder.cc index b7c684431..b08845b4e 100644 --- a/src/cpu/o3/sparc/cpu_builder.cc +++ b/src/cpu/o3/sparc/cpu_builder.cc @@ -81,8 +81,8 @@ DerivO3CPUParams::create() params->itb = itb; params->dtb = dtb; -#if FULL_SYSTEM params->system = system; +#if FULL_SYSTEM params->profile = profile; params->do_quiesce = do_quiesce; diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index a145e046e..efbbc2329 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -314,6 +314,7 @@ template <class Impl> TheISA::FloatReg O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); switch(width) { case 32: return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); @@ -329,6 +330,7 @@ template <class Impl> TheISA::FloatReg O3ThreadContext<Impl>::readFloatReg(int reg_idx) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); } @@ -337,6 +339,7 @@ TheISA::FloatRegBits O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) { DPRINTF(Fault, "Reading floatint register through the TC!\n"); + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); } @@ -344,6 +347,7 @@ template <class Impl> TheISA::FloatRegBits O3ThreadContext<Impl>::readFloatRegBits(int reg_idx) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); } @@ -364,6 +368,7 @@ template <class Impl> void O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); switch(width) { case 32: cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); @@ -383,6 +388,7 @@ template <class Impl> void O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); if (!thread->trapPending && !thread->inSyscall) { @@ -396,6 +402,7 @@ O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) { DPRINTF(Fault, "Setting floatint register through the TC!\n"); + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); // Squash if we're not already in a state update mode. @@ -408,6 +415,7 @@ template <class Impl> void O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); // Squash if we're not already in a state update mode. diff --git a/src/cpu/ozone/SConscript b/src/cpu/ozone/SConscript index cb2006456..0ca1a0d07 100644 --- a/src/cpu/ozone/SConscript +++ b/src/cpu/ozone/SConscript @@ -44,6 +44,15 @@ if 'OzoneCPU' in env['CPU_MODELS']: Source('lw_back_end.cc') Source('lw_lsq.cc') Source('rename_table.cc') + + TraceFlag('BE') + TraceFlag('FE') + TraceFlag('IBE') + TraceFlag('OzoneCPU') + TraceFlag('OzoneLSQ') + + CompoundFlag('OzoneCPUAll', [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU' ]) + if env['USE_CHECKER']: SimObject('OzoneChecker.py') Source('checker_builder.cc') diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc index 625b2a39a..37b9f951a 100644 --- a/src/cpu/ozone/checker_builder.cc +++ b/src/cpu/ozone/checker_builder.cc @@ -89,9 +89,9 @@ OzoneCheckerParams::create() params->itb = itb; params->dtb = dtb; -#if FULL_SYSTEM params->system = system; params->cpu_id = cpu_id; +#if FULL_SYSTEM params->profile = profile; #else params->process = workload; diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 78d0892c4..036db1351 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -315,9 +315,9 @@ class OzoneCPU : public BaseCPU void scheduleTickEvent(int delay) { if (tickEvent.squashed()) - tickEvent.reschedule(curTick + cycles(delay)); + tickEvent.reschedule(curTick + ticks(delay)); else if (!tickEvent.scheduled()) - tickEvent.schedule(curTick + cycles(delay)); + tickEvent.schedule(curTick + ticks(delay)); } /// Unschedule tick event, regardless of its current state. diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc index 7edbe41c9..beb179d41 100644 --- a/src/cpu/ozone/cpu_builder.cc +++ b/src/cpu/ozone/cpu_builder.cc @@ -82,9 +82,9 @@ DerivOzoneCPUParams::create() params->itb = itb; params->dtb = dtb; -#if FULL_SYSTEM params->system = system; params->cpu_id = cpu_id; +#if FULL_SYSTEM params->profile = profile; params->do_quiesce = do_quiesce; params->do_checkpoint_insts = do_checkpoint_insts; diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index 37a91c630..5080c54f6 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -613,7 +613,7 @@ OzoneCPU<Impl>::tick() comInstEventQueue[0]->serviceEvents(numInst); if (!tickEvent.scheduled() && _status == Running) - tickEvent.schedule(curTick + cycles(1)); + tickEvent.schedule(curTick + ticks(1)); } template <class Impl> diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh index f84bda348..42788cee1 100644 --- a/src/cpu/ozone/lw_back_end_impl.hh +++ b/src/cpu/ozone/lw_back_end_impl.hh @@ -45,7 +45,7 @@ LWBackEnd<Impl>::generateTrapEvent(Tick latency) TrapEvent *trap = new TrapEvent(this); - trap->schedule(curTick + cpu->cycles(latency)); + trap->schedule(curTick + cpu->ticks(latency)); thread->trapPending = true; } diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc index ca55cdca4..9cd56fdb4 100644 --- a/src/cpu/ozone/simple_cpu_builder.cc +++ b/src/cpu/ozone/simple_cpu_builder.cc @@ -85,10 +85,9 @@ SimpleOzoneCPUParams::create() params->itb = itb; params->dtb = dtb; -#if FULL_SYSTEM params->system = system; params->cpu_id = cpu_id; -#else +#if !FULL_SYSTEM params->workload = workload; // params->pTable = page_table; #endif // FULL_SYSTEM diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript index ccccab2b5..c090a938c 100644 --- a/src/cpu/simple/SConscript +++ b/src/cpu/simple/SConscript @@ -41,5 +41,9 @@ if 'TimingSimpleCPU' in env['CPU_MODELS']: SimObject('TimingSimpleCPU.py') Source('timing.cc') +if 'AtomicSimpleCPU' in env['CPU_MODELS'] or \ + 'TimingSimpleCPU' in env['CPU_MODELS']: + TraceFlag('SimpleCPU') + if need_simple_base: Source('base.cc') diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 06f52e30e..4e52f9b33 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -159,9 +159,9 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p) icachePort.snoopRangeSent = false; dcachePort.snoopRangeSent = false; - ifetch_req.setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT - data_read_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too - data_write_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too + ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT + data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too + data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too } @@ -237,6 +237,8 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) if (_status != Running) { _status = Idle; } + assert(threadContexts.size() == 1); + cpuId = tc->readCpuId(); } @@ -252,9 +254,10 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay) assert(!tickEvent.scheduled()); notIdleFraction++; + numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend); //Make sure ticks are still on multiples of cycles - tickEvent.schedule(nextCycle(curTick + cycles(delay))); + tickEvent.schedule(nextCycle(curTick + ticks(delay))); _status = Running; } @@ -363,6 +366,61 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) } } +Fault +AtomicSimpleCPU::translateDataReadAddr(Addr vaddr, Addr & paddr, + int size, unsigned flags) +{ + // use the CPU's statically allocated read request and packet objects + Request *req = &data_read_req; + + if (traceData) { + traceData->setAddr(vaddr); + } + + //The block size of our peer. + int blockSize = dcachePort.peerBlockSize(); + //The size of the data we're trying to read. + int dataSize = size; + + bool firstTimeThrough = true; + + //The address of the second part of this access if it needs to be split + //across a cache line boundary. + Addr secondAddr = roundDown(vaddr + dataSize - 1, blockSize); + + if(secondAddr > vaddr) + dataSize = secondAddr - vaddr; + + while(1) { + req->setVirt(0, vaddr, dataSize, flags, thread->readPC()); + + // translate to physical address + Fault fault = thread->translateDataReadReq(req); + + //If there's a fault, return it + if (fault != NoFault) + return fault; + + if (firstTimeThrough) { + paddr = req->getPaddr(); + firstTimeThrough = false; + } + + //If we don't need to access a second cache line, stop now. + if (secondAddr <= vaddr) + return fault; + + /* + * Set up for accessing the second cache line. + */ + + //Adjust the size to get the remaining bytes. + dataSize = vaddr + size - secondAddr; + //And access the right address. + vaddr = secondAddr; + } +} + #ifndef DOXYGEN_SHOULD_SKIP_THIS template @@ -521,6 +579,64 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) } } +Fault +AtomicSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, + int size, unsigned flags) +{ + // use the CPU's statically allocated write request and packet objects + Request *req = &data_write_req; + + if (traceData) { + traceData->setAddr(vaddr); + } + + //The block size of our peer. + int blockSize = dcachePort.peerBlockSize(); + + //The address of the second part of this access if it needs to be split + //across a cache line boundary. + Addr secondAddr = roundDown(vaddr + size - 1, blockSize); + + //The size of the data we're trying to read. + int dataSize = size; + + bool firstTimeThrough = true; + + if(secondAddr > vaddr) + dataSize = secondAddr - vaddr; + + dcache_latency = 0; + + while(1) { + req->setVirt(0, vaddr, flags, flags, thread->readPC()); + + // translate to physical address + Fault fault = thread->translateDataWriteReq(req); + + //If there's a fault or we don't need to access a second cache line, + //stop now. + if (fault != NoFault) + return fault; + + if (firstTimeThrough) { + paddr = req->getPaddr(); + firstTimeThrough = false; + } + + if (secondAddr <= vaddr) + return fault; + + /* + * Set up for accessing the second cache line. + */ + + //Adjust the size to get the remaining bytes. + dataSize = vaddr + size - secondAddr; + //And access the right address. + vaddr = secondAddr; + } +} + #ifndef DOXYGEN_SHOULD_SKIP_THIS @@ -584,7 +700,7 @@ AtomicSimpleCPU::tick() { DPRINTF(SimpleCPU, "Tick\n"); - Tick latency = cycles(1); // instruction takes one cycle by default + Tick latency = ticks(1); // instruction takes one cycle by default for (int i = 0; i < width; ++i) { numCycles++; @@ -642,14 +758,14 @@ AtomicSimpleCPU::tick() if (simulate_stalls) { Tick icache_stall = - icache_access ? icache_latency - cycles(1) : 0; + icache_access ? icache_latency - ticks(1) : 0; Tick dcache_stall = - dcache_access ? dcache_latency - cycles(1) : 0; - Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1); - if (cycles(stall_cycles) < (icache_stall + dcache_stall)) - latency += cycles(stall_cycles+1); + dcache_access ? dcache_latency - ticks(1) : 0; + Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1); + if (ticks(stall_cycles) < (icache_stall + dcache_stall)) + latency += ticks(stall_cycles+1); else - latency += cycles(stall_cycles); + latency += ticks(stall_cycles); } } diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index 96429e5b1..f68f41a90 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -151,6 +151,11 @@ class AtomicSimpleCPU : public BaseSimpleCPU template <class T> Fault write(T data, Addr addr, unsigned flags, uint64_t *res); + + Fault translateDataReadAddr(Addr vaddr, Addr &paddr, + int size, unsigned flags); + Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, + int size, unsigned flags); }; #endif // __CPU_SIMPLE_ATOMIC_HH__ diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index d6b124efc..1611a7275 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -91,6 +91,8 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p) threadContexts.push_back(tc); + cpuId = tc->readCpuId(); + fetchOffset = 0; stayAtPC = false; } @@ -428,11 +430,10 @@ void BaseSimpleCPU::postExecute() { #if FULL_SYSTEM - if (thread->profile) { + if (thread->profile && curStaticInst) { bool usermode = TheISA::inUserMode(tc); thread->profilePC = usermode ? 1 : thread->readPC(); - StaticInstPtr si(inst, thread->readPC()); - ProfileNode *node = thread->profile->consume(tc, si); + ProfileNode *node = thread->profile->consume(tc, curStaticInst); if (node) thread->profileNode = node; } @@ -464,6 +465,7 @@ BaseSimpleCPU::advancePC(Fault fault) fetchOffset = 0; if (fault != NoFault) { curMacroStaticInst = StaticInst::nullStaticInstPtr; + predecoder.reset(); fault->invoke(tc); thread->setMicroPC(0); thread->setNextMicroPC(1); @@ -494,12 +496,10 @@ BaseSimpleCPU::advancePC(Fault fault) } } -#if FULL_SYSTEM Addr oldpc; do { oldpc = thread->readPC(); system->pcEventQueue.service(tc); } while (oldpc != thread->readPC()); -#endif } diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 2bc329b68..337ef5285 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -117,6 +117,10 @@ class BaseSimpleCPU : public BaseCPU * objects to modify this thread's state. */ ThreadContext *tc; + protected: + int cpuId; + + public: #if FULL_SYSTEM Addr dbg_vtophys(Addr addr); diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 8d1cf9a17..998d0b017 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -29,6 +29,7 @@ */ #include "arch/locked_mem.hh" +#include "arch/mmaped_ipr.hh" #include "arch/utility.hh" #include "base/bigint.hh" #include "cpu/exetrace.hh" @@ -103,8 +104,7 @@ TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t) } TimingSimpleCPU::TimingSimpleCPU(Params *p) - : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), - cpu_id(p->cpu_id) + : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock) { _status = Idle; @@ -172,7 +172,6 @@ TimingSimpleCPU::resume() } changeState(SimObject::Running); - previousTick = curTick; } void @@ -180,7 +179,7 @@ TimingSimpleCPU::switchOut() { assert(status() == Running || status() == Idle); _status = SwitchedOut; - numCycles += curTick - previousTick; + numCycles += tickToCycles(curTick - previousTick); // If we've been scheduled to resume but are then told to switch out, // we'll need to cancel it. @@ -207,6 +206,9 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) if (_status != Running) { _status = Idle; } + assert(threadContexts.size() == 1); + cpuId = tc->readCpuId(); + previousTick = curTick; } @@ -222,7 +224,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay) _status = Running; // kick things off by initiating the fetch of the next instruction - fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay))); + fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay))); } @@ -248,7 +250,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) { Request *req = new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), - cpu_id, /* thread ID */ 0); + cpuId, /* thread ID */ 0); if (traceData) { traceData->setAddr(req->getVaddr()); @@ -266,7 +268,13 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) Packet::Broadcast); pkt->dataDynamic<T>(new T); - if (!dcachePort.sendTiming(pkt)) { + if (req->isMmapedIpr()) { + Tick delay; + delay = TheISA::handleIprRead(thread->getTC(), pkt); + new IprEvent(pkt, this, nextCycle(curTick + delay)); + _status = DcacheWaitResponse; + dcache_pkt = NULL; + } else if (!dcachePort.sendTiming(pkt)) { _status = DcacheRetry; dcache_pkt = pkt; } else { @@ -285,6 +293,26 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) return fault; } +Fault +TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr, + int size, unsigned flags) +{ + Request *req = + new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); + + if (traceData) { + traceData->setAddr(vaddr); + } + + Fault fault = thread->translateDataWriteReq(req); + + if (fault == NoFault) + paddr = req->getPaddr(); + + delete req; + return fault; +} + #ifndef DOXYGEN_SHOULD_SKIP_THIS template @@ -342,7 +370,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) { Request *req = new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), - cpu_id, /* thread ID */ 0); + cpuId, /* thread ID */ 0); if (traceData) { traceData->setAddr(req->getVaddr()); @@ -375,7 +403,14 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) dcache_pkt->set(data); if (do_access) { - if (!dcachePort.sendTiming(dcache_pkt)) { + if (req->isMmapedIpr()) { + Tick delay; + dcache_pkt->set(htog(data)); + delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); + new IprEvent(dcache_pkt, this, nextCycle(curTick + delay)); + _status = DcacheWaitResponse; + dcache_pkt = NULL; + } else if (!dcachePort.sendTiming(dcache_pkt)) { _status = DcacheRetry; } else { _status = DcacheWaitResponse; @@ -396,6 +431,26 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) return fault; } +Fault +TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, + int size, unsigned flags) +{ + Request *req = + new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); + + if (traceData) { + traceData->setAddr(vaddr); + } + + Fault fault = thread->translateDataWriteReq(req); + + if (fault == NoFault) + paddr = req->getPaddr(); + + delete req; + return fault; +} + #ifndef DOXYGEN_SHOULD_SKIP_THIS template @@ -460,7 +515,7 @@ TimingSimpleCPU::fetch() checkForInterrupts(); Request *ifetch_req = new Request(); - ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0); + ifetch_req->setThreadContext(cpuId, /* thread ID */ 0); Fault fault = setupFetchRequest(ifetch_req); ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); @@ -483,7 +538,7 @@ TimingSimpleCPU::fetch() advanceInst(fault); } - numCycles += curTick - previousTick; + numCycles += tickToCycles(curTick - previousTick); previousTick = curTick; } @@ -512,7 +567,7 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) _status = Running; - numCycles += curTick - previousTick; + numCycles += tickToCycles(curTick - previousTick); previousTick = curTick; if (getState() == SimObject::Draining) { @@ -551,6 +606,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) } postExecute(); + // @todo remove me after debugging with legion done + if (curStaticInst && (!curStaticInst->isMicroop() || + curStaticInst->isFirstMicroop())) + instCnt++; advanceInst(fault); } } else { @@ -567,6 +626,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt) } postExecute(); + // @todo remove me after debugging with legion done + if (curStaticInst && (!curStaticInst->isMicroop() || + curStaticInst->isFirstMicroop())) + instCnt++; advanceInst(fault); } @@ -629,7 +692,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt) assert(_status == DcacheWaitResponse); _status = Running; - numCycles += curTick - previousTick; + numCycles += tickToCycles(curTick - previousTick); previousTick = curTick; Fault fault = curStaticInst->completeAcc(pkt, this, traceData); @@ -730,6 +793,24 @@ TimingSimpleCPU::DcachePort::recvRetry() } } +TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t) + : Event(&mainEventQueue), pkt(_pkt), cpu(_cpu) +{ + schedule(t); +} + +void +TimingSimpleCPU::IprEvent::process() +{ + cpu->completeDataAccess(pkt); +} + +const char * +TimingSimpleCPU::IprEvent::description() +{ + return "Timing Simple CPU Delay IPR event"; +} + //////////////////////////////////////////////////////////////////////// // diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index ba194b3fa..d7554f6de 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -168,7 +168,6 @@ class TimingSimpleCPU : public BaseSimpleCPU PacketPtr ifetch_pkt; PacketPtr dcache_pkt; - int cpu_id; Tick previousTick; public: @@ -190,9 +189,15 @@ class TimingSimpleCPU : public BaseSimpleCPU template <class T> Fault read(Addr addr, T &data, unsigned flags); + Fault translateDataReadAddr(Addr vaddr, Addr &paddr, + int size, unsigned flags); + template <class T> Fault write(T data, Addr addr, unsigned flags, uint64_t *res); + Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, + int size, unsigned flags); + void fetch(); void completeIfetch(PacketPtr ); void completeDataAccess(PacketPtr ); @@ -203,6 +208,14 @@ class TimingSimpleCPU : public BaseSimpleCPU typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent; FetchEvent *fetchEvent; + struct IprEvent : Event { + Packet *pkt; + TimingSimpleCPU *cpu; + IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t); + virtual void process(); + virtual const char *description(); + }; + void completeDrain(); }; diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 1e87b0bb7..2b79c9708 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -235,52 +235,62 @@ class SimpleThread : public ThreadState // uint64_t readIntReg(int reg_idx) { - return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx)); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + return regs.readIntReg(flatIndex); } FloatReg readFloatReg(int reg_idx, int width) { - return regs.readFloatReg(reg_idx, width); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); + return regs.readFloatReg(flatIndex, width); } FloatReg readFloatReg(int reg_idx) { - return regs.readFloatReg(reg_idx); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); + return regs.readFloatReg(flatIndex); } FloatRegBits readFloatRegBits(int reg_idx, int width) { - return regs.readFloatRegBits(reg_idx, width); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); + return regs.readFloatRegBits(flatIndex, width); } FloatRegBits readFloatRegBits(int reg_idx) { - return regs.readFloatRegBits(reg_idx); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); + return regs.readFloatRegBits(flatIndex); } void setIntReg(int reg_idx, uint64_t val) { - regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + regs.setIntReg(flatIndex, val); } void setFloatReg(int reg_idx, FloatReg val, int width) { - regs.setFloatReg(reg_idx, val, width); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); + regs.setFloatReg(flatIndex, val, width); } void setFloatReg(int reg_idx, FloatReg val) { - regs.setFloatReg(reg_idx, val); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); + regs.setFloatReg(flatIndex, val); } void setFloatRegBits(int reg_idx, FloatRegBits val, int width) { - regs.setFloatRegBits(reg_idx, val, width); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); + regs.setFloatRegBits(flatIndex, val, width); } void setFloatRegBits(int reg_idx, FloatRegBits val) { - regs.setFloatRegBits(reg_idx, val); + int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx); + regs.setFloatRegBits(flatIndex, val); } uint64_t readPC() diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc index e5739b2ce..d3cf34e9d 100644 --- a/src/cpu/trace/trace_cpu.cc +++ b/src/cpu/trace/trace_cpu.cc @@ -110,10 +110,10 @@ TraceCPU::tick() if (mainEventQueue.empty()) { exitSimLoop("end of memory trace reached"); } else { - tickEvent.schedule(mainEventQueue.nextEventTime() + cycles(1)); + tickEvent.schedule(mainEventQueue.nextEventTime() + ticks(1)); } } else { - tickEvent.schedule(max(curTick + cycles(1), nextCycle)); + tickEvent.schedule(max(curTick + ticks(1), nextCycle)); } } diff --git a/src/cpu/trace/trace_cpu.hh b/src/cpu/trace/trace_cpu.hh index 9c96d71d5..b88c7072e 100644 --- a/src/cpu/trace/trace_cpu.hh +++ b/src/cpu/trace/trace_cpu.hh @@ -107,7 +107,7 @@ class TraceCPU : public SimObject MemInterface *dcache_interface, MemTraceReader *data_trace); - inline Tick cycles(int numCycles) { return numCycles; } + inline Tick ticks(int numCycles) { return numCycles; } /** * Perform all the accesses for one cycle. diff --git a/src/dev/SConscript b/src/dev/SConscript index 88ebee573..0aba8ac35 100644 --- a/src/dev/SConscript +++ b/src/dev/SConscript @@ -66,3 +66,35 @@ if env['FULL_SYSTEM']: Source('sinic.cc') Source('uart.cc') Source('uart8250.cc') + + TraceFlag('Console') + TraceFlag('ConsoleVerbose') + TraceFlag('DiskImageRead') + TraceFlag('DiskImageWrite') + TraceFlag('DMA') + TraceFlag('Ethernet') + TraceFlag('EthernetCksum') + TraceFlag('EthernetDMA') + TraceFlag('EthernetData') + TraceFlag('EthernetDesc') + TraceFlag('EthernetEEPROM') + TraceFlag('EthernetIntr') + TraceFlag('EthernetPIO') + TraceFlag('EthernetSM') + TraceFlag('IdeCtrl') + TraceFlag('IdeDisk') + TraceFlag('IsaFake') + TraceFlag('PCIDEV') + TraceFlag('PciConfigAll') + TraceFlag('SimpleDisk') + TraceFlag('SimpleDiskData') + TraceFlag('Uart') + + CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ]) + CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA', + 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM', + 'EthernetCksum' ]) + CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc', + 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ]) + CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ]) + diff --git a/src/dev/alpha/SConscript b/src/dev/alpha/SConscript index 8d7f5493b..2292c3c57 100644 --- a/src/dev/alpha/SConscript +++ b/src/dev/alpha/SConscript @@ -40,3 +40,7 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha': Source('tsunami_cchip.cc') Source('tsunami_io.cc') Source('tsunami_pchip.cc') + + TraceFlag('AlphaConsole') + TraceFlag('MC146818') + TraceFlag('Tsunami') diff --git a/src/dev/etherlink.cc b/src/dev/etherlink.cc index 4130a7b3f..b1266000b 100644 --- a/src/dev/etherlink.cc +++ b/src/dev/etherlink.cc @@ -177,10 +177,9 @@ EtherLink::Link::transmit(EthPacketPtr pkt) packet = pkt; Tick delay = (Tick)ceil(((double)pkt->length * ticksPerByte) + 1.0); - if (delayVar != 0) { - Random<Tick> var; - delay += var.uniform(0, delayVar); - } + if (delayVar != 0) + delay += random_mt.random<Tick>(0, delayVar); + DPRINTF(Ethernet, "scheduling packet: delay=%d, (rate=%f)\n", delay, ticksPerByte); doneEvent.schedule(curTick + delay); diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index 84882b056..460f6a9fb 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -1104,7 +1104,7 @@ IGbE::restartClock() { if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) && getState() == SimObject::Running) - tickEvent.schedule((curTick/cycles(1)) * cycles(1) + cycles(1)); + tickEvent.schedule((curTick/ticks(1)) * ticks(1) + ticks(1)); } unsigned int @@ -1400,7 +1400,7 @@ IGbE::tick() if (rxTick || txTick || txFifoTick) - tickEvent.schedule(curTick + cycles(1)); + tickEvent.schedule(curTick + ticks(1)); } void diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh index cbe7cf8c0..30aa6430e 100644 --- a/src/dev/i8254xGBe.hh +++ b/src/dev/i8254xGBe.hh @@ -614,7 +614,7 @@ class IGbE : public EtherDevice virtual EtherInt *getEthPort(const std::string &if_name, int idx); Tick clock; - inline Tick cycles(int numCycles) const { return numCycles * clock; } + inline Tick ticks(int numCycles) const { return numCycles * clock; } virtual Tick read(PacketPtr pkt); virtual Tick write(PacketPtr pkt); diff --git a/src/dev/isa_fake.cc b/src/dev/isa_fake.cc index 9525436c0..af3ca3b0f 100644 --- a/src/dev/isa_fake.cc +++ b/src/dev/isa_fake.cc @@ -61,12 +61,12 @@ IsaFake::read(PacketPtr pkt) warn("Device %s accessed by read to address %#x size=%d\n", name(), pkt->getAddr(), pkt->getSize()); if (params()->ret_bad_addr) { - DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n", + DPRINTF(IsaFake, "read to bad address va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); pkt->setBadAddress(); } else { assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); - DPRINTF(Tsunami, "read va=%#x size=%d\n", + DPRINTF(IsaFake, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); switch (pkt->getSize()) { case sizeof(uint64_t): @@ -114,11 +114,11 @@ IsaFake::write(PacketPtr pkt) name(), pkt->getAddr(), pkt->getSize(), data); } if (params()->ret_bad_addr) { - DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n", + DPRINTF(IsaFake, "write to bad address va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); pkt->setBadAddress(); } else { - DPRINTF(Tsunami, "write - va=%#x size=%d \n", + DPRINTF(IsaFake, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); if (params()->update_data) { diff --git a/src/dev/isa_fake.hh b/src/dev/isa_fake.hh index 4233d9d4c..1fd2415cb 100644 --- a/src/dev/isa_fake.hh +++ b/src/dev/isa_fake.hh @@ -66,7 +66,7 @@ class IsaFake : public BasicPioDevice return dynamic_cast<const Params *>(_params); } /** - * The constructor for Tsunmami Fake just registers itself with the MMU. + * The constructor for Isa Fake just registers itself with the MMU. * @param p params structure */ IsaFake(Params *p); diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc index 0788b89a9..bd48bdca5 100644 --- a/src/dev/ns_gige.cc +++ b/src/dev/ns_gige.cc @@ -1469,7 +1469,7 @@ NSGigE::rxKick() } // Go to the next state machine clock tick. - rxKickTick = curTick + cycles(1); + rxKickTick = curTick + ticks(1); } switch(rxDmaState) { @@ -1916,7 +1916,7 @@ NSGigE::txKick() } // Go to the next state machine clock tick. - txKickTick = curTick + cycles(1); + txKickTick = curTick + ticks(1); } switch(txDmaState) { @@ -2322,7 +2322,7 @@ NSGigE::transferDone() DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n"); - txEvent.reschedule(curTick + cycles(1), true); + txEvent.reschedule(curTick + ticks(1), true); } bool diff --git a/src/dev/ns_gige.hh b/src/dev/ns_gige.hh index 5e589687a..dfdd81b66 100644 --- a/src/dev/ns_gige.hh +++ b/src/dev/ns_gige.hh @@ -199,7 +199,7 @@ class NSGigE : public EtherDevice /* state machine cycle time */ Tick clock; - inline Tick cycles(int numCycles) const { return numCycles * clock; } + inline Tick ticks(int numCycles) const { return numCycles * clock; } /* tx State Machine */ TxState txState; diff --git a/src/dev/ns_gige_reg.h b/src/dev/ns_gige_reg.h index 80ac5800d..c37c06aed 100644 --- a/src/dev/ns_gige_reg.h +++ b/src/dev/ns_gige_reg.h @@ -37,280 +37,320 @@ #define __DEV_NS_GIGE_REG_H__ /* Device Register Address Map */ -#define CR 0x00 -#define CFGR 0x04 -#define MEAR 0x08 -#define PTSCR 0x0c -#define ISR 0x10 -#define IMR 0x14 -#define IER 0x18 -#define IHR 0x1c -#define TXDP 0x20 -#define TXDP_HI 0x24 -#define TX_CFG 0x28 -#define GPIOR 0x2c -#define RXDP 0x30 -#define RXDP_HI 0x34 -#define RX_CFG 0x38 -#define PQCR 0x3c -#define WCSR 0x40 -#define PCR 0x44 -#define RFCR 0x48 -#define RFDR 0x4c -#define BRAR 0x50 -#define BRDR 0x54 -#define SRR 0x58 -#define MIBC 0x5c -#define MIB_START 0x60 -#define MIB_END 0x88 -#define VRCR 0xbc -#define VTCR 0xc0 -#define VDR 0xc4 -#define CCSR 0xcc -#define TBICR 0xe0 -#define TBISR 0xe4 -#define TANAR 0xe8 -#define TANLPAR 0xec -#define TANER 0xf0 -#define TESR 0xf4 -#define M5REG 0xf8 -#define LAST 0xf8 -#define RESERVED 0xfc +enum DeviceRegisterAddress { + CR = 0x00, + CFGR = 0x04, + MEAR = 0x08, + PTSCR = 0x0c, + ISR = 0x10, + IMR = 0x14, + IER = 0x18, + IHR = 0x1c, + TXDP = 0x20, + TXDP_HI = 0x24, + TX_CFG = 0x28, + GPIOR = 0x2c, + RXDP = 0x30, + RXDP_HI = 0x34, + RX_CFG = 0x38, + PQCR = 0x3c, + WCSR = 0x40, + PCR = 0x44, + RFCR = 0x48, + RFDR = 0x4c, + BRAR = 0x50, + BRDR = 0x54, + SRR = 0x58, + MIBC = 0x5c, + MIB_START = 0x60, + MIB_END = 0x88, + VRCR = 0xbc, + VTCR = 0xc0, + VDR = 0xc4, + CCSR = 0xcc, + TBICR = 0xe0, + TBISR = 0xe4, + TANAR = 0xe8, + TANLPAR = 0xec, + TANER = 0xf0, + TESR = 0xf4, + M5REG = 0xf8, + LAST = 0xf8, + RESERVED = 0xfc +}; /* Chip Command Register */ -#define CR_TXE 0x00000001 -#define CR_TXD 0x00000002 -#define CR_RXE 0x00000004 -#define CR_RXD 0x00000008 -#define CR_TXR 0x00000010 -#define CR_RXR 0x00000020 -#define CR_SWI 0x00000080 -#define CR_RST 0x00000100 +enum ChipCommandRegister { + CR_TXE = 0x00000001, + CR_TXD = 0x00000002, + CR_RXE = 0x00000004, + CR_RXD = 0x00000008, + CR_TXR = 0x00000010, + CR_RXR = 0x00000020, + CR_SWI = 0x00000080, + CR_RST = 0x00000100 +}; /* configuration register */ -#define CFGR_LNKSTS 0x80000000 -#define CFGR_SPDSTS 0x60000000 -#define CFGR_SPDSTS1 0x40000000 -#define CFGR_SPDSTS0 0x20000000 -#define CFGR_DUPSTS 0x10000000 -#define CFGR_TBI_EN 0x01000000 -#define CFGR_RESERVED 0x0e000000 -#define CFGR_MODE_1000 0x00400000 -#define CFGR_AUTO_1000 0x00200000 -#define CFGR_PINT_CTL 0x001c0000 -#define CFGR_PINT_DUPSTS 0x00100000 -#define CFGR_PINT_LNKSTS 0x00080000 -#define CFGR_PINT_SPDSTS 0x00040000 -#define CFGR_TMRTEST 0x00020000 -#define CFGR_MRM_DIS 0x00010000 -#define CFGR_MWI_DIS 0x00008000 -#define CFGR_T64ADDR 0x00004000 -#define CFGR_PCI64_DET 0x00002000 -#define CFGR_DATA64_EN 0x00001000 -#define CFGR_M64ADDR 0x00000800 -#define CFGR_PHY_RST 0x00000400 -#define CFGR_PHY_DIS 0x00000200 -#define CFGR_EXTSTS_EN 0x00000100 -#define CFGR_REQALG 0x00000080 -#define CFGR_SB 0x00000040 -#define CFGR_POW 0x00000020 -#define CFGR_EXD 0x00000010 -#define CFGR_PESEL 0x00000008 -#define CFGR_BROM_DIS 0x00000004 -#define CFGR_EXT_125 0x00000002 -#define CFGR_BEM 0x00000001 +enum ConfigurationRegisters { + CFGR_LNKSTS = 0x80000000, + CFGR_SPDSTS = 0x60000000, + CFGR_SPDSTS1 = 0x40000000, + CFGR_SPDSTS0 = 0x20000000, + CFGR_DUPSTS = 0x10000000, + CFGR_TBI_EN = 0x01000000, + CFGR_RESERVED = 0x0e000000, + CFGR_MODE_1000 = 0x00400000, + CFGR_AUTO_1000 = 0x00200000, + CFGR_PINT_CTL = 0x001c0000, + CFGR_PINT_DUPSTS = 0x00100000, + CFGR_PINT_LNKSTS = 0x00080000, + CFGR_PINT_SPDSTS = 0x00040000, + CFGR_TMRTEST = 0x00020000, + CFGR_MRM_DIS = 0x00010000, + CFGR_MWI_DIS = 0x00008000, + CFGR_T64ADDR = 0x00004000, + CFGR_PCI64_DET = 0x00002000, + CFGR_DATA64_EN = 0x00001000, + CFGR_M64ADDR = 0x00000800, + CFGR_PHY_RST = 0x00000400, + CFGR_PHY_DIS = 0x00000200, + CFGR_EXTSTS_EN = 0x00000100, + CFGR_REQALG = 0x00000080, + CFGR_SB = 0x00000040, + CFGR_POW = 0x00000020, + CFGR_EXD = 0x00000010, + CFGR_PESEL = 0x00000008, + CFGR_BROM_DIS = 0x00000004, + CFGR_EXT_125 = 0x00000002, + CFGR_BEM = 0x00000001 +}; /* EEPROM access register */ -#define MEAR_EEDI 0x00000001 -#define MEAR_EEDO 0x00000002 -#define MEAR_EECLK 0x00000004 -#define MEAR_EESEL 0x00000008 -#define MEAR_MDIO 0x00000010 -#define MEAR_MDDIR 0x00000020 -#define MEAR_MDC 0x00000040 +enum EEPROMAccessRegister { + MEAR_EEDI = 0x00000001, + MEAR_EEDO = 0x00000002, + MEAR_EECLK = 0x00000004, + MEAR_EESEL = 0x00000008, + MEAR_MDIO = 0x00000010, + MEAR_MDDIR = 0x00000020, + MEAR_MDC = 0x00000040, +}; /* PCI test control register */ -#define PTSCR_EEBIST_FAIL 0x00000001 -#define PTSCR_EEBIST_EN 0x00000002 -#define PTSCR_EELOAD_EN 0x00000004 -#define PTSCR_RBIST_FAIL 0x000001b8 -#define PTSCR_RBIST_DONE 0x00000200 -#define PTSCR_RBIST_EN 0x00000400 -#define PTSCR_RBIST_RST 0x00002000 -#define PTSCR_RBIST_RDONLY 0x000003f9 +enum PCITestControlRegister { + PTSCR_EEBIST_FAIL = 0x00000001, + PTSCR_EEBIST_EN = 0x00000002, + PTSCR_EELOAD_EN = 0x00000004, + PTSCR_RBIST_FAIL = 0x000001b8, + PTSCR_RBIST_DONE = 0x00000200, + PTSCR_RBIST_EN = 0x00000400, + PTSCR_RBIST_RST = 0x00002000, + PTSCR_RBIST_RDONLY = 0x000003f9 +}; /* interrupt status register */ -#define ISR_RESERVE 0x80000000 -#define ISR_TXDESC3 0x40000000 -#define ISR_TXDESC2 0x20000000 -#define ISR_TXDESC1 0x10000000 -#define ISR_TXDESC0 0x08000000 -#define ISR_RXDESC3 0x04000000 -#define ISR_RXDESC2 0x02000000 -#define ISR_RXDESC1 0x01000000 -#define ISR_RXDESC0 0x00800000 -#define ISR_TXRCMP 0x00400000 -#define ISR_RXRCMP 0x00200000 -#define ISR_DPERR 0x00100000 -#define ISR_SSERR 0x00080000 -#define ISR_RMABT 0x00040000 -#define ISR_RTABT 0x00020000 -#define ISR_RXSOVR 0x00010000 -#define ISR_HIBINT 0x00008000 -#define ISR_PHY 0x00004000 -#define ISR_PME 0x00002000 -#define ISR_SWI 0x00001000 -#define ISR_MIB 0x00000800 -#define ISR_TXURN 0x00000400 -#define ISR_TXIDLE 0x00000200 -#define ISR_TXERR 0x00000100 -#define ISR_TXDESC 0x00000080 -#define ISR_TXOK 0x00000040 -#define ISR_RXORN 0x00000020 -#define ISR_RXIDLE 0x00000010 -#define ISR_RXEARLY 0x00000008 -#define ISR_RXERR 0x00000004 -#define ISR_RXDESC 0x00000002 -#define ISR_RXOK 0x00000001 -#define ISR_ALL 0x7FFFFFFF -#define ISR_DELAY (ISR_TXIDLE|ISR_TXDESC|ISR_TXOK| \ - ISR_RXIDLE|ISR_RXDESC|ISR_RXOK) -#define ISR_NODELAY (ISR_ALL & ~ISR_DELAY) -#define ISR_IMPL (ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN| \ - ISR_RXIDLE|ISR_RXDESC|ISR_RXOK) -#define ISR_NOIMPL (ISR_ALL & ~ISR_IMPL) +enum InterruptStatusRegister { + ISR_RESERVE = 0x80000000, + ISR_TXDESC3 = 0x40000000, + ISR_TXDESC2 = 0x20000000, + ISR_TXDESC1 = 0x10000000, + ISR_TXDESC0 = 0x08000000, + ISR_RXDESC3 = 0x04000000, + ISR_RXDESC2 = 0x02000000, + ISR_RXDESC1 = 0x01000000, + ISR_RXDESC0 = 0x00800000, + ISR_TXRCMP = 0x00400000, + ISR_RXRCMP = 0x00200000, + ISR_DPERR = 0x00100000, + ISR_SSERR = 0x00080000, + ISR_RMABT = 0x00040000, + ISR_RTAB = 0x00020000, + ISR_RXSOVR = 0x00010000, + ISR_HIBINT = 0x00008000, + ISR_PHY = 0x00004000, + ISR_PME = 0x00002000, + ISR_SWI = 0x00001000, + ISR_MIB = 0x00000800, + ISR_TXURN = 0x00000400, + ISR_TXIDLE = 0x00000200, + ISR_TXERR = 0x00000100, + ISR_TXDESC = 0x00000080, + ISR_TXOK = 0x00000040, + ISR_RXORN = 0x00000020, + ISR_RXIDLE = 0x00000010, + ISR_RXEARLY = 0x00000008, + ISR_RXERR = 0x00000004, + ISR_RXDESC = 0x00000002, + ISR_RXOK = 0x00000001, + ISR_ALL = 0x7FFFFFFF, + ISR_DELAY = (ISR_TXIDLE|ISR_TXDESC|ISR_TXOK| + ISR_RXIDLE|ISR_RXDESC|ISR_RXOK), + ISR_NODELAY = (ISR_ALL & ~ISR_DELAY), + ISR_IMPL = (ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN| + ISR_RXIDLE|ISR_RXDESC|ISR_RXOK), + ISR_NOIMPL = (ISR_ALL & ~ISR_IMPL) +}; /* transmit configuration register */ -#define TX_CFG_CSI 0x80000000 -#define TX_CFG_HBI 0x40000000 -#define TX_CFG_MLB 0x20000000 -#define TX_CFG_ATP 0x10000000 -#define TX_CFG_ECRETRY 0x00800000 -#define TX_CFG_BRST_DIS 0x00080000 -#define TX_CFG_MXDMA1024 0x00000000 -#define TX_CFG_MXDMA512 0x00700000 -#define TX_CFG_MXDMA256 0x00600000 -#define TX_CFG_MXDMA128 0x00500000 -#define TX_CFG_MXDMA64 0x00400000 -#define TX_CFG_MXDMA32 0x00300000 -#define TX_CFG_MXDMA16 0x00200000 -#define TX_CFG_MXDMA8 0x00100000 -#define TX_CFG_MXDMA 0x00700000 +enum TransmitConfigurationRegister { + TX_CFG_CSI = 0x80000000, + TX_CFG_HBI = 0x40000000, + TX_CFG_MLB = 0x20000000, + TX_CFG_ATP = 0x10000000, + TX_CFG_ECRETRY = 0x00800000, + TX_CFG_BRST_DIS = 0x00080000, + TX_CFG_MXDMA1024 = 0x00000000, + TX_CFG_MXDMA512 = 0x00700000, + TX_CFG_MXDMA256 = 0x00600000, + TX_CFG_MXDMA128 = 0x00500000, + TX_CFG_MXDMA64 = 0x00400000, + TX_CFG_MXDMA32 = 0x00300000, + TX_CFG_MXDMA16 = 0x00200000, + TX_CFG_MXDMA8 = 0x00100000, + TX_CFG_MXDMA = 0x00700000, -#define TX_CFG_FLTH_MASK 0x0000ff00 -#define TX_CFG_DRTH_MASK 0x000000ff + TX_CFG_FLTH_MASK = 0x0000ff00, + TX_CFG_DRTH_MASK = 0x000000ff +}; /*general purpose I/O control register */ -#define GPIOR_UNUSED 0xffff8000 -#define GPIOR_GP5_IN 0x00004000 -#define GPIOR_GP4_IN 0x00002000 -#define GPIOR_GP3_IN 0x00001000 -#define GPIOR_GP2_IN 0x00000800 -#define GPIOR_GP1_IN 0x00000400 -#define GPIOR_GP5_OE 0x00000200 -#define GPIOR_GP4_OE 0x00000100 -#define GPIOR_GP3_OE 0x00000080 -#define GPIOR_GP2_OE 0x00000040 -#define GPIOR_GP1_OE 0x00000020 -#define GPIOR_GP5_OUT 0x00000010 -#define GPIOR_GP4_OUT 0x00000008 -#define GPIOR_GP3_OUT 0x00000004 -#define GPIOR_GP2_OUT 0x00000002 -#define GPIOR_GP1_OUT 0x00000001 +enum GeneralPurposeIOControlRegister { + GPIOR_UNUSED = 0xffff8000, + GPIOR_GP5_IN = 0x00004000, + GPIOR_GP4_IN = 0x00002000, + GPIOR_GP3_IN = 0x00001000, + GPIOR_GP2_IN = 0x00000800, + GPIOR_GP1_IN = 0x00000400, + GPIOR_GP5_OE = 0x00000200, + GPIOR_GP4_OE = 0x00000100, + GPIOR_GP3_OE = 0x00000080, + GPIOR_GP2_OE = 0x00000040, + GPIOR_GP1_OE = 0x00000020, + GPIOR_GP5_OUT = 0x00000010, + GPIOR_GP4_OUT = 0x00000008, + GPIOR_GP3_OUT = 0x00000004, + GPIOR_GP2_OUT = 0x00000002, + GPIOR_GP1_OUT = 0x00000001 +}; /* receive configuration register */ -#define RX_CFG_AEP 0x80000000 -#define RX_CFG_ARP 0x40000000 -#define RX_CFG_STRIPCRC 0x20000000 -#define RX_CFG_RX_FD 0x10000000 -#define RX_CFG_ALP 0x08000000 -#define RX_CFG_AIRL 0x04000000 -#define RX_CFG_MXDMA512 0x00700000 -#define RX_CFG_MXDMA 0x00700000 -#define RX_CFG_DRTH 0x0000003e -#define RX_CFG_DRTH0 0x00000002 +enum ReceiveConfigurationRegister { + RX_CFG_AEP = 0x80000000, + RX_CFG_ARP = 0x40000000, + RX_CFG_STRIPCRC = 0x20000000, + RX_CFG_RX_FD = 0x10000000, + RX_CFG_ALP = 0x08000000, + RX_CFG_AIRL = 0x04000000, + RX_CFG_MXDMA512 = 0x00700000, + RX_CFG_MXDMA = 0x00700000, + RX_CFG_DRTH = 0x0000003e, + RX_CFG_DRTH0 = 0x00000002 +}; /* pause control status register */ -#define PCR_PSEN (1 << 31) -#define PCR_PS_MCAST (1 << 30) -#define PCR_PS_DA (1 << 29) -#define PCR_STHI_8 (3 << 23) -#define PCR_STLO_4 (1 << 23) -#define PCR_FFHI_8K (3 << 21) -#define PCR_FFLO_4K (1 << 21) -#define PCR_PAUSE_CNT 0xFFFE +enum PauseControlStatusRegister { + PCR_PSEN = (1 << 31), + PCR_PS_MCAST = (1 << 30), + PCR_PS_DA = (1 << 29), + PCR_STHI_8 = (3 << 23), + PCR_STLO_4 = (1 << 23), + PCR_FFHI_8K = (3 << 21), + PCR_FFLO_4K = (1 << 21), + PCR_PAUSE_CNT = 0xFFFE +}; /*receive filter/match control register */ -#define RFCR_RFEN 0x80000000 -#define RFCR_AAB 0x40000000 -#define RFCR_AAM 0x20000000 -#define RFCR_AAU 0x10000000 -#define RFCR_APM 0x08000000 -#define RFCR_APAT 0x07800000 -#define RFCR_APAT3 0x04000000 -#define RFCR_APAT2 0x02000000 -#define RFCR_APAT1 0x01000000 -#define RFCR_APAT0 0x00800000 -#define RFCR_AARP 0x00400000 -#define RFCR_MHEN 0x00200000 -#define RFCR_UHEN 0x00100000 -#define RFCR_ULM 0x00080000 -#define RFCR_RFADDR 0x000003ff +enum ReceiveFilterMatchControlRegister { + RFCR_RFEN = 0x80000000, + RFCR_AAB = 0x40000000, + RFCR_AAM = 0x20000000, + RFCR_AAU = 0x10000000, + RFCR_APM = 0x08000000, + RFCR_APAT = 0x07800000, + RFCR_APAT3 = 0x04000000, + RFCR_APAT2 = 0x02000000, + RFCR_APAT1 = 0x01000000, + RFCR_APAT0 = 0x00800000, + RFCR_AARP = 0x00400000, + RFCR_MHEN = 0x00200000, + RFCR_UHEN = 0x00100000, + RFCR_ULM = 0x00080000, + RFCR_RFADDR = 0x000003ff +}; /* receive filter/match data register */ -#define RFDR_BMASK 0x00030000 -#define RFDR_RFDATA0 0x000000ff -#define RFDR_RFDATA1 0x0000ff00 +enum ReceiveFilterMatchDataRegister { + RFDR_BMASK = 0x00030000, + RFDR_RFDATA0 = 0x000000ff, + RFDR_RFDATA1 = 0x0000ff00 +}; /* management information base control register */ -#define MIBC_MIBS 0x00000008 -#define MIBC_ACLR 0x00000004 -#define MIBC_FRZ 0x00000002 -#define MIBC_WRN 0x00000001 +enum ManagementInformationBaseControlRegister { + MIBC_MIBS = 0x00000008, + MIBC_ACLR = 0x00000004, + MIBC_FRZ = 0x00000002, + MIBC_WRN = 0x00000001 +}; /* VLAN/IP receive control register */ -#define VRCR_RUDPE 0x00000080 -#define VRCR_RTCPE 0x00000040 -#define VRCR_RIPE 0x00000020 -#define VRCR_IPEN 0x00000010 -#define VRCR_DUTF 0x00000008 -#define VRCR_DVTF 0x00000004 -#define VRCR_VTREN 0x00000002 -#define VRCR_VTDEN 0x00000001 +enum VLANIPReceiveControlRegister { + VRCR_RUDPE = 0x00000080, + VRCR_RTCPE = 0x00000040, + VRCR_RIPE = 0x00000020, + VRCR_IPEN = 0x00000010, + VRCR_DUTF = 0x00000008, + VRCR_DVTF = 0x00000004, + VRCR_VTREN = 0x00000002, + VRCR_VTDEN = 0x00000001 +}; /* VLAN/IP transmit control register */ -#define VTCR_PPCHK 0x00000008 -#define VTCR_GCHK 0x00000004 -#define VTCR_VPPTI 0x00000002 -#define VTCR_VGTI 0x00000001 +enum VLANIPTransmitControlRegister { + VTCR_PPCHK = 0x00000008, + VTCR_GCHK = 0x00000004, + VTCR_VPPTI = 0x00000002, + VTCR_VGTI = 0x00000001 +}; /* Clockrun Control/Status Register */ -#define CCSR_CLKRUN_EN 0x00000001 +enum ClockrunControlStatusRegister { + CCSR_CLKRUN_EN = 0x00000001 +}; /* TBI control register */ -#define TBICR_MR_LOOPBACK 0x00004000 -#define TBICR_MR_AN_ENABLE 0x00001000 -#define TBICR_MR_RESTART_AN 0x00000200 +enum TBIControlRegister { + TBICR_MR_LOOPBACK = 0x00004000, + TBICR_MR_AN_ENABLE = 0x00001000, + TBICR_MR_RESTART_AN = 0x00000200 +}; /* TBI status register */ -#define TBISR_MR_LINK_STATUS 0x00000020 -#define TBISR_MR_AN_COMPLETE 0x00000004 +enum TBIStatusRegister { + TBISR_MR_LINK_STATUS = 0x00000020, + TBISR_MR_AN_COMPLETE = 0x00000004 +}; /* TBI auto-negotiation advertisement register */ -#define TANAR_NP 0x00008000 -#define TANAR_RF2 0x00002000 -#define TANAR_RF1 0x00001000 -#define TANAR_PS2 0x00000100 -#define TANAR_PS1 0x00000080 -#define TANAR_HALF_DUP 0x00000040 -#define TANAR_FULL_DUP 0x00000020 -#define TANAR_UNUSED 0x00000E1F +enum TBIAutoNegotiationAdvertisementRegister { + TANAR_NP = 0x00008000, + TANAR_RF2 = 0x00002000, + TANAR_RF1 = 0x00001000, + TANAR_PS2 = 0x00000100, + TANAR_PS1 = 0x00000080, + TANAR_HALF_DUP = 0x00000040, + TANAR_FULL_DUP = 0x00000020, + TANAR_UNUSED = 0x00000E1F +}; /* M5 control register */ -#define M5REG_RESERVED 0xfffffffc -#define M5REG_RSS 0x00000004 -#define M5REG_RX_THREAD 0x00000002 -#define M5REG_TX_THREAD 0x00000001 +enum M5ControlRegister { + M5REG_RESERVED = 0xfffffffc, + M5REG_RSS = 0x00000004, + M5REG_RX_THREAD = 0x00000002, + M5REG_TX_THREAD = 0x00000001 +}; struct ns_desc32 { uint32_t link; /* link field to next descriptor in linked list */ @@ -327,27 +367,35 @@ struct ns_desc64 { }; /* cmdsts flags for descriptors */ -#define CMDSTS_OWN 0x80000000 -#define CMDSTS_MORE 0x40000000 -#define CMDSTS_INTR 0x20000000 -#define CMDSTS_ERR 0x10000000 -#define CMDSTS_OK 0x08000000 -#define CMDSTS_LEN_MASK 0x0000ffff +enum CMDSTSFlatsForDescriptors { + CMDSTS_OWN = 0x80000000, + CMDSTS_MORE = 0x40000000, + CMDSTS_INTR = 0x20000000, + CMDSTS_ERR = 0x10000000, + CMDSTS_OK = 0x08000000, + CMDSTS_LEN_MASK = 0x0000ffff, -#define CMDSTS_DEST_MASK 0x01800000 -#define CMDSTS_DEST_SELF 0x00800000 -#define CMDSTS_DEST_MULTI 0x01000000 + CMDSTS_DEST_MASK = 0x01800000, + CMDSTS_DEST_SELF = 0x00800000, + CMDSTS_DEST_MULTI = 0x01000000 +}; /* extended flags for descriptors */ -#define EXTSTS_UDPERR 0x00400000 -#define EXTSTS_UDPPKT 0x00200000 -#define EXTSTS_TCPERR 0x00100000 -#define EXTSTS_TCPPKT 0x00080000 -#define EXTSTS_IPERR 0x00040000 -#define EXTSTS_IPPKT 0x00020000 - +enum ExtendedFlagsForDescriptors { + EXTSTS_UDPERR = 0x00400000, + EXTSTS_UDPPKT = 0x00200000, + EXTSTS_TCPERR = 0x00100000, + EXTSTS_TCPPKT = 0x00080000, + EXTSTS_IPERR = 0x00040000, + EXTSTS_IPPKT = 0x00020000 +}; /* speed status */ -#define SPDSTS_POLARITY (CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS | (lnksts ? CFGR_LNKSTS : 0)) +static inline int +SPDSTS_POLARITY(int lnksts) +{ + return (CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS | + (lnksts ? CFGR_LNKSTS : 0)); +} #endif /* __DEV_NS_GIGE_REG_H__ */ diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index 7457a2b47..c63966528 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -1211,7 +1211,7 @@ Device::transferDone() DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n"); - txEvent.reschedule(curTick + cycles(1), true); + txEvent.reschedule(curTick + ticks(1), true); } bool diff --git a/src/dev/sinic.hh b/src/dev/sinic.hh index 469b28191..e85d93fe4 100644 --- a/src/dev/sinic.hh +++ b/src/dev/sinic.hh @@ -51,7 +51,7 @@ class Base : public PciDev bool rxEnable; bool txEnable; Tick clock; - inline Tick cycles(int numCycles) const { return numCycles * clock; } + inline Tick ticks(int numCycles) const { return numCycles * clock; } protected: Tick intrDelay; diff --git a/src/dev/sparc/SConscript b/src/dev/sparc/SConscript index 2ebf9fe05..b546297d1 100644 --- a/src/dev/sparc/SConscript +++ b/src/dev/sparc/SConscript @@ -38,3 +38,5 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'sparc': Source('iob.cc') Source('t1000.cc') Source('mm_disk.cc') + + TraceFlag('Iob') diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc index d0182770f..6608fc64a 100644 --- a/src/dev/sparc/iob.cc +++ b/src/dev/sparc/iob.cc @@ -56,6 +56,9 @@ Iob::Iob(const Params *p) iobJBusAddr = ULL(0x9F00000000); iobJBusSize = ULL(0x0100000000); assert (params()->system->threadContexts.size() <= MaxNiagaraProcs); + + pioDelay = p->pio_latency; + // Get the interrupt controller from the platform ic = platform->intrctrl; diff --git a/src/dev/x86/Opteron.py b/src/dev/x86/Opteron.py new file mode 100644 index 000000000..435ecccb6 --- /dev/null +++ b/src/dev/x86/Opteron.py @@ -0,0 +1,10 @@ +from m5.params import * +from m5.proxy import * +from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr +from Uart import Uart8250 +from Platform import Platform +from SimConsole import SimConsole + +class Opteron(Platform): + type = 'Opteron' + system = Param.System(Parent.any, "system") diff --git a/src/dev/x86/SConscript b/src/dev/x86/SConscript new file mode 100644 index 000000000..c500531b1 --- /dev/null +++ b/src/dev/x86/SConscript @@ -0,0 +1,37 @@ +# -*- mode:python -*- + +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt +# Gabe Black + +Import('*') + +if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86': + SimObject('Opteron.py') + + Source('opteron.cc') diff --git a/src/arch/alpha/linux/aligned.hh b/src/dev/x86/opteron.cc index c4687e348..df28e58de 100644 --- a/src/arch/alpha/linux/aligned.hh +++ b/src/dev/x86/opteron.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2004 The Regents of The University of Michigan + * Copyright (c) 2004-2005 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -25,26 +25,82 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Ali Saidi - * Nathan Binkert + * Authors: Gabe Black */ -#ifndef __ARCH_ALPHA_LINUX_ALIGNED_HH__ -#define __ARCH_ALPHA_LINUX_ALIGNED_HH__ +/** @file + * Implementation of Opteron platform. + */ +#include <deque> +#include <string> +#include <vector> -/* GCC 3.3.X has a bug in which attributes+typedefs don't work. 3.2.X is fine - * as in 3.4.X, but the bug is marked will not fix in 3.3.X so here is - * the work around. - */ -#if (__GNUC__ == 3 && __GNUC_MINOR__ != 3) || __GNUC__ > 3 -typedef uint64_t uint64_ta __attribute__ ((aligned (8))) ; -typedef int64_t int64_ta __attribute__ ((aligned (8))) ; -typedef Addr Addr_a __attribute__ ((aligned (8))) ; -#else -#define uint64_ta uint64_t __attribute__ ((aligned (8))) -#define int64_ta int64_t __attribute__ ((aligned (8))) -#define Addr_a Addr __attribute__ ((aligned (8))) -#endif /* __GNUC__ __GNUC_MINOR__ */ - -#endif /* __ARCH_ALPHA_LINUX_ALIGNED_HH__ */ +#include "cpu/intr_control.hh" +#include "dev/simconsole.hh" +#include "dev/x86/opteron.hh" +#include "sim/system.hh" + +using namespace std; +using namespace TheISA; + +Opteron::Opteron(const Params *p) + : Platform(p), system(p->system) +{ + // set the back pointer from the system to myself + system->platform = this; +} + +Tick +Opteron::intrFrequency() +{ + panic("Need implementation\n"); + M5_DUMMY_RETURN +} + +void +Opteron::postConsoleInt() +{ + warn_once("Don't know what interrupt to post for console.\n"); + //panic("Need implementation\n"); +} + +void +Opteron::clearConsoleInt() +{ + warn_once("Don't know what interrupt to clear for console.\n"); + //panic("Need implementation\n"); +} + +void +Opteron::postPciInt(int line) +{ + panic("Need implementation\n"); +} + +void +Opteron::clearPciInt(int line) +{ + panic("Need implementation\n"); +} + +Addr +Opteron::pciToDma(Addr pciAddr) const +{ + panic("Need implementation\n"); + M5_DUMMY_RETURN +} + + +Addr +Opteron::calcConfigAddr(int bus, int dev, int func) +{ + panic("Need implementation\n"); + M5_DUMMY_RETURN +} + +Opteron * +OpteronParams::create() +{ + return new Opteron(this); +} diff --git a/src/kern/linux/sched.hh b/src/dev/x86/opteron.hh index f849cee30..3026bce73 100644 --- a/src/kern/linux/sched.hh +++ b/src/dev/x86/opteron.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2005 The Regents of The University of Michigan + * Copyright (c) 2004-2005 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -25,24 +25,68 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Ali Saidi - * Nathan Binkert + * Authors: Gabe Black */ -#ifndef __KERN_LINUX_SCHED_HH__ -#define __KERN_LINUX_SCHED_HH__ +/** + * @file + * Declaration of top level class for the Opteron platform chips. This class + * just retains pointers to all its children so the children can communicate. + */ + +#ifndef __DEV_Opteron_HH__ +#define __DEV_Opteron_HH__ + +#include "dev/platform.hh" +#include "params/Opteron.hh" + +class IdeController; +class System; + +class Opteron : public Platform +{ + public: + /** Pointer to the system */ + System *system; + + public: + typedef OpteronParams Params; + + Opteron(const Params *p); + + /** + * Return the interrupting frequency to AlphaAccess + * @return frequency of RTC interrupts + */ + virtual Tick intrFrequency(); + + /** + * Cause the cpu to post a serial interrupt to the CPU. + */ + virtual void postConsoleInt(); + + /** + * Clear a posted CPU interrupt + */ + virtual void clearConsoleInt(); + + /** + * Cause the chipset to post a pci interrupt to the CPU. + */ + virtual void postPciInt(int line); + + /** + * Clear a posted PCI->CPU interrupt + */ + virtual void clearPciInt(int line); -namespace Linux { - struct task_struct { - uint8_t junk1[0xf4]; - int32_t pid; - uint8_t junk2[0x190]; - uint64_ta start; - uint8_t junk3[0x5c]; - char name[16]; - }; + virtual Addr pciToDma(Addr pciAddr) const; -} + /** + * Calculate the configuration address given a bus/dev/func. + */ + virtual Addr calcConfigAddr(int bus, int dev, int func); +}; -#endif // __KERN_LINUX_SCHED_HH__ +#endif // __DEV_OPTERON_HH__ diff --git a/src/kern/SConscript b/src/kern/SConscript index eec8012a7..509e6b3f7 100644 --- a/src/kern/SConscript +++ b/src/kern/SConscript @@ -34,6 +34,9 @@ if env['FULL_SYSTEM']: Source('kernel_stats.cc') Source('system_events.cc') + TraceFlag('DebugPrintf') + TraceFlag('Printf') + Source('linux/events.cc') Source('linux/linux_syscalls.cc') Source('linux/printk.cc') @@ -43,3 +46,5 @@ if env['FULL_SYSTEM']: Source('tru64/printf.cc') Source('tru64/tru64_events.cc') Source('tru64/tru64_syscalls.cc') + TraceFlag('BADADDR') + diff --git a/src/mem/SConscript b/src/mem/SConscript index bbb1e96fe..b572f703c 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -49,3 +49,10 @@ if env['FULL_SYSTEM']: else: Source('page_table.cc') Source('translating_port.cc') + +TraceFlag('Bus') +TraceFlag('BusAddrRanges') +TraceFlag('BusBridge') +TraceFlag('LLSC') +TraceFlag('MMU') +TraceFlag('MemoryAccess') diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript index 546e037bd..5ac7e34ad 100644 --- a/src/mem/cache/SConscript +++ b/src/mem/cache/SConscript @@ -35,3 +35,8 @@ SimObject('BaseCache.py') Source('base_cache.cc') Source('cache.cc') Source('cache_builder.cc') + +TraceFlag('Cache') +TraceFlag('CachePort') +TraceFlag('CacheRepl') +TraceFlag('HWPrefetch') diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript index a65c44f22..18ed8408b 100644 --- a/src/mem/cache/tags/SConscript +++ b/src/mem/cache/tags/SConscript @@ -40,3 +40,7 @@ Source('split_lru.cc') SimObject('Repl.py') Source('repl/gen.cc') + +TraceFlag('IIC') +TraceFlag('IICMore') +TraceFlag('Split') diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc index efafc3f19..6220305b8 100644 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@ -43,15 +43,16 @@ #include "base/intmath.hh" #include "base/trace.hh" #include "mem/page_table.hh" +#include "sim/process.hh" #include "sim/sim_object.hh" #include "sim/system.hh" using namespace std; using namespace TheISA; -PageTable::PageTable(System *_system, Addr _pageSize) +PageTable::PageTable(Process *_process, Addr _pageSize) : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))), - system(_system) + process(_process) { assert(isPowerOf2(pageSize)); pTableCache[0].vaddr = 0; @@ -80,7 +81,8 @@ PageTable::allocate(Addr vaddr, int64_t size) vaddr); } - pTable[vaddr] = TheISA::TlbEntry(system->new_page()); + pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr, + process->system->new_page()); updateCache(vaddr, pTable[vaddr]); } } @@ -118,9 +120,12 @@ bool PageTable::translate(Addr vaddr, Addr &paddr) { TheISA::TlbEntry entry; - if (!lookup(vaddr, entry)) + if (!lookup(vaddr, entry)) { + DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr); return false; - paddr = pageOffset(vaddr) + entry.pageStart; + } + paddr = pageOffset(vaddr) + entry.pageStart(); + DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr); return true; } @@ -151,7 +156,9 @@ PageTable::serialize(std::ostream &os) PTableItr iter = pTable.begin(); PTableItr end = pTable.end(); while (iter != end) { - paramOut(os, csprintf("ptable.entry%dvaddr", count), iter->first); + os << "\n[" << csprintf("%s.Entry%d", name(), count) << "]\n"; + + paramOut(os, "vaddr", iter->first); iter->second.serialize(os); ++iter; @@ -166,14 +173,15 @@ PageTable::unserialize(Checkpoint *cp, const std::string §ion) int i = 0, count; paramIn(cp, section, "ptable.size", count); Addr vaddr; - TheISA::TlbEntry entry; + TheISA::TlbEntry *entry; pTable.clear(); while(i < count) { - paramIn(cp, section, csprintf("ptable.entry%dvaddr", i), vaddr); - entry.unserialize(cp, section); - pTable[vaddr] = entry; + paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr); + entry = new TheISA::TlbEntry(); + entry->unserialize(cp, csprintf("%s.Entry%d", name(), i)); + pTable[vaddr] = *entry; ++i; } } diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh index 845bb9112..b8b52174c 100644 --- a/src/mem/page_table.hh +++ b/src/mem/page_table.hh @@ -46,7 +46,7 @@ #include "sim/host.hh" #include "sim/serialize.hh" -class System; +class Process; /** * Page Table Declaration. @@ -68,11 +68,11 @@ class PageTable const Addr pageSize; const Addr offsetMask; - System *system; + Process *process; public: - PageTable(System *_system, Addr _pageSize = TheISA::VMPageSize); + PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize); ~PageTable(); diff --git a/src/python/generate.py b/src/python/generate.py index 7c6ca1c5e..e52128de2 100644 --- a/src/python/generate.py +++ b/src/python/generate.py @@ -336,3 +336,194 @@ class Generate(object): arcname = py_compiled[zipname].arcname zf.write(zipname, arcname) zf.close() + + def traceFlagsPy(self, target, source, env): + assert(len(target) == 1) + + f = file(str(target[0]), 'w') + + allFlags = [] + for s in source: + val = eval(s.get_contents()) + allFlags.append(val) + + print >>f, 'baseFlags = [' + for flag, compound, desc in allFlags: + if not compound: + print >>f, " '%s'," % flag + print >>f, " ]" + print >>f + + print >>f, 'compoundFlags = [' + print >>f, " 'All'," + for flag, compound, desc in allFlags: + if compound: + print >>f, " '%s'," % flag + print >>f, " ]" + print >>f + + print >>f, "allFlags = frozenset(baseFlags + compoundFlags)" + print >>f + + print >>f, 'compoundFlagMap = {' + all = tuple([flag for flag,compound,desc in allFlags if not compound]) + print >>f, " 'All' : %s," % (all, ) + for flag, compound, desc in allFlags: + if compound: + print >>f, " '%s' : %s," % (flag, compound) + print >>f, " }" + print >>f + + print >>f, 'flagDescriptions = {' + print >>f, " 'All' : 'All flags'," + for flag, compound, desc in allFlags: + print >>f, " '%s' : '%s'," % (flag, desc) + print >>f, " }" + + f.close() + + def traceFlagsCC(self, target, source, env): + assert(len(target) == 1) + + f = file(str(target[0]), 'w') + + allFlags = [] + for s in source: + val = eval(s.get_contents()) + allFlags.append(val) + + # file header + print >>f, ''' +/* + * DO NOT EDIT THIS FILE! Automatically generated + */ + +#include "base/traceflags.hh" + +using namespace Trace; + +const char *Trace::flagStrings[] = +{''' + + # The string array is used by SimpleEnumParam to map the strings + # provided by the user to enum values. + for flag, compound, desc in allFlags: + if not compound: + print >>f, ' "%s",' % flag + + print >>f, ' "All",' + for flag, compound, desc in allFlags: + if compound: + print >>f, ' "%s",' % flag + + print >>f, '};' + print >>f + print >>f, 'const int Trace::numFlagStrings = %d;' % len(allFlags) + print >>f + + # + # Now define the individual compound flag arrays. There is an array + # for each compound flag listing the component base flags. + # + all = tuple([flag for flag,compound,desc in allFlags if not compound]) + print >>f, 'static const Flags AllMap[] = {' + for flag, compound, desc in allFlags: + if not compound: + print >>f, " %s," % flag + print >>f, '};' + print >>f + + for flag, compound, desc in allFlags: + if not compound: + continue + print >>f, 'static const Flags %sMap[] = {' % flag + for flag in compound: + print >>f, " %s," % flag + print >>f, " (Flags)-1" + print >>f, '};' + print >>f + + # + # Finally the compoundFlags[] array maps the compound flags + # to their individual arrays/ + # + print >>f, 'const Flags *Trace::compoundFlags[] =' + print >>f, '{' + print >>f, ' AllMap,' + for flag, compound, desc in allFlags: + if compound: + print >>f, ' %sMap,' % flag + # file trailer + print >>f, '};' + + f.close() + + def traceFlagsHH(self, target, source, env): + assert(len(target) == 1) + + f = file(str(target[0]), 'w') + + allFlags = [] + for s in source: + val = eval(s.get_contents()) + allFlags.append(val) + + # file header boilerplate + print >>f, ''' +/* + * DO NOT EDIT THIS FILE! + * + * Automatically generated from traceflags.py + */ + +#ifndef __BASE_TRACE_FLAGS_HH__ +#define __BASE_TRACE_FLAGS_HH__ + +namespace Trace { + +enum Flags {''' + + # Generate the enum. Base flags come first, then compound flags. + idx = 0 + for flag, compound, desc in allFlags: + if not compound: + print >>f, ' %s = %d,' % (flag, idx) + idx += 1 + + numBaseFlags = idx + print >>f, ' NumFlags = %d,' % idx + + # put a comment in here to separate base from compound flags + print >>f, ''' +// The remaining enum values are *not* valid indices for Trace::flags. +// They are "compound" flags, which correspond to sets of base +// flags, and are used by changeFlag.''' + + print >>f, ' All = %d,' % idx + idx += 1 + for flag, compound, desc in allFlags: + if compound: + print >>f, ' %s = %d,' % (flag, idx) + idx += 1 + + numCompoundFlags = idx - numBaseFlags + print >>f, ' NumCompoundFlags = %d' % numCompoundFlags + + # trailer boilerplate + print >>f, '''\ +}; // enum Flags + +// Array of strings for SimpleEnumParam +extern const char *flagStrings[]; +extern const int numFlagStrings; + +// Array of arraay pointers: for each compound flag, gives the list of +// base flags to set. Inidividual flag arrays are terminated by -1. +extern const Flags *compoundFlags[]; + +/* namespace Trace */ } + +#endif // __BASE_TRACE_FLAGS_HH__ +''' + + f.close() diff --git a/src/sim/Process.py b/src/sim/Process.py index 34ff6c394..07ed2c692 100644 --- a/src/sim/Process.py +++ b/src/sim/Process.py @@ -33,8 +33,10 @@ from m5.proxy import * class Process(SimObject): type = 'Process' abstract = True + input = Param.String('cin', "filename for stdin") output = Param.String('cout', 'filename for stdout/stderr') system = Param.System(Parent.any, "system process will run on") + max_stack_size = Param.MemorySize('64MB', 'maximum size of the stack') class LiveProcess(Process): type = 'LiveProcess' @@ -42,7 +44,6 @@ class LiveProcess(Process): cmd = VectorParam.String("command line (executable plus arguments)") env = VectorParam.String([], "environment settings") cwd = Param.String('', "current working directory") - input = Param.String('cin', "filename for stdin") uid = Param.Int(100, 'user id') euid = Param.Int(100, 'effective user id') gid = Param.Int(100, 'group id') diff --git a/src/sim/SConscript b/src/sim/SConscript index b0af4c795..0b39ab8e8 100644 --- a/src/sim/SConscript +++ b/src/sim/SConscript @@ -58,3 +58,18 @@ else: Source('process.cc') Source('syscall_emul.cc') + +TraceFlag('Config') +TraceFlag('Event') +TraceFlag('Fault') +TraceFlag('Flow') +TraceFlag('IPI') +TraceFlag('IPR') +TraceFlag('Interrupt') +TraceFlag('Loader') +TraceFlag('Stack') +TraceFlag('SyscallVerbose') +TraceFlag('TLB') +TraceFlag('Thread') +TraceFlag('Timer') +TraceFlag('VtoPhys') diff --git a/src/sim/process.cc b/src/sim/process.cc index f943cb565..668be367d 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -45,6 +45,7 @@ #include "mem/page_table.hh" #include "mem/physical.hh" #include "mem/translating_port.hh" +#include "params/Process.hh" #include "params/LiveProcess.hh" #include "sim/process.hh" #include "sim/process_impl.hh" @@ -83,13 +84,34 @@ using namespace TheISA; // current number of allocated processes int num_processes = 0; -Process::Process(const string &nm, - System *_system, - int stdin_fd, // initial I/O descriptors - int stdout_fd, - int stderr_fd) - : SimObject(makeParams(nm)), system(_system) +Process::Process(ProcessParams * params) + : SimObject(params), system(params->system), checkpointRestored(false), + max_stack_size(params->max_stack_size) { + string in = params->input; + string out = params->output; + + // initialize file descriptors to default: same as simulator + int stdin_fd, stdout_fd, stderr_fd; + + if (in == "stdin" || in == "cin") + stdin_fd = STDIN_FILENO; + else if (in == "None") + stdin_fd = -1; + else + stdin_fd = Process::openInputFile(in); + + if (out == "stdout" || out == "cout") + stdout_fd = STDOUT_FILENO; + else if (out == "stderr" || out == "cerr") + stdout_fd = STDERR_FILENO; + else if (out == "None") + stdout_fd = -1; + else + stdout_fd = Process::openOutputFile(out); + + stderr_fd = (stdout_fd != STDOUT_FILENO) ? stdout_fd : STDERR_FILENO; + M5_pid = system->allocatePID(); // initialize first 3 fds (stdin, stdout, stderr) fd_map[STDIN_FILENO] = stdin_fd; @@ -103,7 +125,7 @@ Process::Process(const string &nm, mmap_start = mmap_end = 0; nxm_start = nxm_end = 0; - pTable = new PageTable(system); + pTable = new PageTable(this); // other parameters will be initialized when the program is loaded } @@ -159,12 +181,12 @@ Process::registerThreadContext(ThreadContext *tc) int myIndex = threadContexts.size(); threadContexts.push_back(tc); -// RemoteGDB *rgdb = new RemoteGDB(system, tc); -// GDBListener *gdbl = new GDBListener(rgdb, 7000 + myIndex); -// gdbl->listen(); + RemoteGDB *rgdb = new RemoteGDB(system, tc); + GDBListener *gdbl = new GDBListener(rgdb, 7000 + myIndex); + gdbl->listen(); //gdbl->accept(); -// remoteGDB.push_back(rgdb); + remoteGDB.push_back(rgdb); // return CPU number to caller return myIndex; @@ -264,13 +286,16 @@ Process::checkAndAllocNextPage(Addr vaddr) // We've accessed the next page of the stack, so extend the stack // to cover it. - if(vaddr < stack_min && vaddr >= stack_min - TheISA::PageBytes) - { - stack_min -= TheISA::PageBytes; - if(stack_base - stack_min > 8*1024*1024) - fatal("Over max stack size for one thread\n"); - pTable->allocate(stack_min, TheISA::PageBytes); - warn("Increasing stack size by one page."); + if (vaddr < stack_min && vaddr >= stack_base - max_stack_size) { + while (vaddr < stack_min) { + stack_min -= TheISA::PageBytes; + if(stack_base - stack_min > max_stack_size) + fatal("Maximum stack size exceeded\n"); + if(stack_base - stack_min > 8*1024*1024) + fatal("Over max stack size for one thread\n"); + pTable->allocate(stack_min, TheISA::PageBytes); + warn("Increasing stack size by one page."); + }; return true; } return false; @@ -310,6 +335,10 @@ Process::unserialize(Checkpoint *cp, const std::string §ion) UNSERIALIZE_ARRAY(fd_map, MAX_FD); pTable->unserialize(cp, section); + + + checkpointRestored = true; + } @@ -320,25 +349,18 @@ Process::unserialize(Checkpoint *cp, const std::string §ion) //////////////////////////////////////////////////////////////////////// -LiveProcess::LiveProcess(const string &nm, ObjectFile *_objFile, - System *_system, - int stdin_fd, int stdout_fd, int stderr_fd, - vector<string> &_argv, vector<string> &_envp, - const string &_cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid) - : Process(nm, _system, stdin_fd, stdout_fd, stderr_fd), - objFile(_objFile), argv(_argv), envp(_envp), cwd(_cwd) +LiveProcess::LiveProcess(LiveProcessParams * params, ObjectFile *_objFile) + : Process(params), objFile(_objFile), + argv(params->cmd), envp(params->env), cwd(params->cwd) { - __uid = _uid; - __euid = _euid; - __gid = _gid; - __egid = _egid; - __pid = _pid; - __ppid = _ppid; + __uid = params->uid; + __euid = params->euid; + __gid = params->gid; + __egid = params->egid; + __pid = params->pid; + __ppid = params->ppid; - prog_fname = argv[0]; + prog_fname = params->cmd[0]; // load up symbols, if any... these may be used for debugging or // profiling. @@ -435,17 +457,12 @@ LiveProcess::syscall(int64_t callnum, ThreadContext *tc) } LiveProcess * -LiveProcess::create(const std::string &nm, System *system, int stdin_fd, - int stdout_fd, int stderr_fd, std::string executable, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid) +LiveProcess::create(LiveProcessParams * params) { LiveProcess *process = NULL; + string executable = + params->executable == "" ? params->cmd[0] : params->executable; ObjectFile *objFile = createObjectFile(executable); if (objFile == NULL) { fatal("Can't load object file %s", executable); @@ -456,28 +473,21 @@ LiveProcess::create(const std::string &nm, System *system, int stdin_fd, "executables are supported!\n Please recompile your " "executable as a static binary and try again.\n"); +#if THE_ISA == ALPHA_ISA if (objFile->hasTLS()) - fatal("Object file has a TLS section and loading of TLS sections " - "are not currently supported!\n Please recompile your " - "executable with a non-TLS toolchain or add TLS support to " - "M5 and try again\n"); + fatal("Object file has a TLS section and single threaded TLS is not\n" + " currently supported for Alpha! Please recompile your " + "executable with \n a non-TLS toolchain.\n"); -#if THE_ISA == ALPHA_ISA if (objFile->getArch() != ObjectFile::Alpha) fatal("Object file architecture does not match compiled ISA (Alpha)."); switch (objFile->getOpSys()) { case ObjectFile::Tru64: - process = new AlphaTru64Process(nm, objFile, system, - stdin_fd, stdout_fd, stderr_fd, - argv, envp, cwd, - _uid, _euid, _gid, _egid, _pid, _ppid); + process = new AlphaTru64Process(params, objFile); break; case ObjectFile::Linux: - process = new AlphaLinuxProcess(nm, objFile, system, - stdin_fd, stdout_fd, stderr_fd, - argv, envp, cwd, - _uid, _euid, _gid, _egid, _pid, _ppid); + process = new AlphaLinuxProcess(params, objFile); break; default: @@ -489,26 +499,15 @@ LiveProcess::create(const std::string &nm, System *system, int stdin_fd, switch (objFile->getOpSys()) { case ObjectFile::Linux: if (objFile->getArch() == ObjectFile::SPARC64) { - process = new Sparc64LinuxProcess(nm, objFile, system, - stdin_fd, stdout_fd, stderr_fd, - argv, envp, cwd, - _uid, _euid, _gid, - _egid, _pid, _ppid); + process = new Sparc64LinuxProcess(params, objFile); } else { - process = new Sparc32LinuxProcess(nm, objFile, system, - stdin_fd, stdout_fd, stderr_fd, - argv, envp, cwd, - _uid, _euid, _gid, - _egid, _pid, _ppid); + process = new Sparc32LinuxProcess(params, objFile); } break; case ObjectFile::Solaris: - process = new SparcSolarisProcess(nm, objFile, system, - stdin_fd, stdout_fd, stderr_fd, - argv, envp, cwd, - _uid, _euid, _gid, _egid, _pid, _ppid); + process = new SparcSolarisProcess(params, objFile); break; default: fatal("Unknown/unsupported operating system."); @@ -518,11 +517,7 @@ LiveProcess::create(const std::string &nm, System *system, int stdin_fd, fatal("Object file architecture does not match compiled ISA (x86)."); switch (objFile->getOpSys()) { case ObjectFile::Linux: - process = new X86LinuxProcess(nm, objFile, system, - stdin_fd, stdout_fd, stderr_fd, - argv, envp, cwd, - _uid, _euid, _gid, - _egid, _pid, _ppid); + process = new X86LinuxProcess(params, objFile); break; default: fatal("Unknown/unsupported operating system."); @@ -532,10 +527,7 @@ LiveProcess::create(const std::string &nm, System *system, int stdin_fd, fatal("Object file architecture does not match compiled ISA (MIPS)."); switch (objFile->getOpSys()) { case ObjectFile::Linux: - process = new MipsLinuxProcess(nm, objFile, system, - stdin_fd, stdout_fd, stderr_fd, - argv, envp, cwd, - _uid, _euid, _gid, _egid, _pid, _ppid); + process = new MipsLinuxProcess(params, objFile); break; default: @@ -554,29 +546,5 @@ LiveProcess::create(const std::string &nm, System *system, int stdin_fd, LiveProcess * LiveProcessParams::create() { - string in = input; - string out = output; - - // initialize file descriptors to default: same as simulator - int stdin_fd, stdout_fd, stderr_fd; - - if (in == "stdin" || in == "cin") - stdin_fd = STDIN_FILENO; - else - stdin_fd = Process::openInputFile(input); - - if (out == "stdout" || out == "cout") - stdout_fd = STDOUT_FILENO; - else if (out == "stderr" || out == "cerr") - stdout_fd = STDERR_FILENO; - else - stdout_fd = Process::openOutputFile(out); - - stderr_fd = (stdout_fd != STDOUT_FILENO) ? stdout_fd : STDERR_FILENO; - - return LiveProcess::create(name, system, - stdin_fd, stdout_fd, stderr_fd, - (string)executable == "" ? cmd[0] : executable, - cmd, env, cwd, - uid, euid, gid, egid, pid, ppid); + return LiveProcess::create(this); } diff --git a/src/sim/process.hh b/src/sim/process.hh index 83c00a676..0d2db959c 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -48,12 +48,14 @@ #include "sim/host.hh" #include "sim/sim_object.hh" -class ThreadContext; -class SyscallDesc; +class GDBListener; class PageTable; -class TranslatingPort; +class ProcessParams; +class LiveProcessParams; +class SyscallDesc; class System; -class GDBListener; +class ThreadContext; +class TranslatingPort; namespace TheISA { class RemoteGDB; @@ -72,6 +74,8 @@ class Process : public SimObject // created threads and are not initialized. bool initialContextLoaded; + bool checkpointRestored; + // thread contexts associated with this process std::vector<ThreadContext *> threadContexts; @@ -103,6 +107,9 @@ class Process : public SimObject unsigned stack_size; // initial stack size Addr stack_min; // lowest address accessed on the stack + // The maximum size allowed for the stack. + Addr max_stack_size; + // addr to use for next stack region (for multithreaded apps) Addr next_thread_stack_base; @@ -121,11 +128,7 @@ class Process : public SimObject protected: // constructor - Process(const std::string &nm, - System *_system, - int stdin_fd, // initial I/O descriptors - int stdout_fd, - int stderr_fd); + Process(ProcessParams * params); // post initialization startup virtual void startup(); @@ -195,14 +198,7 @@ class LiveProcess : public Process std::vector<std::string> envp; std::string cwd; - LiveProcess(const std::string &nm, ObjectFile *objFile, - System *_system, int stdin_fd, int stdout_fd, int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid); + LiveProcess(LiveProcessParams * params, ObjectFile *objFile); virtual void argsInit(int intSize, int pageSize); @@ -272,16 +268,7 @@ class LiveProcess : public Process // this function is used to create the LiveProcess object, since // we can't tell which subclass of LiveProcess to use until we // open and look at the object file. - static LiveProcess *create(const std::string &nm, - System *_system, - int stdin_fd, int stdout_fd, int stderr_fd, - std::string executable, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid); + static LiveProcess *create(LiveProcessParams * params); }; diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index 10127aa5f..157d39e93 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -105,7 +105,7 @@ namespace PseudoInst EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); - Tick resume = curTick + tc->getCpuPtr()->cycles(cycles); + Tick resume = curTick + tc->getCpuPtr()->ticks(cycles); quiesceEvent->reschedule(resume, true); diff --git a/src/sim/system.cc b/src/sim/system.cc index 41c1b94e3..7dc1d2ba9 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -240,7 +240,9 @@ System::serialize(ostream &os) { #if FULL_SYSTEM kernelSymtab->serialize("kernel_symtab", os); -#endif // FULL_SYSTEM +#else // !FULL_SYSTEM + SERIALIZE_SCALAR(page_ptr); +#endif } @@ -249,7 +251,9 @@ System::unserialize(Checkpoint *cp, const string §ion) { #if FULL_SYSTEM kernelSymtab->unserialize("kernel_symtab", cp, section); -#endif // FULL_SYSTEM +#else // !FULL_SYSTEM + UNSERIALIZE_SCALAR(page_ptr); +#endif } void diff --git a/src/sim/vptr.hh b/src/sim/vptr.hh index bcc22f0ca..383f65351 100644 --- a/src/sim/vptr.hh +++ b/src/sim/vptr.hh @@ -33,6 +33,7 @@ #include "arch/vtophys.hh" #include "arch/isa_traits.hh" +#include "mem/vport.hh" class ThreadContext; @@ -42,82 +43,95 @@ class VPtr public: typedef T Type; - private: + protected: ThreadContext *tc; Addr ptr; + Addr buffer[(sizeof(T)-1)/sizeof(Addr) + 1]; public: - ThreadContext *GetTC() const { return tc; } - Addr GetPointer() const { return ptr; } + explicit VPtr(ThreadContext *_tc, Addr p = 0) + : tc(_tc), ptr(p) + { + refresh(); + } - public: - explicit VPtr(ThreadContext *_tc, Addr p = 0) : tc(_tc), ptr(p) { } template <class U> - VPtr(const VPtr<U> &vp) : tc(vp.GetTC()), ptr(vp.GetPointer()) {} - ~VPtr() {} + VPtr(const VPtr<U> &vp) + : tc(vp.tc), ptr(vp.ptr) + { + refresh(); + } + + ~VPtr() + {} - bool operator!() const + void + refresh() { - return ptr == 0; + if (!ptr) + return; + + VirtualPort *port = tc->getVirtPort(tc); + port->readBlob(ptr, buffer, sizeof(T)); + tc->delVirtPort(port); } - VPtr<T> operator+(int offset) + bool + operator!() const { - VPtr<T> ptr(*this); - ptr += offset; + return ptr == 0; + } - return ptr; + VPtr<T> + operator+(int offset) + { + return VPtr<T>(tc, ptr + offset); } - const VPtr<T> &operator+=(int offset) + const VPtr<T> & + operator+=(int offset) { ptr += offset; - assert((ptr & (TheISA::PageBytes - 1)) + sizeof(T) - < TheISA::PageBytes); + refresh(); return *this; } - const VPtr<T> &operator=(Addr p) + const VPtr<T> & + operator=(Addr p) { - assert((p & (TheISA::PageBytes - 1)) + sizeof(T) - < TheISA::PageBytes); ptr = p; + refresh(); return *this; } template <class U> - const VPtr<T> &operator=(const VPtr<U> &vp) + const VPtr<T> & + operator=(const VPtr<U> &vp) { - tc = vp.GetTC(); - ptr = vp.GetPointer(); + tc = vp.tc; + ptr = vp.ptr; + refresh(); return *this; } operator T *() { - panic("Needs to be rewritten\n"); -/* void *addr = vtomem(tc, ptr, sizeof(T)); - return (T *)addr; - */ + return (T *)buffer; } - T *operator->() + T * + operator->() { - panic("Needs to be rewritten\n"); -/* void *addr = vtomem(tc, ptr, sizeof(T)); - return (T *)addr; - */ + return (T *)buffer; } - T &operator*() + T & + operator*() { - panic("Needs to be rewritten\n"); -/* void *addr = vtomem(tc, ptr, sizeof(T)); - return *(T *)addr; - */ + return *(T *)buffer; } }; diff --git a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt index 0a81b23fb..c535b6427 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 4207318 # Nu global.BPredUnit.condPredicted 70088985 # Number of conditional branches predicted global.BPredUnit.lookups 76017379 # Number of BP lookups global.BPredUnit.usedRAS 1692882 # Number of times the RAS was used to get a target. -host_inst_rate 211348 # Simulator instruction rate (inst/s) -host_mem_usage 182448 # Number of bytes of host memory used -host_seconds 2675.93 # Real time elapsed on the host -host_tick_rate 60738573 # Simulator tick rate (ticks/s) +host_inst_rate 209676 # Simulator instruction rate (inst/s) +host_mem_usage 200632 # Number of bytes of host memory used +host_seconds 2697.27 # Real time elapsed on the host +host_tick_rate 60257939 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 16721732 # Number of conflicting loads. memdepunit.memDep.conflictingStores 11866335 # Number of conflicting stores. memdepunit.memDep.insertedLoads 126743752 # Number of loads inserted to the mem dependence unit. @@ -157,7 +157,7 @@ system.cpu.fetch.SquashCycles 4233156 # Nu system.cpu.fetch.branchRate 0.233854 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 65923007 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 67369318 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.146836 # Number of inst fetches per cycle +system.cpu.fetch.rate 2.146834 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 325063615 system.cpu.fetch.rateDist.min_value 0 @@ -236,10 +236,10 @@ system.cpu.icache.tagsinuse 770.534444 # Cy system.cpu.icache.total_refs 65922018 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 190397 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 278 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 67319692 # Number of branches executed system.cpu.iew.EXEC:nop 42991424 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.842347 # Inst execution rate +system.cpu.iew.EXEC:rate 1.842345 # Inst execution rate system.cpu.iew.EXEC:refs 163918711 # number of memory reference insts executed system.cpu.iew.EXEC:stores 41167815 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -249,7 +249,7 @@ system.cpu.iew.WB:fanout 0.805927 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 395691865 # num instructions producing a value -system.cpu.iew.WB:rate 1.832664 # insts written-back per cycle +system.cpu.iew.WB:rate 1.832662 # insts written-back per cycle system.cpu.iew.WB:sent 596897738 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 4671822 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 211982 # Number of cycles IEW is blocking @@ -279,8 +279,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 3229074 # system.cpu.iew.memOrderViolationEvents 28955 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 540642 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 4131180 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.739821 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.739821 # IPC: Total IPC of All Threads +system.cpu.ipc 1.739819 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.739819 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 605296760 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued @@ -331,7 +331,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.862087 # Inst issue rate +system.cpu.iq.ISSUE:rate 1.862085 # Inst issue rate system.cpu.iq.iqInstsAdded 619382498 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 605296760 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ @@ -428,7 +428,7 @@ system.cpu.l2cache.tagsinuse 8150.643180 # Cy system.cpu.l2cache.total_refs 66110 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 325063615 # number of cpu cycles simulated +system.cpu.numCycles 325063893 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 11040699 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 31586100 # Number of times rename has blocked due to IQ full diff --git a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt index b76b4e6c1..9e54c6441 100644 --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1730291 # Simulator instruction rate (inst/s) -host_mem_usage 181616 # Number of bytes of host memory used -host_seconds 347.84 # Real time elapsed on the host -host_tick_rate 2208778962 # Simulator tick rate (ticks/s) +host_inst_rate 1400395 # Simulator instruction rate (inst/s) +host_mem_usage 199872 # Number of bytes of host memory used +host_seconds 429.78 # Real time elapsed on the host +host_tick_rate 1787654853 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.768293 # Number of seconds simulated @@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs 52084 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 768292872000 # number of cpu cycles simulated +system.cpu.numCycles 1536585744 # number of cpu cycles simulated system.cpu.num_insts 601856964 # Number of instructions executed system.cpu.num_refs 154866966 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt index f737a8e3b..ae6ff07ca 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 84447535 # Nu global.BPredUnit.condPredicted 256528366 # Number of conditional branches predicted global.BPredUnit.lookups 256528366 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 94020 # Simulator instruction rate (inst/s) -host_mem_usage 184848 # Number of bytes of host memory used -host_seconds 14950.16 # Real time elapsed on the host -host_tick_rate 73409017 # Simulator tick rate (ticks/s) +host_inst_rate 101903 # Simulator instruction rate (inst/s) +host_mem_usage 202864 # Number of bytes of host memory used +host_seconds 13793.57 # Real time elapsed on the host +host_tick_rate 79564409 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 458856790 # Number of conflicting loads. memdepunit.memDep.conflictingStores 141228058 # Number of conflicting stores. memdepunit.memDep.insertedLoads 745627925 # Number of loads inserted to the mem dependence unit. @@ -229,7 +229,7 @@ system.cpu.icache.tagsinuse 1042.348080 # Cy system.cpu.icache.total_refs 355014725 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 94965 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 155 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 128778452 # Number of branches executed system.cpu.iew.EXEC:nop 354384689 # number of nop insts executed system.cpu.iew.EXEC:rate 0.865881 # Inst execution rate @@ -242,7 +242,7 @@ system.cpu.iew.WB:fanout 0.963032 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 1442442170 # num instructions producing a value -system.cpu.iew.WB:rate 0.850638 # insts written-back per cycle +system.cpu.iew.WB:rate 0.850637 # insts written-back per cycle system.cpu.iew.WB:sent 1877161076 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 91327681 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 454443 # Number of cycles IEW is blocking @@ -417,7 +417,7 @@ system.cpu.l2cache.tagsinuse 8527.413561 # Cy system.cpu.l2cache.total_refs 96715 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 2194953627 # number of cpu cycles simulated +system.cpu.numCycles 2194953782 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 13000888 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1244771057 # Number of HB maps that are committed system.cpu.rename.RENAME:FullRegisterEvents 9 # Number of times there has been no free registers diff --git a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr index 6fe2fe04f..70bd1351f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr @@ -1,6 +1,2 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0xb4000 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr index 6fe2fe04f..70bd1351f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr @@ -1,6 +1,2 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0xb4000 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt index 2a33edee7..50e7d390e 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1120793 # Simulator instruction rate (inst/s) -host_mem_usage 183848 # Number of bytes of host memory used -host_seconds 1328.98 # Real time elapsed on the host -host_tick_rate 1558243449 # Simulator tick rate (ticks/s) +host_inst_rate 1001521 # Simulator instruction rate (inst/s) +host_mem_usage 201940 # Number of bytes of host memory used +host_seconds 1487.25 # Real time elapsed on the host +host_tick_rate 1392419330 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1489514761 # Number of instructions simulated sim_seconds 2.070880 # Number of seconds simulated @@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs 62289 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2070879986000 # number of cpu cycles simulated +system.cpu.numCycles 4141759972 # number of cpu cycles simulated system.cpu.num_insts 1489514761 # Number of instructions executed system.cpu.num_refs 569364430 # Number of memory references system.cpu.workload.PROG:num_syscalls 19 # Number of system calls diff --git a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr index 6fe2fe04f..70bd1351f 100644 --- a/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr @@ -1,6 +1,2 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0xb4000 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini new file mode 100644 index 000000000..b66960bf9 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini @@ -0,0 +1,80 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/gzip +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..186158b96 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1240763 # Simulator instruction rate (inst/s) +host_mem_usage 175872 # Number of bytes of host memory used +host_seconds 1292.50 # Real time elapsed on the host +host_tick_rate 738827746 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1603680167 # Number of instructions simulated +sim_seconds 0.954932 # Number of seconds simulated +sim_ticks 954931687500 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1909863376 # number of cpu cycles simulated +system.cpu.num_insts 1603680167 # Number of instructions executed +system.cpu.num_refs 607157396 # Number of memory references +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr new file mode 100644 index 000000000..01076d21a --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr @@ -0,0 +1,6 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: instruction 'rdtsc' unimplemented +warn: Increasing stack size by one page. diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout new file mode 100644 index 000000000..b0a68cad2 --- /dev/null +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout @@ -0,0 +1,44 @@ +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Oct 21 2007 20:57:52 +M5 started Sun Oct 21 21:35:26 2007 +M5 executing on nacho +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic tests/run.py long/00.gzip/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 954931687500 because target called exit() diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr index cf178f133..70bd1351f 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr @@ -1,6 +1,2 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0xa2000 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt index 7fd034515..825271309 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1059302 # Simulator instruction rate (inst/s) -host_mem_usage 184256 # Number of bytes of host memory used -host_seconds 230.18 # Real time elapsed on the host -host_tick_rate 1578613892 # Simulator tick rate (ticks/s) +host_inst_rate 981553 # Simulator instruction rate (inst/s) +host_mem_usage 203224 # Number of bytes of host memory used +host_seconds 248.41 # Real time elapsed on the host +host_tick_rate 1462749007 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 243829010 # Number of instructions simulated sim_seconds 0.363364 # Number of seconds simulated @@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs 553407 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 363364127000 # number of cpu cycles simulated +system.cpu.numCycles 726728254 # number of cpu cycles simulated system.cpu.num_insts 243829010 # Number of instructions executed system.cpu.num_refs 105710359 # Number of memory references system.cpu.workload.PROG:num_syscalls 428 # Number of system calls diff --git a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr index cf178f133..70bd1351f 100644 --- a/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr @@ -1,6 +1,2 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0xa2000 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini new file mode 100644 index 000000000..527f1b385 --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -0,0 +1,80 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=mcf mcf.in +cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +gid=100 +input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:268435455 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..794286196 --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1168424 # Simulator instruction rate (inst/s) +host_mem_usage 310284 # Number of bytes of host memory used +host_seconds 230.78 # Real time elapsed on the host +host_tick_rate 718029499 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 269642969 # Number of instructions simulated +sim_seconds 0.165704 # Number of seconds simulated +sim_ticks 165703616000 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 331407233 # number of cpu cycles simulated +system.cpu.num_insts 269642969 # Number of instructions executed +system.cpu.num_refs 124052668 # Number of memory references +system.cpu.workload.PROG:num_syscalls 429 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out b/tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out new file mode 100644 index 000000000..095132477 --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out @@ -0,0 +1,999 @@ +() +500 +() +499 +() +498 +() +496 +() +495 +() +494 +() +493 +() +492 +() +491 +() +490 +() +489 +() +488 +() +487 +() +486 +() +484 +() +482 +() +481 +() +480 +() +479 +() +478 +() +477 +() +476 +() +475 +() +474 +() +473 +() +472 +() +471 +() +469 +() +468 +() +467 +() +466 +() +465 +() +464 +() +463 +() +462 +() +461 +() +460 +() +459 +() +458 +() +457 +() +455 +() +454 +() +452 +() +451 +() +450 +() +449 +() +448 +() +446 +() +445 +() +444 +() +443 +() +442 +() +440 +() +439 +() +438 +() +436 +() +435 +() +433 +() +432 +() +431 +() +428 +() +427 +() +425 +() +424 +() +423 +() +420 +() +419 +() +416 +() +414 +() +413 +() +412 +() +407 +() +406 +() +405 +() +404 +() +403 +() +402 +() +401 +() +400 +() +399 +() +398 +() +396 +() +395 +() +393 +() +392 +() +390 +() +389 +() +388 +() +387 +() +386 +() +385 +() +384 +() +383 +() +382 +() +381 +() +380 +() +379 +() +377 +() +375 +() +374 +() +373 +() +372 +() +371 +() +370 +() +369 +() +368 +() +366 +() +365 +() +364 +() +362 +() +361 +() +360 +() +359 +() +358 +() +357 +() +356 +() +355 +() +354 +() +352 +() +350 +() +347 +() +344 +() +342 +() +341 +() +340 +() +339 +() +338 +() +332 +() +325 +() +320 +*** +345 +() +319 +*** +497 +() +318 +*** +349 +() +317 +*** +408 +() +316 +*** +324 +() +315 +*** +328 +() +314 +*** +335 +() +313 +*** +378 +() +312 +*** +426 +() +311 +*** +411 +() +304 +*** +343 +() +303 +*** +417 +() +302 +*** +485 +() +301 +*** +363 +() +300 +*** +376 +() +299 +*** +333 +() +292 +*** +337 +() +291 +*** +409 +() +290 +*** +421 +() +289 +*** +437 +() +288 +*** +430 +() +287 +*** +348 +() +286 +*** +326 +() +284 +() +282 +*** +308 +() +279 +*** +297 +*** +305 +() +278 +() +277 +*** +307 +() +276 +*** +296 +() +273 +() +271 +() +265 +() +246 +*** +267 +() +245 +*** +280 +() +244 +*** +391 +() +243 +*** +330 +() +242 +*** +456 +() +241 +*** +346 +() +240 +*** +483 +() +239 +*** +260 +() +238 +*** +261 +() +237 +*** +262 +*** +294 +() +236 +*** +253 +() +229 +*** +397 +() +228 +*** +298 +() +227 +*** +415 +() +226 +*** +264 +() +224 +*** +232 +() +222 +*** +233 +() +217 +*** +250 +() +211 +*** +331 +() +210 +*** +394 +() +209 +*** +410 +() +208 +*** +321 +() +207 +*** +327 +() +206 +*** +309 +() +199 +*** +259 +() +198 +*** +219 +() +197 +*** +220 +() +195 +*** +429 +() +194 +*** +470 +() +193 +*** +274 +() +191 +*** +203 +() +190 +*** +263 +() +189 +215 +*** +230 +() +188 +*** +266 +*** +295 +() +182 +*** +329 +() +181 +*** +351 +() +180 +*** +441 +() +179 +*** +453 +() +178 +*** +418 +() +177 +*** +353 +() +176 +*** +422 +() +175 +*** +225 +*** +255 +() +174 +*** +269 +() +173 +*** +214 +() +172 +*** +186 +() +171 +*** +447 +() +170 +*** +270 +*** +306 +() +169 +*** +336 +() +168 +*** +285 +() +165 +*** +249 +() +146 +*** +154 +() +143 +*** +334 +() +142 +*** +216 +*** +257 +() +141 +*** +167 +*** +251 +() +140 +*** +162 +*** +293 +() +139 +*** +158 +() +137 +*** +166 +*** +201 +() +136 +*** +160 +() +134 +*** +221 +() +132 +*** +213 +() +131 +*** +187 +() +129 +*** +235 +() +128 +*** +153 +() +127 +*** +156 +() +126 +*** +159 +*** +218 +() +125 +*** +155 +() +124 +*** +157 +() +123 +*** +152 +() +116 +*** +135 +*** +163 +() +115 +*** +133 +*** +204 +*** +248 +() +114 +*** +192 +*** +212 +() +113 +*** +268 +() +112 +*** +367 +() +111 +*** +272 +() +110 +*** +434 +() +109 +*** +323 +() +108 +*** +281 +() +107 +*** +144 +*** +148 +() +106 +*** +275 +() +105 +*** +196 +*** +254 +() +104 +*** +138 +*** +161 +() +103 +*** +310 +() +102 +*** +223 +*** +252 +() +80 +() +70 +() +69 +() +68 +() +66 +() +64 +() +62 +*** +256 +() +61 +*** +93 +() +59 +*** +120 +() +58 +() +57 +*** +183 +() +55 +() +54 +() +52 +*** +147 +() +51 +*** +118 +() +50 +*** +83 +() +49 +*** +98 +() +48 +*** +99 +() +47 +() +46 +*** +184 +() +45 +*** +121 +() +44 +() +43 +*** +88 +() +42 +*** +122 +() +41 +*** +91 +() +40 +*** +96 +() +38 +*** +100 +() +37 +*** +149 +() +36 +*** +74 +() +35 +*** +258 +() +34 +*** +151 +() +33 +*** +85 +() +32 +() +31 +*** +94 +() +30 +*** +97 +() +29 +*** +90 +() +28 +*** +89 +() +27 +*** +92 +() +26 +*** +72 +*** +247 +() +25 +*** +86 +() +24 +*** +82 +() +23 +*** +87 +*** +117 +() +22 +*** +76 +*** +119 +() +21 +*** +84 +() +20 +*** +78 +() +19 +*** +73 +() +18 +*** +81 +() +17 +*** +65 +() +16 +*** +63 +*** +101 +() +15 +*** +71 +() +14 +*** +75 +() +13 +*** +322 +() +12 +*** +77 +() +11 +*** +283 +() +10 +*** +79 +() +9 +*** +145 +*** +150 +() +8 +*** +67 +() +7 +*** +60 +*** +231 +() +6 +*** +56 +*** +234 +() +5 +*** +164 +*** +202 +() +4 +*** +53 +() +3 +*** +130 +*** +185 +*** +200 +() +2 +*** +205 +() +1 +*** +39 +*** +95 diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr new file mode 100644 index 000000000..863f1adb9 --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr @@ -0,0 +1,5 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: instruction 'rdtsc' unimplemented diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout new file mode 100644 index 000000000..743c3e8f1 --- /dev/null +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout @@ -0,0 +1,29 @@ + +MCF SPEC version 1.6.I +by Andreas Loebel +Copyright (c) 1998,1999 ZIB Berlin +All Rights Reserved. + +nodes : 500 +active arcs : 1905 +simplex iterations : 1502 +flow value : 4990014995 +new implicit arcs : 23867 +active arcs : 25772 +simplex iterations : 2663 +flow value : 3080014995 +checksum : 68389 +optimal +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Oct 21 2007 20:57:52 +M5 started Sun Oct 21 21:57:00 2007 +M5 executing on nacho +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic tests/run.py long/10.mcf/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 165703616000 because target called exit() diff --git a/tests/long/10.mcf/test.py b/tests/long/10.mcf/test.py index cb8acff22..c4ffb248a 100644 --- a/tests/long/10.mcf/test.py +++ b/tests/long/10.mcf/test.py @@ -31,3 +31,4 @@ from cpu2000 import mcf workload = mcf(isa, opsys, 'smred') root.system.cpu.workload = workload.makeLiveProcess() +root.system.physmem.range=AddrRange('256MB') diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini new file mode 100644 index 000000000..10efbab5f --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -0,0 +1,80 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=parser 2.1.dict -batch +cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/parser +gid=100 +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..e1f98313b --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1244280 # Simulator instruction rate (inst/s) +host_mem_usage 179592 # Number of bytes of host memory used +host_seconds 1193.15 # Real time elapsed on the host +host_tick_rate 723499766 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1484611664 # Number of instructions simulated +sim_seconds 0.863243 # Number of seconds simulated +sim_ticks 863243462500 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 1726486926 # number of cpu cycles simulated +system.cpu.num_insts 1484611664 # Number of instructions executed +system.cpu.num_refs 533543283 # Number of memory references +system.cpu.workload.PROG:num_syscalls 541 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr b/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr new file mode 100644 index 000000000..46a429e22 --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stderr @@ -0,0 +1,8 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: instruction 'rdtsc' unimplemented +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout new file mode 100644 index 000000000..372af2d77 --- /dev/null +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stdout @@ -0,0 +1,72 @@ + + Reading the dictionary files: ************************************************* + 58924 words stored in 3784810 bytes + + +Welcome to the Link Parser -- Version 2.1 + + Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley + +Processing sentences in batch mode + +Echoing of input sentence turned on. +* as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +* how fast the program is it +* I am wondering whether to invite to the party +* I gave him for his birthday it +* I thought terrible after our discussion +* I wonder how much money have you earned +* Janet who is an expert on dogs helped me choose one +* she interviewed more programmers than was hired +* such flowers are found chiefly particularly in Europe +* the dogs some of which were very large ran after the man +* the man whom I play tennis is here +* there is going to be an important meeting January +* to pretend that our program is usable in its current form would be happy +* we're thinking about going to a movie this theater +* which dog you said you chased +- also invited to the meeting were several prominent scientists +- he ran home so quickly that his mother could hardly believe he had called from school +- so many people attended that they spilled over into several neighboring fields +- voting in favor of the bill were 36 Republicans and 4 moderate Democrats +: Grace may not be possible to fix the problem + any program as good as ours should be useful + biochemically , I think the experiment has a lot of problems + Fred has had five years of experience as a programmer + he is looking for another job + how did John do it + how many more people do you think will come + how much more spilled + I have more money than John has time + I made it clear that I was angry + I wonder how John did it + I wonder how much more quickly he ran + invite John and whoever else you want to invite + it is easier to ignore the problem than it is to solve it + many who initially supported Thomas later changed their minds + neither Mary nor Louise are coming to the party + she interviewed more programmers than were hired + telling Joe that Sue was coming to the party would create a real problem + the man with whom I play tennis is here + there is a dog in the park + this is not the man we know and love + we like to eat at restaurants , usually on weekends + what did John say he thought you should do + about 2 million people attended + the five best costumes got prizes +No errors! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Oct 21 2007 20:57:52 +M5 started Sun Oct 21 22:00:51 2007 +M5 executing on nacho +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic tests/run.py long/20.parser/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 863243462500 because target called exit() diff --git a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt index 373ebcd68..f75afa011 100644 --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 5797485 # Nu global.BPredUnit.condPredicted 35586107 # Number of conditional branches predicted global.BPredUnit.lookups 62816866 # Number of BP lookups global.BPredUnit.usedRAS 12584281 # Number of times the RAS was used to get a target. -host_inst_rate 159982 # Simulator instruction rate (inst/s) -host_mem_usage 190068 # Number of bytes of host memory used -host_seconds 2347.61 # Real time elapsed on the host -host_tick_rate 55593251 # Simulator tick rate (ticks/s) +host_inst_rate 162238 # Simulator instruction rate (inst/s) +host_mem_usage 208244 # Number of bytes of host memory used +host_seconds 2314.96 # Real time elapsed on the host +host_tick_rate 56377317 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 72605768 # Number of conflicting loads. memdepunit.memDep.conflictingStores 52678550 # Number of conflicting stores. memdepunit.memDep.insertedLoads 125601766 # Number of loads inserted to the mem dependence unit. @@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 215 # Th system.cpu.commit.commitSquashedInsts 97412298 # The number of squashed insts skipped by commit system.cpu.committedInsts 375574833 # Number of Instructions Simulated system.cpu.committedInsts_total 375574833 # Number of Instructions Simulated -system.cpu.cpi 0.694992 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.694992 # CPI: Total CPI of All Threads +system.cpu.cpi 0.694995 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.694995 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits system.cpu.dcache.ReadReq_accesses 96463931 # number of ReadReq accesses(hits+misses) @@ -154,10 +154,10 @@ system.cpu.fetch.Cycles 169349894 # Nu system.cpu.fetch.IcacheSquashes 1380085 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 550063393 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 6176073 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.240658 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.240657 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 64526365 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 49445851 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.107348 # Number of inst fetches per cycle +system.cpu.fetch.rate 2.107339 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 261021562 system.cpu.fetch.rateDist.min_value 0 @@ -236,10 +236,10 @@ system.cpu.icache.tagsinuse 1827.041992 # Cy system.cpu.icache.total_refs 64522273 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 787561 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 1138 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 51184181 # Number of branches executed system.cpu.iew.EXEC:nop 27521515 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.613810 # Inst execution rate +system.cpu.iew.EXEC:rate 1.613803 # Inst execution rate system.cpu.iew.EXEC:refs 192783461 # number of memory reference insts executed system.cpu.iew.EXEC:stores 80743835 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -249,7 +249,7 @@ system.cpu.iew.WB:fanout 0.706015 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 200824371 # num instructions producing a value -system.cpu.iew.WB:rate 1.598292 # insts written-back per cycle +system.cpu.iew.WB:rate 1.598285 # insts written-back per cycle system.cpu.iew.WB:sent 418096768 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 6170690 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 1426561 # Number of cycles IEW is blocking @@ -279,8 +279,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 19324087 # system.cpu.iew.memOrderViolationEvents 574238 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 908757 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 5261933 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.438865 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.438865 # IPC: Total IPC of All Threads +system.cpu.ipc 1.438859 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.438859 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 431234771 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 33581 0.01% # Type of FU issued @@ -331,7 +331,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.652104 # Inst issue rate +system.cpu.iq.ISSUE:rate 1.652097 # Inst issue rate system.cpu.iq.iqInstsAdded 468556087 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 431234771 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ @@ -428,7 +428,7 @@ system.cpu.l2cache.tagsinuse 3522.085649 # Cy system.cpu.l2cache.total_refs 573 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 261021562 # number of cpu cycles simulated +system.cpu.numCycles 261022700 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 4632657 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 259532351 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 371371 # Number of times rename has blocked due to IQ full diff --git a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt index 9be74e08a..ebb18ce61 100644 --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1404632 # Simulator instruction rate (inst/s) -host_mem_usage 189192 # Number of bytes of host memory used -host_seconds 283.82 # Real time elapsed on the host -host_tick_rate 1998169503 # Simulator tick rate (ticks/s) +host_inst_rate 1238026 # Simulator instruction rate (inst/s) +host_mem_usage 207368 # Number of bytes of host memory used +host_seconds 322.02 # Real time elapsed on the host +host_tick_rate 1761163764 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated sim_seconds 0.567124 # Number of seconds simulated @@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs 510 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 567124013000 # number of cpu cycles simulated +system.cpu.numCycles 1134248026 # number of cpu cycles simulated system.cpu.num_insts 398664609 # Number of instructions executed system.cpu.num_refs 174183455 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt index 4725fc27c..0c4f37988 100644 --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1524477 # Simulator instruction rate (inst/s) -host_mem_usage 188336 # Number of bytes of host memory used -host_seconds 1317.82 # Real time elapsed on the host -host_tick_rate 2100501698 # Simulator tick rate (ticks/s) +host_inst_rate 1159414 # Simulator instruction rate (inst/s) +host_mem_usage 206548 # Number of bytes of host memory used +host_seconds 1732.76 # Real time elapsed on the host +host_tick_rate 1597499589 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 2.768086 # Number of seconds simulated @@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs 22612 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2768085828000 # number of cpu cycles simulated +system.cpu.numCycles 5536171656 # number of cpu cycles simulated system.cpu.num_insts 2008987605 # Number of instructions executed system.cpu.num_refs 722823898 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls diff --git a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt index b4b0c54a3..15ee80644 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 455902 # Nu global.BPredUnit.condPredicted 10551273 # Number of conditional branches predicted global.BPredUnit.lookups 16246333 # Number of BP lookups global.BPredUnit.usedRAS 1941036 # Number of times the RAS was used to get a target. -host_inst_rate 173213 # Simulator instruction rate (inst/s) -host_mem_usage 193376 # Number of bytes of host memory used -host_seconds 459.50 # Real time elapsed on the host -host_tick_rate 54150958 # Simulator tick rate (ticks/s) +host_inst_rate 178455 # Simulator instruction rate (inst/s) +host_mem_usage 211564 # Number of bytes of host memory used +host_seconds 446.00 # Real time elapsed on the host +host_tick_rate 55789781 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 12304370 # Number of conflicting loads. memdepunit.memDep.conflictingStores 10964244 # Number of conflicting stores. memdepunit.memDep.insertedLoads 22974359 # Number of loads inserted to the mem dependence unit. @@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 4583 # Th system.cpu.commit.commitSquashedInsts 8051078 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.625230 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.625230 # CPI: Total CPI of All Threads +system.cpu.cpi 0.625252 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.625252 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits system.cpu.dcache.ReadReq_accesses 20377695 # number of ReadReq accesses(hits+misses) @@ -154,10 +154,10 @@ system.cpu.fetch.Cycles 33194597 # Nu system.cpu.fetch.IcacheSquashes 152184 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 103251284 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 572846 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.326473 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.326461 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 13375683 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 9942709 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.074854 # Number of inst fetches per cycle +system.cpu.fetch.rate 2.074780 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 49763148 system.cpu.fetch.rateDist.min_value 0 @@ -236,10 +236,10 @@ system.cpu.icache.tagsinuse 1922.769682 # Cy system.cpu.icache.total_refs 13289333 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 21643859000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1231826 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 1791 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 14739683 # Number of branches executed system.cpu.iew.EXEC:nop 9380523 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.704450 # Inst execution rate +system.cpu.iew.EXEC:rate 1.704389 # Inst execution rate system.cpu.iew.EXEC:refs 36969776 # number of memory reference insts executed system.cpu.iew.EXEC:stores 15295559 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -249,7 +249,7 @@ system.cpu.iew.WB:fanout 0.765386 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 32456867 # num instructions producing a value -system.cpu.iew.WB:rate 1.694688 # insts written-back per cycle +system.cpu.iew.WB:rate 1.694627 # insts written-back per cycle system.cpu.iew.WB:sent 84566644 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 400717 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 20492 # Number of cycles IEW is blocking @@ -279,8 +279,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 1453767 # system.cpu.iew.memOrderViolationEvents 19531 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 108348 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 292369 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.599412 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.599412 # IPC: Total IPC of All Threads +system.cpu.ipc 1.599354 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.599354 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 85364731 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued @@ -331,7 +331,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.715421 # Inst issue rate +system.cpu.iq.ISSUE:rate 1.715359 # Inst issue rate system.cpu.iq.iqInstsAdded 89442204 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 85364731 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 4987 # Number of non-speculative instructions added to the IQ @@ -428,7 +428,7 @@ system.cpu.l2cache.tagsinuse 4581.530519 # Cy system.cpu.l2cache.total_refs 102503 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 49763148 # number of cpu cycles simulated +system.cpu.numCycles 49764939 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 263435 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 34724 # Number of times rename has blocked due to IQ full diff --git a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt index 42618bd93..c05407db8 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1453070 # Simulator instruction rate (inst/s) -host_mem_usage 191752 # Number of bytes of host memory used -host_seconds 60.80 # Real time elapsed on the host -host_tick_rate 2124138006 # Simulator tick rate (ticks/s) +host_inst_rate 1210019 # Simulator instruction rate (inst/s) +host_mem_usage 209960 # Number of bytes of host memory used +host_seconds 73.01 # Real time elapsed on the host +host_tick_rate 1768843958 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.129140 # Number of seconds simulated @@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs 93692 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 129139604000 # number of cpu cycles simulated +system.cpu.numCycles 258279208 # number of cpu cycles simulated system.cpu.num_insts 88340673 # Number of instructions executed system.cpu.num_refs 35321418 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr index 08cfb2451..2e627b821 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr @@ -1,7 +1,3 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x1838c0 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: ignoring syscall time(4026527856, 4026528256, ...) diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt index 2bb84bd57..8b535e51e 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 960220 # Simulator instruction rate (inst/s) -host_mem_usage 192724 # Number of bytes of host memory used -host_seconds 141.78 # Real time elapsed on the host -host_tick_rate 1412855280 # Simulator tick rate (ticks/s) +host_inst_rate 941673 # Simulator instruction rate (inst/s) +host_mem_usage 210848 # Number of bytes of host memory used +host_seconds 144.57 # Real time elapsed on the host +host_tick_rate 1385565564 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 136141055 # Number of instructions simulated sim_seconds 0.200317 # Number of seconds simulated @@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs 193951 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 200316584000 # number of cpu cycles simulated +system.cpu.numCycles 400633168 # number of cpu cycles simulated system.cpu.num_insts 136141055 # Number of instructions executed system.cpu.num_refs 58160249 # Number of memory references system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr index 08cfb2451..2e627b821 100644 --- a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr @@ -1,7 +1,3 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x1838c0 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: ignoring syscall time(4026527856, 4026528256, ...) diff --git a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt index 57430d61b..752f725e4 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 19407214 # Nu global.BPredUnit.condPredicted 254124044 # Number of conditional branches predicted global.BPredUnit.lookups 329654644 # Number of BP lookups global.BPredUnit.usedRAS 23321143 # Number of times the RAS was used to get a target. -host_inst_rate 153530 # Simulator instruction rate (inst/s) -host_mem_usage 182552 # Number of bytes of host memory used -host_seconds 11307.49 # Real time elapsed on the host -host_tick_rate 57851122 # Simulator tick rate (ticks/s) +host_inst_rate 162413 # Simulator instruction rate (inst/s) +host_mem_usage 200732 # Number of bytes of host memory used +host_seconds 10689.07 # Real time elapsed on the host +host_tick_rate 61198134 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 71970991 # Number of conflicting loads. memdepunit.memDep.conflictingStores 36581423 # Number of conflicting stores. memdepunit.memDep.insertedLoads 594992654 # Number of loads inserted to the mem dependence unit. @@ -244,10 +244,10 @@ system.cpu.icache.tagsinuse 710.981871 # Cy system.cpu.icache.total_refs 338458990 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 287621 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 197 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 270496646 # Number of branches executed system.cpu.iew.EXEC:nop 123104849 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.690527 # Inst execution rate +system.cpu.iew.EXEC:rate 1.690526 # Inst execution rate system.cpu.iew.EXEC:refs 759555990 # number of memory reference insts executed system.cpu.iew.EXEC:stores 199980185 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -436,7 +436,7 @@ system.cpu.l2cache.tagsinuse 18802.772660 # Cy system.cpu.l2cache.total_refs 5868601 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 505903232000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 1308302031 # number of cpu cycles simulated +system.cpu.numCycles 1308302228 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 9337867 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 3445352 # Number of times rename has blocked due to IQ full diff --git a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt index a6eb50453..afbd9c385 100644 --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1514723 # Simulator instruction rate (inst/s) -host_mem_usage 181532 # Number of bytes of host memory used -host_seconds 1201.39 # Real time elapsed on the host -host_tick_rate 2161875158 # Simulator tick rate (ticks/s) +host_inst_rate 1279505 # Simulator instruction rate (inst/s) +host_mem_usage 199716 # Number of bytes of host memory used +host_seconds 1422.25 # Real time elapsed on the host +host_tick_rate 1826162604 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.597265 # Number of seconds simulated @@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs 5824390 # To system.cpu.l2cache.warmup_cycle 2034930554000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2597265186000 # number of cpu cycles simulated +system.cpu.numCycles 5194530372 # number of cpu cycles simulated system.cpu.num_insts 1819780127 # Number of instructions executed system.cpu.num_refs 613169725 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini new file mode 100644 index 000000000..322bfab4b --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -0,0 +1,80 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=bzip2 input.source 1 +cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..03017061d --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1084871 # Simulator instruction rate (inst/s) +host_mem_usage 175684 # Number of bytes of host memory used +host_seconds 4236.15 # Real time elapsed on the host +host_tick_rate 662497504 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 4595672201 # Number of instructions simulated +sim_seconds 2.806437 # Number of seconds simulated +sim_ticks 2806436542000 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 5612873085 # number of cpu cycles simulated +system.cpu.num_insts 4595672201 # Number of instructions executed +system.cpu.num_refs 1686312529 # Number of memory references +system.cpu.workload.PROG:num_syscalls 33 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr new file mode 100644 index 000000000..46a429e22 --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr @@ -0,0 +1,8 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: instruction 'rdtsc' unimplemented +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout new file mode 100644 index 000000000..1a0378ca6 --- /dev/null +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout @@ -0,0 +1,27 @@ +spec_init +Loading Input Data +Input data 1048576 bytes in length +Compressing Input Data, level 7 +Compressed data 198546 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 198677 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Oct 21 2007 20:57:52 +M5 started Sun Oct 21 22:20:45 2007 +M5 executing on nacho +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic tests/run.py long/60.bzip2/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 2806436542000 because target called exit() diff --git a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt index 0262f8e2d..93bbafeb5 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1944478 # Nu global.BPredUnit.condPredicted 14575632 # Number of conditional branches predicted global.BPredUnit.lookups 19422613 # Number of BP lookups global.BPredUnit.usedRAS 1713685 # Number of times the RAS was used to get a target. -host_inst_rate 134486 # Simulator instruction rate (inst/s) -host_mem_usage 187512 # Number of bytes of host memory used -host_seconds 625.94 # Real time elapsed on the host -host_tick_rate 64866574 # Simulator tick rate (ticks/s) +host_inst_rate 135551 # Simulator instruction rate (inst/s) +host_mem_usage 205692 # Number of bytes of host memory used +host_seconds 621.02 # Real time elapsed on the host +host_tick_rate 65380263 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 17216912 # Number of conflicting loads. memdepunit.memDep.conflictingStores 5017487 # Number of conflicting stores. memdepunit.memDep.insertedLoads 33831723 # Number of loads inserted to the mem dependence unit. @@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 389 # Th system.cpu.commit.commitSquashedInsts 55442802 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.964650 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.964650 # CPI: Total CPI of All Threads +system.cpu.cpi 0.964659 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.964659 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits system.cpu.dcache.ReadReq_accesses 23305151 # number of ReadReq accesses(hits+misses) @@ -154,10 +154,10 @@ system.cpu.fetch.Cycles 50102609 # Nu system.cpu.fetch.IcacheSquashes 509210 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 167066208 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 2080138 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.239183 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.239181 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 19195045 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 14724343 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.057366 # Number of inst fetches per cycle +system.cpu.fetch.rate 2.057346 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 81203929 system.cpu.fetch.rateDist.min_value 0 @@ -236,10 +236,10 @@ system.cpu.icache.tagsinuse 1547.586704 # Cy system.cpu.icache.total_refs 19184655 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 554685 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 795 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 12760718 # Number of branches executed system.cpu.iew.EXEC:nop 12520368 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.249722 # Inst execution rate +system.cpu.iew.EXEC:rate 1.249709 # Inst execution rate system.cpu.iew.EXEC:refs 31851627 # number of memory reference insts executed system.cpu.iew.EXEC:stores 7184817 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -249,7 +249,7 @@ system.cpu.iew.WB:fanout 0.723301 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 65598879 # num instructions producing a value -system.cpu.iew.WB:rate 1.226153 # insts written-back per cycle +system.cpu.iew.WB:rate 1.226141 # insts written-back per cycle system.cpu.iew.WB:sent 100495413 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 2106580 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 285272 # Number of cycles IEW is blocking @@ -279,8 +279,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 4054272 # system.cpu.iew.memOrderViolationEvents 250644 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 202889 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1903691 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.036646 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.036646 # IPC: Total IPC of All Threads +system.cpu.ipc 1.036636 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.036636 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 103670386 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 7 0.00% # Type of FU issued @@ -331,7 +331,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.276667 # Inst issue rate +system.cpu.iq.ISSUE:rate 1.276655 # Inst issue rate system.cpu.iq.iqInstsAdded 134823640 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 103670386 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ @@ -428,7 +428,7 @@ system.cpu.l2cache.tagsinuse 2248.754865 # Cy system.cpu.l2cache.total_refs 7137 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 81203929 # number of cpu cycles simulated +system.cpu.numCycles 81204724 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 1670922 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed system.cpu.rename.RENAME:IQFullEvents 1021107 # Number of times rename has blocked due to IQ full diff --git a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt index beacdcee0..d2756f127 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1574277 # Simulator instruction rate (inst/s) -host_mem_usage 186464 # Number of bytes of host memory used -host_seconds 58.38 # Real time elapsed on the host -host_tick_rate 2031398471 # Simulator tick rate (ticks/s) +host_inst_rate 1354641 # Simulator instruction rate (inst/s) +host_mem_usage 204632 # Number of bytes of host memory used +host_seconds 67.84 # Real time elapsed on the host +host_tick_rate 1747991543 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118590 # Number of seconds simulated @@ -245,7 +245,7 @@ system.cpu.l2cache.total_refs 5916 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 118589630000 # number of cpu cycles simulated +system.cpu.numCycles 237179260 # number of cpu cycles simulated system.cpu.num_insts 91903056 # Number of instructions executed system.cpu.num_refs 26537141 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr index 18e13818c..2dcd5f795 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr @@ -1,7 +1,3 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x11e394 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt index bb82b8cc2..8855ab575 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1002711 # Simulator instruction rate (inst/s) -host_mem_usage 188412 # Number of bytes of host memory used -host_seconds 192.91 # Real time elapsed on the host -host_tick_rate 1401662479 # Simulator tick rate (ticks/s) +host_inst_rate 958305 # Simulator instruction rate (inst/s) +host_mem_usage 206472 # Number of bytes of host memory used +host_seconds 201.85 # Real time elapsed on the host +host_tick_rate 1339588721 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 193435005 # Number of instructions simulated sim_seconds 0.270398 # Number of seconds simulated @@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs 8679 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 270397899000 # number of cpu cycles simulated +system.cpu.numCycles 540795798 # number of cpu cycles simulated system.cpu.num_insts 193435005 # Number of instructions executed system.cpu.num_refs 76733003 # Number of memory references system.cpu.workload.PROG:num_syscalls 396 # Number of system calls diff --git a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr index 18e13818c..2dcd5f795 100644 --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr @@ -1,7 +1,3 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x11e394 length 0x10. -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... warn: Ignoring request to flush register windows. warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini new file mode 100644 index 000000000..0644df864 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -0,0 +1,80 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=twolf smred +cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic +egid=100 +env= +euid=100 +executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..db17fc7d7 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 1304954 # Simulator instruction rate (inst/s) +host_mem_usage 183200 # Number of bytes of host memory used +host_seconds 167.36 # Real time elapsed on the host +host_tick_rate 776224834 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 218399764 # Number of instructions simulated +sim_seconds 0.129911 # Number of seconds simulated +sim_ticks 129910855000 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 259821711 # number of cpu cycles simulated +system.cpu.num_insts 218399764 # Number of instructions executed +system.cpu.num_refs 77164404 # Number of memory references +system.cpu.workload.PROG:num_syscalls 395 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.out b/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.out new file mode 100644 index 000000000..00387ae5c --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.out @@ -0,0 +1,276 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + + +NOTE: Restart file .rs2 not used + +TimberWolf will perform a global route step +rowSep: 1.000000 +feedThruWidth: 4 + +****************** +BLOCK DATA +block:1 desire:85 +block:2 desire:85 +Total Desired Length: 170 +total cell length: 168 +total block length: 168 +block x-span:84 block y-span:78 +implicit feed thru range: -84 +Using default value of bin.penalty.control:1.000000 +numBins automatically set to:5 +binWidth = average_cell_width + 0 sigma= 17 +average_cell_width is:16 +standard deviation of cell length is:23.6305 +TimberWolfSC starting from the beginning + + + +THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 +The number of nets with 1 pin is 4 +The number of nets with 2 pin is 9 +The number of nets with 3 pin is 0 +The number of nets with 4 pin is 2 +The number of nets with 5 pin is 0 +The number of nets with 6 pin is 0 +The number of nets with 7 pin is 0 +The number of nets with 8 pin is 0 +The number of nets with 9 pin is 0 +The number of nets with 10 pin or more is 0 + +New Cost Function: Initial Horizontal Cost:242 +New Cost Function: FEEDS:0 MISSING_ROWS:-46 + +bdxlen:86 bdylen:78 +l:0 t:78 r:86 b:0 + + + +THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 + + + +THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 + +The rand generator seed was at utemp() : 1 + + + tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 + tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 + tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 + tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 + + I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs + 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 + 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 + 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 + 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 + 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 + 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 + 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 + 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 + 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 + 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 + 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 + 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 + 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 + 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 + 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 + 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 + 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 + 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 + 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 + 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 + 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 + 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 + 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 + 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 + 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 + 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 + 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 + 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 + 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 + 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 + 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 + 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 + 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 + 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 + 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 + 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 + 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 + 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 + 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 + 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 + 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 + 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 + 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 + 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 + 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 + 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 + 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 + 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 + 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 + 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 + 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 + 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 + 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 + 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 + 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 + 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 + 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 + 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 + 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 + 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 + 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 + 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 + 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 + 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 + 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 + 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 + 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 + 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 + 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 + 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 + 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 + 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 + 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 + 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 + 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 + 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 + 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 + 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 + 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 + 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 + 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 + 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 + 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 + 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 + 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 + 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 + 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 + 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 + 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 + 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 + 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 + 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 + 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 + 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 + 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 + 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 + 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 + 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 + 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 +100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 +101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 +102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 +103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 +104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 +105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 +106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 +107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 +108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 +109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 +110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 +111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 +112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 +113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 +114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 +115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 +116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 +117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 +118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 +119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 +120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 +121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 + +Initial Wiring Cost: 645 Final Wiring Cost: 732 +############## Percent Wire Cost Reduction: -13 + + +Initial Wire Length: 645 Final Wire Length: 732 +************** Percent Wire Length Reduction: -13 + + +Initial Horiz. Wire: 216 Final Horiz. Wire: 147 +$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 + + +Initial Vert. Wire: 429 Final Vert. Wire: 585 +@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 + +Before Feeds are Added: +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 82 -20 + 2 86 -16 + +LONGEST Block is:2 Its length is:86 +BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET + 1 86 -16 + 2 86 -16 + +LONGEST Block is:1 Its length is:86 +Added: 1 feed-through cells + +Removed the cell overlaps --- Will do neighbor interchanges only now + +TOTAL INTERCONNECT LENGTH: 994 +OVERLAP PENALTY: 0 + +initialRowControl: 1.650 +finalRowControl: 0.300 +iter T Wire accept + 122 0.001 976 16% + 123 0.001 971 0% + 124 0.001 971 0% +Total Feed-Alignment Movement (Pass 1): 0 +Total Feed-Alignment Movement (Pass 2): 0 +Total Feed-Alignment Movement (Pass 3): 0 +Total Feed-Alignment Movement (Pass 4): 0 +Total Feed-Alignment Movement (Pass 5): 0 +Total Feed-Alignment Movement (Pass 6): 0 +Total Feed-Alignment Movement (Pass 7): 0 +Total Feed-Alignment Movement (Pass 8): 0 + +The rand generator seed was at globroute() : 987654321 + + +Total Number of Net Segments: 9 +Number of Switchable Net Segments: 0 + +Number of channels: 3 + + + +THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 + + +no. of accepted flips: 0 +no. of attempted flips: 0 +THIS IS THE NUMBER OF TRACKS: 5 + + + +FINAL NUMBER OF ROUTING TRACKS: 5 + +MAX OF CHANNEL: 1 is: 0 +MAX OF CHANNEL: 2 is: 4 +MAX OF CHANNEL: 3 is: 1 +FINAL TOTAL INTERCONNECT LENGTH: 978 +FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 +MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 + + +cost_scale_factor:3.90616 + +Number of Feed Thrus: 0 +Number of Implicit Feed Thrus: 0 + +Statistics: +Number of Standard Cells: 10 +Number of Pads: 0 +Number of Nets: 15 +Number of Pins: 46 +Usage statistics not available diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pin b/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pin new file mode 100644 index 000000000..62b922e4e --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pin @@ -0,0 +1,17 @@ +$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 +$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 +B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 +B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 +B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 +B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 +B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 +$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 +$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 +$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 +$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 b/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 new file mode 100644 index 000000000..bdc569e39 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 @@ -0,0 +1,11 @@ +$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 +$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 +$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 +ACOUNT_1 14 0 18 26 2 1 +twfeed1 18 0 22 26 0 1 +$COUNT_1/$FJK3_1 22 0 86 26 0 1 +$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 +$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 +$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 +$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 +$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 b/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 new file mode 100644 index 000000000..6e2601e82 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 @@ -0,0 +1,2 @@ +1 0 0 86 26 0 0 +2 0 52 86 78 0 0 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sav b/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sav new file mode 100644 index 000000000..04c8e9935 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sav @@ -0,0 +1,18 @@ +0.009592 +121 +0 +1 +0.000000 +0.500000 +3.906156 +1 +1 1 2 37 13 +2 2 0 34 65 +3 2 2 63 65 +4 1 0 59 13 +5 1 2 32 13 +6 2 0 23 65 +7 1 2 12 13 +8 2 0 6 65 +9 1 0 70 13 +10 2 0 70 65 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 b/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 new file mode 100644 index 000000000..9dd68ecdb --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 @@ -0,0 +1,19 @@ +0.001000 +123 +0 +2 +0.000000 +0.500000 +3.906156 +1 +1 1 2 16 13 +2 2 2 19 65 +3 2 2 14 65 +4 1 0 11 13 +5 1 2 6 13 +6 2 0 3 65 +7 1 0 2 13 +8 2 2 9 65 +9 1 0 50 13 +10 2 0 54 65 +11 1 0 84 13 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.twf b/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.twf new file mode 100644 index 000000000..a4c2eac35 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.twf @@ -0,0 +1,29 @@ +net 1 +segment channel 2 + pin1 1 pin2 7 0 0 +net 2 +segment channel 3 +pin1 41 pin2 42 0 0 +segment channel 2 +pin1 12 pin2 3 0 0 +net 3 +segment channel 2 +pin1 35 pin2 36 0 0 +segment channel 2 +pin1 19 pin2 35 0 0 +net 4 +segment channel 2 + pin1 5 pin2 38 0 0 +net 5 +net 7 +segment channel 2 + pin1 14 pin2 43 0 0 +net 8 +segment channel 2 + pin1 23 pin2 17 0 0 +net 9 +net 11 +segment channel 2 + pin1 25 pin2 31 0 0 +net 14 +net 15 diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr new file mode 100644 index 000000000..6947c985e --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr @@ -0,0 +1,7 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: instruction 'rdtsc' unimplemented +warn: Increasing stack size by one page. +warn: Increasing stack size by one page. diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout new file mode 100644 index 000000000..4f9067256 --- /dev/null +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout @@ -0,0 +1,26 @@ + +TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 +Standard Cell Placement and Global Routing Program +Authors: Carl Sechen, Bill Swartz + Yale University + 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 + 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 + 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 + 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 + 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 +106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 +122 123 124 M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Oct 21 2007 20:57:52 +M5 started Sun Oct 21 23:31:23 2007 +M5 executing on nacho +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic tests/run.py long/70.twolf/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 129910855000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index ce1ae8d6f..00f26425a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 409 # Nu global.BPredUnit.condPredicted 1184 # Number of conditional branches predicted global.BPredUnit.lookups 2029 # Number of BP lookups global.BPredUnit.usedRAS 277 # Number of times the RAS was used to get a target. -host_inst_rate 9351 # Simulator instruction rate (inst/s) -host_mem_usage 180452 # Number of bytes of host memory used -host_seconds 0.60 # Real time elapsed on the host -host_tick_rate 7988790 # Simulator tick rate (ticks/s) +host_inst_rate 84357 # Simulator instruction rate (inst/s) +host_mem_usage 197344 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 71887995 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 23 # Number of conflicting loads. memdepunit.memDep.conflictingStores 124 # Number of conflicting stores. memdepunit.memDep.insertedLoads 2030 # Number of loads inserted to the mem dependence unit. @@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 17 # Th system.cpu.commit.commitSquashedInsts 4234 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.680420 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.680420 # CPI: Total CPI of All Threads +system.cpu.cpi 1.709586 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.709586 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1535 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 10443.877551 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6357.142857 # average ReadReq mshr miss latency @@ -152,10 +152,10 @@ system.cpu.fetch.Cycles 3746 # Nu system.cpu.fetch.IcacheSquashes 226 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 12519 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 469 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.214732 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.211068 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1542 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.324902 # Number of inst fetches per cycle +system.cpu.fetch.rate 1.302299 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 9449 system.cpu.fetch.rateDist.min_value 0 @@ -234,10 +234,10 @@ system.cpu.icache.tagsinuse 164.253671 # Cy system.cpu.icache.total_refs 1211 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 110443 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 164 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 1199 # Number of branches executed system.cpu.iew.EXEC:nop 72 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.848450 # Inst execution rate +system.cpu.iew.EXEC:rate 0.833975 # Inst execution rate system.cpu.iew.EXEC:refs 2660 # number of memory reference insts executed system.cpu.iew.EXEC:stores 1006 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -247,7 +247,7 @@ system.cpu.iew.WB:fanout 0.742905 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 4031 # num instructions producing a value -system.cpu.iew.WB:rate 0.811091 # insts written-back per cycle +system.cpu.iew.WB:rate 0.797254 # insts written-back per cycle system.cpu.iew.WB:sent 7781 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 401 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking @@ -277,8 +277,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 424 # system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.595089 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.595089 # IPC: Total IPC of All Threads +system.cpu.ipc 0.584937 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.584937 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 8383 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued @@ -329,7 +329,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.887184 # Inst issue rate +system.cpu.iq.ISSUE:rate 0.872048 # Inst issue rate system.cpu.iq.iqInstsAdded 9901 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 8383 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ @@ -421,7 +421,7 @@ system.cpu.l2cache.tagsinuse 218.025629 # Cy system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 9449 # number of cpu cycles simulated +system.cpu.numCycles 9613 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 50 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed system.cpu.rename.RENAME:IdleCycles 6291 # Number of cycles rename is idle diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index 0908a82c9..51a854d5e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 243703 # Simulator instruction rate (inst/s) -host_mem_usage 179944 # Number of bytes of host memory used +host_inst_rate 341217 # Simulator instruction rate (inst/s) +host_mem_usage 196644 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 781539770 # Simulator tick rate (ticks/s) +host_tick_rate 1094407052 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5641 # Number of instructions simulated sim_seconds 0.000018 # Number of seconds simulated @@ -240,7 +240,7 @@ system.cpu.l2cache.total_refs 1 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 18374000 # number of cpu cycles simulated +system.cpu.numCycles 36748 # number of cpu cycles simulated system.cpu.num_insts 5641 # Number of instructions executed system.cpu.num_refs 1801 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index ffd2f7ab7..5d4ecfb70 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 213 # Nu global.BPredUnit.condPredicted 401 # Number of conditional branches predicted global.BPredUnit.lookups 824 # Number of BP lookups global.BPredUnit.usedRAS 163 # Number of times the RAS was used to get a target. -host_inst_rate 31893 # Simulator instruction rate (inst/s) -host_mem_usage 179460 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 32096529 # Simulator tick rate (ticks/s) +host_inst_rate 66708 # Simulator instruction rate (inst/s) +host_mem_usage 196356 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host +host_tick_rate 66966767 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 698 # Number of loads inserted to the mem dependence unit. @@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 4 # Th system.cpu.commit.commitSquashedInsts 1380 # The number of squashed insts skipped by commit system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 1.984080 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.984080 # CPI: Total CPI of All Threads +system.cpu.cpi 2.019690 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.019690 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 528 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 8639.344262 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5655.737705 # average ReadReq mshr miss latency @@ -152,10 +152,10 @@ system.cpu.fetch.Cycles 1626 # Nu system.cpu.fetch.IcacheSquashes 101 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 5268 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 242 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.173986 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.170919 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 707 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 319 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.112331 # Number of inst fetches per cycle +system.cpu.fetch.rate 1.092719 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 4736 system.cpu.fetch.rateDist.min_value 0 @@ -234,10 +234,10 @@ system.cpu.icache.tagsinuse 92.900452 # Cy system.cpu.icache.total_refs 510 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 56472 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 85 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 538 # Number of branches executed system.cpu.iew.EXEC:nop 274 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.670608 # Inst execution rate +system.cpu.iew.EXEC:rate 0.658784 # Inst execution rate system.cpu.iew.EXEC:refs 934 # number of memory reference insts executed system.cpu.iew.EXEC:stores 356 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -247,7 +247,7 @@ system.cpu.iew.WB:fanout 0.794497 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 1415 # num instructions producing a value -system.cpu.iew.WB:rate 0.651182 # insts written-back per cycle +system.cpu.iew.WB:rate 0.639701 # insts written-back per cycle system.cpu.iew.WB:sent 3123 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 149 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking @@ -277,8 +277,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 118 # system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.504012 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.504012 # IPC: Total IPC of All Threads +system.cpu.ipc 0.495125 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.495125 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 3281 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued @@ -329,7 +329,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.692779 # Inst issue rate +system.cpu.iq.ISSUE:rate 0.680564 # Inst issue rate system.cpu.iq.iqInstsAdded 3776 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 3281 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ @@ -420,7 +420,7 @@ system.cpu.l2cache.tagsinuse 115.687599 # Cy system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 4736 # number of cpu cycles simulated +system.cpu.numCycles 4821 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed system.cpu.rename.RENAME:IdleCycles 3552 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index 89de75b41..d906bb79e 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,9 +6,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 14 2007 17:36:58 -M5 started Tue Aug 14 17:40:04 2007 -M5 executing on nacho +M5 compiled Sep 27 2007 13:46:37 +M5 started Thu Sep 27 20:06:36 2007 +M5 executing on zeep command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second Exiting @ tick 1297500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 942cc1b79..60bfb7de8 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 123219 # Simulator instruction rate (inst/s) -host_mem_usage 178996 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 443932267 # Simulator tick rate (ticks/s) +host_inst_rate 178240 # Simulator instruction rate (inst/s) +host_mem_usage 195696 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 641473527 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000009 # Number of seconds simulated @@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs 0 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 9438000 # number of cpu cycles simulated +system.cpu.numCycles 18876 # number of cpu cycles simulated system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index cb408c2ca..c7e605dd3 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 186969 # Simulator instruction rate (inst/s) -host_mem_usage 180780 # Number of bytes of host memory used +host_inst_rate 192479 # Simulator instruction rate (inst/s) +host_mem_usage 197496 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 602814418 # Simulator tick rate (ticks/s) +host_tick_rate 618816195 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5656 # Number of instructions simulated sim_seconds 0.000018 # Number of seconds simulated @@ -224,7 +224,7 @@ system.cpu.l2cache.total_refs 2 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 18463000 # number of cpu cycles simulated +system.cpu.numCycles 36926 # number of cpu cycles simulated system.cpu.num_insts 5656 # Number of instructions executed system.cpu.num_refs 2055 # Number of memory references system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr index 7873672f2..87866a2a5 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr @@ -1,3 +1 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index ff4bd3dbe..b81236150 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 198489 # Simulator instruction rate (inst/s) -host_mem_usage 181156 # Number of bytes of host memory used +host_inst_rate 290934 # Simulator instruction rate (inst/s) +host_mem_usage 197920 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 645076356 # Simulator tick rate (ticks/s) +host_tick_rate 939694341 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 4833 # Number of instructions simulated sim_seconds 0.000016 # Number of seconds simulated @@ -224,7 +224,7 @@ system.cpu.l2cache.total_refs 3 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 15925000 # number of cpu cycles simulated +system.cpu.numCycles 31850 # number of cpu cycles simulated system.cpu.num_insts 4833 # Number of instructions executed system.cpu.num_refs 1282 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr index 7873672f2..87866a2a5 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr @@ -1,3 +1 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini new file mode 100644 index 000000000..74f6c930e --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -0,0 +1,80 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=AtomicSimpleCPU +children=dtb itb tracer workload +clock=500 +cpu_id=0 +defer_registration=false +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +phase=0 +progress_interval=0 +simulate_stalls=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.port[2] +icache_port=system.membus.port[1] + +[system.cpu.dtb] +type=X86DTB +size=64 + +[system.cpu.itb] +type=X86ITB +size=64 + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +egid=100 +env= +euid=100 +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +responder_set=false +width=64 +port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +zero=false +port=system.membus.port[0] + diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt new file mode 100644 index 000000000..f834f694b --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt @@ -0,0 +1,18 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 21996 # Simulator instruction rate (inst/s) +host_mem_usage 172228 # Number of bytes of host memory used +host_seconds 0.39 # Real time elapsed on the host +host_tick_rate 12789916 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 8472 # Number of instructions simulated +sim_seconds 0.000005 # Number of seconds simulated +sim_ticks 4930500 # Number of ticks simulated +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.numCycles 9862 # number of cpu cycles simulated +system.cpu.num_insts 8472 # Number of instructions executed +system.cpu.num_refs 1765 # Number of memory references +system.cpu.workload.PROG:num_syscalls 11 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr new file mode 100644 index 000000000..863f1adb9 --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr @@ -0,0 +1,5 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 +warn: Entering event queue @ 0. Starting simulation... +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +warn: instruction 'rdtsc' unimplemented diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout new file mode 100644 index 000000000..302f58c0c --- /dev/null +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout @@ -0,0 +1,14 @@ +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Oct 25 2007 18:49:38 +M5 started Thu Oct 25 18:49:42 2007 +M5 executing on nacho +command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic tests/run.py quick/00.hello/x86/linux/simple-atomic +Global frequency set at 1000000000000 ticks per second +Exiting @ tick 4930500 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 71b1480ab..3eda0093a 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -368,7 +368,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin output=cout @@ -384,7 +384,7 @@ cwd= egid=100 env= euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin output=cout diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index e76204a83..6cf4d180e 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 1092 # Nu global.BPredUnit.condPredicted 2350 # Number of conditional branches predicted global.BPredUnit.lookups 4075 # Number of BP lookups global.BPredUnit.usedRAS 561 # Number of times the RAS was used to get a target. -host_inst_rate 76336 # Simulator instruction rate (inst/s) -host_mem_usage 181020 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host -host_tick_rate 38800813 # Simulator tick rate (ticks/s) +host_inst_rate 92493 # Simulator instruction rate (inst/s) +host_mem_usage 197924 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 47019704 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 14 # Number of conflicting loads. memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. memdepunit.memDep.conflictingStores 35 # Number of conflicting stores. @@ -68,9 +68,9 @@ system.cpu.commit.commitSquashedInsts 8053 # Th system.cpu.committedInsts_0 5623 # Number of Instructions Simulated system.cpu.committedInsts_1 5624 # Number of Instructions Simulated system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 2.035568 # CPI: Cycles Per Instruction -system.cpu.cpi_1 2.035206 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.017694 # CPI: Total CPI of All Threads +system.cpu.cpi_0 2.037169 # CPI: Cycles Per Instruction +system.cpu.cpi_1 2.036807 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.018494 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 2934 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses_0 2934 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency_0 12119.897959 # average ReadReq miss latency @@ -244,10 +244,10 @@ system.cpu.fetch.Cycles 7174 # Nu system.cpu.fetch.IcacheSquashes 439 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 24770 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 1207 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.356020 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.355740 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 3019 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 1267 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.164075 # Number of inst fetches per cycle +system.cpu.fetch.rate 2.162375 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 11446 system.cpu.fetch.rateDist.min_value 0 @@ -391,14 +391,14 @@ system.cpu.icache.warmup_cycle 0 # Cy system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles 6496 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 9 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 2386 # Number of branches executed system.cpu.iew.EXEC:branches_0 1188 # Number of branches executed system.cpu.iew.EXEC:branches_1 1198 # Number of branches executed system.cpu.iew.EXEC:nop 127 # number of nop insts executed system.cpu.iew.EXEC:nop_0 66 # number of nop insts executed system.cpu.iew.EXEC:nop_1 61 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.378123 # Inst execution rate +system.cpu.iew.EXEC:rate 1.377041 # Inst execution rate system.cpu.iew.EXEC:refs 5110 # number of memory reference insts executed system.cpu.iew.EXEC:refs_0 2531 # number of memory reference insts executed system.cpu.iew.EXEC:refs_1 2579 # number of memory reference insts executed @@ -426,9 +426,9 @@ system.cpu.iew.WB:penalized_rate_1 0 # fr system.cpu.iew.WB:producers 7913 # num instructions producing a value system.cpu.iew.WB:producers_0 3958 # num instructions producing a value system.cpu.iew.WB:producers_1 3955 # num instructions producing a value -system.cpu.iew.WB:rate 1.323170 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.662590 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.660580 # insts written-back per cycle +system.cpu.iew.WB:rate 1.322130 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.662069 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.660061 # insts written-back per cycle system.cpu.iew.WB:sent 15343 # cumulative count of insts sent to commit system.cpu.iew.WB:sent_0 7675 # cumulative count of insts sent to commit system.cpu.iew.WB:sent_1 7668 # cumulative count of insts sent to commit @@ -472,9 +472,9 @@ system.cpu.iew.lsq.thread.1.squashedStores 328 # system.cpu.iew.memOrderViolationEvents 125 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 788 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 203 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.491263 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.491351 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.982614 # IPC: Total IPC of All Threads +system.cpu.ipc_0 0.490877 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.490965 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.981842 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 8365 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued @@ -563,7 +563,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.458763 # Inst issue rate +system.cpu.iq.ISSUE:rate 1.457617 # Inst issue rate system.cpu.iq.iqInstsAdded 19328 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 16697 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ @@ -729,7 +729,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 11446 # number of cpu cycles simulated +system.cpu.numCycles 11455 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 641 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed system.cpu.rename.RENAME:IdleCycles 15417 # Number of cycles rename is idle diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt index eae7625e9..3c63b3005 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 2012 # Nu global.BPredUnit.condPredicted 7659 # Number of conditional branches predicted global.BPredUnit.lookups 7659 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 7502 # Simulator instruction rate (inst/s) -host_mem_usage 186228 # Number of bytes of host memory used -host_seconds 1.39 # Real time elapsed on the host -host_tick_rate 10800438 # Simulator tick rate (ticks/s) +host_inst_rate 64485 # Simulator instruction rate (inst/s) +host_mem_usage 198296 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 92733729 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. memdepunit.memDep.insertedLoads 3077 # Number of loads inserted to the mem dependence unit. @@ -49,8 +49,8 @@ system.cpu.commit.commitNonSpecStalls 329 # Th system.cpu.commit.commitSquashedInsts 13198 # The number of squashed insts skipped by commit system.cpu.committedInsts 10411 # Number of Instructions Simulated system.cpu.committedInsts_total 10411 # Number of Instructions Simulated -system.cpu.cpi 2.871770 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.871770 # CPI: Total CPI of All Threads +system.cpu.cpi 2.879839 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.879839 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 2274 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 9734.848485 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5560.606061 # average ReadReq mshr miss latency @@ -139,10 +139,10 @@ system.cpu.fetch.Cycles 16219 # Nu system.cpu.fetch.IcacheSquashes 589 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 42202 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 2099 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.256171 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.255453 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 4927 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 2711 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.411533 # Number of inst fetches per cycle +system.cpu.fetch.rate 1.407578 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist.samples 29898 system.cpu.fetch.rateDist.min_value 0 @@ -221,10 +221,10 @@ system.cpu.icache.tagsinuse 233.477311 # Cy system.cpu.icache.total_refs 4537 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 51980 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 84 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.EXEC:branches 3086 # Number of branches executed system.cpu.iew.EXEC:nop 1794 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.576995 # Inst execution rate +system.cpu.iew.EXEC:rate 0.575379 # Inst execution rate system.cpu.iew.EXEC:refs 4543 # number of memory reference insts executed system.cpu.iew.EXEC:stores 2116 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed @@ -234,7 +234,7 @@ system.cpu.iew.WB:fanout 0.827620 # av system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:producers 7605 # num instructions producing a value -system.cpu.iew.WB:rate 0.555823 # insts written-back per cycle +system.cpu.iew.WB:rate 0.554266 # insts written-back per cycle system.cpu.iew.WB:sent 16830 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 2216 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking @@ -264,8 +264,8 @@ system.cpu.iew.lsq.thread.0.squashedStores 1658 # system.cpu.iew.memOrderViolationEvents 57 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 695 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 1521 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.348217 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.348217 # IPC: Total IPC of All Threads +system.cpu.ipc 0.347242 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.347242 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0 20089 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued @@ -316,7 +316,7 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.671918 # Inst issue rate +system.cpu.iq.ISSUE:rate 0.670035 # Inst issue rate system.cpu.iq.iqInstsAdded 21924 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 20089 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 612 # Number of non-speculative instructions added to the IQ @@ -404,7 +404,7 @@ system.cpu.l2cache.tagsinuse 259.708792 # Cy system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 29898 # number of cpu cycles simulated +system.cpu.numCycles 29982 # number of cpu cycles simulated system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed system.cpu.rename.RENAME:IdleCycles 14192 # Number of cycles rename is idle system.cpu.rename.RENAME:RenameLookups 51924 # Number of register rename lookups that rename has made diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr index 7873672f2..87866a2a5 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr @@ -1,3 +1 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr index 7873672f2..87866a2a5 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr @@ -1,3 +1 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt index 4a899f629..49b40d3b8 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 343655 # Simulator instruction rate (inst/s) -host_mem_usage 180816 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 753768067 # Simulator tick rate (ticks/s) +host_inst_rate 472716 # Simulator instruction rate (inst/s) +host_mem_usage 197656 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1037354119 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 10976 # Number of instructions simulated sim_seconds 0.000024 # Number of seconds simulated @@ -226,7 +226,7 @@ system.cpu.l2cache.total_refs 2 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 24355000 # number of cpu cycles simulated +system.cpu.numCycles 48710 # number of cpu cycles simulated system.cpu.num_insts 10976 # Number of instructions executed system.cpu.num_refs 2770 # Number of memory references system.cpu.workload.PROG:num_syscalls 8 # Number of system calls diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr index 7873672f2..87866a2a5 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr @@ -1,3 +1 @@ -warn: More than two loadable segments in ELF object. -warn: Ignoring segment @ 0x0 length 0x0. warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 1f7fcb065..aaa49012b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -460,7 +460,7 @@ pio=system.toL2Bus.default [system.tsunami] type=Tsunami -children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=system.intrctrl system=system @@ -484,48 +484,8 @@ sim_console=system.sim_console system=system pio=system.iobus.port[25] -[system.tsunami.etherint] -type=NSGigEInt -device=system.tsunami.ethernet -peer=Null - [system.tsunami.ethernet] type=NSGigE -children=configdata -clock=0 -config_latency=20000 -configdata=system.tsunami.ethernet.configdata -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -hardware_address=00:90:00:00:00:01 -intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=1000 -platform=system.tsunami -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -config=system.iobus.port[29] -dma=system.iobus.port[30] -pio=system.iobus.port[27] - -[system.tsunami.ethernet.configdata] -type=PciConfigData BAR0=1 BAR0Size=256 BAR1=0 @@ -558,6 +518,36 @@ SubClassCode=0 SubsystemID=0 SubsystemVendorID=0 VendorID=4107 +clock=0 +config_latency=20000 +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:01 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=system +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=system.iobus.port[29] +dma=system.iobus.port[30] +pio=system.iobus.port[27] [system.tsunami.fake_OROM] type=IsaFake @@ -874,24 +864,6 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController -children=configdata -config_latency=20000 -configdata=system.tsunami.ide.configdata -disks=system.disk0 system.disk2 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=1000 -platform=system.tsunami -system=system -config=system.iobus.port[31] -dma=system.iobus.port[32] -pio=system.iobus.port[26] - -[system.tsunami.ide.configdata] -type=PciConfigData BAR0=1 BAR0Size=8 BAR1=1 @@ -924,6 +896,19 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +config_latency=20000 +disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +system=system +config=system.iobus.port[31] +dma=system.iobus.port[32] +pio=system.iobus.port[26] [system.tsunami.io] type=TsunamiIO diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index eabfb44c3..079bec809 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2322076 # Simulator instruction rate (inst/s) -host_mem_usage 309268 # Number of bytes of host memory used -host_seconds 27.18 # Real time elapsed on the host -host_tick_rate 68811889767 # Simulator tick rate (ticks/s) +host_inst_rate 2182924 # Simulator instruction rate (inst/s) +host_mem_usage 325992 # Number of bytes of host memory used +host_seconds 28.91 # Real time elapsed on the host +host_tick_rate 64688316336 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63114079 # Number of instructions simulated sim_seconds 1.870335 # Number of seconds simulated @@ -239,7 +239,7 @@ system.cpu0.kern.syscall_132 2 0.88% 98.23% # nu system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles -system.cpu0.numCycles 57193784 # number of cpu cycles simulated +system.cpu0.numCycles 3740670091 # number of cpu cycles simulated system.cpu0.num_insts 57182116 # Number of instructions executed system.cpu0.num_refs 15322419 # Number of memory references system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) @@ -456,7 +456,7 @@ system.cpu1.kern.syscall_74 8 8.00% 97.00% # nu system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles -system.cpu1.numCycles 5937367 # number of cpu cycles simulated +system.cpu1.numCycles 3740248039 # number of cpu cycles simulated system.cpu1.num_insts 5931963 # Number of instructions executed system.cpu1.num_refs 1926645 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index c2e3afa96..f47a4495c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -350,7 +350,7 @@ pio=system.toL2Bus.default [system.tsunami] type=Tsunami -children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=system.intrctrl system=system @@ -374,48 +374,8 @@ sim_console=system.sim_console system=system pio=system.iobus.port[25] -[system.tsunami.etherint] -type=NSGigEInt -device=system.tsunami.ethernet -peer=Null - [system.tsunami.ethernet] type=NSGigE -children=configdata -clock=0 -config_latency=20000 -configdata=system.tsunami.ethernet.configdata -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -hardware_address=00:90:00:00:00:01 -intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=1000 -platform=system.tsunami -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -config=system.iobus.port[29] -dma=system.iobus.port[30] -pio=system.iobus.port[27] - -[system.tsunami.ethernet.configdata] -type=PciConfigData BAR0=1 BAR0Size=256 BAR1=0 @@ -448,6 +408,36 @@ SubClassCode=0 SubsystemID=0 SubsystemVendorID=0 VendorID=4107 +clock=0 +config_latency=20000 +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:01 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=system +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=system.iobus.port[29] +dma=system.iobus.port[30] +pio=system.iobus.port[27] [system.tsunami.fake_OROM] type=IsaFake @@ -764,24 +754,6 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController -children=configdata -config_latency=20000 -configdata=system.tsunami.ide.configdata -disks=system.disk0 system.disk2 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=1000 -platform=system.tsunami -system=system -config=system.iobus.port[31] -dma=system.iobus.port[32] -pio=system.iobus.port[26] - -[system.tsunami.ide.configdata] -type=PciConfigData BAR0=1 BAR0Size=8 BAR1=1 @@ -814,6 +786,19 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +config_latency=20000 +disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +system=system +config=system.iobus.port[31] +dma=system.iobus.port[32] +pio=system.iobus.port[26] [system.tsunami.io] type=TsunamiIO diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index 73b22dfec..0780c3207 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2191272 # Simulator instruction rate (inst/s) -host_mem_usage 308228 # Number of bytes of host memory used -host_seconds 27.38 # Real time elapsed on the host -host_tick_rate 66777888282 # Simulator tick rate (ticks/s) +host_inst_rate 2454439 # Simulator instruction rate (inst/s) +host_mem_usage 324968 # Number of bytes of host memory used +host_seconds 24.44 # Real time elapsed on the host +host_tick_rate 74797977378 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59995479 # Number of instructions simulated sim_seconds 1.828355 # Number of seconds simulated @@ -234,7 +234,7 @@ system.cpu.kern.syscall_132 4 1.23% 98.77% # nu system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed system.cpu.not_idle_fraction 0.016412 # Percentage of non-idle cycles -system.cpu.numCycles 60012507 # number of cpu cycles simulated +system.cpu.numCycles 3656710843 # number of cpu cycles simulated system.cpu.num_insts 59995479 # Number of instructions executed system.cpu.num_refs 16302129 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index f2dae72bb..4dde5bc10 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -456,7 +456,7 @@ pio=system.toL2Bus.default [system.tsunami] type=Tsunami -children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=system.intrctrl system=system @@ -480,48 +480,8 @@ sim_console=system.sim_console system=system pio=system.iobus.port[25] -[system.tsunami.etherint] -type=NSGigEInt -device=system.tsunami.ethernet -peer=Null - [system.tsunami.ethernet] type=NSGigE -children=configdata -clock=0 -config_latency=20000 -configdata=system.tsunami.ethernet.configdata -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -hardware_address=00:90:00:00:00:01 -intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=1000 -platform=system.tsunami -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -config=system.iobus.port[29] -dma=system.iobus.port[30] -pio=system.iobus.port[27] - -[system.tsunami.ethernet.configdata] -type=PciConfigData BAR0=1 BAR0Size=256 BAR1=0 @@ -554,6 +514,36 @@ SubClassCode=0 SubsystemID=0 SubsystemVendorID=0 VendorID=4107 +clock=0 +config_latency=20000 +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:01 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=system +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=system.iobus.port[29] +dma=system.iobus.port[30] +pio=system.iobus.port[27] [system.tsunami.fake_OROM] type=IsaFake @@ -870,24 +860,6 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController -children=configdata -config_latency=20000 -configdata=system.tsunami.ide.configdata -disks=system.disk0 system.disk2 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=1000 -platform=system.tsunami -system=system -config=system.iobus.port[31] -dma=system.iobus.port[32] -pio=system.iobus.port[26] - -[system.tsunami.ide.configdata] -type=PciConfigData BAR0=1 BAR0Size=8 BAR1=1 @@ -920,6 +892,19 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +config_latency=20000 +disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +system=system +config=system.iobus.port[31] +dma=system.iobus.port[32] +pio=system.iobus.port[26] [system.tsunami.io] type=TsunamiIO diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 8b29b06d6..e6200df10 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 979093 # Simulator instruction rate (inst/s) -host_mem_usage 278732 # Number of bytes of host memory used -host_seconds 66.19 # Real time elapsed on the host -host_tick_rate 29741162851 # Simulator tick rate (ticks/s) +host_inst_rate 1027363 # Simulator instruction rate (inst/s) +host_mem_usage 295468 # Number of bytes of host memory used +host_seconds 63.08 # Real time elapsed on the host +host_tick_rate 31207407187 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 64810685 # Number of instructions simulated sim_seconds 1.968714 # Number of seconds simulated @@ -273,7 +273,7 @@ system.cpu0.kern.syscall_132 2 0.94% 98.58% # nu system.cpu0.kern.syscall_144 1 0.47% 99.06% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.94% 100.00% # number of syscalls executed system.cpu0.not_idle_fraction 0.057929 # Percentage of non-idle cycles -system.cpu0.numCycles 1967810461000 # number of cpu cycles simulated +system.cpu0.numCycles 3935620922 # number of cpu cycles simulated system.cpu0.num_insts 50990937 # Number of instructions executed system.cpu0.num_refs 13220047 # Number of memory references system.cpu1.dcache.LoadLockedReq_accesses 60083 # number of LoadLockedReq accesses(hits+misses) @@ -528,7 +528,7 @@ system.cpu1.kern.syscall_92 2 1.75% 97.37% # nu system.cpu1.kern.syscall_132 2 1.75% 99.12% # number of syscalls executed system.cpu1.kern.syscall_144 1 0.88% 100.00% # number of syscalls executed system.cpu1.not_idle_fraction 0.013720 # Percentage of non-idle cycles -system.cpu1.numCycles 1968713509000 # number of cpu cycles simulated +system.cpu1.numCycles 3937427018 # number of cpu cycles simulated system.cpu1.num_insts 13819748 # Number of instructions executed system.cpu1.num_refs 4429865 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 24a7dfec3..362a1c26c 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -348,7 +348,7 @@ pio=system.toL2Bus.default [system.tsunami] type=Tsunami -children=cchip console etherint ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=cchip console ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart intrctrl=system.intrctrl system=system @@ -372,48 +372,8 @@ sim_console=system.sim_console system=system pio=system.iobus.port[25] -[system.tsunami.etherint] -type=NSGigEInt -device=system.tsunami.ethernet -peer=Null - [system.tsunami.ethernet] type=NSGigE -children=configdata -clock=0 -config_latency=20000 -configdata=system.tsunami.ethernet.configdata -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -hardware_address=00:90:00:00:00:01 -intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=1000 -platform=system.tsunami -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -config=system.iobus.port[29] -dma=system.iobus.port[30] -pio=system.iobus.port[27] - -[system.tsunami.ethernet.configdata] -type=PciConfigData BAR0=1 BAR0Size=256 BAR1=0 @@ -446,6 +406,36 @@ SubClassCode=0 SubsystemID=0 SubsystemVendorID=0 VendorID=4107 +clock=0 +config_latency=20000 +dma_data_free=false +dma_desc_free=false +dma_no_allocate=true +dma_read_delay=0 +dma_read_factor=0 +dma_write_delay=0 +dma_write_factor=0 +hardware_address=00:90:00:00:00:01 +intr_delay=10000000 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=1 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +rss=false +rx_delay=1000000 +rx_fifo_size=524288 +rx_filter=true +rx_thread=false +system=system +tx_delay=1000000 +tx_fifo_size=524288 +tx_thread=false +config=system.iobus.port[29] +dma=system.iobus.port[30] +pio=system.iobus.port[27] [system.tsunami.fake_OROM] type=IsaFake @@ -762,24 +752,6 @@ pio=system.iobus.port[22] [system.tsunami.ide] type=IdeController -children=configdata -config_latency=20000 -configdata=system.tsunami.ide.configdata -disks=system.disk0 system.disk2 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=1000 -platform=system.tsunami -system=system -config=system.iobus.port[31] -dma=system.iobus.port[32] -pio=system.iobus.port[26] - -[system.tsunami.ide.configdata] -type=PciConfigData BAR0=1 BAR0Size=8 BAR1=1 @@ -812,6 +784,19 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +config_latency=20000 +disks=system.disk0 system.disk2 +max_backoff_delay=10000000 +min_backoff_delay=4000 +pci_bus=0 +pci_dev=0 +pci_func=0 +pio_latency=1000 +platform=system.tsunami +system=system +config=system.iobus.port[31] +dma=system.iobus.port[32] +pio=system.iobus.port[26] [system.tsunami.io] type=TsunamiIO diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 8aeb586fd..1b62f3b23 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 986602 # Simulator instruction rate (inst/s) -host_mem_usage 268252 # Number of bytes of host memory used -host_seconds 60.87 # Real time elapsed on the host -host_tick_rate 31682591808 # Simulator tick rate (ticks/s) +host_inst_rate 1046777 # Simulator instruction rate (inst/s) +host_mem_usage 284980 # Number of bytes of host memory used +host_seconds 57.37 # Real time elapsed on the host +host_tick_rate 33615024315 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60057633 # Number of instructions simulated sim_seconds 1.928634 # Number of seconds simulated @@ -268,7 +268,7 @@ system.cpu.kern.syscall_132 4 1.23% 98.77% # nu system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed system.cpu.not_idle_fraction 0.069379 # Percentage of non-idle cycles -system.cpu.numCycles 1928634086000 # number of cpu cycles simulated +system.cpu.numCycles 3857268172 # number of cpu cycles simulated system.cpu.num_insts 60057633 # Number of instructions executed system.cpu.num_refs 16313038 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index a82f45966..064beb313 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2121237 # Simulator instruction rate (inst/s) -host_mem_usage 171724 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host -host_tick_rate 1058992833 # Simulator tick rate (ticks/s) +host_inst_rate 1676309 # Simulator instruction rate (inst/s) +host_mem_usage 188356 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +host_tick_rate 837474668 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000250 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index 62a259095..396463117 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1285667 # Simulator instruction rate (inst/s) -host_mem_usage 179016 # Number of bytes of host memory used -host_seconds 0.39 # Real time elapsed on the host -host_tick_rate 1812257249 # Simulator tick rate (ticks/s) +host_inst_rate 1220265 # Simulator instruction rate (inst/s) +host_mem_usage 195724 # Number of bytes of host memory used +host_seconds 0.41 # Real time elapsed on the host +host_tick_rate 1720644367 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500001 # Number of instructions simulated sim_seconds 0.000705 # Number of seconds simulated @@ -239,7 +239,7 @@ system.cpu.l2cache.total_refs 0 # To system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 705490000 # number of cpu cycles simulated +system.cpu.numCycles 1410980 # number of cpu cycles simulated system.cpu.num_insts 500001 # Number of instructions executed system.cpu.num_refs 182222 # Number of memory references system.cpu.workload.PROG:num_syscalls 18 # Number of system calls diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index e39fb749f..151c1ae57 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/home/blackga/m5/repos/m5/configs/boot/netperf-server.rcS +readfile=/z/saidi/work/m5.dev/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -694,7 +694,7 @@ kernel=/dist/m5/system/binaries/vmlinux mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=testsys.physmem -readfile=/home/blackga/m5/repos/m5/configs/boot/netperf-stream-client.rcS +readfile=/z/saidi/work/m5.dev/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt index e80f9a2ec..9f3e96104 100644 --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt @@ -76,7 +76,7 @@ drivesys.cpu.kern.syscall_106 1 4.55% 86.36% # nu drivesys.cpu.kern.syscall_118 2 9.09% 95.45% # number of syscalls executed drivesys.cpu.kern.syscall_150 1 4.55% 100.00% # number of syscalls executed drivesys.cpu.not_idle_fraction 0.000000 # Percentage of non-idle cycles -drivesys.cpu.numCycles 1958954 # number of cpu cycles simulated +drivesys.cpu.numCycles 199572412849 # number of cpu cycles simulated drivesys.cpu.num_insts 1958129 # Number of instructions executed drivesys.cpu.num_refs 626223 # Number of memory references drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -139,10 +139,10 @@ drivesys.tsunami.ethernet.txPPS 25 # Pa drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 118863353 # Simulator instruction rate (inst/s) -host_mem_usage 459784 # Number of bytes of host memory used -host_seconds 2.30 # Real time elapsed on the host -host_tick_rate 86976188826 # Simulator tick rate (ticks/s) +host_inst_rate 129173906 # Simulator instruction rate (inst/s) +host_mem_usage 476620 # Number of bytes of host memory used +host_seconds 2.12 # Real time elapsed on the host +host_tick_rate 94522664540 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273294782 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated @@ -233,7 +233,7 @@ testsys.cpu.kern.syscall_104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall_105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall_118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.not_idle_fraction 0.000001 # Percentage of non-idle cycles -testsys.cpu.numCycles 3566060 # number of cpu cycles simulated +testsys.cpu.numCycles 199570420361 # number of cpu cycles simulated testsys.cpu.num_insts 3560518 # Number of instructions executed testsys.cpu.num_refs 1173605 # Number of memory references testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -381,10 +381,10 @@ drivesys.tsunami.ethernet.totalSwi 0 # to drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 116742751815 # Simulator instruction rate (inst/s) -host_mem_usage 459784 # Number of bytes of host memory used +host_inst_rate 134363216323 # Simulator instruction rate (inst/s) +host_mem_usage 476620 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 317182405 # Simulator tick rate (ticks/s) +host_tick_rate 362870729 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273294782 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff --git a/util/make_release.py b/util/make_release.py index 636391a96..b6c5f08fa 100755 --- a/util/make_release.py +++ b/util/make_release.py @@ -72,7 +72,7 @@ def movedir(srcdir, destdir, dir): os.makedirs(dirname(dest)) shutil.move(src, dest) -if not isdir('BitKeeper'): +if not isdir('.hg'): sys.exit('Not in the top level of an m5 tree!') usage = '%s <destdir> <release name>' % sys.argv[0] @@ -83,9 +83,9 @@ if len(sys.argv) != 3: destdir = sys.argv[1] releasename = sys.argv[2] release_dest = joinpath(destdir, 'release') -encumbered_dest = joinpath(destdir, 'encumbered') +#encumbered_dest = joinpath(destdir, 'encumbered') release_dir = joinpath(release_dest, releasename) -encumbered_dir = joinpath(encumbered_dest, releasename) +#encumbered_dir = joinpath(encumbered_dest, releasename) if exists(destdir): if not isdir(destdir): @@ -99,42 +99,49 @@ if exists(release_dest): '%s exists, but is not a directory' % release_dest rmtree(release_dest) -if exists(encumbered_dest): - if not isdir(encumbered_dest): - raise AttributeError, \ - '%s exists, but is not a directory' % encumbered_dest - rmtree(encumbered_dest) +#if exists(encumbered_dest): +# if not isdir(encumbered_dest): +# raise AttributeError, \ +# '%s exists, but is not a directory' % encumbered_dest +# rmtree(encumbered_dest) mkdir(release_dest) -mkdir(encumbered_dest) +#mkdir(encumbered_dest) mkdir(release_dir) -mkdir(encumbered_dir) - -system('bk export -tplain -w -r+ %s' % release_dir) - +#mkdir(encumbered_dir) +system('hg update') +system('rsync -av --exclude ".hg*" --exclude build . %s' % release_dir) # move the time forward on some files by a couple of minutes so we can # avoid building things unnecessarily when = int(time.time()) + 120 # make sure scons doesn't try to run flex unnecessarily -touch(release_dir, 'src/encumbered/eio/exolex.cc', when=(when, when)) +#touch(release_dir, 'src/encumbered/eio/exolex.cc', when=(when, when)) # get rid of non-shipping code -rmtree(release_dir, 'src/encumbered/dev') +#rmtree(release_dir, 'src/encumbered/dev') rmtree(release_dir, 'src/cpu/ozone') -rmtree(release_dir, 'src/mem/cache/tags/split*.cc') -rmtree(release_dir, 'src/mem/cache/tags/split*.hh') -rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.cc') -rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.hh') -rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.cc') -rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.hh') +rmtree(release_dir, 'src/arch/x86') +#rmtree(release_dir, 'src/mem/cache/tags/split*.cc') +#rmtree(release_dir, 'src/mem/cache/tags/split*.hh') +#rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.cc') +#rmtree(release_dir, 'src/mem/cache/prefetch/ghb_*.hh') +#rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.cc') +#rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.hh') rmtree(release_dir, 'configs/fullsys') rmtree(release_dir, 'configs/test') rmtree(release_dir, 'configs/splash2') rmtree(release_dir, 'tests/long/*/ref') rmtree(release_dir, 'tests/old') -rmtree(release_dir, 'src/dev/i8*') +rmtree(release_dir, 'tests/quick/00.hello/ref/x86') +rmtree(release_dir, 'tests/test-progs/hello/bin/x86') +rmtree(release_dir, 'src/dev/x86') + +remove(release_dir, 'src/cpu/nativetrace.hh') +remove(release_dir, 'src/cpu/nativetrace.cc') +remove(release_dir, 'build_opts/X86_SE') +remove(release_dir, 'build_opts/X86_FS') # get rid of some of private scripts remove(release_dir, 'util/chgcopyright') @@ -153,19 +160,66 @@ def remove_sources(regex, subdir): outscript.write(line) outscript.close() -# fix up the SConscript to deal with files we've removed -remove_sources(r'.*split.*\.cc', 'src/mem/cache/tags') -remove_sources(r'.*(ghb|stride)_prefetcher\.cc', 'src/mem/cache/prefetch') -remove_sources(r'.*i8254xGBe.*', 'src/dev') +def remove_lines(s_regex, e_regex, f): + f = joinpath(release_dir, f) + if isinstance(s_regex, str): + s_regex = re.compile(s_regex) + if isinstance(e_regex, str): + e_regex = re.compile(e_regex) + inscript = file(f, 'r').readlines() + outscript = file(f, 'w') + skipping = False + for line in inscript: + if (not skipping and s_regex.match(line)) or \ + (e_regex and skipping and not e_regex.match(line)): + skipping = True + continue + skipping = False + outscript.write(line) + outscript.close() + +def replace_line(s_regex, f, rl): + f = joinpath(release_dir, f) + if isinstance(s_regex, str): + s_regex = re.compile(s_regex) + inscript = file(f, 'r').readlines() + outscript = file(f, 'w') + for line in inscript: + if s_regex.match(line): + outscript.write(rl) + continue + outscript.write(line) + outscript.close() + +# fix up the SConscript to deal with files we've removed +#remove_sources(r'.*split.*\.cc', 'src/mem/cache/tags') +#remove_sources(r'.*(ghb|stride)_prefetcher\.cc', 'src/mem/cache/prefetch') +remove_sources(r'.*nativetrace.*', 'src/cpu') + +remove_lines(r'.*X86.*', None, 'src/arch/isa_specific.hh') +remove_lines(r'.*X86.*', None, 'src/base/traceflags.py') +remove_lines(r'.*X86.*', None, 'src/base/loader/object_file.hh') +remove_lines(r'.*_X86_.*', '.*else.*', 'src/base/loader/elf_object.cc') +remove_lines(r'.*X86_ISA.*', r'^.el.*','src/sim/process.cc') +remove_lines(r'.*x86.*', r'.*mips.*','src/cpu/BaseCPU.py') +remove_lines(r'.*X86_ISA.*', r'^.*else.*','src/cpu/o3/dyn_inst.hh') +remove_lines(r'.*X86_ISA.*', r'.*stay.*','src/cpu/simple/base.cc') +remove_lines(r'.*x86.*', r'^if.*','src/cpu/SConscript') + +remove_lines(r'.*makeX86System.*', r'.*makeDualRoot.*','configs/common/FSConfig.py') +remove_lines(r'.*X86.*', None, 'configs/example/fs.py') +remove_lines(r'.*x86.*', None, 'configs/example/fs.py') + +replace_line(r'.*X86_SE.*', 'util/regress', " 'SPARC_SE,SPARC_FS',") benches = [ 'bzip2', 'eon', 'gzip', 'mcf', 'parser', 'perlbmk', 'twolf', 'vortex' ] for bench in benches: rmtree(release_dir, 'tests', 'test-progs', bench) -movedir(release_dir, encumbered_dir, 'src/encumbered') -movedir(release_dir, encumbered_dir, 'tests/test-progs/anagram') -movedir(release_dir, encumbered_dir, 'tests/quick/20.eio-short') +#movedir(release_dir, encumbered_dir, 'src/encumbered') +rmtree(release_dir, 'tests/test-progs/anagram') +rmtree(release_dir, 'tests/quick/20.eio-short') def taritup(directory, destdir, filename): basedir = dirname(directory) @@ -175,8 +229,7 @@ def taritup(directory, destdir, filename): system('cd %s; tar cfj %s %s' % (basedir, tarball, tardir)) taritup(release_dir, destdir, '%s.tar.bz2' % releasename) -taritup(encumbered_dir, destdir, '%s-encumbered.tar.bz2' % releasename) +#taritup(encumbered_dir, destdir, '%s-encumbered.tar.bz2' % releasename) print "release created in %s" % destdir -print "don't forget to tag the repository! The following command will do it:" -print "bk tag %s" % releasename +print "don't forget to tag the repository!" @@ -1,6 +1,6 @@ #! /usr/bin/env python -# Copyright (c) 2004-2005 The Regents of The University of Michigan +# Copyright (c) 2004-2005, 2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -27,6 +27,15 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Steve Reinhardt +# Ali Saidi + +# Important! +# This script expects a simple $ prompt, if you are using a shell other than +# sh which defaults to this you'll need to add something like the following +# to your bashrc/bash_profile script: +#if [ "$OAR_USER" = "xxxx" ]; then +# PS1='$ ' + import sys import os @@ -46,13 +55,13 @@ optparser.add_option('-e', dest='stderr_file', optparser.add_option('-o', dest='stdout_file', help='command stdout output file') optparser.add_option('-l', dest='save_log', action='store_true', - help='save qsub output log file') + help='save oarsub output log file') optparser.add_option('-N', dest='job_name', - help='qsub job name') + help='oarsub job name') optparser.add_option('-q', dest='dest_queue', - help='qsub destination queue') -optparser.add_option('--qwait', dest='qsub_timeout', type='int', - help='qsub queue wait timeout', default=30*60) + help='oarsub destination queue') +optparser.add_option('--qwait', dest='oarsub_timeout', type='int', + help='oarsub queue wait timeout', default=30*60) optparser.add_option('-t', dest='cmd_timeout', type='int', help='command execution timeout', default=600*60) @@ -63,7 +72,7 @@ if cmd == []: sys.exit(1) # If we want to do this, need to add check here to make sure cmd[0] is -# a valid PBS job name, else qsub will die on us. +# a valid PBS job name, else oarsub will die on us. # #if not options.job_name: # options.job_name = cmd[0] @@ -98,11 +107,11 @@ class Shell(pexpect.spawn): self.quick_timeout = 15 # wait for a prompt, then change it try: - self.expect('\$ ', options.qsub_timeout) + self.expect('\$ ', options.oarsub_timeout) except pexpect.TIMEOUT: - print >>sys.stderr, "%s: qsub timed out." % progname + print >>sys.stderr, "%s: oarsub timed out." % progname self.kill(9) - self.close(wait=True) + self.safe_close() sys.exit(1) self.do_command('unset PROMPT_COMMAND; PS1="qdo$ "') @@ -137,8 +146,17 @@ class Shell(pexpect.spawn): (output, status) = shell.do_command('[ -d %s ]' % dirname, self.quick_timeout) return status == 0 - - + + # Don't actually try to close it.. just wait until it closes by itself + # We can't actually kill the pid which is what it's trying to do, and if + # we call wait we could be in an unfortunate situation of it printing input + # right as we call wait, so the input is never read and the process never ends + def safe_close(self): + count = 0 + while self.isalive() and count < 10: + time.sleep(1) + self.close(force=False) + # Spawn the interactive pool job. # Hack to do link on poolfs... disabled for now since @@ -148,11 +166,12 @@ if False and len(cmd) > 50: shell_cmd = 'ssh -t poolfs /bin/sh -l' print "%s: running %s on poolfs" % (progname, cmd[0]) else: - shell_cmd = 'qsub -I -S /bin/sh' + shell_cmd = 'oarsub -I' if options.job_name: - shell_cmd += ' -N "%s"' % options.job_name + shell_cmd += ' -n "%s"' % options.job_name if options.dest_queue: shell_cmd += ' -q ' + options.dest_queue + shell_cmd += ' -d %s' % cwd shell = Shell(shell_cmd) @@ -197,25 +216,23 @@ try: except pexpect.TIMEOUT: print >>sys.stderr, "%s: command timed out after %d seconds." \ % (progname, options.cmd_timeout) - shell.sendline('~.') # qsub/ssh termination escape sequence - shell.close(wait=True) + shell.sendline('~.') # oarsub/ssh termination escape sequence + shell.safe_close() status = 3 if output: print output - finally: # end job if shell.isalive(): shell.sendline('exit') - shell.expect('qsub: job .* completed\r\n') - shell.close(wait=True) + shell.expect('Disconnected from OAR job .*') + shell.safe_close() # if there was an error, log the output even if not requested if status != 0 or options.save_log: log = file('qdo-log.' + str(os.getpid()), 'w') log.write(shell.full_output) log.close() - del shell sys.exit(status) diff --git a/util/regress b/util/regress index 8ff07c453..034201317 100755 --- a/util/regress +++ b/util/regress @@ -40,7 +40,8 @@ optparser.add_option('-v', '--verbose', dest='verbose', action='store_true', default=False, help='echo commands before executing') optparser.add_option('--builds', dest='builds', - default='ALPHA_SE,ALPHA_FS,MIPS_SE,SPARC_SE,SPARC_FS', + default='ALPHA_SE,ALPHA_FS,MIPS_SE,' + \ + 'SPARC_SE,SPARC_FS,X86_SE', help='comma-separated list of build targets to test ' " (default: '%default')" ) optparser.add_option('--variants', dest='variants', |