diff options
| -rw-r--r-- | src/arch/x86/insts/static_inst.cc | 16 | ||||
| -rw-r--r-- | src/arch/x86/isa/microasm.isa | 2 | ||||
| -rw-r--r-- | src/arch/x86/isa/microops/ldstop.isa | 8 | ||||
| -rw-r--r-- | src/arch/x86/miscregs.hh | 4 | ||||
| -rw-r--r-- | src/arch/x86/segmentregs.hh | 1 | ||||
| -rw-r--r-- | src/arch/x86/tlb.cc | 2 |
6 files changed, 21 insertions, 12 deletions
diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc index d2ec8878c..183700fa9 100644 --- a/src/arch/x86/insts/static_inst.cc +++ b/src/arch/x86/insts/static_inst.cc @@ -56,6 +56,7 @@ */ #include "arch/x86/insts/static_inst.hh" +#include "arch/x86/segmentregs.hh" namespace X86ISA { @@ -75,24 +76,27 @@ namespace X86ISA { switch (segment) { - case 0: + case SEGMENT_REG_ES: ccprintf(os, "ES"); break; - case 1: + case SEGMENT_REG_CS: ccprintf(os, "CS"); break; - case 2: + case SEGMENT_REG_SS: ccprintf(os, "SS"); break; - case 3: + case SEGMENT_REG_DS: ccprintf(os, "DS"); break; - case 4: + case SEGMENT_REG_FS: ccprintf(os, "FS"); break; - case 5: + case SEGMENT_REG_GS: ccprintf(os, "GS"); break; + case SEGMENT_REG_INT: + ccprintf(os, "INT"); + break; default: panic("Unrecognized segment %d\n", segment); } diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 0c43d4c13..e05582e37 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -108,7 +108,7 @@ let {{ # This segment selects an internal address space mapped to MSRs, # CPUID info, etc. - assembler.symbols["intseg"] = "NUM_SEGMENTREGS" + assembler.symbols["intseg"] = "SEGMENT_REG_INT" for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'): assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper() diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 61adde8d1..77152a190 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -123,7 +123,7 @@ def template MicroLoadExecute {{ %(ea_code)s; DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); - fault = read(xc, EA, Mem, (%(mem_flags)s) | (1 << segment)); + fault = read(xc, EA, Mem, (%(mem_flags)s) | segment); if(fault == NoFault) { @@ -150,7 +150,7 @@ def template MicroLoadInitiateAcc {{ %(ea_code)s; DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); - fault = read(xc, EA, Mem, (%(mem_flags)s) | (1 << segment)); + fault = read(xc, EA, Mem, (%(mem_flags)s) | segment); return fault; } @@ -197,7 +197,7 @@ def template MicroStoreExecute {{ if(fault == NoFault) { - fault = write(xc, Mem, EA, (%(mem_flags)s) | (1 << segment)); + fault = write(xc, Mem, EA, (%(mem_flags)s) | segment); if(fault == NoFault) { %(op_wb)s; @@ -224,7 +224,7 @@ def template MicroStoreInitiateAcc {{ if(fault == NoFault) { - fault = write(xc, Mem, EA, (%(mem_flags)s) | (1 << segment)); + fault = write(xc, Mem, EA, (%(mem_flags)s) | segment); if(fault == NoFault) { %(op_wb)s; diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh index a516a2018..3a30b9800 100644 --- a/src/arch/x86/miscregs.hh +++ b/src/arch/x86/miscregs.hh @@ -258,6 +258,7 @@ namespace X86ISA MISCREG_DS, MISCREG_FS, MISCREG_GS, + MISCREG_INT, // This isn't actually used. // Hidden segment base field MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NumSegments, @@ -267,6 +268,7 @@ namespace X86ISA MISCREG_DS_BASE, MISCREG_FS_BASE, MISCREG_GS_BASE, + MISCREG_INT_BASE, // Hidden segment limit field MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_BASE_BASE + NumSegments, @@ -276,6 +278,7 @@ namespace X86ISA MISCREG_DS_LIMIT, MISCREG_FS_LIMIT, MISCREG_GS_LIMIT, + MISCREG_INT_LIMIT, // This isn't actually used. // Hidden segment limit attributes MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NumSegments, @@ -285,6 +288,7 @@ namespace X86ISA MISCREG_DS_ATTR, MISCREG_FS_ATTR, MISCREG_GS_ATTR, + MISCREG_INT_ATTR, // This isn't actually used. // System segment selectors MISCREG_SYSSEG_SEL_BASE = MISCREG_SEG_ATTR_BASE + NumSegments, diff --git a/src/arch/x86/segmentregs.hh b/src/arch/x86/segmentregs.hh index 9fd9bcb0e..524b756d6 100644 --- a/src/arch/x86/segmentregs.hh +++ b/src/arch/x86/segmentregs.hh @@ -68,6 +68,7 @@ namespace X86ISA SEGMENT_REG_DS, SEGMENT_REG_FS, SEGMENT_REG_GS, + SEGMENT_REG_INT, NUM_SEGMENTREGS }; diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 6afee6d72..bf5a8434b 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -150,7 +150,7 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute) // If this is true, we're dealing with a request to read an internal // value. - if (seg == NUM_SEGMENTREGS) { + if (seg == SEGMENT_REG_INT) { Addr prefix = vaddr & IntAddrPrefixMask; if (prefix == IntAddrPrefixCPUID) { panic("CPUID memory space not yet implemented!\n"); |