diff options
| -rw-r--r-- | tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt | 44 | ||||
| -rwxr-xr-x | tests/long/10.mcf/ref/x86/linux/simple-timing/stdout | 8 |
2 files changed, 26 insertions, 26 deletions
diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt index 21761f34b..94a44a507 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1094085 # Simulator instruction rate (inst/s) -host_mem_usage 336424 # Number of bytes of host memory used -host_seconds 246.51 # Real time elapsed on the host -host_tick_rate 2009645019 # Simulator tick rate (ticks/s) +host_inst_rate 1084581 # Simulator instruction rate (inst/s) +host_mem_usage 336400 # Number of bytes of host memory used +host_seconds 248.67 # Real time elapsed on the host +host_tick_rate 1992187591 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 269697303 # Number of instructions simulated sim_seconds 0.495388 # Number of seconds simulated @@ -19,13 +19,13 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 25155670000 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.021483 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1950188 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 31439750 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55999.899641 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.899641 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 56000.034908 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000.034908 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 31210573 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 12833889000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 12833920000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.007289 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 229177 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 12146358000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 12146389000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.007289 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 229177 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked @@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 122219193 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 20116.007644 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 17116.007644 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 20116.021869 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency system.cpu.dcache.demand_hits 120039828 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 43840123000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 43840154000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.017832 # miss rate for demand accesses system.cpu.dcache.demand_misses 2179365 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 37302028000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 37302059000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.017832 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2179365 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 122219193 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 20116.007644 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 17116.007644 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 20116.021869 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 17116.021869 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 120039828 # number of overall hits -system.cpu.dcache.overall_miss_latency 43840123000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 43840154000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.017832 # miss rate for overall accesses system.cpu.dcache.overall_misses 2179365 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 37302028000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 37302059000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.017832 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2179365 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -144,9 +144,9 @@ system.cpu.icache.warmup_cycle 0 # Cy system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.l2cache.ReadExReq_accesses 103852 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.298502 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 5400304000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 5400335000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 103852 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_mshr_miss_latency 4154080000 # number of ReadExReq MSHR miss cycles @@ -182,10 +182,10 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 # system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 2054847 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000.160755 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1862007 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10027680000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 10027711000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.093846 # miss rate for demand accesses system.cpu.l2cache.demand_misses 192840 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits @@ -196,11 +196,11 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.overall_accesses 2054847 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000.160755 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1862007 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10027680000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 10027711000 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.093846 # miss rate for overall accesses system.cpu.l2cache.overall_misses 192840 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout b/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout index 70a595464..a552023cf 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stdout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 7 2008 03:21:37 -M5 revision 5728:a583591131186a0f2de150efdfc82a154d166fb5 -M5 commit date Thu Nov 06 23:13:50 2008 -0800 -M5 started Nov 8 2008 01:13:22 +M5 compiled Nov 13 2008 21:51:42 +M5 revision 5729:f186533c0dc2d948be0523b452356918124d7f57 +M5 commit date Sun Nov 09 21:57:15 2008 -0800 +M5 started Nov 13 2008 21:51:43 M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re --stdout-file stdout --stderr-file stderr tests/run.py long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second |