diff options
| -rw-r--r-- | src/arch/x86/x86_traits.hh | 4 | ||||
| -rw-r--r-- | src/cpu/BaseCPU.py | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh index be7572517..0347a7099 100644 --- a/src/arch/x86/x86_traits.hh +++ b/src/arch/x86/x86_traits.hh @@ -92,8 +92,8 @@ namespace X86ISA const Addr PhysAddrPrefixIO = ULL(0x8000000000000000); const Addr PhysAddrPrefixPciConfig = ULL(0xC000000000000000); - const Addr PhysAddrPrefixLocalAPIC = ULL(0xA000000000000000); - const Addr PhysAddrPrefixInterrupts = ULL(0x2000000000000000); + const Addr PhysAddrPrefixLocalAPIC = ULL(0x2000000000000000); + const Addr PhysAddrPrefixInterrupts = ULL(0xA000000000000000); // Each APIC gets two pages. One page is used for local apics to field // accesses from the CPU, and the other is for all APICs to communicate. const Addr PhysAddrAPICRangeSize = 1 << 12; diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 51d447f0b..ef9b54f3f 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -97,7 +97,7 @@ class BaseCPU(MemObject): dtb = Param.X86DTB(X86DTB(), "Data TLB") itb = Param.X86ITB(X86ITB(), "Instruction TLB") if build_env['FULL_SYSTEM']: - _localApic = X86LocalApic(pio_addr=0xa000000000000000) + _localApic = X86LocalApic(pio_addr=0x2000000000000000) interrupts = \ Param.X86LocalApic(_localApic, "Interrupt Controller") elif build_env['TARGET_ISA'] == 'mips': |