diff options
| -rw-r--r-- | src/arch/alpha/predecoder.hh | 6 | ||||
| -rw-r--r-- | src/arch/mips/predecoder.hh | 3 | ||||
| -rw-r--r-- | src/arch/sparc/predecoder.hh | 4 | ||||
| -rw-r--r-- | src/arch/x86/predecoder.hh | 6 | ||||
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 2 | ||||
| -rw-r--r-- | src/cpu/simple/atomic.cc | 6 | ||||
| -rw-r--r-- | src/cpu/simple/base.cc | 10 |
7 files changed, 15 insertions, 22 deletions
diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh index 0407ce99b..4887de856 100644 --- a/src/arch/alpha/predecoder.hh +++ b/src/arch/alpha/predecoder.hh @@ -44,8 +44,6 @@ namespace AlphaISA { protected: ThreadContext * tc; - //The pc of the current instruction - Addr fetchPC; //The extended machine instruction being generated ExtMachInst ext_inst; @@ -69,10 +67,8 @@ namespace AlphaISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr pc, Addr _fetchPC, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr fetchPC, MachInst inst) { - fetchPC = _fetchPC; - assert(off == 0); ext_inst = inst; #if FULL_SYSTEM if (pc && 0x1) diff --git a/src/arch/mips/predecoder.hh b/src/arch/mips/predecoder.hh index 90f768d73..e310dded4 100644 --- a/src/arch/mips/predecoder.hh +++ b/src/arch/mips/predecoder.hh @@ -66,9 +66,8 @@ namespace MipsISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr fetchPC, MachInst inst) { - assert(off == 0); emi = inst; } diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh index 38d8fd1a2..d990c3256 100644 --- a/src/arch/sparc/predecoder.hh +++ b/src/arch/sparc/predecoder.hh @@ -67,10 +67,8 @@ namespace SparcISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst) + void moreBytes(Addr pc, Addr fetchPC, MachInst inst) { - assert(off == 0); - emi = inst; //The I bit, bit 13, is used to figure out where the ASI //should come from. Use that in the ExtMachInst. This is diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh index 3c858f061..f34b66364 100644 --- a/src/arch/x86/predecoder.hh +++ b/src/arch/x86/predecoder.hh @@ -195,12 +195,12 @@ namespace X86ISA //Use this to give data to the predecoder. This should be used //when there is control flow. - void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst data) + void moreBytes(Addr pc, Addr fetchPC, MachInst data) { + DPRINTF(Predecoder, "Getting more bytes.\n"); basePC = fetchPC; - offset = off; + offset = (fetchPC >= pc) ? 0 : pc - fetchPC; fetchChunk = data; - assert(off < sizeof(MachInst)); outOfBytes = false; process(); } diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index ab55ec744..1ce5bd20f 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1128,7 +1128,7 @@ DefaultFetch<Impl>::fetch(bool &status_change) (&cacheData[tid][offset])); predecoder.setTC(cpu->thread[tid]->getTC()); - predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst); + predecoder.moreBytes(fetch_PC, fetch_PC, inst); ext_inst = predecoder.getExtMachInst(); diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index ea1c7d87f..03ff1282b 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -521,15 +521,15 @@ AtomicSimpleCPU::tick() dcache_access = false; // assume no dcache access //Fetch more instruction memory if necessary - if(predecoder.needMoreBytes()) - { + //if(predecoder.needMoreBytes()) + //{ icache_access = true; ifetch_pkt->reinitFromRequest(); icache_latency = icachePort.sendAtomic(ifetch_pkt); // ifetch_req is initialized to read the instruction directly // into the CPU object's inst field. - } + //} preExecute(); diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index b7f60522f..9285aa7b5 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -379,11 +379,11 @@ BaseSimpleCPU::preExecute() //This should go away once the constructor can be set up properly predecoder.setTC(thread->getTC()); //If more fetch data is needed, pass it in. - if(predecoder.needMoreBytes()) - predecoder.moreBytes(thread->readPC(), - (thread->readPC() & PCMask) + fetchOffset, 0, inst); - else - predecoder.process(); + Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset; + //if(predecoder.needMoreBytes()) + predecoder.moreBytes(thread->readPC(), fetchPC, inst); + //else + // predecoder.process(); //If an instruction is ready, decode it. Otherwise, we'll have to //fetch beyond the MachInst at the current pc. |