diff options
| -rw-r--r-- | README | 7 | ||||
| -rw-r--r-- | build/SConstruct | 3 | ||||
| -rw-r--r-- | dev/ide_ctrl.cc | 31 | ||||
| -rw-r--r--[-rwxr-xr-x] | dev/isa_fake.cc | 0 | ||||
| -rw-r--r--[-rwxr-xr-x] | dev/isa_fake.hh | 0 | ||||
| -rw-r--r-- | dev/pcidev.cc | 2 |
6 files changed, 25 insertions, 18 deletions
@@ -65,9 +65,10 @@ To build and test the syscall-emulation simulator: 2. In $top/m5-test, run "./do-tests.pl -B ALPHA_SE". The tests should end with "finished do-tests successfully!" -Note: if you're running under Cygwin several tests will fail with an -"EIO icount mismatch". This is due to the lack of fesetround() under -Cygwin causing differences in floating-point rounding. +Note: if you're running under Cygwin, several tests will fail with an +"EIO trace inconsistency: ICNT mismatch" error. This is due to the +lack of fesetround() under Cygwin causing differences in floating-point +rounding. Other than that discrepancy your simulator is working perfectly. To build and test the full-system simualator: diff --git a/build/SConstruct b/build/SConstruct index 87c215d41..8819e3649 100644 --- a/build/SConstruct +++ b/build/SConstruct @@ -254,6 +254,9 @@ default_env.Append(ENV = { 'M5_EXT' : EXT_SRCDIR }) default_env.Append(CCFLAGS='-pipe') default_env.Append(CCFLAGS='-fno-strict-aliasing') default_env.Append(CCFLAGS=Split('-Wall -Wno-sign-compare -Werror -Wundef')) +if sys.platform == 'cygwin': + # cygwin has some header file issues... + default_env.Append(CCFLAGS=Split("-Wno-uninitialized")) default_env.Append(CPPPATH=[os.path.join(EXT_SRCDIR + '/dnet')]) # libelf build is described in its own SConscript file. Using a diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc index 6ad80e69d..b9b9df654 100644 --- a/dev/ide_ctrl.cc +++ b/dev/ide_ctrl.cc @@ -484,8 +484,8 @@ IdeController::write(MemReqPtr &req, const uint8_t *data) // select the current disk based on DEV bit disk = getDisk(channel); - oldVal = letoh(bmi_regs.chan[channel].bmic); - newVal = letoh(*data); + oldVal = bmi_regs.chan[channel].bmic; + newVal = *data; // if a DMA transfer is in progress, R/W control cannot change if (oldVal & SSBM) { @@ -501,8 +501,8 @@ IdeController::write(MemReqPtr &req, const uint8_t *data) DPRINTF(IdeCtrl, "Stopping DMA transfer\n"); // clear the BMIDEA bit - bmi_regs.chan[channel].bmis = letoh( - letoh(bmi_regs.chan[channel].bmis) & ~BMIDEA); + bmi_regs.chan[channel].bmis = + bmi_regs.chan[channel].bmis & ~BMIDEA; if (disks[disk] == NULL) panic("DMA stop for disk %d which does not exist\n", @@ -515,8 +515,8 @@ IdeController::write(MemReqPtr &req, const uint8_t *data) DPRINTF(IdeCtrl, "Starting DMA transfer\n"); // set the BMIDEA bit - bmi_regs.chan[channel].bmis = letoh( - letoh(bmi_regs.chan[channel].bmis) | BMIDEA); + bmi_regs.chan[channel].bmis = + bmi_regs.chan[channel].bmis | BMIDEA; if (disks[disk] == NULL) panic("DMA start for disk %d which does not exist\n", @@ -528,7 +528,7 @@ IdeController::write(MemReqPtr &req, const uint8_t *data) } // update the register value - bmi_regs.chan[channel].bmic = letoh(newVal); + bmi_regs.chan[channel].bmic = newVal; break; // Bus master IDE status register @@ -537,8 +537,8 @@ IdeController::write(MemReqPtr &req, const uint8_t *data) if (req->size != sizeof(uint8_t)) panic("Invalid BMIS write size: %x\n", req->size); - oldVal = letoh(bmi_regs.chan[channel].bmis); - newVal = letoh(*data); + oldVal = bmi_regs.chan[channel].bmis; + newVal = *data; // the BMIDEA bit is RO newVal |= (oldVal & BMIDEA); @@ -554,17 +554,20 @@ IdeController::write(MemReqPtr &req, const uint8_t *data) else (oldVal & IDEDMAE) ? newVal |= IDEDMAE : newVal &= ~IDEDMAE; - bmi_regs.chan[channel].bmis = letoh(newVal); + bmi_regs.chan[channel].bmis = newVal; break; // Bus master IDE descriptor table pointer register case BMIDTP0: case BMIDTP1: - if (req->size != sizeof(uint32_t)) - panic("Invalid BMIDTP write size: %x\n", req->size); + { + if (req->size != sizeof(uint32_t)) + panic("Invalid BMIDTP write size: %x\n", req->size); - bmi_regs.chan[channel].bmidtp = letoh( - letoh(*(uint32_t*)data) & ~0x3); + uint32_t host_data = letoh(*(uint32_t*)data); + host_data &= ~0x3; + bmi_regs.chan[channel].bmidtp = htole(host_data); + } break; default: diff --git a/dev/isa_fake.cc b/dev/isa_fake.cc index af8005f9c..af8005f9c 100755..100644 --- a/dev/isa_fake.cc +++ b/dev/isa_fake.cc diff --git a/dev/isa_fake.hh b/dev/isa_fake.hh index d3d37b035..d3d37b035 100755..100644 --- a/dev/isa_fake.hh +++ b/dev/isa_fake.hh diff --git a/dev/pcidev.cc b/dev/pcidev.cc index 04a38151e..2bfd8a1c7 100644 --- a/dev/pcidev.cc +++ b/dev/pcidev.cc @@ -203,7 +203,7 @@ PciDev::writeConfig(int offset, int size, const uint8_t *data) case PCI0_ROM_BASE_ADDR: if (letoh(data32) == 0xfffffffe) - config.expansionROM = letoh(0xffffffff); + config.expansionROM = htole((uint32_t)0xffffffff); else config.expansionROM = data32; break; |