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-rw-r--r--src/mem/cache/cache.cc6
-rw-r--r--src/mem/cache/mshr.hh7
2 files changed, 9 insertions, 4 deletions
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 85c96772c..9ee935961 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -1826,10 +1826,10 @@ Cache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks)
Addr repl_addr = tags->regenerateBlkAddr(blk);
MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure());
if (repl_mshr) {
- // must be an outstanding upgrade request
+ // must be an outstanding upgrade or clean request
// on a block we're about to replace...
- assert(!blk->isWritable() || blk->isDirty());
- assert(repl_mshr->needsWritable());
+ assert((!blk->isWritable() && repl_mshr->needsWritable()) ||
+ repl_mshr->isCleaning());
// too hard to replace block with transient state
// allocation failed, block not inserted
return nullptr;
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index 1f59607bf..5fe0fb92d 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2015-2016 ARM Limited
+ * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -235,6 +235,11 @@ class MSHR : public QueueEntry, public Printable
/** True if we need to get a writable copy of the block. */
bool needsWritable() const { return targets.needsWritable; }
+ bool isCleaning() const {
+ PacketPtr pkt = targets.front().pkt;
+ return pkt->isClean();
+ }
+
bool isPendingModified() const {
assert(inService); return pendingModified;
}