diff options
| -rw-r--r-- | src/arch/arm/isa/insts/data.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index f96416168..daac4ed3c 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -96,7 +96,7 @@ let {{ secondOpRe = re.compile("secondOp") immOp2 = "imm" regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodes<29:>)" - regRegOp2 = "shift_rm_rs(Op2, Shift, shiftType, CondCodes<29:>)" + regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodes<29:>)" def buildDataInst(mnem, code, flagType = "logic"): global header_output, decoder_output, exec_output |