diff options
140 files changed, 10571 insertions, 10525 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 586920bf4..dfd7f9bb3 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -101,6 +101,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 @@ -544,6 +545,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index 3648b647f..ef1ae1471 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:33:13 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 16 2013 01:34:33 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 0cce0ce1e..213dc1867 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.902739 # Nu sim_ticks 1902738973500 # Number of ticks simulated final_tick 1902738973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97410 # Simulator instruction rate (inst/s) -host_op_rate 97410 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3267297836 # Simulator tick rate (ticks/s) -host_mem_usage 312988 # Number of bytes of host memory used -host_seconds 582.36 # Real time elapsed on the host +host_inst_rate 132013 # Simulator instruction rate (inst/s) +host_op_rate 132013 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4427958303 # Simulator tick rate (ticks/s) +host_mem_usage 313120 # Number of bytes of host memory used +host_seconds 429.71 # Real time elapsed on the host sim_insts 56727331 # Number of instructions simulated sim_ops 56727331 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 900544 # Number of bytes read from this memory @@ -867,8 +867,8 @@ system.cpu0.rename.IQFullEvents 638131 # Nu system.cpu0.rename.LSQFullEvents 1449994 # Number of times rename has blocked due to LSQ full system.cpu0.rename.RenamedOperands 39722637 # Number of destination operands rename has renamed system.cpu0.rename.RenameLookups 72231674 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 71847381 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 384293 # Number of floating rename lookups +system.cpu0.rename.int_rename_lookups 72093935 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 128190 # Number of floating rename lookups system.cpu0.rename.CommittedMaps 34859464 # Number of HB maps that are committed system.cpu0.rename.UndoneMaps 4863165 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 1453792 # count of serializing insts renamed @@ -1552,8 +1552,8 @@ system.cpu1.rename.IQFullEvents 55937 # Nu system.cpu1.rename.LSQFullEvents 153486 # Number of times rename has blocked due to LSQ full system.cpu1.rename.RenamedOperands 7119549 # Number of destination operands rename has renamed system.cpu1.rename.RenameLookups 12930789 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12790175 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 140614 # Number of floating rename lookups +system.cpu1.rename.int_rename_lookups 12872049 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52940 # Number of floating rename lookups system.cpu1.rename.CommittedMaps 6082585 # Number of HB maps that are committed system.cpu1.rename.UndoneMaps 1036964 # Number of HB maps that are undone due to squashing system.cpu1.rename.serializingInsts 436590 # count of serializing insts renamed diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index d23f48fda..4bc22a482 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -101,6 +101,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 646f2a7f4..7f8767e11 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:33:00 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 16 2013 01:34:33 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index c5784a1fd..56fb70faf 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.860201 # Nu sim_ticks 1860200687500 # Number of ticks simulated final_tick 1860200687500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95880 # Simulator instruction rate (inst/s) -host_op_rate 95880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3366492305 # Simulator tick rate (ticks/s) -host_mem_usage 308824 # Number of bytes of host memory used -host_seconds 552.56 # Real time elapsed on the host +host_inst_rate 133673 # Simulator instruction rate (inst/s) +host_op_rate 133673 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4693486883 # Simulator tick rate (ticks/s) +host_mem_usage 310052 # Number of bytes of host memory used +host_seconds 396.34 # Real time elapsed on the host sim_insts 52979577 # Number of instructions simulated sim_ops 52979577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory @@ -557,8 +557,8 @@ system.cpu.rename.IQFullEvents 505660 # Nu system.cpu.rename.LSQFullEvents 1537414 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 43855524 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 79710296 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79230933 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 479363 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 79531258 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 166586 # Number of floating rename lookups system.cpu.rename.CommittedMaps 38179970 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 5675546 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 1682539 # count of serializing insts renamed diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini index a2e0a4348..8b5822c19 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -259,6 +259,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout index bb27cc97c..6d6f549a2 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:34:17 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 16 2013 01:34:47 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index ea150be87..f5971916a 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.842705 # Nu sim_ticks 1842705252000 # Number of ticks simulated final_tick 1842705252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 308319 # Simulator instruction rate (inst/s) -host_op_rate 308319 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7821132493 # Simulator tick rate (ticks/s) -host_mem_usage 307864 # Number of bytes of host memory used -host_seconds 235.61 # Real time elapsed on the host +host_inst_rate 260475 # Simulator instruction rate (inst/s) +host_op_rate 260475 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6607474809 # Simulator tick rate (ticks/s) +host_mem_usage 309028 # Number of bytes of host memory used +host_seconds 278.88 # Real time elapsed on the host sim_insts 72641883 # Number of instructions simulated sim_ops 72641883 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory @@ -1513,8 +1513,8 @@ system.cpu2.rename.IQFullEvents 231189 # Nu system.cpu2.rename.LSQFullEvents 444117 # Number of times rename has blocked due to LSQ full system.cpu2.rename.RenamedOperands 23541427 # Number of destination operands rename has renamed system.cpu2.rename.RenameLookups 43931372 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 43768405 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 162967 # Number of floating rename lookups +system.cpu2.rename.int_rename_lookups 43874902 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 52705 # Number of floating rename lookups system.cpu2.rename.CommittedMaps 21760313 # Number of HB maps that are committed system.cpu2.rename.UndoneMaps 1781114 # Number of HB maps that are undone due to squashing system.cpu2.rename.serializingInsts 501831 # count of serializing insts renamed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 3a7534dfa..d132fd20b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -127,6 +127,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 4638446ac..6df74fa42 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:14:57 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:31:27 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 4688e11b5..5c2619e22 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.524310 # Nu sim_ticks 2524309551500 # Number of ticks simulated final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67450 # Simulator instruction rate (inst/s) -host_op_rate 86789 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2823365435 # Simulator tick rate (ticks/s) -host_mem_usage 397608 # Number of bytes of host memory used -host_seconds 894.08 # Real time elapsed on the host +host_inst_rate 55803 # Simulator instruction rate (inst/s) +host_op_rate 71803 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2335855340 # Simulator tick rate (ticks/s) +host_mem_usage 401408 # Number of bytes of host memory used +host_seconds 1080.68 # Real time elapsed on the host sim_insts 60305560 # Number of instructions simulated sim_ops 77596391 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory @@ -758,8 +758,8 @@ system.cpu.rename.LSQFullEvents 4066422 # Nu system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 466885287 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90688 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 432104229 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10389 # Number of floating rename lookups system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 83b4b4ad3..7ff8826e3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -25,7 +25,7 @@ load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -127,6 +127,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 @@ -602,6 +603,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 56628ec16..5def9d861 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 07:58:48 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:18:35 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 1d3b3b539..99b249a14 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,31 +4,13 @@ sim_seconds 1.104038 # Nu sim_ticks 1104038330000 # Number of ticks simulated final_tick 1104038330000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67767 # Simulator instruction rate (inst/s) -host_op_rate 87238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1214516577 # Simulator tick rate (ticks/s) -host_mem_usage 404472 # Number of bytes of host memory used -host_seconds 909.04 # Real time elapsed on the host +host_inst_rate 65967 # Simulator instruction rate (inst/s) +host_op_rate 84921 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1182267512 # Simulator tick rate (ticks/s) +host_mem_usage 404512 # Number of bytes of host memory used +host_seconds 933.83 # Real time elapsed on the host sim_insts 61602211 # Number of instructions simulated sim_ops 79302243 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory @@ -485,6 +467,24 @@ system.physmem.writeRowHits 98940 # Nu system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate 12.01 # Row buffer hit rate for writes system.physmem.avgGap 155904.23 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) system.membus.throughput 62410733 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 7306749 # Transaction distribution system.membus.trans_dist::ReadResp 7306749 # Transaction distribution @@ -1252,8 +1252,8 @@ system.cpu0.rename.LSQFullEvents 1152507 # Nu system.cpu0.rename.FullRegisterEvents 84 # Number of times there has been no free registers system.cpu0.rename.RenamedOperands 39264921 # Number of destination operands rename has renamed system.cpu0.rename.RenameLookups 175790758 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175756522 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34236 # Number of floating rename lookups +system.cpu0.rename.int_rename_lookups 161860177 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 4025 # Number of floating rename lookups system.cpu0.rename.CommittedMaps 30938700 # Number of HB maps that are committed system.cpu0.rename.UndoneMaps 8326220 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 411215 # count of serializing insts renamed @@ -1823,8 +1823,8 @@ system.cpu1.rename.LSQFullEvents 3042854 # Nu system.cpu1.rename.FullRegisterEvents 1130 # Number of times there has been no free registers system.cpu1.rename.RenamedOperands 69218982 # Number of destination operands rename has renamed system.cpu1.rename.RenameLookups 302521919 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 302462653 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59266 # Number of floating rename lookups +system.cpu1.rename.int_rename_lookups 280703259 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6508 # Number of floating rename lookups system.cpu1.rename.CommittedMaps 49058929 # Number of HB maps that are committed system.cpu1.rename.UndoneMaps 20160053 # Number of HB maps that are undone due to squashing system.cpu1.rename.serializingInsts 444772 # count of serializing insts renamed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 442f4520f..f1e51a584 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -25,7 +25,7 @@ load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -127,6 +127,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 67309d0d5..3406cd0de 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 07:59:33 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:15:54 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index d95619189..ab328c798 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,25 +4,13 @@ sim_seconds 2.524310 # Nu sim_ticks 2524309551500 # Number of ticks simulated final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66090 # Simulator instruction rate (inst/s) -host_op_rate 85039 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2766442256 # Simulator tick rate (ticks/s) -host_mem_usage 401396 # Number of bytes of host memory used -host_seconds 912.48 # Real time elapsed on the host +host_inst_rate 65403 # Simulator instruction rate (inst/s) +host_op_rate 84155 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2737677908 # Simulator tick rate (ticks/s) +host_mem_usage 401408 # Number of bytes of host memory used +host_seconds 922.06 # Real time elapsed on the host sim_insts 60305560 # Number of instructions simulated sim_ops 77596391 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory @@ -440,6 +428,18 @@ system.physmem.writeRowHits 94229 # Nu system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes system.physmem.avgGap 158662.04 # Average gap between requests +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.membus.throughput 54917647 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 16149440 # Transaction distribution system.membus.trans_dist::ReadResp 16149440 # Transaction distribution @@ -713,8 +713,8 @@ system.cpu.rename.LSQFullEvents 4066422 # Nu system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 466885287 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90688 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 432104229 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10389 # Number of floating rename lookups system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index 843df146b..c314ac71a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -25,7 +25,7 @@ load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -347,6 +347,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index d806d7d51..7de6a94c3 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 09:26:23 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:10:22 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 9d62fc018..2afd1181d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -4,13 +4,25 @@ sim_seconds 2.403596 # Nu sim_ticks 2403595690000 # Number of ticks simulated final_tick 2403595690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160402 # Simulator instruction rate (inst/s) -host_op_rate 206018 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6390741250 # Simulator tick rate (ticks/s) -host_mem_usage 398660 # Number of bytes of host memory used -host_seconds 376.11 # Real time elapsed on the host +host_inst_rate 196358 # Simulator instruction rate (inst/s) +host_op_rate 252199 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7823307249 # Simulator tick rate (ticks/s) +host_mem_usage 401444 # Number of bytes of host memory used +host_seconds 307.24 # Real time elapsed on the host sim_insts 60328186 # Number of instructions simulated sim_ops 77484426 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory @@ -360,18 +372,6 @@ system.physmem.writeRowHits 40077 # Nu system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate 8.98 # Row buffer hit rate for writes system.physmem.avgGap 172524.57 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.membus.throughput 55673401 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 13817014 # Transaction distribution system.membus.trans_dist::ReadResp 13817014 # Transaction distribution @@ -1617,8 +1617,8 @@ system.cpu2.rename.LSQFullEvents 890462 # Nu system.cpu2.rename.FullRegisterEvents 131 # Number of times there has been no free registers system.cpu2.rename.RenamedOperands 37304234 # Number of destination operands rename has renamed system.cpu2.rename.RenameLookups 159387361 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 159360013 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27348 # Number of floating rename lookups +system.cpu2.rename.int_rename_lookups 148242103 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3218 # Number of floating rename lookups system.cpu2.rename.CommittedMaps 26430435 # Number of HB maps that are committed system.cpu2.rename.UndoneMaps 10873798 # Number of HB maps that are undone due to squashing system.cpu2.rename.serializingInsts 231762 # count of serializing insts renamed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 7b9011e3a..0865afb47 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -127,6 +127,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 @@ -602,6 +603,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout index 5ab09214a..e9eaa0c70 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 09:05:36 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:34:20 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 62d3d2d33..b715fd89b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.548576 # Nu sim_ticks 2548576209000 # Number of ticks simulated final_tick 2548576209000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60580 # Simulator instruction rate (inst/s) -host_op_rate 77951 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2559708219 # Simulator tick rate (ticks/s) -host_mem_usage 399668 # Number of bytes of host memory used -host_seconds 995.65 # Real time elapsed on the host +host_inst_rate 64501 # Simulator instruction rate (inst/s) +host_op_rate 82996 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2725389479 # Simulator tick rate (ticks/s) +host_mem_usage 403492 # Number of bytes of host memory used +host_seconds 935.12 # Real time elapsed on the host sim_insts 60316464 # Number of instructions simulated sim_ops 77611603 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory @@ -1088,8 +1088,8 @@ system.cpu0.rename.LSQFullEvents 2115247 # Nu system.cpu0.rename.FullRegisterEvents 208 # Number of times there has been no free registers system.cpu0.rename.RenamedOperands 52034450 # Number of destination operands rename has renamed system.cpu0.rename.RenameLookups 231667374 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 231623806 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 43568 # Number of floating rename lookups +system.cpu0.rename.int_rename_lookups 214169305 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 4937 # Number of floating rename lookups system.cpu0.rename.CommittedMaps 38251156 # Number of HB maps that are committed system.cpu0.rename.UndoneMaps 13783293 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 411980 # count of serializing insts renamed @@ -1776,8 +1776,8 @@ system.cpu1.rename.LSQFullEvents 2033878 # Nu system.cpu1.rename.FullRegisterEvents 525 # Number of times there has been no free registers system.cpu1.rename.RenamedOperands 54353089 # Number of destination operands rename has renamed system.cpu1.rename.RenameLookups 236755846 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 236708688 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 47158 # Number of floating rename lookups +system.cpu1.rename.int_rename_lookups 219276243 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5446 # Number of floating rename lookups system.cpu1.rename.CommittedMaps 40151278 # Number of HB maps that are committed system.cpu1.rename.UndoneMaps 14201811 # Number of HB maps that are undone due to squashing system.cpu1.rename.serializingInsts 419760 # count of serializing insts renamed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index f7596e329..c0ebf9d4a 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -17,7 +17,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing mem_ranges=0:134217727 @@ -128,6 +128,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=true numIQEntries=64 +numPhysCCRegs=1280 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 @@ -1356,7 +1357,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/andreas/m5/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1376,7 +1377,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/andreas/m5/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index c5fec8887..b43511df7 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 1 2013 21:55:52 -gem5 started Oct 1 2013 22:49:39 -gem5 executing on steam +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:57:32 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5133817564000 because m5_exit instruction encountered +Exiting @ tick 5149801602000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index e1d1abdbc..ded25c3bb 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133818 # Number of seconds simulated -sim_ticks 5133817564000 # Number of ticks simulated -final_tick 5133817564000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.149802 # Number of seconds simulated +sim_ticks 5149801602000 # Number of ticks simulated +final_tick 5149801602000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116267 # Simulator instruction rate (inst/s) -host_op_rate 229827 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1463849171 # Simulator tick rate (ticks/s) -host_mem_usage 730944 # Number of bytes of host memory used -host_seconds 3507.07 # Real time elapsed on the host -sim_insts 407756178 # Number of instructions simulated -sim_ops 806017145 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2427456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1027392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10775296 # Number of bytes read from this memory -system.physmem.bytes_read::total 14234240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1027392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1027392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9523712 # Number of bytes written to this memory -system.physmem.bytes_written::total 9523712 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 37929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 58 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16053 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168364 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222410 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 148808 # Number of write requests responded to by this memory -system.physmem.num_writes::total 148808 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 472836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 723 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 200122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2098886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2772642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 200122 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 200122 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1855094 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1855094 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1855094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 472836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 200122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2098886 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4627736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222410 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 148808 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 222410 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 148808 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 14234240 # Total number of bytes read from memory -system.physmem.bytesWritten 9523712 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 14234240 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 9523712 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 59 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 1680 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 14445 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 13880 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 14292 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 13655 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 13870 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 13478 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 13505 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 14003 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 13721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 13556 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 13489 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 13720 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 14708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 14278 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 14115 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 13636 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 9830 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 9327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 9583 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 9096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 9291 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 8966 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8927 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 9335 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 9016 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 8977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 8994 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 9147 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 9992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 9572 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 9603 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 9152 # Track writes on a per bank basis +host_inst_rate 149544 # Simulator instruction rate (inst/s) +host_op_rate 295611 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1888705545 # Simulator tick rate (ticks/s) +host_mem_usage 733444 # Number of bytes of host memory used +host_seconds 2726.63 # Real time elapsed on the host +sim_insts 407752265 # Number of instructions simulated +sim_ops 806021401 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2464448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1029696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10712000 # Number of bytes read from this memory +system.physmem.bytes_read::total 14210368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1029696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1029696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9492864 # Number of bytes written to this memory +system.physmem.bytes_written::total 9492864 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38507 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16089 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167375 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222037 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148326 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148326 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 478552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199949 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2080080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2759401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199949 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199949 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1843346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1843346 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1843346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 478552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2080080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4602747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222037 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 148326 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 222037 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 148326 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 14210368 # Total number of bytes read from memory +system.physmem.bytesWritten 9492864 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 14210368 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9492864 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 1678 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 14222 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 14028 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 14693 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 13767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 13958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 13755 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 13963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 13415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 13462 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 13512 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 13712 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 14980 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 14150 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 13362 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 13288 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 9612 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 9534 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 9830 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 9200 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 9484 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 9208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 9093 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 9396 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 8748 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 8829 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 9077 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 9138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 10300 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 9366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 8795 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8716 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry -system.physmem.totGap 5133817509500 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry +system.physmem.totGap 5149801548000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 222410 # Categorize read packet sizes +system.physmem.readPktSize::6 222037 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 148808 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 174478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7432 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2034 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1131 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 926 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148326 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 173642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1084 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 947 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 914 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 470 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 745 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -137,342 +137,343 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 6410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 6444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 6447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 6454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 6460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 6460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 6462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 6470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 6470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 6470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 6470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 6470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 6470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62679 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 378.930359 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.401970 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1268.483208 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 27823 44.39% 44.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 9775 15.60% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 5839 9.32% 69.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 3939 6.28% 75.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 2540 4.05% 79.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 2068 3.30% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 1534 2.45% 85.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 1237 1.97% 87.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 969 1.55% 88.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 885 1.41% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 570 0.91% 91.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 566 0.90% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 409 0.65% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 368 0.59% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 359 0.57% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 470 0.75% 94.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 261 0.42% 95.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 223 0.36% 95.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 183 0.29% 95.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 154 0.25% 96.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 153 0.24% 96.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 166 0.26% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 503 0.80% 97.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 192 0.31% 97.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 116 0.19% 97.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 97 0.15% 97.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 69 0.11% 98.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 63 0.10% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 31 0.05% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 26 0.04% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 27 0.04% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 24 0.04% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 21 0.03% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 14 0.02% 98.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 16 0.03% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 18 0.03% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 16 0.03% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 13 0.02% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 7 0.01% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 6 0.01% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 11 0.02% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 6 0.01% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 5 0.01% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 7 0.01% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 8 0.01% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 3 0.00% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 4 0.01% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 4 0.01% 98.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 4 0.01% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 10 0.02% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 4 0.01% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3587 6 0.01% 98.66% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 5426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 6386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 6428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 6433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 6435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 6441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 6443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 6443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 6449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 6449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 6449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 6449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 6449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 6449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62488 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 379.140187 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 154.041653 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1280.875932 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 27817 44.52% 44.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 9622 15.40% 59.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 5951 9.52% 69.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 3940 6.31% 75.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 2520 4.03% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1986 3.18% 82.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 1542 2.47% 85.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 1215 1.94% 87.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 1005 1.61% 88.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 910 1.46% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 598 0.96% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 543 0.87% 92.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 367 0.59% 92.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 364 0.58% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 356 0.57% 94.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 454 0.73% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 284 0.45% 95.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 192 0.31% 95.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 180 0.29% 95.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 146 0.23% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 174 0.28% 96.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 177 0.28% 96.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 484 0.77% 97.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 176 0.28% 97.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 118 0.19% 97.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 94 0.15% 97.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 80 0.13% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 58 0.09% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 28 0.04% 98.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 25 0.04% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 31 0.05% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 34 0.05% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 13 0.02% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 15 0.02% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 10 0.02% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 19 0.03% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 17 0.03% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 8 0.01% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 10 0.02% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 8 0.01% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 4 0.01% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 3 0.00% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 9 0.01% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 5 0.01% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 9 0.01% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 4 0.01% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 3 0.00% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 7 0.01% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 2 0.00% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 3 0.00% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 3 0.00% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 5 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 14 0.02% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 5 0.01% 98.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648-3651 4 0.01% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 2 0.00% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 10 0.02% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 4 0.01% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 2 0.00% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4035 4 0.01% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 25 0.04% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 6 0.01% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 11 0.02% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 3 0.00% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 5 0.01% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 1 0.00% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 21 0.03% 98.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::4160-4163 7 0.01% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 2 0.00% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4291 3 0.00% 98.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 5 0.01% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 2 0.00% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4291 1 0.00% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 4 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 6 0.01% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 3 0.00% 98.79% # Bytes accessed per row activation system.physmem.bytesPerActivate::4544-4547 5 0.01% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 2 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4675 1 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4803 1 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 5 0.01% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4995 2 0.00% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 4 0.01% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 6 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 1 0.00% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5251 2 0.00% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4675 4 0.01% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4931 3 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 4 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 2 0.00% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 3 0.00% 98.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::5312-5315 1 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 1 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5443 2 0.00% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5571 2 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 4 0.01% 98.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::5632-5635 2 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5699 3 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5699 1 0.00% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 98.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5955 1 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5955 2 0.00% 98.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::6016-6019 2 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 5 0.01% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 2 0.00% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 2 0.00% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 2 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 1 0.00% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6339 2 0.00% 98.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 2 0.00% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 2 0.00% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 5 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 3 0.00% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 8 0.01% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 2 0.00% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 1 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 5 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7491 2 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7619 3 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7811 2 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 1 0.00% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 3 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8131 4 0.01% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 340 0.54% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8515 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8899 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 6 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9603 3 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 3 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9923 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10048-10051 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 3 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10563 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12160-12163 2 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13376-13379 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14272-14275 1 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 4 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 32 0.05% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 14 0.02% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 7 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 11 0.02% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 5 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 6 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 4 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 5 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 6 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15619 5 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 9 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15808-15811 3 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 8 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 3 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 8 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 2 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 8 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 6 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 15 0.02% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 9 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 59 0.09% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 2 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 3 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16704-16707 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16960-16963 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17795 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62679 # Bytes accessed per row activation -system.physmem.totQLat 3976321749 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8255787999 # Sum of mem lat for all requests -system.physmem.totBusLat 1111755000 # Total cycles spent in databus access -system.physmem.totBankLat 3167711250 # Total cycles spent in bank access -system.physmem.avgQLat 17883.08 # Average queueing delay per request -system.physmem.avgBankLat 14246.44 # Average bank access latency per request +system.physmem.bytesPerActivate::6464-6467 1 0.00% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 1 0.00% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 6 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 2 0.00% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 7 0.01% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 1 0.00% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 2 0.00% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 2 0.00% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 4 0.01% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7619 2 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7683 2 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7747 1 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 2 0.00% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 2 0.00% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 1 0.00% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 339 0.54% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9347 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9411 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 8 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 3 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9731 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10048-10051 4 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10176-10179 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10243 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10560-10563 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10755 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11200-11203 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11392-11395 2 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12096-12099 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12224-12227 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12352-12355 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12867 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13376-13379 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14144-14147 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14467 3 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 28 0.04% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 15 0.02% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 10 0.02% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 9 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 7 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 4 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 5 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 3 0.00% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15427 5 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 6 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 3 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 4 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 6 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15811 6 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 7 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 6 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 4 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 8 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 6 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 10 0.02% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 12 0.02% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 11 0.02% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 62 0.10% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 3 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16576-16579 3 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17027 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17088-17091 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17219 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62488 # Bytes accessed per row activation +system.physmem.totQLat 4021160000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8281507500 # Sum of mem lat for all requests +system.physmem.totBusLat 1109590000 # Total cycles spent in databus access +system.physmem.totBankLat 3150757500 # Total cycles spent in bank access +system.physmem.avgQLat 18120.03 # Average queueing delay per request +system.physmem.avgBankLat 14197.85 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 37129.53 # Average memory access latency -system.physmem.avgRdBW 2.77 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2.77 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 37317.87 # Average memory access latency +system.physmem.avgRdBW 2.76 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 1.84 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 2.76 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.84 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 11.10 # Average write queue length over time -system.physmem.readRowHits 198876 # Number of row buffer hits during reads -system.physmem.writeRowHits 109583 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.64 # Row buffer hit rate for writes -system.physmem.avgGap 13829656.72 # Average gap between requests -system.membus.throughput 5107370 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662136 # Transaction distribution -system.membus.trans_dist::ReadResp 662131 # Transaction distribution -system.membus.trans_dist::WriteReq 13778 # Transaction distribution -system.membus.trans_dist::WriteResp 13778 # Transaction distribution -system.membus.trans_dist::Writeback 148808 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2204 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1699 # Transaction distribution -system.membus.trans_dist::ReadExReq 179955 # Transaction distribution -system.membus.trans_dist::ReadExResp 179952 # Transaction distribution -system.membus.trans_dist::MessageReq 1643 # Transaction distribution -system.membus.trans_dist::MessageResp 1643 # Transaction distribution -system.membus.trans_dist::BadAddressError 5 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 475656 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1721824 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132231 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 132231 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1857341 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550145 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18343808 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20135781 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5414144 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5414144 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25556497 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25556497 # Total data (bytes) -system.membus.snoop_data_through_bus 663808 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 250614500 # Layer occupancy (ticks) +system.physmem.avgWrQLen 9.63 # Average write queue length over time +system.physmem.readRowHits 198603 # Number of row buffer hits during reads +system.physmem.writeRowHits 109131 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes +system.physmem.avgGap 13904740.88 # Average gap between requests +system.membus.throughput 5073674 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 662109 # Transaction distribution +system.membus.trans_dist::ReadResp 662107 # Transaction distribution +system.membus.trans_dist::WriteReq 13770 # Transaction distribution +system.membus.trans_dist::WriteResp 13770 # Transaction distribution +system.membus.trans_dist::Writeback 148326 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2172 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1696 # Transaction distribution +system.membus.trans_dist::ReadExReq 179020 # Transaction distribution +system.membus.trans_dist::ReadExResp 179014 # Transaction distribution +system.membus.trans_dist::MessageReq 1646 # Transaction distribution +system.membus.trans_dist::MessageResp 1646 # Transaction distribution +system.membus.trans_dist::BadAddressError 2 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775088 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473242 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1719372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132805 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 132805 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1855469 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6584 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 6584 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241802 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550173 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18252032 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20044007 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5451200 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5451200 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 25501791 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 25501791 # Total data (bytes) +system.membus.snoop_data_through_bus 626624 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 250581000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583282500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583304500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3292000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1610621247 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1605050249 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 7000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1646000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3158121946 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3149132971 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429462997 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429400997 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47580 # number of replacements -system.iocache.tags.tagsinuse 0.104004 # Cycle average of tags in use +system.iocache.tags.replacements 47576 # number of replacements +system.iocache.tags.tagsinuse 0.153339 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47596 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992837152000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.104004 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006500 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006500 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 915 # number of ReadReq misses -system.iocache.ReadReq_misses::total 915 # number of ReadReq misses +system.iocache.tags.warmup_cycle 4992838664000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.153339 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.009584 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.009584 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses +system.iocache.ReadReq_misses::total 910 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47635 # number of demand (read+write) misses -system.iocache.demand_misses::total 47635 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47635 # number of overall misses -system.iocache.overall_misses::total 47635 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 155029196 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 155029196 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10272164340 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10272164340 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10427193536 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10427193536 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10427193536 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10427193536 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 915 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47630 # number of demand (read+write) misses +system.iocache.demand_misses::total 47630 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47630 # number of overall misses +system.iocache.overall_misses::total 47630 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152977935 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 152977935 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10361858110 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10361858110 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10514836045 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10514836045 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10514836045 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10514836045 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47635 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47635 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47635 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47635 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47630 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47630 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47630 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47630 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -481,40 +482,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 169430.815301 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 169430.815301 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 219866.531250 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 219866.531250 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 218897.733515 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 218897.733515 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 218897.733515 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 218897.733515 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 145846 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 168107.620879 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 168107.620879 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 221786.346533 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 221786.346533 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 220760.781965 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 220760.781965 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 220760.781965 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 220760.781965 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 148180 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 13667 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 13622 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.671398 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.877991 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46667 # number of writebacks -system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 915 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 915 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46668 # number of writebacks +system.iocache.writebacks::total 46668 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47635 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47635 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47635 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47635 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 107414696 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 107414696 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7841262846 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7841262846 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7948677542 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7948677542 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7948677542 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7948677542 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47630 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47630 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47630 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47630 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105623935 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 105623935 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7930990116 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 7930990116 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8036614051 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8036614051 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8036614051 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8036614051 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -523,18 +524,18 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117393.110383 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 117393.110383 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 167835.249272 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 167835.249272 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 166866.328162 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 166866.328162 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 166866.328162 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 166866.328162 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116070.258242 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 116070.258242 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169755.781592 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 169755.781592 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 168730.087151 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 168730.087151 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 168730.087151 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 168730.087151 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -544,16 +545,16 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 638173 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225571 # Transaction distribution -system.iobus.trans_dist::ReadResp 225571 # Transaction distribution -system.iobus.trans_dist::WriteReq 57606 # Transaction distribution -system.iobus.trans_dist::WriteResp 57606 # Transaction distribution -system.iobus.trans_dist::MessageReq 1643 # Transaction distribution -system.iobus.trans_dist::MessageResp 1643 # Transaction distribution +system.iobus.throughput 636182 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 225558 # Transaction distribution +system.iobus.trans_dist::ReadResp 225558 # Transaction distribution +system.iobus.trans_dist::WriteReq 57591 # Transaction distribution +system.iobus.trans_dist::WriteResp 57591 # Transaction distribution +system.iobus.trans_dist::MessageReq 1646 # Transaction distribution +system.iobus.trans_dist::MessageResp 1646 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -569,15 +570,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95270 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95270 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569640 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471038 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3292 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3292 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569590 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -593,20 +594,20 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027864 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027864 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276264 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3919850 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 241802 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6584 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6584 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 3276210 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3276210 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3927144 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -636,154 +637,153 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 424475539 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424444048 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460167000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53455003 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53407003 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1646000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 85568278 # Number of BP lookups -system.cpu.branchPred.condPredicted 85568278 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 875805 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79194721 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77515005 # Number of BTB hits +system.cpu.branchPred.lookups 85588006 # Number of BP lookups +system.cpu.branchPred.condPredicted 85588006 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 877454 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79215990 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77530840 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.879005 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1436703 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 179530 # Number of incorrect RAS predictions. -system.cpu.numCycles 453826303 # number of cpu cycles simulated +system.cpu.branchPred.BTBHitPct 97.872715 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1437704 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180381 # Number of incorrect RAS predictions. +system.cpu.numCycles 453669464 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25491689 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 422571983 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85568278 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 78951708 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 162597841 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3951278 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 103753 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 71390541 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 42483 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 91488 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 407 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8456173 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 381386 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2285 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 262749158 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.176501 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.411322 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 25482716 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 422686689 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85588006 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 78968544 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 162633276 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3972302 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 106554 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 71193509 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 45334 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 89294 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 278 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8469801 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 382535 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2385 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 262601517 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.178991 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.411463 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 100566215 38.27% 38.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1530086 0.58% 38.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 71818264 27.33% 66.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 889095 0.34% 66.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1565087 0.60% 67.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2386199 0.91% 68.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1016423 0.39% 68.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1323196 0.50% 68.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81654593 31.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 100383881 38.23% 38.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1533037 0.58% 38.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71821115 27.35% 66.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 895642 0.34% 66.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1564995 0.60% 67.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2390879 0.91% 68.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1017520 0.39% 68.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1329446 0.51% 68.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81665002 31.10% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 262749158 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.188549 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.931132 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 29394099 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 68537094 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158445926 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3341083 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3030956 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 832311849 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 975 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3030956 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 32089229 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 43247389 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12548061 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158740332 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13093191 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 829412646 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22400 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6072204 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5134846 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 9895 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 991013941 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1799757815 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1799757415 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 400 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963928798 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27085141 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 453471 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 459839 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 29598553 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 16699186 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 9813003 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1103116 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 919400 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 824665019 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1185670 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820786759 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 149059 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19014850 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 28966021 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 131061 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 262749158 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.123842 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.400884 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 262601517 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.188657 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.931706 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29392698 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 68340203 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158479192 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3338868 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3050556 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 832478930 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 959 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3050556 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 32088006 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 43079490 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 12529275 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158770454 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13083736 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 829577701 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21771 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6064622 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5141489 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 991205554 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1800191267 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1106790785 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 123 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 963930499 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27275048 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 452761 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 458610 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 29575764 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 16714812 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 9817459 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1139197 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 962008 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 824812969 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1184552 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820895267 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 151456 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19155682 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29185416 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 129934 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 262601517 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 3.126011 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.400353 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 76415434 29.08% 29.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15773446 6.00% 35.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10534030 4.01% 39.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7363874 2.80% 41.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 75721487 28.82% 70.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3737655 1.42% 72.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72289188 27.51% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 768072 0.29% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 145972 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 76255592 29.04% 29.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15761044 6.00% 35.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10531368 4.01% 39.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7369443 2.81% 41.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 75730840 28.84% 70.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3739599 1.42% 72.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72299562 27.53% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 768121 0.29% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 145948 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 262749158 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 262601517 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 347595 33.06% 33.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 241 0.02% 33.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 298 0.03% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 548989 52.22% 85.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 154170 14.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 345012 32.94% 32.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 241 0.02% 32.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 974 0.09% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 547730 52.30% 85.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 153356 14.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 308427 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 793336759 96.66% 96.69% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 307746 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 793434579 96.65% 96.69% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 149572 0.02% 96.71% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 124334 0.02% 96.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 124688 0.02% 96.73% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.73% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.73% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.73% # Type of FU issued @@ -810,281 +810,283 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.73% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.73% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.73% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 17650951 2.15% 98.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9216716 1.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 17663300 2.15% 98.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9215382 1.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820786759 # Type of FU issued -system.cpu.iq.rate 1.808592 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1051293 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001281 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1905631270 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 844875947 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 816895262 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 170 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 48 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 821529545 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 80 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1693324 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820895267 # Type of FU issued +system.cpu.iq.rate 1.809457 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1047313 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001276 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1905699959 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 845163637 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 816985295 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 199 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 821634741 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1691465 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2710358 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18596 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11994 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1389490 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2728859 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17017 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11975 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1400009 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1931520 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 12323 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1931860 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 12243 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3030956 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 31365465 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2153394 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 825850689 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 245046 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 16699186 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 9813003 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 690244 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1620381 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14551 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11994 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 492991 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506844 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 999835 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819394540 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17351060 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1392218 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3050556 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 31208951 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2150350 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 825997521 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 243405 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 16714812 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 9817459 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 689575 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1619766 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13837 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11975 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 493977 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 506066 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1000043 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819488058 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17361171 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1407208 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26384270 # number of memory reference insts executed -system.cpu.iew.exec_branches 83073397 # Number of branches executed -system.cpu.iew.exec_stores 9033210 # Number of stores executed -system.cpu.iew.exec_rate 1.805525 # Inst execution rate -system.cpu.iew.wb_sent 818994723 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 816895310 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638461899 # num instructions producing a value -system.cpu.iew.wb_consumers 1043741013 # num instructions consuming a value +system.cpu.iew.exec_refs 26390625 # number of memory reference insts executed +system.cpu.iew.exec_branches 83079645 # Number of branches executed +system.cpu.iew.exec_stores 9029454 # Number of stores executed +system.cpu.iew.exec_rate 1.806355 # Inst execution rate +system.cpu.iew.wb_sent 819086222 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 816985349 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638544896 # num instructions producing a value +system.cpu.iew.wb_consumers 1043866074 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.800018 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611705 # average fanout of values written-back +system.cpu.iew.wb_rate 1.800838 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611712 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19724455 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1054609 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 885977 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 259718202 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.103430 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.863863 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 19867682 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1054616 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 887449 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 259550960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.105446 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.863698 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 88192844 33.96% 33.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11850002 4.56% 38.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3832476 1.48% 40.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74743456 28.78% 68.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2382743 0.92% 69.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1477125 0.57% 70.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 857323 0.33% 70.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70846576 27.28% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5535657 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 88027122 33.92% 33.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11847553 4.56% 38.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3827434 1.47% 39.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74752127 28.80% 68.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2379438 0.92% 69.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1475953 0.57% 70.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 857436 0.33% 70.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70850710 27.30% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5533187 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 259718202 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407756178 # Number of instructions committed -system.cpu.commit.committedOps 806017145 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 259550960 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407752265 # Number of instructions committed +system.cpu.commit.committedOps 806021401 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22412340 # Number of memory references committed -system.cpu.commit.loads 13988827 # Number of loads committed -system.cpu.commit.membars 474703 # Number of memory barriers committed -system.cpu.commit.branches 82157257 # Number of branches committed +system.cpu.commit.refs 22403400 # Number of memory references committed +system.cpu.commit.loads 13985950 # Number of loads committed +system.cpu.commit.membars 474657 # Number of memory barriers committed +system.cpu.commit.branches 82156128 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735004802 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155200 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5535657 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 734862948 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155170 # Number of function calls committed. +system.cpu.commit.bw_lim_events 5533187 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1079845864 # The number of ROB reads -system.cpu.rob.rob_writes 1654528920 # The number of ROB writes -system.cpu.timesIdled 1259880 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 191077145 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9813814465 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407756178 # Number of Instructions Simulated -system.cpu.committedOps 806017145 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 407756178 # Number of Instructions Simulated -system.cpu.cpi 1.112984 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.112984 # CPI: Total CPI of All Threads -system.cpu.ipc 0.898485 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.898485 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1504160790 # number of integer regfile reads -system.cpu.int_regfile_writes 975149499 # number of integer regfile writes -system.cpu.fp_regfile_reads 48 # number of floating regfile reads -system.cpu.misc_regfile_reads 263996873 # number of misc regfile reads -system.cpu.misc_regfile_writes 402343 # number of misc regfile writes -system.cpu.toL2Bus.throughput 53588361 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3012770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3012220 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13778 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13778 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1579976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2276 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2276 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 334451 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287744 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 5 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1911499 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6119032 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 17478 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 153515 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8201524 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61164352 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207421989 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 548096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5363392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 274497829 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 274473317 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 639552 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4034739870 # Layer occupancy (ticks) +system.cpu.rob.rob_reads 1079828496 # The number of ROB reads +system.cpu.rob.rob_writes 1654843441 # The number of ROB writes +system.cpu.timesIdled 1258915 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 191067947 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9845938983 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407752265 # Number of Instructions Simulated +system.cpu.committedOps 806021401 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 407752265 # Number of Instructions Simulated +system.cpu.cpi 1.112611 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.112611 # CPI: Total CPI of All Threads +system.cpu.ipc 0.898787 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.898787 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1088694796 # number of integer regfile reads +system.cpu.int_regfile_writes 653771353 # number of integer regfile writes +system.cpu.fp_regfile_reads 54 # number of floating regfile reads +system.cpu.cc_regfile_reads 415601025 # number of cc regfile reads +system.cpu.cc_regfile_writes 321483560 # number of cc regfile writes +system.cpu.misc_regfile_reads 264032145 # number of misc regfile reads +system.cpu.misc_regfile_writes 402444 # number of misc regfile writes +system.cpu.toL2Bus.throughput 53392020 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3013693 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3013151 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13770 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13770 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1577044 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2235 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2235 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 334035 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287322 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1908198 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121437 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18680 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 151603 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8199918 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61058944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207524391 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 566848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5217216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 274367399 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 274343271 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 615040 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4030545417 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 574500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 565500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1437663197 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1435258580 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3140492264 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3141587747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 13374496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 14741736 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 104626155 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 105191645 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 955225 # number of replacements -system.cpu.icache.tags.tagsinuse 509.955368 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7446917 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 955737 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.791806 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147479365250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.955368 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996007 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996007 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 7446917 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7446917 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7446917 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7446917 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7446917 # number of overall hits -system.cpu.icache.overall_hits::total 7446917 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1009251 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1009251 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1009251 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1009251 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1009251 # number of overall misses -system.cpu.icache.overall_misses::total 1009251 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14258935392 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14258935392 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14258935392 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14258935392 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14258935392 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14258935392 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8456168 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8456168 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8456168 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8456168 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8456168 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8456168 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119351 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.119351 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.119351 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.119351 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.119351 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.119351 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14128.235089 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14128.235089 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14128.235089 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14128.235089 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14128.235089 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14128.235089 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6628 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 229 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.943231 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.tags.replacements 953576 # number of replacements +system.cpu.icache.tags.tagsinuse 510.036469 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7463561 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 954088 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.822718 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147479259250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.036469 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996165 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996165 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 7463561 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7463561 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7463561 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7463561 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7463561 # number of overall hits +system.cpu.icache.overall_hits::total 7463561 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1006237 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1006237 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1006237 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1006237 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1006237 # number of overall misses +system.cpu.icache.overall_misses::total 1006237 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14239259264 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14239259264 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14239259264 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14239259264 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14239259264 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14239259264 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8469798 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8469798 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8469798 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8469798 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8469798 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8469798 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118803 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.118803 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.118803 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.118803 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.118803 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.118803 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14150.999480 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14150.999480 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14150.999480 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14150.999480 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14150.999480 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14150.999480 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7035 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 587 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 207 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 33.985507 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 587 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53445 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 53445 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 53445 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 53445 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 53445 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 53445 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 955806 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 955806 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 955806 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 955806 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 955806 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 955806 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11762227547 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11762227547 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11762227547 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11762227547 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11762227547 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11762227547 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.113031 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.113031 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.113031 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.113031 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.113031 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.113031 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12306.082560 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12306.082560 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12306.082560 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12306.082560 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12306.082560 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12306.082560 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52085 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 52085 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 52085 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 52085 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 52085 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 52085 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 954152 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 954152 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 954152 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 954152 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 954152 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 954152 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11748055164 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11748055164 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11748055164 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11748055164 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11748055164 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11748055164 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.112653 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.112653 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.112653 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.112653 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.112653 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.112653 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12312.561483 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12312.561483 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12312.561483 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12312.561483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12312.561483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12312.561483 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 8028 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.311146 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 21788 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 8039 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.710287 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5106556199500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.311146 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.394447 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.394447 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 21802 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 21802 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 8937 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.031585 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 20273 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 8949 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.265393 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5104907998500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.031585 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376974 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.376974 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20288 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 20288 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 21804 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 21804 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 21804 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 21804 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 8914 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 8914 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 8914 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 8914 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 8914 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 8914 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 98082749 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 98082749 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 98082749 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 98082749 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 98082749 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 98082749 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30716 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 30716 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 20290 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 20290 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 20290 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 20290 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 9823 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 9823 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 9823 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 9823 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 9823 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 9823 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 106143491 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 106143491 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 106143491 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 106143491 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 106143491 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 106143491 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 30111 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 30111 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30718 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 30718 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30718 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 30718 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.290207 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.290207 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.290188 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.290188 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.290188 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.290188 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11003.225151 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11003.225151 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11003.225151 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11003.225151 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11003.225151 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11003.225151 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 30113 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 30113 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 30113 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 30113 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.326226 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.326226 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.326205 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.326205 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.326205 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.326205 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10805.608368 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10805.608368 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10805.608368 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10805.608368 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10805.608368 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10805.608368 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1093,78 +1095,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1772 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1772 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 8914 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 8914 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 8914 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 8914 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 8914 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 80247757 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 80247757 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 80247757 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 80247757 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 80247757 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 80247757 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.290207 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.290207 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.290188 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.290188 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.290188 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.290188 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9002.440767 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9002.440767 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9002.440767 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9002.440767 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9002.440767 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9002.440767 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1536 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1536 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 9823 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 9823 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 9823 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 9823 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 9823 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 9823 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 86483019 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 86483019 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 86483019 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 86483019 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 86483019 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 86483019 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.326226 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.326226 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.326205 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.326205 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.326205 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.326205 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8804.135091 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8804.135091 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8804.135091 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8804.135091 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8804.135091 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8804.135091 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 68638 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 13.809611 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 91506 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 68653 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.332877 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5104119753500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 13.809611 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.863101 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.863101 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 91510 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 91510 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 91510 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 91510 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 91510 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 91510 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 69712 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 69712 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 69712 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 69712 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 69712 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 69712 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 854471475 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 854471475 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 854471475 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 854471475 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 854471475 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 854471475 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 161222 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 161222 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 161222 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 161222 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 161222 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 161222 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.432398 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.432398 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.432398 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.432398 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.432398 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.432398 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12257.164835 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12257.164835 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12257.164835 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12257.164835 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12257.164835 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12257.164835 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 69051 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 14.904441 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 92410 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 69067 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.337976 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 4994136871250 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.904441 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.931528 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.931528 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 92410 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 92410 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 92410 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 92410 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 92410 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 92410 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 70084 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 70084 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 70084 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 70084 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 70084 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 70084 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 863900211 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 863900211 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 863900211 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 863900211 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 863900211 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 863900211 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 162494 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 162494 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 162494 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 162494 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 162494 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 162494 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.431302 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.431302 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.431302 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.431302 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.431302 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.431302 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12326.639618 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12326.639618 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12326.639618 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12326.639618 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12326.639618 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12326.639618 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1173,146 +1175,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 20719 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 20719 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 69712 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 69712 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 69712 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 69712 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 69712 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 69712 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 714931165 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 714931165 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 714931165 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 714931165 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 714931165 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 714931165 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.432398 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.432398 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.432398 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.432398 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.432398 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.432398 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10255.496399 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10255.496399 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10255.496399 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10255.496399 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10255.496399 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10255.496399 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 17433 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 17433 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 70084 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 70084 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 70084 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 70084 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 70084 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 70084 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 723600921 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 723600921 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 723600921 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 723600921 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 723600921 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 723600921 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.431302 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.431302 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.431302 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.431302 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.431302 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.431302 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10324.766295 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10324.766295 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10324.766295 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10324.766295 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1655321 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.993756 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18976383 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1655833 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.460324 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1656223 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.995363 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18981681 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1656735 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.457283 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 38296250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.993756 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10875506 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10875506 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8098167 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8098167 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 18973673 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18973673 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18973673 # number of overall hits -system.cpu.dcache.overall_hits::total 18973673 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2232931 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2232931 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315791 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315791 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2548722 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2548722 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2548722 # number of overall misses -system.cpu.dcache.overall_misses::total 2548722 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33105603008 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33105603008 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12178134710 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12178134710 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45283737718 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45283737718 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45283737718 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45283737718 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13108437 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13108437 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8413958 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8413958 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21522395 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21522395 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21522395 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21522395 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170343 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.170343 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037532 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037532 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118422 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118422 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118422 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118422 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14826.075238 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14826.075238 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38563.906856 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38563.906856 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17767.233036 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17767.233036 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17767.233036 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17767.233036 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 397899 # number of cycles access was blocked +system.cpu.dcache.tags.occ_blocks::cpu.data 511.995363 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 10886449 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10886449 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8092566 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8092566 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 18979015 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18979015 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18979015 # number of overall hits +system.cpu.dcache.overall_hits::total 18979015 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2233485 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2233485 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315362 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315362 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2548847 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2548847 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2548847 # number of overall misses +system.cpu.dcache.overall_misses::total 2548847 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33146878091 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33146878091 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12110851955 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12110851955 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45257730046 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45257730046 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45257730046 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45257730046 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13119934 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13119934 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8407928 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8407928 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21527862 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21527862 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21527862 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21527862 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.170236 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.170236 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037508 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037508 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.118398 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.118398 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118398 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118398 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14840.877862 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14840.877862 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38403.016074 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38403.016074 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17756.157998 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17756.157998 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17756.157998 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17756.157998 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 397029 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42056 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42211 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.461171 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.405818 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1557485 # number of writebacks -system.cpu.dcache.writebacks::total 1557485 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 864709 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 864709 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25884 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 25884 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 890593 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 890593 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 890593 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 890593 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1368222 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1368222 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289907 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289907 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1658129 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1658129 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1658129 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1658129 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17890826726 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17890826726 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11280486479 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11280486479 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29171313205 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29171313205 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29171313205 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29171313205 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364618000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364618000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538596500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538596500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903214500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903214500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104377 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104377 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034455 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034455 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077042 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077042 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077042 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077042 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13075.967735 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13075.967735 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38910.707499 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38910.707499 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17592.909360 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17592.909360 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17592.909360 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17592.909360 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1558075 # number of writebacks +system.cpu.dcache.writebacks::total 1558075 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 863964 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 863964 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25903 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 25903 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 889867 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 889867 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 889867 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 889867 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1369521 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1369521 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289459 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289459 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1658980 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1658980 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1658980 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1658980 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17890697467 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17890697467 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11213904776 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11213904776 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29104602243 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29104602243 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29104602243 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29104602243 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97363389500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97363389500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537212500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537212500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99900602000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99900602000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.104385 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.104385 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034427 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034427 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077062 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077062 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077062 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077062 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13063.470708 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13063.470708 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38740.908992 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38740.908992 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17543.672765 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17543.672765 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17543.672765 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17543.672765 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1320,141 +1322,141 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111515 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64833.541766 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3779668 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175596 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.524796 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 111030 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64826.472459 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3778684 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.568570 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50736.164769 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.333778 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.436924 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3104.326837 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10979.279458 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.774172 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000203 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047368 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.167531 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989281 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 63026 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 6786 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 939635 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1331578 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2341025 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1579976 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1579976 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 330 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 330 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 154233 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 154233 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 63026 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 6786 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 939635 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1485811 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2495258 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 63026 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 6786 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 939635 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1485811 # number of overall hits -system.cpu.l2cache.overall_hits::total 2495258 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 58 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16058 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 35805 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 51927 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1441 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1441 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133490 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133490 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 58 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16058 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169295 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 185417 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 58 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16058 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169295 # number of overall misses -system.cpu.l2cache.overall_misses::total 185417 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6074750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 507000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1388421484 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3011977215 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4406980449 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17718298 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 17718298 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9403560917 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9403560917 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6074750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 507000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1388421484 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12415538132 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13810541366 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6074750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 507000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1388421484 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12415538132 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13810541366 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 63084 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 6792 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 955693 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1367383 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2392952 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1579976 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1579976 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1771 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1771 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 287723 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 287723 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 63084 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 6792 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 955693 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1655106 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2680675 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 63084 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 6792 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 955693 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1655106 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2680675 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000919 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000883 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016802 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026185 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021700 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.813665 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.813665 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463953 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.463953 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000919 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000883 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016802 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102287 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.069168 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000919 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000883 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016802 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102287 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.069168 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 104737.068966 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 84500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86462.914684 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84121.692920 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 84868.766711 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12295.834837 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12295.834837 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70443.935254 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70443.935254 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 104737.068966 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 84500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86462.914684 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73336.708893 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74483.684700 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 104737.068966 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 84500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86462.914684 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73336.708893 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74483.684700 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 50681.739726 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 13.389473 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.126360 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3154.839076 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10976.377823 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.773342 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000204 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048139 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.167486 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989173 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64025 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7316 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 937955 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1333061 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2342357 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1577044 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1577044 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 316 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 316 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 154757 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 154757 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 64025 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 7316 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 937955 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1487818 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2497114 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 64025 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 7316 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 937955 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1487818 # number of overall hits +system.cpu.l2cache.overall_hits::total 2497114 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 16091 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 35754 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 51911 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1443 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1443 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 132547 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 132547 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 61 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 16091 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 168301 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 184458 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 61 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 16091 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 168301 # number of overall misses +system.cpu.l2cache.overall_misses::total 184458 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5633750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 417750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1393223986 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2996305709 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 4395581195 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16716837 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 16716837 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9332768700 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9332768700 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5633750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 417750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1393223986 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12329074409 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13728349895 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5633750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 417750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1393223986 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12329074409 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13728349895 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 64086 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 7321 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 954046 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1368815 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2394268 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1577044 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1577044 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1759 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1759 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 287304 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 287304 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 64086 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 7321 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 954046 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1656119 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2681572 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 64086 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 7321 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 954046 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1656119 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2681572 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000952 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000683 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016866 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026120 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021681 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.820352 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.820352 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461348 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.461348 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000952 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000683 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016866 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.101624 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.068787 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000952 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000683 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016866 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.101624 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.068787 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 92356.557377 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83550 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 86584.052327 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83803.370504 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 84675.332685 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11584.779626 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11584.779626 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70411.014206 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70411.014206 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 92356.557377 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83550 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86584.052327 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73256.097165 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74425.342869 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 92356.557377 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83550 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86584.052327 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73256.097165 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74425.342869 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1463,99 +1465,99 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 102141 # number of writebacks -system.cpu.l2cache.writebacks::total 102141 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 58 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16053 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35803 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 51920 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1441 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1441 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133490 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133490 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 58 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16053 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 169293 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 185410 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 58 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16053 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 169293 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 185410 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5335250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 430000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1185393516 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2560977283 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3752136049 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15491421 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15491421 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7726929083 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7726929083 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5335250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 430000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1185393516 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10287906366 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11479065132 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5335250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 430000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1185393516 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10287906366 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11479065132 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251391500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251391500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2372712000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2372712000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624103500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624103500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000919 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000883 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016797 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026184 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021697 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.813665 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.813665 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463953 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463953 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000919 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000883 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016797 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102285 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.069165 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000919 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000883 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016797 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102285 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.069165 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 91987.068966 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73842.491497 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71529.684188 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72267.643471 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10750.465649 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10750.465649 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57883.954476 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57883.954476 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 91987.068966 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73842.491497 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60769.827258 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61911.790799 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 91987.068966 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71666.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73842.491497 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60769.827258 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61911.790799 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 101658 # number of writebacks +system.cpu.l2cache.writebacks::total 101658 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 3 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 61 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16089 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35751 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 51906 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1443 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1443 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132547 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 132547 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 61 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16089 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 168298 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 184453 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 61 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16089 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 168298 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 184453 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4857750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 353750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1189838014 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2545516291 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3740565805 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15357924 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15357924 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7668131300 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7668131300 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4857750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 353750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1189838014 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10213647591 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11408697105 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4857750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 353750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1189838014 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10213647591 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11408697105 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89250267000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89250267000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2371416000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2371416000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91621683000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91621683000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000952 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000683 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016864 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026118 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021679 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.820352 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.820352 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461348 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000952 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000683 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016864 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101622 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068785 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000952 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000683 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016864 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101622 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068785 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 79635.245902 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73953.509479 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71201.261251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72064.227739 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10643.051975 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10643.051975 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57852.167910 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57852.167910 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 79635.245902 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73953.509479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60687.872649 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61851.512879 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 79635.245902 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73953.509479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60687.872649 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61851.512879 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini index e645b1548..b553a1c5b 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini @@ -220,8 +220,8 @@ voltage_domain=system.voltage_domain [system.e820_table] type=X86E820Table -children=entries0 entries1 entries2 -entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 +children=entries0 entries1 entries2 entries3 +entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3 [system.e820_table.entries0] type=X86E820Entry @@ -241,6 +241,12 @@ addr=1048576 range_type=1 size=133169152 +[system.e820_table.entries3] +type=X86E820Entry +addr=4294901760 +range_type=2 +size=65536 + [system.intel_mp_pointer] type=X86IntelMPFloatingPointer default_config=0 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats index e925af082..6473a5fed 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -1,57 +1,42 @@ -Real time: Sep/22/2013 07:54:54 Profiler Stats -------------- -Elapsed_time_in_seconds: 689 -Elapsed_time_in_minutes: 11.4833 -Elapsed_time_in_hours: 0.191389 -Elapsed_time_in_days: 0.00797454 - -Virtual_time_in_seconds: 688.52 -Virtual_time_in_minutes: 11.4753 -Virtual_time_in_hours: 0.191256 -Virtual_time_in_days: 0.00796898 - -Ruby_current_time: 10608810122 +Ruby_current_time: 10608984467 Ruby_start_time: 0 -Ruby_cycles: 10608810122 - -mbytes_resident: 589.816 -mbytes_total: 810.262 -resident_ratio: 0.727933 +Ruby_cycles: 10608984467 Busy Controller Counts: L1Cache-0:10 L1Cache-1:9 -L2Cache-0:0 +L2Cache-0:1 Directory-0:0 DMA-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154826690 average: 1.00012 | standard deviation: 0.0109671 | 0 154808066 18624 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154865725 average: 1.00012 | standard deviation: 0.0109654 | 0 154847102 18623 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -latency: [binsize: 8 max: 146 count: 154826689 average: 3.40667 | standard deviation: 3.89546 | 152128107 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88161 4467 160 159 697 95 ] -latency: LD: [binsize: 8 max: 145 count: 15355330 average: 5.00367 | standard deviation: 7.16019 | 13922963 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20231 1016 49 23 146 37 ] -latency: ST: [binsize: 8 max: 146 count: 9754590 average: 4.6097 | standard deviation: 10.5962 | 9399926 0 199287 31109 53 1 0 0 0 62468 1144 36 142 56433 3258 93 112 471 57 ] -latency: IFETCH: [binsize: 8 max: 145 count: 128502469 average: 3.10882 | standard deviation: 1.62805 | 127704898 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 18 23 76 1 ] -latency: RMW_Read: [binsize: 8 max: 143 count: 526560 average: 6.05821 | standard deviation: 8.42496 | 454441 0 43162 27521 11 1 0 0 0 999 18 2 4 371 26 0 1 3 ] -latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 343870 average: 5.61917 | standard deviation: 7.40449 | 302009 0 23952 17563 31 0 0 0 0 170 2 0 1 134 7 0 0 1 ] -latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343870 average: 3 | standard deviation: 0 | 0 0 0 343870 ] -hit latency: [binsize: 1 max: 3 count: 152128107 average: 3 | standard deviation: 0 | 0 0 0 152128107 ] -hit latency: LD: [binsize: 1 max: 3 count: 13922963 average: 3 | standard deviation: 0 | 0 0 0 13922963 ] -hit latency: ST: [binsize: 1 max: 3 count: 9399926 average: 3 | standard deviation: 0 | 0 0 0 9399926 ] -hit latency: IFETCH: [binsize: 1 max: 3 count: 127704898 average: 3 | standard deviation: 0 | 0 0 0 127704898 ] -hit latency: RMW_Read: [binsize: 1 max: 3 count: 454441 average: 3 | standard deviation: 0 | 0 0 0 454441 ] -hit latency: Locked_RMW_Read: [binsize: 1 max: 3 count: 302009 average: 3 | standard deviation: 0 | 0 0 0 302009 ] -hit latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343870 average: 3 | standard deviation: 0 | 0 0 0 343870 ] -miss latency: [binsize: 8 max: 146 count: 2698582 average: 26.332 | standard deviation: 18.3228 | 0 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88161 4467 160 159 697 95 ] -miss latency: LD: [binsize: 8 max: 145 count: 1432367 average: 24.4798 | standard deviation: 11.4571 | 0 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20231 1016 49 23 146 37 ] -miss latency: ST: [binsize: 8 max: 146 count: 354664 average: 47.2728 | standard deviation: 34.6308 | 0 0 199287 31109 53 1 0 0 0 62468 1144 36 142 56433 3258 93 112 471 57 ] -miss latency: IFETCH: [binsize: 8 max: 145 count: 797571 average: 20.5323 | standard deviation: 11.026 | 0 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 18 23 76 1 ] -miss latency: RMW_Read: [binsize: 8 max: 143 count: 72119 average: 25.3288 | standard deviation: 9.37846 | 0 0 43162 27521 11 1 0 0 0 999 18 2 4 371 26 0 1 3 ] -miss latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 41861 average: 24.5153 | standard deviation: 6.61955 | 0 0 23952 17563 31 0 0 0 0 170 2 0 1 134 7 0 0 1 ] +latency: [binsize: 8 max: 146 count: 154865724 average: 3.40663 | standard deviation: 3.89597 | 152167065 0 2401413 123717 793 1 0 0 0 77289 1392 70 170 88137 4539 155 157 714 112 ] +latency: LD: [binsize: 8 max: 144 count: 15359723 average: 5.00324 | standard deviation: 7.16109 | 13927349 0 1353226 47181 696 0 0 0 0 9514 194 17 27 20186 1048 50 27 160 48 ] +latency: ST: [binsize: 8 max: 146 count: 9756253 average: 4.61012 | standard deviation: 10.5987 | 9401531 0 199293 31091 52 0 0 0 0 62477 1152 44 130 56479 3272 89 110 469 64 ] +latency: IFETCH: [binsize: 8 max: 140 count: 128535441 average: 3.1088 | standard deviation: 1.62806 | 127737856 0 781770 369 6 0 0 0 0 4126 24 8 11 10975 181 16 20 79 ] +latency: RMW_Read: [binsize: 8 max: 140 count: 526545 average: 6.05786 | standard deviation: 8.42243 | 454428 0 43164 27522 7 1 0 0 0 1003 18 1 2 364 31 0 0 4 ] +latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 343881 average: 5.61911 | standard deviation: 7.40549 | 302020 0 23960 17554 32 0 0 0 0 169 4 0 0 133 7 0 0 2 ] +latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343881 average: 3 | standard deviation: 0 | 0 0 0 343881 ] +hit latency: [binsize: 1 max: 3 count: 152167065 average: 3 | standard deviation: 0 | 0 0 0 152167065 ] +hit latency: LD: [binsize: 1 max: 3 count: 13927349 average: 3 | standard deviation: 0 | 0 0 0 13927349 ] +hit latency: ST: [binsize: 1 max: 3 count: 9401531 average: 3 | standard deviation: 0 | 0 0 0 9401531 ] +hit latency: IFETCH: [binsize: 1 max: 3 count: 127737856 average: 3 | standard deviation: 0 | 0 0 0 127737856 ] +hit latency: RMW_Read: [binsize: 1 max: 3 count: 454428 average: 3 | standard deviation: 0 | 0 0 0 454428 ] +hit latency: Locked_RMW_Read: [binsize: 1 max: 3 count: 302020 average: 3 | standard deviation: 0 | 0 0 0 302020 ] +hit latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343881 average: 3 | standard deviation: 0 | 0 0 0 343881 ] +miss latency: [binsize: 8 max: 146 count: 2698659 average: 26.3349 | standard deviation: 18.3306 | 0 0 2401413 123717 793 1 0 0 0 77289 1392 70 170 88137 4539 155 157 714 112 ] +miss latency: LD: [binsize: 8 max: 144 count: 1432374 average: 24.4813 | standard deviation: 11.4669 | 0 0 1353226 47181 696 0 0 0 0 9514 194 17 27 20186 1048 50 27 160 48 ] +miss latency: ST: [binsize: 8 max: 146 count: 354722 average: 47.2848 | standard deviation: 34.6376 | 0 0 199293 31091 52 0 0 0 0 62477 1152 44 130 56479 3272 89 110 469 64 ] +miss latency: IFETCH: [binsize: 8 max: 140 count: 797585 average: 20.5333 | standard deviation: 11.0294 | 0 0 781770 369 6 0 0 0 0 4126 24 8 11 10975 181 16 20 79 ] +miss latency: RMW_Read: [binsize: 8 max: 140 count: 72117 average: 25.3262 | standard deviation: 9.36709 | 0 0 43164 27522 7 1 0 0 0 1003 18 1 2 364 31 0 0 4 ] +miss latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 41861 average: 24.5155 | standard deviation: 6.62905 | 0 0 23960 17554 32 0 0 0 0 169 4 0 0 133 7 0 0 2 ] Request vs. RubySystem State Profile -------------------------------- @@ -60,10 +45,10 @@ Request vs. RubySystem State Profile Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 15 count: 11145866 average: 0.602427 | standard deviation: 1.43356 | 9466902 2991 1616 2582 1666934 2480 317 253 407 1077 12 18 80 196 0 1 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 15 count: 6232784 average: 1.04523 | standard deviation: 1.76212 | 4606142 1096 355 706 1619950 2278 313 251 380 1006 12 18 80 196 0 1 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4782799 average: 0.0411809 | standard deviation: 0.401372 | 4731531 1706 955 1706 46644 155 4 2 27 69 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 130283 average: 0.0224435 | standard deviation: 0.272229 | 129229 189 306 170 340 47 0 0 0 2 ] +Total_delay_cycles: [binsize: 1 max: 15 count: 11146337 average: 0.602409 | standard deviation: 1.43347 | 9467254 3019 1636 2634 1666996 2474 322 244 418 1037 10 19 80 193 0 1 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 15 count: 6232935 average: 1.0452 | standard deviation: 1.76202 | 4606233 1132 350 702 1620005 2287 321 242 393 967 10 19 80 193 0 1 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4783100 average: 0.041195 | standard deviation: 0.40134 | 4731792 1686 982 1765 46636 142 1 2 25 69 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 130302 average: 0.0227472 | standard deviation: 0.27339 | 129229 201 304 167 355 45 0 0 0 1 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr index 6b689ca41..4291cf7c2 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr @@ -3,7 +3,6 @@ warn: Sockets disabled, not accepting terminal connections warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. -warn: instruction 'fxsave' unimplemented warn: x86 cpuid: unknown family 0x8086 warn: instruction 'wbinvd' unimplemented warn: instruction 'wbinvd' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout index 378d964ed..ada852a91 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout -Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:43:05 -gem5 started Sep 22 2013 07:43:21 +gem5 compiled Oct 16 2013 01:55:52 +gem5 started Oct 16 2013 01:57:05 gem5 executing on zizzer command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5304405061000 because m5_exit instruction encountered +Exiting @ tick 5304492233500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index 3b22fc1c2..e0fd581aa 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.304492 # Nu sim_ticks 5304492233500 # Number of ticks simulated final_tick 5304492233500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162344 # Simulator instruction rate (inst/s) -host_op_rate 311496 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7955466900 # Simulator tick rate (ticks/s) -host_mem_usage 830548 # Number of bytes of host memory used -host_seconds 666.77 # Real time elapsed on the host +host_inst_rate 155930 # Simulator instruction rate (inst/s) +host_op_rate 299191 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7641192165 # Simulator tick rate (ticks/s) +host_mem_usage 831032 # Number of bytes of host memory used +host_seconds 694.20 # Real time elapsed on the host sim_insts 108246430 # Number of instructions simulated sim_ops 207697456 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35104 # Number of bytes read from this memory @@ -564,16 +564,18 @@ system.cpu0.numWorkItemsStarted 0 # nu system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 91841555 # Number of instructions committed system.cpu0.committedOps 177241434 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 167241249 # Number of integer alu accesses +system.cpu0.num_int_alu_accesses 167144917 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 2106041 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 16306998 # number of instructions that are conditional controls -system.cpu0.num_int_insts 167241249 # number of integer instructions +system.cpu0.num_int_insts 167144917 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 412874422 # number of times the integer registers were read -system.cpu0.num_int_register_writes 208905412 # number of times the integer registers were written +system.cpu0.num_int_register_reads 315702148 # number of times the integer registers were read +system.cpu0.num_int_register_writes 141403252 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 97172274 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 67502160 # number of times the CC registers were written system.cpu0.num_mem_refs 19838885 # number of memory refs system.cpu0.num_load_insts 12792113 # Number of load instructions system.cpu0.num_store_insts 7046772 # Number of store instructions @@ -588,16 +590,18 @@ system.cpu1.numWorkItemsStarted 0 # nu system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 16404875 # Number of instructions committed system.cpu1.committedOps 30456022 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 29860682 # Number of integer alu accesses +system.cpu1.num_int_alu_accesses 29781645 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 684501 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 2123636 # number of instructions that are conditional controls -system.cpu1.num_int_insts 29860682 # number of integer instructions +system.cpu1.num_int_insts 29781645 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 77387317 # number of times the integer registers were read -system.cpu1.num_int_register_writes 33910763 # number of times the integer registers were written +system.cpu1.num_int_register_reads 60931294 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23868275 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 16456023 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 10042488 # number of times the CC registers were written system.cpu1.num_mem_refs 7344657 # number of memory refs system.cpu1.num_load_insts 4252428 # Number of load instructions system.cpu1.num_store_insts 3092229 # Number of store instructions diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal index 7d0863a29..928f58e3e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal @@ -4,8 +4,9 @@ BIOS-provided physical RAM map: BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)
BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
-end_pfn_map = 32768
-kernel direct mapping tables up to 8000000 @ 8000-a000
+ BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)
+end_pfn_map = 1048576
+kernel direct mapping tables up to 100000000 @ 8000-d000
DMI 2.5 present.
Zone PFN ranges:
DMA 0 -> 4096
@@ -21,9 +22,9 @@ Processor #1 I/O APIC #2 at 0xFEC00000.
Setting APIC routing to flat
Processors: 2
-Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)
+Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)
PERCPU: Allocating 34160 bytes of per cpu data
-Built 1 zonelists. Total pages: 30616
+Built 1 zonelists. Total pages: 30615
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
@@ -34,7 +35,7 @@ console handover: boot [earlyser0] -> real [ttyS0] Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
Checking aperture...
-Memory: 122008k/131072k available (3699k kernel code, 8512k reserved, 1767k data, 248k init)
+Memory: 122004k/131072k available (3699k kernel code, 8516k reserved, 1767k data, 248k init)
Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset
Mount-cache hash table entries: 256
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index e88b54daa..404746deb 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -17,7 +17,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic mem_ranges=0:134217727 @@ -333,6 +333,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=true numIQEntries=64 +numPhysCCRegs=1280 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 @@ -1407,7 +1408,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/andreas/m5/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1427,7 +1428,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/andreas/m5/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout index f6878036a..38a90266b 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full/simout -Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:36:11 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:38:05 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full Global frequency set at 1000000000000 ticks per second @@ -13,17130 +11,17168 @@ info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 1000000000. Starting simulation... switching cpus -info: Entering event queue @ 1000000500. Starting simulation... +info: Entering event queue @ 1000000000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2000000500. Starting simulation... +info: Entering event queue @ 2000000000. Starting simulation... switching cpus -info: Entering event queue @ 2000001500. Starting simulation... +info: Entering event queue @ 2000001000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3000001500. Starting simulation... +info: Entering event queue @ 3000001000. Starting simulation... switching cpus -info: Entering event queue @ 3000012500. Starting simulation... +info: Entering event queue @ 3000009000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4000012500. Starting simulation... +info: Entering event queue @ 4000009000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 5000012500. Starting simulation... +info: Entering event queue @ 5000009000. Starting simulation... switching cpus -info: Entering event queue @ 5000026000. Starting simulation... +info: Entering event queue @ 5000098000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 6000026000. Starting simulation... +info: Entering event queue @ 6000098000. Starting simulation... switching cpus -info: Entering event queue @ 6000200500. Starting simulation... +info: Entering event queue @ 6000272500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 7000200500. Starting simulation... +info: Entering event queue @ 7000272500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 8000200500. Starting simulation... +info: Entering event queue @ 8000272500. Starting simulation... switching cpus -info: Entering event queue @ 8000274000. Starting simulation... +info: Entering event queue @ 8000346000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 9000274000. Starting simulation... +info: Entering event queue @ 9000346000. Starting simulation... switching cpus -info: Entering event queue @ 9000434500. Starting simulation... +info: Entering event queue @ 9000506500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 10000434500. Starting simulation... +info: Entering event queue @ 10000506500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 11000434500. Starting simulation... +info: Entering event queue @ 11000506500. Starting simulation... switching cpus -info: Entering event queue @ 11000508000. Starting simulation... +info: Entering event queue @ 11000580000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 12000508000. Starting simulation... +info: Entering event queue @ 12000580000. Starting simulation... switching cpus -info: Entering event queue @ 12000668500. Starting simulation... +info: Entering event queue @ 12000740500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 13000668500. Starting simulation... +info: Entering event queue @ 13000740500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 14000668500. Starting simulation... +info: Entering event queue @ 14000740500. Starting simulation... switching cpus -info: Entering event queue @ 14000742000. Starting simulation... +info: Entering event queue @ 14000814000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 15000742000. Starting simulation... +info: Entering event queue @ 15000814000. Starting simulation... switching cpus -info: Entering event queue @ 15000902500. Starting simulation... +info: Entering event queue @ 15000974500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 16000902500. Starting simulation... +info: Entering event queue @ 16000974500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 17000902500. Starting simulation... +info: Entering event queue @ 17000974500. Starting simulation... switching cpus -info: Entering event queue @ 17000976000. Starting simulation... +info: Entering event queue @ 17001048000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 18000976000. Starting simulation... +info: Entering event queue @ 18001048000. Starting simulation... switching cpus -info: Entering event queue @ 18001136500. Starting simulation... +info: Entering event queue @ 18001208500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 19001136500. Starting simulation... +info: Entering event queue @ 19001208500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 20001136500. Starting simulation... +info: Entering event queue @ 20001208500. Starting simulation... switching cpus -info: Entering event queue @ 20001210000. Starting simulation... +info: Entering event queue @ 20001282000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 21001210000. Starting simulation... +info: Entering event queue @ 21001282000. Starting simulation... switching cpus -info: Entering event queue @ 21001370500. Starting simulation... +info: Entering event queue @ 21001442500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 22001370500. Starting simulation... +info: Entering event queue @ 22001442500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 23001370500. Starting simulation... +info: Entering event queue @ 23001442500. Starting simulation... switching cpus -info: Entering event queue @ 23001444000. Starting simulation... +info: Entering event queue @ 23001516000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 24001444000. Starting simulation... +info: Entering event queue @ 24001516000. Starting simulation... switching cpus -info: Entering event queue @ 24001604500. Starting simulation... +info: Entering event queue @ 24001676500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 25001604500. Starting simulation... +info: Entering event queue @ 25001676500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 26001604500. Starting simulation... +info: Entering event queue @ 26001676500. Starting simulation... switching cpus -info: Entering event queue @ 26001678000. Starting simulation... +info: Entering event queue @ 26001750000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 27001678000. Starting simulation... +info: Entering event queue @ 27001750000. Starting simulation... switching cpus -info: Entering event queue @ 27001838500. Starting simulation... +info: Entering event queue @ 27001910500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 28001838500. Starting simulation... +info: Entering event queue @ 28001910500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 29001838500. Starting simulation... +info: Entering event queue @ 29001910500. Starting simulation... switching cpus -info: Entering event queue @ 29001912000. Starting simulation... +info: Entering event queue @ 29001984000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 30001912000. Starting simulation... +info: Entering event queue @ 30001984000. Starting simulation... switching cpus -info: Entering event queue @ 30002072500. Starting simulation... +info: Entering event queue @ 30002144500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 31002072500. Starting simulation... +info: Entering event queue @ 31002144500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 32002072500. Starting simulation... +info: Entering event queue @ 32002144500. Starting simulation... switching cpus -info: Entering event queue @ 32002146000. Starting simulation... +info: Entering event queue @ 32002218000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 33002146000. Starting simulation... +info: Entering event queue @ 33002218000. Starting simulation... switching cpus -info: Entering event queue @ 33002306500. Starting simulation... +info: Entering event queue @ 33002378500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 34002306500. Starting simulation... +info: Entering event queue @ 34002378500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 35002306500. Starting simulation... +info: Entering event queue @ 35002378500. Starting simulation... switching cpus -info: Entering event queue @ 35002380000. Starting simulation... +info: Entering event queue @ 35002452000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 36002380000. Starting simulation... +info: Entering event queue @ 36002452000. Starting simulation... switching cpus -info: Entering event queue @ 36002540500. Starting simulation... +info: Entering event queue @ 36002612500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 37002540500. Starting simulation... +info: Entering event queue @ 37002612500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 38002540500. Starting simulation... +info: Entering event queue @ 38002612500. Starting simulation... switching cpus -info: Entering event queue @ 38002614000. Starting simulation... +info: Entering event queue @ 38002686000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 39002614000. Starting simulation... +info: Entering event queue @ 39002686000. Starting simulation... switching cpus -info: Entering event queue @ 39002774500. Starting simulation... +info: Entering event queue @ 39002846500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 40002774500. Starting simulation... +info: Entering event queue @ 40002846500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 41002774500. Starting simulation... +info: Entering event queue @ 41002846500. Starting simulation... switching cpus -info: Entering event queue @ 41002848000. Starting simulation... +info: Entering event queue @ 41002920000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 42002848000. Starting simulation... +info: Entering event queue @ 42002920000. Starting simulation... switching cpus -info: Entering event queue @ 42003008500. Starting simulation... +info: Entering event queue @ 42003080500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 43003008500. Starting simulation... +info: Entering event queue @ 43003080500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 44003008500. Starting simulation... +info: Entering event queue @ 44003080500. Starting simulation... switching cpus -info: Entering event queue @ 44003082000. Starting simulation... +info: Entering event queue @ 44003154000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 45003082000. Starting simulation... +info: Entering event queue @ 45003154000. Starting simulation... switching cpus -info: Entering event queue @ 45003242500. Starting simulation... +info: Entering event queue @ 45003314500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 46003242500. Starting simulation... +info: Entering event queue @ 46003314500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 47003242500. Starting simulation... +info: Entering event queue @ 47003314500. Starting simulation... switching cpus -info: Entering event queue @ 47003316000. Starting simulation... +info: Entering event queue @ 47003388000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 48003316000. Starting simulation... +info: Entering event queue @ 48003388000. Starting simulation... switching cpus -info: Entering event queue @ 48003476500. Starting simulation... +info: Entering event queue @ 48003548500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 49003476500. Starting simulation... +info: Entering event queue @ 49003548500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 50003476500. Starting simulation... +info: Entering event queue @ 50003548500. Starting simulation... switching cpus -info: Entering event queue @ 50003550000. Starting simulation... +info: Entering event queue @ 50003622000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 51003550000. Starting simulation... +info: Entering event queue @ 51003622000. Starting simulation... switching cpus -info: Entering event queue @ 51003710500. Starting simulation... +info: Entering event queue @ 51003782500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 52003710500. Starting simulation... +info: Entering event queue @ 52003782500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 53003710500. Starting simulation... +info: Entering event queue @ 53003782500. Starting simulation... switching cpus -info: Entering event queue @ 53003784000. Starting simulation... +info: Entering event queue @ 53003856000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 54003784000. Starting simulation... +info: Entering event queue @ 54003856000. Starting simulation... switching cpus -info: Entering event queue @ 54003944500. Starting simulation... +info: Entering event queue @ 54004016500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 55003944500. Starting simulation... +info: Entering event queue @ 55004016500. Starting simulation... switching cpus -info: Entering event queue @ 55003945500. Starting simulation... +info: Entering event queue @ 55004017500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 56003945500. Starting simulation... +info: Entering event queue @ 56004017500. Starting simulation... switching cpus -info: Entering event queue @ 56003946000. Starting simulation... +info: Entering event queue @ 56004018000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 57003946000. Starting simulation... +info: Entering event queue @ 57004018000. Starting simulation... switching cpus -info: Entering event queue @ 57004051500. Starting simulation... +info: Entering event queue @ 57004209500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 58004051500. Starting simulation... +info: Entering event queue @ 58004209500. Starting simulation... switching cpus -info: Entering event queue @ 58004052500. Starting simulation... +info: Entering event queue @ 58004210500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 59004052500. Starting simulation... +info: Entering event queue @ 59004210500. Starting simulation... switching cpus -info: Entering event queue @ 59004053000. Starting simulation... +info: Entering event queue @ 59004211000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 60004053000. Starting simulation... +info: Entering event queue @ 60004211000. Starting simulation... switching cpus -info: Entering event queue @ 60004057000. Starting simulation... +info: Entering event queue @ 60004215000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 61004215000. Starting simulation... switching cpus -info: Entering event queue @ 61004057000. Starting simulation... +info: Entering event queue @ 61004215500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 62004057000. Starting simulation... +info: Entering event queue @ 62004215500. Starting simulation... switching cpus -info: Entering event queue @ 62004057500. Starting simulation... +info: Entering event queue @ 62004216000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 63004057500. Starting simulation... +info: Entering event queue @ 63004216000. Starting simulation... switching cpus -info: Entering event queue @ 63004061500. Starting simulation... +info: Entering event queue @ 63004220000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 64004061500. Starting simulation... +info: Entering event queue @ 64004220000. Starting simulation... switching cpus -info: Entering event queue @ 64004062000. Starting simulation... +info: Entering event queue @ 64004221500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 65004062000. Starting simulation... +info: Entering event queue @ 65004221500. Starting simulation... switching cpus -info: Entering event queue @ 65004063000. Starting simulation... +info: Entering event queue @ 65004222000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 66004063000. Starting simulation... +info: Entering event queue @ 66004222000. Starting simulation... switching cpus -info: Entering event queue @ 66004073000. Starting simulation... +info: Entering event queue @ 66004232000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 67004073000. Starting simulation... +info: Entering event queue @ 67004232000. Starting simulation... switching cpus -info: Entering event queue @ 67004073500. Starting simulation... +info: Entering event queue @ 67004232500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 68004073500. Starting simulation... +info: Entering event queue @ 68004232500. Starting simulation... switching cpus -info: Entering event queue @ 68004074000. Starting simulation... +info: Entering event queue @ 68004233000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 69004074000. Starting simulation... +info: Entering event queue @ 69004233000. Starting simulation... switching cpus -info: Entering event queue @ 69004078000. Starting simulation... +info: Entering event queue @ 69004237000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 70004078000. Starting simulation... +info: Entering event queue @ 70004237000. Starting simulation... switching cpus -info: Entering event queue @ 70004078500. Starting simulation... +info: Entering event queue @ 70004238500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 71004078500. Starting simulation... +info: Entering event queue @ 71004238500. Starting simulation... switching cpus -info: Entering event queue @ 71004079000. Starting simulation... +info: Entering event queue @ 71004239000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 72004079000. Starting simulation... +info: Entering event queue @ 72004239000. Starting simulation... switching cpus -info: Entering event queue @ 72004083000. Starting simulation... +info: Entering event queue @ 72004243000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 73004083000. Starting simulation... +info: Entering event queue @ 73004243000. Starting simulation... switching cpus -info: Entering event queue @ 73004084500. Starting simulation... +info: Entering event queue @ 73004244500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 74004084500. Starting simulation... +info: Entering event queue @ 74004244500. Starting simulation... switching cpus -info: Entering event queue @ 74004085000. Starting simulation... +info: Entering event queue @ 74004245000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 75004085000. Starting simulation... +info: Entering event queue @ 75004245000. Starting simulation... switching cpus -info: Entering event queue @ 75004095000. Starting simulation... +info: Entering event queue @ 75004255000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 76004095000. Starting simulation... +info: Entering event queue @ 76004255000. Starting simulation... switching cpus -info: Entering event queue @ 76004096500. Starting simulation... +info: Entering event queue @ 76004256500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 77004096500. Starting simulation... +info: Entering event queue @ 77004256500. Starting simulation... switching cpus -info: Entering event queue @ 77004097000. Starting simulation... +info: Entering event queue @ 77004257000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 78004097000. Starting simulation... +info: Entering event queue @ 78004257000. Starting simulation... switching cpus -info: Entering event queue @ 78004107000. Starting simulation... +info: Entering event queue @ 78004267000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 79004107000. Starting simulation... +info: Entering event queue @ 79004267000. Starting simulation... switching cpus -info: Entering event queue @ 79004107500. Starting simulation... +info: Entering event queue @ 79004267500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 80004107500. Starting simulation... +info: Entering event queue @ 80004267500. Starting simulation... switching cpus -info: Entering event queue @ 80004108000. Starting simulation... +info: Entering event queue @ 80004268000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 81004108000. Starting simulation... +info: Entering event queue @ 81004268000. Starting simulation... switching cpus -info: Entering event queue @ 81004112000. Starting simulation... +info: Entering event queue @ 81004272000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 82004112000. Starting simulation... +info: Entering event queue @ 82004272000. Starting simulation... switching cpus -info: Entering event queue @ 82004112500. Starting simulation... +info: Entering event queue @ 82004273500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 83004112500. Starting simulation... +info: Entering event queue @ 83004273500. Starting simulation... switching cpus -info: Entering event queue @ 83004113000. Starting simulation... +info: Entering event queue @ 83004274000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 84004113000. Starting simulation... +info: Entering event queue @ 84004274000. Starting simulation... switching cpus -info: Entering event queue @ 84004117000. Starting simulation... +info: Entering event queue @ 84004278000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 85004117000. Starting simulation... switching cpus -info: Entering event queue @ 85004117500. Starting simulation... +info: Entering event queue @ 85004278000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 86004117500. Starting simulation... +info: Entering event queue @ 86004278000. Starting simulation... switching cpus -info: Entering event queue @ 86004118000. Starting simulation... +info: Entering event queue @ 86004278500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 87004118000. Starting simulation... +info: Entering event queue @ 87004278500. Starting simulation... switching cpus -info: Entering event queue @ 87004128000. Starting simulation... +info: Entering event queue @ 87004288500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 88004128000. Starting simulation... +info: Entering event queue @ 88004288500. Starting simulation... switching cpus -info: Entering event queue @ 88004128500. Starting simulation... +info: Entering event queue @ 88004289000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 89004128500. Starting simulation... +info: Entering event queue @ 89004289000. Starting simulation... switching cpus -info: Entering event queue @ 89004129500. Starting simulation... +info: Entering event queue @ 89004289500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 90004129500. Starting simulation... +info: Entering event queue @ 90004289500. Starting simulation... switching cpus -info: Entering event queue @ 90004139500. Starting simulation... +info: Entering event queue @ 90004299500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 91004139500. Starting simulation... +info: Entering event queue @ 91004299500. Starting simulation... switching cpus -info: Entering event queue @ 91004141000. Starting simulation... +info: Entering event queue @ 91004300000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 92004141000. Starting simulation... +info: Entering event queue @ 92004300000. Starting simulation... switching cpus -info: Entering event queue @ 92004141500. Starting simulation... +info: Entering event queue @ 92004300500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 93004141500. Starting simulation... +info: Entering event queue @ 93004300500. Starting simulation... switching cpus -info: Entering event queue @ 93004145500. Starting simulation... +info: Entering event queue @ 93004304500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 94004145500. Starting simulation... +info: Entering event queue @ 94004304500. Starting simulation... switching cpus -info: Entering event queue @ 94004147000. Starting simulation... +info: Entering event queue @ 94004305000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 95004147000. Starting simulation... +info: Entering event queue @ 95004305000. Starting simulation... switching cpus -info: Entering event queue @ 95004147500. Starting simulation... +info: Entering event queue @ 95004305500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 96004147500. Starting simulation... +info: Entering event queue @ 96004305500. Starting simulation... switching cpus -info: Entering event queue @ 96004151500. Starting simulation... +info: Entering event queue @ 96004309500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 97004151500. Starting simulation... +info: Entering event queue @ 97004309500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 98004151500. Starting simulation... +info: Entering event queue @ 98004309500. Starting simulation... switching cpus -info: Entering event queue @ 98004216000. Starting simulation... +info: Entering event queue @ 98004317000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 99004216000. Starting simulation... +info: Entering event queue @ 99004317000. Starting simulation... switching cpus -info: Entering event queue @ 99004289500. Starting simulation... +info: Entering event queue @ 99004389500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 100004289500. Starting simulation... +info: Entering event queue @ 100004389500. Starting simulation... switching cpus -info: Entering event queue @ 100004291000. Starting simulation... +info: Entering event queue @ 100004391000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 101004291000. Starting simulation... +info: Entering event queue @ 101004391000. Starting simulation... switching cpus -info: Entering event queue @ 101004324000. Starting simulation... +info: Entering event queue @ 101004424000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 102004324000. Starting simulation... +info: Entering event queue @ 102004424000. Starting simulation... switching cpus -info: Entering event queue @ 102004367500. Starting simulation... +info: Entering event queue @ 102004467500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 103004367500. Starting simulation... +info: Entering event queue @ 103004467500. Starting simulation... switching cpus -info: Entering event queue @ 103004369000. Starting simulation... +info: Entering event queue @ 103004469000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 104004369000. Starting simulation... +info: Entering event queue @ 104004469000. Starting simulation... switching cpus -info: Entering event queue @ 104004402000. Starting simulation... +info: Entering event queue @ 104004502000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 105004402000. Starting simulation... +info: Entering event queue @ 105004502000. Starting simulation... switching cpus -info: Entering event queue @ 105004445500. Starting simulation... +info: Entering event queue @ 105004545500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 106004445500. Starting simulation... +info: Entering event queue @ 106004545500. Starting simulation... switching cpus -info: Entering event queue @ 106004447000. Starting simulation... +info: Entering event queue @ 106004547000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 107004447000. Starting simulation... +info: Entering event queue @ 107004547000. Starting simulation... switching cpus -info: Entering event queue @ 107004480000. Starting simulation... +info: Entering event queue @ 107004580000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 108004480000. Starting simulation... +info: Entering event queue @ 108004580000. Starting simulation... switching cpus -info: Entering event queue @ 108004523500. Starting simulation... +info: Entering event queue @ 108004623500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 109004523500. Starting simulation... +info: Entering event queue @ 109004623500. Starting simulation... switching cpus -info: Entering event queue @ 109004525000. Starting simulation... +info: Entering event queue @ 109004625000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 110004525000. Starting simulation... +info: Entering event queue @ 110004625000. Starting simulation... switching cpus -info: Entering event queue @ 110004558000. Starting simulation... +info: Entering event queue @ 110004658000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 111004558000. Starting simulation... +info: Entering event queue @ 111004658000. Starting simulation... switching cpus -info: Entering event queue @ 111004601500. Starting simulation... +info: Entering event queue @ 111004701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 112004601500. Starting simulation... +info: Entering event queue @ 112004701500. Starting simulation... switching cpus -info: Entering event queue @ 112004603000. Starting simulation... +info: Entering event queue @ 112004703000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 113004603000. Starting simulation... +info: Entering event queue @ 113004703000. Starting simulation... switching cpus -info: Entering event queue @ 113004636000. Starting simulation... +info: Entering event queue @ 113004736000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 114004636000. Starting simulation... +info: Entering event queue @ 114004736000. Starting simulation... switching cpus -info: Entering event queue @ 114004679500. Starting simulation... +info: Entering event queue @ 114004779500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 115004679500. Starting simulation... +info: Entering event queue @ 115004779500. Starting simulation... switching cpus -info: Entering event queue @ 115004681000. Starting simulation... +info: Entering event queue @ 115004781000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 116004681000. Starting simulation... +info: Entering event queue @ 116004781000. Starting simulation... switching cpus -info: Entering event queue @ 116004714000. Starting simulation... +info: Entering event queue @ 116004814000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 117004714000. Starting simulation... +info: Entering event queue @ 117004814000. Starting simulation... switching cpus -info: Entering event queue @ 117004757500. Starting simulation... +info: Entering event queue @ 117004857500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 118004757500. Starting simulation... +info: Entering event queue @ 118004857500. Starting simulation... switching cpus -info: Entering event queue @ 118004759000. Starting simulation... +info: Entering event queue @ 118004859000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 119004759000. Starting simulation... +info: Entering event queue @ 119004859000. Starting simulation... switching cpus -info: Entering event queue @ 119004792000. Starting simulation... +info: Entering event queue @ 119004892000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 120004792000. Starting simulation... +info: Entering event queue @ 120004892000. Starting simulation... switching cpus -info: Entering event queue @ 120004835500. Starting simulation... +info: Entering event queue @ 120004935500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 121004835500. Starting simulation... +info: Entering event queue @ 121004935500. Starting simulation... switching cpus -info: Entering event queue @ 121004837000. Starting simulation... +info: Entering event queue @ 121004937000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 122004837000. Starting simulation... +info: Entering event queue @ 122004937000. Starting simulation... switching cpus -info: Entering event queue @ 122004870000. Starting simulation... +info: Entering event queue @ 122004970000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 123004870000. Starting simulation... +info: Entering event queue @ 123004970000. Starting simulation... switching cpus -info: Entering event queue @ 123004913500. Starting simulation... +info: Entering event queue @ 123005013500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 124004913500. Starting simulation... +info: Entering event queue @ 124005013500. Starting simulation... switching cpus -info: Entering event queue @ 124004915000. Starting simulation... +info: Entering event queue @ 124005015000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 125004915000. Starting simulation... +info: Entering event queue @ 125005015000. Starting simulation... switching cpus -info: Entering event queue @ 125004948000. Starting simulation... +info: Entering event queue @ 125005048000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 126004948000. Starting simulation... +info: Entering event queue @ 126005048000. Starting simulation... switching cpus -info: Entering event queue @ 126004991500. Starting simulation... +info: Entering event queue @ 126005091500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 127004991500. Starting simulation... +info: Entering event queue @ 127005091500. Starting simulation... switching cpus -info: Entering event queue @ 127004993000. Starting simulation... +info: Entering event queue @ 127005093000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 128004993000. Starting simulation... +info: Entering event queue @ 128005093000. Starting simulation... switching cpus -info: Entering event queue @ 128005026000. Starting simulation... +info: Entering event queue @ 128005126000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 129005026000. Starting simulation... +info: Entering event queue @ 129005126000. Starting simulation... switching cpus -info: Entering event queue @ 129005069500. Starting simulation... +info: Entering event queue @ 129005169500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 130005069500. Starting simulation... +info: Entering event queue @ 130005169500. Starting simulation... switching cpus -info: Entering event queue @ 130005071000. Starting simulation... +info: Entering event queue @ 130005171000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 131005071000. Starting simulation... +info: Entering event queue @ 131005171000. Starting simulation... switching cpus -info: Entering event queue @ 131005104000. Starting simulation... +info: Entering event queue @ 131005204000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 132005104000. Starting simulation... +info: Entering event queue @ 132005204000. Starting simulation... switching cpus -info: Entering event queue @ 132005147500. Starting simulation... +info: Entering event queue @ 132005247500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 133005147500. Starting simulation... +info: Entering event queue @ 133005247500. Starting simulation... switching cpus -info: Entering event queue @ 133005149000. Starting simulation... +info: Entering event queue @ 133005249000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 134005149000. Starting simulation... +info: Entering event queue @ 134005249000. Starting simulation... switching cpus -info: Entering event queue @ 134005182000. Starting simulation... +info: Entering event queue @ 134005282000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 135005182000. Starting simulation... +info: Entering event queue @ 135005282000. Starting simulation... switching cpus -info: Entering event queue @ 135005225500. Starting simulation... +info: Entering event queue @ 135005325500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 136005225500. Starting simulation... +info: Entering event queue @ 136005325500. Starting simulation... switching cpus -info: Entering event queue @ 136005227000. Starting simulation... +info: Entering event queue @ 136005327000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 137005227000. Starting simulation... +info: Entering event queue @ 137005327000. Starting simulation... switching cpus -info: Entering event queue @ 137005260000. Starting simulation... +info: Entering event queue @ 137005360000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 138005260000. Starting simulation... +info: Entering event queue @ 138005360000. Starting simulation... switching cpus -info: Entering event queue @ 138005303500. Starting simulation... +info: Entering event queue @ 138005403500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 139005303500. Starting simulation... +info: Entering event queue @ 139005403500. Starting simulation... switching cpus -info: Entering event queue @ 139005305000. Starting simulation... +info: Entering event queue @ 139005405000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 140005305000. Starting simulation... +info: Entering event queue @ 140005405000. Starting simulation... switching cpus -info: Entering event queue @ 140005338000. Starting simulation... +info: Entering event queue @ 140005438000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 141005338000. Starting simulation... +info: Entering event queue @ 141005438000. Starting simulation... switching cpus -info: Entering event queue @ 141005381500. Starting simulation... +info: Entering event queue @ 141005481500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 142005381500. Starting simulation... +info: Entering event queue @ 142005481500. Starting simulation... switching cpus -info: Entering event queue @ 142005383000. Starting simulation... +info: Entering event queue @ 142005483000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 143005383000. Starting simulation... +info: Entering event queue @ 143005483000. Starting simulation... switching cpus -info: Entering event queue @ 143005416000. Starting simulation... +info: Entering event queue @ 143005516000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 144005416000. Starting simulation... +info: Entering event queue @ 144005516000. Starting simulation... switching cpus -info: Entering event queue @ 144005459500. Starting simulation... +info: Entering event queue @ 144005559500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 145005459500. Starting simulation... +info: Entering event queue @ 145005559500. Starting simulation... switching cpus -info: Entering event queue @ 145005461000. Starting simulation... +info: Entering event queue @ 145005561000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 146005461000. Starting simulation... +info: Entering event queue @ 146005561000. Starting simulation... switching cpus -info: Entering event queue @ 146005494000. Starting simulation... +info: Entering event queue @ 146005594000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 147005494000. Starting simulation... +info: Entering event queue @ 147005594000. Starting simulation... switching cpus -info: Entering event queue @ 147005537500. Starting simulation... +info: Entering event queue @ 147005637500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 148005537500. Starting simulation... switching cpus -info: Entering event queue @ 148005538000. Starting simulation... +info: Entering event queue @ 148005637500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 149005538000. Starting simulation... +info: Entering event queue @ 149005637500. Starting simulation... switching cpus -info: Entering event queue @ 149005545500. Starting simulation... +info: Entering event queue @ 149005645000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 150005545500. Starting simulation... +info: Entering event queue @ 150005645000. Starting simulation... +info: Entering event queue @ 150005938000. Starting simulation... switching cpus -info: Entering event queue @ 150005555000. Starting simulation... +info: Entering event queue @ 150005945500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 151005555000. Starting simulation... +info: Entering event queue @ 151005945500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 152005555000. Starting simulation... +info: Entering event queue @ 152005945500. Starting simulation... switching cpus -info: Entering event queue @ 152005562500. Starting simulation... +info: Entering event queue @ 152005953000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 153005562500. Starting simulation... +info: Entering event queue @ 153005953000. Starting simulation... switching cpus -info: Entering event queue @ 155293174000. Starting simulation... +info: Entering event queue @ 155405582000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 156293174000. Starting simulation... +info: Entering event queue @ 156405582000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 157293174000. Starting simulation... +info: Entering event queue @ 157405582000. Starting simulation... switching cpus -info: Entering event queue @ 157293181500. Starting simulation... +info: Entering event queue @ 157405589500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 158293181500. Starting simulation... +info: Entering event queue @ 158405589500. Starting simulation... switching cpus -info: Entering event queue @ 159293125500. Starting simulation... +info: Entering event queue @ 159405533500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 160293125500. Starting simulation... +info: Entering event queue @ 160405533500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 161293125500. Starting simulation... +info: Entering event queue @ 161405533500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 162293125500. Starting simulation... +info: Entering event queue @ 162405533500. Starting simulation... switching cpus -info: Entering event queue @ 163292997500. Starting simulation... +info: Entering event queue @ 163405402000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 164292997500. Starting simulation... +info: Entering event queue @ 164405402000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 165292997500. Starting simulation... +info: Entering event queue @ 165405402000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 166292997500. Starting simulation... +info: Entering event queue @ 166405402000. Starting simulation... switching cpus -info: Entering event queue @ 167292869500. Starting simulation... +info: Entering event queue @ 167405277500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 168292869500. Starting simulation... +info: Entering event queue @ 168405277500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 169292869500. Starting simulation... +info: Entering event queue @ 169405277500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 170292869500. Starting simulation... +info: Entering event queue @ 170405277500. Starting simulation... switching cpus -info: Entering event queue @ 171292741500. Starting simulation... +info: Entering event queue @ 171405149500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 172292741500. Starting simulation... +info: Entering event queue @ 172405149500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 173292741500. Starting simulation... +info: Entering event queue @ 173405149500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 174292741500. Starting simulation... +info: Entering event queue @ 174405149500. Starting simulation... switching cpus -info: Entering event queue @ 175292613500. Starting simulation... +info: Entering event queue @ 175405018000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 176292613500. Starting simulation... +info: Entering event queue @ 176405018000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 177292613500. Starting simulation... +info: Entering event queue @ 177405018000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 178292613500. Starting simulation... +info: Entering event queue @ 178405018000. Starting simulation... switching cpus -info: Entering event queue @ 179292485500. Starting simulation... +info: Entering event queue @ 179404893500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 180292485500. Starting simulation... +info: Entering event queue @ 180404893500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 181292485500. Starting simulation... +info: Entering event queue @ 181404893500. Starting simulation... switching cpus -info: Entering event queue @ 181292493000. Starting simulation... +info: Entering event queue @ 181404901000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 182292493000. Starting simulation... -info: Entering event queue @ 183292357000. Starting simulation... -info: Entering event queue @ 183292358000. Starting simulation... +info: Entering event queue @ 182404901000. Starting simulation... +info: Entering event queue @ 183404700500. Starting simulation... +info: Entering event queue @ 183404701500. Starting simulation... switching cpus -info: Entering event queue @ 183292362500. Starting simulation... +info: Entering event queue @ 183404706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 184292362500. Starting simulation... +info: Entering event queue @ 184404706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 185292362500. Starting simulation... +info: Entering event queue @ 185404706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 186292362500. Starting simulation... +info: Entering event queue @ 186404706000. Starting simulation... switching cpus -info: Entering event queue @ 187292229500. Starting simulation... +info: Entering event queue @ 187404637500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 188292229500. Starting simulation... +info: Entering event queue @ 188404637500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 189292229500. Starting simulation... +info: Entering event queue @ 189404637500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 190292229500. Starting simulation... +info: Entering event queue @ 190404637500. Starting simulation... switching cpus -info: Entering event queue @ 191292101500. Starting simulation... +info: Entering event queue @ 191404509500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 192292101500. Starting simulation... +info: Entering event queue @ 192404509500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 193292101500. Starting simulation... +info: Entering event queue @ 193404509500. Starting simulation... switching cpus -info: Entering event queue @ 193292109000. Starting simulation... +info: Entering event queue @ 193404517000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 194292109000. Starting simulation... +info: Entering event queue @ 194404517000. Starting simulation... +info: Entering event queue @ 194405024000. Starting simulation... switching cpus -info: Entering event queue @ 194292215000. Starting simulation... +info: Entering event queue @ 194405031500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 195292215000. Starting simulation... +info: Entering event queue @ 195405031500. Starting simulation... switching cpus -info: Entering event queue @ 195292215500. Starting simulation... +info: Entering event queue @ 195405033000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 196292215500. Starting simulation... +info: Entering event queue @ 196405033000. Starting simulation... switching cpus -info: Entering event queue @ 196292223000. Starting simulation... +info: Entering event queue @ 196405040500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 197292223000. Starting simulation... +info: Entering event queue @ 197405040500. Starting simulation... switching cpus -info: Entering event queue @ 197292262000. Starting simulation... +info: Entering event queue @ 197405066000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 198292262000. Starting simulation... +info: Entering event queue @ 198405066000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 199292262000. Starting simulation... -info: Entering event queue @ 199292269500. Starting simulation... +info: Entering event queue @ 199405066000. Starting simulation... +info: Entering event queue @ 199405333000. Starting simulation... switching cpus -info: Entering event queue @ 199292273000. Starting simulation... +info: Entering event queue @ 199405340500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 200292273000. Starting simulation... -info: Entering event queue @ 200292294500. Starting simulation... -info: Entering event queue @ 200292304500. Starting simulation... +info: Entering event queue @ 200405340500. Starting simulation... +info: Entering event queue @ 200405348500. Starting simulation... switching cpus -info: Entering event queue @ 200292310000. Starting simulation... +info: Entering event queue @ 200405353000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 201292310000. Starting simulation... +info: Entering event queue @ 201405353000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 202292310000. Starting simulation... -info: Entering event queue @ 202292318000. Starting simulation... +info: Entering event queue @ 202405353000. Starting simulation... switching cpus -info: Entering event queue @ 202292321000. Starting simulation... +info: Entering event queue @ 202405360500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 203292321000. Starting simulation... -info: Entering event queue @ 203292344000. Starting simulation... -info: Entering event queue @ 203292344500. Starting simulation... -info: Entering event queue @ 203292349000. Starting simulation... +info: Entering event queue @ 203405360500. Starting simulation... +info: Entering event queue @ 203405368000. Starting simulation... switching cpus -info: Entering event queue @ 203292350000. Starting simulation... +info: Entering event queue @ 203405369000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 204292350000. Starting simulation... switching cpus -info: Entering event queue @ 204292350500. Starting simulation... +info: Entering event queue @ 204405369000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 205292350500. Starting simulation... +info: Entering event queue @ 205405369000. Starting simulation... +info: Entering event queue @ 205405378500. Starting simulation... switching cpus -info: Entering event queue @ 205292358000. Starting simulation... +info: Entering event queue @ 205405382000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 206292358000. Starting simulation... -info: Entering event queue @ 206292372500. Starting simulation... +info: Entering event queue @ 206405382000. Starting simulation... +info: Entering event queue @ 206405420000. Starting simulation... switching cpus -info: Entering event queue @ 206292378000. Starting simulation... +info: Entering event queue @ 206405427500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 207292378000. Starting simulation... switching cpus -info: Entering event queue @ 207292378500. Starting simulation... +info: Entering event queue @ 207405427500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 208292378500. Starting simulation... +info: Entering event queue @ 208405427500. Starting simulation... switching cpus -info: Entering event queue @ 208292386000. Starting simulation... +info: Entering event queue @ 208405435000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 209292386000. Starting simulation... -info: Entering event queue @ 209292405500. Starting simulation... +info: Entering event queue @ 209405435000. Starting simulation... switching cpus -info: Entering event queue @ 209292411000. Starting simulation... +info: Entering event queue @ 209405451000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 210292411000. Starting simulation... +info: Entering event queue @ 210405451000. Starting simulation... switching cpus -info: Entering event queue @ 210292412000. Starting simulation... +info: Entering event queue @ 210405452000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 211292412000. Starting simulation... +info: Entering event queue @ 211405452000. Starting simulation... switching cpus -info: Entering event queue @ 211292428500. Starting simulation... +info: Entering event queue @ 211405462500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 212292428500. Starting simulation... +info: Entering event queue @ 212405462500. Starting simulation... +info: Entering event queue @ 212405472000. Starting simulation... switching cpus -info: Entering event queue @ 212292441500. Starting simulation... +info: Entering event queue @ 212405473000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 213405473000. Starting simulation... switching cpus -info: Entering event queue @ 213292441500. Starting simulation... +info: Entering event queue @ 213405473500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 214292441500. Starting simulation... -info: Entering event queue @ 214292451000. Starting simulation... +info: Entering event queue @ 214405473500. Starting simulation... +info: Entering event queue @ 214405524000. Starting simulation... switching cpus -info: Entering event queue @ 214292454500. Starting simulation... +info: Entering event queue @ 214405643750. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 215292454500. Starting simulation... -info: Entering event queue @ 215292695500. Starting simulation... +info: Entering event queue @ 215405643750. Starting simulation... +info: Entering event queue @ 215405728500. Starting simulation... switching cpus -info: Entering event queue @ 215292703000. Starting simulation... +info: Entering event queue @ 215406099750. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 216292703000. Starting simulation... switching cpus -info: Entering event queue @ 216292704000. Starting simulation... +info: Entering event queue @ 216406099750. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 217292704000. Starting simulation... +info: Entering event queue @ 217406099750. Starting simulation... switching cpus -info: Entering event queue @ 217292711500. Starting simulation... +info: Entering event queue @ 217406107250. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 218292711500. Starting simulation... -info: Entering event queue @ 218293082000. Starting simulation... +info: Entering event queue @ 218406107250. Starting simulation... +info: Entering event queue @ 218406116500. Starting simulation... +info: Entering event queue @ 218406122500. Starting simulation... switching cpus -info: Entering event queue @ 218293089500. Starting simulation... +info: Entering event queue @ 218406127000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 219406127000. Starting simulation... switching cpus -info: Entering event queue @ 219293089500. Starting simulation... +info: Entering event queue @ 219406127500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 220293089500. Starting simulation... +info: Entering event queue @ 220406127500. Starting simulation... switching cpus -info: Entering event queue @ 220293097000. Starting simulation... +info: Entering event queue @ 220406135000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 221293097000. Starting simulation... -info: Entering event queue @ 221293105500. Starting simulation... +info: Entering event queue @ 221406135000. Starting simulation... +info: Entering event queue @ 221406151500. Starting simulation... +info: Entering event queue @ 221406161000. Starting simulation... +info: Entering event queue @ 221406165500. Starting simulation... switching cpus -info: Entering event queue @ 221293110000. Starting simulation... +info: Entering event queue @ 221406166500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 222293110000. Starting simulation... switching cpus -info: Entering event queue @ 222293110500. Starting simulation... +info: Entering event queue @ 222406166500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 223293110500. Starting simulation... +info: Entering event queue @ 223406166500. Starting simulation... +info: Entering event queue @ 223406175000. Starting simulation... switching cpus -info: Entering event queue @ 223293118000. Starting simulation... +info: Entering event queue @ 223406178500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 224293118000. Starting simulation... +info: Entering event queue @ 224406178500. Starting simulation... +info: Entering event queue @ 224406203500. Starting simulation... switching cpus -info: Entering event queue @ 224293159000. Starting simulation... +info: Entering event queue @ 224406209000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 225293159000. Starting simulation... +info: Entering event queue @ 225406209000. Starting simulation... switching cpus -info: Entering event queue @ 225293159500. Starting simulation... +info: Entering event queue @ 225406210000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 226293159500. Starting simulation... -info: Entering event queue @ 226293167000. Starting simulation... +info: Entering event queue @ 226406210000. Starting simulation... switching cpus -info: Entering event queue @ 226293169000. Starting simulation... +info: Entering event queue @ 226406217500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 227293169000. Starting simulation... -info: Entering event queue @ 227293269000. Starting simulation... +info: Entering event queue @ 227406217500. Starting simulation... +info: Entering event queue @ 227406280000. Starting simulation... switching cpus -info: Entering event queue @ 227293276500. Starting simulation... +info: Entering event queue @ 227406429750. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 228293276500. Starting simulation... +info: Entering event queue @ 228406429750. Starting simulation... switching cpus -info: Entering event queue @ 228293277000. Starting simulation... +info: Entering event queue @ 228406430000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 229293277000. Starting simulation... +info: Entering event queue @ 229406430000. Starting simulation... switching cpus -info: Entering event queue @ 229293284500. Starting simulation... +info: Entering event queue @ 229406437500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 230293284500. Starting simulation... -info: Entering event queue @ 231290821000. Starting simulation... -info: Entering event queue @ 231290822000. Starting simulation... +info: Entering event queue @ 230406437500. Starting simulation... +info: Entering event queue @ 231403229000. Starting simulation... +info: Entering event queue @ 231403230000. Starting simulation... switching cpus -info: Entering event queue @ 231290826500. Starting simulation... +info: Entering event queue @ 231403234500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 232290826500. Starting simulation... +info: Entering event queue @ 232403234500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 233290826500. Starting simulation... +info: Entering event queue @ 233403234500. Starting simulation... switching cpus -info: Entering event queue @ 233290834000. Starting simulation... +info: Entering event queue @ 233403242000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 234290834000. Starting simulation... +info: Entering event queue @ 234403242000. Starting simulation... switching cpus -info: Entering event queue @ 235290693500. Starting simulation... +info: Entering event queue @ 235403101500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 236290693500. Starting simulation... +info: Entering event queue @ 236403101500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 237290693500. Starting simulation... +info: Entering event queue @ 237403101500. Starting simulation... switching cpus -info: Entering event queue @ 237290701000. Starting simulation... +info: Entering event queue @ 237403109000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 238290701000. Starting simulation... +info: Entering event queue @ 238403109000. Starting simulation... switching cpus -info: Entering event queue @ 239290565500. Starting simulation... +info: Entering event queue @ 239402973500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 240290565500. Starting simulation... +info: Entering event queue @ 240402973500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 241290565500. Starting simulation... +info: Entering event queue @ 241402973500. Starting simulation... switching cpus -info: Entering event queue @ 241290573000. Starting simulation... +info: Entering event queue @ 241402981000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 242290573000. Starting simulation... -info: Entering event queue @ 243290437000. Starting simulation... -info: Entering event queue @ 243290438000. Starting simulation... +info: Entering event queue @ 242402981000. Starting simulation... +info: Entering event queue @ 243402845000. Starting simulation... +info: Entering event queue @ 243402846000. Starting simulation... switching cpus -info: Entering event queue @ 243290442500. Starting simulation... +info: Entering event queue @ 243402850500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 244290442500. Starting simulation... +info: Entering event queue @ 244402850500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 245290442500. Starting simulation... +info: Entering event queue @ 245402850500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 246290442500. Starting simulation... +info: Entering event queue @ 246402850500. Starting simulation... switching cpus -info: Entering event queue @ 247290309500. Starting simulation... +info: Entering event queue @ 247402717500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 248290309500. Starting simulation... +info: Entering event queue @ 248402717500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 249290309500. Starting simulation... +info: Entering event queue @ 249402717500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 250290309500. Starting simulation... +info: Entering event queue @ 250402717500. Starting simulation... switching cpus -info: Entering event queue @ 251290181500. Starting simulation... +info: Entering event queue @ 251402589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 252290181500. Starting simulation... +info: Entering event queue @ 252402589500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 253290181500. Starting simulation... +info: Entering event queue @ 253402589500. Starting simulation... switching cpus -info: Entering event queue @ 253290189000. Starting simulation... +info: Entering event queue @ 253402597000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 254290189000. Starting simulation... +info: Entering event queue @ 254402597000. Starting simulation... switching cpus -info: Entering event queue @ 255290053500. Starting simulation... +info: Entering event queue @ 255402461500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 256290053500. Starting simulation... +info: Entering event queue @ 256402461500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 257290053500. Starting simulation... +info: Entering event queue @ 257402461500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 258290053500. Starting simulation... +info: Entering event queue @ 258402461500. Starting simulation... switching cpus -info: Entering event queue @ 259289925500. Starting simulation... +info: Entering event queue @ 259402333500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 260289925500. Starting simulation... +info: Entering event queue @ 260402333500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 261289925500. Starting simulation... +info: Entering event queue @ 261402333500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 262289925500. Starting simulation... +info: Entering event queue @ 262402333500. Starting simulation... switching cpus -info: Entering event queue @ 263289797500. Starting simulation... +info: Entering event queue @ 263402205500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 264289797500. Starting simulation... +info: Entering event queue @ 264402205500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 265289797500. Starting simulation... +info: Entering event queue @ 265402205500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 266289797500. Starting simulation... +info: Entering event queue @ 266402205500. Starting simulation... switching cpus -info: Entering event queue @ 267289669500. Starting simulation... +info: Entering event queue @ 267402077500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 268289669500. Starting simulation... +info: Entering event queue @ 268402077500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 269289669500. Starting simulation... +info: Entering event queue @ 269402077500. Starting simulation... switching cpus -info: Entering event queue @ 269289677000. Starting simulation... +info: Entering event queue @ 269402085000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 270289677000. Starting simulation... +info: Entering event queue @ 270402085000. Starting simulation... switching cpus -info: Entering event queue @ 271289541500. Starting simulation... +info: Entering event queue @ 271401949500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 272289541500. Starting simulation... +info: Entering event queue @ 272401949500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 273289541500. Starting simulation... +info: Entering event queue @ 273401949500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 274289541500. Starting simulation... +info: Entering event queue @ 274401949500. Starting simulation... switching cpus -info: Entering event queue @ 275289413500. Starting simulation... +info: Entering event queue @ 275401821500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 276289413500. Starting simulation... +info: Entering event queue @ 276401821500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 277289413500. Starting simulation... +info: Entering event queue @ 277401821500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 278289413500. Starting simulation... +info: Entering event queue @ 278401821500. Starting simulation... switching cpus -info: Entering event queue @ 279289285500. Starting simulation... +info: Entering event queue @ 279401693500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 280289285500. Starting simulation... +info: Entering event queue @ 280401693500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 281289285500. Starting simulation... +info: Entering event queue @ 281401693500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 282289285500. Starting simulation... +info: Entering event queue @ 282401693500. Starting simulation... switching cpus -info: Entering event queue @ 283289157500. Starting simulation... +info: Entering event queue @ 283401565500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 284289157500. Starting simulation... +info: Entering event queue @ 284401565500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 285289157500. Starting simulation... +info: Entering event queue @ 285401565500. Starting simulation... switching cpus -info: Entering event queue @ 285289165000. Starting simulation... +info: Entering event queue @ 285401573000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 286289165000. Starting simulation... +info: Entering event queue @ 286401573000. Starting simulation... switching cpus -info: Entering event queue @ 287289029500. Starting simulation... +info: Entering event queue @ 287401437500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 288289029500. Starting simulation... +info: Entering event queue @ 288401437500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 289289029500. Starting simulation... +info: Entering event queue @ 289401437500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 290289029500. Starting simulation... +info: Entering event queue @ 290401437500. Starting simulation... switching cpus -info: Entering event queue @ 291288901500. Starting simulation... +info: Entering event queue @ 291401309500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 292288901500. Starting simulation... +info: Entering event queue @ 292401309500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 293288901500. Starting simulation... +info: Entering event queue @ 293401309500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 294288901500. Starting simulation... +info: Entering event queue @ 294401309500. Starting simulation... switching cpus -info: Entering event queue @ 295288773500. Starting simulation... +info: Entering event queue @ 295401181500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 296288773500. Starting simulation... +info: Entering event queue @ 296401181500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 297288773500. Starting simulation... +info: Entering event queue @ 297401181500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 298288773500. Starting simulation... +info: Entering event queue @ 298401181500. Starting simulation... switching cpus -info: Entering event queue @ 299288645500. Starting simulation... +info: Entering event queue @ 299401053500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 300288645500. Starting simulation... +info: Entering event queue @ 300401053500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 301288645500. Starting simulation... switching cpus -info: Entering event queue @ 301288653000. Starting simulation... +info: Entering event queue @ 301401053500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 302288653000. Starting simulation... +info: Entering event queue @ 302401053500. Starting simulation... switching cpus -info: Entering event queue @ 303288517500. Starting simulation... +info: Entering event queue @ 303400925500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 304288517500. Starting simulation... +info: Entering event queue @ 304400925500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 305288517500. Starting simulation... +info: Entering event queue @ 305400925500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 306288517500. Starting simulation... +info: Entering event queue @ 306400925500. Starting simulation... switching cpus -info: Entering event queue @ 307288389500. Starting simulation... +info: Entering event queue @ 307400797500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 308288389500. Starting simulation... +info: Entering event queue @ 308400797500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 309288389500. Starting simulation... +info: Entering event queue @ 309400797500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 310288389500. Starting simulation... +info: Entering event queue @ 310400797500. Starting simulation... switching cpus -info: Entering event queue @ 311288261500. Starting simulation... +info: Entering event queue @ 311400669500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 312288261500. Starting simulation... +info: Entering event queue @ 312400669500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 313288261500. Starting simulation... +info: Entering event queue @ 313400669500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 314288261500. Starting simulation... +info: Entering event queue @ 314400669500. Starting simulation... switching cpus -info: Entering event queue @ 315288133500. Starting simulation... +info: Entering event queue @ 315400541500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 316288133500. Starting simulation... +info: Entering event queue @ 316400541500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 317288133500. Starting simulation... +info: Entering event queue @ 317400541500. Starting simulation... switching cpus -info: Entering event queue @ 317288141000. Starting simulation... +info: Entering event queue @ 317400549000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 318288141000. Starting simulation... +info: Entering event queue @ 318400549000. Starting simulation... switching cpus -info: Entering event queue @ 319288005500. Starting simulation... +info: Entering event queue @ 319400413500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 320288005500. Starting simulation... +info: Entering event queue @ 320400413500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 321288005500. Starting simulation... +info: Entering event queue @ 321400413500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 322288005500. Starting simulation... +info: Entering event queue @ 322400413500. Starting simulation... switching cpus -info: Entering event queue @ 323287877500. Starting simulation... +info: Entering event queue @ 323400285500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 324287877500. Starting simulation... +info: Entering event queue @ 324400285500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 325287877500. Starting simulation... +info: Entering event queue @ 325400285500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 326287877500. Starting simulation... +info: Entering event queue @ 326400285500. Starting simulation... switching cpus -info: Entering event queue @ 327287749500. Starting simulation... +info: Entering event queue @ 327400157500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 328287749500. Starting simulation... +info: Entering event queue @ 328400157500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 329287749500. Starting simulation... +info: Entering event queue @ 329400157500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 330287749500. Starting simulation... +info: Entering event queue @ 330400157500. Starting simulation... switching cpus -info: Entering event queue @ 331287621500. Starting simulation... +info: Entering event queue @ 331400029500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 332287621500. Starting simulation... +info: Entering event queue @ 332400029500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 333400029500. Starting simulation... switching cpus -info: Entering event queue @ 333287621500. Starting simulation... +info: Entering event queue @ 333400037000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 334287621500. Starting simulation... +info: Entering event queue @ 334400037000. Starting simulation... switching cpus -info: Entering event queue @ 335287493500. Starting simulation... +info: Entering event queue @ 335399901500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 336287493500. Starting simulation... +info: Entering event queue @ 336399901500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 337287493500. Starting simulation... +info: Entering event queue @ 337399901500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 338287493500. Starting simulation... +info: Entering event queue @ 338399901500. Starting simulation... switching cpus -info: Entering event queue @ 339287365500. Starting simulation... +info: Entering event queue @ 339399773500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 340287365500. Starting simulation... +info: Entering event queue @ 340399773500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 341287365500. Starting simulation... +info: Entering event queue @ 341399773500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 342287365500. Starting simulation... +info: Entering event queue @ 342399773500. Starting simulation... switching cpus -info: Entering event queue @ 343287237500. Starting simulation... +info: Entering event queue @ 343399645500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 344287237500. Starting simulation... +info: Entering event queue @ 344399645500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 345287237500. Starting simulation... +info: Entering event queue @ 345399645500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 346287237500. Starting simulation... +info: Entering event queue @ 346399645500. Starting simulation... switching cpus -info: Entering event queue @ 347287109500. Starting simulation... +info: Entering event queue @ 347399517500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 348287109500. Starting simulation... +info: Entering event queue @ 348399517500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 349399517500. Starting simulation... switching cpus -info: Entering event queue @ 349287109500. Starting simulation... +info: Entering event queue @ 349399525000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 350287109500. Starting simulation... +info: Entering event queue @ 350399525000. Starting simulation... switching cpus -info: Entering event queue @ 351286981500. Starting simulation... +info: Entering event queue @ 351399389500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 352286981500. Starting simulation... +info: Entering event queue @ 352399389500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 353286981500. Starting simulation... +info: Entering event queue @ 353399389500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 354286981500. Starting simulation... +info: Entering event queue @ 354399389500. Starting simulation... switching cpus -info: Entering event queue @ 355286853500. Starting simulation... +info: Entering event queue @ 355399261500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 356286853500. Starting simulation... +info: Entering event queue @ 356399261500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 357286853500. Starting simulation... +info: Entering event queue @ 357399261500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 358286853500. Starting simulation... +info: Entering event queue @ 358399261500. Starting simulation... switching cpus -info: Entering event queue @ 359286725500. Starting simulation... +info: Entering event queue @ 359399133500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 360286725500. Starting simulation... +info: Entering event queue @ 360399133500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 361286725500. Starting simulation... +info: Entering event queue @ 361399133500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 362286725500. Starting simulation... +info: Entering event queue @ 362399133500. Starting simulation... switching cpus -info: Entering event queue @ 363286597500. Starting simulation... +info: Entering event queue @ 363399005500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 364286597500. Starting simulation... +info: Entering event queue @ 364399005500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 365286597500. Starting simulation... switching cpus -info: Entering event queue @ 365286605000. Starting simulation... +info: Entering event queue @ 365399005500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 366286605000. Starting simulation... +info: Entering event queue @ 366399005500. Starting simulation... switching cpus -info: Entering event queue @ 367286469500. Starting simulation... +info: Entering event queue @ 367398877500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 368286469500. Starting simulation... +info: Entering event queue @ 368398877500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 369286469500. Starting simulation... +info: Entering event queue @ 369398877500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 370286469500. Starting simulation... +info: Entering event queue @ 370398877500. Starting simulation... switching cpus -info: Entering event queue @ 371286341500. Starting simulation... +info: Entering event queue @ 371398749500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 372286341500. Starting simulation... +info: Entering event queue @ 372398749500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 373286341500. Starting simulation... +info: Entering event queue @ 373398749500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 374286341500. Starting simulation... +info: Entering event queue @ 374398749500. Starting simulation... switching cpus -info: Entering event queue @ 375286213500. Starting simulation... +info: Entering event queue @ 375398621500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 376286213500. Starting simulation... +info: Entering event queue @ 376398621500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 377286213500. Starting simulation... +info: Entering event queue @ 377398621500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 378286213500. Starting simulation... +info: Entering event queue @ 378398621500. Starting simulation... switching cpus -info: Entering event queue @ 379286085500. Starting simulation... +info: Entering event queue @ 379398493500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 380286085500. Starting simulation... +info: Entering event queue @ 380398493500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 381286085500. Starting simulation... switching cpus -info: Entering event queue @ 381286093000. Starting simulation... +info: Entering event queue @ 381398493500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 382286093000. Starting simulation... +info: Entering event queue @ 382398493500. Starting simulation... switching cpus -info: Entering event queue @ 383285957500. Starting simulation... +info: Entering event queue @ 383398365500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 384285957500. Starting simulation... +info: Entering event queue @ 384398365500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 385285957500. Starting simulation... +info: Entering event queue @ 385398365500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 386285957500. Starting simulation... +info: Entering event queue @ 386398365500. Starting simulation... switching cpus -info: Entering event queue @ 387285829500. Starting simulation... +info: Entering event queue @ 387398237500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 388285829500. Starting simulation... +info: Entering event queue @ 388398237500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 389285829500. Starting simulation... +info: Entering event queue @ 389398237500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 390285829500. Starting simulation... +info: Entering event queue @ 390398237500. Starting simulation... switching cpus -info: Entering event queue @ 391285701500. Starting simulation... +info: Entering event queue @ 391398109500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 392285701500. Starting simulation... +info: Entering event queue @ 392398109500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 393285701500. Starting simulation... +info: Entering event queue @ 393398109500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 394285701500. Starting simulation... +info: Entering event queue @ 394398109500. Starting simulation... switching cpus -info: Entering event queue @ 395285573500. Starting simulation... +info: Entering event queue @ 395397981500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 396285573500. Starting simulation... +info: Entering event queue @ 396397981500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 397285573500. Starting simulation... switching cpus -info: Entering event queue @ 397285581000. Starting simulation... +info: Entering event queue @ 397397981500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 398285581000. Starting simulation... +info: Entering event queue @ 398397981500. Starting simulation... switching cpus -info: Entering event queue @ 399285445500. Starting simulation... +info: Entering event queue @ 399397853500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 400285445500. Starting simulation... +info: Entering event queue @ 400397853500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 401285445500. Starting simulation... +info: Entering event queue @ 401397853500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 402285445500. Starting simulation... +info: Entering event queue @ 402397853500. Starting simulation... switching cpus -info: Entering event queue @ 403285317500. Starting simulation... +info: Entering event queue @ 403397725500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 404285317500. Starting simulation... +info: Entering event queue @ 404397725500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 405285317500. Starting simulation... +info: Entering event queue @ 405397725500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 406285317500. Starting simulation... +info: Entering event queue @ 406397725500. Starting simulation... switching cpus -info: Entering event queue @ 407285189500. Starting simulation... +info: Entering event queue @ 407397597500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 408285189500. Starting simulation... +info: Entering event queue @ 408397597500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 409285189500. Starting simulation... +info: Entering event queue @ 409397597500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 410285189500. Starting simulation... +info: Entering event queue @ 410397597500. Starting simulation... switching cpus -info: Entering event queue @ 411285061500. Starting simulation... +info: Entering event queue @ 411397469500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 412285061500. Starting simulation... +info: Entering event queue @ 412397469500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 413285061500. Starting simulation... +info: Entering event queue @ 413397469500. Starting simulation... switching cpus -info: Entering event queue @ 413285069000. Starting simulation... +info: Entering event queue @ 413397477000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 414285069000. Starting simulation... +info: Entering event queue @ 414397477000. Starting simulation... switching cpus -info: Entering event queue @ 415284933500. Starting simulation... +info: Entering event queue @ 415397341500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 416284933500. Starting simulation... +info: Entering event queue @ 416397341500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 417284933500. Starting simulation... +info: Entering event queue @ 417397341500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 418284933500. Starting simulation... +info: Entering event queue @ 418397341500. Starting simulation... switching cpus -info: Entering event queue @ 419284805500. Starting simulation... +info: Entering event queue @ 419397213500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 420284805500. Starting simulation... +info: Entering event queue @ 420397213500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 421284805500. Starting simulation... +info: Entering event queue @ 421397213500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 422284805500. Starting simulation... +info: Entering event queue @ 422397213500. Starting simulation... switching cpus -info: Entering event queue @ 423284677500. Starting simulation... +info: Entering event queue @ 423397085500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 424284677500. Starting simulation... +info: Entering event queue @ 424397085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 425284677500. Starting simulation... +info: Entering event queue @ 425397085500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 426284677500. Starting simulation... +info: Entering event queue @ 426397085500. Starting simulation... switching cpus -info: Entering event queue @ 427284549500. Starting simulation... +info: Entering event queue @ 427396957500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 428284549500. Starting simulation... +info: Entering event queue @ 428396957500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 429284549500. Starting simulation... +info: Entering event queue @ 429396957500. Starting simulation... switching cpus -info: Entering event queue @ 429284557000. Starting simulation... +info: Entering event queue @ 429396965000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 430284557000. Starting simulation... +info: Entering event queue @ 430396965000. Starting simulation... switching cpus -info: Entering event queue @ 431284421500. Starting simulation... +info: Entering event queue @ 431396829500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 432284421500. Starting simulation... +info: Entering event queue @ 432396829500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 433284421500. Starting simulation... +info: Entering event queue @ 433396829500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 434284421500. Starting simulation... +info: Entering event queue @ 434396829500. Starting simulation... switching cpus -info: Entering event queue @ 435284293500. Starting simulation... +info: Entering event queue @ 435396701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 436284293500. Starting simulation... +info: Entering event queue @ 436396701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 437284293500. Starting simulation... +info: Entering event queue @ 437396701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 438284293500. Starting simulation... +info: Entering event queue @ 438396701500. Starting simulation... switching cpus -info: Entering event queue @ 439284165500. Starting simulation... +info: Entering event queue @ 439396573500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 440284165500. Starting simulation... +info: Entering event queue @ 440396573500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 441284165500. Starting simulation... +info: Entering event queue @ 441396573500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 442284165500. Starting simulation... +info: Entering event queue @ 442396573500. Starting simulation... switching cpus -info: Entering event queue @ 443284037500. Starting simulation... +info: Entering event queue @ 443396445500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 444284037500. Starting simulation... +info: Entering event queue @ 444396445500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 445284037500. Starting simulation... +info: Entering event queue @ 445396445500. Starting simulation... switching cpus -info: Entering event queue @ 445284045000. Starting simulation... +info: Entering event queue @ 445396453000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 446284045000. Starting simulation... +info: Entering event queue @ 446396453000. Starting simulation... switching cpus -info: Entering event queue @ 447283909500. Starting simulation... +info: Entering event queue @ 447396317500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 448283909500. Starting simulation... +info: Entering event queue @ 448396317500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 449283909500. Starting simulation... +info: Entering event queue @ 449396317500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 450283909500. Starting simulation... +info: Entering event queue @ 450396317500. Starting simulation... switching cpus -info: Entering event queue @ 451283781500. Starting simulation... +info: Entering event queue @ 451396189500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 452283781500. Starting simulation... +info: Entering event queue @ 452396189500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 453283781500. Starting simulation... +info: Entering event queue @ 453396189500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 454283781500. Starting simulation... +info: Entering event queue @ 454396189500. Starting simulation... switching cpus -info: Entering event queue @ 455283653500. Starting simulation... +info: Entering event queue @ 455396061500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 456283653500. Starting simulation... +info: Entering event queue @ 456396061500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 457283653500. Starting simulation... +info: Entering event queue @ 457396061500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 458283653500. Starting simulation... +info: Entering event queue @ 458396061500. Starting simulation... switching cpus -info: Entering event queue @ 459283525500. Starting simulation... +info: Entering event queue @ 459395933500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 460283525500. Starting simulation... +info: Entering event queue @ 460395933500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 461283525500. Starting simulation... +info: Entering event queue @ 461395933500. Starting simulation... switching cpus -info: Entering event queue @ 461283533000. Starting simulation... +info: Entering event queue @ 461395941000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 462283533000. Starting simulation... +info: Entering event queue @ 462395941000. Starting simulation... switching cpus -info: Entering event queue @ 463283397500. Starting simulation... +info: Entering event queue @ 463395805500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 464283397500. Starting simulation... +info: Entering event queue @ 464395805500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 465283397500. Starting simulation... +info: Entering event queue @ 465395805500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 466283397500. Starting simulation... +info: Entering event queue @ 466395805500. Starting simulation... switching cpus -info: Entering event queue @ 467283269500. Starting simulation... +info: Entering event queue @ 467395677500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 468283269500. Starting simulation... +info: Entering event queue @ 468395677500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 469283269500. Starting simulation... +info: Entering event queue @ 469395677500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 470283269500. Starting simulation... +info: Entering event queue @ 470395677500. Starting simulation... switching cpus -info: Entering event queue @ 471283141500. Starting simulation... +info: Entering event queue @ 471395549500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 472283141500. Starting simulation... +info: Entering event queue @ 472395549500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 473283141500. Starting simulation... +info: Entering event queue @ 473395549500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 474283141500. Starting simulation... +info: Entering event queue @ 474395549500. Starting simulation... switching cpus -info: Entering event queue @ 475283013500. Starting simulation... +info: Entering event queue @ 475395421500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 476283013500. Starting simulation... +info: Entering event queue @ 476395421500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 477283013500. Starting simulation... +info: Entering event queue @ 477395421500. Starting simulation... switching cpus -info: Entering event queue @ 477283021000. Starting simulation... +info: Entering event queue @ 477395429000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 478283021000. Starting simulation... +info: Entering event queue @ 478395429000. Starting simulation... switching cpus -info: Entering event queue @ 479282885500. Starting simulation... +info: Entering event queue @ 479395293500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 480282885500. Starting simulation... +info: Entering event queue @ 480395293500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 481282885500. Starting simulation... +info: Entering event queue @ 481395293500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 482282885500. Starting simulation... +info: Entering event queue @ 482395293500. Starting simulation... switching cpus -info: Entering event queue @ 483282757500. Starting simulation... +info: Entering event queue @ 483395165500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 484282757500. Starting simulation... +info: Entering event queue @ 484395165500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 485282757500. Starting simulation... +info: Entering event queue @ 485395165500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 486282757500. Starting simulation... +info: Entering event queue @ 486395165500. Starting simulation... switching cpus -info: Entering event queue @ 487282629500. Starting simulation... +info: Entering event queue @ 487395037500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 488282629500. Starting simulation... +info: Entering event queue @ 488395037500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 489282629500. Starting simulation... +info: Entering event queue @ 489395037500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 490282629500. Starting simulation... +info: Entering event queue @ 490395037500. Starting simulation... switching cpus -info: Entering event queue @ 491282501500. Starting simulation... +info: Entering event queue @ 491394909500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 492282501500. Starting simulation... +info: Entering event queue @ 492394909500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 493282501500. Starting simulation... +info: Entering event queue @ 493394909500. Starting simulation... switching cpus -info: Entering event queue @ 493282509000. Starting simulation... +info: Entering event queue @ 493394917000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 494282509000. Starting simulation... +info: Entering event queue @ 494394917000. Starting simulation... switching cpus -info: Entering event queue @ 495282373500. Starting simulation... +info: Entering event queue @ 495394781500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 496282373500. Starting simulation... +info: Entering event queue @ 496394781500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 497282373500. Starting simulation... +info: Entering event queue @ 497394781500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 498282373500. Starting simulation... +info: Entering event queue @ 498394781500. Starting simulation... switching cpus -info: Entering event queue @ 499282245500. Starting simulation... +info: Entering event queue @ 499394653500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 500282245500. Starting simulation... +info: Entering event queue @ 500394653500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 501282245500. Starting simulation... +info: Entering event queue @ 501394653500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 502282245500. Starting simulation... +info: Entering event queue @ 502394653500. Starting simulation... switching cpus -info: Entering event queue @ 503282117500. Starting simulation... +info: Entering event queue @ 503394525500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 504282117500. Starting simulation... +info: Entering event queue @ 504394525500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 505282117500. Starting simulation... +info: Entering event queue @ 505394525500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 506282117500. Starting simulation... +info: Entering event queue @ 506394525500. Starting simulation... switching cpus -info: Entering event queue @ 507281989500. Starting simulation... +info: Entering event queue @ 507394397500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 508281989500. Starting simulation... +info: Entering event queue @ 508394397500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 509394397500. Starting simulation... switching cpus -info: Entering event queue @ 509281989500. Starting simulation... +info: Entering event queue @ 509394405000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 510281989500. Starting simulation... +info: Entering event queue @ 510394405000. Starting simulation... switching cpus -info: Entering event queue @ 511281861500. Starting simulation... +info: Entering event queue @ 511394269500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 512281861500. Starting simulation... +info: Entering event queue @ 512394269500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 513281861500. Starting simulation... +info: Entering event queue @ 513394269500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 514281861500. Starting simulation... +info: Entering event queue @ 514394269500. Starting simulation... switching cpus -info: Entering event queue @ 515281733500. Starting simulation... +info: Entering event queue @ 515394141500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 516281733500. Starting simulation... +info: Entering event queue @ 516394141500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 517281733500. Starting simulation... +info: Entering event queue @ 517394141500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 518281733500. Starting simulation... +info: Entering event queue @ 518394141500. Starting simulation... switching cpus -info: Entering event queue @ 519281605500. Starting simulation... +info: Entering event queue @ 519394013500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 520281605500. Starting simulation... +info: Entering event queue @ 520394013500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 521281605500. Starting simulation... +info: Entering event queue @ 521394013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 522281605500. Starting simulation... +info: Entering event queue @ 522394013500. Starting simulation... switching cpus -info: Entering event queue @ 523281477500. Starting simulation... +info: Entering event queue @ 523393885500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 524281477500. Starting simulation... +info: Entering event queue @ 524393885500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 525393885500. Starting simulation... switching cpus -info: Entering event queue @ 525281477500. Starting simulation... +info: Entering event queue @ 525393893000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 526281477500. Starting simulation... +info: Entering event queue @ 526393893000. Starting simulation... switching cpus -info: Entering event queue @ 527281349500. Starting simulation... +info: Entering event queue @ 527393757500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 528281349500. Starting simulation... +info: Entering event queue @ 528393757500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 529281349500. Starting simulation... +info: Entering event queue @ 529393757500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 530281349500. Starting simulation... +info: Entering event queue @ 530393757500. Starting simulation... switching cpus -info: Entering event queue @ 531281221500. Starting simulation... +info: Entering event queue @ 531393629500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 532281221500. Starting simulation... +info: Entering event queue @ 532393629500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 533281221500. Starting simulation... +info: Entering event queue @ 533393629500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 534281221500. Starting simulation... +info: Entering event queue @ 534393629500. Starting simulation... switching cpus -info: Entering event queue @ 535281093500. Starting simulation... +info: Entering event queue @ 535393501500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 536281093500. Starting simulation... switching cpus -info: Entering event queue @ 536281103000. Starting simulation... +info: Entering event queue @ 536393501500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 537281103000. Starting simulation... +info: Entering event queue @ 537393501500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 538281103000. Starting simulation... +info: Entering event queue @ 538393501500. Starting simulation... switching cpus -info: Entering event queue @ 539280965500. Starting simulation... +info: Entering event queue @ 539393373500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 540280965500. Starting simulation... switching cpus -info: Entering event queue @ 540280967500. Starting simulation... +info: Entering event queue @ 540393373500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 541393373500. Starting simulation... switching cpus -info: Entering event queue @ 541280967500. Starting simulation... +info: Entering event queue @ 541393381000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 542280967500. Starting simulation... +info: Entering event queue @ 542393381000. Starting simulation... switching cpus -info: Entering event queue @ 543280837500. Starting simulation... +info: Entering event queue @ 543393245500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 544280837500. Starting simulation... +info: Entering event queue @ 544393245500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 545280837500. Starting simulation... +info: Entering event queue @ 545393245500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 546280837500. Starting simulation... +info: Entering event queue @ 546393245500. Starting simulation... switching cpus -info: Entering event queue @ 547280709500. Starting simulation... +info: Entering event queue @ 547393117500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 548280709500. Starting simulation... +info: Entering event queue @ 548393117500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 549280709500. Starting simulation... +info: Entering event queue @ 549393117500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 550280709500. Starting simulation... +info: Entering event queue @ 550393117500. Starting simulation... switching cpus -info: Entering event queue @ 551280581500. Starting simulation... +info: Entering event queue @ 551392989500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 552280581500. Starting simulation... +info: Entering event queue @ 552392989500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 553280581500. Starting simulation... +info: Entering event queue @ 553392989500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 554280581500. Starting simulation... +info: Entering event queue @ 554392989500. Starting simulation... switching cpus -info: Entering event queue @ 555280453500. Starting simulation... +info: Entering event queue @ 555392861500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 556280453500. Starting simulation... +info: Entering event queue @ 556392861500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 557392861500. Starting simulation... switching cpus -info: Entering event queue @ 557280453500. Starting simulation... +info: Entering event queue @ 557392869000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 558280453500. Starting simulation... +info: Entering event queue @ 558392869000. Starting simulation... switching cpus -info: Entering event queue @ 559280325500. Starting simulation... +info: Entering event queue @ 559392733500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 560280325500. Starting simulation... +info: Entering event queue @ 560392733500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 561280325500. Starting simulation... +info: Entering event queue @ 561392733500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 562280325500. Starting simulation... +info: Entering event queue @ 562392733500. Starting simulation... switching cpus -info: Entering event queue @ 563280197500. Starting simulation... +info: Entering event queue @ 563392605500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 564280197500. Starting simulation... +info: Entering event queue @ 564392605500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 565280197500. Starting simulation... +info: Entering event queue @ 565392605500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 566280197500. Starting simulation... +info: Entering event queue @ 566392605500. Starting simulation... switching cpus -info: Entering event queue @ 567280069500. Starting simulation... +info: Entering event queue @ 567392477500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 568280069500. Starting simulation... +info: Entering event queue @ 568392477500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 569280069500. Starting simulation... +info: Entering event queue @ 569392477500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 570280069500. Starting simulation... +info: Entering event queue @ 570392477500. Starting simulation... switching cpus -info: Entering event queue @ 571279941500. Starting simulation... +info: Entering event queue @ 571392349500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 572279941500. Starting simulation... +info: Entering event queue @ 572392349500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 573392349500. Starting simulation... switching cpus -info: Entering event queue @ 573279941500. Starting simulation... +info: Entering event queue @ 573392357000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 574279941500. Starting simulation... +info: Entering event queue @ 574392357000. Starting simulation... switching cpus -info: Entering event queue @ 575279813500. Starting simulation... +info: Entering event queue @ 575392221500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 576279813500. Starting simulation... +info: Entering event queue @ 576392221500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 577279813500. Starting simulation... +info: Entering event queue @ 577392221500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 578279813500. Starting simulation... +info: Entering event queue @ 578392221500. Starting simulation... switching cpus -info: Entering event queue @ 579279685500. Starting simulation... +info: Entering event queue @ 579392093500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 580279685500. Starting simulation... +info: Entering event queue @ 580392093500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 581279685500. Starting simulation... +info: Entering event queue @ 581392093500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 582279685500. Starting simulation... +info: Entering event queue @ 582392093500. Starting simulation... switching cpus -info: Entering event queue @ 583279557500. Starting simulation... +info: Entering event queue @ 583391965500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 584279557500. Starting simulation... +info: Entering event queue @ 584391965500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 585279557500. Starting simulation... +info: Entering event queue @ 585391965500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 586279557500. Starting simulation... +info: Entering event queue @ 586391965500. Starting simulation... switching cpus -info: Entering event queue @ 587279429500. Starting simulation... +info: Entering event queue @ 587391837500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 588279429500. Starting simulation... +info: Entering event queue @ 588391837500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 589391837500. Starting simulation... switching cpus -info: Entering event queue @ 589279429500. Starting simulation... +info: Entering event queue @ 589391845000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 590279429500. Starting simulation... +info: Entering event queue @ 590391845000. Starting simulation... switching cpus -info: Entering event queue @ 591279301500. Starting simulation... +info: Entering event queue @ 591391709500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 592279301500. Starting simulation... +info: Entering event queue @ 592391709500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 593279301500. Starting simulation... +info: Entering event queue @ 593391709500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 594279301500. Starting simulation... +info: Entering event queue @ 594391709500. Starting simulation... switching cpus -info: Entering event queue @ 595279173500. Starting simulation... +info: Entering event queue @ 595391581500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 596279173500. Starting simulation... +info: Entering event queue @ 596391581500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 597279173500. Starting simulation... +info: Entering event queue @ 597391581500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 598279173500. Starting simulation... +info: Entering event queue @ 598391581500. Starting simulation... switching cpus -info: Entering event queue @ 599279045500. Starting simulation... +info: Entering event queue @ 599391453500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 600279045500. Starting simulation... +info: Entering event queue @ 600391453500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 601279045500. Starting simulation... +info: Entering event queue @ 601391453500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 602279045500. Starting simulation... +info: Entering event queue @ 602391453500. Starting simulation... switching cpus -info: Entering event queue @ 603278917500. Starting simulation... +info: Entering event queue @ 603391325500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 604278917500. Starting simulation... +info: Entering event queue @ 604391325500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 605391325500. Starting simulation... switching cpus -info: Entering event queue @ 605278917500. Starting simulation... +info: Entering event queue @ 605391333000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 606278917500. Starting simulation... +info: Entering event queue @ 606391333000. Starting simulation... switching cpus -info: Entering event queue @ 607278789500. Starting simulation... +info: Entering event queue @ 607391197500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 608278789500. Starting simulation... +info: Entering event queue @ 608391197500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 609278789500. Starting simulation... +info: Entering event queue @ 609391197500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 610278789500. Starting simulation... +info: Entering event queue @ 610391197500. Starting simulation... switching cpus -info: Entering event queue @ 611278661500. Starting simulation... +info: Entering event queue @ 611391069500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 612278661500. Starting simulation... +info: Entering event queue @ 612391069500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 613278661500. Starting simulation... +info: Entering event queue @ 613391069500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 614278661500. Starting simulation... +info: Entering event queue @ 614391069500. Starting simulation... switching cpus -info: Entering event queue @ 615278533500. Starting simulation... +info: Entering event queue @ 615390941500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 616278533500. Starting simulation... +info: Entering event queue @ 616390941500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 617278533500. Starting simulation... +info: Entering event queue @ 617390941500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 618278533500. Starting simulation... +info: Entering event queue @ 618390941500. Starting simulation... switching cpus -info: Entering event queue @ 619278405500. Starting simulation... +info: Entering event queue @ 619390813500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 620278405500. Starting simulation... +info: Entering event queue @ 620390813500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 621390813500. Starting simulation... switching cpus -info: Entering event queue @ 621278405500. Starting simulation... +info: Entering event queue @ 621390821000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 622278405500. Starting simulation... +info: Entering event queue @ 622390821000. Starting simulation... switching cpus -info: Entering event queue @ 623278277500. Starting simulation... +info: Entering event queue @ 623390685500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 624278277500. Starting simulation... +info: Entering event queue @ 624390685500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 625278277500. Starting simulation... +info: Entering event queue @ 625390685500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 626278277500. Starting simulation... +info: Entering event queue @ 626390685500. Starting simulation... switching cpus -info: Entering event queue @ 627278149500. Starting simulation... +info: Entering event queue @ 627390557500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 628278149500. Starting simulation... +info: Entering event queue @ 628390557500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 629278149500. Starting simulation... +info: Entering event queue @ 629390557500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 630278149500. Starting simulation... +info: Entering event queue @ 630390557500. Starting simulation... switching cpus -info: Entering event queue @ 631278021500. Starting simulation... +info: Entering event queue @ 631390429500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 632278021500. Starting simulation... +info: Entering event queue @ 632390429500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 633278021500. Starting simulation... +info: Entering event queue @ 633390429500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 634278021500. Starting simulation... +info: Entering event queue @ 634390429500. Starting simulation... switching cpus -info: Entering event queue @ 635277893500. Starting simulation... +info: Entering event queue @ 635390301500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 636277893500. Starting simulation... +info: Entering event queue @ 636390301500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 637390301500. Starting simulation... switching cpus -info: Entering event queue @ 637277893500. Starting simulation... +info: Entering event queue @ 637390309000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 638277893500. Starting simulation... +info: Entering event queue @ 638390309000. Starting simulation... switching cpus -info: Entering event queue @ 639277765500. Starting simulation... +info: Entering event queue @ 639390173500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 640277765500. Starting simulation... +info: Entering event queue @ 640390173500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 641277765500. Starting simulation... +info: Entering event queue @ 641390173500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 642277765500. Starting simulation... +info: Entering event queue @ 642390173500. Starting simulation... switching cpus -info: Entering event queue @ 643277637500. Starting simulation... +info: Entering event queue @ 643390045500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 644277637500. Starting simulation... +info: Entering event queue @ 644390045500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 645277637500. Starting simulation... +info: Entering event queue @ 645390045500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 646277637500. Starting simulation... +info: Entering event queue @ 646390045500. Starting simulation... switching cpus -info: Entering event queue @ 647277509500. Starting simulation... +info: Entering event queue @ 647389917500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 648277509500. Starting simulation... +info: Entering event queue @ 648389917500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 649277509500. Starting simulation... +info: Entering event queue @ 649389917500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 650277509500. Starting simulation... +info: Entering event queue @ 650389917500. Starting simulation... switching cpus -info: Entering event queue @ 651277381500. Starting simulation... +info: Entering event queue @ 651389789500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 652277381500. Starting simulation... +info: Entering event queue @ 652389789500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 653389789500. Starting simulation... switching cpus -info: Entering event queue @ 653277381500. Starting simulation... +info: Entering event queue @ 653389797000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 654277381500. Starting simulation... +info: Entering event queue @ 654389797000. Starting simulation... switching cpus -info: Entering event queue @ 655277253500. Starting simulation... +info: Entering event queue @ 655389661500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 656277253500. Starting simulation... +info: Entering event queue @ 656389661500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 657277253500. Starting simulation... +info: Entering event queue @ 657389661500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 658277253500. Starting simulation... +info: Entering event queue @ 658389661500. Starting simulation... switching cpus -info: Entering event queue @ 659277125500. Starting simulation... +info: Entering event queue @ 659389533500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 660277125500. Starting simulation... +info: Entering event queue @ 660389533500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 661277125500. Starting simulation... +info: Entering event queue @ 661389533500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 662277125500. Starting simulation... +info: Entering event queue @ 662389533500. Starting simulation... switching cpus -info: Entering event queue @ 663276997500. Starting simulation... +info: Entering event queue @ 663389405500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 664276997500. Starting simulation... +info: Entering event queue @ 664389405500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 665276997500. Starting simulation... +info: Entering event queue @ 665389405500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 666276997500. Starting simulation... +info: Entering event queue @ 666389405500. Starting simulation... switching cpus -info: Entering event queue @ 667276869500. Starting simulation... +info: Entering event queue @ 667389277500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 668276869500. Starting simulation... +info: Entering event queue @ 668389277500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 669389277500. Starting simulation... switching cpus -info: Entering event queue @ 669276869500. Starting simulation... +info: Entering event queue @ 669389285000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 670276869500. Starting simulation... +info: Entering event queue @ 670389285000. Starting simulation... switching cpus -info: Entering event queue @ 671276741500. Starting simulation... +info: Entering event queue @ 671389149500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 672276741500. Starting simulation... +info: Entering event queue @ 672389149500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 673276741500. Starting simulation... +info: Entering event queue @ 673389149500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 674276741500. Starting simulation... +info: Entering event queue @ 674389149500. Starting simulation... switching cpus -info: Entering event queue @ 675276613500. Starting simulation... +info: Entering event queue @ 675389021500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 676276613500. Starting simulation... +info: Entering event queue @ 676389021500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 677276613500. Starting simulation... +info: Entering event queue @ 677389021500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 678276613500. Starting simulation... +info: Entering event queue @ 678389021500. Starting simulation... switching cpus -info: Entering event queue @ 679276485500. Starting simulation... +info: Entering event queue @ 679388893500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 680276485500. Starting simulation... +info: Entering event queue @ 680388893500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 681276485500. Starting simulation... +info: Entering event queue @ 681388893500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 682276485500. Starting simulation... +info: Entering event queue @ 682388893500. Starting simulation... switching cpus -info: Entering event queue @ 683276357500. Starting simulation... +info: Entering event queue @ 683388765500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 684276357500. Starting simulation... +info: Entering event queue @ 684388765500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 685388765500. Starting simulation... switching cpus -info: Entering event queue @ 685276357500. Starting simulation... +info: Entering event queue @ 685388773000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 686276357500. Starting simulation... +info: Entering event queue @ 686388773000. Starting simulation... switching cpus -info: Entering event queue @ 687276229500. Starting simulation... +info: Entering event queue @ 687388637500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 688276229500. Starting simulation... +info: Entering event queue @ 688388637500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 689276229500. Starting simulation... +info: Entering event queue @ 689388637500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 690276229500. Starting simulation... +info: Entering event queue @ 690388637500. Starting simulation... switching cpus -info: Entering event queue @ 691276101500. Starting simulation... +info: Entering event queue @ 691388509500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 692276101500. Starting simulation... +info: Entering event queue @ 692388509500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 693276101500. Starting simulation... +info: Entering event queue @ 693388509500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 694276101500. Starting simulation... +info: Entering event queue @ 694388509500. Starting simulation... switching cpus -info: Entering event queue @ 695275973500. Starting simulation... +info: Entering event queue @ 695388381500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 696275973500. Starting simulation... +info: Entering event queue @ 696388381500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 697275973500. Starting simulation... +info: Entering event queue @ 697388381500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 698275973500. Starting simulation... +info: Entering event queue @ 698388381500. Starting simulation... switching cpus -info: Entering event queue @ 699275845500. Starting simulation... +info: Entering event queue @ 699388253500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 700275845500. Starting simulation... +info: Entering event queue @ 700388253500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 701388253500. Starting simulation... switching cpus -info: Entering event queue @ 701275845500. Starting simulation... +info: Entering event queue @ 701388261000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 702275845500. Starting simulation... +info: Entering event queue @ 702388261000. Starting simulation... switching cpus -info: Entering event queue @ 703275717500. Starting simulation... +info: Entering event queue @ 703388125500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 704275717500. Starting simulation... +info: Entering event queue @ 704388125500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 705275717500. Starting simulation... +info: Entering event queue @ 705388125500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 706275717500. Starting simulation... +info: Entering event queue @ 706388125500. Starting simulation... switching cpus -info: Entering event queue @ 707275589500. Starting simulation... +info: Entering event queue @ 707387997500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 708275589500. Starting simulation... +info: Entering event queue @ 708387997500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 709275589500. Starting simulation... +info: Entering event queue @ 709387997500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 710275589500. Starting simulation... +info: Entering event queue @ 710387997500. Starting simulation... switching cpus -info: Entering event queue @ 711275461500. Starting simulation... +info: Entering event queue @ 711387869500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 712275461500. Starting simulation... +info: Entering event queue @ 712387869500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 713275461500. Starting simulation... +info: Entering event queue @ 713387869500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 714275461500. Starting simulation... +info: Entering event queue @ 714387869500. Starting simulation... switching cpus -info: Entering event queue @ 715275333500. Starting simulation... +info: Entering event queue @ 715387741500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 716275333500. Starting simulation... +info: Entering event queue @ 716387741500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 717387741500. Starting simulation... switching cpus -info: Entering event queue @ 717275333500. Starting simulation... +info: Entering event queue @ 717387749000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 718275333500. Starting simulation... +info: Entering event queue @ 718387749000. Starting simulation... switching cpus -info: Entering event queue @ 719275205500. Starting simulation... +info: Entering event queue @ 719387613500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 720275205500. Starting simulation... +info: Entering event queue @ 720387613500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 721275205500. Starting simulation... +info: Entering event queue @ 721387613500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 722275205500. Starting simulation... +info: Entering event queue @ 722387613500. Starting simulation... switching cpus -info: Entering event queue @ 723275077500. Starting simulation... +info: Entering event queue @ 723387485500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 724275077500. Starting simulation... +info: Entering event queue @ 724387485500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 725275077500. Starting simulation... +info: Entering event queue @ 725387485500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 726275077500. Starting simulation... +info: Entering event queue @ 726387485500. Starting simulation... switching cpus -info: Entering event queue @ 727274949500. Starting simulation... +info: Entering event queue @ 727387357500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 728274949500. Starting simulation... +info: Entering event queue @ 728387357500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 729274949500. Starting simulation... +info: Entering event queue @ 729387357500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 730274949500. Starting simulation... +info: Entering event queue @ 730387357500. Starting simulation... switching cpus -info: Entering event queue @ 731274821500. Starting simulation... +info: Entering event queue @ 731387229500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 732274821500. Starting simulation... +info: Entering event queue @ 732387229500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 733387229500. Starting simulation... switching cpus -info: Entering event queue @ 733274821500. Starting simulation... +info: Entering event queue @ 733387237000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 734274821500. Starting simulation... +info: Entering event queue @ 734387237000. Starting simulation... switching cpus -info: Entering event queue @ 735274693500. Starting simulation... +info: Entering event queue @ 735387101500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 736274693500. Starting simulation... +info: Entering event queue @ 736387101500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 737274693500. Starting simulation... +info: Entering event queue @ 737387101500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 738274693500. Starting simulation... +info: Entering event queue @ 738387101500. Starting simulation... switching cpus -info: Entering event queue @ 739274565500. Starting simulation... +info: Entering event queue @ 739386973500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 740274565500. Starting simulation... +info: Entering event queue @ 740386973500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 741274565500. Starting simulation... +info: Entering event queue @ 741386973500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 742274565500. Starting simulation... +info: Entering event queue @ 742386973500. Starting simulation... switching cpus -info: Entering event queue @ 743274437500. Starting simulation... +info: Entering event queue @ 743386845500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 744274437500. Starting simulation... +info: Entering event queue @ 744386845500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 745274437500. Starting simulation... +info: Entering event queue @ 745386845500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 746274437500. Starting simulation... +info: Entering event queue @ 746386845500. Starting simulation... switching cpus -info: Entering event queue @ 747274309500. Starting simulation... +info: Entering event queue @ 747386717500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 748274309500. Starting simulation... +info: Entering event queue @ 748386717500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 749386717500. Starting simulation... switching cpus -info: Entering event queue @ 749274309500. Starting simulation... +info: Entering event queue @ 749386725000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 750274309500. Starting simulation... +info: Entering event queue @ 750386725000. Starting simulation... switching cpus -info: Entering event queue @ 751274181500. Starting simulation... +info: Entering event queue @ 751386589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 752274181500. Starting simulation... +info: Entering event queue @ 752386589500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 753274181500. Starting simulation... +info: Entering event queue @ 753386589500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 754274181500. Starting simulation... +info: Entering event queue @ 754386589500. Starting simulation... switching cpus -info: Entering event queue @ 755274053500. Starting simulation... +info: Entering event queue @ 755386461500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 756274053500. Starting simulation... +info: Entering event queue @ 756386461500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 757274053500. Starting simulation... +info: Entering event queue @ 757386461500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 758274053500. Starting simulation... +info: Entering event queue @ 758386461500. Starting simulation... switching cpus -info: Entering event queue @ 759273925500. Starting simulation... +info: Entering event queue @ 759386333500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 760273925500. Starting simulation... +info: Entering event queue @ 760386333500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 761273925500. Starting simulation... +info: Entering event queue @ 761386333500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 762273925500. Starting simulation... +info: Entering event queue @ 762386333500. Starting simulation... switching cpus -info: Entering event queue @ 763273797500. Starting simulation... +info: Entering event queue @ 763386205500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 764273797500. Starting simulation... +info: Entering event queue @ 764386205500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 765386205500. Starting simulation... switching cpus -info: Entering event queue @ 765273797500. Starting simulation... +info: Entering event queue @ 765386213000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 766273797500. Starting simulation... +info: Entering event queue @ 766386213000. Starting simulation... switching cpus -info: Entering event queue @ 767273669500. Starting simulation... +info: Entering event queue @ 767386077500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 768273669500. Starting simulation... +info: Entering event queue @ 768386077500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 769273669500. Starting simulation... +info: Entering event queue @ 769386077500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 770273669500. Starting simulation... +info: Entering event queue @ 770386077500. Starting simulation... switching cpus -info: Entering event queue @ 771273541500. Starting simulation... +info: Entering event queue @ 771385949500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 772273541500. Starting simulation... +info: Entering event queue @ 772385949500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 773273541500. Starting simulation... +info: Entering event queue @ 773385949500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 774273541500. Starting simulation... +info: Entering event queue @ 774385949500. Starting simulation... switching cpus -info: Entering event queue @ 775273413500. Starting simulation... +info: Entering event queue @ 775385821500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 776273413500. Starting simulation... +info: Entering event queue @ 776385821500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 777273413500. Starting simulation... +info: Entering event queue @ 777385821500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 778273413500. Starting simulation... +info: Entering event queue @ 778385821500. Starting simulation... switching cpus -info: Entering event queue @ 779273285500. Starting simulation... +info: Entering event queue @ 779385693500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 780273285500. Starting simulation... +info: Entering event queue @ 780385693500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 781385693500. Starting simulation... switching cpus -info: Entering event queue @ 781273285500. Starting simulation... +info: Entering event queue @ 781385701000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 782273285500. Starting simulation... +info: Entering event queue @ 782385701000. Starting simulation... switching cpus -info: Entering event queue @ 783273157500. Starting simulation... +info: Entering event queue @ 783385565500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 784273157500. Starting simulation... +info: Entering event queue @ 784385565500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 785273157500. Starting simulation... +info: Entering event queue @ 785385565500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 786273157500. Starting simulation... +info: Entering event queue @ 786385565500. Starting simulation... switching cpus -info: Entering event queue @ 787273029500. Starting simulation... +info: Entering event queue @ 787385437500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 788273029500. Starting simulation... +info: Entering event queue @ 788385437500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 789273029500. Starting simulation... +info: Entering event queue @ 789385437500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 790273029500. Starting simulation... +info: Entering event queue @ 790385437500. Starting simulation... switching cpus -info: Entering event queue @ 791272901500. Starting simulation... +info: Entering event queue @ 791385309500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 792272901500. Starting simulation... +info: Entering event queue @ 792385309500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 793272901500. Starting simulation... +info: Entering event queue @ 793385309500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 794272901500. Starting simulation... +info: Entering event queue @ 794385309500. Starting simulation... switching cpus -info: Entering event queue @ 795272773500. Starting simulation... +info: Entering event queue @ 795385181500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 796272773500. Starting simulation... +info: Entering event queue @ 796385181500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 797385181500. Starting simulation... switching cpus -info: Entering event queue @ 797272773500. Starting simulation... +info: Entering event queue @ 797385189000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 798272773500. Starting simulation... +info: Entering event queue @ 798385189000. Starting simulation... switching cpus -info: Entering event queue @ 799272645500. Starting simulation... +info: Entering event queue @ 799385053500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 800272645500. Starting simulation... +info: Entering event queue @ 800385053500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 801272645500. Starting simulation... +info: Entering event queue @ 801385053500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 802272645500. Starting simulation... +info: Entering event queue @ 802385053500. Starting simulation... switching cpus -info: Entering event queue @ 803272517500. Starting simulation... +info: Entering event queue @ 803384925500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 804272517500. Starting simulation... +info: Entering event queue @ 804384925500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 805272517500. Starting simulation... +info: Entering event queue @ 805384925500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 806272517500. Starting simulation... +info: Entering event queue @ 806384925500. Starting simulation... switching cpus -info: Entering event queue @ 807272389500. Starting simulation... +info: Entering event queue @ 807384797500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 808272389500. Starting simulation... +info: Entering event queue @ 808384797500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 809272389500. Starting simulation... +info: Entering event queue @ 809384797500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 810272389500. Starting simulation... +info: Entering event queue @ 810384797500. Starting simulation... switching cpus -info: Entering event queue @ 811272261500. Starting simulation... +info: Entering event queue @ 811384669500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 812272261500. Starting simulation... +info: Entering event queue @ 812384669500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 813272261500. Starting simulation... +info: Entering event queue @ 813384669500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 814272261500. Starting simulation... +info: Entering event queue @ 814384669500. Starting simulation... switching cpus -info: Entering event queue @ 815272133500. Starting simulation... +info: Entering event queue @ 815384541500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 816272133500. Starting simulation... +info: Entering event queue @ 816384541500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 817272133500. Starting simulation... +info: Entering event queue @ 817384541500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 818272133500. Starting simulation... +info: Entering event queue @ 818384541500. Starting simulation... switching cpus -info: Entering event queue @ 819272005500. Starting simulation... +info: Entering event queue @ 819384413500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 820272005500. Starting simulation... +info: Entering event queue @ 820384413500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 821272005500. Starting simulation... +info: Entering event queue @ 821384413500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 822272005500. Starting simulation... +info: Entering event queue @ 822384413500. Starting simulation... switching cpus -info: Entering event queue @ 823271877500. Starting simulation... +info: Entering event queue @ 823384285500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 824271877500. Starting simulation... +info: Entering event queue @ 824384285500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 825271877500. Starting simulation... +info: Entering event queue @ 825384285500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 826271877500. Starting simulation... +info: Entering event queue @ 826384285500. Starting simulation... switching cpus -info: Entering event queue @ 827271749500. Starting simulation... +info: Entering event queue @ 827384157500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 828271749500. Starting simulation... +info: Entering event queue @ 828384157500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 829271749500. Starting simulation... +info: Entering event queue @ 829384157500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 830271749500. Starting simulation... +info: Entering event queue @ 830384157500. Starting simulation... switching cpus -info: Entering event queue @ 831271621500. Starting simulation... +info: Entering event queue @ 831384029500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 832271621500. Starting simulation... +info: Entering event queue @ 832384029500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 833271621500. Starting simulation... +info: Entering event queue @ 833384029500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 834271621500. Starting simulation... +info: Entering event queue @ 834384029500. Starting simulation... switching cpus -info: Entering event queue @ 835271493500. Starting simulation... +info: Entering event queue @ 835383901500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 836271493500. Starting simulation... +info: Entering event queue @ 836383901500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 837271493500. Starting simulation... +info: Entering event queue @ 837383901500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 838271493500. Starting simulation... +info: Entering event queue @ 838383901500. Starting simulation... switching cpus -info: Entering event queue @ 839271365500. Starting simulation... +info: Entering event queue @ 839383773500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 840271365500. Starting simulation... +info: Entering event queue @ 840383773500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 841271365500. Starting simulation... +info: Entering event queue @ 841383773500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 842271365500. Starting simulation... +info: Entering event queue @ 842383773500. Starting simulation... switching cpus -info: Entering event queue @ 843271237500. Starting simulation... +info: Entering event queue @ 843383645500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 844271237500. Starting simulation... +info: Entering event queue @ 844383645500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 845383645500. Starting simulation... switching cpus -info: Entering event queue @ 845271237500. Starting simulation... +info: Entering event queue @ 845383653000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 846271237500. Starting simulation... +info: Entering event queue @ 846383653000. Starting simulation... switching cpus -info: Entering event queue @ 847271109500. Starting simulation... +info: Entering event queue @ 847383517500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 848271109500. Starting simulation... +info: Entering event queue @ 848383517500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 849271109500. Starting simulation... +info: Entering event queue @ 849383517500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 850271109500. Starting simulation... +info: Entering event queue @ 850383517500. Starting simulation... switching cpus -info: Entering event queue @ 851270981500. Starting simulation... +info: Entering event queue @ 851383389500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 852270981500. Starting simulation... +info: Entering event queue @ 852383389500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 853270981500. Starting simulation... +info: Entering event queue @ 853383389500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 854270981500. Starting simulation... +info: Entering event queue @ 854383389500. Starting simulation... switching cpus -info: Entering event queue @ 855270853500. Starting simulation... +info: Entering event queue @ 855383261500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 856270853500. Starting simulation... +info: Entering event queue @ 856383261500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 857270853500. Starting simulation... +info: Entering event queue @ 857383261500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 858270853500. Starting simulation... +info: Entering event queue @ 858383261500. Starting simulation... switching cpus -info: Entering event queue @ 859270725500. Starting simulation... +info: Entering event queue @ 859383133500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 860270725500. Starting simulation... +info: Entering event queue @ 860383133500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 861383133500. Starting simulation... switching cpus -info: Entering event queue @ 861270725500. Starting simulation... +info: Entering event queue @ 861383141000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 862270725500. Starting simulation... +info: Entering event queue @ 862383141000. Starting simulation... switching cpus -info: Entering event queue @ 863270597500. Starting simulation... +info: Entering event queue @ 863383005500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 864270597500. Starting simulation... +info: Entering event queue @ 864383005500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 865270597500. Starting simulation... +info: Entering event queue @ 865383005500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 866270597500. Starting simulation... +info: Entering event queue @ 866383005500. Starting simulation... switching cpus -info: Entering event queue @ 867270469500. Starting simulation... +info: Entering event queue @ 867382877500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 868270469500. Starting simulation... +info: Entering event queue @ 868382877500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 869270469500. Starting simulation... +info: Entering event queue @ 869382877500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 870270469500. Starting simulation... +info: Entering event queue @ 870382877500. Starting simulation... switching cpus -info: Entering event queue @ 871270341500. Starting simulation... +info: Entering event queue @ 871382749500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 872270341500. Starting simulation... +info: Entering event queue @ 872382749500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 873270341500. Starting simulation... +info: Entering event queue @ 873382749500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 874270341500. Starting simulation... +info: Entering event queue @ 874382749500. Starting simulation... switching cpus -info: Entering event queue @ 875270213500. Starting simulation... +info: Entering event queue @ 875382621500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 876270213500. Starting simulation... +info: Entering event queue @ 876382621500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 877382621500. Starting simulation... switching cpus -info: Entering event queue @ 877270213500. Starting simulation... +info: Entering event queue @ 877382629000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 878270213500. Starting simulation... +info: Entering event queue @ 878382629000. Starting simulation... switching cpus -info: Entering event queue @ 879270085500. Starting simulation... +info: Entering event queue @ 879382493500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 880270085500. Starting simulation... +info: Entering event queue @ 880382493500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 881270085500. Starting simulation... +info: Entering event queue @ 881382493500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 882270085500. Starting simulation... +info: Entering event queue @ 882382493500. Starting simulation... switching cpus -info: Entering event queue @ 883269957500. Starting simulation... +info: Entering event queue @ 883382365500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 884269957500. Starting simulation... +info: Entering event queue @ 884382365500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 885269957500. Starting simulation... +info: Entering event queue @ 885382365500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 886269957500. Starting simulation... +info: Entering event queue @ 886382365500. Starting simulation... switching cpus -info: Entering event queue @ 887269829500. Starting simulation... +info: Entering event queue @ 887382237500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 888269829500. Starting simulation... +info: Entering event queue @ 888382237500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 889269829500. Starting simulation... +info: Entering event queue @ 889382237500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 890269829500. Starting simulation... +info: Entering event queue @ 890382237500. Starting simulation... switching cpus -info: Entering event queue @ 891269701500. Starting simulation... +info: Entering event queue @ 891382109500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 892269701500. Starting simulation... +info: Entering event queue @ 892382109500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 893382109500. Starting simulation... switching cpus -info: Entering event queue @ 893269701500. Starting simulation... +info: Entering event queue @ 893382117000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 894269701500. Starting simulation... +info: Entering event queue @ 894382117000. Starting simulation... switching cpus -info: Entering event queue @ 895269573500. Starting simulation... +info: Entering event queue @ 895381981500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 896269573500. Starting simulation... +info: Entering event queue @ 896381981500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 897269573500. Starting simulation... +info: Entering event queue @ 897381981500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 898269573500. Starting simulation... +info: Entering event queue @ 898381981500. Starting simulation... switching cpus -info: Entering event queue @ 899269445500. Starting simulation... +info: Entering event queue @ 899381853500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 900269445500. Starting simulation... +info: Entering event queue @ 900381853500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 901269445500. Starting simulation... +info: Entering event queue @ 901381853500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 902269445500. Starting simulation... +info: Entering event queue @ 902381853500. Starting simulation... switching cpus -info: Entering event queue @ 903269317500. Starting simulation... +info: Entering event queue @ 903381725500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 904269317500. Starting simulation... +info: Entering event queue @ 904381725500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 905269317500. Starting simulation... +info: Entering event queue @ 905381725500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 906269317500. Starting simulation... +info: Entering event queue @ 906381725500. Starting simulation... switching cpus -info: Entering event queue @ 907269189500. Starting simulation... +info: Entering event queue @ 907381597500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 908269189500. Starting simulation... +info: Entering event queue @ 908381597500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 909381597500. Starting simulation... switching cpus -info: Entering event queue @ 909269189500. Starting simulation... +info: Entering event queue @ 909381605000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 910269189500. Starting simulation... +info: Entering event queue @ 910381605000. Starting simulation... switching cpus -info: Entering event queue @ 911269061500. Starting simulation... +info: Entering event queue @ 911381469500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 912269061500. Starting simulation... +info: Entering event queue @ 912381469500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 913269061500. Starting simulation... +info: Entering event queue @ 913381469500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 914269061500. Starting simulation... +info: Entering event queue @ 914381469500. Starting simulation... switching cpus -info: Entering event queue @ 915268933500. Starting simulation... +info: Entering event queue @ 915381341500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 916268933500. Starting simulation... +info: Entering event queue @ 916381341500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 917268933500. Starting simulation... +info: Entering event queue @ 917381341500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 918268933500. Starting simulation... +info: Entering event queue @ 918381341500. Starting simulation... switching cpus -info: Entering event queue @ 919268805500. Starting simulation... +info: Entering event queue @ 919381213500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 920268805500. Starting simulation... +info: Entering event queue @ 920381213500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 921268805500. Starting simulation... +info: Entering event queue @ 921381213500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 922268805500. Starting simulation... +info: Entering event queue @ 922381213500. Starting simulation... switching cpus -info: Entering event queue @ 923268677500. Starting simulation... +info: Entering event queue @ 923381085500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 924268677500. Starting simulation... +info: Entering event queue @ 924381085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 925381085500. Starting simulation... switching cpus -info: Entering event queue @ 925268677500. Starting simulation... +info: Entering event queue @ 925381093000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 926268677500. Starting simulation... +info: Entering event queue @ 926381093000. Starting simulation... switching cpus -info: Entering event queue @ 927268549500. Starting simulation... +info: Entering event queue @ 927380957500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 928268549500. Starting simulation... +info: Entering event queue @ 928380957500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 929268549500. Starting simulation... +info: Entering event queue @ 929380957500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 930268549500. Starting simulation... +info: Entering event queue @ 930380957500. Starting simulation... switching cpus -info: Entering event queue @ 931268421500. Starting simulation... +info: Entering event queue @ 931380829500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 932268421500. Starting simulation... +info: Entering event queue @ 932380829500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 933268421500. Starting simulation... +info: Entering event queue @ 933380829500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 934268421500. Starting simulation... +info: Entering event queue @ 934380829500. Starting simulation... switching cpus -info: Entering event queue @ 935268293500. Starting simulation... +info: Entering event queue @ 935380701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 936268293500. Starting simulation... +info: Entering event queue @ 936380701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 937268293500. Starting simulation... +info: Entering event queue @ 937380701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 938268293500. Starting simulation... +info: Entering event queue @ 938380701500. Starting simulation... switching cpus -info: Entering event queue @ 939268165500. Starting simulation... +info: Entering event queue @ 939380573500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 940268165500. Starting simulation... +info: Entering event queue @ 940380573500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 941380573500. Starting simulation... switching cpus -info: Entering event queue @ 941268165500. Starting simulation... +info: Entering event queue @ 941380581000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 942268165500. Starting simulation... +info: Entering event queue @ 942380581000. Starting simulation... switching cpus -info: Entering event queue @ 943268037500. Starting simulation... +info: Entering event queue @ 943380445500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 944268037500. Starting simulation... +info: Entering event queue @ 944380445500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 945268037500. Starting simulation... +info: Entering event queue @ 945380445500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 946268037500. Starting simulation... +info: Entering event queue @ 946380445500. Starting simulation... switching cpus -info: Entering event queue @ 947267909500. Starting simulation... +info: Entering event queue @ 947380317500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 948267909500. Starting simulation... +info: Entering event queue @ 948380317500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 949267909500. Starting simulation... +info: Entering event queue @ 949380317500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 950267909500. Starting simulation... +info: Entering event queue @ 950380317500. Starting simulation... switching cpus -info: Entering event queue @ 951267781500. Starting simulation... +info: Entering event queue @ 951380189500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 952267781500. Starting simulation... +info: Entering event queue @ 952380189500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 953267781500. Starting simulation... +info: Entering event queue @ 953380189500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 954267781500. Starting simulation... +info: Entering event queue @ 954380189500. Starting simulation... switching cpus -info: Entering event queue @ 955267653500. Starting simulation... +info: Entering event queue @ 955380061500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 956267653500. Starting simulation... +info: Entering event queue @ 956380061500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 957380061500. Starting simulation... switching cpus -info: Entering event queue @ 957267653500. Starting simulation... +info: Entering event queue @ 957380069000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 958267653500. Starting simulation... +info: Entering event queue @ 958380069000. Starting simulation... switching cpus -info: Entering event queue @ 959267525500. Starting simulation... +info: Entering event queue @ 959379933500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 960267525500. Starting simulation... +info: Entering event queue @ 960379933500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 961267525500. Starting simulation... +info: Entering event queue @ 961379933500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 962267525500. Starting simulation... +info: Entering event queue @ 962379933500. Starting simulation... switching cpus -info: Entering event queue @ 963267397500. Starting simulation... +info: Entering event queue @ 963379805500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 964267397500. Starting simulation... +info: Entering event queue @ 964379805500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 965267397500. Starting simulation... +info: Entering event queue @ 965379805500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 966267397500. Starting simulation... +info: Entering event queue @ 966379805500. Starting simulation... switching cpus -info: Entering event queue @ 967267269500. Starting simulation... +info: Entering event queue @ 967379677500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 968267269500. Starting simulation... +info: Entering event queue @ 968379677500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 969267269500. Starting simulation... +info: Entering event queue @ 969379677500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 970267269500. Starting simulation... +info: Entering event queue @ 970379677500. Starting simulation... switching cpus -info: Entering event queue @ 971267141500. Starting simulation... +info: Entering event queue @ 971379549500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 972267141500. Starting simulation... +info: Entering event queue @ 972379549500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 973379549500. Starting simulation... switching cpus -info: Entering event queue @ 973267141500. Starting simulation... +info: Entering event queue @ 973379557000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 974267141500. Starting simulation... +info: Entering event queue @ 974379557000. Starting simulation... switching cpus -info: Entering event queue @ 975267013500. Starting simulation... +info: Entering event queue @ 975379421500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 976267013500. Starting simulation... +info: Entering event queue @ 976379421500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 977267013500. Starting simulation... +info: Entering event queue @ 977379421500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 978267013500. Starting simulation... +info: Entering event queue @ 978379421500. Starting simulation... switching cpus -info: Entering event queue @ 979266885500. Starting simulation... +info: Entering event queue @ 979379293500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 980266885500. Starting simulation... +info: Entering event queue @ 980379293500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 981266885500. Starting simulation... +info: Entering event queue @ 981379293500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 982266885500. Starting simulation... +info: Entering event queue @ 982379293500. Starting simulation... switching cpus -info: Entering event queue @ 983266757500. Starting simulation... +info: Entering event queue @ 983379165500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 984266757500. Starting simulation... +info: Entering event queue @ 984379165500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 985266757500. Starting simulation... +info: Entering event queue @ 985379165500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 986266757500. Starting simulation... +info: Entering event queue @ 986379165500. Starting simulation... switching cpus -info: Entering event queue @ 987266629500. Starting simulation... +info: Entering event queue @ 987379037500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 988266629500. Starting simulation... +info: Entering event queue @ 988379037500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 989379037500. Starting simulation... switching cpus -info: Entering event queue @ 989266629500. Starting simulation... +info: Entering event queue @ 989379045000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 990266629500. Starting simulation... +info: Entering event queue @ 990379045000. Starting simulation... switching cpus -info: Entering event queue @ 991266501500. Starting simulation... +info: Entering event queue @ 991378909500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 992266501500. Starting simulation... +info: Entering event queue @ 992378909500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 993266501500. Starting simulation... +info: Entering event queue @ 993378909500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 994266501500. Starting simulation... +info: Entering event queue @ 994378909500. Starting simulation... switching cpus -info: Entering event queue @ 995266373500. Starting simulation... +info: Entering event queue @ 995378781500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 996266373500. Starting simulation... +info: Entering event queue @ 996378781500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 997266373500. Starting simulation... +info: Entering event queue @ 997378781500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 998266373500. Starting simulation... +info: Entering event queue @ 998378781500. Starting simulation... switching cpus -info: Entering event queue @ 999266245500. Starting simulation... +info: Entering event queue @ 999378653500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1000266245500. Starting simulation... +info: Entering event queue @ 1000378653500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1001266245500. Starting simulation... +info: Entering event queue @ 1001378653500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1002266245500. Starting simulation... +info: Entering event queue @ 1002378653500. Starting simulation... switching cpus -info: Entering event queue @ 1003266117500. Starting simulation... +info: Entering event queue @ 1003378525500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1004266117500. Starting simulation... +info: Entering event queue @ 1004378525500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1005378525500. Starting simulation... switching cpus -info: Entering event queue @ 1005266117500. Starting simulation... +info: Entering event queue @ 1005378533000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1006266117500. Starting simulation... +info: Entering event queue @ 1006378533000. Starting simulation... switching cpus -info: Entering event queue @ 1007265989500. Starting simulation... +info: Entering event queue @ 1007378397500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1008265989500. Starting simulation... +info: Entering event queue @ 1008378397500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1009265989500. Starting simulation... +info: Entering event queue @ 1009378397500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1010265989500. Starting simulation... +info: Entering event queue @ 1010378397500. Starting simulation... switching cpus -info: Entering event queue @ 1011265861500. Starting simulation... +info: Entering event queue @ 1011378269500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1012265861500. Starting simulation... +info: Entering event queue @ 1012378269500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1013265861500. Starting simulation... +info: Entering event queue @ 1013378269500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1014265861500. Starting simulation... +info: Entering event queue @ 1014378269500. Starting simulation... switching cpus -info: Entering event queue @ 1015265733500. Starting simulation... +info: Entering event queue @ 1015378141500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1016265733500. Starting simulation... +info: Entering event queue @ 1016378141500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1017265733500. Starting simulation... +info: Entering event queue @ 1017378141500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1018265733500. Starting simulation... +info: Entering event queue @ 1018378141500. Starting simulation... switching cpus -info: Entering event queue @ 1019265605500. Starting simulation... +info: Entering event queue @ 1019378013500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1020265605500. Starting simulation... +info: Entering event queue @ 1020378013500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1021378013500. Starting simulation... switching cpus -info: Entering event queue @ 1021265605500. Starting simulation... +info: Entering event queue @ 1021378021000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1022265605500. Starting simulation... +info: Entering event queue @ 1022378021000. Starting simulation... switching cpus -info: Entering event queue @ 1023265477500. Starting simulation... +info: Entering event queue @ 1023377885500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1024265477500. Starting simulation... +info: Entering event queue @ 1024377885500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1025265477500. Starting simulation... +info: Entering event queue @ 1025377885500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1026265477500. Starting simulation... +info: Entering event queue @ 1026377885500. Starting simulation... switching cpus -info: Entering event queue @ 1027265349500. Starting simulation... +info: Entering event queue @ 1027377757500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1028265349500. Starting simulation... +info: Entering event queue @ 1028377757500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1029265349500. Starting simulation... +info: Entering event queue @ 1029377757500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1030265349500. Starting simulation... +info: Entering event queue @ 1030377757500. Starting simulation... switching cpus -info: Entering event queue @ 1031265221500. Starting simulation... +info: Entering event queue @ 1031377629500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1032265221500. Starting simulation... +info: Entering event queue @ 1032377629500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1033265221500. Starting simulation... +info: Entering event queue @ 1033377629500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1034265221500. Starting simulation... +info: Entering event queue @ 1034377629500. Starting simulation... switching cpus -info: Entering event queue @ 1035265093500. Starting simulation... +info: Entering event queue @ 1035377501500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1036265093500. Starting simulation... +info: Entering event queue @ 1036377501500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1037377501500. Starting simulation... switching cpus -info: Entering event queue @ 1037265093500. Starting simulation... +info: Entering event queue @ 1037377509000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1038265093500. Starting simulation... +info: Entering event queue @ 1038377509000. Starting simulation... switching cpus -info: Entering event queue @ 1039264965500. Starting simulation... +info: Entering event queue @ 1039377373500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1040264965500. Starting simulation... +info: Entering event queue @ 1040377373500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1041264965500. Starting simulation... +info: Entering event queue @ 1041377373500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1042264965500. Starting simulation... +info: Entering event queue @ 1042377373500. Starting simulation... switching cpus -info: Entering event queue @ 1043264837500. Starting simulation... +info: Entering event queue @ 1043377245500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1044264837500. Starting simulation... +info: Entering event queue @ 1044377245500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1045264837500. Starting simulation... +info: Entering event queue @ 1045377245500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1046264837500. Starting simulation... +info: Entering event queue @ 1046377245500. Starting simulation... switching cpus -info: Entering event queue @ 1047264709500. Starting simulation... +info: Entering event queue @ 1047377117500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1048264709500. Starting simulation... +info: Entering event queue @ 1048377117500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1049264709500. Starting simulation... +info: Entering event queue @ 1049377117500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1050264709500. Starting simulation... +info: Entering event queue @ 1050377117500. Starting simulation... switching cpus -info: Entering event queue @ 1051264581500. Starting simulation... +info: Entering event queue @ 1051376989500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1052264581500. Starting simulation... +info: Entering event queue @ 1052376989500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1053376989500. Starting simulation... switching cpus -info: Entering event queue @ 1053264581500. Starting simulation... +info: Entering event queue @ 1053376997000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1054264581500. Starting simulation... +info: Entering event queue @ 1054376997000. Starting simulation... switching cpus -info: Entering event queue @ 1055264453500. Starting simulation... +info: Entering event queue @ 1055376861500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1056264453500. Starting simulation... +info: Entering event queue @ 1056376861500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1057264453500. Starting simulation... +info: Entering event queue @ 1057376861500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1058264453500. Starting simulation... +info: Entering event queue @ 1058376861500. Starting simulation... switching cpus -info: Entering event queue @ 1059264325500. Starting simulation... +info: Entering event queue @ 1059376733500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1060264325500. Starting simulation... +info: Entering event queue @ 1060376733500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1061264325500. Starting simulation... +info: Entering event queue @ 1061376733500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1062264325500. Starting simulation... +info: Entering event queue @ 1062376733500. Starting simulation... switching cpus -info: Entering event queue @ 1063264197500. Starting simulation... +info: Entering event queue @ 1063376605500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1064264197500. Starting simulation... +info: Entering event queue @ 1064376605500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1065264197500. Starting simulation... +info: Entering event queue @ 1065376605500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1066264197500. Starting simulation... +info: Entering event queue @ 1066376605500. Starting simulation... switching cpus -info: Entering event queue @ 1067264069500. Starting simulation... +info: Entering event queue @ 1067376477500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1068264069500. Starting simulation... +info: Entering event queue @ 1068376477500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1069376477500. Starting simulation... switching cpus -info: Entering event queue @ 1069264069500. Starting simulation... +info: Entering event queue @ 1069376485000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1070264069500. Starting simulation... +info: Entering event queue @ 1070376485000. Starting simulation... switching cpus -info: Entering event queue @ 1071263941500. Starting simulation... +info: Entering event queue @ 1071376349500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1072263941500. Starting simulation... +info: Entering event queue @ 1072376349500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1073263941500. Starting simulation... +info: Entering event queue @ 1073376349500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1074263941500. Starting simulation... +info: Entering event queue @ 1074376349500. Starting simulation... switching cpus -info: Entering event queue @ 1075263813500. Starting simulation... +info: Entering event queue @ 1075376221500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1076263813500. Starting simulation... +info: Entering event queue @ 1076376221500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1077263813500. Starting simulation... +info: Entering event queue @ 1077376221500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1078263813500. Starting simulation... +info: Entering event queue @ 1078376221500. Starting simulation... switching cpus -info: Entering event queue @ 1079263685500. Starting simulation... +info: Entering event queue @ 1079376093500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1080263685500. Starting simulation... +info: Entering event queue @ 1080376093500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1081263685500. Starting simulation... +info: Entering event queue @ 1081376093500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1082263685500. Starting simulation... +info: Entering event queue @ 1082376093500. Starting simulation... switching cpus -info: Entering event queue @ 1083263557500. Starting simulation... +info: Entering event queue @ 1083375965500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1084263557500. Starting simulation... +info: Entering event queue @ 1084375965500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1085375965500. Starting simulation... switching cpus -info: Entering event queue @ 1085263557500. Starting simulation... +info: Entering event queue @ 1085375973000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1086263557500. Starting simulation... +info: Entering event queue @ 1086375973000. Starting simulation... switching cpus -info: Entering event queue @ 1087263429500. Starting simulation... +info: Entering event queue @ 1087375837500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1088263429500. Starting simulation... +info: Entering event queue @ 1088375837500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1089375837500. Starting simulation... switching cpus -info: Entering event queue @ 1089263429500. Starting simulation... +info: Entering event queue @ 1089375845000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1090263429500. Starting simulation... +info: Entering event queue @ 1090375845000. Starting simulation... switching cpus -info: Entering event queue @ 1091263301500. Starting simulation... +info: Entering event queue @ 1091375709500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1092263301500. Starting simulation... +info: Entering event queue @ 1092375709500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1093263301500. Starting simulation... +info: Entering event queue @ 1093375709500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1094263301500. Starting simulation... +info: Entering event queue @ 1094375709500. Starting simulation... switching cpus -info: Entering event queue @ 1095263173500. Starting simulation... +info: Entering event queue @ 1095375581500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1096263173500. Starting simulation... +info: Entering event queue @ 1096375581500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1097263173500. Starting simulation... +info: Entering event queue @ 1097375581500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1098263173500. Starting simulation... +info: Entering event queue @ 1098375581500. Starting simulation... switching cpus -info: Entering event queue @ 1099263045500. Starting simulation... +info: Entering event queue @ 1099375453500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1100263045500. Starting simulation... +info: Entering event queue @ 1100375453500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1101375453500. Starting simulation... switching cpus -info: Entering event queue @ 1101263045500. Starting simulation... +info: Entering event queue @ 1101375461000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1102263045500. Starting simulation... +info: Entering event queue @ 1102375461000. Starting simulation... switching cpus -info: Entering event queue @ 1103262917500. Starting simulation... +info: Entering event queue @ 1103375325500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1104262917500. Starting simulation... +info: Entering event queue @ 1104375325500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1105262917500. Starting simulation... +info: Entering event queue @ 1105375325500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1106262917500. Starting simulation... +info: Entering event queue @ 1106375325500. Starting simulation... switching cpus -info: Entering event queue @ 1107262789500. Starting simulation... +info: Entering event queue @ 1107375197500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1108262789500. Starting simulation... +info: Entering event queue @ 1108375197500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1109262789500. Starting simulation... +info: Entering event queue @ 1109375197500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1110262789500. Starting simulation... +info: Entering event queue @ 1110375197500. Starting simulation... switching cpus -info: Entering event queue @ 1111262661500. Starting simulation... +info: Entering event queue @ 1111375069500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1112262661500. Starting simulation... +info: Entering event queue @ 1112375069500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1113262661500. Starting simulation... +info: Entering event queue @ 1113375069500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1114262661500. Starting simulation... +info: Entering event queue @ 1114375069500. Starting simulation... switching cpus -info: Entering event queue @ 1115262533500. Starting simulation... +info: Entering event queue @ 1115374941500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1116262533500. Starting simulation... +info: Entering event queue @ 1116374941500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1117374941500. Starting simulation... switching cpus -info: Entering event queue @ 1117262533500. Starting simulation... +info: Entering event queue @ 1117374949000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1118262533500. Starting simulation... +info: Entering event queue @ 1118374949000. Starting simulation... switching cpus -info: Entering event queue @ 1119262405500. Starting simulation... +info: Entering event queue @ 1119374813500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1120262405500. Starting simulation... +info: Entering event queue @ 1120374813500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1121262405500. Starting simulation... +info: Entering event queue @ 1121374813500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1122262405500. Starting simulation... +info: Entering event queue @ 1122374813500. Starting simulation... switching cpus -info: Entering event queue @ 1123262277500. Starting simulation... +info: Entering event queue @ 1123374685500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1124262277500. Starting simulation... +info: Entering event queue @ 1124374685500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1125262277500. Starting simulation... +info: Entering event queue @ 1125374685500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1126262277500. Starting simulation... +info: Entering event queue @ 1126374685500. Starting simulation... switching cpus -info: Entering event queue @ 1127262149500. Starting simulation... +info: Entering event queue @ 1127374557500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1128262149500. Starting simulation... +info: Entering event queue @ 1128374557500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1129262149500. Starting simulation... +info: Entering event queue @ 1129374557500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1130262149500. Starting simulation... +info: Entering event queue @ 1130374557500. Starting simulation... switching cpus -info: Entering event queue @ 1131262021500. Starting simulation... +info: Entering event queue @ 1131374429500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1132262021500. Starting simulation... +info: Entering event queue @ 1132374429500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1133374429500. Starting simulation... switching cpus -info: Entering event queue @ 1133262021500. Starting simulation... +info: Entering event queue @ 1133374437000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1134262021500. Starting simulation... +info: Entering event queue @ 1134374437000. Starting simulation... switching cpus -info: Entering event queue @ 1135261893500. Starting simulation... +info: Entering event queue @ 1135374301500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1136261893500. Starting simulation... +info: Entering event queue @ 1136374301500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1137261893500. Starting simulation... +info: Entering event queue @ 1137374301500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1138261893500. Starting simulation... +info: Entering event queue @ 1138374301500. Starting simulation... switching cpus -info: Entering event queue @ 1139261765500. Starting simulation... +info: Entering event queue @ 1139374173500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1140261765500. Starting simulation... +info: Entering event queue @ 1140374173500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1141261765500. Starting simulation... +info: Entering event queue @ 1141374173500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1142261765500. Starting simulation... +info: Entering event queue @ 1142374173500. Starting simulation... switching cpus -info: Entering event queue @ 1143261637500. Starting simulation... +info: Entering event queue @ 1143374045500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1144261637500. Starting simulation... +info: Entering event queue @ 1144374045500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1145261637500. Starting simulation... +info: Entering event queue @ 1145374045500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1146261637500. Starting simulation... +info: Entering event queue @ 1146374045500. Starting simulation... switching cpus -info: Entering event queue @ 1147261509500. Starting simulation... +info: Entering event queue @ 1147373917500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1148261509500. Starting simulation... +info: Entering event queue @ 1148373917500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1149373917500. Starting simulation... switching cpus -info: Entering event queue @ 1149261509500. Starting simulation... +info: Entering event queue @ 1149373925000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1150261509500. Starting simulation... +info: Entering event queue @ 1150373925000. Starting simulation... switching cpus -info: Entering event queue @ 1151261381500. Starting simulation... +info: Entering event queue @ 1151373789500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1152261381500. Starting simulation... +info: Entering event queue @ 1152373789500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1153261381500. Starting simulation... +info: Entering event queue @ 1153373789500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1154261381500. Starting simulation... +info: Entering event queue @ 1154373789500. Starting simulation... switching cpus -info: Entering event queue @ 1155261253500. Starting simulation... +info: Entering event queue @ 1155373661500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1156261253500. Starting simulation... +info: Entering event queue @ 1156373661500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1157261253500. Starting simulation... +info: Entering event queue @ 1157373661500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1158261253500. Starting simulation... +info: Entering event queue @ 1158373661500. Starting simulation... switching cpus -info: Entering event queue @ 1159261125500. Starting simulation... +info: Entering event queue @ 1159373533500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1160261125500. Starting simulation... +info: Entering event queue @ 1160373533500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1161261125500. Starting simulation... +info: Entering event queue @ 1161373533500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1162261125500. Starting simulation... +info: Entering event queue @ 1162373533500. Starting simulation... switching cpus -info: Entering event queue @ 1163260997500. Starting simulation... +info: Entering event queue @ 1163373405500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1164260997500. Starting simulation... +info: Entering event queue @ 1164373405500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1165373405500. Starting simulation... switching cpus -info: Entering event queue @ 1165260997500. Starting simulation... +info: Entering event queue @ 1165373413000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1166260997500. Starting simulation... +info: Entering event queue @ 1166373413000. Starting simulation... switching cpus -info: Entering event queue @ 1167260869500. Starting simulation... +info: Entering event queue @ 1167373277500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1168260869500. Starting simulation... +info: Entering event queue @ 1168373277500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1169260869500. Starting simulation... +info: Entering event queue @ 1169373277500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1170260869500. Starting simulation... +info: Entering event queue @ 1170373277500. Starting simulation... switching cpus -info: Entering event queue @ 1171260741500. Starting simulation... +info: Entering event queue @ 1171373149500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1172260741500. Starting simulation... +info: Entering event queue @ 1172373149500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1173260741500. Starting simulation... +info: Entering event queue @ 1173373149500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1174260741500. Starting simulation... +info: Entering event queue @ 1174373149500. Starting simulation... switching cpus -info: Entering event queue @ 1175260613500. Starting simulation... +info: Entering event queue @ 1175373021500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1176260613500. Starting simulation... +info: Entering event queue @ 1176373021500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1177260613500. Starting simulation... +info: Entering event queue @ 1177373021500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1178260613500. Starting simulation... +info: Entering event queue @ 1178373021500. Starting simulation... switching cpus -info: Entering event queue @ 1179260485500. Starting simulation... +info: Entering event queue @ 1179372893500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1180260485500. Starting simulation... +info: Entering event queue @ 1180372893500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1181372893500. Starting simulation... switching cpus -info: Entering event queue @ 1181260485500. Starting simulation... +info: Entering event queue @ 1181372901000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1182260485500. Starting simulation... +info: Entering event queue @ 1182372901000. Starting simulation... switching cpus -info: Entering event queue @ 1183260357500. Starting simulation... +info: Entering event queue @ 1183372765500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1184260357500. Starting simulation... +info: Entering event queue @ 1184372765500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1185260357500. Starting simulation... +info: Entering event queue @ 1185372765500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1186260357500. Starting simulation... +info: Entering event queue @ 1186372765500. Starting simulation... switching cpus -info: Entering event queue @ 1187260229500. Starting simulation... +info: Entering event queue @ 1187372637500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1188260229500. Starting simulation... +info: Entering event queue @ 1188372637500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1189260229500. Starting simulation... +info: Entering event queue @ 1189372637500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1190260229500. Starting simulation... +info: Entering event queue @ 1190372637500. Starting simulation... switching cpus -info: Entering event queue @ 1191260101500. Starting simulation... +info: Entering event queue @ 1191372509500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1192260101500. Starting simulation... +info: Entering event queue @ 1192372509500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1193260101500. Starting simulation... +info: Entering event queue @ 1193372509500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1194260101500. Starting simulation... +info: Entering event queue @ 1194372509500. Starting simulation... switching cpus -info: Entering event queue @ 1195259973500. Starting simulation... +info: Entering event queue @ 1195372381500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1196259973500. Starting simulation... +info: Entering event queue @ 1196372381500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1197372381500. Starting simulation... switching cpus -info: Entering event queue @ 1197259973500. Starting simulation... +info: Entering event queue @ 1197372389000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1198259973500. Starting simulation... +info: Entering event queue @ 1198372389000. Starting simulation... switching cpus -info: Entering event queue @ 1199259845500. Starting simulation... +info: Entering event queue @ 1199372253500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1200259845500. Starting simulation... +info: Entering event queue @ 1200372253500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1201259845500. Starting simulation... +info: Entering event queue @ 1201372253500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1202259845500. Starting simulation... +info: Entering event queue @ 1202372253500. Starting simulation... switching cpus -info: Entering event queue @ 1203259717500. Starting simulation... +info: Entering event queue @ 1203372125500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1204259717500. Starting simulation... +info: Entering event queue @ 1204372125500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1205259717500. Starting simulation... +info: Entering event queue @ 1205372125500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1206259717500. Starting simulation... +info: Entering event queue @ 1206372125500. Starting simulation... switching cpus -info: Entering event queue @ 1207259589500. Starting simulation... +info: Entering event queue @ 1207371997500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1208259589500. Starting simulation... +info: Entering event queue @ 1208371997500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1209259589500. Starting simulation... +info: Entering event queue @ 1209371997500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1210259589500. Starting simulation... +info: Entering event queue @ 1210371997500. Starting simulation... switching cpus -info: Entering event queue @ 1211259461500. Starting simulation... +info: Entering event queue @ 1211371869500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1212259461500. Starting simulation... +info: Entering event queue @ 1212371869500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1213371869500. Starting simulation... switching cpus -info: Entering event queue @ 1213259461500. Starting simulation... +info: Entering event queue @ 1213371877000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1214259461500. Starting simulation... +info: Entering event queue @ 1214371877000. Starting simulation... switching cpus -info: Entering event queue @ 1215259333500. Starting simulation... +info: Entering event queue @ 1215371741500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1216259333500. Starting simulation... +info: Entering event queue @ 1216371741500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1217259333500. Starting simulation... +info: Entering event queue @ 1217371741500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1218259333500. Starting simulation... +info: Entering event queue @ 1218371741500. Starting simulation... switching cpus -info: Entering event queue @ 1219259205500. Starting simulation... +info: Entering event queue @ 1219371613500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1220259205500. Starting simulation... +info: Entering event queue @ 1220371613500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1221259205500. Starting simulation... +info: Entering event queue @ 1221371613500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1222259205500. Starting simulation... +info: Entering event queue @ 1222371613500. Starting simulation... switching cpus -info: Entering event queue @ 1223259077500. Starting simulation... +info: Entering event queue @ 1223371485500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1224259077500. Starting simulation... +info: Entering event queue @ 1224371485500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1225259077500. Starting simulation... +info: Entering event queue @ 1225371485500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1226259077500. Starting simulation... +info: Entering event queue @ 1226371485500. Starting simulation... switching cpus -info: Entering event queue @ 1227258949500. Starting simulation... +info: Entering event queue @ 1227371357500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1228258949500. Starting simulation... +info: Entering event queue @ 1228371357500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1229258949500. Starting simulation... +info: Entering event queue @ 1229371357500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1230258949500. Starting simulation... +info: Entering event queue @ 1230371357500. Starting simulation... switching cpus -info: Entering event queue @ 1231258821500. Starting simulation... +info: Entering event queue @ 1231371229500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1232258821500. Starting simulation... +info: Entering event queue @ 1232371229500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1233258821500. Starting simulation... +info: Entering event queue @ 1233371229500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1234258821500. Starting simulation... +info: Entering event queue @ 1234371229500. Starting simulation... switching cpus -info: Entering event queue @ 1235258693500. Starting simulation... +info: Entering event queue @ 1235371101500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1236258693500. Starting simulation... +info: Entering event queue @ 1236371101500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1237258693500. Starting simulation... +info: Entering event queue @ 1237371101500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1238258693500. Starting simulation... +info: Entering event queue @ 1238371101500. Starting simulation... switching cpus -info: Entering event queue @ 1239258565500. Starting simulation... +info: Entering event queue @ 1239370973500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1240258565500. Starting simulation... +info: Entering event queue @ 1240370973500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1241258565500. Starting simulation... +info: Entering event queue @ 1241370973500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1242258565500. Starting simulation... +info: Entering event queue @ 1242370973500. Starting simulation... switching cpus -info: Entering event queue @ 1243258437500. Starting simulation... +info: Entering event queue @ 1243370845500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1244258437500. Starting simulation... +info: Entering event queue @ 1244370845500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1245258437500. Starting simulation... +info: Entering event queue @ 1245370845500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1246258437500. Starting simulation... +info: Entering event queue @ 1246370845500. Starting simulation... switching cpus -info: Entering event queue @ 1247258309500. Starting simulation... +info: Entering event queue @ 1247370717500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1248258309500. Starting simulation... +info: Entering event queue @ 1248370717500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1249258309500. Starting simulation... +info: Entering event queue @ 1249370717500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1250258309500. Starting simulation... +info: Entering event queue @ 1250370717500. Starting simulation... switching cpus -info: Entering event queue @ 1251258181500. Starting simulation... +info: Entering event queue @ 1251370589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1252258181500. Starting simulation... +info: Entering event queue @ 1252370589500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1253258181500. Starting simulation... +info: Entering event queue @ 1253370589500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1254258181500. Starting simulation... +info: Entering event queue @ 1254370589500. Starting simulation... switching cpus -info: Entering event queue @ 1255258053500. Starting simulation... +info: Entering event queue @ 1255370461500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1256258053500. Starting simulation... +info: Entering event queue @ 1256370461500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1257258053500. Starting simulation... +info: Entering event queue @ 1257370461500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1258258053500. Starting simulation... +info: Entering event queue @ 1258370461500. Starting simulation... switching cpus -info: Entering event queue @ 1259257925500. Starting simulation... +info: Entering event queue @ 1259370333500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1260257925500. Starting simulation... +info: Entering event queue @ 1260370333500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1261257925500. Starting simulation... +info: Entering event queue @ 1261370333500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1262257925500. Starting simulation... +info: Entering event queue @ 1262370333500. Starting simulation... switching cpus -info: Entering event queue @ 1263257797500. Starting simulation... +info: Entering event queue @ 1263370205500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1264257797500. Starting simulation... +info: Entering event queue @ 1264370205500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1265257797500. Starting simulation... +info: Entering event queue @ 1265370205500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1266257797500. Starting simulation... +info: Entering event queue @ 1266370205500. Starting simulation... switching cpus -info: Entering event queue @ 1267257669500. Starting simulation... +info: Entering event queue @ 1267370077500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1268257669500. Starting simulation... +info: Entering event queue @ 1268370077500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1269257669500. Starting simulation... +info: Entering event queue @ 1269370077500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1270257669500. Starting simulation... +info: Entering event queue @ 1270370077500. Starting simulation... switching cpus -info: Entering event queue @ 1271257541500. Starting simulation... +info: Entering event queue @ 1271369949500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1272257541500. Starting simulation... +info: Entering event queue @ 1272369949500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1273257541500. Starting simulation... +info: Entering event queue @ 1273369949500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1274257541500. Starting simulation... +info: Entering event queue @ 1274369949500. Starting simulation... switching cpus -info: Entering event queue @ 1275257413500. Starting simulation... +info: Entering event queue @ 1275369821500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1276257413500. Starting simulation... +info: Entering event queue @ 1276369821500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1277257413500. Starting simulation... +info: Entering event queue @ 1277369821500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1278257413500. Starting simulation... +info: Entering event queue @ 1278369821500. Starting simulation... switching cpus -info: Entering event queue @ 1279257285500. Starting simulation... +info: Entering event queue @ 1279369693500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1280257285500. Starting simulation... +info: Entering event queue @ 1280369693500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1281257285500. Starting simulation... +info: Entering event queue @ 1281369693500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1282257285500. Starting simulation... +info: Entering event queue @ 1282369693500. Starting simulation... switching cpus -info: Entering event queue @ 1283257157500. Starting simulation... +info: Entering event queue @ 1283369565500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1284257157500. Starting simulation... +info: Entering event queue @ 1284369565500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1285257157500. Starting simulation... +info: Entering event queue @ 1285369565500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1286257157500. Starting simulation... +info: Entering event queue @ 1286369565500. Starting simulation... switching cpus -info: Entering event queue @ 1287257029500. Starting simulation... +info: Entering event queue @ 1287369437500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1288257029500. Starting simulation... +info: Entering event queue @ 1288369437500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1289257029500. Starting simulation... +info: Entering event queue @ 1289369437500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1290257029500. Starting simulation... +info: Entering event queue @ 1290369437500. Starting simulation... switching cpus -info: Entering event queue @ 1291256901500. Starting simulation... +info: Entering event queue @ 1291369309500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1292256901500. Starting simulation... +info: Entering event queue @ 1292369309500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1293256901500. Starting simulation... +info: Entering event queue @ 1293369309500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1294256901500. Starting simulation... +info: Entering event queue @ 1294369309500. Starting simulation... switching cpus -info: Entering event queue @ 1295256773500. Starting simulation... +info: Entering event queue @ 1295369181500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1296256773500. Starting simulation... +info: Entering event queue @ 1296369181500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1297256773500. Starting simulation... +info: Entering event queue @ 1297369181500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1298256773500. Starting simulation... +info: Entering event queue @ 1298369181500. Starting simulation... switching cpus -info: Entering event queue @ 1299256645500. Starting simulation... +info: Entering event queue @ 1299369053500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1300256645500. Starting simulation... +info: Entering event queue @ 1300369053500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1301256645500. Starting simulation... +info: Entering event queue @ 1301369053500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1302256645500. Starting simulation... +info: Entering event queue @ 1302369053500. Starting simulation... switching cpus -info: Entering event queue @ 1303256517500. Starting simulation... +info: Entering event queue @ 1303368925500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1304256517500. Starting simulation... +info: Entering event queue @ 1304368925500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1305256517500. Starting simulation... +info: Entering event queue @ 1305368925500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1306256517500. Starting simulation... +info: Entering event queue @ 1306368925500. Starting simulation... switching cpus -info: Entering event queue @ 1307256389500. Starting simulation... +info: Entering event queue @ 1307368797500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1308256389500. Starting simulation... +info: Entering event queue @ 1308368797500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1309256389500. Starting simulation... +info: Entering event queue @ 1309368797500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1310256389500. Starting simulation... +info: Entering event queue @ 1310368797500. Starting simulation... switching cpus -info: Entering event queue @ 1311256261500. Starting simulation... +info: Entering event queue @ 1311368669500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1312256261500. Starting simulation... +info: Entering event queue @ 1312368669500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1313256261500. Starting simulation... +info: Entering event queue @ 1313368669500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1314256261500. Starting simulation... +info: Entering event queue @ 1314368669500. Starting simulation... switching cpus -info: Entering event queue @ 1315256133500. Starting simulation... +info: Entering event queue @ 1315368541500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1316256133500. Starting simulation... +info: Entering event queue @ 1316368541500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1317256133500. Starting simulation... +info: Entering event queue @ 1317368541500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1318256133500. Starting simulation... +info: Entering event queue @ 1318368541500. Starting simulation... switching cpus -info: Entering event queue @ 1319256005500. Starting simulation... +info: Entering event queue @ 1319368413500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1320256005500. Starting simulation... +info: Entering event queue @ 1320368413500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1321256005500. Starting simulation... +info: Entering event queue @ 1321368413500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1322256005500. Starting simulation... +info: Entering event queue @ 1322368413500. Starting simulation... switching cpus -info: Entering event queue @ 1323255877500. Starting simulation... +info: Entering event queue @ 1323368285500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1324255877500. Starting simulation... +info: Entering event queue @ 1324368285500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1325255877500. Starting simulation... +info: Entering event queue @ 1325368285500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1326255877500. Starting simulation... +info: Entering event queue @ 1326368285500. Starting simulation... switching cpus -info: Entering event queue @ 1327255749500. Starting simulation... +info: Entering event queue @ 1327368157500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1328255749500. Starting simulation... +info: Entering event queue @ 1328368157500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1329255749500. Starting simulation... +info: Entering event queue @ 1329368157500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1330255749500. Starting simulation... +info: Entering event queue @ 1330368157500. Starting simulation... switching cpus -info: Entering event queue @ 1331255621500. Starting simulation... +info: Entering event queue @ 1331368029500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1332255621500. Starting simulation... +info: Entering event queue @ 1332368029500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1333255621500. Starting simulation... +info: Entering event queue @ 1333368029500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1334255621500. Starting simulation... +info: Entering event queue @ 1334368029500. Starting simulation... switching cpus -info: Entering event queue @ 1335255493500. Starting simulation... +info: Entering event queue @ 1335367901500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1336255493500. Starting simulation... +info: Entering event queue @ 1336367901500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1337255493500. Starting simulation... +info: Entering event queue @ 1337367901500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1338255493500. Starting simulation... +info: Entering event queue @ 1338367901500. Starting simulation... switching cpus -info: Entering event queue @ 1339255365500. Starting simulation... +info: Entering event queue @ 1339367773500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1340255365500. Starting simulation... +info: Entering event queue @ 1340367773500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1341255365500. Starting simulation... +info: Entering event queue @ 1341367773500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1342255365500. Starting simulation... +info: Entering event queue @ 1342367773500. Starting simulation... switching cpus -info: Entering event queue @ 1343255237500. Starting simulation... +info: Entering event queue @ 1343367645500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1344255237500. Starting simulation... +info: Entering event queue @ 1344367645500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1345255237500. Starting simulation... +info: Entering event queue @ 1345367645500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1346255237500. Starting simulation... +info: Entering event queue @ 1346367645500. Starting simulation... switching cpus -info: Entering event queue @ 1347255109500. Starting simulation... +info: Entering event queue @ 1347367517500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1348255109500. Starting simulation... +info: Entering event queue @ 1348367517500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1349255109500. Starting simulation... +info: Entering event queue @ 1349367517500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1350255109500. Starting simulation... +info: Entering event queue @ 1350367517500. Starting simulation... switching cpus -info: Entering event queue @ 1351254981500. Starting simulation... +info: Entering event queue @ 1351367389500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1352254981500. Starting simulation... +info: Entering event queue @ 1352367389500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1353254981500. Starting simulation... +info: Entering event queue @ 1353367389500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1354254981500. Starting simulation... +info: Entering event queue @ 1354367389500. Starting simulation... switching cpus -info: Entering event queue @ 1355254853500. Starting simulation... +info: Entering event queue @ 1355367261500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1356254853500. Starting simulation... +info: Entering event queue @ 1356367261500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1357254853500. Starting simulation... +info: Entering event queue @ 1357367261500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1358254853500. Starting simulation... +info: Entering event queue @ 1358367261500. Starting simulation... switching cpus -info: Entering event queue @ 1359254725500. Starting simulation... +info: Entering event queue @ 1359367133500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1360254725500. Starting simulation... +info: Entering event queue @ 1360367133500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1361254725500. Starting simulation... +info: Entering event queue @ 1361367133500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1362254725500. Starting simulation... +info: Entering event queue @ 1362367133500. Starting simulation... switching cpus -info: Entering event queue @ 1363254597500. Starting simulation... +info: Entering event queue @ 1363367005500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1364254597500. Starting simulation... +info: Entering event queue @ 1364367005500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1365254597500. Starting simulation... +info: Entering event queue @ 1365367005500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1366254597500. Starting simulation... +info: Entering event queue @ 1366367005500. Starting simulation... switching cpus -info: Entering event queue @ 1367254469500. Starting simulation... +info: Entering event queue @ 1367366877500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1368254469500. Starting simulation... +info: Entering event queue @ 1368366877500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1369254469500. Starting simulation... +info: Entering event queue @ 1369366877500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1370254469500. Starting simulation... +info: Entering event queue @ 1370366877500. Starting simulation... switching cpus -info: Entering event queue @ 1371254341500. Starting simulation... +info: Entering event queue @ 1371366749500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1372254341500. Starting simulation... +info: Entering event queue @ 1372366749500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1373254341500. Starting simulation... +info: Entering event queue @ 1373366749500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1374254341500. Starting simulation... +info: Entering event queue @ 1374366749500. Starting simulation... switching cpus -info: Entering event queue @ 1375254213500. Starting simulation... +info: Entering event queue @ 1375366621500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1376254213500. Starting simulation... +info: Entering event queue @ 1376366621500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1377254213500. Starting simulation... +info: Entering event queue @ 1377366621500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1378254213500. Starting simulation... +info: Entering event queue @ 1378366621500. Starting simulation... switching cpus -info: Entering event queue @ 1379254085500. Starting simulation... +info: Entering event queue @ 1379366493500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1380254085500. Starting simulation... +info: Entering event queue @ 1380366493500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1381254085500. Starting simulation... +info: Entering event queue @ 1381366493500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1382254085500. Starting simulation... +info: Entering event queue @ 1382366493500. Starting simulation... switching cpus -info: Entering event queue @ 1383253957500. Starting simulation... +info: Entering event queue @ 1383366365500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1384253957500. Starting simulation... +info: Entering event queue @ 1384366365500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1385253957500. Starting simulation... +info: Entering event queue @ 1385366365500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1386253957500. Starting simulation... +info: Entering event queue @ 1386366365500. Starting simulation... switching cpus -info: Entering event queue @ 1387253829500. Starting simulation... +info: Entering event queue @ 1387366237500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1388253829500. Starting simulation... +info: Entering event queue @ 1388366237500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1389253829500. Starting simulation... +info: Entering event queue @ 1389366237500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1390253829500. Starting simulation... +info: Entering event queue @ 1390366237500. Starting simulation... switching cpus -info: Entering event queue @ 1391253701500. Starting simulation... +info: Entering event queue @ 1391366109500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1392253701500. Starting simulation... +info: Entering event queue @ 1392366109500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1393253701500. Starting simulation... +info: Entering event queue @ 1393366109500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1394253701500. Starting simulation... +info: Entering event queue @ 1394366109500. Starting simulation... switching cpus -info: Entering event queue @ 1395253573500. Starting simulation... +info: Entering event queue @ 1395365981500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1396253573500. Starting simulation... +info: Entering event queue @ 1396365981500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1397253573500. Starting simulation... +info: Entering event queue @ 1397365981500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1398253573500. Starting simulation... +info: Entering event queue @ 1398365981500. Starting simulation... switching cpus -info: Entering event queue @ 1399253445500. Starting simulation... +info: Entering event queue @ 1399365853500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1400253445500. Starting simulation... +info: Entering event queue @ 1400365853500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1401253445500. Starting simulation... +info: Entering event queue @ 1401365853500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1402253445500. Starting simulation... +info: Entering event queue @ 1402365853500. Starting simulation... switching cpus -info: Entering event queue @ 1403253317500. Starting simulation... +info: Entering event queue @ 1403365725500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1404253317500. Starting simulation... +info: Entering event queue @ 1404365725500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1405253317500. Starting simulation... +info: Entering event queue @ 1405365725500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1406253317500. Starting simulation... +info: Entering event queue @ 1406365725500. Starting simulation... switching cpus -info: Entering event queue @ 1407253189500. Starting simulation... +info: Entering event queue @ 1407365597500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1408253189500. Starting simulation... +info: Entering event queue @ 1408365597500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1409253189500. Starting simulation... +info: Entering event queue @ 1409365597500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1410253189500. Starting simulation... +info: Entering event queue @ 1410365597500. Starting simulation... switching cpus -info: Entering event queue @ 1411253061500. Starting simulation... +info: Entering event queue @ 1411365469500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1412253061500. Starting simulation... +info: Entering event queue @ 1412365469500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1413253061500. Starting simulation... +info: Entering event queue @ 1413365469500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1414253061500. Starting simulation... +info: Entering event queue @ 1414365469500. Starting simulation... switching cpus -info: Entering event queue @ 1415252933500. Starting simulation... +info: Entering event queue @ 1415365341500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1416252933500. Starting simulation... +info: Entering event queue @ 1416365341500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1417252933500. Starting simulation... +info: Entering event queue @ 1417365341500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1418252933500. Starting simulation... +info: Entering event queue @ 1418365341500. Starting simulation... switching cpus -info: Entering event queue @ 1419252805500. Starting simulation... +info: Entering event queue @ 1419365213500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1420252805500. Starting simulation... +info: Entering event queue @ 1420365213500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1421252805500. Starting simulation... +info: Entering event queue @ 1421365213500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1422252805500. Starting simulation... +info: Entering event queue @ 1422365213500. Starting simulation... switching cpus -info: Entering event queue @ 1423252677500. Starting simulation... +info: Entering event queue @ 1423365085500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1424252677500. Starting simulation... +info: Entering event queue @ 1424365085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1425252677500. Starting simulation... +info: Entering event queue @ 1425365085500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1426252677500. Starting simulation... +info: Entering event queue @ 1426365085500. Starting simulation... switching cpus -info: Entering event queue @ 1427252549500. Starting simulation... +info: Entering event queue @ 1427364957500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1428252549500. Starting simulation... +info: Entering event queue @ 1428364957500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1429252549500. Starting simulation... +info: Entering event queue @ 1429364957500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1430252549500. Starting simulation... +info: Entering event queue @ 1430364957500. Starting simulation... switching cpus -info: Entering event queue @ 1431252421500. Starting simulation... +info: Entering event queue @ 1431364829500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1432252421500. Starting simulation... +info: Entering event queue @ 1432364829500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1433252421500. Starting simulation... +info: Entering event queue @ 1433364829500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1434252421500. Starting simulation... +info: Entering event queue @ 1434364829500. Starting simulation... switching cpus -info: Entering event queue @ 1435252293500. Starting simulation... +info: Entering event queue @ 1435364701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1436252293500. Starting simulation... +info: Entering event queue @ 1436364701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1437252293500. Starting simulation... +info: Entering event queue @ 1437364701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1438252293500. Starting simulation... +info: Entering event queue @ 1438364701500. Starting simulation... switching cpus -info: Entering event queue @ 1439252165500. Starting simulation... +info: Entering event queue @ 1439364573500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1440252165500. Starting simulation... +info: Entering event queue @ 1440364573500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1441252165500. Starting simulation... +info: Entering event queue @ 1441364573500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1442252165500. Starting simulation... +info: Entering event queue @ 1442364573500. Starting simulation... switching cpus -info: Entering event queue @ 1443252037500. Starting simulation... +info: Entering event queue @ 1443364445500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1444252037500. Starting simulation... +info: Entering event queue @ 1444364445500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1445252037500. Starting simulation... +info: Entering event queue @ 1445364445500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1446252037500. Starting simulation... +info: Entering event queue @ 1446364445500. Starting simulation... switching cpus -info: Entering event queue @ 1447251909500. Starting simulation... +info: Entering event queue @ 1447364317500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1448251909500. Starting simulation... +info: Entering event queue @ 1448364317500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1449251909500. Starting simulation... +info: Entering event queue @ 1449364317500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1450251909500. Starting simulation... +info: Entering event queue @ 1450364317500. Starting simulation... switching cpus -info: Entering event queue @ 1451251781500. Starting simulation... +info: Entering event queue @ 1451364189500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1452251781500. Starting simulation... +info: Entering event queue @ 1452364189500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1453251781500. Starting simulation... +info: Entering event queue @ 1453364189500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1454251781500. Starting simulation... +info: Entering event queue @ 1454364189500. Starting simulation... switching cpus -info: Entering event queue @ 1455251653500. Starting simulation... +info: Entering event queue @ 1455364061500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1456251653500. Starting simulation... +info: Entering event queue @ 1456364061500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1457251653500. Starting simulation... +info: Entering event queue @ 1457364061500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1458251653500. Starting simulation... +info: Entering event queue @ 1458364061500. Starting simulation... switching cpus -info: Entering event queue @ 1459251525500. Starting simulation... +info: Entering event queue @ 1459363933500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1460251525500. Starting simulation... +info: Entering event queue @ 1460363933500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1461251525500. Starting simulation... +info: Entering event queue @ 1461363933500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1462251525500. Starting simulation... +info: Entering event queue @ 1462363933500. Starting simulation... switching cpus -info: Entering event queue @ 1463251397500. Starting simulation... +info: Entering event queue @ 1463363805500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1464251397500. Starting simulation... +info: Entering event queue @ 1464363805500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1465251397500. Starting simulation... +info: Entering event queue @ 1465363805500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1466251397500. Starting simulation... +info: Entering event queue @ 1466363805500. Starting simulation... switching cpus -info: Entering event queue @ 1467251269500. Starting simulation... +info: Entering event queue @ 1467363677500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1468251269500. Starting simulation... +info: Entering event queue @ 1468363677500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1469251269500. Starting simulation... +info: Entering event queue @ 1469363677500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1470251269500. Starting simulation... +info: Entering event queue @ 1470363677500. Starting simulation... switching cpus -info: Entering event queue @ 1471251141500. Starting simulation... +info: Entering event queue @ 1471363549500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1472251141500. Starting simulation... +info: Entering event queue @ 1472363549500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1473251141500. Starting simulation... +info: Entering event queue @ 1473363549500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1474251141500. Starting simulation... +info: Entering event queue @ 1474363549500. Starting simulation... switching cpus -info: Entering event queue @ 1475251013500. Starting simulation... +info: Entering event queue @ 1475363421500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1476251013500. Starting simulation... +info: Entering event queue @ 1476363421500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1477251013500. Starting simulation... +info: Entering event queue @ 1477363421500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1478251013500. Starting simulation... +info: Entering event queue @ 1478363421500. Starting simulation... switching cpus -info: Entering event queue @ 1479250885500. Starting simulation... +info: Entering event queue @ 1479363293500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1480250885500. Starting simulation... +info: Entering event queue @ 1480363293500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1481250885500. Starting simulation... +info: Entering event queue @ 1481363293500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1482250885500. Starting simulation... +info: Entering event queue @ 1482363293500. Starting simulation... switching cpus -info: Entering event queue @ 1483250757500. Starting simulation... +info: Entering event queue @ 1483363165500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1484250757500. Starting simulation... +info: Entering event queue @ 1484363165500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1485250757500. Starting simulation... +info: Entering event queue @ 1485363165500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1486250757500. Starting simulation... +info: Entering event queue @ 1486363165500. Starting simulation... switching cpus -info: Entering event queue @ 1487250629500. Starting simulation... +info: Entering event queue @ 1487363037500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1488250629500. Starting simulation... +info: Entering event queue @ 1488363037500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1489250629500. Starting simulation... +info: Entering event queue @ 1489363037500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1490250629500. Starting simulation... +info: Entering event queue @ 1490363037500. Starting simulation... switching cpus -info: Entering event queue @ 1491250501500. Starting simulation... +info: Entering event queue @ 1491362909500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1492250501500. Starting simulation... +info: Entering event queue @ 1492362909500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1493250501500. Starting simulation... +info: Entering event queue @ 1493362909500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1494250501500. Starting simulation... +info: Entering event queue @ 1494362909500. Starting simulation... switching cpus -info: Entering event queue @ 1495250373500. Starting simulation... +info: Entering event queue @ 1495362781500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1496250373500. Starting simulation... +info: Entering event queue @ 1496362781500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1497250373500. Starting simulation... +info: Entering event queue @ 1497362781500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1498250373500. Starting simulation... +info: Entering event queue @ 1498362781500. Starting simulation... switching cpus -info: Entering event queue @ 1499250245500. Starting simulation... +info: Entering event queue @ 1499362653500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1500250245500. Starting simulation... +info: Entering event queue @ 1500362653500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1501250245500. Starting simulation... +info: Entering event queue @ 1501362653500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1502250245500. Starting simulation... +info: Entering event queue @ 1502362653500. Starting simulation... switching cpus -info: Entering event queue @ 1503250117500. Starting simulation... +info: Entering event queue @ 1503362525500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1504250117500. Starting simulation... +info: Entering event queue @ 1504362525500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1505250117500. Starting simulation... +info: Entering event queue @ 1505362525500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1506250117500. Starting simulation... +info: Entering event queue @ 1506362525500. Starting simulation... switching cpus -info: Entering event queue @ 1507249989500. Starting simulation... +info: Entering event queue @ 1507362397500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1508249989500. Starting simulation... +info: Entering event queue @ 1508362397500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1509249989500. Starting simulation... +info: Entering event queue @ 1509362397500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1510249989500. Starting simulation... +info: Entering event queue @ 1510362397500. Starting simulation... switching cpus -info: Entering event queue @ 1511249861500. Starting simulation... +info: Entering event queue @ 1511362269500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1512249861500. Starting simulation... +info: Entering event queue @ 1512362269500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1513249861500. Starting simulation... +info: Entering event queue @ 1513362269500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1514249861500. Starting simulation... +info: Entering event queue @ 1514362269500. Starting simulation... switching cpus -info: Entering event queue @ 1515249733500. Starting simulation... +info: Entering event queue @ 1515362141500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1516249733500. Starting simulation... +info: Entering event queue @ 1516362141500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1517249733500. Starting simulation... +info: Entering event queue @ 1517362141500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1518249733500. Starting simulation... +info: Entering event queue @ 1518362141500. Starting simulation... switching cpus -info: Entering event queue @ 1519249605500. Starting simulation... +info: Entering event queue @ 1519362013500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1520249605500. Starting simulation... +info: Entering event queue @ 1520362013500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1521249605500. Starting simulation... +info: Entering event queue @ 1521362013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1522249605500. Starting simulation... +info: Entering event queue @ 1522362013500. Starting simulation... switching cpus -info: Entering event queue @ 1523249477500. Starting simulation... +info: Entering event queue @ 1523361885500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1524249477500. Starting simulation... +info: Entering event queue @ 1524361885500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1525249477500. Starting simulation... +info: Entering event queue @ 1525361885500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1526249477500. Starting simulation... +info: Entering event queue @ 1526361885500. Starting simulation... switching cpus -info: Entering event queue @ 1527249349500. Starting simulation... +info: Entering event queue @ 1527361757500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1528249349500. Starting simulation... +info: Entering event queue @ 1528361757500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1529249349500. Starting simulation... +info: Entering event queue @ 1529361757500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1530249349500. Starting simulation... +info: Entering event queue @ 1530361757500. Starting simulation... switching cpus -info: Entering event queue @ 1531249221500. Starting simulation... +info: Entering event queue @ 1531361629500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1532249221500. Starting simulation... +info: Entering event queue @ 1532361629500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1533249221500. Starting simulation... +info: Entering event queue @ 1533361629500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1534249221500. Starting simulation... +info: Entering event queue @ 1534361629500. Starting simulation... switching cpus -info: Entering event queue @ 1535249093500. Starting simulation... +info: Entering event queue @ 1535361501500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1536249093500. Starting simulation... +info: Entering event queue @ 1536361501500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1537249093500. Starting simulation... +info: Entering event queue @ 1537361501500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1538249093500. Starting simulation... +info: Entering event queue @ 1538361501500. Starting simulation... switching cpus -info: Entering event queue @ 1539248965500. Starting simulation... +info: Entering event queue @ 1539361373500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1540248965500. Starting simulation... +info: Entering event queue @ 1540361373500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1541248965500. Starting simulation... +info: Entering event queue @ 1541361373500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1542248965500. Starting simulation... +info: Entering event queue @ 1542361373500. Starting simulation... switching cpus -info: Entering event queue @ 1543248837500. Starting simulation... +info: Entering event queue @ 1543361245500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1544248837500. Starting simulation... +info: Entering event queue @ 1544361245500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1545248837500. Starting simulation... +info: Entering event queue @ 1545361245500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1546248837500. Starting simulation... +info: Entering event queue @ 1546361245500. Starting simulation... switching cpus -info: Entering event queue @ 1547248709500. Starting simulation... +info: Entering event queue @ 1547361117500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1548248709500. Starting simulation... +info: Entering event queue @ 1548361117500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1549248709500. Starting simulation... +info: Entering event queue @ 1549361117500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1550248709500. Starting simulation... +info: Entering event queue @ 1550361117500. Starting simulation... switching cpus -info: Entering event queue @ 1551248581500. Starting simulation... +info: Entering event queue @ 1551360989500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1552248581500. Starting simulation... +info: Entering event queue @ 1552360989500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1553248581500. Starting simulation... +info: Entering event queue @ 1553360989500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1554248581500. Starting simulation... +info: Entering event queue @ 1554360989500. Starting simulation... switching cpus -info: Entering event queue @ 1555248453500. Starting simulation... +info: Entering event queue @ 1555360861500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1556248453500. Starting simulation... +info: Entering event queue @ 1556360861500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1557248453500. Starting simulation... +info: Entering event queue @ 1557360861500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1558248453500. Starting simulation... +info: Entering event queue @ 1558360861500. Starting simulation... switching cpus -info: Entering event queue @ 1559248325500. Starting simulation... +info: Entering event queue @ 1559360733500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1560248325500. Starting simulation... +info: Entering event queue @ 1560360733500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1561248325500. Starting simulation... +info: Entering event queue @ 1561360733500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1562248325500. Starting simulation... +info: Entering event queue @ 1562360733500. Starting simulation... switching cpus -info: Entering event queue @ 1563248197500. Starting simulation... +info: Entering event queue @ 1563360605500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1564248197500. Starting simulation... +info: Entering event queue @ 1564360605500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1565248197500. Starting simulation... +info: Entering event queue @ 1565360605500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1566248197500. Starting simulation... +info: Entering event queue @ 1566360605500. Starting simulation... switching cpus -info: Entering event queue @ 1567248069500. Starting simulation... +info: Entering event queue @ 1567360477500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1568248069500. Starting simulation... +info: Entering event queue @ 1568360477500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1569248069500. Starting simulation... +info: Entering event queue @ 1569360477500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1570248069500. Starting simulation... +info: Entering event queue @ 1570360477500. Starting simulation... switching cpus -info: Entering event queue @ 1571247941500. Starting simulation... +info: Entering event queue @ 1571360349500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1572247941500. Starting simulation... +info: Entering event queue @ 1572360349500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1573247941500. Starting simulation... +info: Entering event queue @ 1573360349500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1574247941500. Starting simulation... +info: Entering event queue @ 1574360349500. Starting simulation... switching cpus -info: Entering event queue @ 1575247813500. Starting simulation... +info: Entering event queue @ 1575360221500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1576247813500. Starting simulation... +info: Entering event queue @ 1576360221500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1577247813500. Starting simulation... +info: Entering event queue @ 1577360221500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1578247813500. Starting simulation... +info: Entering event queue @ 1578360221500. Starting simulation... switching cpus -info: Entering event queue @ 1579247685500. Starting simulation... +info: Entering event queue @ 1579360093500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1580247685500. Starting simulation... +info: Entering event queue @ 1580360093500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1581247685500. Starting simulation... +info: Entering event queue @ 1581360093500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1582247685500. Starting simulation... +info: Entering event queue @ 1582360093500. Starting simulation... switching cpus -info: Entering event queue @ 1583247557500. Starting simulation... +info: Entering event queue @ 1583359965500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1584247557500. Starting simulation... +info: Entering event queue @ 1584359965500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1585247557500. Starting simulation... +info: Entering event queue @ 1585359965500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1586247557500. Starting simulation... +info: Entering event queue @ 1586359965500. Starting simulation... switching cpus -info: Entering event queue @ 1587247429500. Starting simulation... +info: Entering event queue @ 1587359837500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1588247429500. Starting simulation... +info: Entering event queue @ 1588359837500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1589247429500. Starting simulation... +info: Entering event queue @ 1589359837500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1590247429500. Starting simulation... +info: Entering event queue @ 1590359837500. Starting simulation... switching cpus -info: Entering event queue @ 1591247301500. Starting simulation... +info: Entering event queue @ 1591359709500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1592247301500. Starting simulation... +info: Entering event queue @ 1592359709500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1593247301500. Starting simulation... +info: Entering event queue @ 1593359709500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1594247301500. Starting simulation... +info: Entering event queue @ 1594359709500. Starting simulation... switching cpus -info: Entering event queue @ 1595247173500. Starting simulation... +info: Entering event queue @ 1595359581500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1596247173500. Starting simulation... +info: Entering event queue @ 1596359581500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1597247173500. Starting simulation... +info: Entering event queue @ 1597359581500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1598247173500. Starting simulation... +info: Entering event queue @ 1598359581500. Starting simulation... switching cpus -info: Entering event queue @ 1599247045500. Starting simulation... +info: Entering event queue @ 1599359453500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1600247045500. Starting simulation... +info: Entering event queue @ 1600359453500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1601247045500. Starting simulation... +info: Entering event queue @ 1601359453500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1602247045500. Starting simulation... +info: Entering event queue @ 1602359453500. Starting simulation... switching cpus -info: Entering event queue @ 1603246917500. Starting simulation... +info: Entering event queue @ 1603359325500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1604246917500. Starting simulation... +info: Entering event queue @ 1604359325500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1605246917500. Starting simulation... +info: Entering event queue @ 1605359325500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1606246917500. Starting simulation... +info: Entering event queue @ 1606359325500. Starting simulation... switching cpus -info: Entering event queue @ 1607246789500. Starting simulation... +info: Entering event queue @ 1607359197500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1608246789500. Starting simulation... +info: Entering event queue @ 1608359197500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1609246789500. Starting simulation... +info: Entering event queue @ 1609359197500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1610246789500. Starting simulation... +info: Entering event queue @ 1610359197500. Starting simulation... switching cpus -info: Entering event queue @ 1611246661500. Starting simulation... +info: Entering event queue @ 1611359069500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1612246661500. Starting simulation... +info: Entering event queue @ 1612359069500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1613246661500. Starting simulation... +info: Entering event queue @ 1613359069500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1614246661500. Starting simulation... +info: Entering event queue @ 1614359069500. Starting simulation... switching cpus -info: Entering event queue @ 1615246533500. Starting simulation... +info: Entering event queue @ 1615358941500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1616246533500. Starting simulation... +info: Entering event queue @ 1616358941500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1617246533500. Starting simulation... +info: Entering event queue @ 1617358941500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1618246533500. Starting simulation... +info: Entering event queue @ 1618358941500. Starting simulation... switching cpus -info: Entering event queue @ 1619246405500. Starting simulation... +info: Entering event queue @ 1619358813500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1620246405500. Starting simulation... +info: Entering event queue @ 1620358813500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1621246405500. Starting simulation... +info: Entering event queue @ 1621358813500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1622246405500. Starting simulation... +info: Entering event queue @ 1622358813500. Starting simulation... switching cpus -info: Entering event queue @ 1623246277500. Starting simulation... +info: Entering event queue @ 1623358685500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1624246277500. Starting simulation... +info: Entering event queue @ 1624358685500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1625246277500. Starting simulation... +info: Entering event queue @ 1625358685500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1626246277500. Starting simulation... +info: Entering event queue @ 1626358685500. Starting simulation... switching cpus -info: Entering event queue @ 1627246149500. Starting simulation... +info: Entering event queue @ 1627358557500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1628246149500. Starting simulation... +info: Entering event queue @ 1628358557500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1629246149500. Starting simulation... +info: Entering event queue @ 1629358557500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1630246149500. Starting simulation... +info: Entering event queue @ 1630358557500. Starting simulation... switching cpus -info: Entering event queue @ 1631246021500. Starting simulation... +info: Entering event queue @ 1631358429500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1632246021500. Starting simulation... +info: Entering event queue @ 1632358429500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1633246021500. Starting simulation... +info: Entering event queue @ 1633358429500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1634246021500. Starting simulation... +info: Entering event queue @ 1634358429500. Starting simulation... switching cpus -info: Entering event queue @ 1635245893500. Starting simulation... +info: Entering event queue @ 1635358301500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1636245893500. Starting simulation... +info: Entering event queue @ 1636358301500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1637245893500. Starting simulation... +info: Entering event queue @ 1637358301500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1638245893500. Starting simulation... +info: Entering event queue @ 1638358301500. Starting simulation... switching cpus -info: Entering event queue @ 1639245765500. Starting simulation... +info: Entering event queue @ 1639358173500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1640245765500. Starting simulation... +info: Entering event queue @ 1640358173500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1641245765500. Starting simulation... +info: Entering event queue @ 1641358173500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1642245765500. Starting simulation... +info: Entering event queue @ 1642358173500. Starting simulation... switching cpus -info: Entering event queue @ 1643245637500. Starting simulation... +info: Entering event queue @ 1643358045500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1644245637500. Starting simulation... +info: Entering event queue @ 1644358045500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1645245637500. Starting simulation... +info: Entering event queue @ 1645358045500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1646245637500. Starting simulation... +info: Entering event queue @ 1646358045500. Starting simulation... switching cpus -info: Entering event queue @ 1647245509500. Starting simulation... +info: Entering event queue @ 1647357917500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1648245509500. Starting simulation... +info: Entering event queue @ 1648357917500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1649245509500. Starting simulation... +info: Entering event queue @ 1649357917500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1650245509500. Starting simulation... +info: Entering event queue @ 1650357917500. Starting simulation... switching cpus -info: Entering event queue @ 1651245381500. Starting simulation... +info: Entering event queue @ 1651357789500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1652245381500. Starting simulation... +info: Entering event queue @ 1652357789500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1653245381500. Starting simulation... +info: Entering event queue @ 1653357789500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1654245381500. Starting simulation... +info: Entering event queue @ 1654357789500. Starting simulation... switching cpus -info: Entering event queue @ 1655245253500. Starting simulation... +info: Entering event queue @ 1655357661500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1656245253500. Starting simulation... +info: Entering event queue @ 1656357661500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1657245253500. Starting simulation... +info: Entering event queue @ 1657357661500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1658245253500. Starting simulation... +info: Entering event queue @ 1658357661500. Starting simulation... switching cpus -info: Entering event queue @ 1659245125500. Starting simulation... +info: Entering event queue @ 1659357533500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1660245125500. Starting simulation... +info: Entering event queue @ 1660357533500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1661245125500. Starting simulation... +info: Entering event queue @ 1661357533500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1662245125500. Starting simulation... +info: Entering event queue @ 1662357533500. Starting simulation... switching cpus -info: Entering event queue @ 1663244997500. Starting simulation... +info: Entering event queue @ 1663357405500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1664244997500. Starting simulation... +info: Entering event queue @ 1664357405500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1665244997500. Starting simulation... +info: Entering event queue @ 1665357405500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1666244997500. Starting simulation... +info: Entering event queue @ 1666357405500. Starting simulation... switching cpus -info: Entering event queue @ 1667244869500. Starting simulation... +info: Entering event queue @ 1667357277500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1668244869500. Starting simulation... +info: Entering event queue @ 1668357277500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1669244869500. Starting simulation... +info: Entering event queue @ 1669357277500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1670244869500. Starting simulation... +info: Entering event queue @ 1670357277500. Starting simulation... switching cpus -info: Entering event queue @ 1671244741500. Starting simulation... +info: Entering event queue @ 1671357149500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1672244741500. Starting simulation... +info: Entering event queue @ 1672357149500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1673244741500. Starting simulation... +info: Entering event queue @ 1673357149500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1674244741500. Starting simulation... +info: Entering event queue @ 1674357149500. Starting simulation... switching cpus -info: Entering event queue @ 1675244613500. Starting simulation... +info: Entering event queue @ 1675357021500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1676244613500. Starting simulation... +info: Entering event queue @ 1676357021500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1677244613500. Starting simulation... +info: Entering event queue @ 1677357021500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1678244613500. Starting simulation... +info: Entering event queue @ 1678357021500. Starting simulation... switching cpus -info: Entering event queue @ 1679244485500. Starting simulation... +info: Entering event queue @ 1679356893500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1680244485500. Starting simulation... +info: Entering event queue @ 1680356893500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1681244485500. Starting simulation... +info: Entering event queue @ 1681356893500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1682244485500. Starting simulation... +info: Entering event queue @ 1682356893500. Starting simulation... switching cpus -info: Entering event queue @ 1683244357500. Starting simulation... +info: Entering event queue @ 1683356765500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1684244357500. Starting simulation... +info: Entering event queue @ 1684356765500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1685244357500. Starting simulation... +info: Entering event queue @ 1685356765500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1686244357500. Starting simulation... +info: Entering event queue @ 1686356765500. Starting simulation... switching cpus -info: Entering event queue @ 1687244229500. Starting simulation... +info: Entering event queue @ 1687356637500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1688244229500. Starting simulation... +info: Entering event queue @ 1688356637500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1689244229500. Starting simulation... +info: Entering event queue @ 1689356637500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1690244229500. Starting simulation... +info: Entering event queue @ 1690356637500. Starting simulation... switching cpus -info: Entering event queue @ 1691244101500. Starting simulation... +info: Entering event queue @ 1691356509500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1692244101500. Starting simulation... +info: Entering event queue @ 1692356509500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1693244101500. Starting simulation... +info: Entering event queue @ 1693356509500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1694244101500. Starting simulation... +info: Entering event queue @ 1694356509500. Starting simulation... switching cpus -info: Entering event queue @ 1695243973500. Starting simulation... +info: Entering event queue @ 1695356381500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1696243973500. Starting simulation... +info: Entering event queue @ 1696356381500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1697243973500. Starting simulation... +info: Entering event queue @ 1697356381500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1698243973500. Starting simulation... +info: Entering event queue @ 1698356381500. Starting simulation... switching cpus -info: Entering event queue @ 1699243845500. Starting simulation... +info: Entering event queue @ 1699356253500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1700243845500. Starting simulation... +info: Entering event queue @ 1700356253500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1701243845500. Starting simulation... +info: Entering event queue @ 1701356253500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1702243845500. Starting simulation... +info: Entering event queue @ 1702356253500. Starting simulation... switching cpus -info: Entering event queue @ 1703243717500. Starting simulation... +info: Entering event queue @ 1703356125500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1704243717500. Starting simulation... +info: Entering event queue @ 1704356125500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1705243717500. Starting simulation... +info: Entering event queue @ 1705356125500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1706243717500. Starting simulation... +info: Entering event queue @ 1706356125500. Starting simulation... switching cpus -info: Entering event queue @ 1707243589500. Starting simulation... +info: Entering event queue @ 1707355997500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1708243589500. Starting simulation... +info: Entering event queue @ 1708355997500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1709243589500. Starting simulation... +info: Entering event queue @ 1709355997500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1710243589500. Starting simulation... +info: Entering event queue @ 1710355997500. Starting simulation... switching cpus -info: Entering event queue @ 1711243461500. Starting simulation... +info: Entering event queue @ 1711355869500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1712243461500. Starting simulation... +info: Entering event queue @ 1712355869500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1713243461500. Starting simulation... +info: Entering event queue @ 1713355869500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1714243461500. Starting simulation... +info: Entering event queue @ 1714355869500. Starting simulation... switching cpus -info: Entering event queue @ 1715243333500. Starting simulation... +info: Entering event queue @ 1715355741500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1716243333500. Starting simulation... +info: Entering event queue @ 1716355741500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1717243333500. Starting simulation... +info: Entering event queue @ 1717355741500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1718243333500. Starting simulation... +info: Entering event queue @ 1718355741500. Starting simulation... switching cpus -info: Entering event queue @ 1719243205500. Starting simulation... +info: Entering event queue @ 1719355613500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1720243205500. Starting simulation... +info: Entering event queue @ 1720355613500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1721243205500. Starting simulation... +info: Entering event queue @ 1721355613500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1722243205500. Starting simulation... +info: Entering event queue @ 1722355613500. Starting simulation... switching cpus -info: Entering event queue @ 1723243077500. Starting simulation... +info: Entering event queue @ 1723355485500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1724243077500. Starting simulation... +info: Entering event queue @ 1724355485500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1725243077500. Starting simulation... +info: Entering event queue @ 1725355485500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1726243077500. Starting simulation... +info: Entering event queue @ 1726355485500. Starting simulation... switching cpus -info: Entering event queue @ 1727242949500. Starting simulation... +info: Entering event queue @ 1727355357500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1728242949500. Starting simulation... +info: Entering event queue @ 1728355357500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1729242949500. Starting simulation... +info: Entering event queue @ 1729355357500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1730242949500. Starting simulation... +info: Entering event queue @ 1730355357500. Starting simulation... switching cpus -info: Entering event queue @ 1731242821500. Starting simulation... +info: Entering event queue @ 1731355229500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1732242821500. Starting simulation... +info: Entering event queue @ 1732355229500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1733242821500. Starting simulation... +info: Entering event queue @ 1733355229500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1734242821500. Starting simulation... +info: Entering event queue @ 1734355229500. Starting simulation... switching cpus -info: Entering event queue @ 1735242693500. Starting simulation... +info: Entering event queue @ 1735355101500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1736242693500. Starting simulation... +info: Entering event queue @ 1736355101500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1737242693500. Starting simulation... +info: Entering event queue @ 1737355101500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1738242693500. Starting simulation... +info: Entering event queue @ 1738355101500. Starting simulation... switching cpus -info: Entering event queue @ 1739242565500. Starting simulation... +info: Entering event queue @ 1739354973500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1740242565500. Starting simulation... +info: Entering event queue @ 1740354973500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1741242565500. Starting simulation... +info: Entering event queue @ 1741354973500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1742242565500. Starting simulation... +info: Entering event queue @ 1742354973500. Starting simulation... switching cpus -info: Entering event queue @ 1743242437500. Starting simulation... +info: Entering event queue @ 1743354845500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1744242437500. Starting simulation... +info: Entering event queue @ 1744354845500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1745242437500. Starting simulation... +info: Entering event queue @ 1745354845500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1746242437500. Starting simulation... +info: Entering event queue @ 1746354845500. Starting simulation... switching cpus -info: Entering event queue @ 1747242309500. Starting simulation... +info: Entering event queue @ 1747354717500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1748242309500. Starting simulation... +info: Entering event queue @ 1748354717500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1749242309500. Starting simulation... +info: Entering event queue @ 1749354717500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1750242309500. Starting simulation... +info: Entering event queue @ 1750354717500. Starting simulation... switching cpus -info: Entering event queue @ 1751242181500. Starting simulation... +info: Entering event queue @ 1751354589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1752242181500. Starting simulation... +info: Entering event queue @ 1752354589500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1753242181500. Starting simulation... +info: Entering event queue @ 1753354589500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1754242181500. Starting simulation... +info: Entering event queue @ 1754354589500. Starting simulation... switching cpus -info: Entering event queue @ 1755242053500. Starting simulation... +info: Entering event queue @ 1755354461500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1756242053500. Starting simulation... +info: Entering event queue @ 1756354461500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1757242053500. Starting simulation... +info: Entering event queue @ 1757354461500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1758242053500. Starting simulation... +info: Entering event queue @ 1758354461500. Starting simulation... switching cpus -info: Entering event queue @ 1759241925500. Starting simulation... +info: Entering event queue @ 1759354333500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1760241925500. Starting simulation... +info: Entering event queue @ 1760354333500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1761241925500. Starting simulation... +info: Entering event queue @ 1761354333500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1762241925500. Starting simulation... +info: Entering event queue @ 1762354333500. Starting simulation... switching cpus -info: Entering event queue @ 1763241797500. Starting simulation... +info: Entering event queue @ 1763354205500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1764241797500. Starting simulation... +info: Entering event queue @ 1764354205500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1765241797500. Starting simulation... +info: Entering event queue @ 1765354205500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1766241797500. Starting simulation... +info: Entering event queue @ 1766354205500. Starting simulation... switching cpus -info: Entering event queue @ 1767241669500. Starting simulation... +info: Entering event queue @ 1767354077500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1768241669500. Starting simulation... +info: Entering event queue @ 1768354077500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1769241669500. Starting simulation... +info: Entering event queue @ 1769354077500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1770241669500. Starting simulation... +info: Entering event queue @ 1770354077500. Starting simulation... switching cpus -info: Entering event queue @ 1771241541500. Starting simulation... +info: Entering event queue @ 1771353949500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1772241541500. Starting simulation... +info: Entering event queue @ 1772353949500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1773241541500. Starting simulation... +info: Entering event queue @ 1773353949500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1774241541500. Starting simulation... +info: Entering event queue @ 1774353949500. Starting simulation... switching cpus -info: Entering event queue @ 1775241413500. Starting simulation... +info: Entering event queue @ 1775353821500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1776241413500. Starting simulation... +info: Entering event queue @ 1776353821500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1777241413500. Starting simulation... +info: Entering event queue @ 1777353821500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1778241413500. Starting simulation... +info: Entering event queue @ 1778353821500. Starting simulation... switching cpus -info: Entering event queue @ 1779241285500. Starting simulation... +info: Entering event queue @ 1779353693500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1780241285500. Starting simulation... +info: Entering event queue @ 1780353693500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1781241285500. Starting simulation... +info: Entering event queue @ 1781353693500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1782241285500. Starting simulation... +info: Entering event queue @ 1782353693500. Starting simulation... switching cpus -info: Entering event queue @ 1783241157500. Starting simulation... +info: Entering event queue @ 1783353565500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1784241157500. Starting simulation... +info: Entering event queue @ 1784353565500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1785241157500. Starting simulation... +info: Entering event queue @ 1785353565500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1786241157500. Starting simulation... +info: Entering event queue @ 1786353565500. Starting simulation... switching cpus -info: Entering event queue @ 1787241029500. Starting simulation... +info: Entering event queue @ 1787353437500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1788241029500. Starting simulation... +info: Entering event queue @ 1788353437500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1789241029500. Starting simulation... +info: Entering event queue @ 1789353437500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1790241029500. Starting simulation... +info: Entering event queue @ 1790353437500. Starting simulation... switching cpus -info: Entering event queue @ 1791240901500. Starting simulation... +info: Entering event queue @ 1791353309500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1792240901500. Starting simulation... +info: Entering event queue @ 1792353309500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1793240901500. Starting simulation... +info: Entering event queue @ 1793353309500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1794240901500. Starting simulation... +info: Entering event queue @ 1794353309500. Starting simulation... switching cpus -info: Entering event queue @ 1795240773500. Starting simulation... +info: Entering event queue @ 1795353181500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1796240773500. Starting simulation... +info: Entering event queue @ 1796353181500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1797240773500. Starting simulation... +info: Entering event queue @ 1797353181500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1798240773500. Starting simulation... +info: Entering event queue @ 1798353181500. Starting simulation... switching cpus -info: Entering event queue @ 1799240645500. Starting simulation... +info: Entering event queue @ 1799353053500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1800240645500. Starting simulation... +info: Entering event queue @ 1800353053500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1801240645500. Starting simulation... +info: Entering event queue @ 1801353053500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1802240645500. Starting simulation... +info: Entering event queue @ 1802353053500. Starting simulation... switching cpus -info: Entering event queue @ 1803240517500. Starting simulation... +info: Entering event queue @ 1803352925500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1804240517500. Starting simulation... +info: Entering event queue @ 1804352925500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1805240517500. Starting simulation... +info: Entering event queue @ 1805352925500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1806240517500. Starting simulation... +info: Entering event queue @ 1806352925500. Starting simulation... switching cpus -info: Entering event queue @ 1807240389500. Starting simulation... +info: Entering event queue @ 1807352797500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1808240389500. Starting simulation... +info: Entering event queue @ 1808352797500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1809240389500. Starting simulation... +info: Entering event queue @ 1809352797500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1810240389500. Starting simulation... +info: Entering event queue @ 1810352797500. Starting simulation... switching cpus -info: Entering event queue @ 1811240261500. Starting simulation... +info: Entering event queue @ 1811352669500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1812240261500. Starting simulation... +info: Entering event queue @ 1812352669500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1813240261500. Starting simulation... +info: Entering event queue @ 1813352669500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1814240261500. Starting simulation... +info: Entering event queue @ 1814352669500. Starting simulation... switching cpus -info: Entering event queue @ 1815240133500. Starting simulation... +info: Entering event queue @ 1815352541500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1816240133500. Starting simulation... +info: Entering event queue @ 1816352541500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1817240133500. Starting simulation... +info: Entering event queue @ 1817352541500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1818240133500. Starting simulation... +info: Entering event queue @ 1818352541500. Starting simulation... switching cpus -info: Entering event queue @ 1819240005500. Starting simulation... +info: Entering event queue @ 1819352413500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1820240005500. Starting simulation... +info: Entering event queue @ 1820352413500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1821240005500. Starting simulation... +info: Entering event queue @ 1821352413500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1822240005500. Starting simulation... +info: Entering event queue @ 1822352413500. Starting simulation... switching cpus -info: Entering event queue @ 1823239877500. Starting simulation... +info: Entering event queue @ 1823352285500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1824239877500. Starting simulation... +info: Entering event queue @ 1824352285500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1825239877500. Starting simulation... +info: Entering event queue @ 1825352285500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1826239877500. Starting simulation... +info: Entering event queue @ 1826352285500. Starting simulation... switching cpus -info: Entering event queue @ 1827239749500. Starting simulation... +info: Entering event queue @ 1827352157500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1828239749500. Starting simulation... +info: Entering event queue @ 1828352157500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1829239749500. Starting simulation... +info: Entering event queue @ 1829352157500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1830239749500. Starting simulation... +info: Entering event queue @ 1830352157500. Starting simulation... switching cpus -info: Entering event queue @ 1831239621500. Starting simulation... +info: Entering event queue @ 1831352029500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1832239621500. Starting simulation... +info: Entering event queue @ 1832352029500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1833239621500. Starting simulation... +info: Entering event queue @ 1833352029500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1834239621500. Starting simulation... +info: Entering event queue @ 1834352029500. Starting simulation... switching cpus -info: Entering event queue @ 1835239493500. Starting simulation... +info: Entering event queue @ 1835351901500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1836239493500. Starting simulation... +info: Entering event queue @ 1836351901500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1837239493500. Starting simulation... +info: Entering event queue @ 1837351901500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1838239493500. Starting simulation... +info: Entering event queue @ 1838351901500. Starting simulation... switching cpus -info: Entering event queue @ 1839239365500. Starting simulation... +info: Entering event queue @ 1839351773500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1840239365500. Starting simulation... +info: Entering event queue @ 1840351773500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1841239365500. Starting simulation... +info: Entering event queue @ 1841351773500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1842239365500. Starting simulation... +info: Entering event queue @ 1842351773500. Starting simulation... switching cpus -info: Entering event queue @ 1843239237500. Starting simulation... +info: Entering event queue @ 1843351645500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1844239237500. Starting simulation... +info: Entering event queue @ 1844351645500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1845239237500. Starting simulation... +info: Entering event queue @ 1845351645500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1846239237500. Starting simulation... +info: Entering event queue @ 1846351645500. Starting simulation... switching cpus -info: Entering event queue @ 1847239109500. Starting simulation... +info: Entering event queue @ 1847351517500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1848239109500. Starting simulation... +info: Entering event queue @ 1848351517500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1849239109500. Starting simulation... +info: Entering event queue @ 1849351517500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1850239109500. Starting simulation... +info: Entering event queue @ 1850351517500. Starting simulation... switching cpus -info: Entering event queue @ 1851238981500. Starting simulation... +info: Entering event queue @ 1851351389500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1852238981500. Starting simulation... +info: Entering event queue @ 1852351389500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1853238981500. Starting simulation... +info: Entering event queue @ 1853351389500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1854238981500. Starting simulation... +info: Entering event queue @ 1854351389500. Starting simulation... switching cpus -info: Entering event queue @ 1855238853500. Starting simulation... +info: Entering event queue @ 1855351261500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1856238853500. Starting simulation... +info: Entering event queue @ 1856351261500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1857238853500. Starting simulation... +info: Entering event queue @ 1857351261500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1858238853500. Starting simulation... +info: Entering event queue @ 1858351261500. Starting simulation... switching cpus -info: Entering event queue @ 1859238725500. Starting simulation... +info: Entering event queue @ 1859351133500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1860238725500. Starting simulation... +info: Entering event queue @ 1860351133500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1861238725500. Starting simulation... +info: Entering event queue @ 1861351133500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1862238725500. Starting simulation... +info: Entering event queue @ 1862351133500. Starting simulation... switching cpus -info: Entering event queue @ 1863238597500. Starting simulation... +info: Entering event queue @ 1863351005500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1864238597500. Starting simulation... +info: Entering event queue @ 1864351005500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1865238597500. Starting simulation... +info: Entering event queue @ 1865351005500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1866238597500. Starting simulation... +info: Entering event queue @ 1866351005500. Starting simulation... switching cpus -info: Entering event queue @ 1867238469500. Starting simulation... +info: Entering event queue @ 1867350877500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1868238469500. Starting simulation... +info: Entering event queue @ 1868350877500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1869238469500. Starting simulation... +info: Entering event queue @ 1869350877500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1870238469500. Starting simulation... +info: Entering event queue @ 1870350877500. Starting simulation... switching cpus -info: Entering event queue @ 1871238341500. Starting simulation... +info: Entering event queue @ 1871350749500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1872238341500. Starting simulation... +info: Entering event queue @ 1872350749500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1873238341500. Starting simulation... +info: Entering event queue @ 1873350749500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1874238341500. Starting simulation... +info: Entering event queue @ 1874350749500. Starting simulation... switching cpus -info: Entering event queue @ 1875238213500. Starting simulation... +info: Entering event queue @ 1875350621500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1876238213500. Starting simulation... +info: Entering event queue @ 1876350621500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1877238213500. Starting simulation... +info: Entering event queue @ 1877350621500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1878238213500. Starting simulation... +info: Entering event queue @ 1878350621500. Starting simulation... switching cpus -info: Entering event queue @ 1879238085500. Starting simulation... +info: Entering event queue @ 1879350493500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1880238085500. Starting simulation... +info: Entering event queue @ 1880350493500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1881238085500. Starting simulation... +info: Entering event queue @ 1881350493500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1882238085500. Starting simulation... +info: Entering event queue @ 1882350493500. Starting simulation... switching cpus -info: Entering event queue @ 1883237957500. Starting simulation... +info: Entering event queue @ 1883350365500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1884237957500. Starting simulation... +info: Entering event queue @ 1884350365500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1885237957500. Starting simulation... +info: Entering event queue @ 1885350365500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1886237957500. Starting simulation... +info: Entering event queue @ 1886350365500. Starting simulation... switching cpus -info: Entering event queue @ 1887237829500. Starting simulation... +info: Entering event queue @ 1887350237500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1888237829500. Starting simulation... +info: Entering event queue @ 1888350237500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1889237829500. Starting simulation... +info: Entering event queue @ 1889350237500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1890237829500. Starting simulation... +info: Entering event queue @ 1890350237500. Starting simulation... switching cpus -info: Entering event queue @ 1891237701500. Starting simulation... +info: Entering event queue @ 1891350109500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1892237701500. Starting simulation... +info: Entering event queue @ 1892350109500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1893237701500. Starting simulation... +info: Entering event queue @ 1893350109500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1894237701500. Starting simulation... +info: Entering event queue @ 1894350109500. Starting simulation... switching cpus -info: Entering event queue @ 1895237573500. Starting simulation... +info: Entering event queue @ 1895349981500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1896237573500. Starting simulation... +info: Entering event queue @ 1896349981500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1897237573500. Starting simulation... +info: Entering event queue @ 1897349981500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1898237573500. Starting simulation... +info: Entering event queue @ 1898349981500. Starting simulation... switching cpus -info: Entering event queue @ 1899237445500. Starting simulation... +info: Entering event queue @ 1899349853500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1900237445500. Starting simulation... +info: Entering event queue @ 1900349853500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1901237445500. Starting simulation... +info: Entering event queue @ 1901349853500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1902237445500. Starting simulation... +info: Entering event queue @ 1902349853500. Starting simulation... switching cpus -info: Entering event queue @ 1903237317500. Starting simulation... +info: Entering event queue @ 1903349725500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1904237317500. Starting simulation... +info: Entering event queue @ 1904349725500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1905237317500. Starting simulation... +info: Entering event queue @ 1905349725500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1906237317500. Starting simulation... +info: Entering event queue @ 1906349725500. Starting simulation... switching cpus -info: Entering event queue @ 1907237189500. Starting simulation... +info: Entering event queue @ 1907349597500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1908237189500. Starting simulation... +info: Entering event queue @ 1908349597500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1909237189500. Starting simulation... +info: Entering event queue @ 1909349597500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1910237189500. Starting simulation... +info: Entering event queue @ 1910349597500. Starting simulation... switching cpus -info: Entering event queue @ 1911237061500. Starting simulation... +info: Entering event queue @ 1911349469500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1912237061500. Starting simulation... +info: Entering event queue @ 1912349469500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 1913349469500. Starting simulation... switching cpus -info: Entering event queue @ 1913237061500. Starting simulation... +info: Entering event queue @ 1913349477000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1914237061500. Starting simulation... +info: Entering event queue @ 1914349477000. Starting simulation... switching cpus -info: Entering event queue @ 1915236933500. Starting simulation... +info: Entering event queue @ 1915349341500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1916236933500. Starting simulation... +info: Entering event queue @ 1916349341500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1917236933500. Starting simulation... +info: Entering event queue @ 1917349341500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1918236933500. Starting simulation... +info: Entering event queue @ 1918349341500. Starting simulation... switching cpus -info: Entering event queue @ 1919236805500. Starting simulation... +info: Entering event queue @ 1919349213500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1920236805500. Starting simulation... +info: Entering event queue @ 1920349213500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1921236805500. Starting simulation... +info: Entering event queue @ 1921349213500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1922236805500. Starting simulation... +info: Entering event queue @ 1922349213500. Starting simulation... switching cpus -info: Entering event queue @ 1923236677500. Starting simulation... +info: Entering event queue @ 1923349085500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1924236677500. Starting simulation... +info: Entering event queue @ 1924349085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1925236677500. Starting simulation... +info: Entering event queue @ 1925349085500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1926236677500. Starting simulation... +info: Entering event queue @ 1926349085500. Starting simulation... switching cpus -info: Entering event queue @ 1927236549500. Starting simulation... +info: Entering event queue @ 1927348957500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1928236549500. Starting simulation... +info: Entering event queue @ 1928348957500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1929236549500. Starting simulation... +info: Entering event queue @ 1929348957500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1930236549500. Starting simulation... +info: Entering event queue @ 1930348957500. Starting simulation... switching cpus -info: Entering event queue @ 1931236421500. Starting simulation... +info: Entering event queue @ 1931348829500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1932236421500. Starting simulation... +info: Entering event queue @ 1932348829500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1933236421500. Starting simulation... +info: Entering event queue @ 1933348829500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1934236421500. Starting simulation... +info: Entering event queue @ 1934348829500. Starting simulation... switching cpus -info: Entering event queue @ 1935236293500. Starting simulation... +info: Entering event queue @ 1935348701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1936236293500. Starting simulation... +info: Entering event queue @ 1936348701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1937236293500. Starting simulation... +info: Entering event queue @ 1937348701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1938236293500. Starting simulation... +info: Entering event queue @ 1938348701500. Starting simulation... switching cpus -info: Entering event queue @ 1939236165500. Starting simulation... +info: Entering event queue @ 1939348573500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1940236165500. Starting simulation... +info: Entering event queue @ 1940348573500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1941236165500. Starting simulation... +info: Entering event queue @ 1941348573500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1942236165500. Starting simulation... +info: Entering event queue @ 1942348573500. Starting simulation... switching cpus -info: Entering event queue @ 1943236037500. Starting simulation... +info: Entering event queue @ 1943348445500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1944236037500. Starting simulation... +info: Entering event queue @ 1944348445500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1945236037500. Starting simulation... +info: Entering event queue @ 1945348445500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1946236037500. Starting simulation... +info: Entering event queue @ 1946348445500. Starting simulation... switching cpus -info: Entering event queue @ 1947235909500. Starting simulation... +info: Entering event queue @ 1947348317500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1948235909500. Starting simulation... +info: Entering event queue @ 1948348317500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1949235909500. Starting simulation... +info: Entering event queue @ 1949348317500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1950235909500. Starting simulation... +info: Entering event queue @ 1950348317500. Starting simulation... switching cpus -info: Entering event queue @ 1951235781500. Starting simulation... +info: Entering event queue @ 1951348189500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1952235781500. Starting simulation... +info: Entering event queue @ 1952348189500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1953235781500. Starting simulation... +info: Entering event queue @ 1953348189500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1954235781500. Starting simulation... +info: Entering event queue @ 1954348189500. Starting simulation... switching cpus -info: Entering event queue @ 1955235653500. Starting simulation... +info: Entering event queue @ 1955348061500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1956235653500. Starting simulation... +info: Entering event queue @ 1956348061500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1957235653500. Starting simulation... +info: Entering event queue @ 1957348061500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1958235653500. Starting simulation... +info: Entering event queue @ 1958348061500. Starting simulation... switching cpus -info: Entering event queue @ 1959235525500. Starting simulation... +info: Entering event queue @ 1959347933500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1960235525500. Starting simulation... +info: Entering event queue @ 1960347933500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1961235525500. Starting simulation... +info: Entering event queue @ 1961347933500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1962235525500. Starting simulation... +info: Entering event queue @ 1962347933500. Starting simulation... switching cpus -info: Entering event queue @ 1963235397500. Starting simulation... +info: Entering event queue @ 1963347805500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1964235397500. Starting simulation... +info: Entering event queue @ 1964347805500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1965235397500. Starting simulation... +info: Entering event queue @ 1965347805500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1966235397500. Starting simulation... +info: Entering event queue @ 1966347805500. Starting simulation... switching cpus -info: Entering event queue @ 1967235269500. Starting simulation... +info: Entering event queue @ 1967347677500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1968235269500. Starting simulation... +info: Entering event queue @ 1968347677500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1969235269500. Starting simulation... +info: Entering event queue @ 1969347677500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1970235269500. Starting simulation... +info: Entering event queue @ 1970347677500. Starting simulation... switching cpus -info: Entering event queue @ 1971235141500. Starting simulation... +info: Entering event queue @ 1971347549500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1972235141500. Starting simulation... +info: Entering event queue @ 1972347549500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1973235141500. Starting simulation... +info: Entering event queue @ 1973347549500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1974235141500. Starting simulation... +info: Entering event queue @ 1974347549500. Starting simulation... switching cpus -info: Entering event queue @ 1975235013500. Starting simulation... +info: Entering event queue @ 1975347421500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1976235013500. Starting simulation... +info: Entering event queue @ 1976347421500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1977235013500. Starting simulation... +info: Entering event queue @ 1977347421500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1978235013500. Starting simulation... +info: Entering event queue @ 1978347421500. Starting simulation... switching cpus -info: Entering event queue @ 1979234885500. Starting simulation... +info: Entering event queue @ 1979347293500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1980234885500. Starting simulation... +info: Entering event queue @ 1980347293500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1981234885500. Starting simulation... +info: Entering event queue @ 1981347293500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1982234885500. Starting simulation... +info: Entering event queue @ 1982347293500. Starting simulation... switching cpus -info: Entering event queue @ 1983234757500. Starting simulation... +info: Entering event queue @ 1983347165500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1984234757500. Starting simulation... +info: Entering event queue @ 1984347165500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1985234757500. Starting simulation... +info: Entering event queue @ 1985347165500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1986234757500. Starting simulation... +info: Entering event queue @ 1986347165500. Starting simulation... switching cpus -info: Entering event queue @ 1987234629500. Starting simulation... +info: Entering event queue @ 1987347037500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1988234629500. Starting simulation... +info: Entering event queue @ 1988347037500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1989234629500. Starting simulation... +info: Entering event queue @ 1989347037500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1990234629500. Starting simulation... +info: Entering event queue @ 1990347037500. Starting simulation... switching cpus -info: Entering event queue @ 1991234501500. Starting simulation... +info: Entering event queue @ 1991346909500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1992234501500. Starting simulation... +info: Entering event queue @ 1992346909500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1993234501500. Starting simulation... +info: Entering event queue @ 1993346909500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1994234501500. Starting simulation... +info: Entering event queue @ 1994346909500. Starting simulation... switching cpus -info: Entering event queue @ 1995234373500. Starting simulation... +info: Entering event queue @ 1995346781500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1996234373500. Starting simulation... +info: Entering event queue @ 1996346781500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1997234373500. Starting simulation... +info: Entering event queue @ 1997346781500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1998234373500. Starting simulation... +info: Entering event queue @ 1998346781500. Starting simulation... switching cpus -info: Entering event queue @ 1999234245500. Starting simulation... +info: Entering event queue @ 1999346653500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2000234245500. Starting simulation... +info: Entering event queue @ 2000346653500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2001234245500. Starting simulation... +info: Entering event queue @ 2001346653500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2002234245500. Starting simulation... +info: Entering event queue @ 2002346653500. Starting simulation... switching cpus -info: Entering event queue @ 2003234117500. Starting simulation... +info: Entering event queue @ 2003346525500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2004234117500. Starting simulation... +info: Entering event queue @ 2004346525500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2005234117500. Starting simulation... +info: Entering event queue @ 2005346525500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2006234117500. Starting simulation... +info: Entering event queue @ 2006346525500. Starting simulation... switching cpus -info: Entering event queue @ 2007233989500. Starting simulation... +info: Entering event queue @ 2007346397500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2008233989500. Starting simulation... +info: Entering event queue @ 2008346397500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2009233989500. Starting simulation... +info: Entering event queue @ 2009346397500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2010233989500. Starting simulation... +info: Entering event queue @ 2010346397500. Starting simulation... switching cpus -info: Entering event queue @ 2011233861500. Starting simulation... +info: Entering event queue @ 2011346269500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2012233861500. Starting simulation... +info: Entering event queue @ 2012346269500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2013233861500. Starting simulation... +info: Entering event queue @ 2013346269500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2014233861500. Starting simulation... +info: Entering event queue @ 2014346269500. Starting simulation... switching cpus -info: Entering event queue @ 2015233733500. Starting simulation... +info: Entering event queue @ 2015346141500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2016233733500. Starting simulation... +info: Entering event queue @ 2016346141500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2017233733500. Starting simulation... +info: Entering event queue @ 2017346141500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2018233733500. Starting simulation... +info: Entering event queue @ 2018346141500. Starting simulation... switching cpus -info: Entering event queue @ 2019233605500. Starting simulation... +info: Entering event queue @ 2019346013500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2020233605500. Starting simulation... +info: Entering event queue @ 2020346013500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2021233605500. Starting simulation... +info: Entering event queue @ 2021346013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2022233605500. Starting simulation... +info: Entering event queue @ 2022346013500. Starting simulation... switching cpus -info: Entering event queue @ 2023233477500. Starting simulation... +info: Entering event queue @ 2023345885500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2024233477500. Starting simulation... +info: Entering event queue @ 2024345885500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2025233477500. Starting simulation... +info: Entering event queue @ 2025345885500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2026233477500. Starting simulation... +info: Entering event queue @ 2026345885500. Starting simulation... switching cpus -info: Entering event queue @ 2027233349500. Starting simulation... +info: Entering event queue @ 2027345757500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2028233349500. Starting simulation... +info: Entering event queue @ 2028345757500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2029233349500. Starting simulation... +info: Entering event queue @ 2029345757500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2030233349500. Starting simulation... +info: Entering event queue @ 2030345757500. Starting simulation... switching cpus -info: Entering event queue @ 2031233221500. Starting simulation... +info: Entering event queue @ 2031345629500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2032233221500. Starting simulation... +info: Entering event queue @ 2032345629500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2033233221500. Starting simulation... +info: Entering event queue @ 2033345629500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2034233221500. Starting simulation... +info: Entering event queue @ 2034345629500. Starting simulation... switching cpus -info: Entering event queue @ 2035233093500. Starting simulation... +info: Entering event queue @ 2035345501500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2036233093500. Starting simulation... +info: Entering event queue @ 2036345501500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2037233093500. Starting simulation... +info: Entering event queue @ 2037345501500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2038233093500. Starting simulation... +info: Entering event queue @ 2038345501500. Starting simulation... switching cpus -info: Entering event queue @ 2039232965500. Starting simulation... +info: Entering event queue @ 2039345373500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2040232965500. Starting simulation... +info: Entering event queue @ 2040345373500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2041232965500. Starting simulation... +info: Entering event queue @ 2041345373500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2042232965500. Starting simulation... +info: Entering event queue @ 2042345373500. Starting simulation... switching cpus -info: Entering event queue @ 2043232837500. Starting simulation... +info: Entering event queue @ 2043345245500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2044232837500. Starting simulation... +info: Entering event queue @ 2044345245500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2045232837500. Starting simulation... +info: Entering event queue @ 2045345245500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2046232837500. Starting simulation... +info: Entering event queue @ 2046345245500. Starting simulation... switching cpus -info: Entering event queue @ 2047232709500. Starting simulation... +info: Entering event queue @ 2047345117500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2048232709500. Starting simulation... +info: Entering event queue @ 2048345117500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2049232709500. Starting simulation... +info: Entering event queue @ 2049345117500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2050232709500. Starting simulation... +info: Entering event queue @ 2050345117500. Starting simulation... switching cpus -info: Entering event queue @ 2051232581500. Starting simulation... +info: Entering event queue @ 2051344989500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2052232581500. Starting simulation... +info: Entering event queue @ 2052344989500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2053232581500. Starting simulation... +info: Entering event queue @ 2053344989500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2054232581500. Starting simulation... +info: Entering event queue @ 2054344989500. Starting simulation... switching cpus -info: Entering event queue @ 2055232453500. Starting simulation... +info: Entering event queue @ 2055344861500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2056232453500. Starting simulation... +info: Entering event queue @ 2056344861500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2057232453500. Starting simulation... +info: Entering event queue @ 2057344861500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2058232453500. Starting simulation... +info: Entering event queue @ 2058344861500. Starting simulation... switching cpus -info: Entering event queue @ 2059232325500. Starting simulation... +info: Entering event queue @ 2059344733500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2060232325500. Starting simulation... +info: Entering event queue @ 2060344733500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2061232325500. Starting simulation... +info: Entering event queue @ 2061344733500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2062232325500. Starting simulation... +info: Entering event queue @ 2062344733500. Starting simulation... switching cpus -info: Entering event queue @ 2063232197500. Starting simulation... +info: Entering event queue @ 2063344605500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2064232197500. Starting simulation... +info: Entering event queue @ 2064344605500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2065232197500. Starting simulation... +info: Entering event queue @ 2065344605500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2066232197500. Starting simulation... +info: Entering event queue @ 2066344605500. Starting simulation... switching cpus -info: Entering event queue @ 2067232069500. Starting simulation... +info: Entering event queue @ 2067344477500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2068232069500. Starting simulation... +info: Entering event queue @ 2068344477500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2069232069500. Starting simulation... +info: Entering event queue @ 2069344477500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2070232069500. Starting simulation... +info: Entering event queue @ 2070344477500. Starting simulation... switching cpus -info: Entering event queue @ 2071231941500. Starting simulation... +info: Entering event queue @ 2071344349500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2072231941500. Starting simulation... +info: Entering event queue @ 2072344349500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2073231941500. Starting simulation... +info: Entering event queue @ 2073344349500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2074231941500. Starting simulation... +info: Entering event queue @ 2074344349500. Starting simulation... switching cpus -info: Entering event queue @ 2075231813500. Starting simulation... +info: Entering event queue @ 2075344221500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2076231813500. Starting simulation... +info: Entering event queue @ 2076344221500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2077231813500. Starting simulation... +info: Entering event queue @ 2077344221500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2078231813500. Starting simulation... +info: Entering event queue @ 2078344221500. Starting simulation... switching cpus -info: Entering event queue @ 2079231685500. Starting simulation... +info: Entering event queue @ 2079344093500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2080231685500. Starting simulation... +info: Entering event queue @ 2080344093500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2081231685500. Starting simulation... +info: Entering event queue @ 2081344093500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2082231685500. Starting simulation... +info: Entering event queue @ 2082344093500. Starting simulation... switching cpus -info: Entering event queue @ 2083231557500. Starting simulation... +info: Entering event queue @ 2083343965500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2084231557500. Starting simulation... +info: Entering event queue @ 2084343965500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2085231557500. Starting simulation... +info: Entering event queue @ 2085343965500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2086231557500. Starting simulation... +info: Entering event queue @ 2086343965500. Starting simulation... switching cpus -info: Entering event queue @ 2087231429500. Starting simulation... +info: Entering event queue @ 2087343837500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2088231429500. Starting simulation... +info: Entering event queue @ 2088343837500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2089231429500. Starting simulation... +info: Entering event queue @ 2089343837500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2090231429500. Starting simulation... +info: Entering event queue @ 2090343837500. Starting simulation... switching cpus -info: Entering event queue @ 2091231301500. Starting simulation... +info: Entering event queue @ 2091343709500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2092231301500. Starting simulation... +info: Entering event queue @ 2092343709500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2093231301500. Starting simulation... +info: Entering event queue @ 2093343709500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2094231301500. Starting simulation... +info: Entering event queue @ 2094343709500. Starting simulation... switching cpus -info: Entering event queue @ 2095231173500. Starting simulation... +info: Entering event queue @ 2095343581500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2096231173500. Starting simulation... +info: Entering event queue @ 2096343581500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2097231173500. Starting simulation... +info: Entering event queue @ 2097343581500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2098231173500. Starting simulation... +info: Entering event queue @ 2098343581500. Starting simulation... switching cpus -info: Entering event queue @ 2099231045500. Starting simulation... +info: Entering event queue @ 2099343453500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2100231045500. Starting simulation... +info: Entering event queue @ 2100343453500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2101231045500. Starting simulation... +info: Entering event queue @ 2101343453500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2102231045500. Starting simulation... +info: Entering event queue @ 2102343453500. Starting simulation... switching cpus -info: Entering event queue @ 2103230917500. Starting simulation... +info: Entering event queue @ 2103343325500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2104230917500. Starting simulation... +info: Entering event queue @ 2104343325500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2105230917500. Starting simulation... +info: Entering event queue @ 2105343325500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2106230917500. Starting simulation... +info: Entering event queue @ 2106343325500. Starting simulation... switching cpus -info: Entering event queue @ 2107230789500. Starting simulation... +info: Entering event queue @ 2107343197500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2108230789500. Starting simulation... +info: Entering event queue @ 2108343197500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2109230789500. Starting simulation... +info: Entering event queue @ 2109343197500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2110230789500. Starting simulation... +info: Entering event queue @ 2110343197500. Starting simulation... switching cpus -info: Entering event queue @ 2111230661500. Starting simulation... +info: Entering event queue @ 2111343069500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2112230661500. Starting simulation... +info: Entering event queue @ 2112343069500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2113230661500. Starting simulation... +info: Entering event queue @ 2113343069500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2114230661500. Starting simulation... +info: Entering event queue @ 2114343069500. Starting simulation... switching cpus -info: Entering event queue @ 2115230533500. Starting simulation... +info: Entering event queue @ 2115342941500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2116230533500. Starting simulation... +info: Entering event queue @ 2116342941500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2117230533500. Starting simulation... +info: Entering event queue @ 2117342941500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2118230533500. Starting simulation... +info: Entering event queue @ 2118342941500. Starting simulation... switching cpus -info: Entering event queue @ 2119230405500. Starting simulation... +info: Entering event queue @ 2119342813500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2120230405500. Starting simulation... +info: Entering event queue @ 2120342813500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2121230405500. Starting simulation... +info: Entering event queue @ 2121342813500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2122230405500. Starting simulation... +info: Entering event queue @ 2122342813500. Starting simulation... switching cpus -info: Entering event queue @ 2123230277500. Starting simulation... +info: Entering event queue @ 2123342685500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2124230277500. Starting simulation... +info: Entering event queue @ 2124342685500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2125230277500. Starting simulation... +info: Entering event queue @ 2125342685500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2126230277500. Starting simulation... +info: Entering event queue @ 2126342685500. Starting simulation... switching cpus -info: Entering event queue @ 2127230149500. Starting simulation... +info: Entering event queue @ 2127342557500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2128230149500. Starting simulation... +info: Entering event queue @ 2128342557500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2129230149500. Starting simulation... +info: Entering event queue @ 2129342557500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2130230149500. Starting simulation... +info: Entering event queue @ 2130342557500. Starting simulation... switching cpus -info: Entering event queue @ 2131230021500. Starting simulation... +info: Entering event queue @ 2131342429500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2132230021500. Starting simulation... +info: Entering event queue @ 2132342429500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2133230021500. Starting simulation... +info: Entering event queue @ 2133342429500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2134230021500. Starting simulation... +info: Entering event queue @ 2134342429500. Starting simulation... switching cpus -info: Entering event queue @ 2135229893500. Starting simulation... +info: Entering event queue @ 2135342301500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2136229893500. Starting simulation... +info: Entering event queue @ 2136342301500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2137229893500. Starting simulation... +info: Entering event queue @ 2137342301500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2138229893500. Starting simulation... +info: Entering event queue @ 2138342301500. Starting simulation... switching cpus -info: Entering event queue @ 2139229765500. Starting simulation... +info: Entering event queue @ 2139342173500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2140229765500. Starting simulation... +info: Entering event queue @ 2140342173500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2141229765500. Starting simulation... +info: Entering event queue @ 2141342173500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2142229765500. Starting simulation... +info: Entering event queue @ 2142342173500. Starting simulation... switching cpus -info: Entering event queue @ 2143229637500. Starting simulation... +info: Entering event queue @ 2143342045500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2144229637500. Starting simulation... +info: Entering event queue @ 2144342045500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2145229637500. Starting simulation... +info: Entering event queue @ 2145342045500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2146229637500. Starting simulation... +info: Entering event queue @ 2146342045500. Starting simulation... switching cpus -info: Entering event queue @ 2147229509500. Starting simulation... +info: Entering event queue @ 2147341917500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2148229509500. Starting simulation... +info: Entering event queue @ 2148341917500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2149229509500. Starting simulation... +info: Entering event queue @ 2149341917500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2150229509500. Starting simulation... +info: Entering event queue @ 2150341917500. Starting simulation... switching cpus -info: Entering event queue @ 2151229381500. Starting simulation... +info: Entering event queue @ 2151341789500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2152229381500. Starting simulation... +info: Entering event queue @ 2152341789500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2153229381500. Starting simulation... +info: Entering event queue @ 2153341789500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2154229381500. Starting simulation... +info: Entering event queue @ 2154341789500. Starting simulation... switching cpus -info: Entering event queue @ 2155229253500. Starting simulation... +info: Entering event queue @ 2155341661500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2156229253500. Starting simulation... +info: Entering event queue @ 2156341661500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2157229253500. Starting simulation... +info: Entering event queue @ 2157341661500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2158229253500. Starting simulation... +info: Entering event queue @ 2158341661500. Starting simulation... switching cpus -info: Entering event queue @ 2159229125500. Starting simulation... +info: Entering event queue @ 2159341533500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2160229125500. Starting simulation... +info: Entering event queue @ 2160341533500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2161229125500. Starting simulation... +info: Entering event queue @ 2161341533500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2162229125500. Starting simulation... +info: Entering event queue @ 2162341533500. Starting simulation... switching cpus -info: Entering event queue @ 2163228997500. Starting simulation... +info: Entering event queue @ 2163341405500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2164228997500. Starting simulation... +info: Entering event queue @ 2164341405500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2165228997500. Starting simulation... +info: Entering event queue @ 2165341405500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2166228997500. Starting simulation... +info: Entering event queue @ 2166341405500. Starting simulation... switching cpus -info: Entering event queue @ 2167228869500. Starting simulation... +info: Entering event queue @ 2167341277500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2168228869500. Starting simulation... +info: Entering event queue @ 2168341277500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2169228869500. Starting simulation... +info: Entering event queue @ 2169341277500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2170228869500. Starting simulation... +info: Entering event queue @ 2170341277500. Starting simulation... switching cpus -info: Entering event queue @ 2171228741500. Starting simulation... +info: Entering event queue @ 2171341149500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2172228741500. Starting simulation... +info: Entering event queue @ 2172341149500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2173228741500. Starting simulation... +info: Entering event queue @ 2173341149500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2174228741500. Starting simulation... +info: Entering event queue @ 2174341149500. Starting simulation... switching cpus -info: Entering event queue @ 2175228613500. Starting simulation... +info: Entering event queue @ 2175341021500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2176228613500. Starting simulation... +info: Entering event queue @ 2176341021500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2177228613500. Starting simulation... +info: Entering event queue @ 2177341021500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2178228613500. Starting simulation... +info: Entering event queue @ 2178341021500. Starting simulation... switching cpus -info: Entering event queue @ 2179228485500. Starting simulation... +info: Entering event queue @ 2179340893500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2180228485500. Starting simulation... +info: Entering event queue @ 2180340893500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2181228485500. Starting simulation... +info: Entering event queue @ 2181340893500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2182228485500. Starting simulation... +info: Entering event queue @ 2182340893500. Starting simulation... switching cpus -info: Entering event queue @ 2183228357500. Starting simulation... +info: Entering event queue @ 2183340765500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2184228357500. Starting simulation... +info: Entering event queue @ 2184340765500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2185228357500. Starting simulation... +info: Entering event queue @ 2185340765500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2186228357500. Starting simulation... +info: Entering event queue @ 2186340765500. Starting simulation... switching cpus -info: Entering event queue @ 2187228229500. Starting simulation... +info: Entering event queue @ 2187340637500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2188228229500. Starting simulation... +info: Entering event queue @ 2188340637500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2189228229500. Starting simulation... +info: Entering event queue @ 2189340637500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2190228229500. Starting simulation... +info: Entering event queue @ 2190340637500. Starting simulation... switching cpus -info: Entering event queue @ 2191228101500. Starting simulation... +info: Entering event queue @ 2191340509500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2192228101500. Starting simulation... +info: Entering event queue @ 2192340509500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2193228101500. Starting simulation... +info: Entering event queue @ 2193340509500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2194228101500. Starting simulation... +info: Entering event queue @ 2194340509500. Starting simulation... switching cpus -info: Entering event queue @ 2195227973500. Starting simulation... +info: Entering event queue @ 2195340381500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2196227973500. Starting simulation... +info: Entering event queue @ 2196340381500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2197227973500. Starting simulation... +info: Entering event queue @ 2197340381500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2198227973500. Starting simulation... +info: Entering event queue @ 2198340381500. Starting simulation... switching cpus -info: Entering event queue @ 2199227845500. Starting simulation... +info: Entering event queue @ 2199340253500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2200227845500. Starting simulation... +info: Entering event queue @ 2200340253500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2201227845500. Starting simulation... +info: Entering event queue @ 2201340253500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2202227845500. Starting simulation... +info: Entering event queue @ 2202340253500. Starting simulation... switching cpus -info: Entering event queue @ 2203227717500. Starting simulation... +info: Entering event queue @ 2203340125500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2204227717500. Starting simulation... +info: Entering event queue @ 2204340125500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2205227717500. Starting simulation... +info: Entering event queue @ 2205340125500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2206227717500. Starting simulation... +info: Entering event queue @ 2206340125500. Starting simulation... switching cpus -info: Entering event queue @ 2207227589500. Starting simulation... +info: Entering event queue @ 2207339997500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2208227589500. Starting simulation... +info: Entering event queue @ 2208339997500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2209227589500. Starting simulation... +info: Entering event queue @ 2209339997500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2210227589500. Starting simulation... +info: Entering event queue @ 2210339997500. Starting simulation... switching cpus -info: Entering event queue @ 2211227461500. Starting simulation... +info: Entering event queue @ 2211339869500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2212227461500. Starting simulation... +info: Entering event queue @ 2212339869500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2213227461500. Starting simulation... +info: Entering event queue @ 2213339869500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2214227461500. Starting simulation... +info: Entering event queue @ 2214339869500. Starting simulation... switching cpus -info: Entering event queue @ 2215227333500. Starting simulation... +info: Entering event queue @ 2215339741500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2216227333500. Starting simulation... +info: Entering event queue @ 2216339741500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2217227333500. Starting simulation... +info: Entering event queue @ 2217339741500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2218227333500. Starting simulation... +info: Entering event queue @ 2218339741500. Starting simulation... switching cpus -info: Entering event queue @ 2219227205500. Starting simulation... +info: Entering event queue @ 2219339613500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2220227205500. Starting simulation... +info: Entering event queue @ 2220339613500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2221227205500. Starting simulation... +info: Entering event queue @ 2221339613500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2222227205500. Starting simulation... +info: Entering event queue @ 2222339613500. Starting simulation... switching cpus -info: Entering event queue @ 2223227077500. Starting simulation... +info: Entering event queue @ 2223339485500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2224227077500. Starting simulation... +info: Entering event queue @ 2224339485500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2225227077500. Starting simulation... +info: Entering event queue @ 2225339485500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2226227077500. Starting simulation... +info: Entering event queue @ 2226339485500. Starting simulation... switching cpus -info: Entering event queue @ 2227226949500. Starting simulation... +info: Entering event queue @ 2227339357500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2228226949500. Starting simulation... +info: Entering event queue @ 2228339357500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2229226949500. Starting simulation... +info: Entering event queue @ 2229339357500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2230226949500. Starting simulation... +info: Entering event queue @ 2230339357500. Starting simulation... switching cpus -info: Entering event queue @ 2231226821500. Starting simulation... +info: Entering event queue @ 2231339229500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2232226821500. Starting simulation... +info: Entering event queue @ 2232339229500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2233226821500. Starting simulation... +info: Entering event queue @ 2233339229500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2234226821500. Starting simulation... +info: Entering event queue @ 2234339229500. Starting simulation... switching cpus -info: Entering event queue @ 2235226693500. Starting simulation... +info: Entering event queue @ 2235339101500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2236226693500. Starting simulation... +info: Entering event queue @ 2236339101500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2237226693500. Starting simulation... +info: Entering event queue @ 2237339101500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2238226693500. Starting simulation... +info: Entering event queue @ 2238339101500. Starting simulation... switching cpus -info: Entering event queue @ 2239226565500. Starting simulation... +info: Entering event queue @ 2239338973500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2240226565500. Starting simulation... +info: Entering event queue @ 2240338973500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2241226565500. Starting simulation... +info: Entering event queue @ 2241338973500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2242226565500. Starting simulation... +info: Entering event queue @ 2242338973500. Starting simulation... switching cpus -info: Entering event queue @ 2243226437500. Starting simulation... +info: Entering event queue @ 2243338845500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2244226437500. Starting simulation... +info: Entering event queue @ 2244338845500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2245226437500. Starting simulation... +info: Entering event queue @ 2245338845500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2246226437500. Starting simulation... +info: Entering event queue @ 2246338845500. Starting simulation... switching cpus -info: Entering event queue @ 2247226309500. Starting simulation... +info: Entering event queue @ 2247338717500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2248226309500. Starting simulation... +info: Entering event queue @ 2248338717500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2249226309500. Starting simulation... +info: Entering event queue @ 2249338717500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2250226309500. Starting simulation... +info: Entering event queue @ 2250338717500. Starting simulation... switching cpus -info: Entering event queue @ 2251226181500. Starting simulation... +info: Entering event queue @ 2251338589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2252226181500. Starting simulation... +info: Entering event queue @ 2252338589500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2253226181500. Starting simulation... +info: Entering event queue @ 2253338589500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2254226181500. Starting simulation... +info: Entering event queue @ 2254338589500. Starting simulation... switching cpus -info: Entering event queue @ 2255226053500. Starting simulation... +info: Entering event queue @ 2255338461500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2256226053500. Starting simulation... +info: Entering event queue @ 2256338461500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2257226053500. Starting simulation... +info: Entering event queue @ 2257338461500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2258226053500. Starting simulation... +info: Entering event queue @ 2258338461500. Starting simulation... switching cpus -info: Entering event queue @ 2259225925500. Starting simulation... +info: Entering event queue @ 2259338333500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2260225925500. Starting simulation... +info: Entering event queue @ 2260338333500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2261225925500. Starting simulation... +info: Entering event queue @ 2261338333500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2262225925500. Starting simulation... +info: Entering event queue @ 2262338333500. Starting simulation... switching cpus -info: Entering event queue @ 2263225797500. Starting simulation... +info: Entering event queue @ 2263338205500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2264225797500. Starting simulation... +info: Entering event queue @ 2264338205500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2265225797500. Starting simulation... +info: Entering event queue @ 2265338205500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2266225797500. Starting simulation... +info: Entering event queue @ 2266338205500. Starting simulation... switching cpus -info: Entering event queue @ 2267225669500. Starting simulation... +info: Entering event queue @ 2267338077500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2268225669500. Starting simulation... +info: Entering event queue @ 2268338077500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2269225669500. Starting simulation... +info: Entering event queue @ 2269338077500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2270225669500. Starting simulation... +info: Entering event queue @ 2270338077500. Starting simulation... switching cpus -info: Entering event queue @ 2271225541500. Starting simulation... +info: Entering event queue @ 2271337949500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2272225541500. Starting simulation... +info: Entering event queue @ 2272337949500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2273225541500. Starting simulation... +info: Entering event queue @ 2273337949500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2274225541500. Starting simulation... +info: Entering event queue @ 2274337949500. Starting simulation... switching cpus -info: Entering event queue @ 2275225413500. Starting simulation... +info: Entering event queue @ 2275337821500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2276225413500. Starting simulation... +info: Entering event queue @ 2276337821500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2277225413500. Starting simulation... +info: Entering event queue @ 2277337821500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2278225413500. Starting simulation... +info: Entering event queue @ 2278337821500. Starting simulation... switching cpus -info: Entering event queue @ 2279225285500. Starting simulation... +info: Entering event queue @ 2279337693500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2280225285500. Starting simulation... +info: Entering event queue @ 2280337693500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2281225285500. Starting simulation... +info: Entering event queue @ 2281337693500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2282225285500. Starting simulation... +info: Entering event queue @ 2282337693500. Starting simulation... switching cpus -info: Entering event queue @ 2283225157500. Starting simulation... +info: Entering event queue @ 2283337565500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2284225157500. Starting simulation... +info: Entering event queue @ 2284337565500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2285225157500. Starting simulation... +info: Entering event queue @ 2285337565500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2286225157500. Starting simulation... +info: Entering event queue @ 2286337565500. Starting simulation... switching cpus -info: Entering event queue @ 2287225029500. Starting simulation... +info: Entering event queue @ 2287337437500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2288225029500. Starting simulation... +info: Entering event queue @ 2288337437500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2289225029500. Starting simulation... +info: Entering event queue @ 2289337437500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2290225029500. Starting simulation... +info: Entering event queue @ 2290337437500. Starting simulation... switching cpus -info: Entering event queue @ 2291224901500. Starting simulation... +info: Entering event queue @ 2291337309500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2292224901500. Starting simulation... +info: Entering event queue @ 2292337309500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2293224901500. Starting simulation... +info: Entering event queue @ 2293337309500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2294224901500. Starting simulation... +info: Entering event queue @ 2294337309500. Starting simulation... switching cpus -info: Entering event queue @ 2295224773500. Starting simulation... +info: Entering event queue @ 2295337181500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2296224773500. Starting simulation... +info: Entering event queue @ 2296337181500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2297224773500. Starting simulation... +info: Entering event queue @ 2297337181500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2298224773500. Starting simulation... +info: Entering event queue @ 2298337181500. Starting simulation... switching cpus -info: Entering event queue @ 2299224645500. Starting simulation... +info: Entering event queue @ 2299337053500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2300224645500. Starting simulation... +info: Entering event queue @ 2300337053500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2301224645500. Starting simulation... +info: Entering event queue @ 2301337053500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2302224645500. Starting simulation... +info: Entering event queue @ 2302337053500. Starting simulation... switching cpus -info: Entering event queue @ 2303224517500. Starting simulation... +info: Entering event queue @ 2303336925500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2304224517500. Starting simulation... +info: Entering event queue @ 2304336925500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2305224517500. Starting simulation... +info: Entering event queue @ 2305336925500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2306224517500. Starting simulation... +info: Entering event queue @ 2306336925500. Starting simulation... switching cpus -info: Entering event queue @ 2307224389500. Starting simulation... +info: Entering event queue @ 2307336797500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2308224389500. Starting simulation... +info: Entering event queue @ 2308336797500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2309224389500. Starting simulation... +info: Entering event queue @ 2309336797500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2310224389500. Starting simulation... +info: Entering event queue @ 2310336797500. Starting simulation... switching cpus -info: Entering event queue @ 2311224261500. Starting simulation... +info: Entering event queue @ 2311336669500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2312224261500. Starting simulation... +info: Entering event queue @ 2312336669500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2313224261500. Starting simulation... +info: Entering event queue @ 2313336669500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2314224261500. Starting simulation... +info: Entering event queue @ 2314336669500. Starting simulation... switching cpus -info: Entering event queue @ 2315224133500. Starting simulation... +info: Entering event queue @ 2315336541500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2316224133500. Starting simulation... +info: Entering event queue @ 2316336541500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2317224133500. Starting simulation... +info: Entering event queue @ 2317336541500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2318224133500. Starting simulation... +info: Entering event queue @ 2318336541500. Starting simulation... switching cpus -info: Entering event queue @ 2319224005500. Starting simulation... +info: Entering event queue @ 2319336413500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2320224005500. Starting simulation... +info: Entering event queue @ 2320336413500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2321224005500. Starting simulation... +info: Entering event queue @ 2321336413500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2322224005500. Starting simulation... +info: Entering event queue @ 2322336413500. Starting simulation... switching cpus -info: Entering event queue @ 2323223877500. Starting simulation... +info: Entering event queue @ 2323336285500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2324223877500. Starting simulation... +info: Entering event queue @ 2324336285500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2325223877500. Starting simulation... +info: Entering event queue @ 2325336285500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2326223877500. Starting simulation... +info: Entering event queue @ 2326336285500. Starting simulation... switching cpus -info: Entering event queue @ 2327223749500. Starting simulation... +info: Entering event queue @ 2327336157500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2328223749500. Starting simulation... +info: Entering event queue @ 2328336157500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2329223749500. Starting simulation... +info: Entering event queue @ 2329336157500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2330223749500. Starting simulation... +info: Entering event queue @ 2330336157500. Starting simulation... switching cpus -info: Entering event queue @ 2331223621500. Starting simulation... +info: Entering event queue @ 2331336029500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2332223621500. Starting simulation... +info: Entering event queue @ 2332336029500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2333223621500. Starting simulation... +info: Entering event queue @ 2333336029500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2334223621500. Starting simulation... +info: Entering event queue @ 2334336029500. Starting simulation... switching cpus -info: Entering event queue @ 2335223493500. Starting simulation... +info: Entering event queue @ 2335335901500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2336223493500. Starting simulation... +info: Entering event queue @ 2336335901500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2337223493500. Starting simulation... +info: Entering event queue @ 2337335901500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2338223493500. Starting simulation... +info: Entering event queue @ 2338335901500. Starting simulation... switching cpus -info: Entering event queue @ 2339223365500. Starting simulation... +info: Entering event queue @ 2339335773500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2340223365500. Starting simulation... +info: Entering event queue @ 2340335773500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2341223365500. Starting simulation... +info: Entering event queue @ 2341335773500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2342223365500. Starting simulation... +info: Entering event queue @ 2342335773500. Starting simulation... switching cpus -info: Entering event queue @ 2343223237500. Starting simulation... +info: Entering event queue @ 2343335645500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2344223237500. Starting simulation... +info: Entering event queue @ 2344335645500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2345223237500. Starting simulation... +info: Entering event queue @ 2345335645500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2346223237500. Starting simulation... +info: Entering event queue @ 2346335645500. Starting simulation... switching cpus -info: Entering event queue @ 2347223109500. Starting simulation... +info: Entering event queue @ 2347335517500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2348223109500. Starting simulation... +info: Entering event queue @ 2348335517500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2349223109500. Starting simulation... +info: Entering event queue @ 2349335517500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2350223109500. Starting simulation... +info: Entering event queue @ 2350335517500. Starting simulation... switching cpus -info: Entering event queue @ 2351222981500. Starting simulation... +info: Entering event queue @ 2351335389500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2352222981500. Starting simulation... +info: Entering event queue @ 2352335389500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2353222981500. Starting simulation... +info: Entering event queue @ 2353335389500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2354222981500. Starting simulation... +info: Entering event queue @ 2354335389500. Starting simulation... switching cpus -info: Entering event queue @ 2355222853500. Starting simulation... +info: Entering event queue @ 2355335261500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2356222853500. Starting simulation... +info: Entering event queue @ 2356335261500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2357222853500. Starting simulation... +info: Entering event queue @ 2357335261500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2358222853500. Starting simulation... +info: Entering event queue @ 2358335261500. Starting simulation... switching cpus -info: Entering event queue @ 2359222725500. Starting simulation... +info: Entering event queue @ 2359335133500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2360222725500. Starting simulation... +info: Entering event queue @ 2360335133500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2361222725500. Starting simulation... +info: Entering event queue @ 2361335133500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2362222725500. Starting simulation... +info: Entering event queue @ 2362335133500. Starting simulation... switching cpus -info: Entering event queue @ 2363222597500. Starting simulation... +info: Entering event queue @ 2363335005500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2364222597500. Starting simulation... +info: Entering event queue @ 2364335005500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2365222597500. Starting simulation... +info: Entering event queue @ 2365335005500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2366222597500. Starting simulation... +info: Entering event queue @ 2366335005500. Starting simulation... switching cpus -info: Entering event queue @ 2367222469500. Starting simulation... +info: Entering event queue @ 2367334877500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2368222469500. Starting simulation... +info: Entering event queue @ 2368334877500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2369222469500. Starting simulation... +info: Entering event queue @ 2369334877500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2370222469500. Starting simulation... +info: Entering event queue @ 2370334877500. Starting simulation... switching cpus -info: Entering event queue @ 2371222341500. Starting simulation... +info: Entering event queue @ 2371334749500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2372222341500. Starting simulation... +info: Entering event queue @ 2372334749500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2373222341500. Starting simulation... +info: Entering event queue @ 2373334749500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2374222341500. Starting simulation... +info: Entering event queue @ 2374334749500. Starting simulation... switching cpus -info: Entering event queue @ 2375222213500. Starting simulation... +info: Entering event queue @ 2375334621500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2376222213500. Starting simulation... +info: Entering event queue @ 2376334621500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2377222213500. Starting simulation... +info: Entering event queue @ 2377334621500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2378222213500. Starting simulation... +info: Entering event queue @ 2378334621500. Starting simulation... switching cpus -info: Entering event queue @ 2379222085500. Starting simulation... +info: Entering event queue @ 2379334493500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2380222085500. Starting simulation... +info: Entering event queue @ 2380334493500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2381222085500. Starting simulation... +info: Entering event queue @ 2381334493500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2382222085500. Starting simulation... +info: Entering event queue @ 2382334493500. Starting simulation... switching cpus -info: Entering event queue @ 2383221957500. Starting simulation... +info: Entering event queue @ 2383334365500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2384221957500. Starting simulation... +info: Entering event queue @ 2384334365500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2385221957500. Starting simulation... +info: Entering event queue @ 2385334365500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2386221957500. Starting simulation... +info: Entering event queue @ 2386334365500. Starting simulation... switching cpus -info: Entering event queue @ 2387221829500. Starting simulation... +info: Entering event queue @ 2387334237500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2388221829500. Starting simulation... +info: Entering event queue @ 2388334237500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2389221829500. Starting simulation... +info: Entering event queue @ 2389334237500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2390221829500. Starting simulation... +info: Entering event queue @ 2390334237500. Starting simulation... switching cpus -info: Entering event queue @ 2391221701500. Starting simulation... +info: Entering event queue @ 2391334109500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2392221701500. Starting simulation... +info: Entering event queue @ 2392334109500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2393221701500. Starting simulation... +info: Entering event queue @ 2393334109500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2394221701500. Starting simulation... +info: Entering event queue @ 2394334109500. Starting simulation... switching cpus -info: Entering event queue @ 2395221573500. Starting simulation... +info: Entering event queue @ 2395333981500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2396221573500. Starting simulation... +info: Entering event queue @ 2396333981500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2397221573500. Starting simulation... +info: Entering event queue @ 2397333981500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2398221573500. Starting simulation... +info: Entering event queue @ 2398333981500. Starting simulation... switching cpus -info: Entering event queue @ 2399221445500. Starting simulation... +info: Entering event queue @ 2399333853500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2400221445500. Starting simulation... +info: Entering event queue @ 2400333853500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2401221445500. Starting simulation... +info: Entering event queue @ 2401333853500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2402221445500. Starting simulation... +info: Entering event queue @ 2402333853500. Starting simulation... switching cpus -info: Entering event queue @ 2403221317500. Starting simulation... +info: Entering event queue @ 2403333725500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2404221317500. Starting simulation... +info: Entering event queue @ 2404333725500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2405221317500. Starting simulation... +info: Entering event queue @ 2405333725500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2406221317500. Starting simulation... +info: Entering event queue @ 2406333725500. Starting simulation... switching cpus -info: Entering event queue @ 2407221189500. Starting simulation... +info: Entering event queue @ 2407333597500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2408221189500. Starting simulation... +info: Entering event queue @ 2408333597500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2409221189500. Starting simulation... +info: Entering event queue @ 2409333597500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2410221189500. Starting simulation... +info: Entering event queue @ 2410333597500. Starting simulation... switching cpus -info: Entering event queue @ 2411221061500. Starting simulation... +info: Entering event queue @ 2411333469500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2412221061500. Starting simulation... +info: Entering event queue @ 2412333469500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2413221061500. Starting simulation... +info: Entering event queue @ 2413333469500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2414221061500. Starting simulation... +info: Entering event queue @ 2414333469500. Starting simulation... switching cpus -info: Entering event queue @ 2415220933500. Starting simulation... +info: Entering event queue @ 2415333341500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2416220933500. Starting simulation... +info: Entering event queue @ 2416333341500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2417220933500. Starting simulation... +info: Entering event queue @ 2417333341500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2418220933500. Starting simulation... +info: Entering event queue @ 2418333341500. Starting simulation... switching cpus -info: Entering event queue @ 2419220805500. Starting simulation... +info: Entering event queue @ 2419333213500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2420220805500. Starting simulation... +info: Entering event queue @ 2420333213500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2421220805500. Starting simulation... +info: Entering event queue @ 2421333213500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2422220805500. Starting simulation... +info: Entering event queue @ 2422333213500. Starting simulation... switching cpus -info: Entering event queue @ 2423220677500. Starting simulation... +info: Entering event queue @ 2423333085500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2424220677500. Starting simulation... +info: Entering event queue @ 2424333085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2425220677500. Starting simulation... +info: Entering event queue @ 2425333085500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2426220677500. Starting simulation... +info: Entering event queue @ 2426333085500. Starting simulation... switching cpus -info: Entering event queue @ 2427220549500. Starting simulation... +info: Entering event queue @ 2427332957500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2428220549500. Starting simulation... +info: Entering event queue @ 2428332957500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2429220549500. Starting simulation... +info: Entering event queue @ 2429332957500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2430220549500. Starting simulation... +info: Entering event queue @ 2430332957500. Starting simulation... switching cpus -info: Entering event queue @ 2431220421500. Starting simulation... +info: Entering event queue @ 2431332829500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2432220421500. Starting simulation... +info: Entering event queue @ 2432332829500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2433220421500. Starting simulation... +info: Entering event queue @ 2433332829500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2434220421500. Starting simulation... +info: Entering event queue @ 2434332829500. Starting simulation... switching cpus -info: Entering event queue @ 2435220293500. Starting simulation... +info: Entering event queue @ 2435332701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2436220293500. Starting simulation... +info: Entering event queue @ 2436332701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2437220293500. Starting simulation... +info: Entering event queue @ 2437332701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2438220293500. Starting simulation... +info: Entering event queue @ 2438332701500. Starting simulation... switching cpus -info: Entering event queue @ 2439220165500. Starting simulation... +info: Entering event queue @ 2439332573500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2440220165500. Starting simulation... +info: Entering event queue @ 2440332573500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2441220165500. Starting simulation... +info: Entering event queue @ 2441332573500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2442220165500. Starting simulation... +info: Entering event queue @ 2442332573500. Starting simulation... switching cpus -info: Entering event queue @ 2443220037500. Starting simulation... +info: Entering event queue @ 2443332445500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2444220037500. Starting simulation... +info: Entering event queue @ 2444332445500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2445220037500. Starting simulation... +info: Entering event queue @ 2445332445500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2446220037500. Starting simulation... +info: Entering event queue @ 2446332445500. Starting simulation... switching cpus -info: Entering event queue @ 2447219909500. Starting simulation... +info: Entering event queue @ 2447332317500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2448219909500. Starting simulation... +info: Entering event queue @ 2448332317500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2449219909500. Starting simulation... +info: Entering event queue @ 2449332317500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2450219909500. Starting simulation... +info: Entering event queue @ 2450332317500. Starting simulation... switching cpus -info: Entering event queue @ 2451219781500. Starting simulation... +info: Entering event queue @ 2451332189500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2452219781500. Starting simulation... +info: Entering event queue @ 2452332189500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2453219781500. Starting simulation... +info: Entering event queue @ 2453332189500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2454219781500. Starting simulation... +info: Entering event queue @ 2454332189500. Starting simulation... switching cpus -info: Entering event queue @ 2455219653500. Starting simulation... +info: Entering event queue @ 2455332061500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2456219653500. Starting simulation... +info: Entering event queue @ 2456332061500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2457219653500. Starting simulation... +info: Entering event queue @ 2457332061500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2458219653500. Starting simulation... +info: Entering event queue @ 2458332061500. Starting simulation... switching cpus -info: Entering event queue @ 2459219525500. Starting simulation... +info: Entering event queue @ 2459331933500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2460219525500. Starting simulation... +info: Entering event queue @ 2460331933500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2461219525500. Starting simulation... +info: Entering event queue @ 2461331933500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2462219525500. Starting simulation... +info: Entering event queue @ 2462331933500. Starting simulation... switching cpus -info: Entering event queue @ 2463219397500. Starting simulation... +info: Entering event queue @ 2463331805500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2464219397500. Starting simulation... +info: Entering event queue @ 2464331805500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2465219397500. Starting simulation... +info: Entering event queue @ 2465331805500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2466219397500. Starting simulation... +info: Entering event queue @ 2466331805500. Starting simulation... switching cpus -info: Entering event queue @ 2467219269500. Starting simulation... +info: Entering event queue @ 2467331677500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2468219269500. Starting simulation... +info: Entering event queue @ 2468331677500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2469219269500. Starting simulation... +info: Entering event queue @ 2469331677500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2470219269500. Starting simulation... +info: Entering event queue @ 2470331677500. Starting simulation... switching cpus -info: Entering event queue @ 2471219141500. Starting simulation... +info: Entering event queue @ 2471331549500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2472219141500. Starting simulation... +info: Entering event queue @ 2472331549500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2473219141500. Starting simulation... +info: Entering event queue @ 2473331549500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2474219141500. Starting simulation... +info: Entering event queue @ 2474331549500. Starting simulation... switching cpus -info: Entering event queue @ 2475219013500. Starting simulation... +info: Entering event queue @ 2475331421500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2476219013500. Starting simulation... +info: Entering event queue @ 2476331421500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2477219013500. Starting simulation... +info: Entering event queue @ 2477331421500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2478219013500. Starting simulation... +info: Entering event queue @ 2478331421500. Starting simulation... switching cpus -info: Entering event queue @ 2479218885500. Starting simulation... +info: Entering event queue @ 2479331293500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2480218885500. Starting simulation... +info: Entering event queue @ 2480331293500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2481218885500. Starting simulation... +info: Entering event queue @ 2481331293500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2482218885500. Starting simulation... +info: Entering event queue @ 2482331293500. Starting simulation... switching cpus -info: Entering event queue @ 2483218757500. Starting simulation... +info: Entering event queue @ 2483331165500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2484218757500. Starting simulation... +info: Entering event queue @ 2484331165500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2485218757500. Starting simulation... +info: Entering event queue @ 2485331165500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2486218757500. Starting simulation... +info: Entering event queue @ 2486331165500. Starting simulation... switching cpus -info: Entering event queue @ 2487218629500. Starting simulation... +info: Entering event queue @ 2487331037500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2488218629500. Starting simulation... +info: Entering event queue @ 2488331037500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2489218629500. Starting simulation... +info: Entering event queue @ 2489331037500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2490218629500. Starting simulation... +info: Entering event queue @ 2490331037500. Starting simulation... switching cpus -info: Entering event queue @ 2491218501500. Starting simulation... +info: Entering event queue @ 2491330909500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2492218501500. Starting simulation... +info: Entering event queue @ 2492330909500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2493218501500. Starting simulation... +info: Entering event queue @ 2493330909500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2494218501500. Starting simulation... +info: Entering event queue @ 2494330909500. Starting simulation... switching cpus -info: Entering event queue @ 2495218373500. Starting simulation... +info: Entering event queue @ 2495330781500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2496218373500. Starting simulation... +info: Entering event queue @ 2496330781500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2497218373500. Starting simulation... +info: Entering event queue @ 2497330781500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2498218373500. Starting simulation... +info: Entering event queue @ 2498330781500. Starting simulation... switching cpus -info: Entering event queue @ 2499218245500. Starting simulation... +info: Entering event queue @ 2499330653500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2500218245500. Starting simulation... +info: Entering event queue @ 2500330653500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2501218245500. Starting simulation... +info: Entering event queue @ 2501330653500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2502218245500. Starting simulation... +info: Entering event queue @ 2502330653500. Starting simulation... switching cpus -info: Entering event queue @ 2503218117500. Starting simulation... +info: Entering event queue @ 2503330525500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2504218117500. Starting simulation... +info: Entering event queue @ 2504330525500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2505218117500. Starting simulation... +info: Entering event queue @ 2505330525500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2506218117500. Starting simulation... +info: Entering event queue @ 2506330525500. Starting simulation... switching cpus -info: Entering event queue @ 2507217989500. Starting simulation... +info: Entering event queue @ 2507330397500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2508217989500. Starting simulation... +info: Entering event queue @ 2508330397500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2509217989500. Starting simulation... +info: Entering event queue @ 2509330397500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2510217989500. Starting simulation... +info: Entering event queue @ 2510330397500. Starting simulation... switching cpus -info: Entering event queue @ 2511217861500. Starting simulation... +info: Entering event queue @ 2511330269500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2512217861500. Starting simulation... +info: Entering event queue @ 2512330269500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2513217861500. Starting simulation... +info: Entering event queue @ 2513330269500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2514217861500. Starting simulation... +info: Entering event queue @ 2514330269500. Starting simulation... switching cpus -info: Entering event queue @ 2515217733500. Starting simulation... +info: Entering event queue @ 2515330141500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2516217733500. Starting simulation... +info: Entering event queue @ 2516330141500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2517217733500. Starting simulation... +info: Entering event queue @ 2517330141500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2518217733500. Starting simulation... +info: Entering event queue @ 2518330141500. Starting simulation... switching cpus -info: Entering event queue @ 2519217605500. Starting simulation... +info: Entering event queue @ 2519330013500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2520217605500. Starting simulation... +info: Entering event queue @ 2520330013500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2521217605500. Starting simulation... +info: Entering event queue @ 2521330013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2522217605500. Starting simulation... +info: Entering event queue @ 2522330013500. Starting simulation... switching cpus -info: Entering event queue @ 2523217477500. Starting simulation... +info: Entering event queue @ 2523329885500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2524217477500. Starting simulation... +info: Entering event queue @ 2524329885500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2525217477500. Starting simulation... +info: Entering event queue @ 2525329885500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2526217477500. Starting simulation... +info: Entering event queue @ 2526329885500. Starting simulation... switching cpus -info: Entering event queue @ 2527217349500. Starting simulation... +info: Entering event queue @ 2527329757500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2528217349500. Starting simulation... +info: Entering event queue @ 2528329757500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2529217349500. Starting simulation... +info: Entering event queue @ 2529329757500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2530217349500. Starting simulation... +info: Entering event queue @ 2530329757500. Starting simulation... switching cpus -info: Entering event queue @ 2531217221500. Starting simulation... +info: Entering event queue @ 2531329629500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2532217221500. Starting simulation... +info: Entering event queue @ 2532329629500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2533217221500. Starting simulation... +info: Entering event queue @ 2533329629500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2534217221500. Starting simulation... +info: Entering event queue @ 2534329629500. Starting simulation... switching cpus -info: Entering event queue @ 2535217093500. Starting simulation... +info: Entering event queue @ 2535329501500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2536217093500. Starting simulation... +info: Entering event queue @ 2536329501500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2537217093500. Starting simulation... +info: Entering event queue @ 2537329501500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2538217093500. Starting simulation... +info: Entering event queue @ 2538329501500. Starting simulation... switching cpus -info: Entering event queue @ 2539216965500. Starting simulation... +info: Entering event queue @ 2539329373500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2540216965500. Starting simulation... +info: Entering event queue @ 2540329373500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2541216965500. Starting simulation... +info: Entering event queue @ 2541329373500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2542216965500. Starting simulation... +info: Entering event queue @ 2542329373500. Starting simulation... switching cpus -info: Entering event queue @ 2543216837500. Starting simulation... +info: Entering event queue @ 2543329245500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2544216837500. Starting simulation... +info: Entering event queue @ 2544329245500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2545216837500. Starting simulation... +info: Entering event queue @ 2545329245500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2546216837500. Starting simulation... +info: Entering event queue @ 2546329245500. Starting simulation... switching cpus -info: Entering event queue @ 2547216709500. Starting simulation... +info: Entering event queue @ 2547329117500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2548216709500. Starting simulation... +info: Entering event queue @ 2548329117500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2549216709500. Starting simulation... +info: Entering event queue @ 2549329117500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2550216709500. Starting simulation... +info: Entering event queue @ 2550329117500. Starting simulation... switching cpus -info: Entering event queue @ 2551216581500. Starting simulation... +info: Entering event queue @ 2551328989500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2552216581500. Starting simulation... +info: Entering event queue @ 2552328989500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2553216581500. Starting simulation... +info: Entering event queue @ 2553328989500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2554216581500. Starting simulation... +info: Entering event queue @ 2554328989500. Starting simulation... switching cpus -info: Entering event queue @ 2555216453500. Starting simulation... +info: Entering event queue @ 2555328861500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2556216453500. Starting simulation... +info: Entering event queue @ 2556328861500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2557216453500. Starting simulation... +info: Entering event queue @ 2557328861500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2558216453500. Starting simulation... +info: Entering event queue @ 2558328861500. Starting simulation... switching cpus -info: Entering event queue @ 2559216325500. Starting simulation... +info: Entering event queue @ 2559328733500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2560216325500. Starting simulation... +info: Entering event queue @ 2560328733500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2561216325500. Starting simulation... +info: Entering event queue @ 2561328733500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2562216325500. Starting simulation... +info: Entering event queue @ 2562328733500. Starting simulation... switching cpus -info: Entering event queue @ 2563216197500. Starting simulation... +info: Entering event queue @ 2563328605500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2564216197500. Starting simulation... +info: Entering event queue @ 2564328605500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2565216197500. Starting simulation... +info: Entering event queue @ 2565328605500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2566216197500. Starting simulation... +info: Entering event queue @ 2566328605500. Starting simulation... switching cpus -info: Entering event queue @ 2567216069500. Starting simulation... +info: Entering event queue @ 2567328477500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2568216069500. Starting simulation... +info: Entering event queue @ 2568328477500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2569216069500. Starting simulation... +info: Entering event queue @ 2569328477500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2570216069500. Starting simulation... +info: Entering event queue @ 2570328477500. Starting simulation... switching cpus -info: Entering event queue @ 2571215941500. Starting simulation... +info: Entering event queue @ 2571328349500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2572215941500. Starting simulation... +info: Entering event queue @ 2572328349500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2573215941500. Starting simulation... +info: Entering event queue @ 2573328349500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2574215941500. Starting simulation... +info: Entering event queue @ 2574328349500. Starting simulation... switching cpus -info: Entering event queue @ 2575215813500. Starting simulation... +info: Entering event queue @ 2575328221500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2576215813500. Starting simulation... +info: Entering event queue @ 2576328221500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2577215813500. Starting simulation... +info: Entering event queue @ 2577328221500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2578215813500. Starting simulation... +info: Entering event queue @ 2578328221500. Starting simulation... switching cpus -info: Entering event queue @ 2579215685500. Starting simulation... +info: Entering event queue @ 2579328093500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2580215685500. Starting simulation... +info: Entering event queue @ 2580328093500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2581215685500. Starting simulation... +info: Entering event queue @ 2581328093500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2582215685500. Starting simulation... +info: Entering event queue @ 2582328093500. Starting simulation... switching cpus -info: Entering event queue @ 2583215557500. Starting simulation... +info: Entering event queue @ 2583327965500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2584215557500. Starting simulation... +info: Entering event queue @ 2584327965500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2585215557500. Starting simulation... +info: Entering event queue @ 2585327965500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2586215557500. Starting simulation... +info: Entering event queue @ 2586327965500. Starting simulation... switching cpus -info: Entering event queue @ 2587215429500. Starting simulation... +info: Entering event queue @ 2587327837500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2588215429500. Starting simulation... +info: Entering event queue @ 2588327837500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2589215429500. Starting simulation... +info: Entering event queue @ 2589327837500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2590215429500. Starting simulation... +info: Entering event queue @ 2590327837500. Starting simulation... switching cpus -info: Entering event queue @ 2591215301500. Starting simulation... +info: Entering event queue @ 2591327709500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2592215301500. Starting simulation... +info: Entering event queue @ 2592327709500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2593215301500. Starting simulation... +info: Entering event queue @ 2593327709500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2594215301500. Starting simulation... +info: Entering event queue @ 2594327709500. Starting simulation... switching cpus -info: Entering event queue @ 2595215173500. Starting simulation... +info: Entering event queue @ 2595327581500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2596215173500. Starting simulation... +info: Entering event queue @ 2596327581500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2597215173500. Starting simulation... +info: Entering event queue @ 2597327581500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2598215173500. Starting simulation... +info: Entering event queue @ 2598327581500. Starting simulation... switching cpus -info: Entering event queue @ 2599215045500. Starting simulation... +info: Entering event queue @ 2599327453500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2600215045500. Starting simulation... +info: Entering event queue @ 2600327453500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2601215045500. Starting simulation... +info: Entering event queue @ 2601327453500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2602215045500. Starting simulation... +info: Entering event queue @ 2602327453500. Starting simulation... switching cpus -info: Entering event queue @ 2603214917500. Starting simulation... +info: Entering event queue @ 2603327325500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2604214917500. Starting simulation... +info: Entering event queue @ 2604327325500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2605214917500. Starting simulation... +info: Entering event queue @ 2605327325500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2606214917500. Starting simulation... +info: Entering event queue @ 2606327325500. Starting simulation... switching cpus -info: Entering event queue @ 2607214789500. Starting simulation... +info: Entering event queue @ 2607327197500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 2608327197500. Starting simulation... switching cpus -info: Entering event queue @ 2608214789500. Starting simulation... +info: Entering event queue @ 2608327199000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2609214789500. Starting simulation... +info: Entering event queue @ 2609327199000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2610214789500. Starting simulation... +info: Entering event queue @ 2610327199000. Starting simulation... switching cpus -info: Entering event queue @ 2611214661500. Starting simulation... +info: Entering event queue @ 2611327069500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2612214661500. Starting simulation... +info: Entering event queue @ 2612327069500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2613214661500. Starting simulation... +info: Entering event queue @ 2613327069500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2614214661500. Starting simulation... +info: Entering event queue @ 2614327069500. Starting simulation... switching cpus -info: Entering event queue @ 2615214533500. Starting simulation... +info: Entering event queue @ 2615326941500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2616214533500. Starting simulation... +info: Entering event queue @ 2616326941500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2617214533500. Starting simulation... +info: Entering event queue @ 2617326941500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2618214533500. Starting simulation... +info: Entering event queue @ 2618326941500. Starting simulation... switching cpus -info: Entering event queue @ 2619214405500. Starting simulation... +info: Entering event queue @ 2619326813500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2620214405500. Starting simulation... +info: Entering event queue @ 2620326813500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2621214405500. Starting simulation... +info: Entering event queue @ 2621326813500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2622214405500. Starting simulation... +info: Entering event queue @ 2622326813500. Starting simulation... switching cpus -info: Entering event queue @ 2623214277500. Starting simulation... +info: Entering event queue @ 2623326685500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2624214277500. Starting simulation... +info: Entering event queue @ 2624326685500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2625214277500. Starting simulation... +info: Entering event queue @ 2625326685500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2626214277500. Starting simulation... +info: Entering event queue @ 2626326685500. Starting simulation... switching cpus -info: Entering event queue @ 2627214149500. Starting simulation... +info: Entering event queue @ 2627326557500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2628214149500. Starting simulation... +info: Entering event queue @ 2628326557500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2629214149500. Starting simulation... +info: Entering event queue @ 2629326557500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2630214149500. Starting simulation... +info: Entering event queue @ 2630326557500. Starting simulation... switching cpus -info: Entering event queue @ 2631214021500. Starting simulation... +info: Entering event queue @ 2631326429500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2632214021500. Starting simulation... +info: Entering event queue @ 2632326429500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2633214021500. Starting simulation... +info: Entering event queue @ 2633326429500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2634214021500. Starting simulation... +info: Entering event queue @ 2634326429500. Starting simulation... switching cpus -info: Entering event queue @ 2635213893500. Starting simulation... +info: Entering event queue @ 2635326301500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2636213893500. Starting simulation... +info: Entering event queue @ 2636326301500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2637213893500. Starting simulation... +info: Entering event queue @ 2637326301500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2638213893500. Starting simulation... +info: Entering event queue @ 2638326301500. Starting simulation... switching cpus -info: Entering event queue @ 2639213765500. Starting simulation... +info: Entering event queue @ 2639326173500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2640213765500. Starting simulation... +info: Entering event queue @ 2640326173500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2641213765500. Starting simulation... +info: Entering event queue @ 2641326173500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2642213765500. Starting simulation... +info: Entering event queue @ 2642326173500. Starting simulation... switching cpus -info: Entering event queue @ 2643213637500. Starting simulation... +info: Entering event queue @ 2643326045500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2644213637500. Starting simulation... +info: Entering event queue @ 2644326045500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2645213637500. Starting simulation... +info: Entering event queue @ 2645326045500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2646213637500. Starting simulation... +info: Entering event queue @ 2646326045500. Starting simulation... switching cpus -info: Entering event queue @ 2647213509500. Starting simulation... +info: Entering event queue @ 2647325917500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2648213509500. Starting simulation... +info: Entering event queue @ 2648325917500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2649213509500. Starting simulation... +info: Entering event queue @ 2649325917500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2650213509500. Starting simulation... +info: Entering event queue @ 2650325917500. Starting simulation... switching cpus -info: Entering event queue @ 2651213381500. Starting simulation... +info: Entering event queue @ 2651325789500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2652213381500. Starting simulation... +info: Entering event queue @ 2652325789500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2653213381500. Starting simulation... +info: Entering event queue @ 2653325789500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2654213381500. Starting simulation... +info: Entering event queue @ 2654325789500. Starting simulation... switching cpus -info: Entering event queue @ 2655213253500. Starting simulation... +info: Entering event queue @ 2655325661500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2656213253500. Starting simulation... +info: Entering event queue @ 2656325661500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2657213253500. Starting simulation... +info: Entering event queue @ 2657325661500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2658213253500. Starting simulation... +info: Entering event queue @ 2658325661500. Starting simulation... switching cpus -info: Entering event queue @ 2659213125500. Starting simulation... +info: Entering event queue @ 2659325533500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2660213125500. Starting simulation... +info: Entering event queue @ 2660325533500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2661213125500. Starting simulation... +info: Entering event queue @ 2661325533500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2662213125500. Starting simulation... +info: Entering event queue @ 2662325533500. Starting simulation... switching cpus -info: Entering event queue @ 2663212997500. Starting simulation... +info: Entering event queue @ 2663325405500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2664212997500. Starting simulation... +info: Entering event queue @ 2664325405500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2665212997500. Starting simulation... +info: Entering event queue @ 2665325405500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2666212997500. Starting simulation... +info: Entering event queue @ 2666325405500. Starting simulation... switching cpus -info: Entering event queue @ 2667212869500. Starting simulation... +info: Entering event queue @ 2667325277500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2668212869500. Starting simulation... +info: Entering event queue @ 2668325277500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2669212869500. Starting simulation... +info: Entering event queue @ 2669325277500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2670212869500. Starting simulation... +info: Entering event queue @ 2670325277500. Starting simulation... switching cpus -info: Entering event queue @ 2671212741500. Starting simulation... +info: Entering event queue @ 2671325149500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2672212741500. Starting simulation... +info: Entering event queue @ 2672325149500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2673212741500. Starting simulation... +info: Entering event queue @ 2673325149500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2674212741500. Starting simulation... +info: Entering event queue @ 2674325149500. Starting simulation... switching cpus -info: Entering event queue @ 2675212613500. Starting simulation... +info: Entering event queue @ 2675325021500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2676212613500. Starting simulation... +info: Entering event queue @ 2676325021500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2677212613500. Starting simulation... +info: Entering event queue @ 2677325021500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2678212613500. Starting simulation... +info: Entering event queue @ 2678325021500. Starting simulation... switching cpus -info: Entering event queue @ 2679212485500. Starting simulation... +info: Entering event queue @ 2679324893500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2680212485500. Starting simulation... +info: Entering event queue @ 2680324893500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2681212485500. Starting simulation... +info: Entering event queue @ 2681324893500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2682212485500. Starting simulation... +info: Entering event queue @ 2682324893500. Starting simulation... switching cpus -info: Entering event queue @ 2683212357500. Starting simulation... +info: Entering event queue @ 2683324765500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2684212357500. Starting simulation... +info: Entering event queue @ 2684324765500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2685212357500. Starting simulation... +info: Entering event queue @ 2685324765500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2686212357500. Starting simulation... +info: Entering event queue @ 2686324765500. Starting simulation... switching cpus -info: Entering event queue @ 2687212229500. Starting simulation... +info: Entering event queue @ 2687324637500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2688212229500. Starting simulation... +info: Entering event queue @ 2688324637500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2689212229500. Starting simulation... +info: Entering event queue @ 2689324637500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2690212229500. Starting simulation... +info: Entering event queue @ 2690324637500. Starting simulation... switching cpus -info: Entering event queue @ 2691212101500. Starting simulation... +info: Entering event queue @ 2691324509500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2692212101500. Starting simulation... +info: Entering event queue @ 2692324509500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2693212101500. Starting simulation... +info: Entering event queue @ 2693324509500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2694212101500. Starting simulation... +info: Entering event queue @ 2694324509500. Starting simulation... switching cpus -info: Entering event queue @ 2695211973500. Starting simulation... +info: Entering event queue @ 2695324381500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2696211973500. Starting simulation... +info: Entering event queue @ 2696324381500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2697211973500. Starting simulation... +info: Entering event queue @ 2697324381500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2698211973500. Starting simulation... +info: Entering event queue @ 2698324381500. Starting simulation... switching cpus -info: Entering event queue @ 2699211845500. Starting simulation... +info: Entering event queue @ 2699324253500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2700211845500. Starting simulation... +info: Entering event queue @ 2700324253500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2701211845500. Starting simulation... +info: Entering event queue @ 2701324253500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2702211845500. Starting simulation... +info: Entering event queue @ 2702324253500. Starting simulation... switching cpus -info: Entering event queue @ 2703211717500. Starting simulation... +info: Entering event queue @ 2703324125500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2704211717500. Starting simulation... +info: Entering event queue @ 2704324125500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2705211717500. Starting simulation... +info: Entering event queue @ 2705324125500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2706211717500. Starting simulation... +info: Entering event queue @ 2706324125500. Starting simulation... switching cpus -info: Entering event queue @ 2707211589500. Starting simulation... +info: Entering event queue @ 2707323997500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2708211589500. Starting simulation... +info: Entering event queue @ 2708323997500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2709211589500. Starting simulation... +info: Entering event queue @ 2709323997500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2710211589500. Starting simulation... +info: Entering event queue @ 2710323997500. Starting simulation... switching cpus -info: Entering event queue @ 2711211461500. Starting simulation... +info: Entering event queue @ 2711323869500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2712211461500. Starting simulation... +info: Entering event queue @ 2712323869500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2713211461500. Starting simulation... +info: Entering event queue @ 2713323869500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2714211461500. Starting simulation... +info: Entering event queue @ 2714323869500. Starting simulation... switching cpus -info: Entering event queue @ 2715211333500. Starting simulation... +info: Entering event queue @ 2715323741500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2716211333500. Starting simulation... +info: Entering event queue @ 2716323741500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2717211333500. Starting simulation... +info: Entering event queue @ 2717323741500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2718211333500. Starting simulation... +info: Entering event queue @ 2718323741500. Starting simulation... switching cpus -info: Entering event queue @ 2719211205500. Starting simulation... +info: Entering event queue @ 2719323613500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2720211205500. Starting simulation... +info: Entering event queue @ 2720323613500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2721211205500. Starting simulation... +info: Entering event queue @ 2721323613500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2722211205500. Starting simulation... +info: Entering event queue @ 2722323613500. Starting simulation... switching cpus -info: Entering event queue @ 2723211077500. Starting simulation... +info: Entering event queue @ 2723323485500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2724211077500. Starting simulation... +info: Entering event queue @ 2724323485500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2725211077500. Starting simulation... +info: Entering event queue @ 2725323485500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2726211077500. Starting simulation... +info: Entering event queue @ 2726323485500. Starting simulation... switching cpus -info: Entering event queue @ 2727210949500. Starting simulation... +info: Entering event queue @ 2727323357500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2728210949500. Starting simulation... +info: Entering event queue @ 2728323357500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2729210949500. Starting simulation... +info: Entering event queue @ 2729323357500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2730210949500. Starting simulation... +info: Entering event queue @ 2730323357500. Starting simulation... switching cpus -info: Entering event queue @ 2731210821500. Starting simulation... +info: Entering event queue @ 2731323229500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2732210821500. Starting simulation... +info: Entering event queue @ 2732323229500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2733210821500. Starting simulation... +info: Entering event queue @ 2733323229500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2734210821500. Starting simulation... +info: Entering event queue @ 2734323229500. Starting simulation... switching cpus -info: Entering event queue @ 2735210693500. Starting simulation... +info: Entering event queue @ 2735323101500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2736210693500. Starting simulation... +info: Entering event queue @ 2736323101500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2737210693500. Starting simulation... +info: Entering event queue @ 2737323101500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2738210693500. Starting simulation... +info: Entering event queue @ 2738323101500. Starting simulation... switching cpus -info: Entering event queue @ 2739210565500. Starting simulation... +info: Entering event queue @ 2739322973500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2740210565500. Starting simulation... +info: Entering event queue @ 2740322973500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2741210565500. Starting simulation... +info: Entering event queue @ 2741322973500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2742210565500. Starting simulation... +info: Entering event queue @ 2742322973500. Starting simulation... switching cpus -info: Entering event queue @ 2743210437500. Starting simulation... +info: Entering event queue @ 2743322845500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2744210437500. Starting simulation... +info: Entering event queue @ 2744322845500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2745210437500. Starting simulation... +info: Entering event queue @ 2745322845500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2746210437500. Starting simulation... +info: Entering event queue @ 2746322845500. Starting simulation... switching cpus -info: Entering event queue @ 2747210309500. Starting simulation... +info: Entering event queue @ 2747322717500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2748210309500. Starting simulation... +info: Entering event queue @ 2748322717500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2749210309500. Starting simulation... +info: Entering event queue @ 2749322717500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2750210309500. Starting simulation... +info: Entering event queue @ 2750322717500. Starting simulation... switching cpus -info: Entering event queue @ 2751210181500. Starting simulation... +info: Entering event queue @ 2751322589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2752210181500. Starting simulation... +info: Entering event queue @ 2752322589500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2753210181500. Starting simulation... +info: Entering event queue @ 2753322589500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2754210181500. Starting simulation... +info: Entering event queue @ 2754322589500. Starting simulation... switching cpus -info: Entering event queue @ 2755210053500. Starting simulation... +info: Entering event queue @ 2755322461500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2756210053500. Starting simulation... +info: Entering event queue @ 2756322461500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2757210053500. Starting simulation... +info: Entering event queue @ 2757322461500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2758210053500. Starting simulation... +info: Entering event queue @ 2758322461500. Starting simulation... switching cpus -info: Entering event queue @ 2759209925500. Starting simulation... +info: Entering event queue @ 2759322333500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2760209925500. Starting simulation... +info: Entering event queue @ 2760322333500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2761209925500. Starting simulation... +info: Entering event queue @ 2761322333500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2762209925500. Starting simulation... +info: Entering event queue @ 2762322333500. Starting simulation... switching cpus -info: Entering event queue @ 2763209797500. Starting simulation... +info: Entering event queue @ 2763322205500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2764209797500. Starting simulation... +info: Entering event queue @ 2764322205500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2765209797500. Starting simulation... +info: Entering event queue @ 2765322205500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2766209797500. Starting simulation... +info: Entering event queue @ 2766322205500. Starting simulation... switching cpus -info: Entering event queue @ 2767209669500. Starting simulation... +info: Entering event queue @ 2767322077500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2768209669500. Starting simulation... +info: Entering event queue @ 2768322077500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2769209669500. Starting simulation... +info: Entering event queue @ 2769322077500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2770209669500. Starting simulation... +info: Entering event queue @ 2770322077500. Starting simulation... switching cpus -info: Entering event queue @ 2771209541500. Starting simulation... +info: Entering event queue @ 2771321949500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2772209541500. Starting simulation... +info: Entering event queue @ 2772321949500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2773209541500. Starting simulation... +info: Entering event queue @ 2773321949500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2774209541500. Starting simulation... +info: Entering event queue @ 2774321949500. Starting simulation... switching cpus -info: Entering event queue @ 2775209413500. Starting simulation... +info: Entering event queue @ 2775321821500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2776209413500. Starting simulation... +info: Entering event queue @ 2776321821500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2777209413500. Starting simulation... +info: Entering event queue @ 2777321821500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2778209413500. Starting simulation... +info: Entering event queue @ 2778321821500. Starting simulation... switching cpus -info: Entering event queue @ 2779209285500. Starting simulation... +info: Entering event queue @ 2779321693500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2780209285500. Starting simulation... +info: Entering event queue @ 2780321693500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2781209285500. Starting simulation... +info: Entering event queue @ 2781321693500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2782209285500. Starting simulation... +info: Entering event queue @ 2782321693500. Starting simulation... switching cpus -info: Entering event queue @ 2783209157500. Starting simulation... +info: Entering event queue @ 2783321565500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2784209157500. Starting simulation... +info: Entering event queue @ 2784321565500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2785209157500. Starting simulation... +info: Entering event queue @ 2785321565500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2786209157500. Starting simulation... +info: Entering event queue @ 2786321565500. Starting simulation... switching cpus -info: Entering event queue @ 2787209029500. Starting simulation... +info: Entering event queue @ 2787321437500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2788209029500. Starting simulation... +info: Entering event queue @ 2788321437500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2789209029500. Starting simulation... +info: Entering event queue @ 2789321437500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2790209029500. Starting simulation... +info: Entering event queue @ 2790321437500. Starting simulation... switching cpus -info: Entering event queue @ 2791208901500. Starting simulation... +info: Entering event queue @ 2791321309500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2792208901500. Starting simulation... +info: Entering event queue @ 2792321309500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2793208901500. Starting simulation... +info: Entering event queue @ 2793321309500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2794208901500. Starting simulation... +info: Entering event queue @ 2794321309500. Starting simulation... switching cpus -info: Entering event queue @ 2795208773500. Starting simulation... +info: Entering event queue @ 2795321181500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2796208773500. Starting simulation... +info: Entering event queue @ 2796321181500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2797208773500. Starting simulation... +info: Entering event queue @ 2797321181500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2798208773500. Starting simulation... +info: Entering event queue @ 2798321181500. Starting simulation... switching cpus -info: Entering event queue @ 2799208645500. Starting simulation... +info: Entering event queue @ 2799321053500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2800208645500. Starting simulation... +info: Entering event queue @ 2800321053500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2801208645500. Starting simulation... +info: Entering event queue @ 2801321053500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2802208645500. Starting simulation... +info: Entering event queue @ 2802321053500. Starting simulation... switching cpus -info: Entering event queue @ 2803208517500. Starting simulation... +info: Entering event queue @ 2803320925500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2804208517500. Starting simulation... +info: Entering event queue @ 2804320925500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2805208517500. Starting simulation... +info: Entering event queue @ 2805320925500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2806208517500. Starting simulation... +info: Entering event queue @ 2806320925500. Starting simulation... switching cpus -info: Entering event queue @ 2807208389500. Starting simulation... +info: Entering event queue @ 2807320797500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2808208389500. Starting simulation... +info: Entering event queue @ 2808320797500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2809208389500. Starting simulation... +info: Entering event queue @ 2809320797500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2810208389500. Starting simulation... +info: Entering event queue @ 2810320797500. Starting simulation... switching cpus -info: Entering event queue @ 2811208261500. Starting simulation... +info: Entering event queue @ 2811320669500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2812208261500. Starting simulation... +info: Entering event queue @ 2812320669500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2813208261500. Starting simulation... +info: Entering event queue @ 2813320669500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2814208261500. Starting simulation... +info: Entering event queue @ 2814320669500. Starting simulation... switching cpus -info: Entering event queue @ 2815208133500. Starting simulation... +info: Entering event queue @ 2815320541500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2816208133500. Starting simulation... +info: Entering event queue @ 2816320541500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2817208133500. Starting simulation... +info: Entering event queue @ 2817320541500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2818208133500. Starting simulation... +info: Entering event queue @ 2818320541500. Starting simulation... switching cpus -info: Entering event queue @ 2819208005500. Starting simulation... +info: Entering event queue @ 2819320413500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2820208005500. Starting simulation... +info: Entering event queue @ 2820320413500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2821208005500. Starting simulation... +info: Entering event queue @ 2821320413500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2822208005500. Starting simulation... +info: Entering event queue @ 2822320413500. Starting simulation... switching cpus -info: Entering event queue @ 2823207877500. Starting simulation... +info: Entering event queue @ 2823320285500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2824207877500. Starting simulation... +info: Entering event queue @ 2824320285500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2825207877500. Starting simulation... +info: Entering event queue @ 2825320285500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2826207877500. Starting simulation... +info: Entering event queue @ 2826320285500. Starting simulation... switching cpus -info: Entering event queue @ 2827207749500. Starting simulation... +info: Entering event queue @ 2827320157500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2828207749500. Starting simulation... +info: Entering event queue @ 2828320157500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2829207749500. Starting simulation... +info: Entering event queue @ 2829320157500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2830207749500. Starting simulation... +info: Entering event queue @ 2830320157500. Starting simulation... switching cpus -info: Entering event queue @ 2831207621500. Starting simulation... +info: Entering event queue @ 2831320029500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2832207621500. Starting simulation... +info: Entering event queue @ 2832320029500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2833207621500. Starting simulation... +info: Entering event queue @ 2833320029500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2834207621500. Starting simulation... +info: Entering event queue @ 2834320029500. Starting simulation... switching cpus -info: Entering event queue @ 2835207493500. Starting simulation... +info: Entering event queue @ 2835319901500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2836207493500. Starting simulation... +info: Entering event queue @ 2836319901500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2837207493500. Starting simulation... +info: Entering event queue @ 2837319901500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2838207493500. Starting simulation... +info: Entering event queue @ 2838319901500. Starting simulation... switching cpus -info: Entering event queue @ 2839207365500. Starting simulation... +info: Entering event queue @ 2839319773500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2840207365500. Starting simulation... +info: Entering event queue @ 2840319773500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2841207365500. Starting simulation... +info: Entering event queue @ 2841319773500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2842207365500. Starting simulation... +info: Entering event queue @ 2842319773500. Starting simulation... switching cpus -info: Entering event queue @ 2843207237500. Starting simulation... +info: Entering event queue @ 2843319645500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2844207237500. Starting simulation... +info: Entering event queue @ 2844319645500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2845207237500. Starting simulation... +info: Entering event queue @ 2845319645500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2846207237500. Starting simulation... +info: Entering event queue @ 2846319645500. Starting simulation... switching cpus -info: Entering event queue @ 2847207109500. Starting simulation... +info: Entering event queue @ 2847319517500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2848207109500. Starting simulation... +info: Entering event queue @ 2848319517500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2849207109500. Starting simulation... +info: Entering event queue @ 2849319517500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2850207109500. Starting simulation... +info: Entering event queue @ 2850319517500. Starting simulation... switching cpus -info: Entering event queue @ 2851206981500. Starting simulation... +info: Entering event queue @ 2851319389500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2852206981500. Starting simulation... +info: Entering event queue @ 2852319389500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2853206981500. Starting simulation... +info: Entering event queue @ 2853319389500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2854206981500. Starting simulation... +info: Entering event queue @ 2854319389500. Starting simulation... switching cpus -info: Entering event queue @ 2855206853500. Starting simulation... +info: Entering event queue @ 2855319261500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2856206853500. Starting simulation... +info: Entering event queue @ 2856319261500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2857206853500. Starting simulation... +info: Entering event queue @ 2857319261500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2858206853500. Starting simulation... +info: Entering event queue @ 2858319261500. Starting simulation... switching cpus -info: Entering event queue @ 2859206725500. Starting simulation... +info: Entering event queue @ 2859319133500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2860206725500. Starting simulation... +info: Entering event queue @ 2860319133500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2861206725500. Starting simulation... +info: Entering event queue @ 2861319133500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2862206725500. Starting simulation... +info: Entering event queue @ 2862319133500. Starting simulation... switching cpus -info: Entering event queue @ 2863206597500. Starting simulation... +info: Entering event queue @ 2863319005500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2864206597500. Starting simulation... +info: Entering event queue @ 2864319005500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2865206597500. Starting simulation... +info: Entering event queue @ 2865319005500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2866206597500. Starting simulation... +info: Entering event queue @ 2866319005500. Starting simulation... switching cpus -info: Entering event queue @ 2867206469500. Starting simulation... +info: Entering event queue @ 2867318877500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2868206469500. Starting simulation... +info: Entering event queue @ 2868318877500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2869206469500. Starting simulation... +info: Entering event queue @ 2869318877500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2870206469500. Starting simulation... +info: Entering event queue @ 2870318877500. Starting simulation... switching cpus -info: Entering event queue @ 2871206341500. Starting simulation... +info: Entering event queue @ 2871318749500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2872206341500. Starting simulation... +info: Entering event queue @ 2872318749500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2873206341500. Starting simulation... +info: Entering event queue @ 2873318749500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2874206341500. Starting simulation... +info: Entering event queue @ 2874318749500. Starting simulation... switching cpus -info: Entering event queue @ 2875206213500. Starting simulation... +info: Entering event queue @ 2875318621500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2876206213500. Starting simulation... +info: Entering event queue @ 2876318621500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2877206213500. Starting simulation... +info: Entering event queue @ 2877318621500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2878206213500. Starting simulation... +info: Entering event queue @ 2878318621500. Starting simulation... switching cpus -info: Entering event queue @ 2879206085500. Starting simulation... +info: Entering event queue @ 2879318493500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2880206085500. Starting simulation... +info: Entering event queue @ 2880318493500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2881206085500. Starting simulation... +info: Entering event queue @ 2881318493500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2882206085500. Starting simulation... +info: Entering event queue @ 2882318493500. Starting simulation... switching cpus -info: Entering event queue @ 2883205957500. Starting simulation... +info: Entering event queue @ 2883318365500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2884205957500. Starting simulation... +info: Entering event queue @ 2884318365500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2885205957500. Starting simulation... +info: Entering event queue @ 2885318365500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2886205957500. Starting simulation... +info: Entering event queue @ 2886318365500. Starting simulation... switching cpus -info: Entering event queue @ 2887205829500. Starting simulation... +info: Entering event queue @ 2887318237500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2888205829500. Starting simulation... +info: Entering event queue @ 2888318237500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2889205829500. Starting simulation... +info: Entering event queue @ 2889318237500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2890205829500. Starting simulation... +info: Entering event queue @ 2890318237500. Starting simulation... switching cpus -info: Entering event queue @ 2891205701500. Starting simulation... +info: Entering event queue @ 2891318109500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2892205701500. Starting simulation... +info: Entering event queue @ 2892318109500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2893205701500. Starting simulation... +info: Entering event queue @ 2893318109500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2894205701500. Starting simulation... +info: Entering event queue @ 2894318109500. Starting simulation... switching cpus -info: Entering event queue @ 2895205573500. Starting simulation... +info: Entering event queue @ 2895317981500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2896205573500. Starting simulation... +info: Entering event queue @ 2896317981500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2897205573500. Starting simulation... +info: Entering event queue @ 2897317981500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2898205573500. Starting simulation... +info: Entering event queue @ 2898317981500. Starting simulation... switching cpus -info: Entering event queue @ 2899205445500. Starting simulation... +info: Entering event queue @ 2899317853500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2900205445500. Starting simulation... +info: Entering event queue @ 2900317853500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2901205445500. Starting simulation... +info: Entering event queue @ 2901317853500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2902205445500. Starting simulation... +info: Entering event queue @ 2902317853500. Starting simulation... switching cpus -info: Entering event queue @ 2903205317500. Starting simulation... +info: Entering event queue @ 2903317725500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2904205317500. Starting simulation... +info: Entering event queue @ 2904317725500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2905205317500. Starting simulation... +info: Entering event queue @ 2905317725500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2906205317500. Starting simulation... +info: Entering event queue @ 2906317725500. Starting simulation... switching cpus -info: Entering event queue @ 2907205189500. Starting simulation... +info: Entering event queue @ 2907317597500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2908205189500. Starting simulation... +info: Entering event queue @ 2908317597500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2909205189500. Starting simulation... +info: Entering event queue @ 2909317597500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2910205189500. Starting simulation... +info: Entering event queue @ 2910317597500. Starting simulation... switching cpus -info: Entering event queue @ 2911205061500. Starting simulation... +info: Entering event queue @ 2911317469500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2912205061500. Starting simulation... +info: Entering event queue @ 2912317469500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2913205061500. Starting simulation... +info: Entering event queue @ 2913317469500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2914205061500. Starting simulation... +info: Entering event queue @ 2914317469500. Starting simulation... switching cpus -info: Entering event queue @ 2915204933500. Starting simulation... +info: Entering event queue @ 2915317341500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2916204933500. Starting simulation... +info: Entering event queue @ 2916317341500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2917204933500. Starting simulation... +info: Entering event queue @ 2917317341500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2918204933500. Starting simulation... +info: Entering event queue @ 2918317341500. Starting simulation... switching cpus -info: Entering event queue @ 2919204805500. Starting simulation... +info: Entering event queue @ 2919317213500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2920204805500. Starting simulation... +info: Entering event queue @ 2920317213500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2921204805500. Starting simulation... +info: Entering event queue @ 2921317213500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2922204805500. Starting simulation... +info: Entering event queue @ 2922317213500. Starting simulation... switching cpus -info: Entering event queue @ 2923204677500. Starting simulation... +info: Entering event queue @ 2923317085500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2924204677500. Starting simulation... +info: Entering event queue @ 2924317085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2925204677500. Starting simulation... +info: Entering event queue @ 2925317085500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2926204677500. Starting simulation... +info: Entering event queue @ 2926317085500. Starting simulation... switching cpus -info: Entering event queue @ 2927204549500. Starting simulation... +info: Entering event queue @ 2927316957500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2928204549500. Starting simulation... +info: Entering event queue @ 2928316957500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2929204549500. Starting simulation... +info: Entering event queue @ 2929316957500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2930204549500. Starting simulation... +info: Entering event queue @ 2930316957500. Starting simulation... switching cpus -info: Entering event queue @ 2931204421500. Starting simulation... +info: Entering event queue @ 2931316829500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2932204421500. Starting simulation... +info: Entering event queue @ 2932316829500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2933204421500. Starting simulation... +info: Entering event queue @ 2933316829500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2934204421500. Starting simulation... +info: Entering event queue @ 2934316829500. Starting simulation... switching cpus -info: Entering event queue @ 2935204293500. Starting simulation... +info: Entering event queue @ 2935316701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2936204293500. Starting simulation... +info: Entering event queue @ 2936316701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2937204293500. Starting simulation... +info: Entering event queue @ 2937316701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2938204293500. Starting simulation... +info: Entering event queue @ 2938316701500. Starting simulation... switching cpus -info: Entering event queue @ 2939204165500. Starting simulation... +info: Entering event queue @ 2939316573500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2940204165500. Starting simulation... +info: Entering event queue @ 2940316573500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2941204165500. Starting simulation... +info: Entering event queue @ 2941316573500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2942204165500. Starting simulation... +info: Entering event queue @ 2942316573500. Starting simulation... switching cpus -info: Entering event queue @ 2943204037500. Starting simulation... +info: Entering event queue @ 2943316445500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2944204037500. Starting simulation... +info: Entering event queue @ 2944316445500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2945204037500. Starting simulation... +info: Entering event queue @ 2945316445500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2946204037500. Starting simulation... +info: Entering event queue @ 2946316445500. Starting simulation... switching cpus -info: Entering event queue @ 2947203909500. Starting simulation... +info: Entering event queue @ 2947316317500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2948203909500. Starting simulation... +info: Entering event queue @ 2948316317500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2949203909500. Starting simulation... +info: Entering event queue @ 2949316317500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2950203909500. Starting simulation... +info: Entering event queue @ 2950316317500. Starting simulation... switching cpus -info: Entering event queue @ 2951203781500. Starting simulation... +info: Entering event queue @ 2951316189500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2952203781500. Starting simulation... +info: Entering event queue @ 2952316189500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2953203781500. Starting simulation... +info: Entering event queue @ 2953316189500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2954203781500. Starting simulation... +info: Entering event queue @ 2954316189500. Starting simulation... switching cpus -info: Entering event queue @ 2955203653500. Starting simulation... +info: Entering event queue @ 2955316061500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2956203653500. Starting simulation... +info: Entering event queue @ 2956316061500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2957203653500. Starting simulation... +info: Entering event queue @ 2957316061500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2958203653500. Starting simulation... +info: Entering event queue @ 2958316061500. Starting simulation... switching cpus -info: Entering event queue @ 2959203525500. Starting simulation... +info: Entering event queue @ 2959315933500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2960203525500. Starting simulation... +info: Entering event queue @ 2960315933500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2961203525500. Starting simulation... +info: Entering event queue @ 2961315933500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2962203525500. Starting simulation... +info: Entering event queue @ 2962315933500. Starting simulation... switching cpus -info: Entering event queue @ 2963203397500. Starting simulation... +info: Entering event queue @ 2963315805500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2964203397500. Starting simulation... +info: Entering event queue @ 2964315805500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2965203397500. Starting simulation... +info: Entering event queue @ 2965315805500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2966203397500. Starting simulation... +info: Entering event queue @ 2966315805500. Starting simulation... switching cpus -info: Entering event queue @ 2967203269500. Starting simulation... +info: Entering event queue @ 2967315677500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2968203269500. Starting simulation... +info: Entering event queue @ 2968315677500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2969203269500. Starting simulation... +info: Entering event queue @ 2969315677500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2970203269500. Starting simulation... +info: Entering event queue @ 2970315677500. Starting simulation... switching cpus -info: Entering event queue @ 2971203141500. Starting simulation... +info: Entering event queue @ 2971315549500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2972203141500. Starting simulation... +info: Entering event queue @ 2972315549500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2973203141500. Starting simulation... +info: Entering event queue @ 2973315549500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2974203141500. Starting simulation... +info: Entering event queue @ 2974315549500. Starting simulation... switching cpus -info: Entering event queue @ 2975203013500. Starting simulation... +info: Entering event queue @ 2975315421500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2976203013500. Starting simulation... +info: Entering event queue @ 2976315421500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2977203013500. Starting simulation... +info: Entering event queue @ 2977315421500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2978203013500. Starting simulation... +info: Entering event queue @ 2978315421500. Starting simulation... switching cpus -info: Entering event queue @ 2979202885500. Starting simulation... +info: Entering event queue @ 2979315293500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2980202885500. Starting simulation... +info: Entering event queue @ 2980315293500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2981202885500. Starting simulation... +info: Entering event queue @ 2981315293500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2982202885500. Starting simulation... +info: Entering event queue @ 2982315293500. Starting simulation... switching cpus -info: Entering event queue @ 2983202757500. Starting simulation... +info: Entering event queue @ 2983315165500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2984202757500. Starting simulation... +info: Entering event queue @ 2984315165500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2985202757500. Starting simulation... +info: Entering event queue @ 2985315165500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2986202757500. Starting simulation... +info: Entering event queue @ 2986315165500. Starting simulation... switching cpus -info: Entering event queue @ 2987202629500. Starting simulation... +info: Entering event queue @ 2987315037500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2988202629500. Starting simulation... +info: Entering event queue @ 2988315037500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2989202629500. Starting simulation... +info: Entering event queue @ 2989315037500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2990202629500. Starting simulation... +info: Entering event queue @ 2990315037500. Starting simulation... switching cpus -info: Entering event queue @ 2991202501500. Starting simulation... +info: Entering event queue @ 2991314909500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2992202501500. Starting simulation... +info: Entering event queue @ 2992314909500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2993202501500. Starting simulation... +info: Entering event queue @ 2993314909500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2994202501500. Starting simulation... +info: Entering event queue @ 2994314909500. Starting simulation... switching cpus -info: Entering event queue @ 2995202373500. Starting simulation... +info: Entering event queue @ 2995314781500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2996202373500. Starting simulation... +info: Entering event queue @ 2996314781500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2997202373500. Starting simulation... +info: Entering event queue @ 2997314781500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2998202373500. Starting simulation... +info: Entering event queue @ 2998314781500. Starting simulation... switching cpus -info: Entering event queue @ 2999202245500. Starting simulation... +info: Entering event queue @ 2999314653500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3000202245500. Starting simulation... +info: Entering event queue @ 3000314653500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3001202245500. Starting simulation... +info: Entering event queue @ 3001314653500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3002202245500. Starting simulation... +info: Entering event queue @ 3002314653500. Starting simulation... switching cpus -info: Entering event queue @ 3003202117500. Starting simulation... +info: Entering event queue @ 3003314525500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3004202117500. Starting simulation... +info: Entering event queue @ 3004314525500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3005202117500. Starting simulation... +info: Entering event queue @ 3005314525500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3006202117500. Starting simulation... +info: Entering event queue @ 3006314525500. Starting simulation... switching cpus -info: Entering event queue @ 3007201989500. Starting simulation... +info: Entering event queue @ 3007314397500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3008201989500. Starting simulation... +info: Entering event queue @ 3008314397500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3009201989500. Starting simulation... +info: Entering event queue @ 3009314397500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3010201989500. Starting simulation... +info: Entering event queue @ 3010314397500. Starting simulation... switching cpus -info: Entering event queue @ 3011201861500. Starting simulation... +info: Entering event queue @ 3011314269500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3012201861500. Starting simulation... +info: Entering event queue @ 3012314269500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3013201861500. Starting simulation... +info: Entering event queue @ 3013314269500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3014201861500. Starting simulation... +info: Entering event queue @ 3014314269500. Starting simulation... switching cpus -info: Entering event queue @ 3015201733500. Starting simulation... +info: Entering event queue @ 3015314141500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3016201733500. Starting simulation... +info: Entering event queue @ 3016314141500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3017201733500. Starting simulation... +info: Entering event queue @ 3017314141500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3018201733500. Starting simulation... +info: Entering event queue @ 3018314141500. Starting simulation... switching cpus -info: Entering event queue @ 3019201605500. Starting simulation... +info: Entering event queue @ 3019314013500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3020201605500. Starting simulation... +info: Entering event queue @ 3020314013500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3021201605500. Starting simulation... +info: Entering event queue @ 3021314013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3022201605500. Starting simulation... +info: Entering event queue @ 3022314013500. Starting simulation... switching cpus -info: Entering event queue @ 3023201477500. Starting simulation... +info: Entering event queue @ 3023313885500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3024201477500. Starting simulation... +info: Entering event queue @ 3024313885500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3025201477500. Starting simulation... +info: Entering event queue @ 3025313885500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3026201477500. Starting simulation... +info: Entering event queue @ 3026313885500. Starting simulation... switching cpus -info: Entering event queue @ 3027201349500. Starting simulation... +info: Entering event queue @ 3027313757500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3028201349500. Starting simulation... +info: Entering event queue @ 3028313757500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3029201349500. Starting simulation... +info: Entering event queue @ 3029313757500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3030201349500. Starting simulation... +info: Entering event queue @ 3030313757500. Starting simulation... switching cpus -info: Entering event queue @ 3031201221500. Starting simulation... +info: Entering event queue @ 3031313629500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3032201221500. Starting simulation... +info: Entering event queue @ 3032313629500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3033201221500. Starting simulation... +info: Entering event queue @ 3033313629500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3034201221500. Starting simulation... +info: Entering event queue @ 3034313629500. Starting simulation... switching cpus -info: Entering event queue @ 3035201093500. Starting simulation... +info: Entering event queue @ 3035313501500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3036201093500. Starting simulation... +info: Entering event queue @ 3036313501500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3037201093500. Starting simulation... +info: Entering event queue @ 3037313501500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3038201093500. Starting simulation... +info: Entering event queue @ 3038313501500. Starting simulation... switching cpus -info: Entering event queue @ 3039200965500. Starting simulation... +info: Entering event queue @ 3039313373500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3040200965500. Starting simulation... +info: Entering event queue @ 3040313373500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3041200965500. Starting simulation... +info: Entering event queue @ 3041313373500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3042200965500. Starting simulation... +info: Entering event queue @ 3042313373500. Starting simulation... switching cpus -info: Entering event queue @ 3043200837500. Starting simulation... +info: Entering event queue @ 3043313245500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3044200837500. Starting simulation... +info: Entering event queue @ 3044313245500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3045200837500. Starting simulation... +info: Entering event queue @ 3045313245500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3046200837500. Starting simulation... +info: Entering event queue @ 3046313245500. Starting simulation... switching cpus -info: Entering event queue @ 3047200709500. Starting simulation... +info: Entering event queue @ 3047313117500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3048200709500. Starting simulation... +info: Entering event queue @ 3048313117500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3049200709500. Starting simulation... +info: Entering event queue @ 3049313117500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3050200709500. Starting simulation... +info: Entering event queue @ 3050313117500. Starting simulation... switching cpus -info: Entering event queue @ 3051200581500. Starting simulation... +info: Entering event queue @ 3051312989500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3052200581500. Starting simulation... +info: Entering event queue @ 3052312989500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3053200581500. Starting simulation... +info: Entering event queue @ 3053312989500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3054200581500. Starting simulation... +info: Entering event queue @ 3054312989500. Starting simulation... switching cpus -info: Entering event queue @ 3055200453500. Starting simulation... +info: Entering event queue @ 3055312861500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3056200453500. Starting simulation... +info: Entering event queue @ 3056312861500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3057200453500. Starting simulation... +info: Entering event queue @ 3057312861500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3058200453500. Starting simulation... +info: Entering event queue @ 3058312861500. Starting simulation... switching cpus -info: Entering event queue @ 3059200325500. Starting simulation... +info: Entering event queue @ 3059312733500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3060200325500. Starting simulation... +info: Entering event queue @ 3060312733500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3061200325500. Starting simulation... +info: Entering event queue @ 3061312733500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3062200325500. Starting simulation... +info: Entering event queue @ 3062312733500. Starting simulation... switching cpus -info: Entering event queue @ 3063200197500. Starting simulation... +info: Entering event queue @ 3063312605500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3064200197500. Starting simulation... +info: Entering event queue @ 3064312605500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3065200197500. Starting simulation... +info: Entering event queue @ 3065312605500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3066200197500. Starting simulation... +info: Entering event queue @ 3066312605500. Starting simulation... switching cpus -info: Entering event queue @ 3067200069500. Starting simulation... +info: Entering event queue @ 3067312477500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3068200069500. Starting simulation... +info: Entering event queue @ 3068312477500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3069200069500. Starting simulation... +info: Entering event queue @ 3069312477500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3070200069500. Starting simulation... +info: Entering event queue @ 3070312477500. Starting simulation... switching cpus -info: Entering event queue @ 3071199941500. Starting simulation... +info: Entering event queue @ 3071312349500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3072199941500. Starting simulation... +info: Entering event queue @ 3072312349500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3073199941500. Starting simulation... +info: Entering event queue @ 3073312349500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3074199941500. Starting simulation... +info: Entering event queue @ 3074312349500. Starting simulation... switching cpus -info: Entering event queue @ 3075199813500. Starting simulation... +info: Entering event queue @ 3075312221500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3076199813500. Starting simulation... +info: Entering event queue @ 3076312221500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3077199813500. Starting simulation... +info: Entering event queue @ 3077312221500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3078199813500. Starting simulation... +info: Entering event queue @ 3078312221500. Starting simulation... switching cpus -info: Entering event queue @ 3079199685500. Starting simulation... +info: Entering event queue @ 3079312093500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3080199685500. Starting simulation... +info: Entering event queue @ 3080312093500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3081199685500. Starting simulation... +info: Entering event queue @ 3081312093500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3082199685500. Starting simulation... +info: Entering event queue @ 3082312093500. Starting simulation... switching cpus -info: Entering event queue @ 3083199557500. Starting simulation... +info: Entering event queue @ 3083311965500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3084199557500. Starting simulation... +info: Entering event queue @ 3084311965500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3085199557500. Starting simulation... +info: Entering event queue @ 3085311965500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3086199557500. Starting simulation... +info: Entering event queue @ 3086311965500. Starting simulation... switching cpus -info: Entering event queue @ 3087199429500. Starting simulation... +info: Entering event queue @ 3087311837500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3088199429500. Starting simulation... +info: Entering event queue @ 3088311837500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3089199429500. Starting simulation... +info: Entering event queue @ 3089311837500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3090199429500. Starting simulation... +info: Entering event queue @ 3090311837500. Starting simulation... switching cpus -info: Entering event queue @ 3091199301500. Starting simulation... +info: Entering event queue @ 3091311709500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3092199301500. Starting simulation... +info: Entering event queue @ 3092311709500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3093199301500. Starting simulation... +info: Entering event queue @ 3093311709500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3094199301500. Starting simulation... +info: Entering event queue @ 3094311709500. Starting simulation... switching cpus -info: Entering event queue @ 3095199173500. Starting simulation... +info: Entering event queue @ 3095311581500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3096199173500. Starting simulation... +info: Entering event queue @ 3096311581500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3097199173500. Starting simulation... +info: Entering event queue @ 3097311581500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3098199173500. Starting simulation... +info: Entering event queue @ 3098311581500. Starting simulation... switching cpus -info: Entering event queue @ 3099199045500. Starting simulation... +info: Entering event queue @ 3099311453500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3100199045500. Starting simulation... +info: Entering event queue @ 3100311453500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3101199045500. Starting simulation... +info: Entering event queue @ 3101311453500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3102199045500. Starting simulation... +info: Entering event queue @ 3102311453500. Starting simulation... switching cpus -info: Entering event queue @ 3103198917500. Starting simulation... +info: Entering event queue @ 3103311325500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3104198917500. Starting simulation... +info: Entering event queue @ 3104311325500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3105198917500. Starting simulation... +info: Entering event queue @ 3105311325500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3106198917500. Starting simulation... +info: Entering event queue @ 3106311325500. Starting simulation... switching cpus -info: Entering event queue @ 3107198789500. Starting simulation... +info: Entering event queue @ 3107311197500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3108198789500. Starting simulation... +info: Entering event queue @ 3108311197500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3109198789500. Starting simulation... +info: Entering event queue @ 3109311197500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3110198789500. Starting simulation... +info: Entering event queue @ 3110311197500. Starting simulation... switching cpus -info: Entering event queue @ 3111198661500. Starting simulation... +info: Entering event queue @ 3111311069500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3112198661500. Starting simulation... +info: Entering event queue @ 3112311069500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3113198661500. Starting simulation... +info: Entering event queue @ 3113311069500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3114198661500. Starting simulation... +info: Entering event queue @ 3114311069500. Starting simulation... switching cpus -info: Entering event queue @ 3115198533500. Starting simulation... +info: Entering event queue @ 3115310941500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3116198533500. Starting simulation... +info: Entering event queue @ 3116310941500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3117198533500. Starting simulation... +info: Entering event queue @ 3117310941500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3118198533500. Starting simulation... +info: Entering event queue @ 3118310941500. Starting simulation... switching cpus -info: Entering event queue @ 3119198405500. Starting simulation... +info: Entering event queue @ 3119310813500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3120198405500. Starting simulation... +info: Entering event queue @ 3120310813500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3121198405500. Starting simulation... +info: Entering event queue @ 3121310813500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3122198405500. Starting simulation... +info: Entering event queue @ 3122310813500. Starting simulation... switching cpus -info: Entering event queue @ 3123198277500. Starting simulation... +info: Entering event queue @ 3123310685500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3124198277500. Starting simulation... +info: Entering event queue @ 3124310685500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3125198277500. Starting simulation... +info: Entering event queue @ 3125310685500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3126198277500. Starting simulation... +info: Entering event queue @ 3126310685500. Starting simulation... switching cpus -info: Entering event queue @ 3127198149500. Starting simulation... +info: Entering event queue @ 3127310557500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3128198149500. Starting simulation... +info: Entering event queue @ 3128310557500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3129198149500. Starting simulation... +info: Entering event queue @ 3129310557500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3130198149500. Starting simulation... +info: Entering event queue @ 3130310557500. Starting simulation... switching cpus -info: Entering event queue @ 3131198021500. Starting simulation... +info: Entering event queue @ 3131310429500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3132198021500. Starting simulation... +info: Entering event queue @ 3132310429500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3133198021500. Starting simulation... +info: Entering event queue @ 3133310429500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3134198021500. Starting simulation... +info: Entering event queue @ 3134310429500. Starting simulation... switching cpus -info: Entering event queue @ 3135197893500. Starting simulation... +info: Entering event queue @ 3135310301500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3136197893500. Starting simulation... +info: Entering event queue @ 3136310301500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3137197893500. Starting simulation... +info: Entering event queue @ 3137310301500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3138197893500. Starting simulation... +info: Entering event queue @ 3138310301500. Starting simulation... switching cpus -info: Entering event queue @ 3139197765500. Starting simulation... +info: Entering event queue @ 3139310173500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3140197765500. Starting simulation... +info: Entering event queue @ 3140310173500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3141197765500. Starting simulation... +info: Entering event queue @ 3141310173500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3142197765500. Starting simulation... +info: Entering event queue @ 3142310173500. Starting simulation... switching cpus -info: Entering event queue @ 3143197637500. Starting simulation... +info: Entering event queue @ 3143310045500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3144197637500. Starting simulation... +info: Entering event queue @ 3144310045500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3145197637500. Starting simulation... +info: Entering event queue @ 3145310045500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3146197637500. Starting simulation... +info: Entering event queue @ 3146310045500. Starting simulation... switching cpus -info: Entering event queue @ 3147197509500. Starting simulation... +info: Entering event queue @ 3147309917500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3148197509500. Starting simulation... +info: Entering event queue @ 3148309917500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3149197509500. Starting simulation... +info: Entering event queue @ 3149309917500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3150197509500. Starting simulation... +info: Entering event queue @ 3150309917500. Starting simulation... switching cpus -info: Entering event queue @ 3151197381500. Starting simulation... +info: Entering event queue @ 3151309789500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3152197381500. Starting simulation... +info: Entering event queue @ 3152309789500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3153197381500. Starting simulation... +info: Entering event queue @ 3153309789500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3154197381500. Starting simulation... +info: Entering event queue @ 3154309789500. Starting simulation... switching cpus -info: Entering event queue @ 3155197253500. Starting simulation... +info: Entering event queue @ 3155309661500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3156197253500. Starting simulation... +info: Entering event queue @ 3156309661500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3157197253500. Starting simulation... +info: Entering event queue @ 3157309661500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3158197253500. Starting simulation... +info: Entering event queue @ 3158309661500. Starting simulation... switching cpus -info: Entering event queue @ 3159197125500. Starting simulation... +info: Entering event queue @ 3159309533500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3160197125500. Starting simulation... +info: Entering event queue @ 3160309533500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3161197125500. Starting simulation... +info: Entering event queue @ 3161309533500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3162197125500. Starting simulation... +info: Entering event queue @ 3162309533500. Starting simulation... switching cpus -info: Entering event queue @ 3163196997500. Starting simulation... +info: Entering event queue @ 3163309405500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3164196997500. Starting simulation... +info: Entering event queue @ 3164309405500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3165196997500. Starting simulation... +info: Entering event queue @ 3165309405500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3166196997500. Starting simulation... +info: Entering event queue @ 3166309405500. Starting simulation... switching cpus -info: Entering event queue @ 3167196869500. Starting simulation... +info: Entering event queue @ 3167309277500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3168196869500. Starting simulation... +info: Entering event queue @ 3168309277500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3169196869500. Starting simulation... +info: Entering event queue @ 3169309277500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3170196869500. Starting simulation... +info: Entering event queue @ 3170309277500. Starting simulation... switching cpus -info: Entering event queue @ 3171196741500. Starting simulation... +info: Entering event queue @ 3171309149500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3172196741500. Starting simulation... +info: Entering event queue @ 3172309149500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3173196741500. Starting simulation... +info: Entering event queue @ 3173309149500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3174196741500. Starting simulation... +info: Entering event queue @ 3174309149500. Starting simulation... switching cpus -info: Entering event queue @ 3175196613500. Starting simulation... +info: Entering event queue @ 3175309021500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3176196613500. Starting simulation... +info: Entering event queue @ 3176309021500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3177196613500. Starting simulation... +info: Entering event queue @ 3177309021500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3178196613500. Starting simulation... +info: Entering event queue @ 3178309021500. Starting simulation... switching cpus -info: Entering event queue @ 3179196485500. Starting simulation... +info: Entering event queue @ 3179308893500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3180196485500. Starting simulation... +info: Entering event queue @ 3180308893500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3181196485500. Starting simulation... +info: Entering event queue @ 3181308893500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3182196485500. Starting simulation... +info: Entering event queue @ 3182308893500. Starting simulation... switching cpus -info: Entering event queue @ 3183196357500. Starting simulation... +info: Entering event queue @ 3183308765500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3184196357500. Starting simulation... +info: Entering event queue @ 3184308765500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3185196357500. Starting simulation... +info: Entering event queue @ 3185308765500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3186196357500. Starting simulation... +info: Entering event queue @ 3186308765500. Starting simulation... switching cpus -info: Entering event queue @ 3187196229500. Starting simulation... +info: Entering event queue @ 3187308637500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3188196229500. Starting simulation... +info: Entering event queue @ 3188308637500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3189196229500. Starting simulation... +info: Entering event queue @ 3189308637500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3190196229500. Starting simulation... +info: Entering event queue @ 3190308637500. Starting simulation... switching cpus -info: Entering event queue @ 3191196101500. Starting simulation... +info: Entering event queue @ 3191308509500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3192196101500. Starting simulation... +info: Entering event queue @ 3192308509500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3193196101500. Starting simulation... +info: Entering event queue @ 3193308509500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3194196101500. Starting simulation... +info: Entering event queue @ 3194308509500. Starting simulation... switching cpus -info: Entering event queue @ 3195195973500. Starting simulation... +info: Entering event queue @ 3195308381500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3196195973500. Starting simulation... +info: Entering event queue @ 3196308381500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3197195973500. Starting simulation... +info: Entering event queue @ 3197308381500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3198195973500. Starting simulation... +info: Entering event queue @ 3198308381500. Starting simulation... switching cpus -info: Entering event queue @ 3199195845500. Starting simulation... +info: Entering event queue @ 3199308253500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3200195845500. Starting simulation... +info: Entering event queue @ 3200308253500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3201195845500. Starting simulation... +info: Entering event queue @ 3201308253500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3202195845500. Starting simulation... +info: Entering event queue @ 3202308253500. Starting simulation... switching cpus -info: Entering event queue @ 3203195717500. Starting simulation... +info: Entering event queue @ 3203308125500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3204195717500. Starting simulation... +info: Entering event queue @ 3204308125500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3205195717500. Starting simulation... +info: Entering event queue @ 3205308125500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3206195717500. Starting simulation... +info: Entering event queue @ 3206308125500. Starting simulation... switching cpus -info: Entering event queue @ 3207195589500. Starting simulation... +info: Entering event queue @ 3207307997500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3208195589500. Starting simulation... +info: Entering event queue @ 3208307997500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3209195589500. Starting simulation... +info: Entering event queue @ 3209307997500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3210195589500. Starting simulation... +info: Entering event queue @ 3210307997500. Starting simulation... switching cpus -info: Entering event queue @ 3211195461500. Starting simulation... +info: Entering event queue @ 3211307869500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3212195461500. Starting simulation... +info: Entering event queue @ 3212307869500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3213195461500. Starting simulation... +info: Entering event queue @ 3213307869500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3214195461500. Starting simulation... +info: Entering event queue @ 3214307869500. Starting simulation... switching cpus -info: Entering event queue @ 3215195333500. Starting simulation... +info: Entering event queue @ 3215307741500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3216195333500. Starting simulation... +info: Entering event queue @ 3216307741500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3217195333500. Starting simulation... +info: Entering event queue @ 3217307741500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3218195333500. Starting simulation... +info: Entering event queue @ 3218307741500. Starting simulation... switching cpus -info: Entering event queue @ 3219195205500. Starting simulation... +info: Entering event queue @ 3219307613500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3220195205500. Starting simulation... +info: Entering event queue @ 3220307613500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3221195205500. Starting simulation... +info: Entering event queue @ 3221307613500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3222195205500. Starting simulation... +info: Entering event queue @ 3222307613500. Starting simulation... switching cpus -info: Entering event queue @ 3223195077500. Starting simulation... +info: Entering event queue @ 3223307485500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3224195077500. Starting simulation... +info: Entering event queue @ 3224307485500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3225195077500. Starting simulation... +info: Entering event queue @ 3225307485500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3226195077500. Starting simulation... +info: Entering event queue @ 3226307485500. Starting simulation... switching cpus -info: Entering event queue @ 3227194949500. Starting simulation... +info: Entering event queue @ 3227307357500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3228194949500. Starting simulation... +info: Entering event queue @ 3228307357500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3229194949500. Starting simulation... +info: Entering event queue @ 3229307357500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3230194949500. Starting simulation... +info: Entering event queue @ 3230307357500. Starting simulation... switching cpus -info: Entering event queue @ 3231194821500. Starting simulation... +info: Entering event queue @ 3231307229500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3232194821500. Starting simulation... +info: Entering event queue @ 3232307229500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3233194821500. Starting simulation... +info: Entering event queue @ 3233307229500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3234194821500. Starting simulation... +info: Entering event queue @ 3234307229500. Starting simulation... switching cpus -info: Entering event queue @ 3235194693500. Starting simulation... +info: Entering event queue @ 3235307101500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3236194693500. Starting simulation... +info: Entering event queue @ 3236307101500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3237194693500. Starting simulation... +info: Entering event queue @ 3237307101500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3238194693500. Starting simulation... +info: Entering event queue @ 3238307101500. Starting simulation... switching cpus -info: Entering event queue @ 3239194565500. Starting simulation... +info: Entering event queue @ 3239306973500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 3240306973500. Starting simulation... switching cpus -info: Entering event queue @ 3240194565500. Starting simulation... +info: Entering event queue @ 3240306974000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 3241194565500. Starting simulation... +info: Entering event queue @ 3241306974000. Starting simulation... +info: Entering event queue @ 3241306981500. Starting simulation... switching cpus -info: Entering event queue @ 3241194573000. Starting simulation... +info: Entering event queue @ 3241306982500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3242194573000. Starting simulation... +info: Entering event queue @ 3242306982500. Starting simulation... switching cpus -info: Entering event queue @ 3242194585000. Starting simulation... +info: Entering event queue @ 3242306992000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3243194585000. Starting simulation... +info: Entering event queue @ 3243306992000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 3244194585000. Starting simulation... +info: Entering event queue @ 3244306992000. Starting simulation... switching cpus -info: Entering event queue @ 3244194592500. Starting simulation... +info: Entering event queue @ 3244306999500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3245194592500. Starting simulation... +info: Entering event queue @ 3245306999500. Starting simulation... switching cpus -info: Entering event queue @ 3245194600000. Starting simulation... +info: Entering event queue @ 3245307007000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3246194600000. Starting simulation... +info: Entering event queue @ 3246307007000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 3247194600000. Starting simulation... -info: Entering event queue @ 3247194611000. Starting simulation... +info: Entering event queue @ 3247307007000. Starting simulation... +info: Entering event queue @ 3247307019000. Starting simulation... switching cpus -info: Entering event queue @ 3247194613500. Starting simulation... +info: Entering event queue @ 3247307021500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3248194613500. Starting simulation... +info: Entering event queue @ 3248307021500. Starting simulation... switching cpus -info: Entering event queue @ 3248194621000. Starting simulation... +info: Entering event queue @ 3248307029000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 3249307029000. Starting simulation... switching cpus -info: Entering event queue @ 3249194621000. Starting simulation... +info: Entering event queue @ 3249307029500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 3250194621000. Starting simulation... +info: Entering event queue @ 3250307029500. Starting simulation... switching cpus -info: Entering event queue @ 3250194621500. Starting simulation... +info: Entering event queue @ 3250307030000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3251194621500. Starting simulation... +info: Entering event queue @ 3251307030000. Starting simulation... switching cpus -info: Entering event queue @ 3251194629000. Starting simulation... +info: Entering event queue @ 3251307037500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3252194629000. Starting simulation... +info: Entering event queue @ 3252307037500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3253194629000. Starting simulation... +info: Entering event queue @ 3253307037500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3254194629000. Starting simulation... +info: Entering event queue @ 3254307037500. Starting simulation... switching cpus -info: Entering event queue @ 3255194053500. Starting simulation... +info: Entering event queue @ 3255306461500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3256194053500. Starting simulation... +info: Entering event queue @ 3256306461500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3257194053500. Starting simulation... +info: Entering event queue @ 3257306461500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3258194053500. Starting simulation... +info: Entering event queue @ 3258306461500. Starting simulation... switching cpus -info: Entering event queue @ 3259193925500. Starting simulation... +info: Entering event queue @ 3259306333500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3260193925500. Starting simulation... +info: Entering event queue @ 3260306333500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3261193925500. Starting simulation... +info: Entering event queue @ 3261306333500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3262193925500. Starting simulation... +info: Entering event queue @ 3262306333500. Starting simulation... switching cpus -info: Entering event queue @ 3263193797500. Starting simulation... +info: Entering event queue @ 3263306205500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3264193797500. Starting simulation... +info: Entering event queue @ 3264306205500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3265193797500. Starting simulation... +info: Entering event queue @ 3265306205500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3266193797500. Starting simulation... +info: Entering event queue @ 3266306205500. Starting simulation... switching cpus -info: Entering event queue @ 3267193669500. Starting simulation... +info: Entering event queue @ 3267306077500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3268193669500. Starting simulation... +info: Entering event queue @ 3268306077500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3269193669500. Starting simulation... +info: Entering event queue @ 3269306077500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3270193669500. Starting simulation... +info: Entering event queue @ 3270306077500. Starting simulation... switching cpus -info: Entering event queue @ 3271193541500. Starting simulation... +info: Entering event queue @ 3271305949500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3272193541500. Starting simulation... +info: Entering event queue @ 3272305949500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3273193541500. Starting simulation... +info: Entering event queue @ 3273305949500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3274193541500. Starting simulation... +info: Entering event queue @ 3274305949500. Starting simulation... switching cpus -info: Entering event queue @ 3275193413500. Starting simulation... +info: Entering event queue @ 3275305821500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3276193413500. Starting simulation... +info: Entering event queue @ 3276305821500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3277193413500. Starting simulation... +info: Entering event queue @ 3277305821500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3278193413500. Starting simulation... +info: Entering event queue @ 3278305821500. Starting simulation... switching cpus -info: Entering event queue @ 3279193285500. Starting simulation... +info: Entering event queue @ 3279305693500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3280193285500. Starting simulation... +info: Entering event queue @ 3280305693500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3281193285500. Starting simulation... +info: Entering event queue @ 3281305693500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3282193285500. Starting simulation... +info: Entering event queue @ 3282305693500. Starting simulation... switching cpus -info: Entering event queue @ 3283193157500. Starting simulation... +info: Entering event queue @ 3283305565500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3284193157500. Starting simulation... +info: Entering event queue @ 3284305565500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3285193157500. Starting simulation... +info: Entering event queue @ 3285305565500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3286193157500. Starting simulation... +info: Entering event queue @ 3286305565500. Starting simulation... switching cpus -info: Entering event queue @ 3287193029500. Starting simulation... +info: Entering event queue @ 3287305437500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3288193029500. Starting simulation... +info: Entering event queue @ 3288305437500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3289193029500. Starting simulation... +info: Entering event queue @ 3289305437500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3290193029500. Starting simulation... +info: Entering event queue @ 3290305437500. Starting simulation... switching cpus -info: Entering event queue @ 3291192901500. Starting simulation... +info: Entering event queue @ 3291305309500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3292192901500. Starting simulation... +info: Entering event queue @ 3292305309500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3293192901500. Starting simulation... +info: Entering event queue @ 3293305309500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3294192901500. Starting simulation... +info: Entering event queue @ 3294305309500. Starting simulation... switching cpus -info: Entering event queue @ 3295192773500. Starting simulation... +info: Entering event queue @ 3295305181500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3296192773500. Starting simulation... +info: Entering event queue @ 3296305181500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3297192773500. Starting simulation... +info: Entering event queue @ 3297305181500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3298192773500. Starting simulation... +info: Entering event queue @ 3298305181500. Starting simulation... switching cpus -info: Entering event queue @ 3299192645500. Starting simulation... +info: Entering event queue @ 3299305053500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3300192645500. Starting simulation... +info: Entering event queue @ 3300305053500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3301192645500. Starting simulation... +info: Entering event queue @ 3301305053500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3302192645500. Starting simulation... +info: Entering event queue @ 3302305053500. Starting simulation... switching cpus -info: Entering event queue @ 3303192517500. Starting simulation... +info: Entering event queue @ 3303304925500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3304192517500. Starting simulation... +info: Entering event queue @ 3304304925500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3305192517500. Starting simulation... +info: Entering event queue @ 3305304925500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3306192517500. Starting simulation... +info: Entering event queue @ 3306304925500. Starting simulation... switching cpus -info: Entering event queue @ 3307192389500. Starting simulation... +info: Entering event queue @ 3307304797500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3308192389500. Starting simulation... +info: Entering event queue @ 3308304797500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3309192389500. Starting simulation... +info: Entering event queue @ 3309304797500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3310192389500. Starting simulation... +info: Entering event queue @ 3310304797500. Starting simulation... switching cpus -info: Entering event queue @ 3311192261500. Starting simulation... +info: Entering event queue @ 3311304669500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3312192261500. Starting simulation... +info: Entering event queue @ 3312304669500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3313192261500. Starting simulation... +info: Entering event queue @ 3313304669500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3314192261500. Starting simulation... +info: Entering event queue @ 3314304669500. Starting simulation... switching cpus -info: Entering event queue @ 3315192133500. Starting simulation... +info: Entering event queue @ 3315304541500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3316192133500. Starting simulation... +info: Entering event queue @ 3316304541500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3317192133500. Starting simulation... +info: Entering event queue @ 3317304541500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3318192133500. Starting simulation... +info: Entering event queue @ 3318304541500. Starting simulation... switching cpus -info: Entering event queue @ 3319192005500. Starting simulation... +info: Entering event queue @ 3319304413500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3320192005500. Starting simulation... +info: Entering event queue @ 3320304413500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3321192005500. Starting simulation... +info: Entering event queue @ 3321304413500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3322192005500. Starting simulation... +info: Entering event queue @ 3322304413500. Starting simulation... switching cpus -info: Entering event queue @ 3323191877500. Starting simulation... +info: Entering event queue @ 3323304285500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3324191877500. Starting simulation... +info: Entering event queue @ 3324304285500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3325191877500. Starting simulation... +info: Entering event queue @ 3325304285500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3326191877500. Starting simulation... +info: Entering event queue @ 3326304285500. Starting simulation... switching cpus -info: Entering event queue @ 3327191749500. Starting simulation... +info: Entering event queue @ 3327304157500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3328191749500. Starting simulation... +info: Entering event queue @ 3328304157500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3329191749500. Starting simulation... +info: Entering event queue @ 3329304157500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3330191749500. Starting simulation... +info: Entering event queue @ 3330304157500. Starting simulation... switching cpus -info: Entering event queue @ 3331191621500. Starting simulation... +info: Entering event queue @ 3331304029500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3332191621500. Starting simulation... +info: Entering event queue @ 3332304029500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3333191621500. Starting simulation... +info: Entering event queue @ 3333304029500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3334191621500. Starting simulation... +info: Entering event queue @ 3334304029500. Starting simulation... switching cpus -info: Entering event queue @ 3335191493500. Starting simulation... +info: Entering event queue @ 3335303901500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3336191493500. Starting simulation... +info: Entering event queue @ 3336303901500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3337191493500. Starting simulation... +info: Entering event queue @ 3337303901500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3338191493500. Starting simulation... +info: Entering event queue @ 3338303901500. Starting simulation... switching cpus -info: Entering event queue @ 3339191365500. Starting simulation... +info: Entering event queue @ 3339303773500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3340191365500. Starting simulation... +info: Entering event queue @ 3340303773500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3341191365500. Starting simulation... +info: Entering event queue @ 3341303773500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3342191365500. Starting simulation... +info: Entering event queue @ 3342303773500. Starting simulation... switching cpus -info: Entering event queue @ 3343191237500. Starting simulation... +info: Entering event queue @ 3343303645500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3344191237500. Starting simulation... +info: Entering event queue @ 3344303645500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3345191237500. Starting simulation... +info: Entering event queue @ 3345303645500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3346191237500. Starting simulation... +info: Entering event queue @ 3346303645500. Starting simulation... switching cpus -info: Entering event queue @ 3347191109500. Starting simulation... +info: Entering event queue @ 3347303517500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3348191109500. Starting simulation... +info: Entering event queue @ 3348303517500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3349191109500. Starting simulation... +info: Entering event queue @ 3349303517500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3350191109500. Starting simulation... +info: Entering event queue @ 3350303517500. Starting simulation... switching cpus -info: Entering event queue @ 3351190981500. Starting simulation... +info: Entering event queue @ 3351303389500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3352190981500. Starting simulation... +info: Entering event queue @ 3352303389500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3353190981500. Starting simulation... +info: Entering event queue @ 3353303389500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3354190981500. Starting simulation... +info: Entering event queue @ 3354303389500. Starting simulation... switching cpus -info: Entering event queue @ 3355190853500. Starting simulation... +info: Entering event queue @ 3355303261500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3356190853500. Starting simulation... +info: Entering event queue @ 3356303261500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3357190853500. Starting simulation... +info: Entering event queue @ 3357303261500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3358190853500. Starting simulation... +info: Entering event queue @ 3358303261500. Starting simulation... switching cpus -info: Entering event queue @ 3359190725500. Starting simulation... +info: Entering event queue @ 3359303133500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3360190725500. Starting simulation... +info: Entering event queue @ 3360303133500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3361190725500. Starting simulation... +info: Entering event queue @ 3361303133500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3362190725500. Starting simulation... +info: Entering event queue @ 3362303133500. Starting simulation... switching cpus -info: Entering event queue @ 3363190597500. Starting simulation... +info: Entering event queue @ 3363303005500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3364190597500. Starting simulation... +info: Entering event queue @ 3364303005500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3365190597500. Starting simulation... +info: Entering event queue @ 3365303005500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3366190597500. Starting simulation... +info: Entering event queue @ 3366303005500. Starting simulation... switching cpus -info: Entering event queue @ 3367190469500. Starting simulation... +info: Entering event queue @ 3367302877500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3368190469500. Starting simulation... +info: Entering event queue @ 3368302877500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3369190469500. Starting simulation... +info: Entering event queue @ 3369302877500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3370190469500. Starting simulation... +info: Entering event queue @ 3370302877500. Starting simulation... switching cpus -info: Entering event queue @ 3371190341500. Starting simulation... +info: Entering event queue @ 3371302749500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3372190341500. Starting simulation... +info: Entering event queue @ 3372302749500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3373190341500. Starting simulation... +info: Entering event queue @ 3373302749500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3374190341500. Starting simulation... +info: Entering event queue @ 3374302749500. Starting simulation... switching cpus -info: Entering event queue @ 3375190213500. Starting simulation... +info: Entering event queue @ 3375302621500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3376190213500. Starting simulation... +info: Entering event queue @ 3376302621500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3377190213500. Starting simulation... +info: Entering event queue @ 3377302621500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3378190213500. Starting simulation... +info: Entering event queue @ 3378302621500. Starting simulation... switching cpus -info: Entering event queue @ 3379190085500. Starting simulation... +info: Entering event queue @ 3379302493500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3380190085500. Starting simulation... +info: Entering event queue @ 3380302493500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3381190085500. Starting simulation... +info: Entering event queue @ 3381302493500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3382190085500. Starting simulation... +info: Entering event queue @ 3382302493500. Starting simulation... switching cpus -info: Entering event queue @ 3383189957500. Starting simulation... +info: Entering event queue @ 3383302365500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3384189957500. Starting simulation... +info: Entering event queue @ 3384302365500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3385189957500. Starting simulation... +info: Entering event queue @ 3385302365500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3386189957500. Starting simulation... +info: Entering event queue @ 3386302365500. Starting simulation... switching cpus -info: Entering event queue @ 3387189829500. Starting simulation... +info: Entering event queue @ 3387302237500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3388189829500. Starting simulation... +info: Entering event queue @ 3388302237500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3389189829500. Starting simulation... +info: Entering event queue @ 3389302237500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3390189829500. Starting simulation... +info: Entering event queue @ 3390302237500. Starting simulation... switching cpus -info: Entering event queue @ 3391189701500. Starting simulation... +info: Entering event queue @ 3391302109500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3392189701500. Starting simulation... +info: Entering event queue @ 3392302109500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3393189701500. Starting simulation... +info: Entering event queue @ 3393302109500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3394189701500. Starting simulation... +info: Entering event queue @ 3394302109500. Starting simulation... switching cpus -info: Entering event queue @ 3395189573500. Starting simulation... +info: Entering event queue @ 3395301981500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3396189573500. Starting simulation... +info: Entering event queue @ 3396301981500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3397189573500. Starting simulation... +info: Entering event queue @ 3397301981500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3398189573500. Starting simulation... +info: Entering event queue @ 3398301981500. Starting simulation... switching cpus -info: Entering event queue @ 3399189445500. Starting simulation... +info: Entering event queue @ 3399301853500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3400189445500. Starting simulation... +info: Entering event queue @ 3400301853500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3401189445500. Starting simulation... +info: Entering event queue @ 3401301853500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3402189445500. Starting simulation... +info: Entering event queue @ 3402301853500. Starting simulation... switching cpus -info: Entering event queue @ 3403189317500. Starting simulation... +info: Entering event queue @ 3403301725500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3404189317500. Starting simulation... +info: Entering event queue @ 3404301725500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3405189317500. Starting simulation... +info: Entering event queue @ 3405301725500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3406189317500. Starting simulation... +info: Entering event queue @ 3406301725500. Starting simulation... switching cpus -info: Entering event queue @ 3407189189500. Starting simulation... +info: Entering event queue @ 3407301597500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3408189189500. Starting simulation... +info: Entering event queue @ 3408301597500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3409189189500. Starting simulation... +info: Entering event queue @ 3409301597500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3410189189500. Starting simulation... +info: Entering event queue @ 3410301597500. Starting simulation... switching cpus -info: Entering event queue @ 3411189061500. Starting simulation... +info: Entering event queue @ 3411301469500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3412189061500. Starting simulation... +info: Entering event queue @ 3412301469500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3413189061500. Starting simulation... +info: Entering event queue @ 3413301469500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3414189061500. Starting simulation... +info: Entering event queue @ 3414301469500. Starting simulation... switching cpus -info: Entering event queue @ 3415188933500. Starting simulation... +info: Entering event queue @ 3415301341500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3416188933500. Starting simulation... +info: Entering event queue @ 3416301341500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3417188933500. Starting simulation... +info: Entering event queue @ 3417301341500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3418188933500. Starting simulation... +info: Entering event queue @ 3418301341500. Starting simulation... switching cpus -info: Entering event queue @ 3419188805500. Starting simulation... +info: Entering event queue @ 3419301213500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3420188805500. Starting simulation... +info: Entering event queue @ 3420301213500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3421188805500. Starting simulation... +info: Entering event queue @ 3421301213500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3422188805500. Starting simulation... +info: Entering event queue @ 3422301213500. Starting simulation... switching cpus -info: Entering event queue @ 3423188677500. Starting simulation... +info: Entering event queue @ 3423301085500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3424188677500. Starting simulation... +info: Entering event queue @ 3424301085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3425188677500. Starting simulation... +info: Entering event queue @ 3425301085500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3426188677500. Starting simulation... +info: Entering event queue @ 3426301085500. Starting simulation... switching cpus -info: Entering event queue @ 3427188549500. Starting simulation... +info: Entering event queue @ 3427300957500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3428188549500. Starting simulation... +info: Entering event queue @ 3428300957500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3429188549500. Starting simulation... +info: Entering event queue @ 3429300957500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3430188549500. Starting simulation... +info: Entering event queue @ 3430300957500. Starting simulation... switching cpus -info: Entering event queue @ 3431188421500. Starting simulation... +info: Entering event queue @ 3431300829500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3432188421500. Starting simulation... +info: Entering event queue @ 3432300829500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3433188421500. Starting simulation... +info: Entering event queue @ 3433300829500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3434188421500. Starting simulation... +info: Entering event queue @ 3434300829500. Starting simulation... switching cpus -info: Entering event queue @ 3435188293500. Starting simulation... +info: Entering event queue @ 3435300701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3436188293500. Starting simulation... +info: Entering event queue @ 3436300701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3437188293500. Starting simulation... +info: Entering event queue @ 3437300701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3438188293500. Starting simulation... +info: Entering event queue @ 3438300701500. Starting simulation... switching cpus -info: Entering event queue @ 3439188165500. Starting simulation... +info: Entering event queue @ 3439300573500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3440188165500. Starting simulation... +info: Entering event queue @ 3440300573500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3441188165500. Starting simulation... +info: Entering event queue @ 3441300573500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3442188165500. Starting simulation... +info: Entering event queue @ 3442300573500. Starting simulation... switching cpus -info: Entering event queue @ 3443188037500. Starting simulation... +info: Entering event queue @ 3443300445500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3444188037500. Starting simulation... +info: Entering event queue @ 3444300445500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3445188037500. Starting simulation... +info: Entering event queue @ 3445300445500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3446188037500. Starting simulation... +info: Entering event queue @ 3446300445500. Starting simulation... switching cpus -info: Entering event queue @ 3447187909500. Starting simulation... +info: Entering event queue @ 3447300317500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3448187909500. Starting simulation... +info: Entering event queue @ 3448300317500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3449187909500. Starting simulation... +info: Entering event queue @ 3449300317500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3450187909500. Starting simulation... +info: Entering event queue @ 3450300317500. Starting simulation... switching cpus -info: Entering event queue @ 3451187781500. Starting simulation... +info: Entering event queue @ 3451300189500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3452187781500. Starting simulation... +info: Entering event queue @ 3452300189500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3453187781500. Starting simulation... +info: Entering event queue @ 3453300189500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3454187781500. Starting simulation... +info: Entering event queue @ 3454300189500. Starting simulation... switching cpus -info: Entering event queue @ 3455187653500. Starting simulation... +info: Entering event queue @ 3455300061500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3456187653500. Starting simulation... +info: Entering event queue @ 3456300061500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3457187653500. Starting simulation... +info: Entering event queue @ 3457300061500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3458187653500. Starting simulation... +info: Entering event queue @ 3458300061500. Starting simulation... switching cpus -info: Entering event queue @ 3459187525500. Starting simulation... +info: Entering event queue @ 3459299933500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3460187525500. Starting simulation... +info: Entering event queue @ 3460299933500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3461187525500. Starting simulation... +info: Entering event queue @ 3461299933500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3462187525500. Starting simulation... +info: Entering event queue @ 3462299933500. Starting simulation... switching cpus -info: Entering event queue @ 3463187397500. Starting simulation... +info: Entering event queue @ 3463299805500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3464187397500. Starting simulation... +info: Entering event queue @ 3464299805500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3465187397500. Starting simulation... +info: Entering event queue @ 3465299805500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3466187397500. Starting simulation... +info: Entering event queue @ 3466299805500. Starting simulation... switching cpus -info: Entering event queue @ 3467187269500. Starting simulation... +info: Entering event queue @ 3467299677500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3468187269500. Starting simulation... +info: Entering event queue @ 3468299677500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3469187269500. Starting simulation... +info: Entering event queue @ 3469299677500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3470187269500. Starting simulation... +info: Entering event queue @ 3470299677500. Starting simulation... switching cpus -info: Entering event queue @ 3471187141500. Starting simulation... +info: Entering event queue @ 3471299549500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3472187141500. Starting simulation... +info: Entering event queue @ 3472299549500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3473187141500. Starting simulation... +info: Entering event queue @ 3473299549500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3474187141500. Starting simulation... +info: Entering event queue @ 3474299549500. Starting simulation... switching cpus -info: Entering event queue @ 3475187013500. Starting simulation... +info: Entering event queue @ 3475299421500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3476187013500. Starting simulation... +info: Entering event queue @ 3476299421500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3477187013500. Starting simulation... +info: Entering event queue @ 3477299421500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3478187013500. Starting simulation... +info: Entering event queue @ 3478299421500. Starting simulation... switching cpus -info: Entering event queue @ 3479186885500. Starting simulation... +info: Entering event queue @ 3479299293500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3480186885500. Starting simulation... +info: Entering event queue @ 3480299293500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3481186885500. Starting simulation... +info: Entering event queue @ 3481299293500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3482186885500. Starting simulation... +info: Entering event queue @ 3482299293500. Starting simulation... switching cpus -info: Entering event queue @ 3483186757500. Starting simulation... +info: Entering event queue @ 3483299165500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3484186757500. Starting simulation... +info: Entering event queue @ 3484299165500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3485186757500. Starting simulation... +info: Entering event queue @ 3485299165500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3486186757500. Starting simulation... +info: Entering event queue @ 3486299165500. Starting simulation... switching cpus -info: Entering event queue @ 3487186629500. Starting simulation... +info: Entering event queue @ 3487299037500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3488186629500. Starting simulation... +info: Entering event queue @ 3488299037500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3489186629500. Starting simulation... +info: Entering event queue @ 3489299037500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3490186629500. Starting simulation... +info: Entering event queue @ 3490299037500. Starting simulation... switching cpus -info: Entering event queue @ 3491186501500. Starting simulation... +info: Entering event queue @ 3491298909500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3492186501500. Starting simulation... +info: Entering event queue @ 3492298909500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3493186501500. Starting simulation... +info: Entering event queue @ 3493298909500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3494186501500. Starting simulation... +info: Entering event queue @ 3494298909500. Starting simulation... switching cpus -info: Entering event queue @ 3495186373500. Starting simulation... +info: Entering event queue @ 3495298781500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3496186373500. Starting simulation... +info: Entering event queue @ 3496298781500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3497186373500. Starting simulation... +info: Entering event queue @ 3497298781500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3498186373500. Starting simulation... +info: Entering event queue @ 3498298781500. Starting simulation... switching cpus -info: Entering event queue @ 3499186245500. Starting simulation... +info: Entering event queue @ 3499298653500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3500186245500. Starting simulation... +info: Entering event queue @ 3500298653500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3501186245500. Starting simulation... +info: Entering event queue @ 3501298653500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3502186245500. Starting simulation... +info: Entering event queue @ 3502298653500. Starting simulation... switching cpus -info: Entering event queue @ 3503186117500. Starting simulation... +info: Entering event queue @ 3503298525500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3504186117500. Starting simulation... +info: Entering event queue @ 3504298525500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3505186117500. Starting simulation... +info: Entering event queue @ 3505298525500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3506186117500. Starting simulation... +info: Entering event queue @ 3506298525500. Starting simulation... switching cpus -info: Entering event queue @ 3507185989500. Starting simulation... +info: Entering event queue @ 3507298397500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3508185989500. Starting simulation... +info: Entering event queue @ 3508298397500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3509185989500. Starting simulation... +info: Entering event queue @ 3509298397500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3510185989500. Starting simulation... +info: Entering event queue @ 3510298397500. Starting simulation... switching cpus -info: Entering event queue @ 3511185861500. Starting simulation... +info: Entering event queue @ 3511298269500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3512185861500. Starting simulation... +info: Entering event queue @ 3512298269500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3513185861500. Starting simulation... +info: Entering event queue @ 3513298269500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3514185861500. Starting simulation... +info: Entering event queue @ 3514298269500. Starting simulation... switching cpus -info: Entering event queue @ 3515185733500. Starting simulation... +info: Entering event queue @ 3515298141500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3516185733500. Starting simulation... +info: Entering event queue @ 3516298141500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3517185733500. Starting simulation... +info: Entering event queue @ 3517298141500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3518185733500. Starting simulation... +info: Entering event queue @ 3518298141500. Starting simulation... switching cpus -info: Entering event queue @ 3519185605500. Starting simulation... +info: Entering event queue @ 3519298013500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3520185605500. Starting simulation... +info: Entering event queue @ 3520298013500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3521185605500. Starting simulation... +info: Entering event queue @ 3521298013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3522185605500. Starting simulation... +info: Entering event queue @ 3522298013500. Starting simulation... switching cpus -info: Entering event queue @ 3523185477500. Starting simulation... +info: Entering event queue @ 3523297885500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3524185477500. Starting simulation... +info: Entering event queue @ 3524297885500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3525185477500. Starting simulation... +info: Entering event queue @ 3525297885500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3526185477500. Starting simulation... +info: Entering event queue @ 3526297885500. Starting simulation... switching cpus -info: Entering event queue @ 3527185349500. Starting simulation... +info: Entering event queue @ 3527297757500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3528185349500. Starting simulation... +info: Entering event queue @ 3528297757500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3529185349500. Starting simulation... +info: Entering event queue @ 3529297757500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3530185349500. Starting simulation... +info: Entering event queue @ 3530297757500. Starting simulation... switching cpus -info: Entering event queue @ 3531185221500. Starting simulation... +info: Entering event queue @ 3531297629500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3532185221500. Starting simulation... +info: Entering event queue @ 3532297629500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3533185221500. Starting simulation... +info: Entering event queue @ 3533297629500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3534185221500. Starting simulation... +info: Entering event queue @ 3534297629500. Starting simulation... switching cpus -info: Entering event queue @ 3535185093500. Starting simulation... +info: Entering event queue @ 3535297501500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3536185093500. Starting simulation... +info: Entering event queue @ 3536297501500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3537185093500. Starting simulation... +info: Entering event queue @ 3537297501500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3538185093500. Starting simulation... +info: Entering event queue @ 3538297501500. Starting simulation... switching cpus -info: Entering event queue @ 3539184965500. Starting simulation... +info: Entering event queue @ 3539297373500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3540184965500. Starting simulation... +info: Entering event queue @ 3540297373500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3541184965500. Starting simulation... +info: Entering event queue @ 3541297373500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3542184965500. Starting simulation... +info: Entering event queue @ 3542297373500. Starting simulation... switching cpus -info: Entering event queue @ 3543184837500. Starting simulation... +info: Entering event queue @ 3543297245500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3544184837500. Starting simulation... +info: Entering event queue @ 3544297245500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3545184837500. Starting simulation... +info: Entering event queue @ 3545297245500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3546184837500. Starting simulation... +info: Entering event queue @ 3546297245500. Starting simulation... switching cpus -info: Entering event queue @ 3547184709500. Starting simulation... +info: Entering event queue @ 3547297117500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3548184709500. Starting simulation... +info: Entering event queue @ 3548297117500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3549184709500. Starting simulation... +info: Entering event queue @ 3549297117500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3550184709500. Starting simulation... +info: Entering event queue @ 3550297117500. Starting simulation... switching cpus -info: Entering event queue @ 3551184581500. Starting simulation... +info: Entering event queue @ 3551296989500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3552184581500. Starting simulation... +info: Entering event queue @ 3552296989500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3553184581500. Starting simulation... +info: Entering event queue @ 3553296989500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3554184581500. Starting simulation... +info: Entering event queue @ 3554296989500. Starting simulation... switching cpus -info: Entering event queue @ 3555184453500. Starting simulation... +info: Entering event queue @ 3555296861500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3556184453500. Starting simulation... +info: Entering event queue @ 3556296861500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3557184453500. Starting simulation... +info: Entering event queue @ 3557296861500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3558184453500. Starting simulation... +info: Entering event queue @ 3558296861500. Starting simulation... switching cpus -info: Entering event queue @ 3559184325500. Starting simulation... +info: Entering event queue @ 3559296733500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3560184325500. Starting simulation... +info: Entering event queue @ 3560296733500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3561184325500. Starting simulation... +info: Entering event queue @ 3561296733500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3562184325500. Starting simulation... +info: Entering event queue @ 3562296733500. Starting simulation... switching cpus -info: Entering event queue @ 3563184197500. Starting simulation... +info: Entering event queue @ 3563296605500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3564184197500. Starting simulation... +info: Entering event queue @ 3564296605500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3565184197500. Starting simulation... +info: Entering event queue @ 3565296605500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3566184197500. Starting simulation... +info: Entering event queue @ 3566296605500. Starting simulation... switching cpus -info: Entering event queue @ 3567184069500. Starting simulation... +info: Entering event queue @ 3567296477500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3568184069500. Starting simulation... +info: Entering event queue @ 3568296477500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3569184069500. Starting simulation... +info: Entering event queue @ 3569296477500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3570184069500. Starting simulation... +info: Entering event queue @ 3570296477500. Starting simulation... switching cpus -info: Entering event queue @ 3571183941500. Starting simulation... +info: Entering event queue @ 3571296349500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3572183941500. Starting simulation... +info: Entering event queue @ 3572296349500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3573183941500. Starting simulation... +info: Entering event queue @ 3573296349500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3574183941500. Starting simulation... +info: Entering event queue @ 3574296349500. Starting simulation... switching cpus -info: Entering event queue @ 3575183813500. Starting simulation... +info: Entering event queue @ 3575296221500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3576183813500. Starting simulation... +info: Entering event queue @ 3576296221500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3577183813500. Starting simulation... +info: Entering event queue @ 3577296221500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3578183813500. Starting simulation... +info: Entering event queue @ 3578296221500. Starting simulation... switching cpus -info: Entering event queue @ 3579183685500. Starting simulation... +info: Entering event queue @ 3579296093500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3580183685500. Starting simulation... +info: Entering event queue @ 3580296093500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3581183685500. Starting simulation... +info: Entering event queue @ 3581296093500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3582183685500. Starting simulation... +info: Entering event queue @ 3582296093500. Starting simulation... switching cpus -info: Entering event queue @ 3583183557500. Starting simulation... +info: Entering event queue @ 3583295965500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3584183557500. Starting simulation... +info: Entering event queue @ 3584295965500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3585183557500. Starting simulation... +info: Entering event queue @ 3585295965500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3586183557500. Starting simulation... +info: Entering event queue @ 3586295965500. Starting simulation... switching cpus -info: Entering event queue @ 3587183429500. Starting simulation... +info: Entering event queue @ 3587295837500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3588183429500. Starting simulation... +info: Entering event queue @ 3588295837500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3589183429500. Starting simulation... +info: Entering event queue @ 3589295837500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3590183429500. Starting simulation... +info: Entering event queue @ 3590295837500. Starting simulation... switching cpus -info: Entering event queue @ 3591183301500. Starting simulation... +info: Entering event queue @ 3591295709500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3592183301500. Starting simulation... +info: Entering event queue @ 3592295709500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3593183301500. Starting simulation... +info: Entering event queue @ 3593295709500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3594183301500. Starting simulation... +info: Entering event queue @ 3594295709500. Starting simulation... switching cpus -info: Entering event queue @ 3595183173500. Starting simulation... +info: Entering event queue @ 3595295581500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3596183173500. Starting simulation... +info: Entering event queue @ 3596295581500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3597183173500. Starting simulation... +info: Entering event queue @ 3597295581500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3598183173500. Starting simulation... +info: Entering event queue @ 3598295581500. Starting simulation... switching cpus -info: Entering event queue @ 3599183045500. Starting simulation... +info: Entering event queue @ 3599295453500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3600183045500. Starting simulation... +info: Entering event queue @ 3600295453500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3601183045500. Starting simulation... +info: Entering event queue @ 3601295453500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3602183045500. Starting simulation... +info: Entering event queue @ 3602295453500. Starting simulation... switching cpus -info: Entering event queue @ 3603182917500. Starting simulation... +info: Entering event queue @ 3603295325500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3604182917500. Starting simulation... +info: Entering event queue @ 3604295325500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3605182917500. Starting simulation... +info: Entering event queue @ 3605295325500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3606182917500. Starting simulation... +info: Entering event queue @ 3606295325500. Starting simulation... switching cpus -info: Entering event queue @ 3607182789500. Starting simulation... +info: Entering event queue @ 3607295197500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3608182789500. Starting simulation... +info: Entering event queue @ 3608295197500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3609182789500. Starting simulation... +info: Entering event queue @ 3609295197500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3610182789500. Starting simulation... +info: Entering event queue @ 3610295197500. Starting simulation... switching cpus -info: Entering event queue @ 3611182661500. Starting simulation... +info: Entering event queue @ 3611295069500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3612182661500. Starting simulation... +info: Entering event queue @ 3612295069500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3613182661500. Starting simulation... +info: Entering event queue @ 3613295069500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3614182661500. Starting simulation... +info: Entering event queue @ 3614295069500. Starting simulation... switching cpus -info: Entering event queue @ 3615182533500. Starting simulation... +info: Entering event queue @ 3615294941500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3616182533500. Starting simulation... +info: Entering event queue @ 3616294941500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3617182533500. Starting simulation... +info: Entering event queue @ 3617294941500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3618182533500. Starting simulation... +info: Entering event queue @ 3618294941500. Starting simulation... switching cpus -info: Entering event queue @ 3619182405500. Starting simulation... +info: Entering event queue @ 3619294813500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3620182405500. Starting simulation... +info: Entering event queue @ 3620294813500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3621182405500. Starting simulation... +info: Entering event queue @ 3621294813500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3622182405500. Starting simulation... +info: Entering event queue @ 3622294813500. Starting simulation... switching cpus -info: Entering event queue @ 3623182277500. Starting simulation... +info: Entering event queue @ 3623294685500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3624182277500. Starting simulation... +info: Entering event queue @ 3624294685500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3625182277500. Starting simulation... +info: Entering event queue @ 3625294685500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3626182277500. Starting simulation... +info: Entering event queue @ 3626294685500. Starting simulation... switching cpus -info: Entering event queue @ 3627182149500. Starting simulation... +info: Entering event queue @ 3627294557500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3628182149500. Starting simulation... +info: Entering event queue @ 3628294557500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3629182149500. Starting simulation... +info: Entering event queue @ 3629294557500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3630182149500. Starting simulation... +info: Entering event queue @ 3630294557500. Starting simulation... switching cpus -info: Entering event queue @ 3631182021500. Starting simulation... +info: Entering event queue @ 3631294429500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3632182021500. Starting simulation... +info: Entering event queue @ 3632294429500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3633182021500. Starting simulation... +info: Entering event queue @ 3633294429500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3634182021500. Starting simulation... +info: Entering event queue @ 3634294429500. Starting simulation... switching cpus -info: Entering event queue @ 3635181893500. Starting simulation... +info: Entering event queue @ 3635294301500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3636181893500. Starting simulation... +info: Entering event queue @ 3636294301500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3637181893500. Starting simulation... +info: Entering event queue @ 3637294301500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3638181893500. Starting simulation... +info: Entering event queue @ 3638294301500. Starting simulation... switching cpus -info: Entering event queue @ 3639181765500. Starting simulation... +info: Entering event queue @ 3639294173500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3640181765500. Starting simulation... +info: Entering event queue @ 3640294173500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3641181765500. Starting simulation... +info: Entering event queue @ 3641294173500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3642181765500. Starting simulation... +info: Entering event queue @ 3642294173500. Starting simulation... switching cpus -info: Entering event queue @ 3643181637500. Starting simulation... +info: Entering event queue @ 3643294045500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3644181637500. Starting simulation... +info: Entering event queue @ 3644294045500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3645181637500. Starting simulation... +info: Entering event queue @ 3645294045500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3646181637500. Starting simulation... +info: Entering event queue @ 3646294045500. Starting simulation... switching cpus -info: Entering event queue @ 3647181509500. Starting simulation... +info: Entering event queue @ 3647293917500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3648181509500. Starting simulation... +info: Entering event queue @ 3648293917500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3649181509500. Starting simulation... +info: Entering event queue @ 3649293917500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3650181509500. Starting simulation... +info: Entering event queue @ 3650293917500. Starting simulation... switching cpus -info: Entering event queue @ 3651181381500. Starting simulation... +info: Entering event queue @ 3651293789500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3652181381500. Starting simulation... +info: Entering event queue @ 3652293789500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3653181381500. Starting simulation... +info: Entering event queue @ 3653293789500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3654181381500. Starting simulation... +info: Entering event queue @ 3654293789500. Starting simulation... switching cpus -info: Entering event queue @ 3655181253500. Starting simulation... +info: Entering event queue @ 3655293661500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3656181253500. Starting simulation... +info: Entering event queue @ 3656293661500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3657181253500. Starting simulation... +info: Entering event queue @ 3657293661500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3658181253500. Starting simulation... +info: Entering event queue @ 3658293661500. Starting simulation... switching cpus -info: Entering event queue @ 3659181125500. Starting simulation... +info: Entering event queue @ 3659293533500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3660181125500. Starting simulation... +info: Entering event queue @ 3660293533500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3661181125500. Starting simulation... +info: Entering event queue @ 3661293533500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3662181125500. Starting simulation... +info: Entering event queue @ 3662293533500. Starting simulation... switching cpus -info: Entering event queue @ 3663180997500. Starting simulation... +info: Entering event queue @ 3663293405500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3664180997500. Starting simulation... +info: Entering event queue @ 3664293405500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3665180997500. Starting simulation... +info: Entering event queue @ 3665293405500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3666180997500. Starting simulation... +info: Entering event queue @ 3666293405500. Starting simulation... switching cpus -info: Entering event queue @ 3667180869500. Starting simulation... +info: Entering event queue @ 3667293277500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3668180869500. Starting simulation... +info: Entering event queue @ 3668293277500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3669180869500. Starting simulation... +info: Entering event queue @ 3669293277500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3670180869500. Starting simulation... +info: Entering event queue @ 3670293277500. Starting simulation... switching cpus -info: Entering event queue @ 3671180741500. Starting simulation... +info: Entering event queue @ 3671293149500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3672180741500. Starting simulation... +info: Entering event queue @ 3672293149500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3673180741500. Starting simulation... +info: Entering event queue @ 3673293149500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3674180741500. Starting simulation... +info: Entering event queue @ 3674293149500. Starting simulation... switching cpus -info: Entering event queue @ 3675180613500. Starting simulation... +info: Entering event queue @ 3675293021500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3676180613500. Starting simulation... +info: Entering event queue @ 3676293021500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3677180613500. Starting simulation... +info: Entering event queue @ 3677293021500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3678180613500. Starting simulation... +info: Entering event queue @ 3678293021500. Starting simulation... switching cpus -info: Entering event queue @ 3679180485500. Starting simulation... +info: Entering event queue @ 3679292893500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3680180485500. Starting simulation... +info: Entering event queue @ 3680292893500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3681180485500. Starting simulation... +info: Entering event queue @ 3681292893500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3682180485500. Starting simulation... +info: Entering event queue @ 3682292893500. Starting simulation... switching cpus -info: Entering event queue @ 3683180357500. Starting simulation... +info: Entering event queue @ 3683292765500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3684180357500. Starting simulation... +info: Entering event queue @ 3684292765500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3685180357500. Starting simulation... +info: Entering event queue @ 3685292765500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3686180357500. Starting simulation... +info: Entering event queue @ 3686292765500. Starting simulation... switching cpus -info: Entering event queue @ 3687180229500. Starting simulation... +info: Entering event queue @ 3687292637500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3688180229500. Starting simulation... +info: Entering event queue @ 3688292637500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3689180229500. Starting simulation... +info: Entering event queue @ 3689292637500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3690180229500. Starting simulation... +info: Entering event queue @ 3690292637500. Starting simulation... switching cpus -info: Entering event queue @ 3691180101500. Starting simulation... +info: Entering event queue @ 3691292509500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3692180101500. Starting simulation... +info: Entering event queue @ 3692292509500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3693180101500. Starting simulation... +info: Entering event queue @ 3693292509500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3694180101500. Starting simulation... +info: Entering event queue @ 3694292509500. Starting simulation... switching cpus -info: Entering event queue @ 3695179973500. Starting simulation... +info: Entering event queue @ 3695292381500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3696179973500. Starting simulation... +info: Entering event queue @ 3696292381500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3697179973500. Starting simulation... +info: Entering event queue @ 3697292381500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3698179973500. Starting simulation... +info: Entering event queue @ 3698292381500. Starting simulation... switching cpus -info: Entering event queue @ 3699179845500. Starting simulation... +info: Entering event queue @ 3699292253500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3700179845500. Starting simulation... +info: Entering event queue @ 3700292253500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3701179845500. Starting simulation... +info: Entering event queue @ 3701292253500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3702179845500. Starting simulation... +info: Entering event queue @ 3702292253500. Starting simulation... switching cpus -info: Entering event queue @ 3703179717500. Starting simulation... +info: Entering event queue @ 3703292125500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3704179717500. Starting simulation... +info: Entering event queue @ 3704292125500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3705179717500. Starting simulation... +info: Entering event queue @ 3705292125500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3706179717500. Starting simulation... +info: Entering event queue @ 3706292125500. Starting simulation... switching cpus -info: Entering event queue @ 3707179589500. Starting simulation... +info: Entering event queue @ 3707291997500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3708179589500. Starting simulation... +info: Entering event queue @ 3708291997500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3709179589500. Starting simulation... +info: Entering event queue @ 3709291997500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3710179589500. Starting simulation... +info: Entering event queue @ 3710291997500. Starting simulation... switching cpus -info: Entering event queue @ 3711179461500. Starting simulation... +info: Entering event queue @ 3711291869500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3712179461500. Starting simulation... +info: Entering event queue @ 3712291869500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3713179461500. Starting simulation... +info: Entering event queue @ 3713291869500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3714179461500. Starting simulation... +info: Entering event queue @ 3714291869500. Starting simulation... switching cpus -info: Entering event queue @ 3715179333500. Starting simulation... +info: Entering event queue @ 3715291741500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3716179333500. Starting simulation... +info: Entering event queue @ 3716291741500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3717179333500. Starting simulation... +info: Entering event queue @ 3717291741500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3718179333500. Starting simulation... +info: Entering event queue @ 3718291741500. Starting simulation... switching cpus -info: Entering event queue @ 3719179205500. Starting simulation... +info: Entering event queue @ 3719291613500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3720179205500. Starting simulation... +info: Entering event queue @ 3720291613500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3721179205500. Starting simulation... +info: Entering event queue @ 3721291613500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3722179205500. Starting simulation... +info: Entering event queue @ 3722291613500. Starting simulation... switching cpus -info: Entering event queue @ 3723179077500. Starting simulation... +info: Entering event queue @ 3723291485500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3724179077500. Starting simulation... +info: Entering event queue @ 3724291485500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3725179077500. Starting simulation... +info: Entering event queue @ 3725291485500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3726179077500. Starting simulation... +info: Entering event queue @ 3726291485500. Starting simulation... switching cpus -info: Entering event queue @ 3727178949500. Starting simulation... +info: Entering event queue @ 3727291357500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3728178949500. Starting simulation... +info: Entering event queue @ 3728291357500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3729178949500. Starting simulation... +info: Entering event queue @ 3729291357500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3730178949500. Starting simulation... +info: Entering event queue @ 3730291357500. Starting simulation... switching cpus -info: Entering event queue @ 3731178821500. Starting simulation... +info: Entering event queue @ 3731291229500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3732178821500. Starting simulation... +info: Entering event queue @ 3732291229500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3733178821500. Starting simulation... +info: Entering event queue @ 3733291229500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3734178821500. Starting simulation... +info: Entering event queue @ 3734291229500. Starting simulation... switching cpus -info: Entering event queue @ 3735178693500. Starting simulation... +info: Entering event queue @ 3735291101500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3736178693500. Starting simulation... +info: Entering event queue @ 3736291101500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3737178693500. Starting simulation... +info: Entering event queue @ 3737291101500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3738178693500. Starting simulation... +info: Entering event queue @ 3738291101500. Starting simulation... switching cpus -info: Entering event queue @ 3739178565500. Starting simulation... +info: Entering event queue @ 3739290973500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3740178565500. Starting simulation... +info: Entering event queue @ 3740290973500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3741178565500. Starting simulation... +info: Entering event queue @ 3741290973500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3742178565500. Starting simulation... +info: Entering event queue @ 3742290973500. Starting simulation... switching cpus -info: Entering event queue @ 3743178437500. Starting simulation... +info: Entering event queue @ 3743290845500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3744178437500. Starting simulation... +info: Entering event queue @ 3744290845500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3745178437500. Starting simulation... +info: Entering event queue @ 3745290845500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3746178437500. Starting simulation... +info: Entering event queue @ 3746290845500. Starting simulation... switching cpus -info: Entering event queue @ 3747178309500. Starting simulation... +info: Entering event queue @ 3747290717500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3748178309500. Starting simulation... +info: Entering event queue @ 3748290717500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3749178309500. Starting simulation... +info: Entering event queue @ 3749290717500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3750178309500. Starting simulation... +info: Entering event queue @ 3750290717500. Starting simulation... switching cpus -info: Entering event queue @ 3751178181500. Starting simulation... +info: Entering event queue @ 3751290589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3752178181500. Starting simulation... +info: Entering event queue @ 3752290589500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3753178181500. Starting simulation... +info: Entering event queue @ 3753290589500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3754178181500. Starting simulation... +info: Entering event queue @ 3754290589500. Starting simulation... switching cpus -info: Entering event queue @ 3755178053500. Starting simulation... +info: Entering event queue @ 3755290461500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3756178053500. Starting simulation... +info: Entering event queue @ 3756290461500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3757178053500. Starting simulation... +info: Entering event queue @ 3757290461500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3758178053500. Starting simulation... +info: Entering event queue @ 3758290461500. Starting simulation... switching cpus -info: Entering event queue @ 3759177925500. Starting simulation... +info: Entering event queue @ 3759290333500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3760177925500. Starting simulation... +info: Entering event queue @ 3760290333500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3761177925500. Starting simulation... +info: Entering event queue @ 3761290333500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3762177925500. Starting simulation... +info: Entering event queue @ 3762290333500. Starting simulation... switching cpus -info: Entering event queue @ 3763177797500. Starting simulation... +info: Entering event queue @ 3763290205500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3764177797500. Starting simulation... +info: Entering event queue @ 3764290205500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3765177797500. Starting simulation... +info: Entering event queue @ 3765290205500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3766177797500. Starting simulation... +info: Entering event queue @ 3766290205500. Starting simulation... switching cpus -info: Entering event queue @ 3767177669500. Starting simulation... +info: Entering event queue @ 3767290077500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3768177669500. Starting simulation... +info: Entering event queue @ 3768290077500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3769177669500. Starting simulation... +info: Entering event queue @ 3769290077500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3770177669500. Starting simulation... +info: Entering event queue @ 3770290077500. Starting simulation... switching cpus -info: Entering event queue @ 3771177541500. Starting simulation... +info: Entering event queue @ 3771289949500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3772177541500. Starting simulation... +info: Entering event queue @ 3772289949500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3773177541500. Starting simulation... +info: Entering event queue @ 3773289949500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3774177541500. Starting simulation... +info: Entering event queue @ 3774289949500. Starting simulation... switching cpus -info: Entering event queue @ 3775177413500. Starting simulation... +info: Entering event queue @ 3775289821500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3776177413500. Starting simulation... +info: Entering event queue @ 3776289821500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3777177413500. Starting simulation... +info: Entering event queue @ 3777289821500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3778177413500. Starting simulation... +info: Entering event queue @ 3778289821500. Starting simulation... switching cpus -info: Entering event queue @ 3779177285500. Starting simulation... +info: Entering event queue @ 3779289693500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3780177285500. Starting simulation... +info: Entering event queue @ 3780289693500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3781177285500. Starting simulation... +info: Entering event queue @ 3781289693500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3782177285500. Starting simulation... +info: Entering event queue @ 3782289693500. Starting simulation... switching cpus -info: Entering event queue @ 3783177157500. Starting simulation... +info: Entering event queue @ 3783289565500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3784177157500. Starting simulation... +info: Entering event queue @ 3784289565500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3785177157500. Starting simulation... +info: Entering event queue @ 3785289565500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3786177157500. Starting simulation... +info: Entering event queue @ 3786289565500. Starting simulation... switching cpus -info: Entering event queue @ 3787177029500. Starting simulation... +info: Entering event queue @ 3787289437500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3788177029500. Starting simulation... +info: Entering event queue @ 3788289437500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3789177029500. Starting simulation... +info: Entering event queue @ 3789289437500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3790177029500. Starting simulation... +info: Entering event queue @ 3790289437500. Starting simulation... switching cpus -info: Entering event queue @ 3791176901500. Starting simulation... +info: Entering event queue @ 3791289309500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3792176901500. Starting simulation... +info: Entering event queue @ 3792289309500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3793176901500. Starting simulation... +info: Entering event queue @ 3793289309500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3794176901500. Starting simulation... +info: Entering event queue @ 3794289309500. Starting simulation... switching cpus -info: Entering event queue @ 3795176773500. Starting simulation... +info: Entering event queue @ 3795289181500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3796176773500. Starting simulation... +info: Entering event queue @ 3796289181500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3797176773500. Starting simulation... +info: Entering event queue @ 3797289181500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3798176773500. Starting simulation... +info: Entering event queue @ 3798289181500. Starting simulation... switching cpus -info: Entering event queue @ 3799176645500. Starting simulation... +info: Entering event queue @ 3799289053500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3800176645500. Starting simulation... +info: Entering event queue @ 3800289053500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3801176645500. Starting simulation... +info: Entering event queue @ 3801289053500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3802176645500. Starting simulation... +info: Entering event queue @ 3802289053500. Starting simulation... switching cpus -info: Entering event queue @ 3803176517500. Starting simulation... +info: Entering event queue @ 3803288925500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3804176517500. Starting simulation... +info: Entering event queue @ 3804288925500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3805176517500. Starting simulation... +info: Entering event queue @ 3805288925500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3806176517500. Starting simulation... +info: Entering event queue @ 3806288925500. Starting simulation... switching cpus -info: Entering event queue @ 3807176389500. Starting simulation... +info: Entering event queue @ 3807288797500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3808176389500. Starting simulation... +info: Entering event queue @ 3808288797500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3809176389500. Starting simulation... +info: Entering event queue @ 3809288797500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3810176389500. Starting simulation... +info: Entering event queue @ 3810288797500. Starting simulation... switching cpus -info: Entering event queue @ 3811176261500. Starting simulation... +info: Entering event queue @ 3811288669500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3812176261500. Starting simulation... +info: Entering event queue @ 3812288669500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3813176261500. Starting simulation... +info: Entering event queue @ 3813288669500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3814176261500. Starting simulation... +info: Entering event queue @ 3814288669500. Starting simulation... switching cpus -info: Entering event queue @ 3815176133500. Starting simulation... +info: Entering event queue @ 3815288541500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3816176133500. Starting simulation... +info: Entering event queue @ 3816288541500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3817176133500. Starting simulation... +info: Entering event queue @ 3817288541500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3818176133500. Starting simulation... +info: Entering event queue @ 3818288541500. Starting simulation... switching cpus -info: Entering event queue @ 3819176005500. Starting simulation... +info: Entering event queue @ 3819288413500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3820176005500. Starting simulation... +info: Entering event queue @ 3820288413500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3821176005500. Starting simulation... +info: Entering event queue @ 3821288413500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3822176005500. Starting simulation... +info: Entering event queue @ 3822288413500. Starting simulation... switching cpus -info: Entering event queue @ 3823175877500. Starting simulation... +info: Entering event queue @ 3823288285500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3824175877500. Starting simulation... +info: Entering event queue @ 3824288285500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3825175877500. Starting simulation... +info: Entering event queue @ 3825288285500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3826175877500. Starting simulation... +info: Entering event queue @ 3826288285500. Starting simulation... switching cpus -info: Entering event queue @ 3827175749500. Starting simulation... +info: Entering event queue @ 3827288157500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3828175749500. Starting simulation... +info: Entering event queue @ 3828288157500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3829175749500. Starting simulation... +info: Entering event queue @ 3829288157500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3830175749500. Starting simulation... +info: Entering event queue @ 3830288157500. Starting simulation... switching cpus -info: Entering event queue @ 3831175621500. Starting simulation... +info: Entering event queue @ 3831288029500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3832175621500. Starting simulation... +info: Entering event queue @ 3832288029500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3833175621500. Starting simulation... +info: Entering event queue @ 3833288029500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3834175621500. Starting simulation... +info: Entering event queue @ 3834288029500. Starting simulation... switching cpus -info: Entering event queue @ 3835175493500. Starting simulation... +info: Entering event queue @ 3835287901500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3836175493500. Starting simulation... +info: Entering event queue @ 3836287901500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3837175493500. Starting simulation... +info: Entering event queue @ 3837287901500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3838175493500. Starting simulation... +info: Entering event queue @ 3838287901500. Starting simulation... switching cpus -info: Entering event queue @ 3839175365500. Starting simulation... +info: Entering event queue @ 3839287773500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3840175365500. Starting simulation... +info: Entering event queue @ 3840287773500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3841175365500. Starting simulation... +info: Entering event queue @ 3841287773500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3842175365500. Starting simulation... +info: Entering event queue @ 3842287773500. Starting simulation... switching cpus -info: Entering event queue @ 3843175237500. Starting simulation... +info: Entering event queue @ 3843287645500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3844175237500. Starting simulation... +info: Entering event queue @ 3844287645500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3845175237500. Starting simulation... +info: Entering event queue @ 3845287645500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3846175237500. Starting simulation... +info: Entering event queue @ 3846287645500. Starting simulation... switching cpus -info: Entering event queue @ 3847175109500. Starting simulation... +info: Entering event queue @ 3847287517500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3848175109500. Starting simulation... +info: Entering event queue @ 3848287517500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3849175109500. Starting simulation... +info: Entering event queue @ 3849287517500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3850175109500. Starting simulation... +info: Entering event queue @ 3850287517500. Starting simulation... switching cpus -info: Entering event queue @ 3851174981500. Starting simulation... +info: Entering event queue @ 3851287389500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3852174981500. Starting simulation... +info: Entering event queue @ 3852287389500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3853174981500. Starting simulation... +info: Entering event queue @ 3853287389500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3854174981500. Starting simulation... +info: Entering event queue @ 3854287389500. Starting simulation... switching cpus -info: Entering event queue @ 3855174853500. Starting simulation... +info: Entering event queue @ 3855287261500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3856174853500. Starting simulation... +info: Entering event queue @ 3856287261500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3857174853500. Starting simulation... +info: Entering event queue @ 3857287261500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3858174853500. Starting simulation... +info: Entering event queue @ 3858287261500. Starting simulation... switching cpus -info: Entering event queue @ 3859174725500. Starting simulation... +info: Entering event queue @ 3859287133500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3860174725500. Starting simulation... +info: Entering event queue @ 3860287133500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3861174725500. Starting simulation... +info: Entering event queue @ 3861287133500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3862174725500. Starting simulation... +info: Entering event queue @ 3862287133500. Starting simulation... switching cpus -info: Entering event queue @ 3863174597500. Starting simulation... +info: Entering event queue @ 3863287005500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 3864174597500. Starting simulation... +info: Entering event queue @ 3864287005500. Starting simulation... switching cpus -info: Entering event queue @ 3864174598500. Starting simulation... +info: Entering event queue @ 3864287006000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 3865174598500. Starting simulation... +info: Entering event queue @ 3865287006000. Starting simulation... switching cpus -info: Entering event queue @ 3865174599000. Starting simulation... +info: Entering event queue @ 3865287013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3866174599000. Starting simulation... +info: Entering event queue @ 3866287013500. Starting simulation... switching cpus -info: Entering event queue @ 3866174603000. Starting simulation... +info: Entering event queue @ 3866287017500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3867174603000. Starting simulation... +info: Entering event queue @ 3867287017500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 3868174603000. Starting simulation... +info: Entering event queue @ 3868287017500. Starting simulation... switching cpus -info: Entering event queue @ 3868174604000. Starting simulation... +info: Entering event queue @ 3868287018500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3869174604000. Starting simulation... +info: Entering event queue @ 3869287018500. Starting simulation... switching cpus -info: Entering event queue @ 3869174608000. Starting simulation... +info: Entering event queue @ 3869287022500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 3870287022500. Starting simulation... switching cpus -info: Entering event queue @ 3870174608000. Starting simulation... +info: Entering event queue @ 3870287023500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 3871174608000. Starting simulation... +info: Entering event queue @ 3871287023500. Starting simulation... switching cpus -info: Entering event queue @ 3871174608500. Starting simulation... +info: Entering event queue @ 3871287024000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3872174608500. Starting simulation... +info: Entering event queue @ 3872287024000. Starting simulation... switching cpus -info: Entering event queue @ 3872174616000. Starting simulation... +info: Entering event queue @ 3872287031500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 3873287031500. Starting simulation... switching cpus -info: Entering event queue @ 3873174616000. Starting simulation... +info: Entering event queue @ 3873287032500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3874174616000. Starting simulation... +info: Entering event queue @ 3874287032500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3875174616000. Starting simulation... +info: Entering event queue @ 3875287032500. Starting simulation... +info: Entering event queue @ 3875287061250. Starting simulation... switching cpus -info: Entering event queue @ 3875174619500. Starting simulation... +info: Entering event queue @ 3875287068750. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3876174619500. Starting simulation... +info: Entering event queue @ 3876287068750. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3877174619500. Starting simulation... +info: Entering event queue @ 3877287068750. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3878174619500. Starting simulation... +info: Entering event queue @ 3878287068750. Starting simulation... switching cpus -info: Entering event queue @ 3879174082000. Starting simulation... +info: Entering event queue @ 3879286493500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3880174082000. Starting simulation... +info: Entering event queue @ 3880286493500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3881174082000. Starting simulation... +info: Entering event queue @ 3881286493500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3882174082000. Starting simulation... +info: Entering event queue @ 3882286493500. Starting simulation... switching cpus -info: Entering event queue @ 3883173957500. Starting simulation... +info: Entering event queue @ 3883286365500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3884173957500. Starting simulation... +info: Entering event queue @ 3884286365500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3885173957500. Starting simulation... +info: Entering event queue @ 3885286365500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3886173957500. Starting simulation... +info: Entering event queue @ 3886286365500. Starting simulation... switching cpus -info: Entering event queue @ 3887173829500. Starting simulation... +info: Entering event queue @ 3887286237500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3888173829500. Starting simulation... +info: Entering event queue @ 3888286237500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3889173829500. Starting simulation... +info: Entering event queue @ 3889286237500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3890173829500. Starting simulation... +info: Entering event queue @ 3890286237500. Starting simulation... switching cpus -info: Entering event queue @ 3891173701500. Starting simulation... +info: Entering event queue @ 3891286109500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3892173701500. Starting simulation... +info: Entering event queue @ 3892286109500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3893173701500. Starting simulation... +info: Entering event queue @ 3893286109500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3894173701500. Starting simulation... +info: Entering event queue @ 3894286109500. Starting simulation... switching cpus -info: Entering event queue @ 3895173573500. Starting simulation... +info: Entering event queue @ 3895285981500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3896173573500. Starting simulation... +info: Entering event queue @ 3896285981500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3897173573500. Starting simulation... +info: Entering event queue @ 3897285981500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3898173573500. Starting simulation... +info: Entering event queue @ 3898285981500. Starting simulation... switching cpus -info: Entering event queue @ 3899173445500. Starting simulation... +info: Entering event queue @ 3899285853500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3900173445500. Starting simulation... +info: Entering event queue @ 3900285853500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3901173445500. Starting simulation... +info: Entering event queue @ 3901285853500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3902173445500. Starting simulation... +info: Entering event queue @ 3902285853500. Starting simulation... switching cpus -info: Entering event queue @ 3903173317500. Starting simulation... +info: Entering event queue @ 3903285725500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3904173317500. Starting simulation... +info: Entering event queue @ 3904285725500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3905173317500. Starting simulation... +info: Entering event queue @ 3905285725500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3906173317500. Starting simulation... +info: Entering event queue @ 3906285725500. Starting simulation... switching cpus -info: Entering event queue @ 3907173189500. Starting simulation... +info: Entering event queue @ 3907285597500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3908173189500. Starting simulation... +info: Entering event queue @ 3908285597500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3909173189500. Starting simulation... +info: Entering event queue @ 3909285597500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3910173189500. Starting simulation... +info: Entering event queue @ 3910285597500. Starting simulation... switching cpus -info: Entering event queue @ 3911173061500. Starting simulation... +info: Entering event queue @ 3911285469500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3912173061500. Starting simulation... +info: Entering event queue @ 3912285469500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3913173061500. Starting simulation... +info: Entering event queue @ 3913285469500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3914173061500. Starting simulation... +info: Entering event queue @ 3914285469500. Starting simulation... switching cpus -info: Entering event queue @ 3915172933500. Starting simulation... +info: Entering event queue @ 3915285341500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3916172933500. Starting simulation... +info: Entering event queue @ 3916285341500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3917172933500. Starting simulation... +info: Entering event queue @ 3917285341500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3918172933500. Starting simulation... +info: Entering event queue @ 3918285341500. Starting simulation... switching cpus -info: Entering event queue @ 3919172805500. Starting simulation... +info: Entering event queue @ 3919285213500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3920172805500. Starting simulation... +info: Entering event queue @ 3920285213500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3921172805500. Starting simulation... +info: Entering event queue @ 3921285213500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3922172805500. Starting simulation... +info: Entering event queue @ 3922285213500. Starting simulation... switching cpus -info: Entering event queue @ 3923172677500. Starting simulation... +info: Entering event queue @ 3923285085500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3924172677500. Starting simulation... +info: Entering event queue @ 3924285085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3925172677500. Starting simulation... +info: Entering event queue @ 3925285085500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3926172677500. Starting simulation... +info: Entering event queue @ 3926285085500. Starting simulation... switching cpus -info: Entering event queue @ 3927172549500. Starting simulation... +info: Entering event queue @ 3927284957500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3928172549500. Starting simulation... +info: Entering event queue @ 3928284957500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3929172549500. Starting simulation... +info: Entering event queue @ 3929284957500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3930172549500. Starting simulation... +info: Entering event queue @ 3930284957500. Starting simulation... switching cpus -info: Entering event queue @ 3931172421500. Starting simulation... +info: Entering event queue @ 3931284829500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3932172421500. Starting simulation... +info: Entering event queue @ 3932284829500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3933172421500. Starting simulation... +info: Entering event queue @ 3933284829500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3934172421500. Starting simulation... +info: Entering event queue @ 3934284829500. Starting simulation... switching cpus -info: Entering event queue @ 3935172293500. Starting simulation... +info: Entering event queue @ 3935284701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3936172293500. Starting simulation... +info: Entering event queue @ 3936284701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3937172293500. Starting simulation... +info: Entering event queue @ 3937284701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3938172293500. Starting simulation... +info: Entering event queue @ 3938284701500. Starting simulation... switching cpus -info: Entering event queue @ 3939172165500. Starting simulation... +info: Entering event queue @ 3939284573500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3940172165500. Starting simulation... +info: Entering event queue @ 3940284573500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3941172165500. Starting simulation... +info: Entering event queue @ 3941284573500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3942172165500. Starting simulation... +info: Entering event queue @ 3942284573500. Starting simulation... switching cpus -info: Entering event queue @ 3943172037500. Starting simulation... +info: Entering event queue @ 3943284445500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3944172037500. Starting simulation... +info: Entering event queue @ 3944284445500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3945172037500. Starting simulation... +info: Entering event queue @ 3945284445500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3946172037500. Starting simulation... +info: Entering event queue @ 3946284445500. Starting simulation... switching cpus -info: Entering event queue @ 3947171909500. Starting simulation... +info: Entering event queue @ 3947284317500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3948171909500. Starting simulation... +info: Entering event queue @ 3948284317500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3949171909500. Starting simulation... +info: Entering event queue @ 3949284317500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3950171909500. Starting simulation... +info: Entering event queue @ 3950284317500. Starting simulation... switching cpus -info: Entering event queue @ 3951171781500. Starting simulation... +info: Entering event queue @ 3951284189500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3952171781500. Starting simulation... +info: Entering event queue @ 3952284189500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3953171781500. Starting simulation... +info: Entering event queue @ 3953284189500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3954171781500. Starting simulation... +info: Entering event queue @ 3954284189500. Starting simulation... switching cpus -info: Entering event queue @ 3955171653500. Starting simulation... +info: Entering event queue @ 3955284061500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3956171653500. Starting simulation... +info: Entering event queue @ 3956284061500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3957171653500. Starting simulation... +info: Entering event queue @ 3957284061500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3958171653500. Starting simulation... +info: Entering event queue @ 3958284061500. Starting simulation... switching cpus -info: Entering event queue @ 3959171525500. Starting simulation... +info: Entering event queue @ 3959283933500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3960171525500. Starting simulation... +info: Entering event queue @ 3960283933500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3961171525500. Starting simulation... +info: Entering event queue @ 3961283933500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3962171525500. Starting simulation... +info: Entering event queue @ 3962283933500. Starting simulation... switching cpus -info: Entering event queue @ 3963171397500. Starting simulation... +info: Entering event queue @ 3963283805500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3964171397500. Starting simulation... +info: Entering event queue @ 3964283805500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3965171397500. Starting simulation... +info: Entering event queue @ 3965283805500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3966171397500. Starting simulation... +info: Entering event queue @ 3966283805500. Starting simulation... switching cpus -info: Entering event queue @ 3967171269500. Starting simulation... +info: Entering event queue @ 3967283677500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3968171269500. Starting simulation... +info: Entering event queue @ 3968283677500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3969171269500. Starting simulation... +info: Entering event queue @ 3969283677500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3970171269500. Starting simulation... +info: Entering event queue @ 3970283677500. Starting simulation... switching cpus -info: Entering event queue @ 3971171141500. Starting simulation... +info: Entering event queue @ 3971283549500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3972171141500. Starting simulation... +info: Entering event queue @ 3972283549500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3973171141500. Starting simulation... +info: Entering event queue @ 3973283549500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3974171141500. Starting simulation... +info: Entering event queue @ 3974283549500. Starting simulation... switching cpus -info: Entering event queue @ 3975171013500. Starting simulation... +info: Entering event queue @ 3975283421500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3976171013500. Starting simulation... +info: Entering event queue @ 3976283421500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3977171013500. Starting simulation... +info: Entering event queue @ 3977283421500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3978171013500. Starting simulation... +info: Entering event queue @ 3978283421500. Starting simulation... switching cpus -info: Entering event queue @ 3979170885500. Starting simulation... +info: Entering event queue @ 3979283293500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3980170885500. Starting simulation... +info: Entering event queue @ 3980283293500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3981170885500. Starting simulation... +info: Entering event queue @ 3981283293500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3982170885500. Starting simulation... +info: Entering event queue @ 3982283293500. Starting simulation... switching cpus -info: Entering event queue @ 3983170757500. Starting simulation... +info: Entering event queue @ 3983283165500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3984170757500. Starting simulation... +info: Entering event queue @ 3984283165500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3985170757500. Starting simulation... +info: Entering event queue @ 3985283165500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3986170757500. Starting simulation... +info: Entering event queue @ 3986283165500. Starting simulation... switching cpus -info: Entering event queue @ 3987170629500. Starting simulation... +info: Entering event queue @ 3987283037500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3988170629500. Starting simulation... +info: Entering event queue @ 3988283037500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3989170629500. Starting simulation... +info: Entering event queue @ 3989283037500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3990170629500. Starting simulation... +info: Entering event queue @ 3990283037500. Starting simulation... switching cpus -info: Entering event queue @ 3991170501500. Starting simulation... +info: Entering event queue @ 3991282909500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3992170501500. Starting simulation... +info: Entering event queue @ 3992282909500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3993170501500. Starting simulation... +info: Entering event queue @ 3993282909500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3994170501500. Starting simulation... +info: Entering event queue @ 3994282909500. Starting simulation... switching cpus -info: Entering event queue @ 3995170373500. Starting simulation... +info: Entering event queue @ 3995282781500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 3996170373500. Starting simulation... +info: Entering event queue @ 3996282781500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 3997170373500. Starting simulation... +info: Entering event queue @ 3997282781500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3998170373500. Starting simulation... +info: Entering event queue @ 3998282781500. Starting simulation... switching cpus -info: Entering event queue @ 3999170245500. Starting simulation... +info: Entering event queue @ 3999282653500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4000170245500. Starting simulation... +info: Entering event queue @ 4000282653500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4001170245500. Starting simulation... +info: Entering event queue @ 4001282653500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4002170245500. Starting simulation... +info: Entering event queue @ 4002282653500. Starting simulation... switching cpus -info: Entering event queue @ 4003170117500. Starting simulation... +info: Entering event queue @ 4003282525500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4004170117500. Starting simulation... +info: Entering event queue @ 4004282525500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4005170117500. Starting simulation... +info: Entering event queue @ 4005282525500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4006170117500. Starting simulation... +info: Entering event queue @ 4006282525500. Starting simulation... switching cpus -info: Entering event queue @ 4007169989500. Starting simulation... +info: Entering event queue @ 4007282397500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4008169989500. Starting simulation... +info: Entering event queue @ 4008282397500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4009169989500. Starting simulation... +info: Entering event queue @ 4009282397500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4010169989500. Starting simulation... +info: Entering event queue @ 4010282397500. Starting simulation... switching cpus -info: Entering event queue @ 4011169861500. Starting simulation... +info: Entering event queue @ 4011282269500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4012169861500. Starting simulation... +info: Entering event queue @ 4012282269500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4013169861500. Starting simulation... +info: Entering event queue @ 4013282269500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4014169861500. Starting simulation... +info: Entering event queue @ 4014282269500. Starting simulation... switching cpus -info: Entering event queue @ 4015169733500. Starting simulation... +info: Entering event queue @ 4015282141500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4016169733500. Starting simulation... +info: Entering event queue @ 4016282141500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4017169733500. Starting simulation... +info: Entering event queue @ 4017282141500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4018169733500. Starting simulation... +info: Entering event queue @ 4018282141500. Starting simulation... switching cpus -info: Entering event queue @ 4019169605500. Starting simulation... +info: Entering event queue @ 4019282013500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4020169605500. Starting simulation... +info: Entering event queue @ 4020282013500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4021169605500. Starting simulation... +info: Entering event queue @ 4021282013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4022169605500. Starting simulation... +info: Entering event queue @ 4022282013500. Starting simulation... switching cpus -info: Entering event queue @ 4023169477500. Starting simulation... +info: Entering event queue @ 4023281885500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4024169477500. Starting simulation... +info: Entering event queue @ 4024281885500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4025169477500. Starting simulation... +info: Entering event queue @ 4025281885500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4026169477500. Starting simulation... +info: Entering event queue @ 4026281885500. Starting simulation... switching cpus -info: Entering event queue @ 4027169349500. Starting simulation... +info: Entering event queue @ 4027281757500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4028169349500. Starting simulation... +info: Entering event queue @ 4028281757500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4029169349500. Starting simulation... +info: Entering event queue @ 4029281757500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4030169349500. Starting simulation... +info: Entering event queue @ 4030281757500. Starting simulation... switching cpus -info: Entering event queue @ 4031169221500. Starting simulation... +info: Entering event queue @ 4031281629500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4032169221500. Starting simulation... +info: Entering event queue @ 4032281629500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4033169221500. Starting simulation... +info: Entering event queue @ 4033281629500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4034169221500. Starting simulation... +info: Entering event queue @ 4034281629500. Starting simulation... switching cpus -info: Entering event queue @ 4035169093500. Starting simulation... +info: Entering event queue @ 4035281501500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4036169093500. Starting simulation... +info: Entering event queue @ 4036281501500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4037169093500. Starting simulation... +info: Entering event queue @ 4037281501500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4038169093500. Starting simulation... +info: Entering event queue @ 4038281501500. Starting simulation... switching cpus -info: Entering event queue @ 4039168965500. Starting simulation... +info: Entering event queue @ 4039281373500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4040168965500. Starting simulation... +info: Entering event queue @ 4040281373500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4041168965500. Starting simulation... +info: Entering event queue @ 4041281373500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4042168965500. Starting simulation... +info: Entering event queue @ 4042281373500. Starting simulation... switching cpus -info: Entering event queue @ 4043168837500. Starting simulation... +info: Entering event queue @ 4043281245500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4044168837500. Starting simulation... +info: Entering event queue @ 4044281245500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4045168837500. Starting simulation... +info: Entering event queue @ 4045281245500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4046168837500. Starting simulation... +info: Entering event queue @ 4046281245500. Starting simulation... switching cpus -info: Entering event queue @ 4047168709500. Starting simulation... +info: Entering event queue @ 4047281117500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4048168709500. Starting simulation... +info: Entering event queue @ 4048281117500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4049168709500. Starting simulation... +info: Entering event queue @ 4049281117500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4050168709500. Starting simulation... +info: Entering event queue @ 4050281117500. Starting simulation... switching cpus -info: Entering event queue @ 4051168581500. Starting simulation... +info: Entering event queue @ 4051280989500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4052168581500. Starting simulation... +info: Entering event queue @ 4052280989500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4053168581500. Starting simulation... +info: Entering event queue @ 4053280989500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4054168581500. Starting simulation... +info: Entering event queue @ 4054280989500. Starting simulation... switching cpus -info: Entering event queue @ 4055168453500. Starting simulation... +info: Entering event queue @ 4055280861500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4056168453500. Starting simulation... +info: Entering event queue @ 4056280861500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4057168453500. Starting simulation... +info: Entering event queue @ 4057280861500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4058168453500. Starting simulation... +info: Entering event queue @ 4058280861500. Starting simulation... switching cpus -info: Entering event queue @ 4059168325500. Starting simulation... +info: Entering event queue @ 4059280733500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4060168325500. Starting simulation... +info: Entering event queue @ 4060280733500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4061168325500. Starting simulation... +info: Entering event queue @ 4061280733500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4062168325500. Starting simulation... +info: Entering event queue @ 4062280733500. Starting simulation... switching cpus -info: Entering event queue @ 4063168197500. Starting simulation... +info: Entering event queue @ 4063280605500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4064168197500. Starting simulation... +info: Entering event queue @ 4064280605500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4065168197500. Starting simulation... +info: Entering event queue @ 4065280605500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4066168197500. Starting simulation... +info: Entering event queue @ 4066280605500. Starting simulation... switching cpus -info: Entering event queue @ 4067168069500. Starting simulation... +info: Entering event queue @ 4067280477500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4068168069500. Starting simulation... +info: Entering event queue @ 4068280477500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4069168069500. Starting simulation... +info: Entering event queue @ 4069280477500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4070168069500. Starting simulation... +info: Entering event queue @ 4070280477500. Starting simulation... switching cpus -info: Entering event queue @ 4071167941500. Starting simulation... +info: Entering event queue @ 4071280349500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4072167941500. Starting simulation... +info: Entering event queue @ 4072280349500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4073167941500. Starting simulation... +info: Entering event queue @ 4073280349500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4074167941500. Starting simulation... +info: Entering event queue @ 4074280349500. Starting simulation... switching cpus -info: Entering event queue @ 4075167813500. Starting simulation... +info: Entering event queue @ 4075280221500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4076167813500. Starting simulation... +info: Entering event queue @ 4076280221500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4077167813500. Starting simulation... +info: Entering event queue @ 4077280221500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4078167813500. Starting simulation... +info: Entering event queue @ 4078280221500. Starting simulation... switching cpus -info: Entering event queue @ 4079167685500. Starting simulation... +info: Entering event queue @ 4079280093500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4080167685500. Starting simulation... +info: Entering event queue @ 4080280093500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4081167685500. Starting simulation... +info: Entering event queue @ 4081280093500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4082167685500. Starting simulation... +info: Entering event queue @ 4082280093500. Starting simulation... switching cpus -info: Entering event queue @ 4083167557500. Starting simulation... +info: Entering event queue @ 4083279965500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4084167557500. Starting simulation... +info: Entering event queue @ 4084279965500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4085167557500. Starting simulation... +info: Entering event queue @ 4085279965500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4086167557500. Starting simulation... +info: Entering event queue @ 4086279965500. Starting simulation... switching cpus -info: Entering event queue @ 4087167429500. Starting simulation... +info: Entering event queue @ 4087279837500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4088167429500. Starting simulation... +info: Entering event queue @ 4088279837500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4089167429500. Starting simulation... +info: Entering event queue @ 4089279837500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4090167429500. Starting simulation... +info: Entering event queue @ 4090279837500. Starting simulation... switching cpus -info: Entering event queue @ 4091167301500. Starting simulation... +info: Entering event queue @ 4091279709500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4092167301500. Starting simulation... +info: Entering event queue @ 4092279709500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4093167301500. Starting simulation... +info: Entering event queue @ 4093279709500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4094167301500. Starting simulation... +info: Entering event queue @ 4094279709500. Starting simulation... switching cpus -info: Entering event queue @ 4095167173500. Starting simulation... +info: Entering event queue @ 4095279581500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4096167173500. Starting simulation... +info: Entering event queue @ 4096279581500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4097167173500. Starting simulation... +info: Entering event queue @ 4097279581500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4098167173500. Starting simulation... +info: Entering event queue @ 4098279581500. Starting simulation... switching cpus -info: Entering event queue @ 4099167045500. Starting simulation... +info: Entering event queue @ 4099279453500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4100167045500. Starting simulation... +info: Entering event queue @ 4100279453500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4101167045500. Starting simulation... +info: Entering event queue @ 4101279453500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4102167045500. Starting simulation... +info: Entering event queue @ 4102279453500. Starting simulation... switching cpus -info: Entering event queue @ 4103166917500. Starting simulation... +info: Entering event queue @ 4103279325500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4104166917500. Starting simulation... +info: Entering event queue @ 4104279325500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4105166917500. Starting simulation... +info: Entering event queue @ 4105279325500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4106166917500. Starting simulation... +info: Entering event queue @ 4106279325500. Starting simulation... switching cpus -info: Entering event queue @ 4107166789500. Starting simulation... +info: Entering event queue @ 4107279197500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4108166789500. Starting simulation... +info: Entering event queue @ 4108279197500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4109166789500. Starting simulation... +info: Entering event queue @ 4109279197500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4110166789500. Starting simulation... +info: Entering event queue @ 4110279197500. Starting simulation... switching cpus -info: Entering event queue @ 4111166661500. Starting simulation... +info: Entering event queue @ 4111279069500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4112166661500. Starting simulation... +info: Entering event queue @ 4112279069500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4113166661500. Starting simulation... +info: Entering event queue @ 4113279069500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4114166661500. Starting simulation... +info: Entering event queue @ 4114279069500. Starting simulation... switching cpus -info: Entering event queue @ 4115166533500. Starting simulation... +info: Entering event queue @ 4115278941500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4116166533500. Starting simulation... +info: Entering event queue @ 4116278941500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4117166533500. Starting simulation... +info: Entering event queue @ 4117278941500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4118166533500. Starting simulation... +info: Entering event queue @ 4118278941500. Starting simulation... switching cpus -info: Entering event queue @ 4119166405500. Starting simulation... +info: Entering event queue @ 4119278813500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4120166405500. Starting simulation... +info: Entering event queue @ 4120278813500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4121166405500. Starting simulation... +info: Entering event queue @ 4121278813500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4122166405500. Starting simulation... +info: Entering event queue @ 4122278813500. Starting simulation... switching cpus -info: Entering event queue @ 4123166277500. Starting simulation... +info: Entering event queue @ 4123278685500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4124166277500. Starting simulation... +info: Entering event queue @ 4124278685500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4125166277500. Starting simulation... +info: Entering event queue @ 4125278685500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4126166277500. Starting simulation... +info: Entering event queue @ 4126278685500. Starting simulation... switching cpus -info: Entering event queue @ 4127166149500. Starting simulation... +info: Entering event queue @ 4127278557500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4128166149500. Starting simulation... +info: Entering event queue @ 4128278557500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4129166149500. Starting simulation... +info: Entering event queue @ 4129278557500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4130166149500. Starting simulation... +info: Entering event queue @ 4130278557500. Starting simulation... switching cpus -info: Entering event queue @ 4131166021500. Starting simulation... +info: Entering event queue @ 4131278429500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4132166021500. Starting simulation... +info: Entering event queue @ 4132278429500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4133166021500. Starting simulation... +info: Entering event queue @ 4133278429500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4134166021500. Starting simulation... +info: Entering event queue @ 4134278429500. Starting simulation... switching cpus -info: Entering event queue @ 4135165893500. Starting simulation... +info: Entering event queue @ 4135278301500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4136165893500. Starting simulation... +info: Entering event queue @ 4136278301500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4137165893500. Starting simulation... +info: Entering event queue @ 4137278301500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4138165893500. Starting simulation... +info: Entering event queue @ 4138278301500. Starting simulation... switching cpus -info: Entering event queue @ 4139165765500. Starting simulation... +info: Entering event queue @ 4139278173500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4140165765500. Starting simulation... +info: Entering event queue @ 4140278173500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4141165765500. Starting simulation... +info: Entering event queue @ 4141278173500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4142165765500. Starting simulation... +info: Entering event queue @ 4142278173500. Starting simulation... switching cpus -info: Entering event queue @ 4143165637500. Starting simulation... +info: Entering event queue @ 4143278045500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4144165637500. Starting simulation... +info: Entering event queue @ 4144278045500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4145165637500. Starting simulation... +info: Entering event queue @ 4145278045500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4146165637500. Starting simulation... +info: Entering event queue @ 4146278045500. Starting simulation... switching cpus -info: Entering event queue @ 4147165509500. Starting simulation... +info: Entering event queue @ 4147277917500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4148165509500. Starting simulation... +info: Entering event queue @ 4148277917500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4149165509500. Starting simulation... +info: Entering event queue @ 4149277917500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4150165509500. Starting simulation... +info: Entering event queue @ 4150277917500. Starting simulation... switching cpus -info: Entering event queue @ 4151165381500. Starting simulation... +info: Entering event queue @ 4151277789500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4152165381500. Starting simulation... +info: Entering event queue @ 4152277789500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4153165381500. Starting simulation... +info: Entering event queue @ 4153277789500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4154165381500. Starting simulation... +info: Entering event queue @ 4154277789500. Starting simulation... switching cpus -info: Entering event queue @ 4155165253500. Starting simulation... +info: Entering event queue @ 4155277661500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4156165253500. Starting simulation... +info: Entering event queue @ 4156277661500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4157165253500. Starting simulation... +info: Entering event queue @ 4157277661500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4158165253500. Starting simulation... +info: Entering event queue @ 4158277661500. Starting simulation... switching cpus -info: Entering event queue @ 4159165125500. Starting simulation... +info: Entering event queue @ 4159277533500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4160165125500. Starting simulation... +info: Entering event queue @ 4160277533500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4161165125500. Starting simulation... +info: Entering event queue @ 4161277533500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4162165125500. Starting simulation... +info: Entering event queue @ 4162277533500. Starting simulation... switching cpus -info: Entering event queue @ 4163164997500. Starting simulation... +info: Entering event queue @ 4163277405500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4164164997500. Starting simulation... +info: Entering event queue @ 4164277405500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4165164997500. Starting simulation... +info: Entering event queue @ 4165277405500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4166164997500. Starting simulation... +info: Entering event queue @ 4166277405500. Starting simulation... switching cpus -info: Entering event queue @ 4167164869500. Starting simulation... +info: Entering event queue @ 4167277277500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4168164869500. Starting simulation... +info: Entering event queue @ 4168277277500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4169164869500. Starting simulation... +info: Entering event queue @ 4169277277500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4170164869500. Starting simulation... +info: Entering event queue @ 4170277277500. Starting simulation... switching cpus -info: Entering event queue @ 4171164741500. Starting simulation... +info: Entering event queue @ 4171277149500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4172164741500. Starting simulation... +info: Entering event queue @ 4172277149500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4173164741500. Starting simulation... +info: Entering event queue @ 4173277149500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4174164741500. Starting simulation... +info: Entering event queue @ 4174277149500. Starting simulation... switching cpus -info: Entering event queue @ 4175164613500. Starting simulation... +info: Entering event queue @ 4175277021500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4176164613500. Starting simulation... +info: Entering event queue @ 4176277021500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4177164613500. Starting simulation... +info: Entering event queue @ 4177277021500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4178164613500. Starting simulation... +info: Entering event queue @ 4178277021500. Starting simulation... switching cpus -info: Entering event queue @ 4179164485500. Starting simulation... +info: Entering event queue @ 4179276893500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4180164485500. Starting simulation... +info: Entering event queue @ 4180276893500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4181164485500. Starting simulation... +info: Entering event queue @ 4181276893500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4182164485500. Starting simulation... +info: Entering event queue @ 4182276893500. Starting simulation... switching cpus -info: Entering event queue @ 4183164357500. Starting simulation... +info: Entering event queue @ 4183276765500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4184164357500. Starting simulation... +info: Entering event queue @ 4184276765500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4185164357500. Starting simulation... +info: Entering event queue @ 4185276765500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4186164357500. Starting simulation... +info: Entering event queue @ 4186276765500. Starting simulation... switching cpus -info: Entering event queue @ 4187164229500. Starting simulation... +info: Entering event queue @ 4187276637500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4188164229500. Starting simulation... +info: Entering event queue @ 4188276637500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4189164229500. Starting simulation... +info: Entering event queue @ 4189276637500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4190164229500. Starting simulation... +info: Entering event queue @ 4190276637500. Starting simulation... switching cpus -info: Entering event queue @ 4191164101500. Starting simulation... +info: Entering event queue @ 4191276509500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4192164101500. Starting simulation... +info: Entering event queue @ 4192276509500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4193164101500. Starting simulation... +info: Entering event queue @ 4193276509500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4194164101500. Starting simulation... +info: Entering event queue @ 4194276509500. Starting simulation... switching cpus -info: Entering event queue @ 4195163973500. Starting simulation... +info: Entering event queue @ 4195276381500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4196163973500. Starting simulation... +info: Entering event queue @ 4196276381500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4197163973500. Starting simulation... +info: Entering event queue @ 4197276381500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4198163973500. Starting simulation... +info: Entering event queue @ 4198276381500. Starting simulation... switching cpus -info: Entering event queue @ 4199163845500. Starting simulation... +info: Entering event queue @ 4199276253500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4200163845500. Starting simulation... +info: Entering event queue @ 4200276253500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4201163845500. Starting simulation... +info: Entering event queue @ 4201276253500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4202163845500. Starting simulation... +info: Entering event queue @ 4202276253500. Starting simulation... switching cpus -info: Entering event queue @ 4203163717500. Starting simulation... +info: Entering event queue @ 4203276125500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4204163717500. Starting simulation... +info: Entering event queue @ 4204276125500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4205163717500. Starting simulation... +info: Entering event queue @ 4205276125500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4206163717500. Starting simulation... +info: Entering event queue @ 4206276125500. Starting simulation... switching cpus -info: Entering event queue @ 4207163589500. Starting simulation... +info: Entering event queue @ 4207275997500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4208163589500. Starting simulation... +info: Entering event queue @ 4208275997500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4209163589500. Starting simulation... +info: Entering event queue @ 4209275997500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4210163589500. Starting simulation... +info: Entering event queue @ 4210275997500. Starting simulation... switching cpus -info: Entering event queue @ 4211163461500. Starting simulation... +info: Entering event queue @ 4211275869500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4212163461500. Starting simulation... +info: Entering event queue @ 4212275869500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4213163461500. Starting simulation... +info: Entering event queue @ 4213275869500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4214163461500. Starting simulation... +info: Entering event queue @ 4214275869500. Starting simulation... switching cpus -info: Entering event queue @ 4215163333500. Starting simulation... +info: Entering event queue @ 4215275741500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4216163333500. Starting simulation... +info: Entering event queue @ 4216275741500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4217163333500. Starting simulation... +info: Entering event queue @ 4217275741500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4218163333500. Starting simulation... +info: Entering event queue @ 4218275741500. Starting simulation... switching cpus -info: Entering event queue @ 4219163205500. Starting simulation... +info: Entering event queue @ 4219275613500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4220163205500. Starting simulation... +info: Entering event queue @ 4220275613500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4221163205500. Starting simulation... +info: Entering event queue @ 4221275613500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4222163205500. Starting simulation... +info: Entering event queue @ 4222275613500. Starting simulation... switching cpus -info: Entering event queue @ 4223163077500. Starting simulation... +info: Entering event queue @ 4223275485500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4224163077500. Starting simulation... +info: Entering event queue @ 4224275485500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4225163077500. Starting simulation... +info: Entering event queue @ 4225275485500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4226163077500. Starting simulation... +info: Entering event queue @ 4226275485500. Starting simulation... switching cpus -info: Entering event queue @ 4227162949500. Starting simulation... +info: Entering event queue @ 4227275357500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4228162949500. Starting simulation... +info: Entering event queue @ 4228275357500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4229162949500. Starting simulation... +info: Entering event queue @ 4229275357500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4230162949500. Starting simulation... +info: Entering event queue @ 4230275357500. Starting simulation... switching cpus -info: Entering event queue @ 4231162821500. Starting simulation... +info: Entering event queue @ 4231275229500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4232162821500. Starting simulation... +info: Entering event queue @ 4232275229500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4233162821500. Starting simulation... +info: Entering event queue @ 4233275229500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4234162821500. Starting simulation... +info: Entering event queue @ 4234275229500. Starting simulation... switching cpus -info: Entering event queue @ 4235162693500. Starting simulation... +info: Entering event queue @ 4235275101500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4236162693500. Starting simulation... +info: Entering event queue @ 4236275101500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4237162693500. Starting simulation... +info: Entering event queue @ 4237275101500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4238162693500. Starting simulation... +info: Entering event queue @ 4238275101500. Starting simulation... switching cpus -info: Entering event queue @ 4239162565500. Starting simulation... +info: Entering event queue @ 4239274973500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4240162565500. Starting simulation... +info: Entering event queue @ 4240274973500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4241162565500. Starting simulation... +info: Entering event queue @ 4241274973500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4242162565500. Starting simulation... +info: Entering event queue @ 4242274973500. Starting simulation... switching cpus -info: Entering event queue @ 4243162437500. Starting simulation... +info: Entering event queue @ 4243274845500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4244162437500. Starting simulation... +info: Entering event queue @ 4244274845500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4245162437500. Starting simulation... +info: Entering event queue @ 4245274845500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4246162437500. Starting simulation... +info: Entering event queue @ 4246274845500. Starting simulation... switching cpus -info: Entering event queue @ 4247162309500. Starting simulation... +info: Entering event queue @ 4247274717500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4248162309500. Starting simulation... +info: Entering event queue @ 4248274717500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4249162309500. Starting simulation... +info: Entering event queue @ 4249274717500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4250162309500. Starting simulation... +info: Entering event queue @ 4250274717500. Starting simulation... switching cpus -info: Entering event queue @ 4251162181500. Starting simulation... +info: Entering event queue @ 4251274589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4252162181500. Starting simulation... +info: Entering event queue @ 4252274589500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4253162181500. Starting simulation... +info: Entering event queue @ 4253274589500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4254162181500. Starting simulation... +info: Entering event queue @ 4254274589500. Starting simulation... switching cpus -info: Entering event queue @ 4255162053500. Starting simulation... +info: Entering event queue @ 4255274461500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4256162053500. Starting simulation... +info: Entering event queue @ 4256274461500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4257162053500. Starting simulation... +info: Entering event queue @ 4257274461500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4258162053500. Starting simulation... +info: Entering event queue @ 4258274461500. Starting simulation... switching cpus -info: Entering event queue @ 4259161925500. Starting simulation... +info: Entering event queue @ 4259274333500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4260161925500. Starting simulation... +info: Entering event queue @ 4260274333500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4261161925500. Starting simulation... +info: Entering event queue @ 4261274333500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4262161925500. Starting simulation... +info: Entering event queue @ 4262274333500. Starting simulation... switching cpus -info: Entering event queue @ 4263161797500. Starting simulation... +info: Entering event queue @ 4263274205500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4264161797500. Starting simulation... +info: Entering event queue @ 4264274205500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4265161797500. Starting simulation... +info: Entering event queue @ 4265274205500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4266161797500. Starting simulation... +info: Entering event queue @ 4266274205500. Starting simulation... switching cpus -info: Entering event queue @ 4267161669500. Starting simulation... +info: Entering event queue @ 4267274077500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4268161669500. Starting simulation... +info: Entering event queue @ 4268274077500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4269161669500. Starting simulation... +info: Entering event queue @ 4269274077500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4270161669500. Starting simulation... +info: Entering event queue @ 4270274077500. Starting simulation... switching cpus -info: Entering event queue @ 4271161541500. Starting simulation... +info: Entering event queue @ 4271273949500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4272161541500. Starting simulation... +info: Entering event queue @ 4272273949500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4273161541500. Starting simulation... +info: Entering event queue @ 4273273949500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4274161541500. Starting simulation... +info: Entering event queue @ 4274273949500. Starting simulation... switching cpus -info: Entering event queue @ 4275161413500. Starting simulation... +info: Entering event queue @ 4275273821500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4276161413500. Starting simulation... +info: Entering event queue @ 4276273821500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4277161413500. Starting simulation... +info: Entering event queue @ 4277273821500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4278161413500. Starting simulation... +info: Entering event queue @ 4278273821500. Starting simulation... switching cpus -info: Entering event queue @ 4279161285500. Starting simulation... +info: Entering event queue @ 4279273693500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4280161285500. Starting simulation... +info: Entering event queue @ 4280273693500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4281161285500. Starting simulation... +info: Entering event queue @ 4281273693500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4282161285500. Starting simulation... +info: Entering event queue @ 4282273693500. Starting simulation... switching cpus -info: Entering event queue @ 4283161157500. Starting simulation... +info: Entering event queue @ 4283273565500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4284161157500. Starting simulation... +info: Entering event queue @ 4284273565500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4285161157500. Starting simulation... +info: Entering event queue @ 4285273565500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4286161157500. Starting simulation... +info: Entering event queue @ 4286273565500. Starting simulation... switching cpus -info: Entering event queue @ 4287161029500. Starting simulation... +info: Entering event queue @ 4287273437500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4288161029500. Starting simulation... +info: Entering event queue @ 4288273437500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4289161029500. Starting simulation... +info: Entering event queue @ 4289273437500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4290161029500. Starting simulation... +info: Entering event queue @ 4290273437500. Starting simulation... switching cpus -info: Entering event queue @ 4291160901500. Starting simulation... +info: Entering event queue @ 4291273309500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4292160901500. Starting simulation... +info: Entering event queue @ 4292273309500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4293160901500. Starting simulation... +info: Entering event queue @ 4293273309500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4294160901500. Starting simulation... +info: Entering event queue @ 4294273309500. Starting simulation... switching cpus -info: Entering event queue @ 4295160773500. Starting simulation... +info: Entering event queue @ 4295273181500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4296160773500. Starting simulation... +info: Entering event queue @ 4296273181500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4297160773500. Starting simulation... +info: Entering event queue @ 4297273181500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4298160773500. Starting simulation... +info: Entering event queue @ 4298273181500. Starting simulation... switching cpus -info: Entering event queue @ 4299160645500. Starting simulation... +info: Entering event queue @ 4299273053500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4300160645500. Starting simulation... +info: Entering event queue @ 4300273053500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4301160645500. Starting simulation... +info: Entering event queue @ 4301273053500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4302160645500. Starting simulation... +info: Entering event queue @ 4302273053500. Starting simulation... switching cpus -info: Entering event queue @ 4303160517500. Starting simulation... +info: Entering event queue @ 4303272925500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4304160517500. Starting simulation... +info: Entering event queue @ 4304272925500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4305160517500. Starting simulation... +info: Entering event queue @ 4305272925500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4306160517500. Starting simulation... +info: Entering event queue @ 4306272925500. Starting simulation... switching cpus -info: Entering event queue @ 4307160389500. Starting simulation... +info: Entering event queue @ 4307272797500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4308160389500. Starting simulation... +info: Entering event queue @ 4308272797500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4309160389500. Starting simulation... +info: Entering event queue @ 4309272797500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4310160389500. Starting simulation... +info: Entering event queue @ 4310272797500. Starting simulation... switching cpus -info: Entering event queue @ 4311160261500. Starting simulation... +info: Entering event queue @ 4311272669500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4312160261500. Starting simulation... +info: Entering event queue @ 4312272669500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4313160261500. Starting simulation... +info: Entering event queue @ 4313272669500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4314160261500. Starting simulation... +info: Entering event queue @ 4314272669500. Starting simulation... switching cpus -info: Entering event queue @ 4315160133500. Starting simulation... +info: Entering event queue @ 4315272541500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4316160133500. Starting simulation... +info: Entering event queue @ 4316272541500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4317160133500. Starting simulation... +info: Entering event queue @ 4317272541500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4318160133500. Starting simulation... +info: Entering event queue @ 4318272541500. Starting simulation... switching cpus -info: Entering event queue @ 4319160005500. Starting simulation... +info: Entering event queue @ 4319272413500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4320160005500. Starting simulation... +info: Entering event queue @ 4320272413500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4321160005500. Starting simulation... +info: Entering event queue @ 4321272413500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4322160005500. Starting simulation... +info: Entering event queue @ 4322272413500. Starting simulation... switching cpus -info: Entering event queue @ 4323159877500. Starting simulation... +info: Entering event queue @ 4323272285500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4324159877500. Starting simulation... +info: Entering event queue @ 4324272285500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4325159877500. Starting simulation... +info: Entering event queue @ 4325272285500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4326159877500. Starting simulation... +info: Entering event queue @ 4326272285500. Starting simulation... switching cpus -info: Entering event queue @ 4327159749500. Starting simulation... +info: Entering event queue @ 4327272157500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4328159749500. Starting simulation... +info: Entering event queue @ 4328272157500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4329159749500. Starting simulation... +info: Entering event queue @ 4329272157500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4330159749500. Starting simulation... +info: Entering event queue @ 4330272157500. Starting simulation... switching cpus -info: Entering event queue @ 4331159621500. Starting simulation... +info: Entering event queue @ 4331272029500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4332159621500. Starting simulation... +info: Entering event queue @ 4332272029500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4333159621500. Starting simulation... +info: Entering event queue @ 4333272029500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4334159621500. Starting simulation... +info: Entering event queue @ 4334272029500. Starting simulation... switching cpus -info: Entering event queue @ 4335159493500. Starting simulation... +info: Entering event queue @ 4335271901500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4336159493500. Starting simulation... +info: Entering event queue @ 4336271901500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4337159493500. Starting simulation... +info: Entering event queue @ 4337271901500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4338159493500. Starting simulation... +info: Entering event queue @ 4338271901500. Starting simulation... switching cpus -info: Entering event queue @ 4339159365500. Starting simulation... +info: Entering event queue @ 4339271773500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4340159365500. Starting simulation... +info: Entering event queue @ 4340271773500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4341159365500. Starting simulation... +info: Entering event queue @ 4341271773500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4342159365500. Starting simulation... +info: Entering event queue @ 4342271773500. Starting simulation... switching cpus -info: Entering event queue @ 4343159237500. Starting simulation... +info: Entering event queue @ 4343271645500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4344159237500. Starting simulation... +info: Entering event queue @ 4344271645500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4345159237500. Starting simulation... +info: Entering event queue @ 4345271645500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4346159237500. Starting simulation... +info: Entering event queue @ 4346271645500. Starting simulation... switching cpus -info: Entering event queue @ 4347159109500. Starting simulation... +info: Entering event queue @ 4347271517500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4348159109500. Starting simulation... +info: Entering event queue @ 4348271517500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4349159109500. Starting simulation... +info: Entering event queue @ 4349271517500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4350159109500. Starting simulation... +info: Entering event queue @ 4350271517500. Starting simulation... switching cpus -info: Entering event queue @ 4351158981500. Starting simulation... +info: Entering event queue @ 4351271389500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4352158981500. Starting simulation... +info: Entering event queue @ 4352271389500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4353158981500. Starting simulation... +info: Entering event queue @ 4353271389500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4354158981500. Starting simulation... +info: Entering event queue @ 4354271389500. Starting simulation... switching cpus -info: Entering event queue @ 4355158853500. Starting simulation... +info: Entering event queue @ 4355271261500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4356158853500. Starting simulation... +info: Entering event queue @ 4356271261500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4357158853500. Starting simulation... +info: Entering event queue @ 4357271261500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4358158853500. Starting simulation... +info: Entering event queue @ 4358271261500. Starting simulation... switching cpus -info: Entering event queue @ 4359158725500. Starting simulation... +info: Entering event queue @ 4359271133500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4360158725500. Starting simulation... +info: Entering event queue @ 4360271133500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4361158725500. Starting simulation... +info: Entering event queue @ 4361271133500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4362158725500. Starting simulation... +info: Entering event queue @ 4362271133500. Starting simulation... switching cpus -info: Entering event queue @ 4363158597500. Starting simulation... +info: Entering event queue @ 4363271005500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4364158597500. Starting simulation... +info: Entering event queue @ 4364271005500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4365158597500. Starting simulation... +info: Entering event queue @ 4365271005500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4366158597500. Starting simulation... +info: Entering event queue @ 4366271005500. Starting simulation... switching cpus -info: Entering event queue @ 4367158469500. Starting simulation... +info: Entering event queue @ 4367270877500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4368158469500. Starting simulation... +info: Entering event queue @ 4368270877500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4369158469500. Starting simulation... +info: Entering event queue @ 4369270877500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4370158469500. Starting simulation... +info: Entering event queue @ 4370270877500. Starting simulation... switching cpus -info: Entering event queue @ 4371158341500. Starting simulation... +info: Entering event queue @ 4371270749500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4372158341500. Starting simulation... +info: Entering event queue @ 4372270749500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4373158341500. Starting simulation... +info: Entering event queue @ 4373270749500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4374158341500. Starting simulation... +info: Entering event queue @ 4374270749500. Starting simulation... switching cpus -info: Entering event queue @ 4375158213500. Starting simulation... +info: Entering event queue @ 4375270621500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4376158213500. Starting simulation... +info: Entering event queue @ 4376270621500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4377158213500. Starting simulation... +info: Entering event queue @ 4377270621500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4378158213500. Starting simulation... +info: Entering event queue @ 4378270621500. Starting simulation... switching cpus -info: Entering event queue @ 4379158085500. Starting simulation... +info: Entering event queue @ 4379270493500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4380158085500. Starting simulation... +info: Entering event queue @ 4380270493500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4381158085500. Starting simulation... +info: Entering event queue @ 4381270493500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4382158085500. Starting simulation... +info: Entering event queue @ 4382270493500. Starting simulation... switching cpus -info: Entering event queue @ 4383157957500. Starting simulation... +info: Entering event queue @ 4383270365500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4384157957500. Starting simulation... +info: Entering event queue @ 4384270365500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4385157957500. Starting simulation... +info: Entering event queue @ 4385270365500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4386157957500. Starting simulation... +info: Entering event queue @ 4386270365500. Starting simulation... switching cpus -info: Entering event queue @ 4387157829500. Starting simulation... +info: Entering event queue @ 4387270237500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4388157829500. Starting simulation... +info: Entering event queue @ 4388270237500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4389157829500. Starting simulation... +info: Entering event queue @ 4389270237500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4390157829500. Starting simulation... +info: Entering event queue @ 4390270237500. Starting simulation... switching cpus -info: Entering event queue @ 4391157701500. Starting simulation... +info: Entering event queue @ 4391270109500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4392157701500. Starting simulation... +info: Entering event queue @ 4392270109500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4393157701500. Starting simulation... +info: Entering event queue @ 4393270109500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4394157701500. Starting simulation... +info: Entering event queue @ 4394270109500. Starting simulation... switching cpus -info: Entering event queue @ 4395157573500. Starting simulation... +info: Entering event queue @ 4395269981500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4396157573500. Starting simulation... +info: Entering event queue @ 4396269981500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4397157573500. Starting simulation... +info: Entering event queue @ 4397269981500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4398157573500. Starting simulation... +info: Entering event queue @ 4398269981500. Starting simulation... switching cpus -info: Entering event queue @ 4399157445500. Starting simulation... +info: Entering event queue @ 4399269853500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4400157445500. Starting simulation... +info: Entering event queue @ 4400269853500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4401157445500. Starting simulation... +info: Entering event queue @ 4401269853500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4402157445500. Starting simulation... +info: Entering event queue @ 4402269853500. Starting simulation... switching cpus -info: Entering event queue @ 4403157317500. Starting simulation... +info: Entering event queue @ 4403269725500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4404157317500. Starting simulation... +info: Entering event queue @ 4404269725500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4405157317500. Starting simulation... +info: Entering event queue @ 4405269725500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4406157317500. Starting simulation... +info: Entering event queue @ 4406269725500. Starting simulation... switching cpus -info: Entering event queue @ 4407157189500. Starting simulation... +info: Entering event queue @ 4407269597500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4408157189500. Starting simulation... +info: Entering event queue @ 4408269597500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4409157189500. Starting simulation... +info: Entering event queue @ 4409269597500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4410157189500. Starting simulation... +info: Entering event queue @ 4410269597500. Starting simulation... switching cpus -info: Entering event queue @ 4411157061500. Starting simulation... +info: Entering event queue @ 4411269469500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4412157061500. Starting simulation... +info: Entering event queue @ 4412269469500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4413157061500. Starting simulation... +info: Entering event queue @ 4413269469500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4414157061500. Starting simulation... +info: Entering event queue @ 4414269469500. Starting simulation... switching cpus -info: Entering event queue @ 4415156933500. Starting simulation... +info: Entering event queue @ 4415269341500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4416156933500. Starting simulation... +info: Entering event queue @ 4416269341500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4417156933500. Starting simulation... +info: Entering event queue @ 4417269341500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4418156933500. Starting simulation... +info: Entering event queue @ 4418269341500. Starting simulation... switching cpus -info: Entering event queue @ 4419156805500. Starting simulation... +info: Entering event queue @ 4419269213500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4420156805500. Starting simulation... +info: Entering event queue @ 4420269213500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4421156805500. Starting simulation... +info: Entering event queue @ 4421269213500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4422156805500. Starting simulation... +info: Entering event queue @ 4422269213500. Starting simulation... switching cpus -info: Entering event queue @ 4423156677500. Starting simulation... +info: Entering event queue @ 4423269085500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4424156677500. Starting simulation... +info: Entering event queue @ 4424269085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4425156677500. Starting simulation... +info: Entering event queue @ 4425269085500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4426156677500. Starting simulation... +info: Entering event queue @ 4426269085500. Starting simulation... switching cpus -info: Entering event queue @ 4427156549500. Starting simulation... +info: Entering event queue @ 4427268957500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4428156549500. Starting simulation... +info: Entering event queue @ 4428268957500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4429156549500. Starting simulation... +info: Entering event queue @ 4429268957500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4430156549500. Starting simulation... +info: Entering event queue @ 4430268957500. Starting simulation... switching cpus -info: Entering event queue @ 4431156421500. Starting simulation... +info: Entering event queue @ 4431268829500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 4432156421500. Starting simulation... switching cpus -info: Entering event queue @ 4432156422500. Starting simulation... +info: Entering event queue @ 4432268829500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 4433156422500. Starting simulation... +info: Entering event queue @ 4433268829500. Starting simulation... switching cpus -info: Entering event queue @ 4433156423000. Starting simulation... +info: Entering event queue @ 4433268830000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4434156423000. Starting simulation... +info: Entering event queue @ 4434268830000. Starting simulation... switching cpus -info: Entering event queue @ 4434156427000. Starting simulation... +info: Entering event queue @ 4434268834000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4435156427000. Starting simulation... +info: Entering event queue @ 4435268834000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 4436156427000. Starting simulation... +info: Entering event queue @ 4436268834000. Starting simulation... switching cpus -info: Entering event queue @ 4436156428000. Starting simulation... +info: Entering event queue @ 4436268835000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4437156428000. Starting simulation... +info: Entering event queue @ 4437268835000. Starting simulation... switching cpus -info: Entering event queue @ 4437156432000. Starting simulation... +info: Entering event queue @ 4437268839000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4438156432000. Starting simulation... +info: Entering event queue @ 4438268839000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 4439156432000. Starting simulation... +info: Entering event queue @ 4439268839000. Starting simulation... switching cpus -info: Entering event queue @ 4439156432500. Starting simulation... +info: Entering event queue @ 4439268840500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4440156432500. Starting simulation... +info: Entering event queue @ 4440268840500. Starting simulation... switching cpus -info: Entering event queue @ 4440156440000. Starting simulation... +info: Entering event queue @ 4440268844500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4441156440000. Starting simulation... +info: Entering event queue @ 4441268844500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4442156440000. Starting simulation... +info: Entering event queue @ 4442268844500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4443156440000. Starting simulation... +info: Entering event queue @ 4443268844500. Starting simulation... switching cpus -info: Entering event queue @ 4443156443500. Starting simulation... +info: Entering event queue @ 4443268849000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4444156443500. Starting simulation... +info: Entering event queue @ 4444268849000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4445156443500. Starting simulation... +info: Entering event queue @ 4445268849000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4446156443500. Starting simulation... +info: Entering event queue @ 4446268849000. Starting simulation... switching cpus -info: Entering event queue @ 4447155909500. Starting simulation... +info: Entering event queue @ 4447268317500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4448155909500. Starting simulation... +info: Entering event queue @ 4448268317500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4449155909500. Starting simulation... +info: Entering event queue @ 4449268317500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4450155909500. Starting simulation... +info: Entering event queue @ 4450268317500. Starting simulation... switching cpus -info: Entering event queue @ 4451155781500. Starting simulation... +info: Entering event queue @ 4451268189500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4452155781500. Starting simulation... +info: Entering event queue @ 4452268189500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4453155781500. Starting simulation... +info: Entering event queue @ 4453268189500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4454155781500. Starting simulation... +info: Entering event queue @ 4454268189500. Starting simulation... switching cpus -info: Entering event queue @ 4455155653500. Starting simulation... +info: Entering event queue @ 4455268061500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4456155653500. Starting simulation... +info: Entering event queue @ 4456268061500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4457155653500. Starting simulation... +info: Entering event queue @ 4457268061500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4458155653500. Starting simulation... +info: Entering event queue @ 4458268061500. Starting simulation... switching cpus -info: Entering event queue @ 4459155525500. Starting simulation... +info: Entering event queue @ 4459267933500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4460155525500. Starting simulation... +info: Entering event queue @ 4460267933500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4461155525500. Starting simulation... +info: Entering event queue @ 4461267933500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4462155525500. Starting simulation... +info: Entering event queue @ 4462267933500. Starting simulation... switching cpus -info: Entering event queue @ 4463155397500. Starting simulation... +info: Entering event queue @ 4463267805500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4464155397500. Starting simulation... +info: Entering event queue @ 4464267805500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4465155397500. Starting simulation... +info: Entering event queue @ 4465267805500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4466155397500. Starting simulation... +info: Entering event queue @ 4466267805500. Starting simulation... switching cpus -info: Entering event queue @ 4467155269500. Starting simulation... +info: Entering event queue @ 4467267677500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4468155269500. Starting simulation... +info: Entering event queue @ 4468267677500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4469155269500. Starting simulation... +info: Entering event queue @ 4469267677500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4470155269500. Starting simulation... +info: Entering event queue @ 4470267677500. Starting simulation... switching cpus -info: Entering event queue @ 4471155141500. Starting simulation... +info: Entering event queue @ 4471267549500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4472155141500. Starting simulation... +info: Entering event queue @ 4472267549500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4473155141500. Starting simulation... +info: Entering event queue @ 4473267549500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4474155141500. Starting simulation... +info: Entering event queue @ 4474267549500. Starting simulation... switching cpus -info: Entering event queue @ 4475155013500. Starting simulation... +info: Entering event queue @ 4475267421500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4476155013500. Starting simulation... +info: Entering event queue @ 4476267421500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4477155013500. Starting simulation... +info: Entering event queue @ 4477267421500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4478155013500. Starting simulation... +info: Entering event queue @ 4478267421500. Starting simulation... switching cpus -info: Entering event queue @ 4479154885500. Starting simulation... +info: Entering event queue @ 4479267293500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4480154885500. Starting simulation... +info: Entering event queue @ 4480267293500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4481154885500. Starting simulation... +info: Entering event queue @ 4481267293500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4482154885500. Starting simulation... +info: Entering event queue @ 4482267293500. Starting simulation... switching cpus -info: Entering event queue @ 4483154757500. Starting simulation... +info: Entering event queue @ 4483267165500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4484154757500. Starting simulation... +info: Entering event queue @ 4484267165500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4485154757500. Starting simulation... +info: Entering event queue @ 4485267165500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4486154757500. Starting simulation... +info: Entering event queue @ 4486267165500. Starting simulation... switching cpus -info: Entering event queue @ 4487154629500. Starting simulation... +info: Entering event queue @ 4487267037500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4488154629500. Starting simulation... +info: Entering event queue @ 4488267037500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4489154629500. Starting simulation... +info: Entering event queue @ 4489267037500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4490154629500. Starting simulation... +info: Entering event queue @ 4490267037500. Starting simulation... switching cpus -info: Entering event queue @ 4491154501500. Starting simulation... +info: Entering event queue @ 4491266909500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4492154501500. Starting simulation... +info: Entering event queue @ 4492266909500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4493154501500. Starting simulation... +info: Entering event queue @ 4493266909500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4494154501500. Starting simulation... +info: Entering event queue @ 4494266909500. Starting simulation... switching cpus -info: Entering event queue @ 4495154373500. Starting simulation... +info: Entering event queue @ 4495266781500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4496154373500. Starting simulation... +info: Entering event queue @ 4496266781500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4497154373500. Starting simulation... +info: Entering event queue @ 4497266781500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4498154373500. Starting simulation... +info: Entering event queue @ 4498266781500. Starting simulation... switching cpus -info: Entering event queue @ 4499154245500. Starting simulation... +info: Entering event queue @ 4499266653500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4500154245500. Starting simulation... +info: Entering event queue @ 4500266653500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4501154245500. Starting simulation... +info: Entering event queue @ 4501266653500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4502154245500. Starting simulation... +info: Entering event queue @ 4502266653500. Starting simulation... switching cpus -info: Entering event queue @ 4503154117500. Starting simulation... +info: Entering event queue @ 4503266525500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4504154117500. Starting simulation... +info: Entering event queue @ 4504266525500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4505154117500. Starting simulation... +info: Entering event queue @ 4505266525500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4506154117500. Starting simulation... +info: Entering event queue @ 4506266525500. Starting simulation... switching cpus -info: Entering event queue @ 4507153989500. Starting simulation... +info: Entering event queue @ 4507266397500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4508153989500. Starting simulation... +info: Entering event queue @ 4508266397500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4509153989500. Starting simulation... +info: Entering event queue @ 4509266397500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4510153989500. Starting simulation... +info: Entering event queue @ 4510266397500. Starting simulation... switching cpus -info: Entering event queue @ 4511153861500. Starting simulation... +info: Entering event queue @ 4511266269500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4512153861500. Starting simulation... +info: Entering event queue @ 4512266269500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4513153861500. Starting simulation... +info: Entering event queue @ 4513266269500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4514153861500. Starting simulation... +info: Entering event queue @ 4514266269500. Starting simulation... switching cpus -info: Entering event queue @ 4515153733500. Starting simulation... +info: Entering event queue @ 4515266141500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4516153733500. Starting simulation... +info: Entering event queue @ 4516266141500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4517153733500. Starting simulation... +info: Entering event queue @ 4517266141500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4518153733500. Starting simulation... +info: Entering event queue @ 4518266141500. Starting simulation... switching cpus -info: Entering event queue @ 4519153605500. Starting simulation... +info: Entering event queue @ 4519266013500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4520153605500. Starting simulation... +info: Entering event queue @ 4520266013500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4521153605500. Starting simulation... +info: Entering event queue @ 4521266013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4522153605500. Starting simulation... +info: Entering event queue @ 4522266013500. Starting simulation... switching cpus -info: Entering event queue @ 4523153477500. Starting simulation... +info: Entering event queue @ 4523265885500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4524153477500. Starting simulation... +info: Entering event queue @ 4524265885500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4525153477500. Starting simulation... +info: Entering event queue @ 4525265885500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4526153477500. Starting simulation... +info: Entering event queue @ 4526265885500. Starting simulation... switching cpus -info: Entering event queue @ 4527153349500. Starting simulation... +info: Entering event queue @ 4527265757500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4528153349500. Starting simulation... +info: Entering event queue @ 4528265757500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4529153349500. Starting simulation... +info: Entering event queue @ 4529265757500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4530153349500. Starting simulation... +info: Entering event queue @ 4530265757500. Starting simulation... switching cpus -info: Entering event queue @ 4531153221500. Starting simulation... +info: Entering event queue @ 4531265629500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4532153221500. Starting simulation... +info: Entering event queue @ 4532265629500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4533153221500. Starting simulation... +info: Entering event queue @ 4533265629500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4534153221500. Starting simulation... +info: Entering event queue @ 4534265629500. Starting simulation... switching cpus -info: Entering event queue @ 4535153093500. Starting simulation... +info: Entering event queue @ 4535265501500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4536153093500. Starting simulation... +info: Entering event queue @ 4536265501500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4537153093500. Starting simulation... +info: Entering event queue @ 4537265501500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4538153093500. Starting simulation... +info: Entering event queue @ 4538265501500. Starting simulation... switching cpus -info: Entering event queue @ 4539152965500. Starting simulation... +info: Entering event queue @ 4539265373500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4540152965500. Starting simulation... +info: Entering event queue @ 4540265373500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4541152965500. Starting simulation... +info: Entering event queue @ 4541265373500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4542152965500. Starting simulation... +info: Entering event queue @ 4542265373500. Starting simulation... switching cpus -info: Entering event queue @ 4543152837500. Starting simulation... +info: Entering event queue @ 4543265245500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4544152837500. Starting simulation... +info: Entering event queue @ 4544265245500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4545152837500. Starting simulation... +info: Entering event queue @ 4545265245500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4546152837500. Starting simulation... +info: Entering event queue @ 4546265245500. Starting simulation... switching cpus -info: Entering event queue @ 4547152709500. Starting simulation... +info: Entering event queue @ 4547265117500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4548152709500. Starting simulation... +info: Entering event queue @ 4548265117500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4549152709500. Starting simulation... +info: Entering event queue @ 4549265117500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4550152709500. Starting simulation... +info: Entering event queue @ 4550265117500. Starting simulation... switching cpus -info: Entering event queue @ 4551152581500. Starting simulation... +info: Entering event queue @ 4551264989500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4552152581500. Starting simulation... +info: Entering event queue @ 4552264989500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4553152581500. Starting simulation... +info: Entering event queue @ 4553264989500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4554152581500. Starting simulation... +info: Entering event queue @ 4554264989500. Starting simulation... switching cpus -info: Entering event queue @ 4555152453500. Starting simulation... +info: Entering event queue @ 4555264861500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4556152453500. Starting simulation... +info: Entering event queue @ 4556264861500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4557152453500. Starting simulation... +info: Entering event queue @ 4557264861500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4558152453500. Starting simulation... +info: Entering event queue @ 4558264861500. Starting simulation... switching cpus -info: Entering event queue @ 4559152325500. Starting simulation... +info: Entering event queue @ 4559264733500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4560152325500. Starting simulation... +info: Entering event queue @ 4560264733500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4561152325500. Starting simulation... +info: Entering event queue @ 4561264733500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4562152325500. Starting simulation... +info: Entering event queue @ 4562264733500. Starting simulation... switching cpus -info: Entering event queue @ 4563152197500. Starting simulation... +info: Entering event queue @ 4563264605500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4564152197500. Starting simulation... +info: Entering event queue @ 4564264605500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4565152197500. Starting simulation... +info: Entering event queue @ 4565264605500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4566152197500. Starting simulation... +info: Entering event queue @ 4566264605500. Starting simulation... switching cpus -info: Entering event queue @ 4567152069500. Starting simulation... +info: Entering event queue @ 4567264477500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4568152069500. Starting simulation... +info: Entering event queue @ 4568264477500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4569152069500. Starting simulation... +info: Entering event queue @ 4569264477500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4570152069500. Starting simulation... +info: Entering event queue @ 4570264477500. Starting simulation... switching cpus -info: Entering event queue @ 4571151941500. Starting simulation... +info: Entering event queue @ 4571264349500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4572151941500. Starting simulation... +info: Entering event queue @ 4572264349500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4573151941500. Starting simulation... +info: Entering event queue @ 4573264349500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4574151941500. Starting simulation... +info: Entering event queue @ 4574264349500. Starting simulation... switching cpus -info: Entering event queue @ 4575151813500. Starting simulation... +info: Entering event queue @ 4575264221500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4576151813500. Starting simulation... +info: Entering event queue @ 4576264221500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4577151813500. Starting simulation... +info: Entering event queue @ 4577264221500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4578151813500. Starting simulation... +info: Entering event queue @ 4578264221500. Starting simulation... switching cpus -info: Entering event queue @ 4579151685500. Starting simulation... +info: Entering event queue @ 4579264093500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4580151685500. Starting simulation... +info: Entering event queue @ 4580264093500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4581151685500. Starting simulation... +info: Entering event queue @ 4581264093500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4582151685500. Starting simulation... +info: Entering event queue @ 4582264093500. Starting simulation... switching cpus -info: Entering event queue @ 4583151557500. Starting simulation... +info: Entering event queue @ 4583263965500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4584151557500. Starting simulation... +info: Entering event queue @ 4584263965500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4585151557500. Starting simulation... +info: Entering event queue @ 4585263965500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4586151557500. Starting simulation... +info: Entering event queue @ 4586263965500. Starting simulation... switching cpus -info: Entering event queue @ 4587151429500. Starting simulation... +info: Entering event queue @ 4587263837500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4588151429500. Starting simulation... +info: Entering event queue @ 4588263837500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4589151429500. Starting simulation... +info: Entering event queue @ 4589263837500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4590151429500. Starting simulation... +info: Entering event queue @ 4590263837500. Starting simulation... switching cpus -info: Entering event queue @ 4591151301500. Starting simulation... +info: Entering event queue @ 4591263709500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4592151301500. Starting simulation... +info: Entering event queue @ 4592263709500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4593151301500. Starting simulation... +info: Entering event queue @ 4593263709500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4594151301500. Starting simulation... +info: Entering event queue @ 4594263709500. Starting simulation... switching cpus -info: Entering event queue @ 4595151173500. Starting simulation... +info: Entering event queue @ 4595263581500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4596151173500. Starting simulation... +info: Entering event queue @ 4596263581500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4597151173500. Starting simulation... +info: Entering event queue @ 4597263581500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4598151173500. Starting simulation... +info: Entering event queue @ 4598263581500. Starting simulation... switching cpus -info: Entering event queue @ 4599151045500. Starting simulation... +info: Entering event queue @ 4599263453500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4600151045500. Starting simulation... +info: Entering event queue @ 4600263453500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4601151045500. Starting simulation... +info: Entering event queue @ 4601263453500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4602151045500. Starting simulation... +info: Entering event queue @ 4602263453500. Starting simulation... switching cpus -info: Entering event queue @ 4603150917500. Starting simulation... +info: Entering event queue @ 4603263325500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4604150917500. Starting simulation... +info: Entering event queue @ 4604263325500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4605150917500. Starting simulation... +info: Entering event queue @ 4605263325500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4606150917500. Starting simulation... +info: Entering event queue @ 4606263325500. Starting simulation... switching cpus -info: Entering event queue @ 4607150789500. Starting simulation... +info: Entering event queue @ 4607263197500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4608150789500. Starting simulation... +info: Entering event queue @ 4608263197500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4609150789500. Starting simulation... +info: Entering event queue @ 4609263197500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4610150789500. Starting simulation... +info: Entering event queue @ 4610263197500. Starting simulation... switching cpus -info: Entering event queue @ 4611150661500. Starting simulation... +info: Entering event queue @ 4611263069500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4612150661500. Starting simulation... +info: Entering event queue @ 4612263069500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4613150661500. Starting simulation... +info: Entering event queue @ 4613263069500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4614150661500. Starting simulation... +info: Entering event queue @ 4614263069500. Starting simulation... switching cpus -info: Entering event queue @ 4615150533500. Starting simulation... +info: Entering event queue @ 4615262941500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4616150533500. Starting simulation... +info: Entering event queue @ 4616262941500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4617150533500. Starting simulation... +info: Entering event queue @ 4617262941500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4618150533500. Starting simulation... +info: Entering event queue @ 4618262941500. Starting simulation... switching cpus -info: Entering event queue @ 4619150405500. Starting simulation... +info: Entering event queue @ 4619262813500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4620150405500. Starting simulation... +info: Entering event queue @ 4620262813500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4621150405500. Starting simulation... +info: Entering event queue @ 4621262813500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4622150405500. Starting simulation... +info: Entering event queue @ 4622262813500. Starting simulation... switching cpus -info: Entering event queue @ 4623150277500. Starting simulation... +info: Entering event queue @ 4623262685500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4624150277500. Starting simulation... +info: Entering event queue @ 4624262685500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4625150277500. Starting simulation... +info: Entering event queue @ 4625262685500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4626150277500. Starting simulation... +info: Entering event queue @ 4626262685500. Starting simulation... switching cpus -info: Entering event queue @ 4627150149500. Starting simulation... +info: Entering event queue @ 4627262557500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4628150149500. Starting simulation... +info: Entering event queue @ 4628262557500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4629150149500. Starting simulation... +info: Entering event queue @ 4629262557500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4630150149500. Starting simulation... +info: Entering event queue @ 4630262557500. Starting simulation... switching cpus -info: Entering event queue @ 4631150021500. Starting simulation... +info: Entering event queue @ 4631262429500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4632150021500. Starting simulation... +info: Entering event queue @ 4632262429500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4633150021500. Starting simulation... +info: Entering event queue @ 4633262429500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4634150021500. Starting simulation... +info: Entering event queue @ 4634262429500. Starting simulation... switching cpus -info: Entering event queue @ 4635149893500. Starting simulation... +info: Entering event queue @ 4635262301500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4636149893500. Starting simulation... +info: Entering event queue @ 4636262301500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4637149893500. Starting simulation... +info: Entering event queue @ 4637262301500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4638149893500. Starting simulation... +info: Entering event queue @ 4638262301500. Starting simulation... switching cpus -info: Entering event queue @ 4639149765500. Starting simulation... +info: Entering event queue @ 4639262173500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4640149765500. Starting simulation... +info: Entering event queue @ 4640262173500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4641149765500. Starting simulation... +info: Entering event queue @ 4641262173500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4642149765500. Starting simulation... +info: Entering event queue @ 4642262173500. Starting simulation... switching cpus -info: Entering event queue @ 4643149637500. Starting simulation... +info: Entering event queue @ 4643262045500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4644149637500. Starting simulation... +info: Entering event queue @ 4644262045500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4645149637500. Starting simulation... +info: Entering event queue @ 4645262045500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4646149637500. Starting simulation... +info: Entering event queue @ 4646262045500. Starting simulation... switching cpus -info: Entering event queue @ 4647149509500. Starting simulation... +info: Entering event queue @ 4647261917500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4648149509500. Starting simulation... +info: Entering event queue @ 4648261917500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4649149509500. Starting simulation... +info: Entering event queue @ 4649261917500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4650149509500. Starting simulation... +info: Entering event queue @ 4650261917500. Starting simulation... switching cpus -info: Entering event queue @ 4651149381500. Starting simulation... +info: Entering event queue @ 4651261789500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4652149381500. Starting simulation... +info: Entering event queue @ 4652261789500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4653149381500. Starting simulation... +info: Entering event queue @ 4653261789500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4654149381500. Starting simulation... +info: Entering event queue @ 4654261789500. Starting simulation... switching cpus -info: Entering event queue @ 4655149253500. Starting simulation... +info: Entering event queue @ 4655261661500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4656149253500. Starting simulation... +info: Entering event queue @ 4656261661500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4657149253500. Starting simulation... +info: Entering event queue @ 4657261661500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4658149253500. Starting simulation... +info: Entering event queue @ 4658261661500. Starting simulation... switching cpus -info: Entering event queue @ 4659149125500. Starting simulation... +info: Entering event queue @ 4659261533500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4660149125500. Starting simulation... +info: Entering event queue @ 4660261533500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4661149125500. Starting simulation... +info: Entering event queue @ 4661261533500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4662149125500. Starting simulation... +info: Entering event queue @ 4662261533500. Starting simulation... switching cpus -info: Entering event queue @ 4663148997500. Starting simulation... +info: Entering event queue @ 4663261405500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4664148997500. Starting simulation... +info: Entering event queue @ 4664261405500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4665148997500. Starting simulation... +info: Entering event queue @ 4665261405500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4666148997500. Starting simulation... +info: Entering event queue @ 4666261405500. Starting simulation... switching cpus -info: Entering event queue @ 4667148869500. Starting simulation... +info: Entering event queue @ 4667261277500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4668148869500. Starting simulation... +info: Entering event queue @ 4668261277500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4669148869500. Starting simulation... +info: Entering event queue @ 4669261277500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4670148869500. Starting simulation... +info: Entering event queue @ 4670261277500. Starting simulation... switching cpus -info: Entering event queue @ 4671148741500. Starting simulation... +info: Entering event queue @ 4671261149500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4672148741500. Starting simulation... +info: Entering event queue @ 4672261149500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4673148741500. Starting simulation... +info: Entering event queue @ 4673261149500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4674148741500. Starting simulation... +info: Entering event queue @ 4674261149500. Starting simulation... switching cpus -info: Entering event queue @ 4675148613500. Starting simulation... +info: Entering event queue @ 4675261021500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4676148613500. Starting simulation... +info: Entering event queue @ 4676261021500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4677148613500. Starting simulation... +info: Entering event queue @ 4677261021500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4678148613500. Starting simulation... +info: Entering event queue @ 4678261021500. Starting simulation... switching cpus -info: Entering event queue @ 4679148485500. Starting simulation... +info: Entering event queue @ 4679260893500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4680148485500. Starting simulation... +info: Entering event queue @ 4680260893500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4681148485500. Starting simulation... +info: Entering event queue @ 4681260893500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4682148485500. Starting simulation... +info: Entering event queue @ 4682260893500. Starting simulation... switching cpus -info: Entering event queue @ 4683148357500. Starting simulation... +info: Entering event queue @ 4683260765500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4684148357500. Starting simulation... +info: Entering event queue @ 4684260765500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4685148357500. Starting simulation... +info: Entering event queue @ 4685260765500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4686148357500. Starting simulation... +info: Entering event queue @ 4686260765500. Starting simulation... switching cpus -info: Entering event queue @ 4687148229500. Starting simulation... +info: Entering event queue @ 4687260637500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4688148229500. Starting simulation... +info: Entering event queue @ 4688260637500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4689148229500. Starting simulation... +info: Entering event queue @ 4689260637500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4690148229500. Starting simulation... +info: Entering event queue @ 4690260637500. Starting simulation... switching cpus -info: Entering event queue @ 4691148101500. Starting simulation... +info: Entering event queue @ 4691260509500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4692148101500. Starting simulation... +info: Entering event queue @ 4692260509500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4693148101500. Starting simulation... +info: Entering event queue @ 4693260509500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4694148101500. Starting simulation... +info: Entering event queue @ 4694260509500. Starting simulation... switching cpus -info: Entering event queue @ 4695147973500. Starting simulation... +info: Entering event queue @ 4695260381500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4696147973500. Starting simulation... +info: Entering event queue @ 4696260381500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4697147973500. Starting simulation... +info: Entering event queue @ 4697260381500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4698147973500. Starting simulation... +info: Entering event queue @ 4698260381500. Starting simulation... switching cpus -info: Entering event queue @ 4699147845500. Starting simulation... +info: Entering event queue @ 4699260253500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4700147845500. Starting simulation... +info: Entering event queue @ 4700260253500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4701147845500. Starting simulation... +info: Entering event queue @ 4701260253500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4702147845500. Starting simulation... +info: Entering event queue @ 4702260253500. Starting simulation... switching cpus -info: Entering event queue @ 4703147717500. Starting simulation... +info: Entering event queue @ 4703260125500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4704147717500. Starting simulation... +info: Entering event queue @ 4704260125500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4705147717500. Starting simulation... +info: Entering event queue @ 4705260125500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4706147717500. Starting simulation... +info: Entering event queue @ 4706260125500. Starting simulation... switching cpus -info: Entering event queue @ 4707147589500. Starting simulation... +info: Entering event queue @ 4707259997500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4708147589500. Starting simulation... +info: Entering event queue @ 4708259997500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4709147589500. Starting simulation... +info: Entering event queue @ 4709259997500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4710147589500. Starting simulation... +info: Entering event queue @ 4710259997500. Starting simulation... switching cpus -info: Entering event queue @ 4711147461500. Starting simulation... +info: Entering event queue @ 4711259869500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4712147461500. Starting simulation... +info: Entering event queue @ 4712259869500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4713147461500. Starting simulation... +info: Entering event queue @ 4713259869500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4714147461500. Starting simulation... +info: Entering event queue @ 4714259869500. Starting simulation... switching cpus -info: Entering event queue @ 4715147333500. Starting simulation... +info: Entering event queue @ 4715259741500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4716147333500. Starting simulation... +info: Entering event queue @ 4716259741500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4717147333500. Starting simulation... +info: Entering event queue @ 4717259741500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4718147333500. Starting simulation... +info: Entering event queue @ 4718259741500. Starting simulation... switching cpus -info: Entering event queue @ 4719147205500. Starting simulation... +info: Entering event queue @ 4719259613500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4720147205500. Starting simulation... +info: Entering event queue @ 4720259613500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4721147205500. Starting simulation... +info: Entering event queue @ 4721259613500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4722147205500. Starting simulation... +info: Entering event queue @ 4722259613500. Starting simulation... switching cpus -info: Entering event queue @ 4723147077500. Starting simulation... +info: Entering event queue @ 4723259485500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4724147077500. Starting simulation... +info: Entering event queue @ 4724259485500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4725147077500. Starting simulation... +info: Entering event queue @ 4725259485500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4726147077500. Starting simulation... +info: Entering event queue @ 4726259485500. Starting simulation... switching cpus -info: Entering event queue @ 4727146949500. Starting simulation... +info: Entering event queue @ 4727259357500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4728146949500. Starting simulation... +info: Entering event queue @ 4728259357500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4729146949500. Starting simulation... +info: Entering event queue @ 4729259357500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4730146949500. Starting simulation... +info: Entering event queue @ 4730259357500. Starting simulation... switching cpus -info: Entering event queue @ 4731146821500. Starting simulation... +info: Entering event queue @ 4731259229500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4732146821500. Starting simulation... +info: Entering event queue @ 4732259229500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4733146821500. Starting simulation... +info: Entering event queue @ 4733259229500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4734146821500. Starting simulation... +info: Entering event queue @ 4734259229500. Starting simulation... switching cpus -info: Entering event queue @ 4735146693500. Starting simulation... +info: Entering event queue @ 4735259101500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4736146693500. Starting simulation... +info: Entering event queue @ 4736259101500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4737146693500. Starting simulation... +info: Entering event queue @ 4737259101500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4738146693500. Starting simulation... +info: Entering event queue @ 4738259101500. Starting simulation... switching cpus -info: Entering event queue @ 4739146565500. Starting simulation... +info: Entering event queue @ 4739258973500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4740146565500. Starting simulation... +info: Entering event queue @ 4740258973500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4741146565500. Starting simulation... +info: Entering event queue @ 4741258973500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4742146565500. Starting simulation... +info: Entering event queue @ 4742258973500. Starting simulation... switching cpus -info: Entering event queue @ 4743146437500. Starting simulation... +info: Entering event queue @ 4743258845500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4744146437500. Starting simulation... +info: Entering event queue @ 4744258845500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4745146437500. Starting simulation... +info: Entering event queue @ 4745258845500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4746146437500. Starting simulation... +info: Entering event queue @ 4746258845500. Starting simulation... switching cpus -info: Entering event queue @ 4747146309500. Starting simulation... +info: Entering event queue @ 4747258717500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4748146309500. Starting simulation... +info: Entering event queue @ 4748258717500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4749146309500. Starting simulation... +info: Entering event queue @ 4749258717500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4750146309500. Starting simulation... +info: Entering event queue @ 4750258717500. Starting simulation... switching cpus -info: Entering event queue @ 4751146181500. Starting simulation... +info: Entering event queue @ 4751258589500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4752146181500. Starting simulation... +info: Entering event queue @ 4752258589500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4753146181500. Starting simulation... +info: Entering event queue @ 4753258589500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4754146181500. Starting simulation... +info: Entering event queue @ 4754258589500. Starting simulation... switching cpus -info: Entering event queue @ 4755146053500. Starting simulation... +info: Entering event queue @ 4755258461500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4756146053500. Starting simulation... +info: Entering event queue @ 4756258461500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4757146053500. Starting simulation... +info: Entering event queue @ 4757258461500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4758146053500. Starting simulation... +info: Entering event queue @ 4758258461500. Starting simulation... switching cpus -info: Entering event queue @ 4759145925500. Starting simulation... +info: Entering event queue @ 4759258333500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4760145925500. Starting simulation... +info: Entering event queue @ 4760258333500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4761145925500. Starting simulation... +info: Entering event queue @ 4761258333500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4762145925500. Starting simulation... +info: Entering event queue @ 4762258333500. Starting simulation... switching cpus -info: Entering event queue @ 4763145797500. Starting simulation... +info: Entering event queue @ 4763258205500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4764145797500. Starting simulation... +info: Entering event queue @ 4764258205500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4765145797500. Starting simulation... +info: Entering event queue @ 4765258205500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4766145797500. Starting simulation... +info: Entering event queue @ 4766258205500. Starting simulation... switching cpus -info: Entering event queue @ 4767145669500. Starting simulation... +info: Entering event queue @ 4767258077500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4768145669500. Starting simulation... +info: Entering event queue @ 4768258077500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4769145669500. Starting simulation... +info: Entering event queue @ 4769258077500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4770145669500. Starting simulation... +info: Entering event queue @ 4770258077500. Starting simulation... switching cpus -info: Entering event queue @ 4771145541500. Starting simulation... +info: Entering event queue @ 4771257949500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4772145541500. Starting simulation... +info: Entering event queue @ 4772257949500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4773145541500. Starting simulation... +info: Entering event queue @ 4773257949500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4774145541500. Starting simulation... +info: Entering event queue @ 4774257949500. Starting simulation... switching cpus -info: Entering event queue @ 4775145413500. Starting simulation... +info: Entering event queue @ 4775257821500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4776145413500. Starting simulation... +info: Entering event queue @ 4776257821500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4777145413500. Starting simulation... +info: Entering event queue @ 4777257821500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4778145413500. Starting simulation... +info: Entering event queue @ 4778257821500. Starting simulation... switching cpus -info: Entering event queue @ 4779145285500. Starting simulation... +info: Entering event queue @ 4779257693500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4780145285500. Starting simulation... +info: Entering event queue @ 4780257693500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4781145285500. Starting simulation... +info: Entering event queue @ 4781257693500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4782145285500. Starting simulation... +info: Entering event queue @ 4782257693500. Starting simulation... switching cpus -info: Entering event queue @ 4783145157500. Starting simulation... +info: Entering event queue @ 4783257565500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4784145157500. Starting simulation... +info: Entering event queue @ 4784257565500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4785145157500. Starting simulation... +info: Entering event queue @ 4785257565500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4786145157500. Starting simulation... +info: Entering event queue @ 4786257565500. Starting simulation... switching cpus -info: Entering event queue @ 4787145029500. Starting simulation... +info: Entering event queue @ 4787257437500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4788145029500. Starting simulation... +info: Entering event queue @ 4788257437500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4789145029500. Starting simulation... +info: Entering event queue @ 4789257437500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4790145029500. Starting simulation... +info: Entering event queue @ 4790257437500. Starting simulation... switching cpus -info: Entering event queue @ 4791144901500. Starting simulation... +info: Entering event queue @ 4791257309500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4792144901500. Starting simulation... +info: Entering event queue @ 4792257309500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4793144901500. Starting simulation... +info: Entering event queue @ 4793257309500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4794144901500. Starting simulation... +info: Entering event queue @ 4794257309500. Starting simulation... switching cpus -info: Entering event queue @ 4795144773500. Starting simulation... +info: Entering event queue @ 4795257181500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4796144773500. Starting simulation... +info: Entering event queue @ 4796257181500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4797144773500. Starting simulation... +info: Entering event queue @ 4797257181500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4798144773500. Starting simulation... +info: Entering event queue @ 4798257181500. Starting simulation... switching cpus -info: Entering event queue @ 4799144645500. Starting simulation... +info: Entering event queue @ 4799257053500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4800144645500. Starting simulation... +info: Entering event queue @ 4800257053500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4801144645500. Starting simulation... +info: Entering event queue @ 4801257053500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4802144645500. Starting simulation... +info: Entering event queue @ 4802257053500. Starting simulation... switching cpus -info: Entering event queue @ 4803144517500. Starting simulation... +info: Entering event queue @ 4803256925500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4804144517500. Starting simulation... +info: Entering event queue @ 4804256925500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4805144517500. Starting simulation... +info: Entering event queue @ 4805256925500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4806144517500. Starting simulation... +info: Entering event queue @ 4806256925500. Starting simulation... switching cpus -info: Entering event queue @ 4807144389500. Starting simulation... +info: Entering event queue @ 4807256797500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4808144389500. Starting simulation... +info: Entering event queue @ 4808256797500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4809144389500. Starting simulation... +info: Entering event queue @ 4809256797500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4810144389500. Starting simulation... +info: Entering event queue @ 4810256797500. Starting simulation... switching cpus -info: Entering event queue @ 4811144261500. Starting simulation... +info: Entering event queue @ 4811256669500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4812144261500. Starting simulation... +info: Entering event queue @ 4812256669500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4813144261500. Starting simulation... +info: Entering event queue @ 4813256669500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4814144261500. Starting simulation... +info: Entering event queue @ 4814256669500. Starting simulation... switching cpus -info: Entering event queue @ 4815144133500. Starting simulation... +info: Entering event queue @ 4815256541500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4816144133500. Starting simulation... +info: Entering event queue @ 4816256541500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4817144133500. Starting simulation... +info: Entering event queue @ 4817256541500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4818144133500. Starting simulation... +info: Entering event queue @ 4818256541500. Starting simulation... switching cpus -info: Entering event queue @ 4819144005500. Starting simulation... +info: Entering event queue @ 4819256413500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4820144005500. Starting simulation... +info: Entering event queue @ 4820256413500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4821144005500. Starting simulation... +info: Entering event queue @ 4821256413500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4822144005500. Starting simulation... +info: Entering event queue @ 4822256413500. Starting simulation... switching cpus -info: Entering event queue @ 4823143877500. Starting simulation... +info: Entering event queue @ 4823256285500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4824143877500. Starting simulation... +info: Entering event queue @ 4824256285500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4825143877500. Starting simulation... +info: Entering event queue @ 4825256285500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4826143877500. Starting simulation... +info: Entering event queue @ 4826256285500. Starting simulation... switching cpus -info: Entering event queue @ 4827143749500. Starting simulation... +info: Entering event queue @ 4827256157500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4828143749500. Starting simulation... +info: Entering event queue @ 4828256157500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4829143749500. Starting simulation... +info: Entering event queue @ 4829256157500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4830143749500. Starting simulation... +info: Entering event queue @ 4830256157500. Starting simulation... switching cpus -info: Entering event queue @ 4831143621500. Starting simulation... +info: Entering event queue @ 4831256029500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4832143621500. Starting simulation... +info: Entering event queue @ 4832256029500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4833143621500. Starting simulation... +info: Entering event queue @ 4833256029500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4834143621500. Starting simulation... +info: Entering event queue @ 4834256029500. Starting simulation... switching cpus -info: Entering event queue @ 4835143493500. Starting simulation... +info: Entering event queue @ 4835255901500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4836143493500. Starting simulation... +info: Entering event queue @ 4836255901500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4837143493500. Starting simulation... +info: Entering event queue @ 4837255901500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4838143493500. Starting simulation... +info: Entering event queue @ 4838255901500. Starting simulation... switching cpus -info: Entering event queue @ 4839143365500. Starting simulation... +info: Entering event queue @ 4839255773500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4840143365500. Starting simulation... +info: Entering event queue @ 4840255773500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4841143365500. Starting simulation... +info: Entering event queue @ 4841255773500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4842143365500. Starting simulation... +info: Entering event queue @ 4842255773500. Starting simulation... switching cpus -info: Entering event queue @ 4843143237500. Starting simulation... +info: Entering event queue @ 4843255645500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4844143237500. Starting simulation... +info: Entering event queue @ 4844255645500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4845143237500. Starting simulation... +info: Entering event queue @ 4845255645500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4846143237500. Starting simulation... +info: Entering event queue @ 4846255645500. Starting simulation... switching cpus -info: Entering event queue @ 4847143109500. Starting simulation... +info: Entering event queue @ 4847255517500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4848143109500. Starting simulation... +info: Entering event queue @ 4848255517500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4849143109500. Starting simulation... +info: Entering event queue @ 4849255517500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4850143109500. Starting simulation... +info: Entering event queue @ 4850255517500. Starting simulation... switching cpus -info: Entering event queue @ 4851142981500. Starting simulation... +info: Entering event queue @ 4851255389500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4852142981500. Starting simulation... +info: Entering event queue @ 4852255389500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4853142981500. Starting simulation... +info: Entering event queue @ 4853255389500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4854142981500. Starting simulation... +info: Entering event queue @ 4854255389500. Starting simulation... switching cpus -info: Entering event queue @ 4855142853500. Starting simulation... +info: Entering event queue @ 4855255261500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4856142853500. Starting simulation... +info: Entering event queue @ 4856255261500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4857142853500. Starting simulation... +info: Entering event queue @ 4857255261500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4858142853500. Starting simulation... +info: Entering event queue @ 4858255261500. Starting simulation... switching cpus -info: Entering event queue @ 4859142725500. Starting simulation... +info: Entering event queue @ 4859255133500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4860142725500. Starting simulation... +info: Entering event queue @ 4860255133500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4861142725500. Starting simulation... +info: Entering event queue @ 4861255133500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4862142725500. Starting simulation... +info: Entering event queue @ 4862255133500. Starting simulation... switching cpus -info: Entering event queue @ 4863142597500. Starting simulation... +info: Entering event queue @ 4863255005500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4864142597500. Starting simulation... +info: Entering event queue @ 4864255005500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4865142597500. Starting simulation... +info: Entering event queue @ 4865255005500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4866142597500. Starting simulation... +info: Entering event queue @ 4866255005500. Starting simulation... switching cpus -info: Entering event queue @ 4867142469500. Starting simulation... +info: Entering event queue @ 4867254877500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4868142469500. Starting simulation... +info: Entering event queue @ 4868254877500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4869142469500. Starting simulation... +info: Entering event queue @ 4869254877500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4870142469500. Starting simulation... +info: Entering event queue @ 4870254877500. Starting simulation... switching cpus -info: Entering event queue @ 4871142341500. Starting simulation... +info: Entering event queue @ 4871254749500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4872142341500. Starting simulation... +info: Entering event queue @ 4872254749500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4873142341500. Starting simulation... +info: Entering event queue @ 4873254749500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4874142341500. Starting simulation... +info: Entering event queue @ 4874254749500. Starting simulation... switching cpus -info: Entering event queue @ 4875142213500. Starting simulation... +info: Entering event queue @ 4875254621500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4876142213500. Starting simulation... +info: Entering event queue @ 4876254621500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4877142213500. Starting simulation... +info: Entering event queue @ 4877254621500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4878142213500. Starting simulation... +info: Entering event queue @ 4878254621500. Starting simulation... switching cpus -info: Entering event queue @ 4879142085500. Starting simulation... +info: Entering event queue @ 4879254493500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4880142085500. Starting simulation... +info: Entering event queue @ 4880254493500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4881142085500. Starting simulation... +info: Entering event queue @ 4881254493500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4882142085500. Starting simulation... +info: Entering event queue @ 4882254493500. Starting simulation... switching cpus -info: Entering event queue @ 4883141957500. Starting simulation... +info: Entering event queue @ 4883254365500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4884141957500. Starting simulation... +info: Entering event queue @ 4884254365500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4885141957500. Starting simulation... +info: Entering event queue @ 4885254365500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4886141957500. Starting simulation... +info: Entering event queue @ 4886254365500. Starting simulation... switching cpus -info: Entering event queue @ 4887141829500. Starting simulation... +info: Entering event queue @ 4887254237500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4888141829500. Starting simulation... +info: Entering event queue @ 4888254237500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4889141829500. Starting simulation... +info: Entering event queue @ 4889254237500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4890141829500. Starting simulation... +info: Entering event queue @ 4890254237500. Starting simulation... switching cpus -info: Entering event queue @ 4891141701500. Starting simulation... +info: Entering event queue @ 4891254109500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4892141701500. Starting simulation... +info: Entering event queue @ 4892254109500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4893141701500. Starting simulation... +info: Entering event queue @ 4893254109500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4894141701500. Starting simulation... +info: Entering event queue @ 4894254109500. Starting simulation... switching cpus -info: Entering event queue @ 4895141573500. Starting simulation... +info: Entering event queue @ 4895253981500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4896141573500. Starting simulation... +info: Entering event queue @ 4896253981500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4897141573500. Starting simulation... +info: Entering event queue @ 4897253981500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4898141573500. Starting simulation... +info: Entering event queue @ 4898253981500. Starting simulation... switching cpus -info: Entering event queue @ 4899141445500. Starting simulation... +info: Entering event queue @ 4899253853500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4900141445500. Starting simulation... +info: Entering event queue @ 4900253853500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4901141445500. Starting simulation... +info: Entering event queue @ 4901253853500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4902141445500. Starting simulation... +info: Entering event queue @ 4902253853500. Starting simulation... switching cpus -info: Entering event queue @ 4903141317500. Starting simulation... +info: Entering event queue @ 4903253725500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4904141317500. Starting simulation... +info: Entering event queue @ 4904253725500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4905141317500. Starting simulation... +info: Entering event queue @ 4905253725500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4906141317500. Starting simulation... +info: Entering event queue @ 4906253725500. Starting simulation... switching cpus -info: Entering event queue @ 4907141189500. Starting simulation... +info: Entering event queue @ 4907253597500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4908141189500. Starting simulation... +info: Entering event queue @ 4908253597500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4909141189500. Starting simulation... +info: Entering event queue @ 4909253597500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4910141189500. Starting simulation... +info: Entering event queue @ 4910253597500. Starting simulation... switching cpus -info: Entering event queue @ 4911141061500. Starting simulation... +info: Entering event queue @ 4911253469500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4912141061500. Starting simulation... +info: Entering event queue @ 4912253469500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4913141061500. Starting simulation... +info: Entering event queue @ 4913253469500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4914141061500. Starting simulation... +info: Entering event queue @ 4914253469500. Starting simulation... switching cpus -info: Entering event queue @ 4915140933500. Starting simulation... +info: Entering event queue @ 4915253341500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4916140933500. Starting simulation... +info: Entering event queue @ 4916253341500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4917140933500. Starting simulation... +info: Entering event queue @ 4917253341500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4918140933500. Starting simulation... +info: Entering event queue @ 4918253341500. Starting simulation... switching cpus -info: Entering event queue @ 4919140805500. Starting simulation... +info: Entering event queue @ 4919253213500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4920140805500. Starting simulation... +info: Entering event queue @ 4920253213500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4921140805500. Starting simulation... +info: Entering event queue @ 4921253213500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4922140805500. Starting simulation... +info: Entering event queue @ 4922253213500. Starting simulation... switching cpus -info: Entering event queue @ 4923140677500. Starting simulation... +info: Entering event queue @ 4923253085500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4924140677500. Starting simulation... +info: Entering event queue @ 4924253085500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4925140677500. Starting simulation... +info: Entering event queue @ 4925253085500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4926140677500. Starting simulation... +info: Entering event queue @ 4926253085500. Starting simulation... switching cpus -info: Entering event queue @ 4927140549500. Starting simulation... +info: Entering event queue @ 4927252957500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4928140549500. Starting simulation... +info: Entering event queue @ 4928252957500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4929140549500. Starting simulation... +info: Entering event queue @ 4929252957500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4930140549500. Starting simulation... +info: Entering event queue @ 4930252957500. Starting simulation... switching cpus -info: Entering event queue @ 4931140421500. Starting simulation... +info: Entering event queue @ 4931252829500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4932140421500. Starting simulation... +info: Entering event queue @ 4932252829500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4933140421500. Starting simulation... +info: Entering event queue @ 4933252829500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4934140421500. Starting simulation... +info: Entering event queue @ 4934252829500. Starting simulation... switching cpus -info: Entering event queue @ 4935140293500. Starting simulation... +info: Entering event queue @ 4935252701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4936140293500. Starting simulation... +info: Entering event queue @ 4936252701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4937140293500. Starting simulation... +info: Entering event queue @ 4937252701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4938140293500. Starting simulation... +info: Entering event queue @ 4938252701500. Starting simulation... switching cpus -info: Entering event queue @ 4939140165500. Starting simulation... +info: Entering event queue @ 4939252573500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4940140165500. Starting simulation... +info: Entering event queue @ 4940252573500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4941140165500. Starting simulation... +info: Entering event queue @ 4941252573500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4942140165500. Starting simulation... +info: Entering event queue @ 4942252573500. Starting simulation... switching cpus -info: Entering event queue @ 4943140037500. Starting simulation... +info: Entering event queue @ 4943252445500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4944140037500. Starting simulation... +info: Entering event queue @ 4944252445500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4945140037500. Starting simulation... +info: Entering event queue @ 4945252445500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4946140037500. Starting simulation... +info: Entering event queue @ 4946252445500. Starting simulation... switching cpus -info: Entering event queue @ 4947139909500. Starting simulation... +info: Entering event queue @ 4947252317500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4948139909500. Starting simulation... +info: Entering event queue @ 4948252317500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4949139909500. Starting simulation... +info: Entering event queue @ 4949252317500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4950139909500. Starting simulation... +info: Entering event queue @ 4950252317500. Starting simulation... switching cpus -info: Entering event queue @ 4951139781500. Starting simulation... +info: Entering event queue @ 4951252189500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4952139781500. Starting simulation... +info: Entering event queue @ 4952252189500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4953139781500. Starting simulation... +info: Entering event queue @ 4953252189500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4954139781500. Starting simulation... +info: Entering event queue @ 4954252189500. Starting simulation... switching cpus -info: Entering event queue @ 4955139653500. Starting simulation... +info: Entering event queue @ 4955252061500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4956139653500. Starting simulation... +info: Entering event queue @ 4956252061500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4957139653500. Starting simulation... +info: Entering event queue @ 4957252061500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4958139653500. Starting simulation... +info: Entering event queue @ 4958252061500. Starting simulation... switching cpus -info: Entering event queue @ 4959139525500. Starting simulation... +info: Entering event queue @ 4959251933500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4960139525500. Starting simulation... +info: Entering event queue @ 4960251933500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4961139525500. Starting simulation... +info: Entering event queue @ 4961251933500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4962139525500. Starting simulation... +info: Entering event queue @ 4962251933500. Starting simulation... switching cpus -info: Entering event queue @ 4963139397500. Starting simulation... +info: Entering event queue @ 4963251805500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4964139397500. Starting simulation... +info: Entering event queue @ 4964251805500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4965139397500. Starting simulation... +info: Entering event queue @ 4965251805500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4966139397500. Starting simulation... +info: Entering event queue @ 4966251805500. Starting simulation... switching cpus -info: Entering event queue @ 4967139269500. Starting simulation... +info: Entering event queue @ 4967251677500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4968139269500. Starting simulation... +info: Entering event queue @ 4968251677500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4969139269500. Starting simulation... +info: Entering event queue @ 4969251677500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4970139269500. Starting simulation... +info: Entering event queue @ 4970251677500. Starting simulation... switching cpus -info: Entering event queue @ 4971139141500. Starting simulation... +info: Entering event queue @ 4971251549500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4972139141500. Starting simulation... +info: Entering event queue @ 4972251549500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4973139141500. Starting simulation... +info: Entering event queue @ 4973251549500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4974139141500. Starting simulation... +info: Entering event queue @ 4974251549500. Starting simulation... switching cpus -info: Entering event queue @ 4975139013500. Starting simulation... +info: Entering event queue @ 4975251421500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4976139013500. Starting simulation... +info: Entering event queue @ 4976251421500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4977139013500. Starting simulation... +info: Entering event queue @ 4977251421500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4978139013500. Starting simulation... +info: Entering event queue @ 4978251421500. Starting simulation... switching cpus -info: Entering event queue @ 4979138885500. Starting simulation... +info: Entering event queue @ 4979251293500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4980138885500. Starting simulation... +info: Entering event queue @ 4980251293500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4981138885500. Starting simulation... +info: Entering event queue @ 4981251293500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4982138885500. Starting simulation... +info: Entering event queue @ 4982251293500. Starting simulation... switching cpus -info: Entering event queue @ 4983138757500. Starting simulation... +info: Entering event queue @ 4983251165500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4984138757500. Starting simulation... +info: Entering event queue @ 4984251165500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4985138757500. Starting simulation... +info: Entering event queue @ 4985251165500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4986138757500. Starting simulation... +info: Entering event queue @ 4986251165500. Starting simulation... switching cpus -info: Entering event queue @ 4987138629500. Starting simulation... +info: Entering event queue @ 4987251037500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4988138629500. Starting simulation... +info: Entering event queue @ 4988251037500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4989138629500. Starting simulation... +info: Entering event queue @ 4989251037500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4990138629500. Starting simulation... +info: Entering event queue @ 4990251037500. Starting simulation... switching cpus -info: Entering event queue @ 4991138501500. Starting simulation... +info: Entering event queue @ 4991250909500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4992138501500. Starting simulation... +info: Entering event queue @ 4992250909500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4993138501500. Starting simulation... +info: Entering event queue @ 4993250909500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4994138501500. Starting simulation... +info: Entering event queue @ 4994250909500. Starting simulation... switching cpus -info: Entering event queue @ 4995138373500. Starting simulation... +info: Entering event queue @ 4995250781500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 4996138373500. Starting simulation... +info: Entering event queue @ 4996250781500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 4997138373500. Starting simulation... +info: Entering event queue @ 4997250781500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4998138373500. Starting simulation... +info: Entering event queue @ 4998250781500. Starting simulation... switching cpus -info: Entering event queue @ 4999138245500. Starting simulation... +info: Entering event queue @ 4999250653500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5000138245500. Starting simulation... +info: Entering event queue @ 5000250653500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 5001138245500. Starting simulation... +info: Entering event queue @ 5001250653500. Starting simulation... switching cpus -info: Entering event queue @ 5001138253000. Starting simulation... +info: Entering event queue @ 5001250661000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5002138253000. Starting simulation... +info: Entering event queue @ 5002250661000. Starting simulation... switching cpus -info: Entering event queue @ 5002138262500. Starting simulation... +info: Entering event queue @ 5002250670500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 5003250670500. Starting simulation... switching cpus -info: Entering event queue @ 5003138262500. Starting simulation... +info: Entering event queue @ 5003250671000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 5004138262500. Starting simulation... -info: Entering event queue @ 5004138451000. Starting simulation... +info: Entering event queue @ 5004250671000. Starting simulation... switching cpus -info: Entering event queue @ 5004138458500. Starting simulation... +info: Entering event queue @ 5004250678500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5005138458500. Starting simulation... -info: Entering event queue @ 5007137924500. Starting simulation... -info: Entering event queue @ 5007137925500. Starting simulation... +info: Entering event queue @ 5005250678500. Starting simulation... +info: Entering event queue @ 5007250332500. Starting simulation... +info: Entering event queue @ 5007250333500. Starting simulation... switching cpus -info: Entering event queue @ 5007137930000. Starting simulation... +info: Entering event queue @ 5007250338000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5008137930000. Starting simulation... +info: Entering event queue @ 5008250338000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5009137930000. Starting simulation... +info: Entering event queue @ 5009250338000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5010137930000. Starting simulation... +info: Entering event queue @ 5010250338000. Starting simulation... switching cpus -info: Entering event queue @ 5011137861500. Starting simulation... +info: Entering event queue @ 5011250269500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5012137861500. Starting simulation... +info: Entering event queue @ 5012250269500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5013137861500. Starting simulation... +info: Entering event queue @ 5013250269500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5014137861500. Starting simulation... +info: Entering event queue @ 5014250269500. Starting simulation... switching cpus -info: Entering event queue @ 5015137733500. Starting simulation... +info: Entering event queue @ 5015250141500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5016137733500. Starting simulation... +info: Entering event queue @ 5016250141500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5017137733500. Starting simulation... +info: Entering event queue @ 5017250141500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5018137733500. Starting simulation... +info: Entering event queue @ 5018250141500. Starting simulation... switching cpus -info: Entering event queue @ 5019137605500. Starting simulation... +info: Entering event queue @ 5019250013500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5020137605500. Starting simulation... +info: Entering event queue @ 5020250013500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5021137605500. Starting simulation... +info: Entering event queue @ 5021250013500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5022137605500. Starting simulation... +info: Entering event queue @ 5022250013500. Starting simulation... switching cpus -info: Entering event queue @ 5023137477500. Starting simulation... +info: Entering event queue @ 5023249885500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5024137477500. Starting simulation... +info: Entering event queue @ 5024249885500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5025137477500. Starting simulation... +info: Entering event queue @ 5025249885500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5026137477500. Starting simulation... +info: Entering event queue @ 5026249885500. Starting simulation... switching cpus -info: Entering event queue @ 5027137349500. Starting simulation... +info: Entering event queue @ 5027249757500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5028137349500. Starting simulation... +info: Entering event queue @ 5028249757500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5029137349500. Starting simulation... +info: Entering event queue @ 5029249757500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5030137349500. Starting simulation... +info: Entering event queue @ 5030249757500. Starting simulation... switching cpus -info: Entering event queue @ 5031137221500. Starting simulation... +info: Entering event queue @ 5031249629500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5032137221500. Starting simulation... +info: Entering event queue @ 5032249629500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5033137221500. Starting simulation... +info: Entering event queue @ 5033249629500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5034137221500. Starting simulation... +info: Entering event queue @ 5034249629500. Starting simulation... switching cpus -info: Entering event queue @ 5035137093500. Starting simulation... +info: Entering event queue @ 5035249501500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5036137093500. Starting simulation... +info: Entering event queue @ 5036249501500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5037137093500. Starting simulation... +info: Entering event queue @ 5037249501500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5038137093500. Starting simulation... +info: Entering event queue @ 5038249501500. Starting simulation... switching cpus -info: Entering event queue @ 5039136965500. Starting simulation... +info: Entering event queue @ 5039249373500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5040136965500. Starting simulation... +info: Entering event queue @ 5040249373500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5041136965500. Starting simulation... +info: Entering event queue @ 5041249373500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5042136965500. Starting simulation... +info: Entering event queue @ 5042249373500. Starting simulation... switching cpus -info: Entering event queue @ 5043136837500. Starting simulation... +info: Entering event queue @ 5043249245500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5044136837500. Starting simulation... +info: Entering event queue @ 5044249245500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5045136837500. Starting simulation... +info: Entering event queue @ 5045249245500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5046136837500. Starting simulation... +info: Entering event queue @ 5046249245500. Starting simulation... switching cpus -info: Entering event queue @ 5047136709500. Starting simulation... +info: Entering event queue @ 5047249117500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5048136709500. Starting simulation... +info: Entering event queue @ 5048249117500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5049136709500. Starting simulation... +info: Entering event queue @ 5049249117500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5050136709500. Starting simulation... +info: Entering event queue @ 5050249117500. Starting simulation... switching cpus -info: Entering event queue @ 5051136581500. Starting simulation... +info: Entering event queue @ 5051248989500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5052136581500. Starting simulation... +info: Entering event queue @ 5052248989500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5053136581500. Starting simulation... +info: Entering event queue @ 5053248989500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5054136581500. Starting simulation... +info: Entering event queue @ 5054248989500. Starting simulation... switching cpus -info: Entering event queue @ 5055136453500. Starting simulation... +info: Entering event queue @ 5055248861500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5056136453500. Starting simulation... +info: Entering event queue @ 5056248861500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5057136453500. Starting simulation... +info: Entering event queue @ 5057248861500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5058136453500. Starting simulation... +info: Entering event queue @ 5058248861500. Starting simulation... switching cpus -info: Entering event queue @ 5059136325500. Starting simulation... +info: Entering event queue @ 5059248733500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5060136325500. Starting simulation... +info: Entering event queue @ 5060248733500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5061136325500. Starting simulation... +info: Entering event queue @ 5061248733500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5062136325500. Starting simulation... +info: Entering event queue @ 5062248733500. Starting simulation... switching cpus -info: Entering event queue @ 5063136197500. Starting simulation... +info: Entering event queue @ 5063248605500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5064136197500. Starting simulation... +info: Entering event queue @ 5064248605500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5065136197500. Starting simulation... +info: Entering event queue @ 5065248605500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5066136197500. Starting simulation... +info: Entering event queue @ 5066248605500. Starting simulation... switching cpus -info: Entering event queue @ 5067136069500. Starting simulation... +info: Entering event queue @ 5067248477500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5068136069500. Starting simulation... +info: Entering event queue @ 5068248477500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5069136069500. Starting simulation... +info: Entering event queue @ 5069248477500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5070136069500. Starting simulation... +info: Entering event queue @ 5070248477500. Starting simulation... switching cpus -info: Entering event queue @ 5071135941500. Starting simulation... +info: Entering event queue @ 5071248349500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5072135941500. Starting simulation... +info: Entering event queue @ 5072248349500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5073135941500. Starting simulation... +info: Entering event queue @ 5073248349500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5074135941500. Starting simulation... +info: Entering event queue @ 5074248349500. Starting simulation... switching cpus -info: Entering event queue @ 5075135813500. Starting simulation... +info: Entering event queue @ 5075248221500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5076135813500. Starting simulation... +info: Entering event queue @ 5076248221500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5077135813500. Starting simulation... +info: Entering event queue @ 5077248221500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5078135813500. Starting simulation... +info: Entering event queue @ 5078248221500. Starting simulation... switching cpus -info: Entering event queue @ 5079135685500. Starting simulation... +info: Entering event queue @ 5079248093500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5080135685500. Starting simulation... +info: Entering event queue @ 5080248093500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5081135685500. Starting simulation... +info: Entering event queue @ 5081248093500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5082135685500. Starting simulation... +info: Entering event queue @ 5082248093500. Starting simulation... switching cpus -info: Entering event queue @ 5083135557500. Starting simulation... +info: Entering event queue @ 5083247965500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5084135557500. Starting simulation... +info: Entering event queue @ 5084247965500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5085135557500. Starting simulation... +info: Entering event queue @ 5085247965500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5086135557500. Starting simulation... +info: Entering event queue @ 5086247965500. Starting simulation... switching cpus -info: Entering event queue @ 5087135429500. Starting simulation... +info: Entering event queue @ 5087247837500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5088135429500. Starting simulation... +info: Entering event queue @ 5088247837500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5089135429500. Starting simulation... +info: Entering event queue @ 5089247837500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5090135429500. Starting simulation... +info: Entering event queue @ 5090247837500. Starting simulation... switching cpus -info: Entering event queue @ 5091135301500. Starting simulation... +info: Entering event queue @ 5091247709500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5092135301500. Starting simulation... +info: Entering event queue @ 5092247709500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5093135301500. Starting simulation... +info: Entering event queue @ 5093247709500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5094135301500. Starting simulation... +info: Entering event queue @ 5094247709500. Starting simulation... switching cpus -info: Entering event queue @ 5095135173500. Starting simulation... +info: Entering event queue @ 5095247581500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5096135173500. Starting simulation... +info: Entering event queue @ 5096247581500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5097135173500. Starting simulation... +info: Entering event queue @ 5097247581500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5098135173500. Starting simulation... +info: Entering event queue @ 5098247581500. Starting simulation... switching cpus -info: Entering event queue @ 5099135045500. Starting simulation... +info: Entering event queue @ 5099247453500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5100135045500. Starting simulation... +info: Entering event queue @ 5100247453500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5101135045500. Starting simulation... +info: Entering event queue @ 5101247453500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5102135045500. Starting simulation... +info: Entering event queue @ 5102247453500. Starting simulation... switching cpus -info: Entering event queue @ 5103134917500. Starting simulation... +info: Entering event queue @ 5103247325500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 5104134917500. Starting simulation... +info: Entering event queue @ 5104247325500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 5105134917500. Starting simulation... +info: Entering event queue @ 5105247325500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5106134917500. Starting simulation... +info: Entering event queue @ 5106247325500. Starting simulation... switching cpus -info: Entering event queue @ 5107134789500. Starting simulation... +info: Entering event queue @ 5107247197500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 5108134789500. Starting simulation... switching cpus -info: Entering event queue @ 5108134791000. Starting simulation... +info: Entering event queue @ 5108247197500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 5109134791000. Starting simulation... +info: Entering event queue @ 5109247197500. Starting simulation... +info: Entering event queue @ 5109247212000. Starting simulation... switching cpus -info: Entering event queue @ 5109134798500. Starting simulation... +info: Entering event queue @ 5109247571250. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5110134798500. Starting simulation... -info: Entering event queue @ 5110134845250. Starting simulation... +info: Entering event queue @ 5110247571250. Starting simulation... switching cpus -info: Entering event queue @ 5110134982250. Starting simulation... +info: Entering event queue @ 5110247578750. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 5111247578750. Starting simulation... switching cpus -info: Entering event queue @ 5111134982250. Starting simulation... +info: Entering event queue @ 5111247579000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 5112134982250. Starting simulation... -info: Entering event queue @ 5112135240000. Starting simulation... +info: Entering event queue @ 5112247579000. Starting simulation... switching cpus -info: Entering event queue @ 5112135247500. Starting simulation... +info: Entering event queue @ 5112247586500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5113135247500. Starting simulation... -info: Entering event queue @ 5115134468500. Starting simulation... -info: Entering event queue @ 5115134469500. Starting simulation... +info: Entering event queue @ 5113247586500. Starting simulation... switching cpus -info: Entering event queue @ 5115134474000. Starting simulation... +info: Entering event queue @ 5113247604500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 5116134474000. Starting simulation... switching cpus -info: Entering event queue @ 5116134474500. Starting simulation... +info: Entering event queue @ 5114247604500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 5117134474500. Starting simulation... +info: Entering event queue @ 5115247604500. Starting simulation... switching cpus -info: Entering event queue @ 5117134482000. Starting simulation... +info: Entering event queue @ 5115247621000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5118134482000. Starting simulation... -info: Entering event queue @ 5119134341500. Starting simulation... -info: Entering event queue @ 5119134342500. Starting simulation... +info: Entering event queue @ 5116247621000. Starting simulation... +info: Entering event queue @ 5119246748500. Starting simulation... +info: Entering event queue @ 5119246749500. Starting simulation... switching cpus -info: Entering event queue @ 5119134347000. Starting simulation... +info: Entering event queue @ 5119246754000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 5120134347000. Starting simulation... switching cpus -info: Entering event queue @ 5120134348500. Starting simulation... +info: Entering event queue @ 5120246754000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 5121134348500. Starting simulation... +info: Entering event queue @ 5121246754000. Starting simulation... switching cpus -info: Entering event queue @ 5121134356000. Starting simulation... +info: Entering event queue @ 5121246761500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5122134356000. Starting simulation... -info: Entering event queue @ 5123134212500. Starting simulation... -info: Entering event queue @ 5123134213500. Starting simulation... +info: Entering event queue @ 5122246761500. Starting simulation... +info: Entering event queue @ 5123246620500. Starting simulation... +info: Entering event queue @ 5123246621500. Starting simulation... switching cpus -info: Entering event queue @ 5123134218000. Starting simulation... +info: Entering event queue @ 5123246626000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 5124246626000. Starting simulation... switching cpus -info: Entering event queue @ 5124134218000. Starting simulation... +info: Entering event queue @ 5124246627000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 5125246627000. Starting simulation... switching cpus -info: Entering event queue @ 5125134218000. Starting simulation... +info: Entering event queue @ 5125246634500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5126134218000. Starting simulation... -info: Entering event queue @ 5127134484500. Starting simulation... -info: Entering event queue @ 5127134485500. Starting simulation... +info: Entering event queue @ 5126246634500. Starting simulation... +info: Entering event queue @ 5127246915000. Starting simulation... +info: Entering event queue @ 5127246916000. Starting simulation... switching cpus -info: Entering event queue @ 5127134490000. Starting simulation... +info: Entering event queue @ 5127246920500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 5128246920500. Starting simulation... switching cpus -info: Entering event queue @ 5128134490000. Starting simulation... +info: Entering event queue @ 5128246922000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 5129134490000. Starting simulation... -info: Entering event queue @ 5129134497500. Starting simulation... +info: Entering event queue @ 5129246922000. Starting simulation... switching cpus -info: Entering event queue @ 5129134498000. Starting simulation... +info: Entering event queue @ 5129246929500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5130134498000. Starting simulation... +info: Entering event queue @ 5130246929500. Starting simulation... +info: Entering event queue @ 5131246364500. Starting simulation... +info: Entering event queue @ 5131246365500. Starting simulation... switching cpus -info: Entering event queue @ 5130134511000. Starting simulation... +info: Entering event queue @ 5131246370000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 5132246370000. Starting simulation... switching cpus -info: Entering event queue @ 5131134511000. Starting simulation... +info: Entering event queue @ 5132246371000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 5132134511000. Starting simulation... -info: Entering event queue @ 5132134561000. Starting simulation... +info: Entering event queue @ 5133246371000. Starting simulation... switching cpus -info: Entering event queue @ 5132134794500. Starting simulation... +info: Entering event queue @ 5133246378500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5133134794500. Starting simulation... -info: Entering event queue @ 5135133830000. Starting simulation... -info: Entering event queue @ 5135133831000. Starting simulation... +info: Entering event queue @ 5134246378500. Starting simulation... +info: Entering event queue @ 5135246236500. Starting simulation... +info: Entering event queue @ 5135246237500. Starting simulation... switching cpus -info: Entering event queue @ 5135133835500. Starting simulation... +info: Entering event queue @ 5135246242000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 5136133835500. Starting simulation... +info: Entering event queue @ 5136246242000. Starting simulation... switching cpus -info: Entering event queue @ 5136133836500. Starting simulation... +info: Entering event queue @ 5136246243500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 5137133836500. Starting simulation... -switching cpus -info: Entering event queue @ 5137133844000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5138133844000. Starting simulation... -info: Entering event queue @ 5139134126500. Starting simulation... -info: Entering event queue @ 5139134127500. Starting simulation... +info: Entering event queue @ 5137246243500. Starting simulation... switching cpus -info: Entering event queue @ 5139134132000. Starting simulation... +info: Entering event queue @ 5137246251000. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 4e965874c..f1500ba2f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,151 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.133841 # Number of seconds simulated -sim_ticks 5133841152500 # Number of ticks simulated -final_tick 5133841152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.137889 # Number of seconds simulated +sim_ticks 5137889173500 # Number of ticks simulated +final_tick 5137889173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 177631 # Simulator instruction rate (inst/s) -host_op_rate 353062 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3741933991 # Simulator tick rate (ticks/s) -host_mem_usage 941552 # Number of bytes of host memory used -host_seconds 1371.98 # Real time elapsed on the host -sim_insts 243704660 # Number of instructions simulated -sim_ops 484392635 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2439680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 417472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5435008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 153664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1637440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 389440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3273088 # Number of bytes read from this memory -system.physmem.bytes_read::total 13748288 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 417472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 153664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 389440 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 960576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9087296 # Number of bytes written to this memory -system.physmem.bytes_written::total 9087296 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38120 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6523 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 84922 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2401 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 25585 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 34 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6085 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 51142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 214817 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141989 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141989 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 475215 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 81318 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1058663 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 29932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 318950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 75857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 637551 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2677973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 81318 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 29932 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 75857 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 187107 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1770077 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1770077 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1770077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 475215 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 81318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1058663 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 29932 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 318950 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 75857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 637551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4448050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 109407 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 86017 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 109407 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 86017 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 7002048 # Total number of bytes read from memory -system.physmem.bytesWritten 5505088 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 7002048 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5505088 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 46 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 985 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 6677 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 6958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 6998 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 7052 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7052 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 7335 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 6832 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7518 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 6667 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 6488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 6603 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 6903 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 6546 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 6589 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 6857 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 6286 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5445 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5613 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5579 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5490 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5857 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5967 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5488 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5044 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4972 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5220 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5090 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5143 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4887 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5403 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4667 # Track writes on a per bank basis +host_inst_rate 239672 # Simulator instruction rate (inst/s) +host_op_rate 476391 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5046842796 # Simulator tick rate (ticks/s) +host_mem_usage 957396 # Number of bytes of host memory used +host_seconds 1018.04 # Real time elapsed on the host +sim_insts 243995320 # Number of instructions simulated +sim_ops 484985266 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2475904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 403712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5648960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 122048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1730432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 439808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2919040 # Number of bytes read from this memory +system.physmem.bytes_read::total 13741824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 403712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 122048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 439808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 965568 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9081216 # Number of bytes written to this memory +system.physmem.bytes_written::total 9081216 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 38686 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6308 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 88265 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 27038 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 25 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6872 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 45610 # Number of read requests responded to by this memory +system.physmem.num_reads::total 214716 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 141894 # Number of write requests responded to by this memory +system.physmem.num_writes::total 141894 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 481891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 78575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1099471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 23755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 336798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 311 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 85601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 568140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2674605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 78575 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 23755 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 85601 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 187931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1767499 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1767499 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1767499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 481891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 78575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1099471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 23755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 336798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 85601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 568140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4442104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 101962 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 77214 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 101962 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 77214 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 6525568 # Total number of bytes read from memory +system.physmem.bytesWritten 4941696 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 6525568 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 4941696 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 66 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 761 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 6643 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 6709 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 6361 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 6804 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 6400 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 6366 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 5890 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 6159 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 5804 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 6034 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 5639 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 6376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 6508 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 6377 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 6998 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 6828 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5378 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5214 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4748 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5235 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5043 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 4974 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4413 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4576 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 4071 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 4483 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4133 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 4579 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5113 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 4622 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5461 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5171 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 5132841022000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry +system.physmem.totGap 5136889044500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 109407 # Categorize read packet sizes +system.physmem.readPktSize::6 101962 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 86017 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 82002 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11011 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 769 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 587 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 606 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 77214 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 78859 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1511 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1094 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 669 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 509 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -157,526 +161,534 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 34126 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 366.337455 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.216704 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 1274.009312 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-67 15243 44.67% 44.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-131 5253 15.39% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-195 3189 9.34% 69.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-259 2065 6.05% 75.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-323 1417 4.15% 79.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-387 1112 3.26% 82.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-451 885 2.59% 85.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-515 703 2.06% 87.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-579 508 1.49% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-643 509 1.49% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-707 307 0.90% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-771 283 0.83% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-835 211 0.62% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-899 233 0.68% 93.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-963 184 0.54% 94.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1027 239 0.70% 94.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1091 139 0.41% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1155 117 0.34% 95.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1219 116 0.34% 95.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1283 75 0.22% 96.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1347 103 0.30% 96.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1411 85 0.25% 96.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1475 293 0.86% 97.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1539 132 0.39% 97.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1603 64 0.19% 98.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1667 54 0.16% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1731 36 0.11% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1795 37 0.11% 98.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1859 21 0.06% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1923 15 0.04% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1987 15 0.04% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2051 22 0.06% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2115 8 0.02% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2179 8 0.02% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2243 13 0.04% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2307 6 0.02% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2371 9 0.03% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2435 4 0.01% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2499 6 0.02% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2563 7 0.02% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2627 5 0.01% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2691 3 0.01% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2755 7 0.02% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2819 4 0.01% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2883 2 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2947 2 0.01% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3011 3 0.01% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3075 6 0.02% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3139 3 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3203 3 0.01% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3331 1 0.00% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3395 2 0.01% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3459 7 0.02% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3523 2 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3651 2 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3715 3 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3779 4 0.01% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3843 2 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3907 1 0.00% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3971 3 0.01% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4099 8 0.02% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4227 4 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4419 3 0.01% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4483 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4547 3 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4611 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4867 1 0.00% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4931 1 0.00% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5059 2 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5123 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5187 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5315 2 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5507 2 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5827 1 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5891 2 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6019 3 0.01% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6147 1 0.00% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6275 1 0.00% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6339 1 0.00% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6595 2 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6723 5 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6979 2 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7043 2 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7171 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7747 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7875 2 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7939 2 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8067 1 0.00% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8195 49 0.14% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9088-9091 2 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9219 3 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9539 3 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9667 3 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9731 1 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9795 4 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9923 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11011 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11075 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11139 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11331 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11456-11459 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12099 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12867 3 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13888-13891 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14016-14019 2 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14595 3 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14912-14915 23 0.07% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14976-14979 8 0.02% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15043 5 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15107 7 0.02% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15171 5 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15232-15235 2 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15296-15299 7 0.02% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15363 8 0.02% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15488-15491 4 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15552-15555 3 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15747 2 0.01% 99.75% # Bytes accessed per row activation +system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 32753 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 349.964889 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 152.240831 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1180.348858 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-67 14687 44.84% 44.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-131 5019 15.32% 60.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-195 3032 9.26% 69.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-259 2021 6.17% 75.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-323 1281 3.91% 79.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-387 1132 3.46% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-451 832 2.54% 85.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-515 693 2.12% 87.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-579 503 1.54% 89.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-643 527 1.61% 90.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-707 287 0.88% 91.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-771 266 0.81% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-835 203 0.62% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-899 195 0.60% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-963 197 0.60% 94.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1027 238 0.73% 94.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1091 149 0.45% 95.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1155 112 0.34% 95.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1219 86 0.26% 96.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1283 79 0.24% 96.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1347 89 0.27% 96.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1411 70 0.21% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1475 290 0.89% 97.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1539 98 0.30% 97.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1603 63 0.19% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1667 48 0.15% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1731 49 0.15% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1795 27 0.08% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1859 22 0.07% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1923 16 0.05% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1987 16 0.05% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2051 11 0.03% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2115 5 0.02% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2179 13 0.04% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2243 5 0.02% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2307 10 0.03% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2371 7 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2435 5 0.02% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2499 3 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2563 7 0.02% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2627 3 0.01% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2691 3 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2755 3 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2819 3 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2883 5 0.02% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2947 2 0.01% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3011 2 0.01% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3075 2 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3139 4 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3203 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3267 3 0.01% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3331 4 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3395 4 0.01% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3459 7 0.02% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3523 2 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3587 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3651 4 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3715 1 0.00% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3779 6 0.02% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3843 2 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3907 5 0.02% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3971 2 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4035 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4099 9 0.03% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4163 1 0.00% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4227 2 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4355 1 0.00% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4419 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4483 2 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4547 2 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4611 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4867 2 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4995 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5059 2 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5123 3 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5187 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5251 2 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5315 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5379 1 0.00% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5507 2 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5891 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6019 2 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6083 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6147 2 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6211 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6275 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6467 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6531 3 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6595 2 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6723 5 0.02% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6851 2 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6915 2 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6979 3 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7043 4 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7171 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7939 3 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8003 2 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8067 2 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8195 48 0.15% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9219 2 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9600-9603 2 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9792-9795 2 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11712-11715 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12672-12675 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12931 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13632-13635 1 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14912-14915 13 0.04% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-14979 3 0.01% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15107 7 0.02% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15168-15171 2 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15488-15491 3 0.01% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15552-15555 3 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15680-15683 3 0.01% 99.74% # Bytes accessed per row activation system.physmem.bytesPerActivate::15808-15811 2 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15936-15939 2 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16064-16067 3 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16131 6 0.02% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16192-16195 6 0.02% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16256-16259 13 0.04% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16323 11 0.03% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16387 30 0.09% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16448-16451 2 0.01% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16512-16515 2 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16576-16579 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16643 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15875 2 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16131 3 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16192-16195 9 0.03% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16256-16259 10 0.03% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16320-16323 15 0.05% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16387 34 0.10% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16448-16451 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::16704-16707 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17411 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-17987 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20483 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 34126 # Bytes accessed per row activation -system.physmem.totQLat 2227577000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4316939500 # Sum of mem lat for all requests -system.physmem.totBusLat 546805000 # Total cycles spent in databus access -system.physmem.totBankLat 1542557500 # Total cycles spent in bank access -system.physmem.avgQLat 20369.03 # Average queueing delay per request -system.physmem.avgBankLat 14105.19 # Average bank access latency per request +system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16899 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17667 2 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 32753 # Bytes accessed per row activation +system.physmem.totQLat 1954361749 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 3940385499 # Sum of mem lat for all requests +system.physmem.totBusLat 509480000 # Total cycles spent in databus access +system.physmem.totBankLat 1476543750 # Total cycles spent in bank access +system.physmem.avgQLat 19179.97 # Average queueing delay per request +system.physmem.avgBankLat 14490.69 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 39474.21 # Average memory access latency -system.physmem.avgRdBW 1.36 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 1.07 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1.36 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.07 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38670.66 # Average memory access latency +system.physmem.avgRdBW 1.27 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.96 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 1.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.96 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.12 # Average write queue length over time -system.physmem.readRowHits 96443 # Number of row buffer hits during reads -system.physmem.writeRowHits 64788 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.32 # Row buffer hit rate for writes -system.physmem.avgGap 26265151.78 # Average gap between requests -system.membus.throughput 6435647 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 426045 # Transaction distribution -system.membus.trans_dist::ReadResp 426045 # Transaction distribution -system.membus.trans_dist::WriteReq 6051 # Transaction distribution -system.membus.trans_dist::WriteResp 6051 # Transaction distribution -system.membus.trans_dist::Writeback 86017 # Transaction distribution -system.membus.trans_dist::UpgradeReq 992 # Transaction distribution -system.membus.trans_dist::UpgradeResp 992 # Transaction distribution -system.membus.trans_dist::ReadExReq 86731 # Transaction distribution -system.membus.trans_dist::ReadExResp 86731 # Transaction distribution -system.membus.trans_dist::MessageReq 839 # Transaction distribution -system.membus.trans_dist::MessageResp 839 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1678 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 1678 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 309632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497840 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 229352 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1036824 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83140 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83140 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1121642 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3356 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 3356 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 158773 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995677 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 9079040 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 10233490 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3428096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 3428096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13664942 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 32675815 # Total data (bytes) -system.membus.snoop_data_through_bus 363776 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 162435000 # Layer occupancy (ticks) +system.physmem.readRowHits 89443 # Number of row buffer hits during reads +system.physmem.writeRowHits 56909 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.78 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes +system.physmem.avgGap 28669515.14 # Average gap between requests +system.membus.throughput 6421183 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 424471 # Transaction distribution +system.membus.trans_dist::ReadResp 424470 # Transaction distribution +system.membus.trans_dist::WriteReq 6959 # Transaction distribution +system.membus.trans_dist::WriteResp 6959 # Transaction distribution +system.membus.trans_dist::Writeback 77214 # Transaction distribution +system.membus.trans_dist::UpgradeReq 768 # Transaction distribution +system.membus.trans_dist::UpgradeResp 768 # Transaction distribution +system.membus.trans_dist::ReadExReq 79729 # Transaction distribution +system.membus.trans_dist::ReadExResp 79729 # Transaction distribution +system.membus.trans_dist::MessageReq 903 # Transaction distribution +system.membus.trans_dist::MessageResp 903 # Transaction distribution +system.membus.trans_dist::BadAddressError 1 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 1806 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 1806 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 312334 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 497960 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 218608 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1028904 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 68108 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 68108 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1098818 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 3612 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.apicbridge.master::total 3612 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160445 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 995917 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8655808 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 9812170 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2811456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 2811456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 12627238 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 32732190 # Total data (bytes) +system.membus.snoop_data_through_bus 259136 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 164966500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315254500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315386000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1678000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1806000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 909214250 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 820026249 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 839000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 903000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1669428217 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1636763940 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 266628000 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 218001500 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 103896 # number of replacements -system.l2c.tags.tagsinuse 64824.162456 # Cycle average of tags in use -system.l2c.tags.total_refs 3654371 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167960 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.757389 # Average number of references to valid blocks. +system.l2c.tags.replacements 103793 # number of replacements +system.l2c.tags.tagsinuse 64823.461690 # Cycle average of tags in use +system.l2c.tags.total_refs 3658744 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 167885 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.793156 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51338.562640 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.124968 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1291.708374 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4472.671123 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 224.398277 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1500.107620 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 12.436537 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1357.602773 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 4626.550145 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.783364 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51284.674060 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.121869 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1299.911935 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4544.856644 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 221.437918 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1509.586927 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.216404 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003202 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1337.967786 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 4616.684944 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.782542 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.019710 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.068248 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003424 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.022890 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000190 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.020715 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.070596 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989138 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 17952 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 9698 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 334064 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 501848 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 11245 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6309 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 156420 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 227136 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 54455 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 10230 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 347276 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 575532 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2252165 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.019835 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.069349 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003379 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023034 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000125 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.020416 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.070445 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989128 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 22091 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 11658 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 334413 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 510225 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10171 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5452 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 152259 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 227659 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 50814 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 10913 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 351942 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 566551 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2254148 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1543820 # number of Writeback hits -system.l2c.Writeback_hits::total 1543820 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 85 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 61 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 121 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 267 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 59704 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 38749 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 68883 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 167336 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 17952 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 9700 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 334064 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 561552 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 11245 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6309 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 156420 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 265885 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 54455 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 10230 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 347276 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 644415 # number of demand (read+write) hits -system.l2c.demand_hits::total 2419503 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 17952 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 9700 # number of overall hits -system.l2c.overall_hits::cpu0.inst 334064 # number of overall hits -system.l2c.overall_hits::cpu0.data 561552 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 11245 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6309 # number of overall hits -system.l2c.overall_hits::cpu1.inst 156420 # number of overall hits -system.l2c.overall_hits::cpu1.data 265885 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 54455 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 10230 # number of overall hits -system.l2c.overall_hits::cpu2.inst 347276 # number of overall hits -system.l2c.overall_hits::cpu2.data 644415 # number of overall hits -system.l2c.overall_hits::total 2419503 # number of overall hits -system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6523 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 13238 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2401 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4542 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 34 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 6087 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 15146 # number of ReadReq misses -system.l2c.ReadReq_misses::total 47976 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 449 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 296 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 618 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1363 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 72270 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 21215 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 36170 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 129655 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6523 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 85508 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2401 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 25757 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 34 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 6087 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 51316 # number of demand (read+write) misses -system.l2c.demand_misses::total 177631 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6523 # number of overall misses -system.l2c.overall_misses::cpu0.data 85508 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2401 # number of overall misses -system.l2c.overall_misses::cpu1.data 25757 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 34 # number of overall misses -system.l2c.overall_misses::cpu2.inst 6087 # number of overall misses -system.l2c.overall_misses::cpu2.data 51316 # number of overall misses -system.l2c.overall_misses::total 177631 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 190776000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 357065989 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3670750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 535117250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1265414987 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2352044976 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 3779850 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 6916712 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 10696562 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1454896180 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 2695279940 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 4150176120 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 190776000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1811962169 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 3670750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 535117250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3960694927 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 6502221096 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 190776000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1811962169 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 3670750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 535117250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3960694927 # number of overall miss cycles -system.l2c.overall_miss_latency::total 6502221096 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 17952 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 9703 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 340587 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 515086 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 11245 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6309 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 158821 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 231678 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 54489 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 10230 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 353363 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 590678 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2300141 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_hits::writebacks 1543420 # number of Writeback hits +system.l2c.Writeback_hits::total 1543420 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 115 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 83 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 254 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 69377 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 36565 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 61899 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 167841 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 22091 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 11660 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 334413 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 579602 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10171 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5452 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 152259 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 264224 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 50814 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 10913 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 351942 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 628450 # number of demand (read+write) hits +system.l2c.demand_hits::total 2421991 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 22091 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 11660 # number of overall hits +system.l2c.overall_hits::cpu0.inst 334413 # number of overall hits +system.l2c.overall_hits::cpu0.data 579602 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10171 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5452 # number of overall hits +system.l2c.overall_hits::cpu1.inst 152259 # number of overall hits +system.l2c.overall_hits::cpu1.data 264224 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 50814 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 10913 # number of overall hits +system.l2c.overall_hits::cpu2.inst 351942 # number of overall hits +system.l2c.overall_hits::cpu2.data 628450 # number of overall hits +system.l2c.overall_hits::total 2421991 # number of overall hits +system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6308 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 16059 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1908 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3914 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 25 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 6873 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 12824 # number of ReadReq misses +system.l2c.ReadReq_misses::total 47916 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 775 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 221 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 356 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1352 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 72577 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 23336 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 33144 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 129057 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6308 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 88636 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1908 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 27250 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 25 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 6873 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 45968 # number of demand (read+write) misses +system.l2c.demand_misses::total 176973 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6308 # number of overall misses +system.l2c.overall_misses::cpu0.data 88636 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1908 # number of overall misses +system.l2c.overall_misses::cpu1.data 27250 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 25 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu2.inst 6873 # number of overall misses +system.l2c.overall_misses::cpu2.data 45968 # number of overall misses +system.l2c.overall_misses::total 176973 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 145483750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 305732245 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2908500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 88750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 619386243 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1056307494 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2129906982 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2658895 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 4530318 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 7189213 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1598265396 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 2458778359 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 4057043755 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 145483750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1903997641 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 2908500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 88750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 619386243 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 3515085853 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 6186950737 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 145483750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1903997641 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 2908500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 88750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 619386243 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 3515085853 # number of overall miss cycles +system.l2c.overall_miss_latency::total 6186950737 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 22091 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 11662 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 340721 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 526284 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 10171 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5452 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 154167 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 231573 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 50839 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 10914 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 358815 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 579375 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2302064 # number of ReadReq accesses(hits+misses) system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1543820 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1543820 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 534 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 357 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 739 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1630 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 131974 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 59964 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 105053 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296991 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 17952 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 9705 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 340587 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 647060 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 11245 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6309 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 158821 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 291642 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 54489 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 10230 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 353363 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 695731 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2597134 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 17952 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 9705 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 340587 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 647060 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 11245 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6309 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 158821 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 291642 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 54489 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 10230 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 353363 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 695731 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2597134 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000515 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.019152 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.025701 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.015118 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.019605 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000624 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.017226 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.025642 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020858 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.840824 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.829132 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.836265 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.836196 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.547608 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.353796 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.344302 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.436562 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000515 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019152 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.132148 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.015118 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.088317 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000624 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.017226 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.073758 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.068395 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000515 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019152 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.132148 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.015118 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.088317 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000624 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.017226 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.073758 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.068395 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 79456.892961 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 78614.264421 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 107963.235294 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 87911.491704 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 83547.800541 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 49025.449725 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12769.763514 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11192.090615 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 7847.807777 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68578.655668 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74517.001382 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 32009.379661 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 79456.892961 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 70348.339053 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 107963.235294 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 87911.491704 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 77182.456290 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 36605.215846 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 79456.892961 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 70348.339053 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 107963.235294 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 87911.491704 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 77182.456290 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 36605.215846 # average overall miss latency +system.l2c.Writeback_accesses::writebacks 1543420 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1543420 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 890 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 277 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 439 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1606 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 141954 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 59901 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 95043 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296898 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 22091 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 11664 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 340721 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 668238 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 10171 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5452 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 154167 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 291474 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 50839 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 10914 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 358815 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 674418 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2598964 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 22091 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 11664 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 340721 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 668238 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 10171 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5452 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 154167 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 291474 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 50839 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 10914 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 358815 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 674418 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2598964 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000343 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018514 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.030514 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.012376 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.016902 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000492 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000092 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.019155 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.022134 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.020814 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.870787 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.797834 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.810934 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.841843 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.511271 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.389576 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.348726 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.434685 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000343 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018514 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.132641 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.012376 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.093490 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000492 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000092 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.019155 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.068160 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.068094 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000343 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018514 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.132641 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.012376 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.093490 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000492 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000092 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.019155 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.068160 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.068094 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76249.344864 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 78112.479561 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 116340 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 88750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 90118.760803 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 82369.580006 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 44450.851114 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12031.199095 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12725.612360 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5317.465237 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68489.261056 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74184.719979 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 31436.061237 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 76249.344864 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 69871.473064 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 116340 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 90118.760803 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 76468.105051 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 34959.856797 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 76249.344864 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 69871.473064 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 116340 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 88750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 90118.760803 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 76468.105051 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 34959.856797 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,119 +697,131 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 95322 # number of writebacks -system.l2c.writebacks::total 95322 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.inst 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.inst 2401 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4542 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 34 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 6085 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 15146 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 28208 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 296 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 618 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 914 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 21215 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 36170 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 57385 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2401 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 25757 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 34 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 6085 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 51316 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 85593 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2401 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 25757 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 34 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 6085 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 51316 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 85593 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 160439500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 299438011 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 3240750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 458127750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 1073760993 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1995007004 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3160292 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 6338615 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 9498907 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1188287320 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2240519524 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 3428806844 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 160439500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1487725331 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3240750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 458127750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 3314280517 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5423813848 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 160439500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1487725331 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3240750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 458127750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 3314280517 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5423813848 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28206379000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30385404000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 58591783000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 459404000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 643945000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1103349000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28665783000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31029349000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 59695132000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015118 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019605 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000624 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.017220 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.025642 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.012264 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829132 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.836265 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.560736 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.353796 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.344302 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.193221 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015118 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.088317 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000624 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.017220 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.073758 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.032957 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015118 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.088317 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000624 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.017220 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.073758 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.032957 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66821.949188 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65926.466535 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 95316.176471 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 75288.044371 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 70894.030965 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 70724.865428 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10676.662162 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10256.658576 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10392.677243 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56011.657789 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61944.139453 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 59750.925224 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66821.949188 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57760.039251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 95316.176471 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 75288.044371 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 64585.714339 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 63367.493230 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66821.949188 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57760.039251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 95316.176471 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 75288.044371 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 64585.714339 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63367.493230 # average overall mshr miss latency +system.l2c.writebacks::writebacks 95227 # number of writebacks +system.l2c.writebacks::total 95227 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu1.inst 1908 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 3914 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 25 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 6872 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 12824 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25544 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 221 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 356 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 577 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 23336 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 33144 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 56480 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1908 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 27250 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 25 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 6872 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 45968 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 82024 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1908 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 27250 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 25 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 6872 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 45968 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 82024 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 121373750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 256053755 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2594000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 76250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 532537507 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 893917000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1806552262 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 2360218 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 3787353 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 6147571 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1304557104 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2042074099 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 3346631203 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 121373750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1560610859 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2594000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 76250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 532537507 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2935991099 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5153183465 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 121373750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1560610859 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2594000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 76250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 532537507 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2935991099 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5153183465 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28189792500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30481780500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 58671573000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 471155500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 768000500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1239156000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28660948000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31249781000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59910729000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.012376 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016902 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000492 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000092 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.019152 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.022134 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.011096 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.797834 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.810934 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.359278 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.389576 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.348726 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.190234 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.012376 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.093490 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000492 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000092 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.019152 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.068160 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.031560 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.012376 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.093490 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000492 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000092 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.019152 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.068160 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.031560 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63613.076520 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65419.968063 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 103760 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 77493.816502 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 69706.565814 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 70723.154635 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10679.719457 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10638.632022 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10654.369151 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55903.201234 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61612.180153 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 59253.385322 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63613.076520 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57270.123266 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 103760 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 77493.816502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63870.324987 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62825.312896 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63613.076520 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57270.123266 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 103760 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 77493.816502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63870.324987 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62825.312896 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -808,39 +832,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47572 # number of replacements -system.iocache.tags.tagsinuse 0.081746 # Cycle average of tags in use +system.iocache.tags.replacements 47570 # number of replacements +system.iocache.tags.tagsinuse 0.094174 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47586 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000166717509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081746 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005109 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005109 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses -system.iocache.ReadReq_misses::total 907 # number of ReadReq misses +system.iocache.tags.warmup_cycle 5000166705009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.094174 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005886 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005886 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses +system.iocache.ReadReq_misses::total 905 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47627 # number of demand (read+write) misses -system.iocache.demand_misses::total 47627 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47627 # number of overall misses -system.iocache.overall_misses::total 47627 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 17254172 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 17254172 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6526811791 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 6526811791 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 6544065963 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 6544065963 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 6544065963 # number of overall miss cycles -system.iocache.overall_miss_latency::total 6544065963 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses +system.iocache.demand_misses::total 47625 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses +system.iocache.overall_misses::total 47625 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131928771 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 131928771 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 5225930177 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5225930177 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 5357858948 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5357858948 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 5357858948 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5357858948 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47627 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47627 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -849,60 +873,60 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 19023.342889 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 19023.342889 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 139700.594842 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 139700.594842 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 137402.439016 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 137402.439016 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 137402.439016 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 137402.439016 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 93815 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145777.647514 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145777.647514 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 111856.382213 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 111856.382213 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 112500.975286 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 112500.975286 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 112500.975286 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 112500.975286 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 75733 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9015 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7002 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.406545 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.815910 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 152 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 29424 # number of WriteReq MSHR misses -system.iocache.WriteReq_mshr_misses::total 29424 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 29576 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 29576 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 29576 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 29576 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 9350172 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 9350172 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4995875791 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 4995875791 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 5005225963 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5005225963 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 5005225963 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5005225963 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.167585 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.167585 # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.629795 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total 0.629795 # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.620992 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.620992 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.620992 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.620992 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 61514.289474 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 61514.289474 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169789.144610 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 169789.144610 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 169232.687415 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 169232.687415 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 169232.687415 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 169232.687415 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 739 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 739 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 23440 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 23440 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 24179 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 24179 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 24179 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 24179 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93470771 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 93470771 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4006299177 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4006299177 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4099769948 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4099769948 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4099769948 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4099769948 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.816575 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.816575 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 0.501712 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 0.501712 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.507696 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.507696 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.507696 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.507696 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 126482.775372 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 126482.775372 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 170917.200384 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 170917.200384 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 169559.119401 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 169559.119401 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 169559.119401 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 169559.119401 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -912,101 +936,102 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 52334793 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1839633 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1839631 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 6051 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 6051 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 932295 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1096 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1096 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 194441 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 165022 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1024400 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3716860 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 38970 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 150527 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4930757 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32779776 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 124023122 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 132312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 525872 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 157461082 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 268452219 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 226296 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5204318000 # Layer occupancy (ticks) +system.toL2Bus.throughput 52280174 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1811511 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1810976 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 6959 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 6959 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 914733 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 716 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 716 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 178384 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 154949 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1025990 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3658453 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 36523 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 129481 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4850447 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 32830848 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 121529738 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 130928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 488080 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 154979594 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 268493674 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 116064 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5106548110 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 697500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2307741753 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2311338505 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4862432158 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4765806692 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 22450957 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 20170721 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 84915011 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 68576287 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1275830 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 149760 # Transaction distribution -system.iobus.trans_dist::ReadResp 149760 # Transaction distribution -system.iobus.trans_dist::WriteReq 34632 # Transaction distribution -system.iobus.trans_dist::WriteResp 34632 # Transaction distribution -system.iobus.trans_dist::MessageReq 839 # Transaction distribution -system.iobus.trans_dist::MessageResp 839 # Transaction distribution +system.iobus.throughput 1274820 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 150850 # Transaction distribution +system.iobus.trans_dist::ReadResp 150850 # Transaction distribution +system.iobus.trans_dist::WriteReq 29496 # Transaction distribution +system.iobus.trans_dist::WriteResp 29496 # Transaction distribution +system.iobus.trans_dist::MessageReq 903 # Transaction distribution +system.iobus.trans_dist::MessageResp 903 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 3660 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5804 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 26 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 46 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287488 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 432 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 552 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 14654 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 15072 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 4 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 309632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 59152 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 59152 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1678 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1678 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 370462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 312334 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 48358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 48358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 1806 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 1806 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 362498 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 2064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3277 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 13 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 23 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143744 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 864 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1104 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7327 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 7536 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 2 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 158773 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1884352 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1884352 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3356 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3356 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2046481 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6549906 # Total data (bytes) -system.iobus.reqLayer0.occupancy 1995988 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 160445 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1536536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1536536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3612 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 3612 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 1700593 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 6549885 # Total data (bytes) +system.iobus.reqLayer0.occupancy 2124548 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 3028000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4801000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 24000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 39000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) @@ -1014,354 +1039,356 @@ system.iobus.reqLayer8.occupancy 18000 # La system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 143745000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 340000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 436000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10951000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11266000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 266780963 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 213288448 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 304424000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 306278000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 30398000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 29307500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 839000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 903000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.numCycles 1216058379 # number of cpu cycles simulated +system.cpu0.numCycles 1216464910 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 70973751 # Number of instructions committed -system.cpu0.committedOps 144754752 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 132876215 # Number of integer alu accesses +system.cpu0.committedInsts 71961421 # Number of instructions committed +system.cpu0.committedOps 146368954 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134434152 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 954469 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14058767 # number of instructions that are conditional controls -system.cpu0.num_int_insts 132876215 # number of integer instructions +system.cpu0.num_func_calls 983451 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14191112 # number of instructions that are conditional controls +system.cpu0.num_int_insts 134434152 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 326195357 # number of times the integer registers were read -system.cpu0.num_int_register_writes 169360741 # number of times the integer registers were written +system.cpu0.num_int_register_reads 247103574 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115380288 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 13502778 # number of memory refs -system.cpu0.num_load_insts 9976335 # Number of load instructions -system.cpu0.num_store_insts 3526443 # Number of store instructions -system.cpu0.num_idle_cycles 1154763739.944412 # Number of idle cycles -system.cpu0.num_busy_cycles 61294639.055587 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050404 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949596 # Percentage of idle cycles +system.cpu0.num_cc_register_reads 83614520 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55784493 # number of times the CC registers were written +system.cpu0.num_mem_refs 14023782 # number of memory refs +system.cpu0.num_load_insts 10248970 # Number of load instructions +system.cpu0.num_store_insts 3774812 # Number of store instructions +system.cpu0.num_idle_cycles 1155422884.085227 # Number of idle cycles +system.cpu0.num_busy_cycles 61042025.914772 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050180 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949820 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 852277 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.807193 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 128191488 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 852789 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 150.320288 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 853207 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.801369 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 129244758 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 853719 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 151.390279 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 147441059000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 310.064023 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 127.526237 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 73.216933 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.605594 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.249075 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.143002 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997670 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 86216719 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39136583 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2838186 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 128191488 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 86216719 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39136583 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2838186 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 128191488 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 86216719 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39136583 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2838186 # number of overall hits -system.cpu0.icache.overall_hits::total 128191488 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 340588 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 158821 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 373273 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 872682 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 340588 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 158821 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 373273 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 872682 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 340588 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 158821 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 373273 # number of overall misses -system.cpu0.icache.overall_misses::total 872682 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2239882500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5368625144 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7608507644 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2239882500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5368625144 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7608507644 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2239882500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5368625144 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7608507644 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 86557307 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39295404 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3211459 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 129064170 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 86557307 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39295404 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3211459 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 129064170 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 86557307 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39295404 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3211459 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 129064170 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003935 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004042 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.116232 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006762 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003935 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004042 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.116232 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006762 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003935 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004042 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.116232 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006762 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14103.188495 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14382.570248 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8718.533949 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14103.188495 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14382.570248 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8718.533949 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14103.188495 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14382.570248 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8718.533949 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3629 # number of cycles access was blocked +system.cpu0.icache.tags.occ_blocks::cpu0.inst 310.509377 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 127.091120 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 73.200872 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.606464 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.248225 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.142970 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997659 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 87593978 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 38906796 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2743984 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 129244758 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 87593978 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 38906796 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2743984 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 129244758 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 87593978 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 38906796 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2743984 # number of overall hits +system.cpu0.icache.overall_hits::total 129244758 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 340722 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 154167 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 378624 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 873513 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 340722 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 154167 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 378624 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 873513 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 340722 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 154167 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 378624 # number of overall misses +system.cpu0.icache.overall_misses::total 873513 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2138351750 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5548047899 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7686399649 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2138351750 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5548047899 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7686399649 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2138351750 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5548047899 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7686399649 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 87934700 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 39060963 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3122608 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 130118271 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 87934700 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 39060963 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3122608 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 130118271 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 87934700 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 39060963 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3122608 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 130118271 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003875 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.003947 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.121252 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006713 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003875 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.003947 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121252 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006713 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003875 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.003947 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121252 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006713 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13870.359740 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14653.186008 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8799.410712 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13870.359740 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14653.186008 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8799.410712 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13870.359740 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14653.186008 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8799.410712 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 6480 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 204 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 241 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.789216 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.887967 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 19878 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 19878 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 19878 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 19878 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 19878 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 19878 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 158821 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 353395 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 512216 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 158821 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 353395 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 512216 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 158821 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 353395 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 512216 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1921073500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4443772241 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6364845741 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1921073500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4443772241 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6364845741 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1921073500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4443772241 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6364845741 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004042 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110042 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003969 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004042 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110042 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.003969 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004042 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110042 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.003969 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12095.840600 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12574.519280 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12426.097078 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12095.840600 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12574.519280 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12426.097078 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12095.840600 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12574.519280 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12426.097078 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 19783 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 19783 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 19783 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 19783 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 19783 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 19783 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 154167 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 358841 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 513008 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 154167 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 358841 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 513008 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 154167 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 358841 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 513008 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1829084250 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4581098483 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6410182733 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1829084250 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4581098483 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6410182733 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1829084250 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4581098483 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6410182733 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.003947 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.114917 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.003943 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.003947 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.114917 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.003943 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.003947 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.114917 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.003943 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11864.304618 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12766.374196 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12495.288052 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11864.304618 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12766.374196 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12495.288052 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11864.304618 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12766.374196 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12495.288052 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1633907 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999457 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19585249 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1634419 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.983004 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1633606 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999469 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19601664 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1634118 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.995256 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 202.365565 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 302.948237 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.685655 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.395245 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.591696 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013058 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 202.875385 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 302.501214 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.622869 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.396241 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.590823 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012935 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4859041 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2539484 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4098776 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11497301 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3389758 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1674537 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3021878 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8086173 # number of WriteReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8248799 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4214021 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7120654 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19583474 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8248799 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4214021 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7120654 # number of overall hits -system.cpu0.dcache.overall_hits::total 19583474 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 515086 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 231678 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 978230 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1724994 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 132508 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 60321 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 122659 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 315488 # number of WriteReq misses -system.cpu0.dcache.demand_misses::cpu0.data 647594 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 291999 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1100889 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2040482 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 647594 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 291999 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1100889 # number of overall misses -system.cpu0.dcache.overall_misses::total 2040482 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3333147011 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 16401267335 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 19734414346 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2044900112 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3952716068 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5997616180 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5378047123 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 20353983403 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 25732030526 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 5378047123 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 20353983403 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 25732030526 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5374127 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2771162 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 5077006 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13222295 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3522266 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1734858 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3144537 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8401661 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8896393 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4506020 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 8221543 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21623956 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8896393 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4506020 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 8221543 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21623956 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.095846 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083603 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.192679 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.130461 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037620 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034770 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.039007 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.037551 # miss rate for WriteReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.072793 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.064802 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.133903 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.094362 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.072793 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.064802 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.133903 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.094362 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14386.981116 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16766.269011 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11440.279993 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 33900.301918 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32225.242893 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19010.600023 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18418.032675 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18488.679061 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 12610.760853 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18418.032675 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18488.679061 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12610.760853 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 185998 # number of cycles access was blocked +system.cpu0.dcache.ReadReq_hits::cpu0.data 5120812 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2495791 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 3903609 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11520212 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3628684 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1642970 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2808111 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8079765 # number of WriteReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8749496 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 4138761 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6711720 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19599977 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8749496 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 4138761 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6711720 # number of overall hits +system.cpu0.dcache.overall_hits::total 19599977 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 526284 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 231573 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 944815 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1702672 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 142844 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 60178 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 112298 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 315320 # number of WriteReq misses +system.cpu0.dcache.demand_misses::cpu0.data 669128 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 291751 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1057113 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2017992 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 669128 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 291751 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1057113 # number of overall misses +system.cpu0.dcache.overall_misses::total 2017992 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3286416755 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15267347781 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 18553764536 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2165300822 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3604529651 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5769830473 # number of WriteReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 5451717577 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 18871877432 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 24323595009 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 5451717577 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 18871877432 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 24323595009 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5647096 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 2727364 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4848424 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13222884 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3771528 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1703148 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2920409 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8395085 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9418624 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4430512 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7768833 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21617969 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9418624 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4430512 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7768833 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21617969 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.093196 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.084907 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.194871 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.128767 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037874 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.035333 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.038453 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.037560 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.071043 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065850 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.136071 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.093348 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071043 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065850 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.136071 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.093348 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14191.709547 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16159.086997 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10896.851852 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35981.601615 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32097.897122 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18298.333353 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18686.200140 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17852.280155 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 12053.365429 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18686.200140 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17852.280155 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12053.365429 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 177204 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 11819 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 11696 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.737203 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.150821 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1543820 # number of writebacks -system.cpu0.dcache.writebacks::total 1543820 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 387497 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 387497 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 16923 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 16923 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 404420 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 404420 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 404420 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 404420 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 231678 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 590733 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 822411 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 60321 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 105736 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 166057 # number of WriteReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 291999 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 696469 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 988468 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 291999 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 696469 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 988468 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2867647989 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8746594786 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11614242775 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1913927888 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3540253677 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5454181565 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4781575877 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 12286848463 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 17068424340 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4781575877 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12286848463 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 17068424340 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30680226500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33146860500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63827087000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 492961500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 683134500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1176096000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31173188000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33829995000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65003183000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083603 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.116355 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.062199 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034770 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.033625 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019765 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.064802 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.084713 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.045712 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.064802 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.084713 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.045712 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12377.731114 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14806.341928 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14122.188024 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31729.047728 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33482.008748 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32845.237268 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16375.315933 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17641.630084 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17267.553770 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16375.315933 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17641.630084 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17267.553770 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1543420 # number of writebacks +system.cpu0.dcache.writebacks::total 1543420 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 365400 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 365400 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 16856 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 16856 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 382256 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 382256 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 382256 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 382256 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 231573 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 579415 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 810988 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 60178 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 95442 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 155620 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 291751 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 674857 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 966608 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 291751 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 674857 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 966608 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2821426245 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 8425862038 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 11247288283 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2033592178 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3216384846 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5249977024 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4855018423 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 11642246884 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16497265307 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4855018423 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11642246884 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16497265307 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30662990000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33250431500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63913421500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 506056500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 816755500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1322812000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31169046500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34067187000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65236233500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.084907 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.119506 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.061332 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035333 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032681 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018537 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065850 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.086867 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.044713 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065850 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086867 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.044713 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12183.744413 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14542.015719 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13868.624792 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33792.950547 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33699.889420 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33735.876006 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16640.965834 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17251.427908 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17067.172325 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16640.965834 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17251.427908 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17067.172325 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1372,303 +1399,306 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2604006231 # number of cpu cycles simulated +system.cpu1.numCycles 2606006645 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35468286 # Number of instructions committed -system.cpu1.committedOps 68966826 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64112699 # Number of integer alu accesses +system.cpu1.committedInsts 35315213 # Number of instructions committed +system.cpu1.committedOps 68682433 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63797816 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 467397 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6516733 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64112699 # number of integer instructions +system.cpu1.num_func_calls 457734 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6497995 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63797816 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 154768017 # number of times the integer registers were read -system.cpu1.num_int_register_writes 82365610 # number of times the integer registers were written +system.cpu1.num_int_register_reads 117816925 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55078781 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 4696856 # number of memory refs -system.cpu1.num_load_insts 2960322 # Number of load instructions -system.cpu1.num_store_insts 1736534 # Number of store instructions -system.cpu1.num_idle_cycles 2474842610.831012 # Number of idle cycles -system.cpu1.num_busy_cycles 129163620.168988 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049602 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950398 # Percentage of idle cycles +system.cpu1.num_cc_register_reads 36195960 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26980721 # number of times the CC registers were written +system.cpu1.num_mem_refs 4621452 # number of memory refs +system.cpu1.num_load_insts 2916499 # Number of load instructions +system.cpu1.num_store_insts 1704953 # Number of store instructions +system.cpu1.num_idle_cycles 2477007170.096548 # Number of idle cycles +system.cpu1.num_busy_cycles 128999474.903452 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049501 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950499 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 28951326 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28951326 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 314609 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26444223 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25831001 # Number of BTB hits +system.cpu2.branchPred.lookups 28832932 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28832932 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 311283 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26470595 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25835663 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.681074 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 549086 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 62360 # Number of incorrect RAS predictions. -system.cpu2.numCycles 157333790 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.601369 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 539109 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63758 # Number of incorrect RAS predictions. +system.cpu2.numCycles 156318365 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9628033 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 142779184 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28951326 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26380087 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 54597571 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1466251 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 74094 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 26092625 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 3700 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 8528 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 28165 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 264 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3211459 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 142418 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1960 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 91566528 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 3.070894 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.405285 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9648571 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 142153316 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28832932 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26374772 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 54477061 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1438031 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 74339 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 25017392 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 3513 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 6379 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 22688 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 421 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3122610 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 142940 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2082 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 90361689 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 3.101501 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.407201 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 37107042 40.52% 40.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 606936 0.66% 41.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23738841 25.93% 67.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 323417 0.35% 67.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 617037 0.67% 68.14% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 822992 0.90% 69.04% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 354044 0.39% 69.43% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 540920 0.59% 70.02% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27455299 29.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 36017869 39.86% 39.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 584325 0.65% 40.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23803917 26.34% 66.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 312236 0.35% 67.19% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 599559 0.66% 67.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 810629 0.90% 68.76% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 333254 0.37% 69.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 522143 0.58% 69.70% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27377757 30.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 91566528 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.184012 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.907492 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 11182494 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 24930048 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 34120224 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1336422 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1136839 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 280365996 # Number of instructions handled by decode +system.cpu2.fetch.rateDist::total 90361689 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.184450 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.909383 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 11120847 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 23921754 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 35744474 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1291324 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1114642 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 279457828 # Number of instructions handled by decode system.cpu2.decode.SquashedInsts 12 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1136839 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12213242 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 15294999 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4292193 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 34251970 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5516857 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 279357990 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 7057 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 2496977 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 2317195 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 3859 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 333649845 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 608867337 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 608867129 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 208 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 323590484 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10059359 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 155930 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 156830 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 11908821 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6436780 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3659466 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 346383 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 291566 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 277678174 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 418845 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 276116383 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 64009 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7123201 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10899779 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 56873 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 91566528 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 3.015473 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.405372 # Number of insts issued each cycle +system.cpu2.rename.SquashCycles 1114642 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12111653 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 14421944 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4371925 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 35874443 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5298501 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 278479903 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 7178 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2457632 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 2167618 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 332694530 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 605890178 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 372281709 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 54 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 322791874 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 9902651 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 146965 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 147763 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11459312 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6166984 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3428654 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 344111 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 288647 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 276817235 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 412713 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 275284943 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 59120 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 6994425 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10714687 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 55194 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 90361689 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 3.046479 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.402703 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 27610803 30.15% 30.15% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6353978 6.94% 37.09% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 4055937 4.43% 41.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2815603 3.07% 44.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 25104677 27.42% 72.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1385023 1.51% 73.53% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23879782 26.08% 99.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 304593 0.33% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 56132 0.06% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 26846835 29.71% 29.71% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6154250 6.81% 36.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3929000 4.35% 40.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2711977 3.00% 43.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 25114660 27.79% 71.66% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1340428 1.48% 73.15% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23928680 26.48% 99.63% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 282970 0.31% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 52889 0.06% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 91566528 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 90361689 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 137927 34.75% 34.75% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 241 0.06% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 34.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 196105 49.41% 84.22% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 62645 15.78% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 125502 33.84% 33.84% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 241 0.06% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.91% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 190694 51.42% 85.33% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 54418 14.67% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 83641 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 265753381 96.25% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 56758 0.02% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 49344 0.02% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6728768 2.44% 98.75% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3444491 1.25% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 78208 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 265424287 96.42% 96.45% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 56044 0.02% 96.47% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 46278 0.02% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.48% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6463688 2.35% 98.83% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3216438 1.17% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 276116383 # Type of FU issued -system.cpu2.iq.rate 1.754972 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 396918 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001438 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 644304824 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 285224158 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 274754060 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 88 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 100 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 276429621 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 39 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 673179 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 275284943 # Type of FU issued +system.cpu2.iq.rate 1.761053 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 370855 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001347 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 641401400 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 284227989 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 273934511 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 90 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 102 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 22 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 275577549 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 41 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 638960 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1005768 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 7012 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4597 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 510812 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 974310 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6664 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4257 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 503319 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 656130 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 10580 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 656257 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 10390 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1136839 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 10403399 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 827340 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 278097019 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 73172 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6436780 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3659466 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 241606 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 635543 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 5914 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4597 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 175933 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 181620 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 357553 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 275617670 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6616724 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 498712 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1114642 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9684851 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 815798 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 277229948 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 71784 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6166984 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3428654 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 232570 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 630862 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 4638 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4257 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 175308 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 177843 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 353151 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 274790127 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6353973 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 494815 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9995202 # number of memory reference insts executed -system.cpu2.iew.exec_branches 28042459 # Number of branches executed -system.cpu2.iew.exec_stores 3378478 # Number of stores executed -system.cpu2.iew.exec_rate 1.751802 # Inst execution rate -system.cpu2.iew.wb_sent 275465212 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 274754080 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 213963670 # num instructions producing a value -system.cpu2.iew.wb_consumers 349997640 # num instructions consuming a value +system.cpu2.iew.exec_refs 9504896 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27944071 # Number of branches executed +system.cpu2.iew.exec_stores 3150923 # Number of stores executed +system.cpu2.iew.exec_rate 1.757888 # Inst execution rate +system.cpu2.iew.wb_sent 274642284 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 273934533 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 213583516 # num instructions producing a value +system.cpu2.iew.wb_consumers 349233536 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.746313 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.611329 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.752414 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.611578 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7423416 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 361972 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 317845 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 90429689 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 2.993166 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.871852 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7294558 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357518 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 313650 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 89247046 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 3.024569 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.872131 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 32465154 35.90% 35.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4609597 5.10% 41.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1298624 1.44% 42.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24718633 27.33% 69.77% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 888931 0.98% 70.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 601938 0.67% 71.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 359938 0.40% 71.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23311721 25.78% 97.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2175153 2.41% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 31615758 35.42% 35.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4405793 4.94% 40.36% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1230871 1.38% 41.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24727866 27.71% 69.45% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 857199 0.96% 70.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 581394 0.65% 71.06% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 343629 0.39% 71.44% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23391082 26.21% 97.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2093454 2.35% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 90429689 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 137262623 # Number of instructions committed -system.cpu2.commit.committedOps 270671057 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 89247046 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 136718686 # Number of instructions committed +system.cpu2.commit.committedOps 269933879 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8579665 # Number of memory references committed -system.cpu2.commit.loads 5431011 # Number of loads committed -system.cpu2.commit.membars 163136 # Number of memory barriers committed -system.cpu2.commit.branches 27702153 # Number of branches committed +system.cpu2.commit.refs 8118007 # Number of memory references committed +system.cpu2.commit.loads 5192672 # Number of loads committed +system.cpu2.commit.membars 165488 # Number of memory barriers committed +system.cpu2.commit.branches 27614013 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 247298072 # Number of committed integer instructions. -system.cpu2.commit.function_calls 442677 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 2175153 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 246437097 # Number of committed integer instructions. +system.cpu2.commit.function_calls 432570 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 2093454 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 366318021 # The number of ROB reads -system.cpu2.rob.rob_writes 557330113 # The number of ROB writes -system.cpu2.timesIdled 474514 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 65767262 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4902343932 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 137262623 # Number of Instructions Simulated -system.cpu2.committedOps 270671057 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 137262623 # Number of Instructions Simulated -system.cpu2.cpi 1.146225 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.146225 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.872429 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.872429 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 507419768 # number of integer regfile reads -system.cpu2.int_regfile_writes 327840306 # number of integer regfile writes -system.cpu2.fp_regfile_reads 62468 # number of floating regfile reads -system.cpu2.fp_regfile_writes 62496 # number of floating regfile writes -system.cpu2.misc_regfile_reads 89605766 # number of misc regfile reads -system.cpu2.misc_regfile_writes 140916 # number of misc regfile writes +system.cpu2.rob.rob_reads 364355237 # The number of ROB reads +system.cpu2.rob.rob_writes 555575410 # The number of ROB writes +system.cpu2.timesIdled 476451 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 65956676 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4907452688 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 136718686 # Number of Instructions Simulated +system.cpu2.committedOps 269933879 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 136718686 # Number of Instructions Simulated +system.cpu2.cpi 1.143358 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.143358 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.874617 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.874617 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 365607519 # number of integer regfile reads +system.cpu2.int_regfile_writes 219416427 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72934 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes +system.cpu2.cc_regfile_reads 139623375 # number of cc regfile reads +system.cpu2.cc_regfile_writes 107543298 # number of cc regfile writes +system.cpu2.misc_regfile_reads 89002893 # number of misc regfile reads +system.cpu2.misc_regfile_writes 130765 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index 108881308..e070ad588 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 9be633e93..f7ab26f15 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:20:51 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 01:59:02 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 14bb680f9..5d8366912 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.026877 # Nu sim_ticks 26877484000 # Number of ticks simulated final_tick 26877484000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190344 # Simulator instruction rate (inst/s) -host_op_rate 191711 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56473959 # Simulator tick rate (ticks/s) -host_mem_usage 375760 # Number of bytes of host memory used -host_seconds 475.93 # Real time elapsed on the host +host_inst_rate 158705 # Simulator instruction rate (inst/s) +host_op_rate 159844 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47086787 # Simulator tick rate (ticks/s) +host_mem_usage 380172 # Number of bytes of host memory used +host_seconds 570.81 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 44928 # Number of bytes read from this memory @@ -333,8 +333,8 @@ system.cpu.rename.LSQFullEvents 4597767 # Nu system.cpu.rename.FullRegisterEvents 1304 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 143579240 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 536319966 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536314240 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5726 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 499912232 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 925 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 36165054 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4615 # count of serializing insts renamed diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 5b842e86b..11900168b 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=true numIQEntries=64 +numPhysCCRegs=1280 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 14639c3c6..0a86dbd97 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:21:35 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:42:09 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -18,12 +16,12 @@ All Rights Reserved. nodes : 500 active arcs : 1905 simplex iterations : 1502 -info: Increasing stack size by one page. flow value : 4990014995 new implicit arcs : 23867 active arcs : 25772 simplex iterations : 2663 +info: Increasing stack size by one page. flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 65501881000 because target called exit() +Exiting @ tick 65497052500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 9d42f660f..3b6f53bfa 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,75 +1,75 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065502 # Number of seconds simulated -sim_ticks 65501881000 # Number of ticks simulated -final_tick 65501881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065497 # Number of seconds simulated +sim_ticks 65497052500 # Number of ticks simulated +final_tick 65497052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73961 # Simulator instruction rate (inst/s) -host_op_rate 130234 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30664297 # Simulator tick rate (ticks/s) -host_mem_usage 385548 # Number of bytes of host memory used -host_seconds 2136.10 # Real time elapsed on the host +host_inst_rate 99498 # Simulator instruction rate (inst/s) +host_op_rate 175200 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41248682 # Simulator tick rate (ticks/s) +host_mem_usage 388584 # Number of bytes of host memory used +host_seconds 1587.86 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1882496 # Number of bytes read from this memory -system.physmem.bytes_read::total 1946112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 63616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 63616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10432 # Number of bytes written to this memory -system.physmem.bytes_written::total 10432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29414 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30408 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 163 # Number of write requests responded to by this memory -system.physmem.num_writes::total 163 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 971209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28739572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29710780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 971209 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 971209 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 159263 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 159263 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 159263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 971209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28739572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 29870043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30410 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 163 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 30410 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 163 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 1946112 # Total number of bytes read from memory -system.physmem.bytesWritten 10432 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1946112 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 10432 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q +system.physmem.bytes_read::cpu.inst 63296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1882240 # Number of bytes read from this memory +system.physmem.bytes_read::total 1945536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 63296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 63296 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9984 # Number of bytes written to this memory +system.physmem.bytes_written::total 9984 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 989 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29410 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30399 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 156 # Number of write requests responded to by this memory +system.physmem.num_writes::total 156 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 966395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28737782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29704176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 966395 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 966395 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 152434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 152434 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 152434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 966395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28737782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29856611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30400 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 156 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 30400 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 156 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 1945536 # Total number of bytes read from memory +system.physmem.bytesWritten 9984 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1945536 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 9984 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1921 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 1924 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 2027 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 2030 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 2025 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1924 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 2029 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 1898 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1964 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1963 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 1861 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1939 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1934 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1938 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1932 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 1804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1796 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1797 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 1792 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1800 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1818 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1820 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 1779 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 14 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 101 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 13 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 13 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 14 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 1 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 3 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis @@ -78,23 +78,23 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 65501859000 # Total gap between requests +system.physmem.totGap 65497035500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 30410 # Categorize read packet sizes +system.physmem.readPktSize::6 30400 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 163 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 29912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 364 # What read queue length does an incoming req see +system.physmem.writePktSize::6 156 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 29908 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 365 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 65 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -125,8 +125,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see @@ -143,11 +143,11 @@ system.physmem.wrQLenPdf::14 7 # Wh system.physmem.wrQLenPdf::15 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -157,332 +157,331 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 552 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 3503.884058 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 832.064707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 3839.690246 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 138 25.00% 25.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 47 8.51% 33.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 28 5.07% 38.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 12 2.17% 40.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 14 2.54% 43.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 11 1.99% 45.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 8 1.45% 46.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 4 0.72% 47.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 9 1.63% 49.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 7 1.27% 50.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 4 0.72% 51.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 7 1.27% 52.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 2 0.36% 52.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 2 0.36% 53.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 3 0.54% 53.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 1 0.18% 53.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 9 1.63% 55.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 2 0.36% 55.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 1 0.18% 55.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 1 0.18% 56.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 1 0.18% 56.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 2 0.36% 56.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 1 0.18% 56.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 1 0.18% 57.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 2 0.36% 57.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 1 0.18% 57.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 2 0.36% 57.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 1 0.18% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 1 0.18% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 1 0.18% 58.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 2 0.36% 58.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 1 0.18% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 1 0.18% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 1 0.18% 59.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 1 0.18% 59.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 1 0.18% 59.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 2 0.36% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.18% 60.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.36% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.18% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.18% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 215 38.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 552 # Bytes accessed per row activation -system.physmem.totQLat 7596000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 583088500 # Sum of mem lat for all requests -system.physmem.totBusLat 151800000 # Total cycles spent in databus access -system.physmem.totBankLat 423692500 # Total cycles spent in bank access -system.physmem.avgQLat 250.20 # Average queueing delay per request -system.physmem.avgBankLat 13955.62 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 535 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 3610.915888 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 887.471357 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 3852.235562 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 128 23.93% 23.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 47 8.79% 32.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 24 4.49% 37.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 12 2.24% 39.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 11 2.06% 41.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 11 2.06% 43.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 8 1.50% 45.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 3 0.56% 45.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 9 1.68% 47.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 10 1.87% 49.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2 0.37% 49.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 7 1.31% 50.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1 0.19% 51.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 3 0.56% 51.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.56% 52.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1 0.19% 52.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 9 1.68% 54.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.37% 54.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.19% 54.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 1 0.19% 54.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 1 0.19% 54.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.37% 55.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 1 0.19% 55.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.19% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.37% 56.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 1 0.19% 56.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.37% 56.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.19% 56.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.19% 57.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.19% 57.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.37% 57.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.19% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.19% 57.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.19% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.19% 58.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.19% 58.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 2 0.37% 58.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.19% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.37% 59.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.19% 59.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.19% 59.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 215 40.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 535 # Bytes accessed per row activation +system.physmem.totQLat 5969250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 581474250 # Sum of mem lat for all requests +system.physmem.totBusLat 151785000 # Total cycles spent in databus access +system.physmem.totBankLat 423720000 # Total cycles spent in bank access +system.physmem.avgQLat 196.64 # Average queueing delay per request +system.physmem.avgBankLat 13957.90 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 19205.81 # Average memory access latency -system.physmem.avgRdBW 29.71 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 29.71 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 19154.54 # Average memory access latency +system.physmem.avgRdBW 29.70 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 29.70 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 12.43 # Average write queue length over time -system.physmem.readRowHits 29868 # Number of row buffer hits during reads -system.physmem.writeRowHits 101 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.39 # Average write queue length over time +system.physmem.readRowHits 29864 # Number of row buffer hits during reads +system.physmem.writeRowHits 96 # Number of row buffer hits during writes system.physmem.readRowHitRate 98.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.96 # Row buffer hit rate for writes -system.physmem.avgGap 2142474.05 # Average gap between requests -system.membus.throughput 29869066 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 1406 # Transaction distribution -system.membus.trans_dist::ReadResp 1403 # Transaction distribution -system.membus.trans_dist::Writeback 163 # Transaction distribution -system.membus.trans_dist::ReadExReq 29004 # Transaction distribution -system.membus.trans_dist::ReadExResp 29004 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60980 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60980 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60980 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956480 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956480 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 1956480 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 1956480 # Total data (bytes) +system.physmem.writeRowHitRate 61.54 # Row buffer hit rate for writes +system.physmem.avgGap 2143508.17 # Average gap between requests +system.membus.throughput 29855634 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1399 # Transaction distribution +system.membus.trans_dist::ReadResp 1397 # Transaction distribution +system.membus.trans_dist::Writeback 156 # Transaction distribution +system.membus.trans_dist::ReadExReq 29001 # Transaction distribution +system.membus.trans_dist::ReadExResp 29001 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60954 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60954 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60954 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1955456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1955456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1955456 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1955456 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 35091000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 35006500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 284259500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 284183250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.branchPred.lookups 33859772 # Number of BP lookups -system.cpu.branchPred.condPredicted 33859772 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 774888 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19298286 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19204033 # Number of BTB hits +system.cpu.branchPred.lookups 33858224 # Number of BP lookups +system.cpu.branchPred.condPredicted 33858224 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 774589 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19295548 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19203800 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.511599 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5017180 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5379 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.524512 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5017950 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5443 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 131003766 # number of cpu cycles simulated +system.cpu.numCycles 130994109 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26135908 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 182273755 # Number of instructions fetch has processed -system.cpu.fetch.Branches 33859772 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24221213 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 55461769 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5355546 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 44756866 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 381 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 26134025 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 182258914 # Number of instructions fetch has processed +system.cpu.fetch.Branches 33858224 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24221750 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 55458228 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5352681 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 44757241 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 56 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 354 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 1 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 25575264 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 165870 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 130900361 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.454854 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.314999 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 25574362 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 166199 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 130892614 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.454818 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.314961 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 77915453 59.52% 59.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1959993 1.50% 61.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2942167 2.25% 63.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3834775 2.93% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7768215 5.93% 72.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757692 3.63% 75.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2664580 2.04% 77.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1316041 1.01% 78.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 27741445 21.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77910684 59.52% 59.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1961091 1.50% 61.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2941416 2.25% 63.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3833946 2.93% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7767539 5.93% 72.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4757616 3.63% 75.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2666164 2.04% 77.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1316720 1.01% 78.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27737438 21.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 130900361 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258464 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.391363 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36822089 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 36980976 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 43893831 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8658090 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4545375 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 318858939 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 4545375 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42309692 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9552635 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7405 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46756316 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27728938 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 315018359 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 180 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26669 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25876041 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 477 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 317189446 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 836531493 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 836530400 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1093 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 130892614 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258471 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.391352 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36819659 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36980368 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 43894473 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8655405 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4542709 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 318839804 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 4542709 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42306626 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9548363 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7363 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46754553 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27733000 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 314999780 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 245 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26808 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25879667 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 317173158 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 836491506 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 515038229 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 344 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37976699 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 479 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 477 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62612991 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 101555768 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 34778786 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39638216 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5865755 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 311479938 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1623 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 300277679 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 89964 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32707513 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 46093052 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1178 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 130900361 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.293941 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.699121 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 37960411 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 483 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62657657 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 101560400 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 34776362 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39636404 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5873969 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 311477073 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1619 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 300261813 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 90477 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32704303 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 46143152 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1174 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 130892614 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.293955 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.698909 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24175636 18.47% 18.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23209060 17.73% 36.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25458730 19.45% 55.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25817772 19.72% 75.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18910783 14.45% 89.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8235477 6.29% 96.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3954804 3.02% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 956290 0.73% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181809 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24143436 18.45% 18.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23235636 17.75% 36.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25474582 19.46% 55.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25828603 19.73% 75.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18887958 14.43% 89.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8220714 6.28% 96.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3961121 3.03% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 955436 0.73% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 185128 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 130900361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 130892614 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31412 1.53% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1912178 93.02% 94.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 111979 5.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 31366 1.52% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1915737 93.06% 94.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 111488 5.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 31276 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 169839925 56.56% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11359 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 330 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 35 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97303672 32.40% 88.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33091082 11.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 169828970 56.56% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11213 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 334 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97302750 32.41% 88.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33087237 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 300277679 # Type of FU issued -system.cpu.iq.rate 2.292130 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2055569 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006846 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 733600907 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344221068 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 298025850 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 345 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 456 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 123 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302301800 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54184658 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 300261813 # Type of FU issued +system.cpu.iq.rate 2.292178 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2058591 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006856 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 733564971 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344215080 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 298003281 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 337 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 435 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 126 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302288959 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 169 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54190051 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10776383 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 30894 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33570 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3339034 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10781015 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 32177 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33336 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3336610 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3237 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8568 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3220 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8613 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4545375 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2618322 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 161863 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 311481561 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 197279 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 101555768 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 34778786 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 468 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2613 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73457 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33570 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393653 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 427979 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 821632 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 298876380 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 96891177 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1401299 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4542709 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2622554 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 162089 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 311478692 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 196017 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 101560400 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 34776362 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 469 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2626 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73556 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33336 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 393441 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 427689 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 821130 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 298856938 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 96890588 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1404875 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 129818452 # number of memory reference insts executed -system.cpu.iew.exec_branches 30820594 # Number of branches executed -system.cpu.iew.exec_stores 32927275 # Number of stores executed -system.cpu.iew.exec_rate 2.281433 # Inst execution rate -system.cpu.iew.wb_sent 298395371 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 298025973 # cumulative count of insts written-back -system.cpu.iew.wb_producers 218267458 # num instructions producing a value -system.cpu.iew.wb_consumers 296778027 # num instructions consuming a value +system.cpu.iew.exec_refs 129814899 # number of memory reference insts executed +system.cpu.iew.exec_branches 30818444 # Number of branches executed +system.cpu.iew.exec_stores 32924311 # Number of stores executed +system.cpu.iew.exec_rate 2.281453 # Inst execution rate +system.cpu.iew.wb_sent 298373185 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 298003407 # cumulative count of insts written-back +system.cpu.iew.wb_producers 218253384 # num instructions producing a value +system.cpu.iew.wb_consumers 296750864 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.274942 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.735457 # average fanout of values written-back +system.cpu.iew.wb_rate 2.274937 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.735477 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 33301924 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 33298978 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 774937 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 126354986 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.201674 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.972574 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 774634 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126349905 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.201762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.972659 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 58072502 45.96% 45.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19158205 15.16% 61.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11637077 9.21% 70.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9445238 7.48% 77.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1852713 1.47% 79.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2072442 1.64% 80.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1294957 1.02% 81.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 693229 0.55% 82.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22128623 17.51% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58072656 45.96% 45.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19155409 15.16% 61.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11632100 9.21% 70.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9445412 7.48% 77.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1855076 1.47% 79.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2067896 1.64% 80.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1301136 1.03% 81.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 691741 0.55% 82.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22128479 17.51% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 126354986 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126349905 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -491,92 +490,94 @@ system.cpu.commit.loads 90779385 # Nu system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 29309705 # Number of branches committed system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. -system.cpu.commit.int_insts 278186174 # Number of committed integer instructions. +system.cpu.commit.int_insts 278169481 # Number of committed integer instructions. system.cpu.commit.function_calls 4237596 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22128623 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22128479 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 415720751 # The number of ROB reads -system.cpu.rob.rob_writes 627537958 # The number of ROB writes -system.cpu.timesIdled 13918 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 103405 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 415712868 # The number of ROB reads +system.cpu.rob.rob_writes 627529396 # The number of ROB writes +system.cpu.timesIdled 13705 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 101495 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.829198 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.829198 # CPI: Total CPI of All Threads -system.cpu.ipc 1.205985 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.205985 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 590807496 # number of integer regfile reads -system.cpu.int_regfile_writes 298603166 # number of integer regfile writes -system.cpu.fp_regfile_reads 109 # number of floating regfile reads -system.cpu.fp_regfile_writes 74 # number of floating regfile writes -system.cpu.misc_regfile_reads 191829835 # number of misc regfile reads +system.cpu.cpi 0.829137 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.829137 # CPI: Total CPI of All Threads +system.cpu.ipc 1.206074 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.206074 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 483722109 # number of integer regfile reads +system.cpu.int_regfile_writes 234582139 # number of integer regfile writes +system.cpu.fp_regfile_reads 117 # number of floating regfile reads +system.cpu.fp_regfile_writes 75 # number of floating regfile writes +system.cpu.cc_regfile_reads 107053198 # number of cc regfile reads +system.cpu.cc_regfile_writes 64000024 # number of cc regfile writes +system.cpu.misc_regfile_reads 191821503 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 4049183259 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1995273 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995270 # Transaction distribution +system.cpu.toL2Bus.throughput 4049501312 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1995298 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995296 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2066630 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82305 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82305 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2020 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6221783 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265164480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 265229120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 265229120 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 82299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82299 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2012 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219810 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6221822 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265166016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 265230400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 265230400 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4138734000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 4138743500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1707500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1699750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3122065000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3122104250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) -system.cpu.icache.tags.replacements 57 # number of replacements -system.cpu.icache.tags.tagsinuse 818.042584 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25573967 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1010 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25320.759406 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 55 # number of replacements +system.cpu.icache.tags.tagsinuse 816.683247 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25573067 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1006 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25420.543738 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 818.042584 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.399435 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.399435 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25573967 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25573967 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25573967 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25573967 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25573967 # number of overall hits -system.cpu.icache.overall_hits::total 25573967 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1297 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1297 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1297 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1297 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1297 # number of overall misses -system.cpu.icache.overall_misses::total 1297 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 86393250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 86393250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 86393250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 86393250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 86393250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 86393250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25575264 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25575264 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25575264 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25575264 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25575264 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25575264 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 816.683247 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.398771 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.398771 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25573067 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25573067 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25573067 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25573067 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25573067 # number of overall hits +system.cpu.icache.overall_hits::total 25573067 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1295 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1295 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1295 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1295 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1295 # number of overall misses +system.cpu.icache.overall_misses::total 1295 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 85604250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 85604250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 85604250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 85604250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 85604250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 85604250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25574362 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25574362 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25574362 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25574362 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25574362 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25574362 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66610.061681 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66610.061681 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66610.061681 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66610.061681 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66610.061681 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66610.061681 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66103.667954 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66103.667954 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66103.667954 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66103.667954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66103.667954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66103.667954 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 113 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -585,120 +586,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 37.666667 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 287 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 287 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 287 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 287 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 287 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1010 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1010 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1010 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1010 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68485500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 68485500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68485500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 68485500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68485500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 68485500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 289 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 289 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 289 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 289 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 289 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 289 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1006 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1006 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1006 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1006 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1006 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1006 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67541250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 67541250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67541250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 67541250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67541250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 67541250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67807.425743 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67807.425743 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67807.425743 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67807.425743 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67807.425743 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67807.425743 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67138.419483 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67138.419483 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67138.419483 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67138.419483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67138.419483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67138.419483 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 474 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20820.406004 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4029365 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30391 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.584153 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 461 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20819.547231 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4029398 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30381 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.628880 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19907.577759 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 667.404621 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 245.423625 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.607531 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020368 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007490 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.635388 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1993851 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1993867 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 19905.791561 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 667.283783 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 246.471887 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.607477 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020364 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007522 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.635362 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1993882 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1993899 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2066630 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 2066630 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 53301 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 53301 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2047152 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2047168 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2047152 # number of overall hits -system.cpu.l2cache.overall_hits::total 2047168 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 994 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 412 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1406 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 29004 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 29004 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 994 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29416 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30410 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 994 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29416 # number of overall misses -system.cpu.l2cache.overall_misses::total 30410 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 67308000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28553000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 95861000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1783241500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1783241500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 67308000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1811794500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1879102500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 67308000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1811794500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1879102500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1010 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1994263 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1995273 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 53298 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 53298 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2047180 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2047197 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2047180 # number of overall hits +system.cpu.l2cache.overall_hits::total 2047197 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 989 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 410 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1399 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 29001 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 29001 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 989 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29411 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30400 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 989 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29411 # number of overall misses +system.cpu.l2cache.overall_misses::total 30400 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 66362250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 27817000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94179250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1783074500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1783074500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 66362250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1810891500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1877253750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 66362250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1810891500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1877253750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1006 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1994292 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1995298 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 2066630 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 2066630 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 82305 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 82305 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1010 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076568 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077578 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1010 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076568 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077578 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984158 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000207 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000705 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352397 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.352397 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984158 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014166 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014637 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984158 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014166 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014637 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67714.285714 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69303.398058 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68179.943101 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61482.605847 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61482.605847 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67714.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61592.143731 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 61792.255837 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67714.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61592.143731 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 61792.255837 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82299 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82299 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1006 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076591 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077597 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1006 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076591 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077597 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983101 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000206 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000701 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.352386 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.352386 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983101 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014163 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014632 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983101 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014163 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014632 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67100.353893 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67846.341463 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67318.977841 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61483.207476 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61483.207476 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67100.353893 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61571.911870 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 61751.768092 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67100.353893 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61571.911870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 61751.768092 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -707,160 +708,160 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 163 # number of writebacks -system.cpu.l2cache.writebacks::total 163 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 994 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 412 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1406 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29004 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 29004 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 994 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29416 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30410 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 994 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29416 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30410 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 54811000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23413500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 78224500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1417981500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1417981500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 54811000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1441395000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1496206000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 54811000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1441395000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1496206000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984158 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000207 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000705 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352397 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352397 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984158 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014166 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014637 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984158 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014166 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014637 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55141.851107 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56828.883495 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55636.201991 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 48889.170459 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 48889.170459 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55141.851107 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49000.373946 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49201.118053 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55141.851107 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49000.373946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49201.118053 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 156 # number of writebacks +system.cpu.l2cache.writebacks::total 156 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 989 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 410 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1399 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29001 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29001 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 989 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29411 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30400 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 989 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29411 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30400 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53927250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22692500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 76619750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1417840500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1417840500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53927250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1440533000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1494460250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53927250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1440533000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1494460250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983101 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000206 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000701 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352386 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352386 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983101 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014163 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014632 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983101 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014163 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014632 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54527.047523 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55347.560976 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54767.512509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 48889.365884 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 48889.365884 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54527.047523 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48979.395464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49159.876645 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54527.047523 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48979.395464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49159.876645 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2072469 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.884717 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71377775 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076565 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.373003 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20648680250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.884717 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 2072493 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.881910 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71371808 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076589 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.369732 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20650704250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.881910 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993624 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993624 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40036076 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40036076 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341699 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341699 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71377775 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71377775 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71377775 # number of overall hits -system.cpu.dcache.overall_hits::total 71377775 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2626397 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2626397 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 98053 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 98053 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2724450 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2724450 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2724450 # number of overall misses -system.cpu.dcache.overall_misses::total 2724450 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31390082250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31390082250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2686066747 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2686066747 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34076148997 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34076148997 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34076148997 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34076148997 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42662473 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42662473 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 40030061 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40030061 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31341747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31341747 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71371808 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71371808 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71371808 # number of overall hits +system.cpu.dcache.overall_hits::total 71371808 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2626396 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2626396 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 98005 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 98005 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2724401 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2724401 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2724401 # number of overall misses +system.cpu.dcache.overall_misses::total 2724401 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31387330250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31387330250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2685755248 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2685755248 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34073085498 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34073085498 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34073085498 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34073085498 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42656457 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42656457 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74102225 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74102225 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74102225 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74102225 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061562 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061562 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036766 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036766 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036766 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036766 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11951.765955 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11951.765955 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27394.029219 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27394.029219 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12507.533262 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12507.533262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12507.533262 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12507.533262 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32680 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 74096209 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74096209 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74096209 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74096209 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061571 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061571 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003117 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003117 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036768 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036768 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036768 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036768 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11950.722682 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11950.722682 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27404.267619 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27404.267619 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12506.633751 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12506.633751 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12506.633751 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12506.633751 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32988 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9460 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9490 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.454545 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.476080 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 2066630 # number of writebacks system.cpu.dcache.writebacks::total 2066630 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 632021 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 632021 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15861 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 15861 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 647882 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 647882 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 647882 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 647882 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994376 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994376 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82192 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82192 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076568 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076568 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076568 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076568 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994845000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994845000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2397806497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2397806497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24392651497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24392651497 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24392651497 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24392651497 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046748 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046748 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631996 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 631996 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15814 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 15814 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 647810 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 647810 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647810 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647810 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994400 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994400 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82191 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82191 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076591 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076591 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076591 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076591 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994515250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994515250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2397679498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2397679498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24392194748 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24392194748 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24392194748 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24392194748 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046755 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046755 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002614 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002614 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028023 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028023 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028023 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028023 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.434458 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.434458 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29173.234585 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29173.234585 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11746.618217 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11746.618217 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11746.618217 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11746.618217 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028026 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028026 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028026 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028026 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.136407 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.136407 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29172.044360 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29172.044360 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11746.268162 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11746.268162 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11746.268162 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11746.268162 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout index 670a5ba2d..98402c27f 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic/simout -Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:52:30 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:43:36 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index fcf1f6acc..d28c1e1a8 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu sim_ticks 168950040000 # Number of ticks simulated final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 992711 # Simulator instruction rate (inst/s) -host_op_rate 1748005 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1061587108 # Simulator tick rate (ticks/s) -host_mem_usage 424044 # Number of bytes of host memory used -host_seconds 159.15 # Real time elapsed on the host +host_inst_rate 1229454 # Simulator instruction rate (inst/s) +host_op_rate 2164871 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1314755229 # Simulator tick rate (ticks/s) +host_mem_usage 378084 # Number of bytes of host memory used +host_seconds 128.50 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory @@ -42,16 +42,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 8475189 # number of times a function call or return occured system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls -system.cpu.num_int_insts 278186175 # number of integer instructions +system.cpu.num_int_insts 278169482 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 739520003 # number of times the integer registers were read -system.cpu.num_int_register_writes 279212721 # number of times the integer registers were written +system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read +system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written +system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read +system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written system.cpu.num_mem_refs 122219137 # number of memory refs system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index 2c70ca6cf..033910815 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:32:00 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:48:06 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index 2b38a25ba..fa71cbd3c 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.365989 # Nu sim_ticks 365989065000 # Number of ticks simulated final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 324809 # Simulator instruction rate (inst/s) -host_op_rate 571936 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 752437231 # Simulator tick rate (ticks/s) -host_mem_usage 382748 # Number of bytes of host memory used -host_seconds 486.40 # Real time elapsed on the host +host_inst_rate 746941 # Simulator instruction rate (inst/s) +host_op_rate 1315244 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1730329772 # Simulator tick rate (ticks/s) +host_mem_usage 386536 # Number of bytes of host memory used +host_seconds 211.51 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory @@ -58,16 +58,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278186175 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses system.cpu.num_func_calls 8475189 # number of times a function call or return occured system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls -system.cpu.num_int_insts 278186175 # number of integer instructions +system.cpu.num_int_insts 278169482 # number of integer instructions system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 739520003 # number of times the integer registers were read -system.cpu.num_int_register_writes 279212721 # number of times the integer registers were written +system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read +system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written system.cpu.num_fp_register_reads 40 # number of times the floating registers were read system.cpu.num_fp_register_writes 26 # number of times the floating registers were written +system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read +system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written system.cpu.num_mem_refs 122219137 # number of memory refs system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 7756821bd..01aecce27 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 27bb412f8..cb7300a3e 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 07:58:36 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:08:48 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index d58d3f98b..76f42f35e 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.202350 # Nu sim_ticks 202349747500 # Number of ticks simulated final_tick 202349747500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95439 # Simulator instruction rate (inst/s) -host_op_rate 107602 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38223736 # Simulator tick rate (ticks/s) -host_mem_usage 246676 # Number of bytes of host memory used -host_seconds 5293.82 # Real time elapsed on the host +host_inst_rate 125600 # Simulator instruction rate (inst/s) +host_op_rate 141606 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50303215 # Simulator tick rate (ticks/s) +host_mem_usage 251352 # Number of bytes of host memory used +host_seconds 4022.61 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 216896 # Number of bytes read from this memory @@ -416,8 +416,8 @@ system.cpu.rename.LSQFullEvents 8947899 # Nu system.cpu.rename.FullRegisterEvents 349 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 954230037 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 3500483849 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3500482489 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1360 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 3242011448 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 408 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 287977746 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 2292997 # count of serializing insts renamed diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 6ab0a9e51..60a82514d 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=true numIQEntries=64 +numPhysCCRegs=1280 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 29b59675c..5d75453d9 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,15 +1,28 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 1 2013 21:55:52 -gem5 started Oct 1 2013 22:49:39 -gem5 executing on steam +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 02:08:50 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: *********info: Increasing stack size by one page. -**************************************** +**********************************info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +****** 58924 words stored in 3784810 bytes @@ -21,18 +34,8 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success -info: Increasing stack size by one page. -info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -72,11 +75,9 @@ info: Increasing stack size by one page. the man with whom I play tennis is here there is a dog in the park this is not the man we know and love -info: Increasing stack size by one page. -info: Increasing stack size by one page. we like to eat at restaurants , usually on weekends what did John say he thought you should do about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 458275427000 because target called exit() +Exiting @ tick 458276279000 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 7e5dfb93e..c15724aa4 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.458275 # Number of seconds simulated -sim_ticks 458275427000 # Number of ticks simulated -final_tick 458275427000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.458276 # Number of seconds simulated +sim_ticks 458276279000 # Number of ticks simulated +final_tick 458276279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66021 # Simulator instruction rate (inst/s) -host_op_rate 122081 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36590577 # Simulator tick rate (ticks/s) -host_mem_usage 346580 # Number of bytes of host memory used -host_seconds 12524.41 # Real time elapsed on the host +host_inst_rate 81967 # Simulator instruction rate (inst/s) +host_op_rate 151565 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45427941 # Simulator tick rate (ticks/s) +host_mem_usage 343960 # Number of bytes of host memory used +host_seconds 10087.98 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 202752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24473408 # Number of bytes read from this memory -system.physmem.bytes_read::total 24676160 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18786624 # Number of bytes written to this memory -system.physmem.bytes_written::total 18786624 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382397 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385565 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293541 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293541 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53403274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53845697 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442424 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40994177 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40994177 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40994177 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53403274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94839875 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385565 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 293541 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 385565 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 293541 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 24676160 # Total number of bytes read from memory -system.physmem.bytesWritten 18786624 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24676160 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18786624 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 158 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 130355 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 24064 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 26434 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 24675 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 24503 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 23662 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24409 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24202 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 23617 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 23804 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24780 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24047 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 23248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 22961 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 23770 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23994 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 18525 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 19820 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 18911 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18030 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18408 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18975 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18544 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 18098 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18807 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 17702 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 17351 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 16955 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 17708 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 17829 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 202688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24475520 # Number of bytes read from this memory +system.physmem.bytes_read::total 24678208 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202688 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18791744 # Number of bytes written to this memory +system.physmem.bytes_written::total 18791744 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382430 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385597 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293621 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293621 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442283 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53407783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53850066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442283 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442283 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41005273 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41005273 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41005273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442283 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53407783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94855339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385597 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 293621 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 385597 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 293621 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 24678208 # Total number of bytes read from memory +system.physmem.bytesWritten 18791744 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24678208 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18791744 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 167 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 129454 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 24004 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 26368 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 24819 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 24535 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 23690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24438 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24255 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 23670 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 23840 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 23982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 23151 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 22850 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 23658 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23921 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 18532 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 19819 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18953 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 18919 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18083 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18410 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18967 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18941 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18561 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18114 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 17718 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 17344 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 16935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 17686 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 17818 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 13 # Number of times wr buffer was full causing retry -system.physmem.totGap 458275318500 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times wr buffer was full causing retry +system.physmem.totGap 458276251500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385565 # Categorize read packet sizes +system.physmem.readPktSize::6 385597 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 293541 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 380824 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293621 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 380795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -125,346 +125,346 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12731 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 12731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 125751 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 345.531089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 162.070662 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 668.026506 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 53960 42.91% 42.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 23382 18.59% 61.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 10554 8.39% 69.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 6402 5.09% 74.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 3989 3.17% 78.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 2874 2.29% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 2122 1.69% 82.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1769 1.41% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 1442 1.15% 84.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 1166 0.93% 85.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 1242 0.99% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 1075 0.85% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 727 0.58% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 689 0.55% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 609 0.48% 89.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 572 0.45% 89.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 523 0.42% 89.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 500 0.40% 90.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 598 0.48% 90.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 763 0.61% 91.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 633 0.50% 91.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 692 0.55% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 6202 4.93% 97.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 529 0.42% 97.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 343 0.27% 98.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 283 0.23% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 212 0.17% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 156 0.12% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 148 0.12% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 111 0.09% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 101 0.08% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 82 0.07% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 91 0.07% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 56 0.04% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 52 0.04% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 46 0.04% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 44 0.03% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 29 0.02% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 32 0.03% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 21 0.02% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 22 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 18 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 15 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 19 0.02% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 11 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 25 0.02% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 22 0.02% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 17 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 13 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 10 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 18 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 10 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 20 0.02% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 6 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 12 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 10 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 13 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 9 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 10 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 10 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 11 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 7 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 9 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 5 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 10 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 4 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 8 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 6 0.00% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 3 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 5 0.00% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 7 0.01% 99.57% # Bytes accessed per row activation +system.physmem.wrQLenPdf::31 13 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 125846 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.334329 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.235120 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 666.634247 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 53836 42.78% 42.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 23576 18.73% 61.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 10431 8.29% 69.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 6405 5.09% 74.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 4091 3.25% 78.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 2950 2.34% 80.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 2205 1.75% 82.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1721 1.37% 83.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 1423 1.13% 84.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 1129 0.90% 85.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 1178 0.94% 86.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 1088 0.86% 87.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 719 0.57% 88.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 691 0.55% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 593 0.47% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 590 0.47% 89.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 543 0.43% 89.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 555 0.44% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 625 0.50% 90.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 694 0.55% 91.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 625 0.50% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 735 0.58% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 6224 4.95% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 501 0.40% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 329 0.26% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 262 0.21% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 235 0.19% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 154 0.12% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 168 0.13% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 127 0.10% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 91 0.07% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 78 0.06% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 63 0.05% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 57 0.05% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 48 0.04% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 48 0.04% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 32 0.03% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 31 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 30 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 21 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 34 0.03% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 24 0.02% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 22 0.02% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 28 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 22 0.02% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 15 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 11 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 26 0.02% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 10 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 12 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 9 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 17 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 8 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 11 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 10 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 14 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 11 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 10 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 9 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 9 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 11 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 6 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 4 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 11 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 3 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 5 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 10 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 5 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 4 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 4 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 4 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 4 0.00% 99.56% # Bytes accessed per row activation system.physmem.bytesPerActivate::4864-4865 7 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 3 0.00% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 6 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 5 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 8 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 6 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 12 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 8 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 6 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 4 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 1 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 5 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 5 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 4 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 6 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 6 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 3 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 6 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 10 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 9 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 8 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 3 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 5 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 3 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 4 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 2 0.00% 99.65% # Bytes accessed per row activation system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 3 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 7 0.01% 99.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 7 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 4 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 4 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::6784-6785 3 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 5 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 3 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 3 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 3 0.00% 99.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7809 3 0.00% 99.69% # Bytes accessed per row activation system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 3 0.00% 99.70% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 3 0.00% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 378 0.30% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 125751 # Bytes accessed per row activation -system.physmem.totQLat 3033779750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11207673500 # Sum of mem lat for all requests -system.physmem.totBusLat 1927035000 # Total cycles spent in databus access -system.physmem.totBankLat 6246858750 # Total cycles spent in bank access -system.physmem.avgQLat 7871.63 # Average queueing delay per request -system.physmem.avgBankLat 16208.47 # Average bank access latency per request +system.physmem.bytesPerActivate::8192-8193 376 0.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 125846 # Bytes accessed per row activation +system.physmem.totQLat 3013395500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11189631750 # Sum of mem lat for all requests +system.physmem.totBusLat 1927150000 # Total cycles spent in databus access +system.physmem.totBankLat 6249086250 # Total cycles spent in bank access +system.physmem.avgQLat 7818.27 # Average queueing delay per request +system.physmem.avgBankLat 16213.28 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29080.10 # Average memory access latency +system.physmem.avgMemAccLat 29031.55 # Average memory access latency system.physmem.avgRdBW 53.85 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 40.99 # Average achieved write bandwidth in MB/s +system.physmem.avgWrBW 41.01 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 53.85 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 40.99 # Average consumed write bandwidth in MB/s +system.physmem.avgConsumedWrBW 41.01 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 10.19 # Average write queue length over time -system.physmem.readRowHits 346237 # Number of row buffer hits during reads -system.physmem.writeRowHits 206945 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 70.50 # Row buffer hit rate for writes -system.physmem.avgGap 674821.48 # Average gap between requests -system.membus.throughput 94839875 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178718 # Transaction distribution -system.membus.trans_dist::ReadResp 178718 # Transaction distribution -system.membus.trans_dist::Writeback 293541 # Transaction distribution -system.membus.trans_dist::UpgradeReq 130355 # Transaction distribution -system.membus.trans_dist::UpgradeResp 130355 # Transaction distribution -system.membus.trans_dist::ReadExReq 206847 # Transaction distribution -system.membus.trans_dist::ReadExResp 206847 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1325381 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1325381 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1325381 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43462784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43462784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43462784 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43462784 # Total data (bytes) +system.physmem.avgWrQLen 10.13 # Average write queue length over time +system.physmem.readRowHits 346215 # Number of row buffer hits during reads +system.physmem.writeRowHits 206987 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.49 # Row buffer hit rate for writes +system.physmem.avgGap 674711.58 # Average gap between requests +system.membus.throughput 94855339 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178753 # Transaction distribution +system.membus.trans_dist::ReadResp 178753 # Transaction distribution +system.membus.trans_dist::Writeback 293621 # Transaction distribution +system.membus.trans_dist::UpgradeReq 129454 # Transaction distribution +system.membus.trans_dist::UpgradeResp 129454 # Transaction distribution +system.membus.trans_dist::ReadExReq 206844 # Transaction distribution +system.membus.trans_dist::ReadExResp 206844 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1323723 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1323723 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1323723 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469952 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469952 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43469952 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43469952 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3388183000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3387419250 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3900602651 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3898953053 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.branchPred.lookups 205585963 # Number of BP lookups -system.cpu.branchPred.condPredicted 205585963 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9896898 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117084329 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114697569 # Number of BTB hits +system.cpu.branchPred.lookups 205598458 # Number of BP lookups +system.cpu.branchPred.condPredicted 205598458 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9896380 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117174051 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114692881 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.961503 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25058112 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1791626 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.882492 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25059076 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1793638 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 916710548 # number of cpu cycles simulated +system.cpu.numCycles 916711426 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167348410 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131642862 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205585963 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139755681 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352231951 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71067415 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 303674725 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 47310 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 248698 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162008096 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2545258 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 884470252 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.380434 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325121 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167358741 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131763090 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205598458 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139751957 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352259726 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71078928 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 303625713 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 47908 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 254198 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 85 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 162013852 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2539166 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 884476430 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.380618 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325214 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 536305374 60.64% 60.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23381398 2.64% 63.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25249677 2.85% 66.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27894624 3.15% 69.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17755657 2.01% 71.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22913193 2.59% 73.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29422157 3.33% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26648623 3.01% 80.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174899549 19.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 536284008 60.63% 60.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23384253 2.64% 63.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25253496 2.86% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27902300 3.15% 69.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17749201 2.01% 71.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22913352 2.59% 73.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29416028 3.33% 77.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26647385 3.01% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174926407 19.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 884470252 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224265 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.234460 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222591066 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 258702766 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295279341 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46977961 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60919118 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071200226 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 884476430 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224278 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.234590 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222500802 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258763432 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295392395 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 46889742 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60930059 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071354254 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60919118 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 256021570 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 114401726 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17692 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306707585 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146402561 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035040457 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 18320 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24691093 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106444419 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 265 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2137898681 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5150156292 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5150048563 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 107729 # Number of floating rename lookups +system.cpu.rename.SquashCycles 60930059 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 255984410 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 114277740 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18348 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306680368 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146585505 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035184371 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 17660 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24877077 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106438010 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2138008878 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5150477195 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3273486109 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 27867 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 523857827 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1226 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1159 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 345797829 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495831912 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194432339 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195703509 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55003285 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975319588 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13057 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772061886 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 486216 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441442603 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 734769754 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12505 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 884470252 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.003529 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.883234 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 523968024 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1260 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1188 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 346256555 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495848123 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194451746 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195373810 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54752041 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975440933 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 14060 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772196947 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 491373 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441593338 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 734714175 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13508 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 884476430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.003668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.883218 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 268041211 30.31% 30.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151493171 17.13% 47.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137403926 15.54% 62.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131820403 14.90% 77.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91692561 10.37% 88.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55993839 6.33% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34399481 3.89% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11841951 1.34% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1783709 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 267871954 30.29% 30.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151795933 17.16% 47.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137193879 15.51% 62.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131984117 14.92% 77.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91584837 10.35% 88.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 55972472 6.33% 94.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34407043 3.89% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11912621 1.35% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1753574 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 884470252 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 884476430 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4921151 32.49% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.49% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7620621 50.31% 82.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2606942 17.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4900873 32.33% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7664927 50.56% 82.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2594883 17.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2621205 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165737036 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 353398 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880807 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2622931 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165806661 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 353241 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880883 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued @@ -491,84 +491,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429244538 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170224897 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429278261 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170254965 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772061886 # Type of FU issued -system.cpu.iq.rate 1.933066 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15148714 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008549 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4444213917 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2416999842 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744830269 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15037 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 32010 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3518 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784582309 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7086 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172513794 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772196947 # Type of FU issued +system.cpu.iq.rate 1.933211 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15160683 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008555 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4444507102 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2417272272 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744936391 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15278 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 33048 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3640 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784727445 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7254 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172555642 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111729755 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 382662 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 328443 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45273076 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111746790 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 385650 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 328822 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45291560 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 15362 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 587 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 15317 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 618 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60919118 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 66781934 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7163097 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975332645 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 792462 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495831912 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194433262 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3156 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4458880 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83353 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 328443 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5899350 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4421061 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10320411 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1752917873 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424115674 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19144013 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60930059 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 66792766 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7181188 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975454993 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 789344 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495848947 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194451746 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3446 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4469390 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 83563 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 328822 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5897715 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4420728 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10318443 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1753033326 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424140898 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19163621 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590898440 # number of memory reference insts executed -system.cpu.iew.exec_branches 167466606 # Number of branches executed -system.cpu.iew.exec_stores 166782766 # Number of stores executed -system.cpu.iew.exec_rate 1.912183 # Inst execution rate -system.cpu.iew.wb_sent 1749674904 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744833787 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1325104556 # num instructions producing a value -system.cpu.iew.wb_consumers 1945968985 # num instructions consuming a value +system.cpu.iew.exec_refs 590949993 # number of memory reference insts executed +system.cpu.iew.exec_branches 167484534 # Number of branches executed +system.cpu.iew.exec_stores 166809095 # Number of stores executed +system.cpu.iew.exec_rate 1.912307 # Inst execution rate +system.cpu.iew.wb_sent 1749784390 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744940031 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1325078811 # num instructions producing a value +system.cpu.iew.wb_consumers 1946006295 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.903364 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680948 # average fanout of values written-back +system.cpu.iew.wb_rate 1.903478 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680922 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446372129 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446495753 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9924639 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823551134 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.856580 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.437034 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9924967 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 823546371 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.856591 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.436968 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 331597809 40.26% 40.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193248476 23.47% 63.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63098135 7.66% 71.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92588887 11.24% 82.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24967401 3.03% 85.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27517381 3.34% 89.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9278594 1.13% 90.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11386387 1.38% 91.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69868064 8.48% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 331540397 40.26% 40.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193316161 23.47% 63.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63109500 7.66% 71.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92579702 11.24% 82.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24975285 3.03% 85.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27432624 3.33% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9320772 1.13% 90.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11449898 1.39% 91.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69822032 8.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823551134 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 823546371 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -577,228 +577,230 @@ system.cpu.commit.loads 384102157 # Nu system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 149758583 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. +system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69868064 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69822032 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2729043900 # The number of ROB reads -system.cpu.rob.rob_writes 4011801822 # The number of ROB writes -system.cpu.timesIdled 3353209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32240296 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2729208793 # The number of ROB reads +system.cpu.rob.rob_writes 4012058416 # The number of ROB writes +system.cpu.timesIdled 3349890 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32234996 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.108642 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.108642 # CPI: Total CPI of All Threads -system.cpu.ipc 0.902005 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.902005 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3313398089 # number of integer regfile reads -system.cpu.int_regfile_writes 1825851160 # number of integer regfile writes -system.cpu.fp_regfile_reads 3505 # number of floating regfile reads -system.cpu.fp_regfile_writes 24 # number of floating regfile writes -system.cpu.misc_regfile_reads 964629229 # number of misc regfile reads +system.cpu.cpi 1.108643 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.108643 # CPI: Total CPI of All Threads +system.cpu.ipc 0.902004 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.902004 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2716444328 # number of integer regfile reads +system.cpu.int_regfile_writes 1420478428 # number of integer regfile writes +system.cpu.fp_regfile_reads 3628 # number of floating regfile reads +system.cpu.fp_regfile_writes 22 # number of floating regfile writes +system.cpu.cc_regfile_reads 597234249 # number of cc regfile reads +system.cpu.cc_regfile_writes 405441134 # number of cc regfile writes +system.cpu.misc_regfile_reads 964696527 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 698744583 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1900899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1900898 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330727 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 131758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 131758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771773 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 145540 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7662191 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7807731 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 437888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311340864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311778752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311778752 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8438720 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4901666269 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 698612009 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1899997 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1899996 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330686 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 130874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 130874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771776 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771776 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 144643 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7660372 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7805015 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 437696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311337920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 311775616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311775616 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8381696 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4900939314 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 208719992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 207374491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3959172045 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3958743651 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5320 # number of replacements -system.cpu.icache.tags.tagsinuse 1038.062732 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 161865564 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6903 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23448.582355 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5318 # number of replacements +system.cpu.icache.tags.tagsinuse 1036.794557 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 161872030 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6894 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23480.131999 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1038.062732 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506867 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506867 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161867461 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161867461 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161867461 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161867461 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161867461 # number of overall hits -system.cpu.icache.overall_hits::total 161867461 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 140635 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 140635 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 140635 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 140635 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 140635 # number of overall misses -system.cpu.icache.overall_misses::total 140635 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 923937485 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 923937485 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 923937485 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 923937485 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 923937485 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 923937485 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162008096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162008096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162008096 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162008096 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162008096 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162008096 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000868 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000868 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000868 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000868 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000868 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000868 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6569.754933 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6569.754933 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6569.754933 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6569.754933 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6569.754933 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6569.754933 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 708 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1036.794557 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506247 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506247 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161874097 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161874097 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161874097 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161874097 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161874097 # number of overall hits +system.cpu.icache.overall_hits::total 161874097 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 139755 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 139755 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 139755 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 139755 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 139755 # number of overall misses +system.cpu.icache.overall_misses::total 139755 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 916174482 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 916174482 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 916174482 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 916174482 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 916174482 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 916174482 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162013852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162013852 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162013852 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162013852 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162013852 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162013852 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000863 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000863 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000863 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000863 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000863 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000863 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6555.575700 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6555.575700 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6555.575700 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6555.575700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6555.575700 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6555.575700 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1833 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 118 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 166.636364 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1937 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1937 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1937 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1937 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1937 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1937 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 138698 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 138698 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 138698 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 138698 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 138698 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 138698 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 556491008 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 556491008 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 556491008 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 556491008 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 556491008 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 556491008 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000856 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000856 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000856 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000856 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000856 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000856 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4012.249694 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4012.249694 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4012.249694 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4012.249694 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4012.249694 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4012.249694 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1951 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1951 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1951 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1951 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1951 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1951 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 137804 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 137804 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 137804 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 137804 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 137804 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 137804 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 553553258 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 553553258 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 553553258 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 553553258 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 553553258 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 553553258 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000851 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000851 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000851 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000851 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000851 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000851 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4016.960741 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4016.960741 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4016.960741 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4016.960741 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4016.960741 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4016.960741 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 352883 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29672.816995 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3696782 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 385243 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.595974 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 199077347000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21120.561633 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 222.415022 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8329.840341 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.644548 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006788 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.254207 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.905543 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3674 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1586650 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1590324 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2330727 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2330727 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1427 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1427 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564902 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564902 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3674 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2151552 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2155226 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3674 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2151552 # number of overall hits -system.cpu.l2cache.overall_hits::total 2155226 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3169 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 175551 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 178720 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 130331 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 130331 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206871 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206871 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3169 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382422 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 385591 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3169 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382422 # number of overall misses -system.cpu.l2cache.overall_misses::total 385591 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245985250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13221288951 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13467274201 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6607716 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 6607716 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14252900476 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14252900476 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 245985250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27474189427 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27720174677 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 245985250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27474189427 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27720174677 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6843 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1762201 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1769044 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2330727 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2330727 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 131758 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 131758 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771773 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771773 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6843 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2533974 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2540817 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6843 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2533974 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2540817 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.463101 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099620 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.101026 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989170 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989170 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268046 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268046 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463101 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150918 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151759 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463101 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150918 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151759 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77622.357210 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75313.093921 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75354.040964 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 50.699496 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 50.699496 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68897.527812 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68897.527812 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77622.357210 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71842.596469 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71890.097738 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77622.357210 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71842.596469 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71890.097738 # average overall miss latency +system.cpu.l2cache.tags.replacements 352916 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29674.078168 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3696976 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 385280 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.595556 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 199035325000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21118.733135 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 224.036414 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8331.308620 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.644493 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006837 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.254251 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.905581 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 3672 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1586607 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1590279 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2330686 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2330686 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1446 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1446 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 564906 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 564906 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3672 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2151513 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2155185 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3672 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2151513 # number of overall hits +system.cpu.l2cache.overall_hits::total 2155185 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3168 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 175586 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 178754 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 129428 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 129428 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 206870 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 206870 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3168 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 382456 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 385624 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3168 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 382456 # number of overall misses +system.cpu.l2cache.overall_misses::total 385624 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245961000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13200679958 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13446640958 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 6462222 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 6462222 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14256875974 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14256875974 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 245961000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 27457555932 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 27703516932 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 245961000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 27457555932 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 27703516932 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 6840 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1762193 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1769033 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2330686 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2330686 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 130874 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 130874 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771776 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771776 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 6840 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2533969 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2540809 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 6840 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2533969 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2540809 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.463158 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099641 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.101046 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988951 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988951 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268044 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268044 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463158 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150932 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151772 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463158 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150932 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151772 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77639.204545 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75180.708929 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75224.280061 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49.929088 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49.929088 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68917.078233 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68917.078233 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77639.204545 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71792.718462 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71840.748843 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77639.204545 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71792.718462 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71840.748843 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -807,174 +809,168 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293541 # number of writebacks -system.cpu.l2cache.writebacks::total 293541 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3169 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175550 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 178719 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 130331 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 130331 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206871 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206871 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3169 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 382421 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 385590 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3169 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 382421 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 385590 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205942250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10968319701 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11174261951 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1306769847 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1306769847 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11624255024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11624255024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205942250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22592574725 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22798516975 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205942250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22592574725 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22798516975 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.463101 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099620 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101026 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989170 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989170 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268046 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268046 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463101 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150917 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151758 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463101 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150917 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151758 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64986.509940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62479.747656 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62524.196929 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10026.546616 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10026.546616 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56190.838851 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56190.838851 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64986.509940 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59077.756517 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59126.318045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64986.509940 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59077.756517 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59126.318045 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293621 # number of writebacks +system.cpu.l2cache.writebacks::total 293621 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3168 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 175586 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 178754 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 129428 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 129428 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206870 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206870 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3168 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 382456 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 385624 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 382456 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 385624 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205953000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10947318958 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11153271958 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1297954472 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1297954472 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11628367526 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11628367526 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205953000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22575686484 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22781639484 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205953000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22575686484 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22781639484 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099641 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101046 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988951 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988951 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268044 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268044 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150932 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151772 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463158 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151772 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65010.416667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62347.333831 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62394.530797 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10028.390086 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10028.390086 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56210.990119 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56210.990119 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65010.416667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59028.192744 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59077.338247 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65010.416667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59028.192744 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59077.338247 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2529878 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.353781 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 396093197 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2533974 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 156.313047 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2529873 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.353795 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 396071280 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2533969 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 156.304706 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1764467250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.353781 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.353795 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998133 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998133 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 247361230 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 247361230 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148239956 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148239956 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 395601186 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 395601186 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 395601186 # number of overall hits -system.cpu.dcache.overall_hits::total 395601186 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2863617 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2863617 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 920246 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 920246 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3783863 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3783863 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3783863 # number of overall misses -system.cpu.dcache.overall_misses::total 3783863 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57446251269 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57446251269 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25840120296 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25840120296 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83286371565 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83286371565 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83286371565 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83286371565 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250224847 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250224847 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::cpu.data 247337709 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247337709 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148240799 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148240799 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395578508 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 395578508 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 395578508 # number of overall hits +system.cpu.dcache.overall_hits::total 395578508 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2867309 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2867309 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 919403 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 919403 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3786712 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3786712 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3786712 # number of overall misses +system.cpu.dcache.overall_misses::total 3786712 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57500595434 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57500595434 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25821603651 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25821603651 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83322199085 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83322199085 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83322199085 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83322199085 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250205018 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250205018 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399385049 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399385049 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399385049 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399385049 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011444 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011444 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006170 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006170 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009474 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009474 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009474 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009474 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20060.731330 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20060.731330 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28079.579043 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28079.579043 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22010.937385 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22010.937385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22010.937385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22010.937385 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7195 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399365220 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399365220 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399365220 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399365220 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011460 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011460 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006164 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006164 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009482 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009482 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009482 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009482 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20053.853782 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20053.853782 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28085.185333 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28085.185333 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22003.838445 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22003.838445 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22003.838445 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22003.838445 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7384 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 685 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 704 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.503650 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.488636 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330727 # number of writebacks -system.cpu.dcache.writebacks::total 2330727 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1101143 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1101143 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16988 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16988 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1118131 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1118131 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1118131 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1118131 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762474 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1762474 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 903258 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 903258 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2665732 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2665732 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2665732 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2665732 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30885946501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30885946501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23721964454 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23721964454 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54607910955 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 54607910955 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54607910955 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 54607910955 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2330686 # number of writebacks +system.cpu.dcache.writebacks::total 2330686 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1104851 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1104851 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17019 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17019 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1121870 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1121870 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1121870 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1121870 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762458 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762458 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 902384 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 902384 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2664842 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2664842 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2664842 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2664842 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30865724250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30865724250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23705880099 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23705880099 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54571604349 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 54571604349 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54571604349 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 54571604349 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006056 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006056 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006675 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006675 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006675 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006675 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17524.199790 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17524.199790 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26262.667426 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26262.667426 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20485.146652 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20485.146652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20485.146652 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20485.146652 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006050 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006050 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006673 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006673 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006673 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006673 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17512.884988 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17512.884988 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26270.279725 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26270.279725 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20478.363951 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20478.363951 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20478.363951 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20478.363951 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index 7a734044e..abce0a0d4 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:21:35 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:44:23 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 0326dde96..87dac48c4 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.885229 # Nu sim_ticks 885229328000 # Number of ticks simulated final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1006678 # Simulator instruction rate (inst/s) -host_op_rate 1861461 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1077718973 # Simulator tick rate (ticks/s) -host_mem_usage 296180 # Number of bytes of host memory used -host_seconds 821.39 # Real time elapsed on the host +host_inst_rate 1293065 # Simulator instruction rate (inst/s) +host_op_rate 2391022 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1384315331 # Simulator tick rate (ticks/s) +host_mem_usage 251216 # Number of bytes of host memory used +host_seconds 639.47 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory @@ -42,16 +42,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 35346287 # number of times a function call or return occured system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317562 # number of integer instructions +system.cpu.num_int_insts 1526605510 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3855106260 # number of times the integer registers were read -system.cpu.num_int_register_writes 1614040854 # number of times the integer registers were written +system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read +system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read +system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written system.cpu.num_mem_refs 533262343 # number of memory refs system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index 5ef733649..59b399b0b 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:48:16 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:41:23 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 7c10a36f9..43f2a7587 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.647873 # Nu sim_ticks 1647872849000 # Number of ticks simulated final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 418246 # Simulator instruction rate (inst/s) -host_op_rate 773383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 833516309 # Simulator tick rate (ticks/s) -host_mem_usage 254900 # Number of bytes of host memory used -host_seconds 1977.01 # Real time elapsed on the host +host_inst_rate 788676 # Simulator instruction rate (inst/s) +host_op_rate 1458350 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1571742015 # Simulator tick rate (ticks/s) +host_mem_usage 258676 # Number of bytes of host memory used +host_seconds 1048.44 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory @@ -58,16 +58,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1528317562 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 35346287 # number of times a function call or return occured system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls -system.cpu.num_int_insts 1528317562 # number of integer instructions +system.cpu.num_int_insts 1526605510 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3855106260 # number of times the integer registers were read -system.cpu.num_int_register_writes 1614040854 # number of times the integer registers were written +system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read +system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read +system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written system.cpu.num_mem_refs 533262343 # number of memory refs system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index dfa123161..14dada76e 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index dc6d59bdf..58c019f98 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 09:53:14 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 16 2013 01:34:33 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index a56a193ad..e492ac5d0 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.077522 # Nu sim_ticks 77521581000 # Number of ticks simulated final_tick 77521581000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 226587 # Simulator instruction rate (inst/s) -host_op_rate 226587 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46769350 # Simulator tick rate (ticks/s) -host_mem_usage 233048 # Number of bytes of host memory used -host_seconds 1657.53 # Real time elapsed on the host +host_inst_rate 201802 # Simulator instruction rate (inst/s) +host_op_rate 201802 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41653613 # Simulator tick rate (ticks/s) +host_mem_usage 236024 # Number of bytes of host memory used +host_seconds 1861.10 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory @@ -350,8 +350,8 @@ system.cpu.rename.IQFullEvents 25268 # Nu system.cpu.rename.LSQFullEvents 8017940 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 287478957 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 579418122 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 306415899 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 273002223 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 413955402 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 165462719 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 27946628 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 36876 # count of serializing insts renamed diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index c6c5b71d8..dd0636ebe 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index d9d67c53c..d3e872fc3 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:27:24 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:05:47 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index cfe46b65a..8bc1d638d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.068375 # Nu sim_ticks 68375005500 # Number of ticks simulated final_tick 68375005500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121198 # Simulator instruction rate (inst/s) -host_op_rate 154946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30350947 # Simulator tick rate (ticks/s) -host_mem_usage 251080 # Number of bytes of host memory used -host_seconds 2252.81 # Real time elapsed on the host +host_inst_rate 143200 # Simulator instruction rate (inst/s) +host_op_rate 183074 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35860683 # Simulator tick rate (ticks/s) +host_mem_usage 256516 # Number of bytes of host memory used +host_seconds 1906.68 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 194176 # Number of bytes read from this memory @@ -362,8 +362,8 @@ system.cpu.rename.LSQFullEvents 10191603 # Nu system.cpu.rename.FullRegisterEvents 1124 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 432142984 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 2330358431 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1257645546 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1072712885 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 1572902779 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 200313916 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 47576791 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 11831 # count of serializing insts renamed diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index cb1d4f78d..507dc65a9 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 6fa75b847..091ca3b5c 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,10 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 09:53:14 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 15 2013 18:56:50 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 669d3dfc7..580dd6a6a 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.631883 # Nu sim_ticks 631883288500 # Number of ticks simulated final_tick 631883288500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 177291 # Simulator instruction rate (inst/s) -host_op_rate 177291 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61450789 # Simulator tick rate (ticks/s) -host_mem_usage 236780 # Number of bytes of host memory used -host_seconds 10282.75 # Real time elapsed on the host +host_inst_rate 151695 # Simulator instruction rate (inst/s) +host_op_rate 151695 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52578725 # Simulator tick rate (ticks/s) +host_mem_usage 240040 # Number of bytes of host memory used +host_seconds 12017.85 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory @@ -370,8 +370,8 @@ system.cpu.rename.IQFullEvents 15191 # Nu system.cpu.rename.LSQFullEvents 28875434 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 2054257390 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 3579193509 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3458491340 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 120702169 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 3493818421 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 85375087 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 669288320 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4234 # count of serializing insts renamed diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index f5cd82b95..be78ce1bf 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 6bce28421..3ba2de45d 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:57:23 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:40:46 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 5f69a496c..d3db51b2e 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.640648 # Nu sim_ticks 640648369500 # Number of ticks simulated final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 107808 # Simulator instruction rate (inst/s) -host_op_rate 146820 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49890421 # Simulator tick rate (ticks/s) -host_mem_usage 251704 # Number of bytes of host memory used -host_seconds 12841.11 # Real time elapsed on the host +host_inst_rate 92518 # Simulator instruction rate (inst/s) +host_op_rate 125998 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42814979 # Simulator tick rate (ticks/s) +host_mem_usage 256100 # Number of bytes of host memory used +host_seconds 14963.18 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory @@ -363,8 +363,8 @@ system.cpu.rename.LSQFullEvents 52259250 # Nu system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 2968696668 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 14208671481 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13600947598 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 607723883 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 12321480350 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90240197 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 975556578 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 21287 # count of serializing insts renamed diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 7b8dd0790..684c8c0e1 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 0840178d9..d12ffcc4f 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 09:57:43 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 16 2013 01:34:33 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 5b9e2998f..f889e2dcc 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.024977 # Nu sim_ticks 24977022500 # Number of ticks simulated final_tick 24977022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124025 # Simulator instruction rate (inst/s) -host_op_rate 124025 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38920856 # Simulator tick rate (ticks/s) -host_mem_usage 235900 # Number of bytes of host memory used -host_seconds 641.74 # Real time elapsed on the host +host_inst_rate 179872 # Simulator instruction rate (inst/s) +host_op_rate 179872 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56446381 # Simulator tick rate (ticks/s) +host_mem_usage 238148 # Number of bytes of host memory used +host_seconds 442.49 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory @@ -417,8 +417,8 @@ system.cpu.rename.IQFullEvents 2492 # Nu system.cpu.rename.LSQFullEvents 2137772 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 61631332 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 123302278 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122850608 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 451670 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 122982558 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 319719 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 9084451 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 5532 # count of serializing insts renamed diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 19517f85f..a8a1f643c 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index b38f95469..946783e23 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 09:04:25 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:08:44 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 06aaaa021..9aa909b09 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.026765 # Nu sim_ticks 26765004500 # Number of ticks simulated final_tick 26765004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102307 # Simulator instruction rate (inst/s) -host_op_rate 145187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38617115 # Simulator tick rate (ticks/s) -host_mem_usage 251228 # Number of bytes of host memory used -host_seconds 693.09 # Real time elapsed on the host +host_inst_rate 122306 # Simulator instruction rate (inst/s) +host_op_rate 173568 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46166163 # Simulator tick rate (ticks/s) +host_mem_usage 255896 # Number of bytes of host memory used +host_seconds 579.75 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 297792 # Number of bytes read from this memory @@ -432,8 +432,8 @@ system.cpu.rename.LSQFullEvents 4627273 # Nu system.cpu.rename.FullRegisterEvents 285 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 115384718 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 530174580 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 530166885 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7695 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 476867094 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3452 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 16252046 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 20256 # count of serializing insts renamed diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 5c873ae8a..898bd1404 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index a9e5ff044..3d7fe8a25 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,10 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:05:25 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 15 2013 19:07:40 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 82bf88993..d01882912 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.694171 # Nu sim_ticks 694171131000 # Number of ticks simulated final_tick 694171131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 178600 # Simulator instruction rate (inst/s) -host_op_rate 178600 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 71414604 # Simulator tick rate (ticks/s) -host_mem_usage 227828 # Number of bytes of host memory used -host_seconds 9720.30 # Real time elapsed on the host +host_inst_rate 145628 # Simulator instruction rate (inst/s) +host_op_rate 145628 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58230614 # Simulator tick rate (ticks/s) +host_mem_usage 230068 # Number of bytes of host memory used +host_seconds 11921.07 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory @@ -424,8 +424,8 @@ system.cpu.rename.IQFullEvents 1826446 # Nu system.cpu.rename.LSQFullEvents 51579864 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 2248363732 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 3900421320 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3899178783 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1242537 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 3900278198 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 143121 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 872160769 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 168 # count of serializing insts renamed diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index 67c7195c6..30ce01df4 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 4c68e7cbb..7f1aa9216 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:11:07 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:37:44 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index f9e4efd28..3c2739180 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.541686 # Nu sim_ticks 541686426500 # Number of ticks simulated final_tick 541686426500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146656 # Simulator instruction rate (inst/s) -host_op_rate 163606 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51433162 # Simulator tick rate (ticks/s) -host_mem_usage 242412 # Number of bytes of host memory used -host_seconds 10531.85 # Real time elapsed on the host +host_inst_rate 133850 # Simulator instruction rate (inst/s) +host_op_rate 149320 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46941984 # Simulator tick rate (ticks/s) +host_mem_usage 248124 # Number of bytes of host memory used +host_seconds 11539.49 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory @@ -433,8 +433,8 @@ system.cpu.rename.LSQFullEvents 60088597 # Nu system.cpu.rename.FullRegisterEvents 10 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 2286724696 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 10669719595 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10669716841 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2754 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 9782199775 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 333 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 580404766 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 862 # count of serializing insts renamed diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index 09e2cbd6f..5a2f2668d 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic/simout -Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 07:00:18 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:38:48 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 09bbb2360..256e15dc9 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1114602 # Simulator instruction rate (inst/s) -host_op_rate 1736651 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1054547884 # Simulator tick rate (ticks/s) -host_mem_usage 286860 # Number of bytes of host memory used -host_seconds 2698.79 # Real time elapsed on the host +host_inst_rate 1357896 # Simulator instruction rate (inst/s) +host_op_rate 2115724 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1284732870 # Simulator tick rate (ticks/s) +host_mem_usage 240864 # Number of bytes of host memory used +host_seconds 2215.25 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory @@ -42,16 +42,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 33534539 # number of times a function call or return occured system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls -system.cpu.num_int_insts 4686862527 # number of integer instructions +system.cpu.num_int_insts 4684368009 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 11915474428 # number of times the integer registers were read -system.cpu.num_int_register_writes 5355771938 # number of times the integer registers were written +system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read +system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read +system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written system.cpu.num_mem_refs 1677713084 # number of memory refs system.cpu.num_load_insts 1239184746 # Number of load instructions system.cpu.num_store_insts 438528338 # Number of store instructions diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index 842f4ca6e..2a7659f1c 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simout -Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:22:01 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:55:52 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 776ec92d3..f740c02c8 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.882581 # Nu sim_ticks 5882580526000 # Number of ticks simulated final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 645050 # Simulator instruction rate (inst/s) -host_op_rate 1005047 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1261455450 # Simulator tick rate (ticks/s) -host_mem_usage 245540 # Number of bytes of host memory used -host_seconds 4663.33 # Real time elapsed on the host +host_inst_rate 876676 # Simulator instruction rate (inst/s) +host_op_rate 1365940 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1714420225 # Simulator tick rate (ticks/s) +host_mem_usage 249312 # Number of bytes of host memory used +host_seconds 3431.24 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory @@ -58,16 +58,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4686862527 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 33534539 # number of times a function call or return occured system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls -system.cpu.num_int_insts 4686862527 # number of integer instructions +system.cpu.num_int_insts 4684368009 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 11915474428 # number of times the integer registers were read -system.cpu.num_int_register_writes 5355771938 # number of times the integer registers were written +system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read +system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read +system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written system.cpu.num_mem_refs 1677713084 # number of memory refs system.cpu.num_load_insts 1239184746 # Number of load instructions system.cpu.num_store_insts 438528338 # Number of store instructions diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 8c9cfc594..b1f130dee 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index f8802d4f7..2fe61da2d 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:24:35 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 16 2013 01:34:33 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index b7d057d9f..758c8228e 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.023492 # Nu sim_ticks 23492267500 # Number of ticks simulated final_tick 23492267500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120531 # Simulator instruction rate (inst/s) -host_op_rate 120531 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33636905 # Simulator tick rate (ticks/s) -host_mem_usage 231740 # Number of bytes of host memory used -host_seconds 698.41 # Real time elapsed on the host +host_inst_rate 158745 # Simulator instruction rate (inst/s) +host_op_rate 158745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44301493 # Simulator tick rate (ticks/s) +host_mem_usage 233720 # Number of bytes of host memory used +host_seconds 530.28 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory @@ -346,8 +346,8 @@ system.cpu.rename.IQFullEvents 398899 # Nu system.cpu.rename.LSQFullEvents 2436739 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 89066471 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 157595093 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 147895466 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9699627 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 150534218 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7060874 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 20639110 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 733 # count of serializing insts renamed diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 271729e48..d981a43f0 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 000af632b..5ce7704c2 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,14 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 09:14:29 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 02:15:41 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index cd02e0594..a815317b1 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.074201 # Nu sim_ticks 74201024500 # Number of ticks simulated final_tick 74201024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88798 # Simulator instruction rate (inst/s) -host_op_rate 97225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38240010 # Simulator tick rate (ticks/s) -host_mem_usage 245976 # Number of bytes of host memory used -host_seconds 1940.40 # Real time elapsed on the host +host_inst_rate 115322 # Simulator instruction rate (inst/s) +host_op_rate 126267 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49662501 # Simulator tick rate (ticks/s) +host_mem_usage 251448 # Number of bytes of host memory used +host_seconds 1494.11 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 131328 # Number of bytes read from this memory @@ -358,8 +358,8 @@ system.cpu.rename.LSQFullEvents 3662384 # Nu system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers system.cpu.rename.RenamedOperands 631760398 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 1581883462 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1564582781 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17300681 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 1507069248 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3196133 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 333716259 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25188 # count of serializing insts renamed diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 078b2c3e8..5e4a8f947 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=true numIQEntries=64 +numPhysCCRegs=1280 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index da55dd7a8..607420641 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 1 2013 21:55:52 -gem5 started Oct 1 2013 22:49:39 -gem5 executing on steam +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:39:37 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index cd707d2d7..06f12379e 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.144337 # Nu sim_ticks 144337151000 # Number of ticks simulated final_tick 144337151000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53269 # Simulator instruction rate (inst/s) -host_op_rate 89284 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58216660 # Simulator tick rate (ticks/s) -host_mem_usage 281036 # Number of bytes of host memory used -host_seconds 2479.31 # Real time elapsed on the host +host_inst_rate 71990 # Simulator instruction rate (inst/s) +host_op_rate 120663 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78676444 # Simulator tick rate (ticks/s) +host_mem_usage 280564 # Number of bytes of host memory used +host_seconds 1834.57 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 217984 # Number of bytes read from this memory @@ -215,14 +215,14 @@ system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.80% # system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 5 1.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 502 # Bytes accessed per row activation -system.physmem.totQLat 12663500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 119173500 # Sum of mem lat for all requests +system.physmem.totQLat 12694000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 119204000 # Sum of mem lat for all requests system.physmem.totBusLat 26815000 # Total cycles spent in databus access system.physmem.totBankLat 79695000 # Total cycles spent in bank access -system.physmem.avgQLat 2361.27 # Average queueing delay per request +system.physmem.avgQLat 2366.96 # Average queueing delay per request system.physmem.avgBankLat 14860.15 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 22221.42 # Average memory access latency +system.physmem.avgMemAccLat 22227.11 # Average memory access latency system.physmem.avgRdBW 2.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.38 # Average consumed read bandwidth in MB/s @@ -251,110 +251,109 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 343040 system.membus.tot_pkt_size::total 343040 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 343040 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 6992500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6990500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50918345 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 50919845 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.branchPred.lookups 18643049 # Number of BP lookups -system.cpu.branchPred.condPredicted 18643049 # Number of conditional branches predicted +system.cpu.branchPred.lookups 18643050 # Number of BP lookups +system.cpu.branchPred.condPredicted 18643050 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1490032 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11410311 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10785937 # Number of BTB hits +system.cpu.branchPred.BTBLookups 11410312 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10785938 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.527984 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 94.527985 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1319504 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 23183 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 288958648 # number of cpu cycles simulated +system.cpu.numCycles 288958646 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 23449793 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 206693383 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18643049 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12105441 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54202283 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15520862 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 177854698 # Number of cycles fetch has spent blocked +system.cpu.fetch.Insts 206693394 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18643050 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12105442 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 54202287 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15520872 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 177854529 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 10399 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22344440 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 223501 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269290807 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.269558 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.757533 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 22344441 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 223502 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269290652 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.269559 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.757534 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 216527174 80.41% 80.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216527015 80.41% 80.41% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2848467 1.06% 81.46% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 2311919 0.86% 82.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2635919 0.98% 83.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2635920 0.98% 83.30% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 3216253 1.19% 84.50% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 3385278 1.26% 85.75% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 3830479 1.42% 87.18% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 2556488 0.95% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31978830 11.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31978833 11.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269290807 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 269290652 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.064518 # Number of branch fetches per cycle system.cpu.fetch.rate 0.715304 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36876726 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 166835214 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41579224 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10227847 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13771796 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 335978319 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13771796 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44930870 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116571073 # Number of cycles rename is blocking +system.cpu.decode.IdleCycles 36876732 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 166835033 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41579230 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10227851 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13771806 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 335978387 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13771806 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44930878 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116570981 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 32723 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 42705730 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51278615 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 329616563 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10879 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26000887 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22678374 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 233 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 382329747 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 917574423 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 909394709 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8179714 # Number of floating rename lookups +system.cpu.rename.UnblockCycles 51278534 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329616672 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10920 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26000838 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22678371 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 382329896 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 917574751 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 605864950 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4114395 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 122900297 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 122900446 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 2069 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 2059 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 104883276 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84491863 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 104883314 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84491871 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 30099442 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58238424 # Number of conflicting loads. +system.cpu.memDep0.conflictingLoads 58238426 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 18921052 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322680217 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 322680314 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 4268 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260554825 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118516 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 100936987 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 209936629 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 260554870 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 118520 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 100937084 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 209936848 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3023 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269290807 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.967559 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.344978 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 269290652 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.967560 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.344979 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143216984 53.18% 53.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55392011 20.57% 73.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34136175 12.68% 86.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19056796 7.08% 93.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10890988 4.04% 97.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4174840 1.55% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1812715 0.67% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 476750 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143216818 53.18% 53.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55391998 20.57% 73.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34136198 12.68% 86.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19056794 7.08% 93.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10890991 4.04% 97.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4174838 1.55% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1812713 0.67% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 476754 0.18% 99.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 133548 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269290807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269290652 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 129590 4.77% 4.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 129591 4.77% 4.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.77% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 4.77% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.77% # attempts to use FU when none available @@ -388,8 +387,8 @@ system.cpu.iq.fu_full::MemWrite 301448 11.09% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1210947 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162062843 62.20% 62.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 788599 0.30% 62.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162062878 62.20% 62.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 788601 0.30% 62.97% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 7035610 2.70% 65.67% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 1446949 0.56% 66.22% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued @@ -417,25 +416,25 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65458478 25.12% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65458486 25.12% 91.34% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 22551399 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260554825 # Type of FU issued +system.cpu.iq.FU_type_0::total 260554870 # Type of FU issued system.cpu.iq.rate 0.901703 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2717985 # FU busy when requested +system.cpu.iq.fu_busy_cnt 2717986 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010432 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 788349726 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 420314001 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255192171 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 788349666 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420314195 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255192215 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4887232 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 3589351 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2349681 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259602149 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 259602195 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2459714 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18922789 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 18922795 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27842276 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 27842284 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 26598 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 287421 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 9583725 # Number of stores squashed @@ -444,57 +443,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 49875 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13771796 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 85093935 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5458597 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 322684485 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 13771806 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85094278 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5458618 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322684582 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 133416 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84491863 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 84491871 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 30099442 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 2045 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2689496 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 2689502 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 13828 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 287421 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 641114 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 899581 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1540695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258780587 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64687693 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1774238 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 258780631 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64687698 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1774239 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87035311 # number of memory reference insts executed +system.cpu.iew.exec_refs 87035316 # number of memory reference insts executed system.cpu.iew.exec_branches 14266808 # Number of branches executed system.cpu.iew.exec_stores 22347618 # Number of stores executed system.cpu.iew.exec_rate 0.895563 # Inst execution rate -system.cpu.iew.wb_sent 258140928 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257541852 # cumulative count of insts written-back -system.cpu.iew.wb_producers 206006710 # num instructions producing a value -system.cpu.iew.wb_consumers 369206768 # num instructions consuming a value +system.cpu.iew.wb_sent 258140972 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257541896 # cumulative count of insts written-back +system.cpu.iew.wb_producers 206006775 # num instructions producing a value +system.cpu.iew.wb_consumers 369206880 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 0.891276 # insts written-back per cycle system.cpu.iew.wb_fanout 0.557971 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101393272 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101393363 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1491544 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 255519011 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.866328 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.656610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 255518846 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.866329 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.656611 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156315570 61.18% 61.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156315405 61.18% 61.18% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 57071451 22.34% 83.51% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 14008929 5.48% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12048530 4.72% 93.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4172669 1.63% 95.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12048531 4.72% 93.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4172668 1.63% 95.34% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 2970306 1.16% 96.50% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 908783 0.36% 96.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1048603 0.41% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6974170 2.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1048602 0.41% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6974171 2.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 255519011 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255518846 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -503,14 +502,14 @@ system.cpu.commit.loads 56649587 # Nu system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 12326938 # Number of branches committed system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. -system.cpu.commit.int_insts 220339553 # Number of committed integer instructions. +system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6974170 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6974171 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 571301497 # The number of ROB reads -system.cpu.rob.rob_writes 659310607 # The number of ROB writes -system.cpu.timesIdled 5931768 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19667841 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571301422 # The number of ROB reads +system.cpu.rob.rob_writes 659310799 # The number of ROB writes +system.cpu.timesIdled 5931788 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19667994 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated @@ -518,11 +517,13 @@ system.cpu.cpi 2.187901 # CP system.cpu.cpi_total 2.187901 # CPI: Total CPI of All Threads system.cpu.ipc 0.457059 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.457059 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 554180321 # number of integer regfile reads -system.cpu.int_regfile_writes 293821719 # number of integer regfile writes +system.cpu.int_regfile_reads 451358394 # number of integer regfile reads +system.cpu.int_regfile_writes 233998694 # number of integer regfile writes system.cpu.fp_regfile_reads 3217923 # number of floating regfile reads system.cpu.fp_regfile_writes 2009376 # number of floating regfile writes -system.cpu.misc_regfile_reads 133360565 # number of misc regfile reads +system.cpu.cc_regfile_reads 102822009 # number of cc regfile reads +system.cpu.cc_regfile_writes 59823089 # number of cc regfile writes +system.cpu.misc_regfile_reads 133360573 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes system.cpu.toL2Bus.throughput 3892220 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 7233 # Transaction distribution @@ -547,50 +548,50 @@ system.cpu.toL2Bus.respLayer0.utilization 0.0 # L system.cpu.toL2Bus.respLayer1.occupancy 3517155 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.icache.tags.replacements 4647 # number of replacements -system.cpu.icache.tags.tagsinuse 1626.526470 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22335617 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1626.526476 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22335618 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6612 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3378.042498 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3378.042650 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1626.526470 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1626.526476 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.794202 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.794202 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 22335617 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22335617 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22335617 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22335617 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22335617 # number of overall hits -system.cpu.icache.overall_hits::total 22335617 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 22335618 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22335618 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22335618 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22335618 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22335618 # number of overall hits +system.cpu.icache.overall_hits::total 22335618 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 8823 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 8823 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 8823 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 8823 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8823 # number of overall misses system.cpu.icache.overall_misses::total 8823 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 351986000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 351986000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 351986000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 351986000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 351986000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 351986000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22344440 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22344440 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22344440 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22344440 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22344440 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22344440 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 352032500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 352032500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 352032500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 352032500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 352032500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 352032500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22344441 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22344441 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22344441 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22344441 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22344441 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22344441 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000395 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000395 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000395 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000395 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000395 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000395 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39894.140315 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39894.140315 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39894.140315 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39894.140315 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39894.140315 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39894.140315 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39899.410631 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39899.410631 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39899.410631 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39899.410631 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39899.410631 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 978 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked @@ -611,34 +612,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 6769 system.cpu.icache.demand_mshr_misses::total 6769 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6769 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6769 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262790750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 262790750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262790750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 262790750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262790750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 262790750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 262819250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 262819250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 262819250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 262819250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 262819250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 262819250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38822.684296 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38822.684296 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38822.684296 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 38822.684296 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38822.684296 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 38822.684296 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38826.894667 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38826.894667 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38826.894667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 38826.894667 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2554.250999 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2554.251018 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3246 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3834 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.846635 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 1.761986 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2240.158867 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 312.330146 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2240.158882 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 312.330149 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068364 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.009532 # Average percentage of cache occupancy @@ -671,17 +672,17 @@ system.cpu.l2cache.demand_misses::total 5364 # nu system.cpu.l2cache.overall_misses::cpu.inst 3407 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1957 # number of overall misses system.cpu.l2cache.overall_misses::total 5364 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223798500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31028500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 254827000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223827000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31029500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 254856500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 96683500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 96683500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 223798500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 127712000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 351510500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 223798500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 127712000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 351510500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 223827000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 127713000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 351540000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 223827000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 127713000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 351540000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6613 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 464 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7077 # number of ReadReq accesses(hits+misses) @@ -710,17 +711,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.622780 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.515197 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.978500 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.622780 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65687.848547 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72496.495327 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66447.718383 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65696.213678 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72498.831776 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 66455.410691 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 63233.158927 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 63233.158927 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65687.848547 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65259.070005 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65531.413125 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65687.848547 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65259.070005 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65531.413125 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65696.213678 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65259.580991 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65536.912752 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65696.213678 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65259.580991 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65536.912752 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -742,19 +743,19 @@ system.cpu.l2cache.demand_mshr_misses::total 5364 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3407 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1957 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5364 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180903000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25684500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 206587500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180933000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25685000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 206618000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1550155 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1550155 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77075500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77075500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180903000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 102760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 283663000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180903000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 102760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 283663000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180933000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 102760500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 283693500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180933000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 102760500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 283693500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.515197 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922414 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.541896 # mshr miss rate for ReadReq accesses @@ -768,37 +769,37 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.622780 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.515197 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978500 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.622780 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53097.446434 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60010.514019 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53868.970013 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53106.251834 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60011.682243 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53876.923077 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50409.090909 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50409.090909 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53097.446434 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52508.942259 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52882.736764 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53097.446434 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52508.942259 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52882.736764 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53106.251834 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52888.422819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53106.251834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52509.197752 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52888.422819 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 54 # number of replacements -system.cpu.dcache.tags.tagsinuse 1431.071362 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66125332 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1431.071380 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 66125331 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1997 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33112.334502 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33112.334001 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1431.071362 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1431.071380 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.349383 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.349383 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 45611086 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45611086 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 45611085 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45611085 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514038 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 20514038 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66125124 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66125124 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66125124 # number of overall hits -system.cpu.dcache.overall_hits::total 66125124 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 66125123 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66125123 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66125123 # number of overall hits +system.cpu.dcache.overall_hits::total 66125123 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 915 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 915 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1693 # number of WriteReq misses @@ -807,22 +808,22 @@ system.cpu.dcache.demand_misses::cpu.data 2608 # n system.cpu.dcache.demand_misses::total 2608 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2608 # number of overall misses system.cpu.dcache.overall_misses::total 2608 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55173302 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55173302 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 106078655 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 106078655 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 161251957 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 161251957 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 161251957 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 161251957 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45612001 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45612001 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 55175302 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 55175302 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 106081155 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 106081155 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 161256457 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 161256457 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 161256457 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 161256457 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45612000 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45612000 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66127732 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66127732 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66127732 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66127732 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 66127731 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66127731 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66127731 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66127731 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses @@ -831,14 +832,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60298.690710 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60298.690710 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62657.209096 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62657.209096 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61829.738113 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61829.738113 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61829.738113 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61829.738113 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60300.876503 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60300.876503 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62658.685765 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62658.685765 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61831.463574 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61831.463574 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61831.463574 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 351 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -865,14 +866,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2156 system.cpu.dcache.demand_mshr_misses::total 2156 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2156 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2156 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31923750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31923750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101848595 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 101848595 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133772345 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 133772345 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133772345 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 133772345 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31924750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31924750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101851095 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 101851095 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133775845 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 133775845 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133775845 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 133775845 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses @@ -881,14 +882,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000033 system.cpu.dcache.demand_mshr_miss_rate::total 0.000033 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000033 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000033 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68653.225806 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68653.225806 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60229.801892 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60229.801892 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62046.542208 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62046.542208 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62046.542208 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62046.542208 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68655.376344 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68655.376344 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60231.280308 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60231.280308 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62048.165584 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62048.165584 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout index 8d9f2b3f2..61953e3fc 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 1 2013 21:55:52 -gem5 started Oct 1 2013 22:49:39 -gem5 executing on steam +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:46:06 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 2bac376f2..30630542a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu sim_ticks 131393279000 # Number of ticks simulated final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 399836 # Simulator instruction rate (inst/s) -host_op_rate 670162 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 397783827 # Simulator tick rate (ticks/s) -host_mem_usage 267400 # Number of bytes of host memory used -host_seconds 330.31 # Real time elapsed on the host +host_inst_rate 1210449 # Simulator instruction rate (inst/s) +host_op_rate 2028822 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1204235272 # Simulator tick rate (ticks/s) +host_mem_usage 265804 # Number of bytes of host memory used +host_seconds 109.11 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory @@ -42,16 +42,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 1595632 # number of times a function call or return occured system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls -system.cpu.num_int_insts 220339554 # number of integer instructions +system.cpu.num_int_insts 219019986 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 616959402 # number of times the integer registers were read -system.cpu.num_int_register_writes 257598047 # number of times the integer registers were written +system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read +system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written +system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read +system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written system.cpu.num_mem_refs 77165304 # number of memory refs system.cpu.num_load_insts 56649587 # Number of load instructions system.cpu.num_store_insts 20515717 # Number of store instructions diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index 04fae0566..b436e7f9e 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,12 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 1 2013 21:55:52 -gem5 started Oct 1 2013 22:49:39 -gem5 executing on steam +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:51:48 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 3f7324a80..9cfd1bb27 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.250954 # Nu sim_ticks 250953957000 # Number of ticks simulated final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 290889 # Simulator instruction rate (inst/s) -host_op_rate 487557 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 552730735 # Simulator tick rate (ticks/s) -host_mem_usage 274892 # Number of bytes of host memory used -host_seconds 454.03 # Real time elapsed on the host +host_inst_rate 789102 # Simulator instruction rate (inst/s) +host_op_rate 1322606 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1499404446 # Simulator tick rate (ticks/s) +host_mem_usage 274284 # Number of bytes of host memory used +host_seconds 167.37 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory @@ -50,16 +50,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 220339554 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses system.cpu.num_func_calls 1595632 # number of times a function call or return occured system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls -system.cpu.num_int_insts 220339554 # number of integer instructions +system.cpu.num_int_insts 219019986 # number of integer instructions system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 616959402 # number of times the integer registers were read -system.cpu.num_int_register_writes 257598047 # number of times the integer registers were written +system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read +system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written +system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read +system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written system.cpu.num_mem_refs 77165304 # number of memory refs system.cpu.num_load_insts 56649587 # Number of load instructions system.cpu.num_store_insts 20515717 # Number of store instructions diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 371241c9a..5c09eba9d 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -17,7 +17,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic mem_ranges=0:134217727 @@ -1029,7 +1029,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/andreas/m5/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1049,7 +1049,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/andreas/m5/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index a908efbe8..bbf756dc6 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 1 2013 21:55:52 -gem5 started Oct 1 2013 22:03:55 -gem5 executing on steam +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:42:07 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5112126311000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 2407ce1be..6c2f1a10d 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112126 # Nu sim_ticks 5112126311000 # Number of ticks simulated final_tick 5112126311000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1020096 # Simulator instruction rate (inst/s) -host_op_rate 2088583 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26083435490 # Simulator tick rate (ticks/s) -host_mem_usage 587152 # Number of bytes of host memory used -host_seconds 195.99 # Real time elapsed on the host +host_inst_rate 1595516 # Simulator instruction rate (inst/s) +host_op_rate 3266720 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 40796695114 # Simulator tick rate (ticks/s) +host_mem_usage 587608 # Number of bytes of host memory used +host_seconds 125.31 # Real time elapsed on the host sim_insts 199929810 # Number of instructions simulated sim_ops 409343980 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory @@ -259,16 +259,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 199929810 # Number of instructions committed system.cpu.committedOps 409343980 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374506599 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 374364740 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 2307717 # number of times a function call or return occured system.cpu.num_conditional_control_insts 39976354 # number of instructions that are conditional controls -system.cpu.num_int_insts 374506599 # number of integer instructions +system.cpu.num_int_insts 374364740 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 916001165 # number of times the integer registers were read -system.cpu.num_int_register_writes 480603129 # number of times the integer registers were written +system.cpu.num_int_register_reads 682285995 # number of times the integer registers were read +system.cpu.num_int_register_writes 323369548 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 233715170 # number of times the CC registers were read +system.cpu.num_cc_register_writes 157233581 # number of times the CC registers were written system.cpu.num_mem_refs 35660913 # number of memory refs system.cpu.num_load_insts 27238816 # Number of load instructions system.cpu.num_store_insts 8422097 # Number of store instructions diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index aa647f626..4c888767a 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -17,7 +17,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing mem_ranges=0:134217727 @@ -1022,7 +1022,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/andreas/m5/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1042,7 +1042,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/andreas/m5/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 6c4476b75..3c12ad36c 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 1 2013 21:55:52 -gem5 started Oct 1 2013 22:03:55 -gem5 executing on steam +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:55:08 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/andreas/m5/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5192277855000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 379d92f84..e69bdd504 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.192278 # Nu sim_ticks 5192277855000 # Number of ticks simulated final_tick 5192277855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 672895 # Simulator instruction rate (inst/s) -host_op_rate 1297076 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27224181866 # Simulator tick rate (ticks/s) -host_mem_usage 587160 # Number of bytes of host memory used -host_seconds 190.72 # Real time elapsed on the host +host_inst_rate 964497 # Simulator instruction rate (inst/s) +host_op_rate 1859169 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39021883302 # Simulator tick rate (ticks/s) +host_mem_usage 587612 # Number of bytes of host memory used +host_seconds 133.06 # Real time elapsed on the host sim_insts 128336541 # Number of instructions simulated sim_ops 247382226 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2866368 # Number of bytes read from this memory @@ -605,16 +605,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 128336541 # Number of instructions committed system.cpu.committedOps 247382226 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232116398 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 231975048 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 2299863 # number of times a function call or return occured system.cpu.num_conditional_control_insts 23167946 # number of instructions that are conditional controls -system.cpu.num_int_insts 232116398 # number of integer instructions +system.cpu.num_int_insts 231975048 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 567322022 # number of times the integer registers were read -system.cpu.num_int_register_writes 293376346 # number of times the integer registers were written +system.cpu.num_int_register_reads 434515715 # number of times the integer registers were read +system.cpu.num_int_register_writes 197846848 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 132806307 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95529498 # number of times the CC registers were written system.cpu.num_mem_refs 22249600 # number of memory refs system.cpu.num_load_insts 13881232 # Number of load instructions system.cpu.num_store_insts 8368368 # Number of store instructions diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index dce50f688..b09aafac2 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index ab8450b87..589b57e2d 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:26 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 16 2013 01:34:33 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 60f469d0d..31fc74f80 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20671000 # Number of ticks simulated final_tick 20671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24570 # Simulator instruction rate (inst/s) -host_op_rate 24568 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79697022 # Simulator tick rate (ticks/s) -host_mem_usage 227340 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host +host_inst_rate 10783 # Simulator instruction rate (inst/s) +host_op_rate 10783 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34979840 # Simulator tick rate (ticks/s) +host_mem_usage 229184 # Number of bytes of host memory used +host_seconds 0.59 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -301,8 +301,8 @@ system.cpu.rename.IQFullEvents 5 # Nu system.cpu.rename.LSQFullEvents 313 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 10969 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 18250 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18233 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 18241 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 6399 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index c5e8a16e6..b9dbe7d51 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index c47a79c1f..4cf5ca9ef 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:27 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 16 2013 01:34:33 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 746096984..2906fdf0c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 11933500 # Number of ticks simulated final_tick 11933500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64 # Simulator instruction rate (inst/s) -host_op_rate 64 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 321705 # Simulator tick rate (ticks/s) -host_mem_usage 226036 # Number of bytes of host memory used -host_seconds 37.09 # Real time elapsed on the host +host_inst_rate 3639 # Simulator instruction rate (inst/s) +host_op_rate 3638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18189727 # Simulator tick rate (ticks/s) +host_mem_usage 227880 # Number of bytes of host memory used +host_seconds 0.66 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory @@ -298,8 +298,8 @@ system.cpu.rename.IQFullEvents 14 # Nu system.cpu.rename.LSQFullEvents 13 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 4285 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 6686 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6674 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 6679 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 2517 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index a65f6cef4..91966eab0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index ceaa08d85..47104f06c 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout -Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 07:58:36 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 01:55:20 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 81f115ce9..ca5a55de6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu sim_ticks 16494000 # Number of ticks simulated final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32065 # Simulator instruction rate (inst/s) -host_op_rate 40006 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115159682 # Simulator tick rate (ticks/s) -host_mem_usage 240696 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 19652 # Simulator instruction rate (inst/s) +host_op_rate 24522 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70593484 # Simulator tick rate (ticks/s) +host_mem_usage 246136 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory @@ -354,8 +354,8 @@ system.cpu.rename.IQFullEvents 9 # Nu system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56202 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 51511 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index c7dae4bd5..507cb5799 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index 91a377601..d3be13c32 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 09:14:18 +gem5 compiled Oct 16 2013 01:36:42 +gem5 started Oct 16 2013 01:55:13 gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index ace16d792..add5a91d0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu sim_ticks 16494000 # Number of ticks simulated final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36590 # Simulator instruction rate (inst/s) -host_op_rate 45651 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131406771 # Simulator tick rate (ticks/s) -host_mem_usage 240696 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 22159 # Simulator instruction rate (inst/s) +host_op_rate 27650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79599293 # Simulator tick rate (ticks/s) +host_mem_usage 246136 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory @@ -309,8 +309,8 @@ system.cpu.rename.IQFullEvents 9 # Nu system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 12464 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 56458 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56202 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 51511 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 6791 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index daf8c58a2..8335373d5 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index 64f5582df..a390bccf8 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simout -Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:51:54 -gem5 started Sep 22 2013 05:52:09 +gem5 compiled Oct 16 2013 01:28:28 +gem5 started Oct 16 2013 01:35:02 gem5 executing on zizzer command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index f0a85d261..423a70e1a 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21805500 # Number of ticks simulated final_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44396 # Simulator instruction rate (inst/s) -host_op_rate 44386 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 187676879 # Simulator tick rate (ticks/s) -host_mem_usage 228012 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 31004 # Simulator instruction rate (inst/s) +host_op_rate 31001 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131093072 # Simulator tick rate (ticks/s) +host_mem_usage 229800 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -286,8 +286,8 @@ system.cpu.rename.IQFullEvents 6 # Nu system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 7186 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 14116 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14112 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 13887 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 3788 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 16 # count of serializing insts renamed diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 92f5ec07b..3e13ce8e1 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -87,6 +87,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 14f2d2615..92c45258c 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simout -Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 05:59:47 -gem5 started Sep 22 2013 05:59:59 +gem5 compiled Oct 16 2013 01:29:56 +gem5 started Oct 16 2013 01:35:14 gem5 executing on zizzer command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 9bd3a3844..bf93774ff 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000018 # Nu sim_ticks 18469500 # Number of ticks simulated final_tick 18469500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100626 # Simulator instruction rate (inst/s) -host_op_rate 100602 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 320728752 # Simulator tick rate (ticks/s) -host_mem_usage 223260 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 33738 # Simulator instruction rate (inst/s) +host_op_rate 33735 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 107564291 # Simulator tick rate (ticks/s) +host_mem_usage 225768 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -285,8 +285,8 @@ system.cpu.rename.IQFullEvents 4 # Nu system.cpu.rename.LSQFullEvents 226 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 9701 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 18192 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18137 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 18166 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 4703 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 3ff31f398..12dff19e9 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=true numIQEntries=64 +numPhysCCRegs=1280 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 2fb7489b2..6fd808106 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:21:36 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:54:57 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index cfacb8ad4..45776fad9 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 19639500 # Number of ticks simulated final_tick 19639500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30549 # Simulator instruction rate (inst/s) -host_op_rate 55338 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 111488682 # Simulator tick rate (ticks/s) -host_mem_usage 243516 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 27608 # Simulator instruction rate (inst/s) +host_op_rate 50013 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 100764572 # Simulator tick rate (ticks/s) +host_mem_usage 247304 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17536 # Number of bytes read from this memory @@ -267,8 +267,8 @@ system.cpu.rename.IQFullEvents 35 # Nu system.cpu.rename.LSQFullEvents 666 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 25267 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 55251 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 55235 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 31469 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 14204 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed @@ -452,7 +452,7 @@ system.cpu.commit.loads 1053 # Nu system.cpu.commit.membars 0 # Number of memory barriers committed system.cpu.commit.branches 1208 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 9654 # Number of committed integer instructions. +system.cpu.commit.int_insts 9653 # Number of committed integer instructions. system.cpu.commit.function_calls 106 # Number of function calls committed. system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits @@ -467,9 +467,11 @@ system.cpu.cpi 7.301115 # CP system.cpu.cpi_total 7.301115 # CPI: Total CPI of All Threads system.cpu.ipc 0.136965 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.136965 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28824 # number of integer regfile reads -system.cpu.int_regfile_writes 17237 # number of integer regfile writes +system.cpu.int_regfile_reads 20780 # number of integer regfile reads +system.cpu.int_regfile_writes 12385 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads +system.cpu.cc_regfile_reads 8044 # number of cc regfile reads +system.cpu.cc_regfile_writes 4852 # number of cc regfile writes system.cpu.misc_regfile_reads 7122 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.toL2Bus.throughput 1362152804 # Throughput (bytes/s) diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index 5c187d2d2..551fc8a46 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic/simout -Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:21:50 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:45:55 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 3b513d323..34f6daec3 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu sim_ticks 5615000 # Number of ticks simulated final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70800 # Simulator instruction rate (inst/s) -host_op_rate 128226 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73842503 # Simulator tick rate (ticks/s) -host_mem_usage 280580 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 57992 # Simulator instruction rate (inst/s) +host_op_rate 105036 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60491180 # Simulator tick rate (ticks/s) +host_mem_usage 236648 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory @@ -42,16 +42,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 209 # number of times a function call or return occured system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9655 # number of integer instructions +system.cpu.num_int_insts 9654 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 24822 # number of times the integer registers were read -system.cpu.num_int_register_writes 11063 # number of times the integer registers were written +system.cpu.num_int_register_reads 18335 # number of times the integer registers were read +system.cpu.num_int_register_writes 7527 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read +system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written system.cpu.num_mem_refs 1988 # number of memory refs system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index b58867c62..967016cd1 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -1,25 +1,10 @@ -Real time: Sep/22/2013 07:07:53 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 - -Virtual_time_in_seconds: 0.43 -Virtual_time_in_minutes: 0.00716667 -Virtual_time_in_hours: 0.000119444 -Virtual_time_in_days: 4.97685e-06 - Ruby_current_time: 121759 Ruby_start_time: 0 Ruby_cycles: 121759 -mbytes_resident: 80.4375 -mbytes_total: 139.961 -resident_ratio: 0.574714 - Busy Controller Counts: L1Cache-0:0 Directory-0:0 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index cb677e65b..78a38ee4d 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simout -Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 07:07:52 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:54:46 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 8372264a3..8e528df87 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000122 # Nu sim_ticks 121759 # Number of ticks simulated final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 28174 # Simulator instruction rate (inst/s) -host_op_rate 51034 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 637400 # Simulator tick rate (ticks/s) -host_mem_usage 143324 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 29550 # Simulator instruction rate (inst/s) +host_op_rate 53526 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 668523 # Simulator tick rate (ticks/s) +host_mem_usage 143652 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits @@ -70,16 +70,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 209 # number of times a function call or return occured system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9655 # number of integer instructions +system.cpu.num_int_insts 9654 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 24822 # number of times the integer registers were read -system.cpu.num_int_register_writes 11063 # number of times the integer registers were written +system.cpu.num_int_register_reads 18335 # number of times the integer registers were read +system.cpu.num_int_register_writes 7527 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read +system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written system.cpu.num_mem_refs 1988 # number of memory refs system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index 628ef5965..c59dbb17e 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simout -Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:21:20 -gem5 started Sep 22 2013 06:48:05 +gem5 compiled Oct 16 2013 01:35:57 +gem5 started Oct 16 2013 01:41:56 gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 0aa71b968..ff37d4bfb 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 28358000 # Number of ticks simulated final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186481 # Simulator instruction rate (inst/s) -host_op_rate 337520 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 981039317 # Simulator tick rate (ticks/s) -host_mem_usage 241472 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 41834 # Simulator instruction rate (inst/s) +host_op_rate 75775 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 220409714 # Simulator tick rate (ticks/s) +host_mem_usage 245252 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory @@ -50,16 +50,18 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9655 # Number of integer alu accesses +system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 209 # number of times a function call or return occured system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9655 # number of integer instructions +system.cpu.num_int_insts 9654 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 24822 # number of times the integer registers were read -system.cpu.num_int_register_writes 11063 # number of times the integer registers were written +system.cpu.num_int_register_reads 18335 # number of times the integer registers were read +system.cpu.num_int_register_writes 7527 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read +system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written system.cpu.num_mem_refs 1988 # number of memory refs system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 5d2204eb4..ffa288769 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 32cdff876..d74926aee 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 03:05:38 +gem5 compiled Oct 15 2013 18:24:51 +gem5 started Oct 16 2013 01:34:33 gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index d195e9d48..12317fca2 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 24404000 # Number of ticks simulated final_tick 24404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 780 # Simulator instruction rate (inst/s) -host_op_rate 780 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1494307 # Simulator tick rate (ticks/s) -host_mem_usage 227936 # Number of bytes of host memory used -host_seconds 16.33 # Real time elapsed on the host +host_inst_rate 12749 # Simulator instruction rate (inst/s) +host_op_rate 12749 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24410850 # Simulator tick rate (ticks/s) +host_mem_usage 229776 # Number of bytes of host memory used +host_seconds 1.00 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory @@ -310,8 +310,8 @@ system.cpu.rename.ROBFullEvents 60 # Nu system.cpu.rename.LSQFullEvents 2293 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 22579 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 37089 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 37055 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups +system.cpu.rename.int_rename_lookups 37071 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 13439 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 57 # count of serializing insts renamed diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index d46e2cc0c..e50ecc67e 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index f835cd945..3384dd19c 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simout -Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:07:44 +gem5 compiled Oct 16 2013 01:31:26 +gem5 started Oct 16 2013 01:35:23 gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 46cdc1496..6e72806cb 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu sim_ticks 26524500 # Number of ticks simulated final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95044 # Simulator instruction rate (inst/s) -host_op_rate 95035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174603061 # Simulator tick rate (ticks/s) -host_mem_usage 232868 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 19767 # Simulator instruction rate (inst/s) +host_op_rate 19766 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36317578 # Simulator tick rate (ticks/s) +host_mem_usage 236084 # Number of bytes of host memory used +host_seconds 0.73 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -265,7 +265,7 @@ system.cpu.rename.IQFullEvents 2 # Nu system.cpu.rename.LSQFullEvents 147 # Number of times rename has blocked due to LSQ full system.cpu.rename.RenamedOperands 23951 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 49456 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 49456 # Number of integer rename lookups +system.cpu.rename.int_rename_lookups 40918 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 10132 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 691 # count of serializing insts renamed diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 717f44afc..80c73e0c8 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -86,6 +86,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 @@ -548,6 +549,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 @@ -991,6 +993,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 @@ -1434,6 +1437,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false numIQEntries=64 +numPhysCCRegs=0 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index f522c13b1..0b0b9c7cf 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,10 +1,8 @@ -Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout -Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:07:31 +gem5 compiled Oct 16 2013 01:31:26 +gem5 started Oct 16 2013 01:35:27 gem5 executing on zizzer command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 53e641a1b..1df87c21b 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000111 # Nu sim_ticks 110804500 # Number of ticks simulated final_tick 110804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170931 # Simulator instruction rate (inst/s) -host_op_rate 170931 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18163832 # Simulator tick rate (ticks/s) -host_mem_usage 247816 # Number of bytes of host memory used -host_seconds 6.10 # Real time elapsed on the host +host_inst_rate 91896 # Simulator instruction rate (inst/s) +host_op_rate 91896 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9765210 # Simulator tick rate (ticks/s) +host_mem_usage 250112 # Number of bytes of host memory used +host_seconds 11.35 # Real time elapsed on the host sim_insts 1042724 # Number of instructions simulated sim_ops 1042724 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory @@ -750,7 +750,7 @@ system.cpu0.rename.RenamedInsts 486837 # Nu system.cpu0.rename.LSQFullEvents 188 # Number of times rename has blocked due to LSQ full system.cpu0.rename.RenamedOperands 332900 # Number of destination operands rename has renamed system.cpu0.rename.RenameLookups 970872 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 970872 # Number of integer rename lookups +system.cpu0.rename.int_rename_lookups 733333 # Number of integer rename lookups system.cpu0.rename.CommittedMaps 319955 # Number of HB maps that are committed system.cpu0.rename.UndoneMaps 12945 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed @@ -1226,7 +1226,7 @@ system.cpu1.rename.IQFullEvents 4 # Nu system.cpu1.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full system.cpu1.rename.RenamedOperands 156532 # Number of destination operands rename has renamed system.cpu1.rename.RenameLookups 420697 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 420697 # Number of integer rename lookups +system.cpu1.rename.int_rename_lookups 330316 # Number of integer rename lookups system.cpu1.rename.CommittedMaps 143693 # Number of HB maps that are committed system.cpu1.rename.UndoneMaps 12839 # Number of HB maps that are undone due to squashing system.cpu1.rename.serializingInsts 1114 # count of serializing insts renamed @@ -1701,7 +1701,7 @@ system.cpu2.rename.IQFullEvents 4 # Nu system.cpu2.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full system.cpu2.rename.RenamedOperands 196553 # Number of destination operands rename has renamed system.cpu2.rename.RenameLookups 537620 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 537620 # Number of integer rename lookups +system.cpu2.rename.int_rename_lookups 418050 # Number of integer rename lookups system.cpu2.rename.CommittedMaps 183508 # Number of HB maps that are committed system.cpu2.rename.UndoneMaps 13045 # Number of HB maps that are undone due to squashing system.cpu2.rename.serializingInsts 1112 # count of serializing insts renamed @@ -2176,7 +2176,7 @@ system.cpu3.rename.IQFullEvents 1 # Nu system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full system.cpu3.rename.RenamedOperands 219058 # Number of destination operands rename has renamed system.cpu3.rename.RenameLookups 604346 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 604346 # Number of integer rename lookups +system.cpu3.rename.int_rename_lookups 468076 # Number of integer rename lookups system.cpu3.rename.CommittedMaps 206290 # Number of HB maps that are committed system.cpu3.rename.UndoneMaps 12768 # Number of HB maps that are undone due to squashing system.cpu3.rename.serializingInsts 1082 # count of serializing insts renamed |