diff options
47 files changed, 640 insertions, 449 deletions
diff --git a/src/arch/x86/isa/decoder/locked_opcodes.isa b/src/arch/x86/isa/decoder/locked_opcodes.isa index f38f2abb8..14d5e58a3 100644 --- a/src/arch/x86/isa/decoder/locked_opcodes.isa +++ b/src/arch/x86/isa/decoder/locked_opcodes.isa @@ -160,7 +160,8 @@ 0x1: XADD_LOCKED(Mv,Gv); //0x7: group9(); 0x7: decode MODRM_REG { - 0x1: WarnUnimpl::cmpxchg_Mq_LOCKED(); + //Also CMPXCHG16B + 0x1: CMPXCHG8B_LOCKED(Mdp); } } } diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index f365ed4b0..d6cfdc593 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -544,7 +544,7 @@ 0x5: IMUL_B(Eb); //This should be Eb, but it access the entire word value ax. 0x6: DIV_B(Ew); - 0x7: IDIV(Eb); + 0x7: IDIV_B(Eb); } //0x7: group3_Ev(); 0x7: decode MODRM_REG { diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index c344ee550..55056da81 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -820,8 +820,8 @@ Rdx = result.rdx; }}); 0x3: Inst::BT(Ev,Gv); - 0x4: shld_Ev_Gv_Ib(); - 0x5: shld_Ev_Gv_rCl(); + 0x4: Inst::SHLD(Ev,Gv,Ib); + 0x5: Inst::SHLD(Ev,Gv); 0x6: xbts_and_cmpxchg(); 0x7: ibts_and_cmpxchg(); } @@ -831,7 +831,7 @@ 0x2: rsm_smm(); 0x3: Inst::BTS(Ev,Gv); 0x4: Inst::SHRD(Ev,Gv,Ib); - 0x5: shrd_Ev_Gv_rCl(); + 0x5: Inst::SHRD(Ev,Gv); //0x6: group16(); 0x6: decode MODRM_REG { 0x0: fxsave(); @@ -898,7 +898,8 @@ 0x1: Inst::XADD(Ev,Gv); //0x7: group9(); 0x7: decode MODRM_REG { - 0x1: cmpxchg_Mq(); + //Also CMPXCHG16B + 0x1: Inst::CMPXCHG8B(Mdp); 0x6: decode LEGACY_OP { 0x1: vmclear_Mq(); default: decode LEGACY_REP { @@ -1067,7 +1068,7 @@ } default: Inst::UD2(); } - 0x1E: decode OPCODE_OP_BOTTOM3 { + 0x1E: decode LEGACY_DECODEVAL { // no prefix 0x0: decode OPCODE_OP_BOTTOM3 { 0x1: psllw_Pq_Qq(); diff --git a/src/arch/x86/isa/insts/general_purpose/arithmetic/multiply_and_divide.py b/src/arch/x86/isa/insts/general_purpose/arithmetic/multiply_and_divide.py index dbc803350..47ad1d53c 100644 --- a/src/arch/x86/isa/insts/general_purpose/arithmetic/multiply_and_divide.py +++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/multiply_and_divide.py @@ -388,7 +388,6 @@ def macroop IDIV_B_R sub t2, t2, t4 #Find the sign of the divisor - #FIXME!!! This depends on shifts setting the carry flag correctly. slli t0, reg, 1, flags=(ECF,), dataSize=1 # Negate divisor @@ -397,7 +396,6 @@ def macroop IDIV_B_R mov t3, t3, reg, flags=(nCECF,), dataSize=1 #Find the sign of the dividend - #FIXME!!! This depends on shifts setting the carry flag correctly. slli t0, ah, 1, flags=(ECF,), dataSize=1 # Put the dividend's absolute value into t1 and t2 @@ -440,7 +438,7 @@ divLoopTop: mov t5, t5, t4, (CECF,), dataSize=1 # Check the sign of the divisor - slli t0, t3, 1, flags=(ECF,), dataSize=1 + slli t0, reg, 1, flags=(ECF,), dataSize=1 # Negate the (possibly already negated) quotient sub t4, t0, t5, dataSize=1 @@ -458,19 +456,17 @@ def macroop IDIV_B_M sub t2, t0, ah, dataSize=1 sub t2, t2, t4 - ld t3, seg, sib, disp + ld t8, seg, sib, disp #Find the sign of the divisor - #FIXME!!! This depends on shifts setting the carry flag correctly. slli t0, t3, 1, flags=(ECF,), dataSize=1 # Negate divisor - sub t4, t0, t3, dataSize=1 + sub t3, t0, t8, dataSize=1 # Put the divisor's absolute value into t3 - mov t3, t3, t4, flags=(CECF,), dataSize=1 + mov t3, t3, t8, flags=(nCECF,), dataSize=1 #Find the sign of the dividend - #FIXME!!! This depends on shifts setting the carry flag correctly. slli t0, ah, 1, flags=(ECF,), dataSize=1 # Put the dividend's absolute value into t1 and t2 @@ -513,7 +509,7 @@ divLoopTop: mov t5, t5, t4, (CECF,), dataSize=1 # Check the sign of the divisor - slli t0, t3, 1, flags=(ECF,), dataSize=1 + slli t0, t8, 1, flags=(ECF,), dataSize=1 # Negate the (possibly already negated) quotient sub t4, t0, t5, dataSize=1 @@ -532,19 +528,17 @@ def macroop IDIV_B_P sub t2, t2, t4 rdip t7 - ld t3, seg, riprel, disp + ld t8, seg, riprel, disp #Find the sign of the divisor - #FIXME!!! This depends on shifts setting the carry flag correctly. slli t0, t3, 1, flags=(ECF,), dataSize=1 # Negate divisor - sub t4, t0, t3, dataSize=1 + sub t3, t0, t8, dataSize=1 # Put the divisor's absolute value into t3 - mov t3, t3, t4, flags=(CECF,), dataSize=1 + mov t3, t3, t8, flags=(nCECF,), dataSize=1 #Find the sign of the dividend - #FIXME!!! This depends on shifts setting the carry flag correctly. slli t0, ah, 1, flags=(ECF,), dataSize=1 # Put the dividend's absolute value into t1 and t2 @@ -587,7 +581,7 @@ divLoopTop: mov t5, t5, t4, (CECF,), dataSize=1 # Check the sign of the divisor - slli t0, t3, 1, flags=(ECF,), dataSize=1 + slli t0, t8, 1, flags=(ECF,), dataSize=1 # Negate the (possibly already negated) quotient sub t4, t0, t5, dataSize=1 @@ -610,7 +604,6 @@ def macroop IDIV_R sub t2, t2, t4 #Find the sign of the divisor - #FIXME!!! This depends on shifts setting the carry flag correctly. slli t0, reg, 1, flags=(ECF,) # Negate divisor @@ -619,7 +612,6 @@ def macroop IDIV_R mov t3, t3, reg, flags=(nCECF,) #Find the sign of the dividend - #FIXME!!! This depends on shifts setting the carry flag correctly. slli t0, rdx, 1, flags=(ECF,) # Put the dividend's absolute value into t1 and t2 @@ -664,7 +656,7 @@ divLoopTop: mov t5, t5, t4, (CECF,) # Check the sign of the divisor - slli t0, t3, 1, flags=(ECF,) + slli t0, reg, 1, flags=(ECF,) # Negate the (possibly already negated) quotient sub t4, t0, t5 @@ -682,16 +674,16 @@ def macroop IDIV_M sub t2, t0, rdx sub t2, t2, t4 - ld t3, seg, sib, disp + ld t8, seg, sib, disp #Find the sign of the divisor #FIXME!!! This depends on shifts setting the carry flag correctly. slli t0, t3, 1, flags=(ECF,) # Negate divisor - sub t4, t0, t3 + sub t3, t0, t8 # Put the divisor's absolute value into t3 - mov t3, t3, t4, flags=(CECF,) + mov t3, t3, t8, flags=(nCECF,) #Find the sign of the dividend #FIXME!!! This depends on shifts setting the carry flag correctly. @@ -739,7 +731,7 @@ divLoopTop: mov t5, t5, t4, (CECF,) # Check the sign of the divisor - slli t0, t3, 1, flags=(ECF,) + slli t0, t8, 1, flags=(ECF,) # Negate the (possibly already negated) quotient sub t4, t0, t5 @@ -758,16 +750,16 @@ def macroop IDIV_P sub t2, t2, t4 rdip t7 - ld t3, seg, riprel, disp + ld t8, seg, riprel, disp #Find the sign of the divisor #FIXME!!! This depends on shifts setting the carry flag correctly. slli t0, t3, 1, flags=(ECF,) # Negate divisor - sub t4, t0, t3 + sub t3, t0, t8 # Put the divisor's absolute value into t3 - mov t3, t3, t4, flags=(CECF,) + mov t3, t3, t4, flags=(nCECF,) #Find the sign of the dividend #FIXME!!! This depends on shifts setting the carry flag correctly. @@ -815,7 +807,7 @@ divLoopTop: mov t5, t5, t4, (CECF,) # Check the sign of the divisor - slli t0, t3, 1, flags=(ECF,) + slli t0, t8, 1, flags=(ECF,) # Negate the (possibly already negated) quotient sub t4, t0, t5 diff --git a/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py b/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py index ac2343462..f6aac1761 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py +++ b/src/arch/x86/isa/insts/general_purpose/data_conversion/endian_conversion.py @@ -64,15 +64,15 @@ def macroop BSWAP_D_R def macroop BSWAP_Q_R { roli reg, reg, 8, dataSize=2 - roli reg, reg, 16, dataSize=4 - roli reg, reg, 8, dataSize=2 - roli reg, reg, 32, dataSize=8 - roli reg, reg, 8, dataSize=2 - roli reg, reg, 16, dataSize=4 - roli reg, reg, 8, dataSize=2 + roli t1, reg, 16, dataSize=4 + # Top 4 bytes of t1 are now zero + roli t1, t1, 8, dataSize=2 + roli t1, t1, 32, dataSize=8 + srli t2, reg, 32, dataSize=8 + roli t2, t2, 8, dataSize=2 + roli t2, t2, 16, dataSize=4 + # Top 4 bytes of t2 are now zero + roli t2, t2, 8, dataSize=2 + or reg, t1, t2, dataSize=8 }; ''' -#let {{ -# class BSWAP(Inst): -# "GenFault ${new UnimpInstFault}" -#}}; diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py index 1a60c5b61..264bbe370 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/conditional_move.py @@ -56,12 +56,14 @@ microcode = ''' def macroop CMOVZ_R_R { + mov reg, reg, reg, flags=(nCZF,) mov reg, reg, regm, flags=(CZF,) }; def macroop CMOVZ_R_M { ld t1, seg, sib, disp + mov reg, reg, reg, flags=(nCZF,) mov reg, reg, t1, flags=(CZF,) }; @@ -69,17 +71,20 @@ def macroop CMOVZ_R_P { rdip t7 ld t1, seg, riprel, disp + mov reg, reg, reg, flags=(nCZF,) mov reg, reg, t1, flags=(CZF,) }; def macroop CMOVNZ_R_R { + mov reg, reg, reg, flags=(CZF,) mov reg, reg, regm, flags=(nCZF,) }; def macroop CMOVNZ_R_M { ld t1, seg, sib, disp + mov reg, reg, reg, flags=(CZF,) mov reg, reg, t1, flags=(nCZF,) }; @@ -87,17 +92,20 @@ def macroop CMOVNZ_R_P { rdip t7 ld t1, seg, riprel, disp + mov reg, reg, reg, flags=(CZF,) mov reg, reg, t1, flags=(nCZF,) }; def macroop CMOVB_R_R { + mov reg, reg, reg, flags=(nCCF,) mov reg, reg, regm, flags=(CCF,) }; def macroop CMOVB_R_M { ld t1, seg, sib, disp + mov reg, reg, reg, flags=(nCCF,) mov reg, reg, t1, flags=(CCF,) }; @@ -105,17 +113,20 @@ def macroop CMOVB_R_P { rdip t7 ld t1, seg, riprel, disp + mov reg, reg, reg, flags=(nCCF,) mov reg, reg, t1, flags=(CCF,) }; def macroop CMOVNB_R_R { + mov reg, reg, reg, flags=(CCF,) mov reg, reg, regm, flags=(nCCF,) }; def macroop CMOVNB_R_M { ld t1, seg, sib, disp + mov reg, reg, reg, flags=(CCF,) mov reg, reg, t1, flags=(nCCF,) }; @@ -123,17 +134,20 @@ def macroop CMOVNB_R_P { rdip t7 ld t1, seg, riprel, disp + mov reg, reg, reg, flags=(CCF,) mov reg, reg, t1, flags=(nCCF,) }; def macroop CMOVBE_R_R { + mov reg, reg, reg, flags=(nCCvZF,) mov reg, reg, regm, flags=(CCvZF,) }; def macroop CMOVBE_R_M { ld t1, seg, sib, disp + mov reg, reg, reg, flags=(nCCvZF,) mov reg, reg, t1, flags=(CCvZF,) }; @@ -141,17 +155,20 @@ def macroop CMOVBE_R_P { rdip t7 ld t1, seg, riprel, disp + mov reg, reg, reg, flags=(nCCvZF,) mov reg, reg, t1, flags=(CCvZF,) }; def macroop CMOVNBE_R_R { + mov reg, reg, reg, flags=(CCvZF,) mov reg, reg, regm, flags=(nCCvZF,) }; def macroop CMOVNBE_R_M { ld t1, seg, sib, disp + mov reg, reg, reg, flags=(CCvZF,) mov reg, reg, t1, flags=(nCCvZF,) }; @@ -159,17 +176,20 @@ def macroop CMOVNBE_R_P { rdip t7 ld t1, seg, riprel, disp + mov reg, reg, reg, flags=(CCvZF,) mov reg, reg, t1, flags=(nCCvZF,) }; def macroop CMOVS_R_R { + mov reg, reg, reg, flags=(nCSF,) mov reg, reg, regm, flags=(CSF,) }; def macroop CMOVS_R_M { ld t1, seg, sib, disp + mov reg, reg, reg, flags=(nCSF,) mov reg, reg, t1, flags=(CSF,) }; @@ -177,17 +197,20 @@ def macroop CMOVS_R_P { rdip t7 ld t1, seg, riprel, disp + mov reg, reg, reg, flags=(nCSF,) mov reg, reg, t1, flags=(CSF,) }; def macroop CMOVNS_R_R { + mov reg, reg, reg, flags=(CSF,) mov reg, reg, regm, flags=(nCSF,) }; def macroop CMOVNS_R_M { ld t1, seg, sib, disp + mov reg, reg, reg, flags=(CSF,) mov reg, reg, t1, flags=(nCSF,) }; @@ -195,17 +218,20 @@ def macroop CMOVNS_R_P { rdip t7 ld t1, seg, riprel, disp + mov reg, reg, reg, flags=(CSF,) mov reg, reg, t1, flags=(nCSF,) }; def macroop CMOVP_R_R { + mov reg, reg, reg, flags=(nCPF,) mov reg, reg, regm, flags=(CPF,) }; def macroop CMOVP_R_M { ld t1, seg, sib, disp + mov reg, reg, reg, flags=(nCPF,) mov reg, reg, t1, flags=(CPF,) }; @@ -213,35 +239,41 @@ def macroop CMOVP_R_P { rdip t7 ld t1, seg, riprel, disp + mov reg, reg, reg, flags=(nCPF,) mov reg, reg, t1, flags=(CPF,) }; def macroop CMOVNP_R_R { + mov reg, reg, reg, flags=(CPF,) mov reg, reg, regm, flags=(nCPF,) }; def macroop CMOVNP_R_M { ld t1, seg, sib, disp - mov reg, reg, regm, flags=(nCPF,) + mov reg, reg, reg, flags=(CPF,) + mov reg, reg, t1, flags=(nCPF,) }; def macroop CMOVNP_R_P { rdip t7 ld t1, seg, riprel, disp - mov reg, reg, regm, flags=(nCPF,) + mov reg, reg, reg, flags=(CPF,) + mov reg, reg, t1, flags=(nCPF,) }; def macroop CMOVL_R_R { + mov reg, reg, reg, flags=(nCSxOF,) mov reg, reg, regm, flags=(CSxOF,) }; def macroop CMOVL_R_M { ld t1, seg, sib, disp + mov reg, reg, reg, flags=(nCSxOF,) mov reg, reg, t1, flags=(CSxOF,) }; @@ -249,17 +281,20 @@ def macroop CMOVL_R_P { rdip t7 ld t1, seg, riprel, disp + mov reg, reg, reg, flags=(nCSxOF,) mov reg, reg, t1, flags=(CSxOF,) }; def macroop CMOVNL_R_R { + mov reg, reg, reg, flags=(CSxOF,) mov reg, reg, regm, flags=(nCSxOF,) }; def macroop CMOVNL_R_M { ld t1, seg, sib, disp + mov reg, reg, reg, flags=(CSxOF,) mov reg, reg, t1, flags=(nCSxOF,) }; @@ -267,17 +302,20 @@ def macroop CMOVNL_R_P { rdip t7 ld t1, seg, riprel, disp + mov reg, reg, reg, flags=(CSxOF,) mov reg, reg, t1, flags=(nCSxOF,) }; def macroop CMOVLE_R_R { + mov reg, reg, reg, flags=(nCSxOvZF,) mov reg, reg, regm, flags=(CSxOvZF,) }; def macroop CMOVLE_R_M { ld t1, seg, sib, disp + mov reg, reg, reg, flags=(nCSxOvZF,) mov reg, reg, t1, flags=(CSxOvZF,) }; @@ -285,17 +323,20 @@ def macroop CMOVLE_R_P { rdip t7 ld t1, seg, riprel, disp + mov reg, reg, reg, flags=(nCSxOvZF,) mov reg, reg, t1, flags=(CSxOvZF,) }; def macroop CMOVNLE_R_R { + mov reg, reg, reg, flags=(CSxOvZF,) mov reg, reg, regm, flags=(nCSxOvZF,) }; def macroop CMOVNLE_R_M { ld t1, seg, sib, disp + mov reg, reg, reg, flags=(CSxOvZF,) mov reg, reg, t1, flags=(nCSxOvZF,) }; @@ -303,17 +344,20 @@ def macroop CMOVNLE_R_P { rdip t7 ld t1, seg, riprel, disp + mov reg, reg, reg, flags=(CSxOvZF,) mov reg, reg, t1, flags=(nCSxOvZF,) }; def macroop CMOVO_R_R { + mov reg, reg, reg, flags=(nCOF,) mov reg, reg, regm, flags=(COF,) }; def macroop CMOVO_R_M { ld t1, seg, sib, disp + mov reg, reg, reg, flags=(nCOF,) mov reg, reg, t1, flags=(COF,) }; @@ -321,17 +365,20 @@ def macroop CMOVO_R_P { rdip t7 ld t1, seg, riprel, disp + mov reg, reg, reg, flags=(nCOF,) mov reg, reg, t1, flags=(COF,) }; def macroop CMOVNO_R_R { + mov reg, reg, reg, flags=(COF,) mov reg, reg, regm, flags=(nCOF,) }; def macroop CMOVNO_R_M { ld t1, seg, sib, disp + mov reg, reg, reg, flags=(COF,) mov reg, reg, t1, flags=(nCOF,) }; @@ -339,6 +386,7 @@ def macroop CMOVNO_R_P { rdip t7 ld t1, seg, riprel, disp + mov reg, reg, reg, flags=(COF,) mov reg, reg, t1, flags=(nCOF,) }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py index f4c8a4663..6b18caef0 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py @@ -150,28 +150,29 @@ def macroop LEAVE { # Make the default data size of pops 64 bits in 64 bit mode .adjust_env oszIn64Override - mov t1, t1, rbp, dataSize=asz + mov t1, t1, rbp, dataSize=ssz ld rbp, ss, [1, t0, t1], dataSize=ssz - mov rsp, rsp, t1, dataSize=asz - addi rsp, rsp, ssz, dataSize=asz + mov rsp, rsp, t1, dataSize=ssz + addi rsp, rsp, ssz, dataSize=ssz }; def macroop ENTER_I_I { + .adjust_env oszIn64Override # This needs to check all the addresses it writes to before it actually # writes any values. # Pull the different components out of the immediate - limm t1, imm + limm t1, imm, dataSize=8 zexti t2, t1, 15, dataSize=8 - srli t1, t1, 16 + srli t1, t1, 16, dataSize=8 zexti t1, t1, 5, dataSize=8 # t1 is now the masked nesting level, and t2 is the amount of storage. # Push rbp. - stupd rbp, ss, [1, t0, rsp], "-env.stackSize", dataSize=ssz + stupd rbp, ss, [1, t0, rsp], "-env.dataSize" # Save the stack pointer for later - mov t6, t6, rsp, dataSize=asz + mov t6, t6, rsp # If the nesting level is zero, skip all this stuff. sub t0, t1, t0, flags=(EZF,), dataSize=2 @@ -183,8 +184,8 @@ def macroop ENTER_I_I { limm t4, "ULL(-1)", dataSize=8 topOfLoop: - ld t5, ss, [ssz, t4, rbp], dataSize=ssz - stupd t5, ss, [1, t0, rsp], "-env.stackSize" + ld t5, ss, [dsz, t4, rbp] + stupd t5, ss, [1, t0, rsp], "-env.dataSize" # If we're not done yet, loop subi t4, t4, 1, dataSize=8 @@ -193,10 +194,10 @@ topOfLoop: bottomOfLoop: # Push the old rbp onto the stack - stupd t6, ss, [1, t0, rsp], "-env.stackSize" + stupd t6, ss, [1, t0, rsp], "-env.dataSize" skipLoop: - sub rsp, rsp, t2, dataSize=asz - mov rbp, rbp, t6, dataSize=asz + sub rsp, rsp, t2, dataSize=ssz + mov rbp, rbp, t6 }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py index caaeca974..092fb4213 100644 --- a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py +++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py @@ -114,6 +114,52 @@ def macroop SAL_P_R st t1, seg, riprel, disp }; +def macroop SHLD_R_R +{ + mdbi regm, 0 + sld reg, reg, rcx, flags=(CF,OF,SF,ZF,PF) +}; + +def macroop SHLD_M_R +{ + ldst t1, seg, sib, disp + mdbi reg, 0 + sld t1, t1, rcx, flags=(CF,OF,SF,ZF,PF) + st t1, seg, sib, disp +}; + +def macroop SHLD_P_R +{ + rdip t7 + ldst t1, seg, riprel, disp + mdbi reg, 0 + sld t1, t1, rcx, flags=(CF,OF,SF,ZF,PF) + st t1, seg, riprel, disp +}; + +def macroop SHLD_R_R_I +{ + mdbi regm, 0 + sldi reg, reg, imm, flags=(CF,OF,SF,ZF,PF) +}; + +def macroop SHLD_M_R_I +{ + ldst t1, seg, sib, disp + mdbi reg, 0 + sldi t1, t1, imm, flags=(CF,OF,SF,ZF,PF) + st t1, seg, sib, disp +}; + +def macroop SHLD_P_R_I +{ + rdip t7 + ldst t1, seg, riprel, disp + mdbi reg, 0 + sldi t1, t1, imm, flags=(CF,OF,SF,ZF,PF) + st t1, seg, riprel, disp +}; + def macroop SHR_R_I { srli reg, reg, imm, flags=(CF,OF,SF,ZF,PF) @@ -174,38 +220,49 @@ def macroop SHR_P_R st t1, seg, riprel, disp }; -# SHRD will not set OF correctly when the shift count is 1. +def macroop SHRD_R_R +{ + mdbi regm, 0 + srd reg, reg, rcx, flags=(CF,OF,SF,ZF,PF) +}; + +def macroop SHRD_M_R +{ + ldst t1, seg, sib, disp + mdbi reg, 0 + srd t1, t1, rcx, flags=(CF,OF,SF,ZF,PF) + st t1, seg, sib, disp +}; + +def macroop SHRD_P_R +{ + rdip t7 + ldst t1, seg, riprel, disp + mdbi reg, 0 + srd t1, t1, rcx, flags=(CF,OF,SF,ZF,PF) + st t1, seg, riprel, disp +}; + def macroop SHRD_R_R_I { - srli t1, reg, imm, flags=(CF,) - rori t2, regm, imm - srli t3, regm, imm - xor t2, t2, t3 - or reg, t1, t2 + mdbi regm, 0 + srdi reg, reg, imm, flags=(CF,OF,SF,ZF,PF) }; -# SHRD will not set OF correctly when the shift count is 1. def macroop SHRD_M_R_I { ldst t1, seg, sib, disp - srli t1, t1, imm, flags=(CF,) - rori t2, reg, imm - srli t3, reg, imm - xor t2, t2, t3 - or t1, t1, t2 + mdbi reg, 0 + srdi t1, t1, imm, flags=(CF,OF,SF,ZF,PF) st t1, seg, sib, disp }; -# SHRD will not set OF correctly when the shift count is 1. def macroop SHRD_P_R_I { rdip t7 ldst t1, seg, riprel, disp - srli t1, t1, imm, flags=(CF,) - rori t2, reg, imm - srli t3, reg, imm - xor t2, t2, t3 - or t1, t1, t2 + mdbi reg, 0 + srdi t1, t1, imm, flags=(CF,OF,SF,ZF,PF) st t1, seg, riprel, disp }; diff --git a/src/arch/x86/isa/insts/general_purpose/semaphores.py b/src/arch/x86/isa/insts/general_purpose/semaphores.py index a7da0720e..2bdbd0ada 100644 --- a/src/arch/x86/isa/insts/general_purpose/semaphores.py +++ b/src/arch/x86/isa/insts/general_purpose/semaphores.py @@ -98,6 +98,100 @@ def macroop CMPXCHG_LOCKED_P_R { mov rax, rax, t1, flags=(nCZF,) }; +def macroop CMPXCHG8B_M { + lea t1, seg, sib, disp, dataSize=asz + ldst t2, seg, [1, t0, t1], 0 + ldst t3, seg, [1, t0, t1], dsz + + sub t0, rax, t2, flags=(ZF,) + br label("doneComparing"), flags=(nCZF,) + sub t0, rdx, t3, flags=(ZF,) +doneComparing: + + # If they're equal, set t3:t2 to rbx:rcx to write to memory + mov t2, t2, rbx, flags=(CZF,) + mov t3, t3, rcx, flags=(CZF,) + + # If they're not equal, set rdx:rax to the value from memory. + mov rax, rax, t2, flags=(nCZF,) + mov rdx, rdx, t3, flags=(nCZF,) + + # Write to memory + st t3, seg, [1, t0, t1], dsz + st t2, seg, [1, t0, t1], 0 +}; + +def macroop CMPXCHG8B_P { + rdip t7 + lea t1, seg, riprel, disp, dataSize=asz + ldst t2, seg, [1, t0, t1], 0 + ldst t3, seg, [1, t0, t1], dsz + + sub t0, rax, t2, flags=(ZF,) + br label("doneComparing"), flags=(nCZF,) + sub t0, rdx, t3, flags=(ZF,) +doneComparing: + + # If they're equal, set t3:t2 to rbx:rcx to write to memory + mov t2, t2, rbx, flags=(CZF,) + mov t3, t3, rcx, flags=(CZF,) + + # If they're not equal, set rdx:rax to the value from memory. + mov rax, rax, t2, flags=(nCZF,) + mov rdx, rdx, t3, flags=(nCZF,) + + # Write to memory + st t3, seg, [1, t0, t1], dsz + st t2, seg, [1, t0, t1], 0 +}; + +def macroop CMPXCHG8B_LOCKED_M { + lea t1, seg, sib, disp, dataSize=asz + ldstl t2, seg, [1, t0, t1], 0 + ldstl t3, seg, [1, t0, t1], dsz + + sub t0, rax, t2, flags=(ZF,) + br label("doneComparing"), flags=(nCZF,) + sub t0, rdx, t3, flags=(ZF,) +doneComparing: + + # If they're equal, set t3:t2 to rbx:rcx to write to memory + mov t2, t2, rbx, flags=(CZF,) + mov t3, t3, rcx, flags=(CZF,) + + # If they're not equal, set rdx:rax to the value from memory. + mov rax, rax, t2, flags=(nCZF,) + mov rdx, rdx, t3, flags=(nCZF,) + + # Write to memory + stul t3, seg, [1, t0, t1], dsz + stul t2, seg, [1, t0, t1], 0 +}; + +def macroop CMPXCHG8B_LOCKED_P { + rdip t7 + lea t1, seg, riprel, disp, dataSize=asz + ldstl t2, seg, [1, t0, t1], 0 + ldstl t3, seg, [1, t0, t1], dsz + + sub t0, rax, t2, flags=(ZF,) + br label("doneComparing"), flags=(nCZF,) + sub t0, rdx, t3, flags=(ZF,) +doneComparing: + + # If they're equal, set t3:t2 to rbx:rcx to write to memory + mov t2, t2, rbx, flags=(CZF,) + mov t3, t3, rcx, flags=(CZF,) + + # If they're not equal, set rdx:rax to the value from memory. + mov rax, rax, t2, flags=(nCZF,) + mov rdx, rdx, t3, flags=(nCZF,) + + # Write to memory + stul t3, seg, [1, t0, t1], dsz + stul t2, seg, [1, t0, t1], 0 +}; + def macroop XADD_M_R { ldst t1, seg, sib, disp add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF) diff --git a/src/arch/x86/isa/insts/general_purpose/string/scan_string.py b/src/arch/x86/isa/insts/general_purpose/string/scan_string.py index 5b0e74aad..5115fe8a2 100644 --- a/src/arch/x86/isa/insts/general_purpose/string/scan_string.py +++ b/src/arch/x86/isa/insts/general_purpose/string/scan_string.py @@ -62,7 +62,7 @@ def macroop SCAS_M { mov t2, t2, t3, flags=(nCEZF,), dataSize=asz ld t1, es, [1, t0, rdi] - sub t0, t1, rax, flags=(OF, SF, ZF, AF, PF, CF) + sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF) add rdi, rdi, t2, dataSize=asz }; @@ -84,7 +84,7 @@ def macroop SCAS_E_M { topOfLoop: ld t1, es, [1, t0, rdi] - sub t0, t1, rax, flags=(OF, SF, ZF, AF, PF, CF) + sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF) subi rcx, rcx, 1, flags=(EZF,), dataSize=asz add rdi, rdi, t2, dataSize=asz @@ -105,7 +105,7 @@ def macroop SCAS_N_M { topOfLoop: ld t1, es, [1, t0, rdi] - sub t0, t1, rax, flags=(OF, SF, ZF, AF, PF, CF) + sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF) subi rcx, rcx, 1, flags=(EZF,), dataSize=asz add rdi, rdi, t2, dataSize=asz diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index dc6819886..a4cb6f4cc 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -639,7 +639,7 @@ let {{ class Mov(CondRegOp): code = 'DestReg = merge(SrcReg1, op2, dataSize)' - else_code = 'DestReg = merge(DestReg, DestReg, dataSize);' + else_code = 'DestReg = DestReg;' # Shift instructions @@ -884,6 +884,107 @@ let {{ } ''' + class Sld(RegOp): + code = ''' + uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); + uint8_t dataBits = dataSize * 8; + uint8_t realShiftAmt = shiftAmt % (2 * dataBits); + uint64_t result; + if (realShiftAmt == 0) { + result = psrc1; + } else if (realShiftAmt < dataBits) { + result = (psrc1 << realShiftAmt) | + (DoubleBits >> (dataBits - realShiftAmt)); + } else { + result = (DoubleBits << (realShiftAmt - dataBits)) | + (psrc1 >> (2 * dataBits - realShiftAmt)); + } + DestReg = merge(DestReg, result, dataSize); + ''' + flag_code = ''' + // If the shift amount is zero, no flags should be modified. + if (shiftAmt) { + //Zero out any flags we might modify. This way we only have to + //worry about setting them. + ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); + int CFBits = 0; + //Figure out if we -would- set the CF bits if requested. + if ((realShiftAmt == 0 && + bits(DoubleBits, 0)) || + (realShiftAmt <= dataBits && + bits(SrcReg1, dataBits - realShiftAmt)) || + (realShiftAmt > dataBits && + bits(DoubleBits, 2 * dataBits - realShiftAmt))) { + CFBits = 1; + } + //If some combination of the CF bits need to be set, set them. + if ((ext & (CFBit | ECFBit)) && CFBits) + ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); + //Figure out what the OF bit should be. + if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ + bits(result, dataBits - 1))) + ccFlagBits = ccFlagBits | OFBit; + //Use the regular mechanisms to calculate the other flags. + ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), + DestReg, psrc1, op2); + } + ''' + + class Srd(RegOp): + code = ''' + uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); + uint8_t dataBits = dataSize * 8; + uint8_t realShiftAmt = shiftAmt % (2 * dataBits); + uint64_t result; + if (realShiftAmt == 0) { + result = psrc1; + } else if (realShiftAmt < dataBits) { + // Because what happens to the bits shift -in- on a right + // shift is not defined in the C/C++ standard, we have to + // mask them out to be sure they're zero. + uint64_t logicalMask = mask(dataBits - realShiftAmt); + result = ((psrc1 >> realShiftAmt) & logicalMask) | + (DoubleBits << (dataBits - realShiftAmt)); + } else { + uint64_t logicalMask = mask(2 * dataBits - realShiftAmt); + result = ((DoubleBits >> (realShiftAmt - dataBits)) & + logicalMask) | + (psrc1 << (2 * dataBits - realShiftAmt)); + } + DestReg = merge(DestReg, result, dataSize); + ''' + flag_code = ''' + // If the shift amount is zero, no flags should be modified. + if (shiftAmt) { + //Zero out any flags we might modify. This way we only have to + //worry about setting them. + ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); + int CFBits = 0; + //If some combination of the CF bits need to be set, set them. + if ((realShiftAmt == 0 && + bits(DoubleBits, dataBits - 1)) || + (realShiftAmt <= dataBits && + bits(SrcReg1, realShiftAmt - 1)) || + (realShiftAmt > dataBits && + bits(DoubleBits, realShiftAmt - dataBits - 1))) { + CFBits = 1; + } + //If some combination of the CF bits need to be set, set them. + if ((ext & (CFBit | ECFBit)) && CFBits) + ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); + //Figure out what the OF bit should be. + if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ + bits(result, dataBits - 1))) + ccFlagBits = ccFlagBits | OFBit; + //Use the regular mechanisms to calculate the other flags. + ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), + DestReg, psrc1, op2); + } + ''' + + class Mdb(WrRegOp): + code = 'DoubleBits = psrc1 ^ op2;' + class Wrip(WrRegOp, CondRegOp): code = 'RIP = psrc1 + sop2 + CSBase' else_code="RIP = RIP;" diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 5ea803bfc..135fc10df 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -127,6 +127,7 @@ def operands {{ 'Quotient': impIntReg(2, 9), 'Remainder': impIntReg(3, 10), 'Divisor': impIntReg(4, 11), + 'DoubleBits': impIntReg(5, 11), 'Rax': intReg('(INTREG_RAX)', 12), 'Rbx': intReg('(INTREG_RBX)', 13), 'Rcx': intReg('(INTREG_RCX)', 14), diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh index 8b50bdf9b..a73aaef19 100644 --- a/src/arch/x86/x86_traits.hh +++ b/src/arch/x86/x86_traits.hh @@ -68,12 +68,13 @@ namespace X86ISA const int NumPseudoIntRegs = 1; //1. The condition code bits of the rflags register. - const int NumImplicitIntRegs = 5; + const int NumImplicitIntRegs = 6; //1. The lower part of the result of multiplication. //2. The upper part of the result of multiplication. //3. The quotient from division //4. The remainder from division //5. The divisor for division + //6. The register to use for shift doubles const int NumMMXRegs = 8; const int NumXMMRegs = 16; diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout index 86ee4acee..4a4332de9 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 19:00:07 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 19:00:32 -M5 executing on zizzer +M5 compiled Aug 8 2009 12:09:45 +M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch +M5 started Aug 8 2009 12:09:46 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -44,4 +44,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 962928684000 because target called exit() +Exiting @ tick 962929075000 because target called exit() diff --git a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt index f2c9a60d4..f1a9425ca 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2698152 # Simulator instruction rate (inst/s) -host_mem_usage 198060 # Number of bytes of host memory used -host_seconds 600.18 # Real time elapsed on the host -host_tick_rate 1604410387 # Simulator tick rate (ticks/s) +host_inst_rate 1432576 # Simulator instruction rate (inst/s) +host_mem_usage 198272 # Number of bytes of host memory used +host_seconds 1130.39 # Real time elapsed on the host +host_tick_rate 851856908 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1619365954 # Number of instructions simulated +sim_insts 1619366736 # Number of instructions simulated sim_seconds 0.962929 # Number of seconds simulated -sim_ticks 962928684000 # Number of ticks simulated +sim_ticks 962929075000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1925857369 # number of cpu cycles simulated -system.cpu.num_insts 1619365954 # Number of instructions executed +system.cpu.numCycles 1925858151 # number of cpu cycles simulated +system.cpu.num_insts 1619366736 # Number of instructions executed system.cpu.num_refs 607228174 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout index 450751534..7e3ef4fb7 100755 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/simout +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:55 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:33:03 -M5 executing on maize +M5 compiled Aug 8 2009 12:09:45 +M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch +M5 started Aug 8 2009 12:09:46 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt index 7585c05e4..574e2f381 100644 --- a/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1739159 # Simulator instruction rate (inst/s) -host_mem_usage 207648 # Number of bytes of host memory used -host_seconds 931.12 # Real time elapsed on the host -host_tick_rate 1949153444 # Simulator tick rate (ticks/s) +host_inst_rate 989143 # Simulator instruction rate (inst/s) +host_mem_usage 205900 # Number of bytes of host memory used +host_seconds 1637.14 # Real time elapsed on the host +host_tick_rate 1108576660 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1619365954 # Number of instructions simulated +sim_insts 1619366736 # Number of instructions simulated sim_seconds 1.814897 # Number of seconds simulated sim_ticks 1814896735000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 419042118 # number of ReadReq accesses(hits+misses) @@ -200,7 +200,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 61724 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 3629793470 # number of cpu cycles simulated -system.cpu.num_insts 1619365954 # Number of instructions executed +system.cpu.num_insts 1619366736 # Number of instructions executed system.cpu.num_refs 607228174 # Number of memory references system.cpu.workload.PROG:num_syscalls 48 # Number of system calls diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout index 4d45a89fb..269df7389 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 19:00:07 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 19:23:20 -M5 executing on zizzer +M5 compiled Aug 8 2009 12:09:45 +M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch +M5 started Aug 8 2009 12:09:46 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,4 +28,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 164697199000 because target called exit() +Exiting @ tick 164701785000 because target called exit() diff --git a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 2349e3c11..9a0d3d024 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1596079 # Simulator instruction rate (inst/s) -host_mem_usage 332596 # Number of bytes of host memory used -host_seconds 168.97 # Real time elapsed on the host -host_tick_rate 974720885 # Simulator tick rate (ticks/s) +host_inst_rate 1102214 # Simulator instruction rate (inst/s) +host_mem_usage 332796 # Number of bytes of host memory used +host_seconds 244.69 # Real time elapsed on the host +host_tick_rate 673115258 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269686785 # Number of instructions simulated -sim_seconds 0.164697 # Number of seconds simulated -sim_ticks 164697199000 # Number of ticks simulated +sim_insts 269695957 # Number of instructions simulated +sim_seconds 0.164702 # Number of seconds simulated +sim_ticks 164701785000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 329394399 # number of cpu cycles simulated -system.cpu.num_insts 269686785 # Number of instructions executed +system.cpu.numCycles 329403571 # number of cpu cycles simulated +system.cpu.num_insts 269695957 # Number of instructions executed system.cpu.num_refs 122219131 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout index d2184b8d7..e353b0889 100755 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:55 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:35:54 -M5 executing on maize +M5 compiled Aug 8 2009 12:09:45 +M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch +M5 started Aug 8 2009 12:13:51 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt index fe50ece29..094d83d97 100644 --- a/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1578716 # Simulator instruction rate (inst/s) -host_mem_usage 342176 # Number of bytes of host memory used -host_seconds 170.83 # Real time elapsed on the host -host_tick_rate 2233960314 # Simulator tick rate (ticks/s) +host_inst_rate 617251 # Simulator instruction rate (inst/s) +host_mem_usage 340428 # Number of bytes of host memory used +host_seconds 436.93 # Real time elapsed on the host +host_tick_rate 873410949 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 269686785 # Number of instructions simulated +sim_insts 269695957 # Number of instructions simulated sim_seconds 0.381621 # Number of seconds simulated sim_ticks 381620562000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 90779443 # number of ReadReq accesses(hits+misses) @@ -200,7 +200,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 70892 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 763241124 # number of cpu cycles simulated -system.cpu.num_insts 269686785 # Number of instructions executed +system.cpu.num_insts 269695957 # Number of instructions executed system.cpu.num_refs 122219131 # Number of memory references system.cpu.workload.PROG:num_syscalls 444 # Number of system calls diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout index b9e7f6545..d34525ab8 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 19:00:07 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 19:26:09 -M5 executing on zizzer +M5 compiled Aug 8 2009 12:09:45 +M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch +M5 started Aug 8 2009 12:09:45 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -74,4 +74,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 868476160000 because target called exit() +Exiting @ tick 868585211000 because target called exit() diff --git a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt index cffeaf89a..54f4e25be 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2677527 # Simulator instruction rate (inst/s) -host_mem_usage 201788 # Number of bytes of host memory used -host_seconds 558.53 # Real time elapsed on the host -host_tick_rate 1554928126 # Simulator tick rate (ticks/s) +host_inst_rate 1252342 # Simulator instruction rate (inst/s) +host_mem_usage 201956 # Number of bytes of host memory used +host_seconds 1194.32 # Real time elapsed on the host +host_tick_rate 727261872 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1495482368 # Number of instructions simulated -sim_seconds 0.868476 # Number of seconds simulated -sim_ticks 868476160000 # Number of ticks simulated +sim_insts 1495700470 # Number of instructions simulated +sim_seconds 0.868585 # Number of seconds simulated +sim_ticks 868585211000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1736952321 # number of cpu cycles simulated -system.cpu.num_insts 1495482368 # Number of instructions executed +system.cpu.numCycles 1737170423 # number of cpu cycles simulated +system.cpu.num_insts 1495700470 # Number of instructions executed system.cpu.num_refs 533262337 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/20.parser/ref/x86/linux/simple-timing/simout index fb61c1f63..a5dbe2b41 100755 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:55 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:37:54 -M5 executing on maize +M5 compiled Aug 8 2009 12:09:45 +M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch +M5 started Aug 8 2009 12:09:46 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt index 190dc2ac9..c62dd0754 100644 --- a/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1774247 # Simulator instruction rate (inst/s) -host_mem_usage 211336 # Number of bytes of host memory used -host_seconds 842.88 # Real time elapsed on the host -host_tick_rate 2043406156 # Simulator tick rate (ticks/s) +host_inst_rate 924480 # Simulator instruction rate (inst/s) +host_mem_usage 209588 # Number of bytes of host memory used +host_seconds 1617.88 # Real time elapsed on the host +host_tick_rate 1064572030 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1495482368 # Number of instructions simulated +sim_insts 1495700470 # Number of instructions simulated sim_seconds 1.722353 # Number of seconds simulated sim_ticks 1722352562000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 384102182 # number of ReadReq accesses(hits+misses) @@ -200,7 +200,7 @@ system.cpu.l2cache.warmup_cycle 921771494000 # Cy system.cpu.l2cache.writebacks 481430 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 3444705124 # number of cpu cycles simulated -system.cpu.num_insts 1495482368 # Number of instructions executed +system.cpu.num_insts 1495700470 # Number of instructions executed system.cpu.num_refs 533262337 # Number of memory references system.cpu.workload.PROG:num_syscalls 551 # Number of system calls diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout index aacd62b2b..583e2baa8 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 19:00:07 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 19:35:29 -M5 executing on zizzer +M5 compiled Aug 8 2009 12:09:45 +M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch +M5 started Aug 8 2009 12:09:46 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -29,4 +29,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 2829164063500 because target called exit() +Exiting @ tick 2829239875500 because target called exit() diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 80e9ba912..8024dc3cd 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2097364 # Simulator instruction rate (inst/s) -host_mem_usage 197956 # Number of bytes of host memory used -host_seconds 2218.58 # Real time elapsed on the host -host_tick_rate 1275211959 # Simulator tick rate (ticks/s) +host_inst_rate 1851230 # Simulator instruction rate (inst/s) +host_mem_usage 198160 # Number of bytes of host memory used +host_seconds 2513.64 # Real time elapsed on the host +host_tick_rate 1125554314 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4653176270 # Number of instructions simulated -sim_seconds 2.829164 # Number of seconds simulated -sim_ticks 2829164063500 # Number of ticks simulated +sim_insts 4653327894 # Number of instructions simulated +sim_seconds 2.829240 # Number of seconds simulated +sim_ticks 2829239875500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5658328128 # number of cpu cycles simulated -system.cpu.num_insts 4653176270 # Number of instructions executed +system.cpu.numCycles 5658479752 # number of cpu cycles simulated +system.cpu.num_insts 4653327894 # Number of instructions executed system.cpu.num_refs 1677713078 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout index b190e5ac3..ea6185a03 100755 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:55 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:42:41 -M5 executing on maize +M5 compiled Aug 8 2009 12:09:45 +M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch +M5 started Aug 8 2009 12:13:11 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 103b5bcb4..129e4b866 100644 --- a/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1577505 # Simulator instruction rate (inst/s) -host_mem_usage 207544 # Number of bytes of host memory used -host_seconds 2949.71 # Real time elapsed on the host -host_tick_rate 2030054219 # Simulator tick rate (ticks/s) +host_inst_rate 1178978 # Simulator instruction rate (inst/s) +host_mem_usage 205796 # Number of bytes of host memory used +host_seconds 3946.92 # Real time elapsed on the host +host_tick_rate 1517149915 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4653176270 # Number of instructions simulated +sim_insts 4653327894 # Number of instructions simulated sim_seconds 5.988064 # Number of seconds simulated sim_ticks 5988064038000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1239184742 # number of ReadReq accesses(hits+misses) @@ -200,7 +200,7 @@ system.cpu.l2cache.warmup_cycle 4737814312000 # C system.cpu.l2cache.writebacks 1199171 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 11976128076 # number of cpu cycles simulated -system.cpu.num_insts 4653176270 # Number of instructions executed +system.cpu.num_insts 4653327894 # Number of instructions executed system.cpu.num_refs 1677713078 # Number of memory references system.cpu.workload.PROG:num_syscalls 46 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout index cc9142f47..3079b1105 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 19:00:07 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 19:52:32 -M5 executing on zizzer +M5 compiled Aug 8 2009 12:09:45 +M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch +M5 started Aug 8 2009 12:09:46 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -27,4 +27,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 130009241500 because target called exit() +122 123 124 Exiting @ tick 130326747000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 0e46be9eb..5e4641113 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1749933 # Simulator instruction rate (inst/s) -host_mem_usage 205336 # Number of bytes of host memory used -host_seconds 124.92 # Real time elapsed on the host -host_tick_rate 1040768333 # Simulator tick rate (ticks/s) +host_inst_rate 1070420 # Simulator instruction rate (inst/s) +host_mem_usage 205608 # Number of bytes of host memory used +host_seconds 204.81 # Real time elapsed on the host +host_tick_rate 636336293 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 218595312 # Number of instructions simulated -sim_seconds 0.130009 # Number of seconds simulated -sim_ticks 130009241500 # Number of ticks simulated +sim_insts 219230323 # Number of instructions simulated +sim_seconds 0.130327 # Number of seconds simulated +sim_ticks 130326747000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 260018484 # number of cpu cycles simulated -system.cpu.num_insts 218595312 # Number of instructions executed +system.cpu.numCycles 260653495 # number of cpu cycles simulated +system.cpu.num_insts 219230323 # Number of instructions executed system.cpu.num_refs 77165298 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout index ddb53fb83..498becaaf 100755 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:55 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:46:04 -M5 executing on maize +M5 compiled Aug 8 2009 12:09:45 +M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch +M5 started Aug 8 2009 12:09:46 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt index f9e29c4be..35b37aaa2 100644 --- a/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1679742 # Simulator instruction rate (inst/s) -host_mem_usage 214928 # Number of bytes of host memory used -host_seconds 130.14 # Real time elapsed on the host -host_tick_rate 1928325538 # Simulator tick rate (ticks/s) +host_inst_rate 632486 # Simulator instruction rate (inst/s) +host_mem_usage 213180 # Number of bytes of host memory used +host_seconds 346.62 # Real time elapsed on the host +host_tick_rate 723985351 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 218595312 # Number of instructions simulated +sim_insts 219230323 # Number of instructions simulated sim_seconds 0.250946 # Number of seconds simulated sim_ticks 250945548000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses) @@ -200,7 +200,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 501891096 # number of cpu cycles simulated -system.cpu.num_insts 218595312 # Number of instructions executed +system.cpu.num_insts 219230323 # Number of instructions executed system.cpu.num_refs 77165298 # Number of memory references system.cpu.workload.PROG:num_syscalls 400 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/config.ini index 033b2dffb..cd22dbeae 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/config.ini @@ -81,7 +81,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=RubyMemory clock=1 -config_file=build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby/ruby.config +config_file=build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic-ruby/ruby.config debug=false debug_file=ruby.debug file= diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/ruby.stats index 2ec29786e..aef340be6 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/ruby.stats @@ -2,7 +2,7 @@ ================ Begin RubySystem Configuration Print ================ RubySystem config: - random_seed: 30545 + random_seed: 1234 randomization: 0 tech_nm: 45 freq_mhz: 3000 @@ -14,18 +14,20 @@ DMA_Controller config: DMAController_0 version: 0 buffer_size: 32 dma_sequencer: DMASequencer_0 - number_of_TBEs: 128 + number_of_TBEs: 256 + recycle_latency: 10 + request_latency: 6 transitions_per_cycle: 32 Directory_Controller config: DirectoryController_0 version: 0 buffer_size: 32 directory_latency: 6 directory_name: DirectoryMemory_0 + dma_select_low_bit: 6 + dma_select_num_bits: 0 memory_controller_name: MemoryControl_0 - memory_latency: 158 - number_of_TBEs: 128 + number_of_TBEs: 256 recycle_latency: 10 - to_mem_ctrl_latency: 1 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_0 version: 0 @@ -33,7 +35,8 @@ L1Cache_Controller config: L1CacheController_0 cache: l1u_0 cache_response_latency: 12 issue_latency: 2 - number_of_TBEs: 128 + number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_0 transitions_per_cycle: 32 Cache config: l1u_0 @@ -103,80 +106,40 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jul/06/2009 11:11:42 +Real time: Aug/09/2009 03:58:51 Profiler Stats -------------- -Elapsed_time_in_seconds: 0 -Elapsed_time_in_minutes: 0 -Elapsed_time_in_hours: 0 -Elapsed_time_in_days: 0 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.28 -Virtual_time_in_minutes: 0.00466667 -Virtual_time_in_hours: 7.77778e-05 -Virtual_time_in_days: 7.77778e-05 +Virtual_time_in_seconds: 0.34 +Virtual_time_in_minutes: 0.00566667 +Virtual_time_in_hours: 9.44444e-05 +Virtual_time_in_days: 3.93519e-06 -Ruby_current_time: 5491501 +Ruby_current_time: 5504001 Ruby_start_time: 1 -Ruby_cycles: 5491500 +Ruby_cycles: 5504000 -mbytes_resident: 144.855 -mbytes_total: 1330.54 -resident_ratio: 0.108873 +mbytes_resident: 144.359 +mbytes_total: 1352.23 +resident_ratio: 0.106763 Total_misses: 0 total_misses: 0 [ 0 ] user_misses: 0 [ 0 ] supervisor_misses: 0 [ 0 ] -instruction_executed: 1 [ 1 ] -ruby_cycles_executed: 5491501 [ 5491501 ] -cycles_per_instruction: 5.4915e+06 [ 5.4915e+06 ] -misses_per_thousand_instructions: 0 [ 0 ] +ruby_cycles_executed: 5504001 [ 5504001 ] transactions_started: 0 [ 0 ] transactions_ended: 0 [ 0 ] -instructions_per_transaction: 0 [ 0 ] cycles_per_transaction: 0 [ 0 ] misses_per_transaction: 0 [ 0 ] -L1D_cache cache stats: - L1D_cache_total_misses: 0 - L1D_cache_total_demand_misses: 0 - L1D_cache_total_prefetches: 0 - L1D_cache_total_sw_prefetches: 0 - L1D_cache_total_hw_prefetches: 0 - L1D_cache_misses_per_transaction: 0 - L1D_cache_misses_per_instruction: 0 - L1D_cache_instructions_per_misses: NaN - - L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L1I_cache cache stats: - L1I_cache_total_misses: 0 - L1I_cache_total_demand_misses: 0 - L1I_cache_total_prefetches: 0 - L1I_cache_total_sw_prefetches: 0 - L1I_cache_total_hw_prefetches: 0 - L1I_cache_misses_per_transaction: 0 - L1I_cache_misses_per_instruction: 0 - L1I_cache_instructions_per_misses: NaN - - L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L2_cache cache stats: - L2_cache_total_misses: 0 - L2_cache_total_demand_misses: 0 - L2_cache_total_prefetches: 0 - L2_cache_total_sw_prefetches: 0 - L2_cache_total_hw_prefetches: 0 - L2_cache_misses_per_transaction: 0 - L2_cache_misses_per_instruction: 0 - L2_cache_instructions_per_misses: NaN - - L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - Busy Controller Counts: L1Cache-0:0 @@ -185,27 +148,16 @@ DMA-0:0 Busy Bank Count:0 -L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - Request vs. RubySystem State Profile -------------------------------- @@ -228,11 +180,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 37781 -page_faults: 0 +page_reclaims: 38267 +page_faults: 1 swaps: 0 block_inputs: 0 -block_outputs: 40 +block_outputs: 0 Network Stats ------------- @@ -266,7 +218,17 @@ links_utilized_percent_switch_3: 0 links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1 - --- DMA --- +l1u_0 cache stats: + l1u_0_total_misses: 0 + l1u_0_total_demand_misses: 0 + l1u_0_total_prefetches: 0 + l1u_0_total_sw_prefetches: 0 + l1u_0_total_hw_prefetches: 0 + l1u_0_misses_per_transaction: nan + + l1u_0_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + + --- DMA 0 --- - Event Counts - ReadRequest 0 WriteRequest 0 @@ -281,7 +243,7 @@ BUSY_RD Data 0 <-- BUSY_WR Ack 0 <-- - --- Directory --- + --- Directory 0 --- - Event Counts - GETX 0 GETS 0 @@ -344,7 +306,7 @@ ID_W DMA_READ 0 <-- ID_W DMA_WRITE 0 <-- ID_W Memory_Ack 0 <-- - --- L1Cache --- + --- L1Cache 0 --- - Event Counts - Load 0 Ifetch 0 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simerr b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simerr index 5af43697b..dba65c3fc 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simerr +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simerr @@ -1,23 +1,7 @@ ["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"] +Error: User specified set of debug components, but the RUBY_DEBUG compile-time flag is false. +Solution: Re-compile with RUBY_DEBUG set to true. print config: 1 -Creating new MessageBuffer for 0 0 -Creating new MessageBuffer for 0 1 -Creating new MessageBuffer for 0 2 -Creating new MessageBuffer for 0 3 -Creating new MessageBuffer for 0 4 -Creating new MessageBuffer for 0 5 -Creating new MessageBuffer for 1 0 -Creating new MessageBuffer for 1 1 -Creating new MessageBuffer for 1 2 -Creating new MessageBuffer for 1 3 -Creating new MessageBuffer for 1 4 -Creating new MessageBuffer for 1 5 -Creating new MessageBuffer for 2 0 -Creating new MessageBuffer for 2 1 -Creating new MessageBuffer for 2 2 -Creating new MessageBuffer for 2 3 -Creating new MessageBuffer for 2 4 -Creating new MessageBuffer for 2 5 warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simout index 90ac86d82..85200a1c8 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/simout @@ -5,13 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:09:41 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:41 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic-ruby +M5 compiled Aug 9 2009 03:58:47 +M5 revision 33faa9915d16 6486 default tip +M5 started Aug 9 2009 03:58:49 +M5 executing on tater +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic-ruby Global frequency set at 1000000000000 ticks per second - Debug: Adding to filter: 'q' (Queue) info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 5491500 because target called exit() +Exiting @ tick 5504000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/stats.txt index 6fed8184d..e8b0be97b 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic-ruby/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 70231 # Simulator instruction rate (inst/s) -host_mem_usage 1362472 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host -host_tick_rate 40570791 # Simulator tick rate (ticks/s) +host_inst_rate 7886 # Simulator instruction rate (inst/s) +host_mem_usage 1384684 # Number of bytes of host memory used +host_seconds 1.21 # Real time elapsed on the host +host_tick_rate 4559114 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 9494 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5491500 # Number of ticks simulated +sim_insts 9519 # Number of instructions simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 5504000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 10984 # number of cpu cycles simulated -system.cpu.num_insts 9494 # Number of instructions executed +system.cpu.numCycles 11009 # number of cpu cycles simulated +system.cpu.num_insts 9519 # Number of instructions executed system.cpu.num_refs 1987 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index dbaa3b09e..0030aae6b 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 21 2009 19:00:07 -M5 revision e6dd09514462 6117 default qtip tip stats-update -M5 started Apr 21 2009 19:57:53 -M5 executing on zizzer +M5 compiled Aug 8 2009 12:09:45 +M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch +M5 started Aug 8 2009 12:09:46 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 5491500 because target called exit() +Exiting @ tick 5504000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index f96fa3e66..a72432b3a 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 544881 # Simulator instruction rate (inst/s) -host_mem_usage 193800 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 311186037 # Simulator tick rate (ticks/s) +host_inst_rate 23019 # Simulator instruction rate (inst/s) +host_mem_usage 193704 # Number of bytes of host memory used +host_seconds 0.41 # Real time elapsed on the host +host_tick_rate 13302912 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 9494 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5491500 # Number of ticks simulated +sim_insts 9519 # Number of instructions simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 5504000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 10984 # number of cpu cycles simulated -system.cpu.num_insts 9494 # Number of instructions executed +system.cpu.numCycles 11009 # number of cpu cycles simulated +system.cpu.num_insts 9519 # Number of instructions executed system.cpu.num_refs 1987 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 70c54a02f..bb30a8458 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -78,7 +78,7 @@ port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=RubyMemory clock=1 -config_file=build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby/ruby.config +config_file=build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/ruby.config debug=false debug_file=ruby.debug file= diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index 68f2b9852..7d6d1b187 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -2,7 +2,7 @@ ================ Begin RubySystem Configuration Print ================ RubySystem config: - random_seed: 184716 + random_seed: 1234 randomization: 0 tech_nm: 45 freq_mhz: 3000 @@ -14,18 +14,20 @@ DMA_Controller config: DMAController_0 version: 0 buffer_size: 32 dma_sequencer: DMASequencer_0 - number_of_TBEs: 128 + number_of_TBEs: 256 + recycle_latency: 10 + request_latency: 6 transitions_per_cycle: 32 Directory_Controller config: DirectoryController_0 version: 0 buffer_size: 32 directory_latency: 6 directory_name: DirectoryMemory_0 + dma_select_low_bit: 6 + dma_select_num_bits: 0 memory_controller_name: MemoryControl_0 - memory_latency: 158 - number_of_TBEs: 128 + number_of_TBEs: 256 recycle_latency: 10 - to_mem_ctrl_latency: 1 transitions_per_cycle: 32 L1Cache_Controller config: L1CacheController_0 version: 0 @@ -33,7 +35,8 @@ L1Cache_Controller config: L1CacheController_0 cache: l1u_0 cache_response_latency: 12 issue_latency: 2 - number_of_TBEs: 128 + number_of_TBEs: 256 + recycle_latency: 10 sequencer: Sequencer_0 transitions_per_cycle: 32 Cache config: l1u_0 @@ -103,82 +106,42 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jul/06/2009 11:11:44 +Real time: Aug/09/2009 04:00:22 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 4 +Elapsed_time_in_minutes: 0.0666667 +Elapsed_time_in_hours: 0.00111111 +Elapsed_time_in_days: 4.62963e-05 -Virtual_time_in_seconds: 0.87 -Virtual_time_in_minutes: 0.0145 -Virtual_time_in_hours: 0.000241667 -Virtual_time_in_days: 0.000241667 +Virtual_time_in_seconds: 1.19 +Virtual_time_in_minutes: 0.0198333 +Virtual_time_in_hours: 0.000330556 +Virtual_time_in_days: 1.37731e-05 Ruby_current_time: 26617001 Ruby_start_time: 1 Ruby_cycles: 26617000 -mbytes_resident: 145.273 -mbytes_total: 1330.63 -resident_ratio: 0.109179 +mbytes_resident: 144.777 +mbytes_total: 1352.41 +resident_ratio: 0.107057 Total_misses: 0 total_misses: 0 [ 0 ] user_misses: 0 [ 0 ] supervisor_misses: 0 [ 0 ] -instruction_executed: 1 [ 1 ] ruby_cycles_executed: 26617001 [ 26617001 ] -cycles_per_instruction: 2.6617e+07 [ 2.6617e+07 ] -misses_per_thousand_instructions: 0 [ 0 ] transactions_started: 0 [ 0 ] transactions_ended: 0 [ 0 ] -instructions_per_transaction: 0 [ 0 ] cycles_per_transaction: 0 [ 0 ] misses_per_transaction: 0 [ 0 ] -L1D_cache cache stats: - L1D_cache_total_misses: 0 - L1D_cache_total_demand_misses: 0 - L1D_cache_total_prefetches: 0 - L1D_cache_total_sw_prefetches: 0 - L1D_cache_total_hw_prefetches: 0 - L1D_cache_misses_per_transaction: 0 - L1D_cache_misses_per_instruction: 0 - L1D_cache_instructions_per_misses: NaN - - L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L1I_cache cache stats: - L1I_cache_total_misses: 0 - L1I_cache_total_demand_misses: 0 - L1I_cache_total_prefetches: 0 - L1I_cache_total_sw_prefetches: 0 - L1I_cache_total_hw_prefetches: 0 - L1I_cache_misses_per_transaction: 0 - L1I_cache_misses_per_instruction: 0 - L1I_cache_instructions_per_misses: NaN - - L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -L2_cache cache stats: - L2_cache_total_misses: 0 - L2_cache_total_demand_misses: 0 - L2_cache_total_prefetches: 0 - L2_cache_total_sw_prefetches: 0 - L2_cache_total_hw_prefetches: 0 - L2_cache_misses_per_transaction: 0 - L2_cache_misses_per_instruction: 0 - L2_cache_instructions_per_misses: NaN - - L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - -Memory control: + +Memory control MemoryControl_0: memory_total_requests: 1082 memory_reads: 557 memory_writes: 525 @@ -205,30 +168,19 @@ DMA-0:0 Busy Bank Count:0 -L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -L2TBE_usage: [binsize: 1 max: 1 count: 1082 average: 0.485213 | standard deviation: 0.500693 | 557 525 ] -StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8873 average: 1 | standard deviation: 0 | 0 8873 ] -store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 279 count: 8873 average: 12.5938 | standard deviation: 41.1326 | 0 8316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 11 0 0 0 0 480 0 0 0 0 10 0 0 0 0 10 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 279 count: 6886 average: 9.86669 | standard deviation: 35.7801 | 0 6566 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 6 0 0 0 0 280 0 0 0 0 7 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 279 count: 1053 average: 24.4786 | standard deviation: 57.8541 | 0 913 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 4 0 0 0 0 118 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 259 count: 934 average: 19.3009 | standard deviation: 51.067 | 0 837 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 82 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency: [binsize: 2 max: 277 count: 8873 average: 11.531 | standard deviation: 40.8912 | 8316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 11 0 0 0 0 480 0 0 0 0 10 0 0 0 0 10 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_1: [binsize: 2 max: 277 count: 6886 average: 8.82021 | standard deviation: 35.5704 | 6566 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 6 0 0 0 0 280 0 0 0 0 7 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_2: [binsize: 2 max: 277 count: 1053 average: 23.3457 | standard deviation: 57.517 | 913 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 4 0 0 0 0 118 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_3: [binsize: 2 max: 257 count: 934 average: 18.197 | standard deviation: 50.763 | 837 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 82 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - Request vs. RubySystem State Profile -------------------------------- @@ -249,13 +201,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1082 average: 0 | standa Resource Usage -------------- page_size: 4096 -user_time: 0 +user_time: 1 system_time: 0 -page_reclaims: 37883 +page_reclaims: 38363 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 48 +block_outputs: 0 Network Stats ------------- @@ -301,7 +253,22 @@ links_utilized_percent_switch_3: 0.000135502 outgoing_messages_switch_3_link_1_Control: 557 4456 [ 557 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_1_Data: 525 4200 [ 525 0 0 0 0 0 ] base_latency: 1 - --- DMA --- +l1u_0 cache stats: + l1u_0_total_misses: 557 + l1u_0_total_demand_misses: 557 + l1u_0_total_prefetches: 0 + l1u_0_total_sw_prefetches: 0 + l1u_0_total_hw_prefetches: 0 + l1u_0_misses_per_transaction: inf + + l1u_0_request_type_LD: 25.1346% + l1u_0_request_type_ST: 17.4147% + l1u_0_request_type_IFETCH: 57.4506% + + l1u_0_access_mode_type_SupervisorMode: 557 100% + l1u_0_request_size: [binsize: log2 max: 8 count: 557 average: 7.5368 | standard deviation: 1.45496 | 0 12 1 42 502 ] + + --- DMA 0 --- - Event Counts - ReadRequest 0 WriteRequest 0 @@ -316,7 +283,7 @@ BUSY_RD Data 0 <-- BUSY_WR Ack 0 <-- - --- Directory --- + --- Directory 0 --- - Event Counts - GETX 557 GETS 0 @@ -379,7 +346,7 @@ ID_W DMA_READ 0 <-- ID_W DMA_WRITE 0 <-- ID_W Memory_Ack 0 <-- - --- L1Cache --- + --- L1Cache 0 --- - Event Counts - Load 1053 Ifetch 6886 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr index 5af43697b..dba65c3fc 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr @@ -1,23 +1,7 @@ ["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"] +Error: User specified set of debug components, but the RUBY_DEBUG compile-time flag is false. +Solution: Re-compile with RUBY_DEBUG set to true. print config: 1 -Creating new MessageBuffer for 0 0 -Creating new MessageBuffer for 0 1 -Creating new MessageBuffer for 0 2 -Creating new MessageBuffer for 0 3 -Creating new MessageBuffer for 0 4 -Creating new MessageBuffer for 0 5 -Creating new MessageBuffer for 1 0 -Creating new MessageBuffer for 1 1 -Creating new MessageBuffer for 1 2 -Creating new MessageBuffer for 1 3 -Creating new MessageBuffer for 1 4 -Creating new MessageBuffer for 1 5 -Creating new MessageBuffer for 2 0 -Creating new MessageBuffer for 2 1 -Creating new MessageBuffer for 2 2 -Creating new MessageBuffer for 2 3 -Creating new MessageBuffer for 2 4 -Creating new MessageBuffer for 2 5 warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 warn: instruction 'fnstcw_Mw' unimplemented diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout index f24cd70eb..e450b1234 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -5,13 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 6 2009 11:09:41 -M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip -M5 started Jul 6 2009 11:11:43 -M5 executing on maize -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby +M5 compiled Aug 9 2009 04:00:16 +M5 revision 33faa9915d16+ 6486+ default tip +M5 started Aug 9 2009 04:00:18 +M5 executing on tater +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000000 ticks per second - Debug: Adding to filter: 'q' (Queue) info: Entering event queue @ 0. Starting simulation... Hello world! Exiting @ tick 26617000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 65a218a7c..f970da101 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,17 +1,17 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 12919 # Simulator instruction rate (inst/s) -host_mem_usage 1362572 # Number of bytes of host memory used -host_seconds 0.74 # Real time elapsed on the host -host_tick_rate 36211191 # Simulator tick rate (ticks/s) +host_inst_rate 2962 # Simulator instruction rate (inst/s) +host_mem_usage 1384872 # Number of bytes of host memory used +host_seconds 3.21 # Real time elapsed on the host +host_tick_rate 8282962 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 9494 # Number of instructions simulated +sim_insts 9519 # Number of instructions simulated sim_seconds 0.000027 # Number of seconds simulated sim_ticks 26617000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 53234 # number of cpu cycles simulated -system.cpu.num_insts 9494 # Number of instructions executed +system.cpu.num_insts 9519 # Number of instructions executed system.cpu.num_refs 1987 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index 869d0cef1..299195d5b 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 22 2009 06:58:55 -M5 revision ce26a627c841 6126 default qtip tip stats_no_compat.diff -M5 started Apr 22 2009 07:48:15 -M5 executing on maize +M5 compiled Aug 8 2009 12:09:45 +M5 revision f8cd1918b0c6 6483 default qtip tip condmovezerostats.patch +M5 started Aug 8 2009 12:09:46 +M5 executing on tater command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index b46b73886..e83d6fcbe 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,11 +1,11 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 183914 # Simulator instruction rate (inst/s) -host_mem_usage 203340 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 573138759 # Simulator tick rate (ticks/s) +host_inst_rate 21415 # Simulator instruction rate (inst/s) +host_mem_usage 201336 # Number of bytes of host memory used +host_seconds 0.44 # Real time elapsed on the host +host_tick_rate 66853602 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 9494 # Number of instructions simulated +sim_insts 9519 # Number of instructions simulated sim_seconds 0.000030 # Number of seconds simulated sim_ticks 29731000 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 1053 # number of ReadReq accesses(hits+misses) @@ -198,7 +198,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 59462 # number of cpu cycles simulated -system.cpu.num_insts 9494 # Number of instructions executed +system.cpu.num_insts 9519 # Number of instructions executed system.cpu.num_refs 1987 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls |