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-rw-r--r--src/arch/arm/utility.cc17
-rw-r--r--src/cpu/BaseCPU.py1
-rw-r--r--src/cpu/base.cc5
-rw-r--r--src/cpu/base.hh10
-rw-r--r--src/cpu/base_dyn_inst.hh3
-rw-r--r--src/cpu/checker/thread_context.hh2
-rw-r--r--src/cpu/inorder/thread_context.hh3
-rwxr-xr-xsrc/cpu/o3/thread_context.hh3
-rw-r--r--src/cpu/thread_context.hh4
-rw-r--r--src/cpu/thread_state.hh2
10 files changed, 46 insertions, 4 deletions
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index d5b062621..ae84391e9 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -195,13 +195,26 @@ longDescFormatInUse(ThreadContext *tc)
uint32_t
getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
{
+ // Multiprocessor Affinity Register MPIDR from Cortex(tm)-A15 Technical
+ // Reference Manual
+ //
+ // bit 31 - Multi-processor extensions available
+ // bit 30 - Uni-processor system
+ // bit 24 - Multi-threaded cores
+ // bit 11-8 - Cluster ID
+ // bit 1-0 - CPU ID
+ //
+ // We deliberately extend both the Cluster ID and CPU ID fields to allow
+ // for simulation of larger systems
+ assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
+ assert((0 <= tc->socketId()) && (tc->socketId() < 65536));
if (arm_sys->multiProc) {
return 0x80000000 | // multiprocessor extensions available
- tc->cpuId();
+ tc->cpuId() | tc->socketId() << 8;
} else {
return 0x80000000 | // multiprocessor extensions available
0x40000000 | // in up system
- tc->cpuId();
+ tc->cpuId() | tc->socketId() << 8;
}
}
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 652af0b80..b7f0b2089 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -128,6 +128,7 @@ class BaseCPU(MemObject):
system = Param.System(Parent.any, "system object")
cpu_id = Param.Int(-1, "CPU identifier")
+ socket_id = Param.Unsigned(0, "Physical Socket identifier")
numThreads = Param.Unsigned(1, "number of HW thread contexts")
function_trace = Param.Bool(False, "Enable function trace")
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 3078472fd..905785631 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -117,7 +117,7 @@ CPUProgressEvent::description() const
}
BaseCPU::BaseCPU(Params *p, bool is_checker)
- : MemObject(p), instCnt(0), _cpuId(p->cpu_id),
+ : MemObject(p), instCnt(0), _cpuId(p->cpu_id), _socketId(p->socket_id),
_instMasterId(p->system->getMasterId(name() + ".inst")),
_dataMasterId(p->system->getMasterId(name() + ".data")),
_taskId(ContextSwitchTaskId::Unknown), _pid(Request::invldPid),
@@ -133,7 +133,8 @@ BaseCPU::BaseCPU(Params *p, bool is_checker)
// add self to global list of CPUs
cpuList.push_back(this);
- DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId);
+ DPRINTF(SyscallVerbose, "Constructing CPU with id %d, socket id %d\n",
+ _cpuId, _socketId);
if (numThreads > maxThreadsPerCPU)
maxThreadsPerCPU = numThreads;
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 321b785a2..cc3f861cc 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -101,6 +101,13 @@ class BaseCPU : public MemObject
// therefore no setCpuId() method is provided
int _cpuId;
+ /** Each cpu will have a socket ID that corresponds to its physical location
+ * in the system. This is usually used to bucket cpu cores under single DVFS
+ * domain. This information may also be required by the OS to identify the
+ * cpu core grouping (as in the case of ARM via MPIDR register)
+ */
+ const uint32_t _socketId;
+
/** instruction side request id that must be placed in all requests */
MasterID _instMasterId;
@@ -145,6 +152,9 @@ class BaseCPU : public MemObject
/** Reads this CPU's ID. */
int cpuId() const { return _cpuId; }
+ /** Reads this CPU's Socket ID. */
+ uint32_t socketId() const { return _socketId; }
+
/** Reads this CPU's unique data requestor ID */
MasterID dataMasterId() { return _dataMasterId; }
/** Reads this CPU's unique instruction requestor ID */
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index cafe51fd7..08e16d330 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -456,6 +456,9 @@ class BaseDynInst : public RefCounted
/** Read this CPU's ID. */
int cpuId() const { return cpu->cpuId(); }
+ /** Read this CPU's Socket ID. */
+ uint32_t socketId() const { return cpu->socketId(); }
+
/** Read this CPU's data requestor ID */
MasterID masterId() const { return cpu->dataMasterId(); }
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index ddd07ea58..f868f4cbb 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -92,6 +92,8 @@ class CheckerThreadContext : public ThreadContext
BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
+ uint32_t socketId() const { return actualTC->socketId(); }
+
int cpuId() const { return actualTC->cpuId(); }
int contextId() const { return actualTC->contextId(); }
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 96ec063c8..2e525eb2a 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -113,6 +113,9 @@ class InOrderThreadContext : public ThreadContext
/** Reads this CPU's ID. */
int cpuId() const { return cpu->cpuId(); }
+ /** Reads this CPU's Socket ID. */
+ uint32_t socketId() const { return cpu->socketId(); }
+
int contextId() const { return thread->contextId(); }
void setContextId(int id) { thread->setContextId(id); }
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index ef72fdb03..a00d2ffa3 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -98,6 +98,9 @@ class O3ThreadContext : public ThreadContext
/** Reads this CPU's ID. */
virtual int cpuId() const { return cpu->cpuId(); }
+ /** Reads this CPU's Socket ID. */
+ virtual uint32_t socketId() const { return cpu->socketId(); }
+
virtual int contextId() const { return thread->contextId(); }
virtual void setContextId(int id) { thread->setContextId(id); }
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 4b88b4a0b..40150ac05 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -123,6 +123,8 @@ class ThreadContext
virtual int cpuId() const = 0;
+ virtual uint32_t socketId() const = 0;
+
virtual int threadId() const = 0;
virtual void setThreadId(int id) = 0;
@@ -323,6 +325,8 @@ class ProxyThreadContext : public ThreadContext
int cpuId() const { return actualTC->cpuId(); }
+ uint32_t socketId() const { return actualTC->socketId(); }
+
int threadId() const { return actualTC->threadId(); }
void setThreadId(int id) { actualTC->setThreadId(id); }
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 775f6fbd4..f937964ff 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -69,6 +69,8 @@ struct ThreadState {
int cpuId() const { return baseCpu->cpuId(); }
+ uint32_t socketId() const { return baseCpu->socketId(); }
+
int contextId() const { return _contextId; }
void setContextId(int id) { _contextId = id; }
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-14 03:57:37 +0000