diff options
86 files changed, 3422 insertions, 4397 deletions
diff --git a/configs/example/fs.py b/configs/example/fs.py index 71c5961ef..5edda6e5f 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -49,10 +49,12 @@ parser.add_option("--dual", action="store_true", parser.add_option("-b", "--benchmark", action="store", type="string", dest="benchmark", help="Specify the benchmark to run. Available benchmarks: %s"\ - % DefinedBenchmarks) + % DefinedBenchmarks) parser.add_option("--etherdump", action="store", type="string", dest="etherdump", - help="Specify the filename to dump a pcap capture of the ethernet" - "traffic") + help="Specify the filename to dump a pcap capture of the" \ + "ethernet traffic") +parser.add_option("--checkpoint_dir", action="store", type="string", + help="Place all checkpoints in this absolute directory") (options, args) = parser.parse_args() @@ -123,7 +125,14 @@ else: exit_event = m5.simulate(maxtick) while exit_event.getCause() == "checkpoint": - m5.checkpoint(root, "cpt.%d") - exit_event = m5.simulate(maxtick - m5.curTick()) + if options.checkpoint_dir: + m5.checkpoint(root, "/".join([options.checkpoint_dir, "cpt.%d"])) + else: + m5.checkpoint(root, "cpt.%d") + + if maxtick == -1: + exit_event = m5.simulate(maxtick) + else: + exit_event = m5.simulate(maxtick - m5.curTick()) print 'Exiting @ cycle', m5.curTick(), 'because', exit_event.getCause() diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 4fc9da3f3..5bd19b677 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -701,7 +701,7 @@ decode OPCODE default Unknown::unknown() { 0x00: decode PALFUNC { format EmulatedCallPal { 0x00: halt ({{ - exitSimLoop(curTick, "halt instruction encountered"); + exitSimLoop("halt instruction encountered"); }}, IsNonSpeculative); 0x83: callsys({{ xc->syscall(R0); diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc index 63cbbe057..ef6443d17 100644 --- a/src/arch/sparc/system.cc +++ b/src/arch/sparc/system.cc @@ -152,10 +152,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem) Param<std::string> readfile; Param<unsigned int> init_param; - Param<bool> bin; - VectorParam<std::string> binned_fns; - Param<bool> bin_int; - END_DECLARE_SIM_OBJECT_PARAMS(SparcSystem) BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem) @@ -173,10 +169,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem) INIT_PARAM_DFLT(readfile, "file to read startup script from", ""), INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0), INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34), - INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10), - INIT_PARAM_DFLT(bin, "is this system to be binned", false), - INIT_PARAM(binned_fns, "functions to be broken down and binned"), - INIT_PARAM_DFLT(bin_int, "is interrupt code binned seperately?", true) + INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10) END_INIT_SIM_OBJECT_PARAMS(SparcSystem) @@ -196,9 +189,6 @@ CREATE_SIM_OBJECT(SparcSystem) p->readfile = readfile; p->system_type = system_type; p->system_rev = system_rev; - p->bin = bin; - p->binned_fns = binned_fns; - p->bin_int = bin_int; return new SparcSystem(p); } diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 513dd7c55..ea4b03bf2 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -41,6 +41,7 @@ #include "cpu/cpuevent.hh" #include "cpu/thread_context.hh" #include "cpu/profile.hh" +#include "sim/sim_exit.hh" #include "sim/param.hh" #include "sim/process.hh" #include "sim/sim_events.hh" @@ -125,8 +126,9 @@ BaseCPU::BaseCPU(Params *p) // if (p->max_insts_any_thread != 0) for (int i = 0; i < number_of_threads; ++i) - new SimLoopExitEvent(comInstEventQueue[i], p->max_insts_any_thread, - "a thread reached the max instruction count"); + schedExitSimLoop("a thread reached the max instruction count", + p->max_insts_any_thread, 0, + comInstEventQueue[i]); if (p->max_insts_all_threads != 0) { // allocate & initialize shared downcounter: each event will @@ -150,8 +152,9 @@ BaseCPU::BaseCPU(Params *p) // if (p->max_loads_any_thread != 0) for (int i = 0; i < number_of_threads; ++i) - new SimLoopExitEvent(comLoadEventQueue[i], p->max_loads_any_thread, - "a thread reached the max load count"); + schedExitSimLoop("a thread reached the max load count", + p->max_loads_any_thread, 0, + comLoadEventQueue[i]); if (p->max_loads_all_threads != 0) { // allocate & initialize shared downcounter: each event will diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index c396f5033..88698bfee 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -161,9 +161,9 @@ AtomicSimpleCPU::serialize(ostream &os) { SimObject::State so_state = SimObject::getState(); SERIALIZE_ENUM(so_state); + BaseSimpleCPU::serialize(os); nameOut(os, csprintf("%s.tickEvent", name())); tickEvent.serialize(os); - BaseSimpleCPU::serialize(os); } void @@ -171,8 +171,8 @@ AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) { SimObject::State so_state; UNSERIALIZE_ENUM(so_state); - tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); BaseSimpleCPU::unserialize(cp, section); + tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); } void @@ -464,6 +464,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) Param<Counter> max_insts_all_threads; Param<Counter> max_loads_any_thread; Param<Counter> max_loads_all_threads; + Param<Tick> progress_interval; SimObjectParam<MemObject *> mem; SimObjectParam<System *> system; @@ -496,6 +497,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) "terminate when any thread reaches this load count"), INIT_PARAM(max_loads_all_threads, "terminate when all threads have reached this load count"), + INIT_PARAM(progress_interval, "Progress interval"), INIT_PARAM(mem, "memory"), INIT_PARAM(system, "system object"), @@ -527,6 +529,7 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU) params->max_insts_all_threads = max_insts_all_threads; params->max_loads_any_thread = max_loads_any_thread; params->max_loads_all_threads = max_loads_all_threads; + params->progress_interval = progress_interval; params->deferRegistration = defer_registration; params->clock = clock; params->functionTrace = function_trace; diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 5c1654f7e..03ee27e04 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -589,6 +589,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) Param<Counter> max_insts_all_threads; Param<Counter> max_loads_any_thread; Param<Counter> max_loads_all_threads; + Param<Tick> progress_interval; SimObjectParam<MemObject *> mem; SimObjectParam<System *> system; @@ -621,6 +622,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) "terminate when any thread reaches this load count"), INIT_PARAM(max_loads_all_threads, "terminate when all threads have reached this load count"), + INIT_PARAM(progress_interval, "Progress interval"), INIT_PARAM(mem, "memory"), INIT_PARAM(system, "system object"), @@ -652,6 +654,7 @@ CREATE_SIM_OBJECT(TimingSimpleCPU) params->max_insts_all_threads = max_insts_all_threads; params->max_loads_any_thread = max_loads_any_thread; params->max_loads_all_threads = max_loads_all_threads; + params->progress_interval = progress_interval; params->deferRegistration = defer_registration; params->clock = clock; params->functionTrace = function_trace; diff --git a/src/mem/bus.cc b/src/mem/bus.cc index cf9e54e62..3c5283a77 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -252,6 +252,7 @@ Bus::recvFunctional(Packet *pkt) DPRINTF(Bus, "recvFunctional: packet src %d dest %d addr 0x%x cmd %s\n", pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString()); assert(pkt->getDest() == Packet::Broadcast); + atomicSnoop(pkt); findPort(pkt->getAddr(), pkt->getSrc())->sendFunctional(pkt); } diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc index a172847df..d7ccca8c0 100644 --- a/src/mem/cache/base_cache.cc +++ b/src/mem/cache/base_cache.cc @@ -96,6 +96,15 @@ void BaseCache::CachePort::recvRetry() { Packet *pkt; + if (!drainList.empty()) { + //We have some responses to drain first + bool result = true; + while (result && !drainList.empty()) { + result = sendTiming(drainList.front()); + if (result) + drainList.pop_front(); + } + } if (!isCpuSide) { @@ -199,8 +208,17 @@ BaseCache::CacheEvent::process() return; } //Response - //Know the packet to send, no need to mark in service (must succed) - assert(cachePort->sendTiming(pkt)); + //Know the packet to send + pkt->result = Packet::Success; + pkt->makeTimingResponse(); + if (!cachePort->drainList.empty()) { + //Already blocked waiting for bus, just append + cachePort->drainList.push_back(pkt); + } + else if (!cachePort->sendTiming(pkt)) { + //It failed, save it to list of drain events + cachePort->drainList.push_back(pkt); + } } const char * diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh index 069dbab58..c69fb7fd5 100644 --- a/src/mem/cache/base_cache.hh +++ b/src/mem/cache/base_cache.hh @@ -110,6 +110,8 @@ class BaseCache : public MemObject bool mustSendRetry; bool isCpuSide; + + std::list<Packet *> drainList; }; struct CacheEvent : public Event @@ -127,6 +129,8 @@ class BaseCache : public MemObject CachePort *cpuSidePort; CachePort *memSidePort; + bool snoopRangesSent; + public: virtual Port *getPort(const std::string &if_name, int idx = -1); @@ -149,17 +153,22 @@ class BaseCache : public MemObject void recvStatusChange(Port::Status status, bool isCpuSide) { - if (status == Port::RangeChange) - { - if (!isCpuSide) - { + if (status == Port::RangeChange){ + if (!isCpuSide) { cpuSidePort->sendStatusChange(Port::RangeChange); + if (topLevelCache && !snoopRangesSent) { + snoopRangesSent = true; + memSidePort->sendStatusChange(Port::RangeChange); + } } - else - { + else { memSidePort->sendStatusChange(Port::RangeChange); } } + else if (status == Port::SnoopSquash) { + assert(snoopPhase2); + snoopPhase2 = false; + } } virtual Packet *getPacket() @@ -205,6 +214,10 @@ class BaseCache : public MemObject /** True if this cache is connected to the CPU. */ bool topLevelCache; + + /** True if we are now in phase 2 of the snoop process. */ + bool snoopPhase2; + /** Stores time the cache blocked for statistics. */ Tick blockedCycle; @@ -332,6 +345,7 @@ class BaseCache : public MemObject //Start ports at null if more than one is created we should panic cpuSidePort = NULL; memSidePort = NULL; + snoopRangesSent = false; } virtual void init(); @@ -382,9 +396,12 @@ class BaseCache : public MemObject blocked_causes[cause]++; blockedCycle = curTick; } - blocked |= flag; - DPRINTF(Cache,"Blocking for cause %s\n", cause); - cpuSidePort->setBlocked(); + if (!(blocked & flag)) { + //Wasn't already blocked for this cause + blocked |= flag; + DPRINTF(Cache,"Blocking for cause %s\n", cause); + cpuSidePort->setBlocked(); + } } /** @@ -395,8 +412,11 @@ class BaseCache : public MemObject void setBlockedForSnoop(BlockedCause cause) { uint8_t flag = 1 << cause; - blockedSnoop |= flag; - memSidePort->setBlocked(); + if (!(blocked & flag)) { + //Wasn't already blocked for this cause + blockedSnoop |= flag; + memSidePort->setBlocked(); + } } /** @@ -503,8 +523,6 @@ class BaseCache : public MemObject */ void respond(Packet *pkt, Tick time) { - pkt->makeTimingResponse(); - pkt->result = Packet::Success; CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt); reqCpu->schedule(time); } @@ -517,10 +535,8 @@ class BaseCache : public MemObject void respondToMiss(Packet *pkt, Tick time) { if (!pkt->req->isUncacheable()) { - missLatency[pkt->cmdToIndex()][pkt->req->getThreadNum()] += time - pkt->time; + missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time; } - pkt->makeTimingResponse(); - pkt->result = Packet::Success; CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt); reqCpu->schedule(time); } @@ -529,10 +545,12 @@ class BaseCache : public MemObject * Suppliess the data if cache to cache transfers are enabled. * @param pkt The bus transaction to fulfill. */ - void respondToSnoop(Packet *pkt) + void respondToSnoop(Packet *pkt, Tick time) { - assert("Implement\n" && 0); +// assert("Implement\n" && 0); // mi->respond(pkt,curTick + hitLatency); + CacheEvent *reqMem = new CacheEvent(memSidePort, pkt); + reqMem->schedule(time); } /** @@ -551,6 +569,16 @@ class BaseCache : public MemObject else { //This is where snoops get updated + AddrRangeList dummy; + if (!topLevelCache) + { + cpuSidePort->getPeerAddressRanges(dummy, snoop); + } + else + { + snoop.push_back(RangeSize(0,-1)); + } + return; } } diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 989b8743e..4b8870c95 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -251,7 +251,7 @@ class Cache : public BaseCache * request. * @return The estimated completion time. */ - Tick probe(Packet * &pkt, bool update); + Tick probe(Packet * &pkt, bool update, CachePort * otherSidePort); /** * Snoop for the provided request in the cache and return the estimated @@ -262,7 +262,7 @@ class Cache : public BaseCache * request. * @return The estimated completion time. */ - Tick snoopProbe(Packet * &pkt, bool update); + Tick snoopProbe(Packet * &pkt); }; #endif // __CACHE_HH__ diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 11cd84e88..46f4b0ebe 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -51,7 +51,7 @@ #include "mem/cache/miss/mshr.hh" #include "mem/cache/prefetch/prefetcher.hh" -#include "sim/sim_events.hh" // for SimExitEvent +#include "sim/sim_exit.hh" // for SimExitEvent template<class TagStore, class Buffering, class Coherence> bool @@ -63,14 +63,26 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide) if (pkt->isWrite() && (pkt->req->getFlags() & LOCKED)) { pkt->req->setScResult(1); } - access(pkt); + if (!(pkt->flags & SATISFIED)) { + access(pkt); + } } else { if (pkt->isResponse()) handleResponse(pkt); - else - snoop(pkt); + else { + //Check if we are in phase1 + if (!snoopPhase2) { + snoopPhase2 = true; + } + else { + //Check if we should do the snoop + if (pkt->flags && SNOOP_COMMIT) + snoop(pkt); + snoopPhase2 = false; + } + } } return true; } @@ -87,7 +99,7 @@ doAtomicAccess(Packet *pkt, bool isCpuSide) pkt->req->setScResult(1); } - probe(pkt, true); + probe(pkt, true, NULL); //TEMP ALWAYS SUCCES FOR NOW pkt->result = Packet::Success; } @@ -96,7 +108,7 @@ doAtomicAccess(Packet *pkt, bool isCpuSide) if (pkt->isResponse()) handleResponse(pkt); else - snoopProbe(pkt, true); + snoopProbe(pkt); } //Fix this timing info return hitLatency; @@ -117,16 +129,13 @@ doFunctionalAccess(Packet *pkt, bool isCpuSide) assert("Can't handle LL/SC on functional path\n"); } - probe(pkt, true); + probe(pkt, false, memSidePort); //TEMP ALWAYS SUCCESFUL FOR NOW pkt->result = Packet::Success; } else { - if (pkt->isResponse()) - handleResponse(pkt); - else - snoopProbe(pkt, true); + probe(pkt, false, cpuSidePort); } } @@ -239,7 +248,7 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt) pkt->getAddr() & ~((Addr)blkSize - 1), pkt->req->getPC()); if (blk) { // Hit - hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++; + hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; // clear dirty bit if write through if (pkt->needsResponse()) respond(pkt, curTick+lat); @@ -249,12 +258,12 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt) // Miss if (!pkt->req->isUncacheable()) { - misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++; + misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; /** @todo Move miss count code into BaseCache */ if (missCount) { --missCount; if (missCount == 0) - new SimLoopExitEvent(curTick, "A cache reached the maximum miss count"); + exitSimLoop("A cache reached the maximum miss count"); } } missQueue->handleMiss(pkt, size, curTick + hitLatency); @@ -270,7 +279,7 @@ Cache<TagStore,Buffering,Coherence>::getPacket() Packet * pkt = missQueue->getPacket(); if (pkt) { if (!pkt->req->isUncacheable()) { - if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][pkt->req->getThreadNum()]++; + if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++; BlkType *blk = tags->findBlock(pkt); Packet::Command cmd = coherence->getBusCmd(pkt->cmd, (blk)? blk->status : 0); @@ -314,9 +323,10 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt) PacketList writebacks; blk = tags->handleFill(blk, (MSHR*)pkt->senderState, coherence->getNewState(pkt,old_state), - writebacks); + writebacks, pkt); while (!writebacks.empty()) { missQueue->doWriteback(writebacks.front()); + writebacks.pop_front(); } } missQueue->handleResponse(pkt, curTick + hitLatency); @@ -372,7 +382,6 @@ template<class TagStore, class Buffering, class Coherence> void Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt) { - Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1)); BlkType *blk = tags->findBlock(pkt); MSHR *mshr = missQueue->findMSHR(blk_addr); @@ -385,7 +394,10 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt) //If the outstanding request was an invalidate (upgrade,readex,..) //Then we need to ACK the request until we get the data //Also NACK if the outstanding request is not a cachefill (writeback) + pkt->flags |= SATISFIED; pkt->flags |= NACKED_LINE; + assert("Don't detect these on the other side yet\n"); + respondToSnoop(pkt, curTick + hitLatency); return; } else { @@ -398,6 +410,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt) //@todo Make it so that a read to a pending read can't be exclusive now. //Set the address so find match works + assert("Don't have invalidates yet\n"); invalidatePkt->addrOverride(pkt->getAddr()); //Append the invalidate on @@ -433,7 +446,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt) assert(offset + pkt->getSize() <=blkSize); memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize()); - respondToSnoop(pkt); + respondToSnoop(pkt, curTick + hitLatency); } if (pkt->isInvalidate()) { @@ -449,7 +462,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt) bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state); if (satisfy) { tags->handleSnoop(blk, new_state, pkt); - respondToSnoop(pkt); + respondToSnoop(pkt, curTick + hitLatency); return; } tags->handleSnoop(blk, new_state); @@ -486,7 +499,7 @@ Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr) */ template<class TagStore, class Buffering, class Coherence> Tick -Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update) +Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort* otherSidePort) { // MemDebug::cacheProbe(pkt); if (!pkt->req->isUncacheable()) { @@ -517,7 +530,8 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update) missQueue->findWrites(blk_addr, writes); if (!update) { - memSidePort->sendFunctional(pkt); + otherSidePort->sendFunctional(pkt); + // Check for data in MSHR and writebuffer. if (mshr) { warn("Found outstanding miss on an non-update probe"); @@ -612,12 +626,15 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update) lat = memSidePort->sendAtomic(busPkt); + //Be sure to flip the response to a request for coherence + busPkt->makeAtomicResponse(); + /* if (!(busPkt->flags & SATISFIED)) { // blocked at a higher level, just return return 0; } -*/ misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++; +*/ misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; CacheBlk::State old_state = (blk) ? blk->status : 0; tags->handleFill(blk, busPkt, @@ -642,10 +659,10 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update) } if (update) { - hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++; + hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; } else if (pkt->isWrite()) { // Still need to change data in all locations. - return memSidePort->sendAtomic(pkt); + return otherSidePort->sendAtomic(pkt); } return curTick + lat; } @@ -655,18 +672,18 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update) template<class TagStore, class Buffering, class Coherence> Tick -Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt, bool update) +Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt) { - Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1)); - BlkType *blk = tags->findBlock(pkt); - MSHR *mshr = missQueue->findMSHR(blk_addr); - CacheBlk::State new_state = 0; - bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state); - if (satisfy) { - tags->handleSnoop(blk, new_state, pkt); - return hitLatency; - } - tags->handleSnoop(blk, new_state); - return 0; + Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1)); + BlkType *blk = tags->findBlock(pkt); + MSHR *mshr = missQueue->findMSHR(blk_addr); + CacheBlk::State new_state = 0; + bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state); + if (satisfy) { + tags->handleSnoop(blk, new_state, pkt); + return hitLatency; + } + tags->handleSnoop(blk, new_state); + return 0; } diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc index 67fc7ae56..7a6ea9133 100644 --- a/src/mem/cache/miss/blocking_buffer.cc +++ b/src/mem/cache/miss/blocking_buffer.cc @@ -189,7 +189,7 @@ BlockingBuffer::squash(int threadNum) if (miss.threadNum == threadNum) { Packet * target = miss.getTarget(); miss.popTarget(); - assert(target->req->getThreadNum() == threadNum); + assert(0/*target->req->getThreadNum()*/ == threadNum); target = NULL; assert(!miss.hasTargets()); miss.ntargets=0; @@ -218,7 +218,7 @@ BlockingBuffer::doWriteback(Addr addr, } ///All writebacks charged to same thread @todo figure this out - writebacks[pkt->req->getThreadNum()]++; + writebacks[0/*pkt->req->getThreadNum()*/]++; wb.allocateAsBuffer(pkt); cache->setMasterRequest(Request_WB, curTick); @@ -230,7 +230,7 @@ BlockingBuffer::doWriteback(Addr addr, void BlockingBuffer::doWriteback(Packet * &pkt) { - writebacks[pkt->req->getThreadNum()]++; + writebacks[0/*pkt->req->getThreadNum()*/]++; wb.allocateAsBuffer(pkt); diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc index 76fb25716..273b6587f 100644 --- a/src/mem/cache/miss/miss_queue.cc +++ b/src/mem/cache/miss/miss_queue.cc @@ -413,8 +413,8 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time) mshr = mq.findMatch(blkAddr); if (mshr) { //@todo remove hw_pf here - mshr_hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++; - if (mshr->threadNum != pkt->req->getThreadNum()) { + mshr_hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; + if (mshr->threadNum != 0/*pkt->req->getThreadNum()*/) { mshr->threadNum = -1; } mq.allocateTarget(mshr, pkt); @@ -434,11 +434,11 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time) mshr_no_allocate_misses++; } else { - mshr_misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++; + mshr_misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; } } else { //Count uncacheable accesses - mshr_uncacheable[pkt->cmdToIndex()][pkt->req->getThreadNum()]++; + mshr_uncacheable[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; size = pkt->getSize(); } if (pkt->isWrite() && (pkt->req->isUncacheable() || !writeAllocate || @@ -499,7 +499,7 @@ MissQueue::getPacket() pkt = prefetcher->getPacket(); if (pkt) { //Update statistic on number of prefetches issued (hwpf_mshr_misses) - mshr_misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++; + mshr_misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++; //It will request the bus for the future, but should clear that immedieatley allocateMiss(pkt, pkt->getSize(), curTick); pkt = mq.getReq(); @@ -592,7 +592,7 @@ MissQueue::handleResponse(Packet * &pkt, Tick time) BlockedCause cause = NUM_BLOCKED_CAUSES; if (pkt->isCacheFill() && !pkt->isNoAllocate()) { - mshr_miss_latency[mshr->originalCmd][pkt->req->getThreadNum()] += + mshr_miss_latency[mshr->originalCmd][0/*pkt->req->getThreadNum()*/] += curTick - pkt->time; // targets were handled in the cache tags if (mshr == noTargetMSHR) { @@ -619,7 +619,7 @@ MissQueue::handleResponse(Packet * &pkt, Tick time) } } else { if (pkt->req->isUncacheable()) { - mshr_uncacheable_lat[pkt->cmd][pkt->req->getThreadNum()] += + mshr_uncacheable_lat[pkt->cmd][0/*pkt->req->getThreadNum()*/] += curTick - pkt->time; } if (mshr->hasTargets() && pkt->req->isUncacheable()) { @@ -725,7 +725,7 @@ MissQueue::doWriteback(Addr addr, } ///All writebacks charged to same thread @todo figure this out - writebacks[pkt->req->getThreadNum()]++; + writebacks[0/*pkt->req->getThreadNum()*/]++; allocateWrite(pkt, 0, curTick); } @@ -734,7 +734,7 @@ MissQueue::doWriteback(Addr addr, void MissQueue::doWriteback(Packet * &pkt) { - writebacks[pkt->req->getThreadNum()]++; + writebacks[0/*pkt->req->getThreadNum()*/]++; allocateWrite(pkt, 0, curTick); } diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc index 519ec5ebd..f36032672 100644 --- a/src/mem/cache/miss/mshr.cc +++ b/src/mem/cache/miss/mshr.cc @@ -88,7 +88,7 @@ void MSHR::allocateAsBuffer(Packet * &target) { addr = target->getAddr(); - threadNum = target->req->getThreadNum(); + threadNum = 0/*target->req->getThreadNum()*/; pkt = new Packet(target->req, target->cmd, -1); pkt->allocate(); pkt->senderState = (Packet::SenderState*)this; diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc index 97a56119f..bd9667529 100644 --- a/src/mem/cache/miss/mshr_queue.cc +++ b/src/mem/cache/miss/mshr_queue.cc @@ -128,6 +128,7 @@ MSHR* MSHRQueue::allocate(Packet * &pkt, int size) { Addr aligned_addr = pkt->getAddr() & ~((Addr)size - 1); + assert(!freeList.empty()); MSHR *mshr = freeList.front(); assert(mshr->getNumTargets() == 0); freeList.pop_front(); @@ -251,7 +252,7 @@ MSHRQueue::squash(int threadNum) Packet * target = mshr->getTarget(); mshr->popTarget(); - assert(target->req->getThreadNum() == threadNum); + assert(0/*target->req->getThreadNum()*/ == threadNum); target = NULL; } assert(!mshr->hasTargets()); diff --git a/src/mem/packet.hh b/src/mem/packet.hh index c7d28010c..be9bf5f57 100644 --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -312,7 +312,7 @@ class Packet * for returning as a response to that request. Used for timing * accesses only. For atomic and functional accesses, the * request packet is always implicitly passed back *without* - * modifying the command or destination fields, so this function + * modifying the destination fields, so this function * should not be called. */ void makeTimingResponse() { assert(needsResponse()); @@ -325,6 +325,18 @@ class Packet srcValid = false; } + /** Take a request packet and modify it in place to be suitable + * for returning as a response to that request. + */ + void makeAtomicResponse() { + assert(needsResponse()); + assert(isRequest()); + int icmd = (int)cmd; + icmd &= ~(IsRequest); + icmd |= IsResponse; + cmd = (Command)icmd; + } + /** Take a request packet that has been returned as NACKED and modify it so * that it can be sent out again. Only packets that need a response can be * NACKED, so verify that that is true. */ diff --git a/src/python/m5/main.py b/src/python/m5/main.py index e93ef3a36..ccd6c5807 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -278,6 +278,7 @@ def main(): # set tracing options objects.Trace.flags = options.trace_flags objects.Trace.start = options.trace_start + objects.Trace.cycle = options.trace_cycle objects.Trace.file = options.trace_file objects.Trace.bufsize = options.trace_circlebuf objects.Trace.dump_on_exit = options.trace_dumponexit diff --git a/src/sim/main.cc b/src/sim/main.cc index 5725897f8..874d0ac85 100644 --- a/src/sim/main.cc +++ b/src/sim/main.cc @@ -317,8 +317,8 @@ simulate(Tick num_cycles = -1) else num_cycles = curTick + num_cycles; - Event *limit_event = new SimLoopExitEvent(num_cycles, - "simulate() limit reached"); + Event *limit_event = schedExitSimLoop("simulate() limit reached", + num_cycles); while (1) { // there should always be at least one event (the SimLoopExitEvent @@ -414,7 +414,12 @@ unserializeAll(const std::string &cpt_dir) /** * Queue of C++ callbacks to invoke on simulator exit. */ -CallbackQueue exitCallbacks; +CallbackQueue& +exitCallbacks() +{ + static CallbackQueue theQueue; + return theQueue; +} /** * Register an exit callback. @@ -422,7 +427,7 @@ CallbackQueue exitCallbacks; void registerExitCallback(Callback *callback) { - exitCallbacks.add(callback); + exitCallbacks().add(callback); } BaseCPU * @@ -442,8 +447,8 @@ convertToBaseCPUPtr(SimObject *obj) void doExitCleanup() { - exitCallbacks.process(); - exitCallbacks.clear(); + exitCallbacks().process(); + exitCallbacks().clear(); cout.flush(); diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index b66c78b2c..addf897c6 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -138,14 +138,14 @@ namespace AlphaPseudo void m5exit_old(ThreadContext *tc) { - exitSimLoop(curTick, "m5_exit_old instruction encountered"); + exitSimLoop("m5_exit_old instruction encountered"); } void m5exit(ThreadContext *tc, Tick delay) { Tick when = curTick + delay * Clock::Int::ns; - exitSimLoop(when, "m5_exit instruction encountered"); + schedExitSimLoop("m5_exit instruction encountered", when); } void @@ -270,7 +270,11 @@ namespace AlphaPseudo { if (!doCheckpointInsts) return; - exitSimLoop("checkpoint"); + + Tick when = curTick + delay * Clock::Int::ns; + Tick repeat = period * Clock::Int::ns; + + schedExitSimLoop("checkpoint", when, repeat); } uint64_t diff --git a/src/sim/root.cc b/src/sim/root.cc index ec5e2f7e2..565b57269 100644 --- a/src/sim/root.cc +++ b/src/sim/root.cc @@ -100,7 +100,7 @@ void Root::startup() { if (max_tick != 0) - exitSimLoop(curTick + max_tick, "reached maximum cycle count"); + schedExitSimLoop("reached maximum cycle count", curTick + max_tick); if (progress_interval != 0) new ProgressEvent(&mainEventQueue, progress_interval); diff --git a/src/sim/sim_events.cc b/src/sim/sim_events.cc index d9e8bdeaa..2ccc9dad2 100644 --- a/src/sim/sim_events.cc +++ b/src/sim/sim_events.cc @@ -57,6 +57,11 @@ SimLoopExitEvent::process() // otherwise do nothing... the IsExitEvent flag takes care of // exiting the simulation loop and returning this object to Python + + // but if you are doing this on intervals, don't forget to make another + if (repeat) { + schedule(curTick + repeat); + } } @@ -66,16 +71,20 @@ SimLoopExitEvent::description() return "simulation loop exit"; } -void -exitSimLoop(Tick when, const std::string &message, int exit_code) +SimLoopExitEvent * +schedExitSimLoop(const std::string &message, Tick when, Tick repeat, + EventQueue *q, int exit_code) { - new SimLoopExitEvent(when, message, exit_code); + if (q == NULL) + q = &mainEventQueue; + + return new SimLoopExitEvent(q, when, repeat, message, exit_code); } void exitSimLoop(const std::string &message, int exit_code) { - exitSimLoop(curTick, message, exit_code); + schedExitSimLoop(message, curTick, 0, NULL, exit_code); } void diff --git a/src/sim/sim_events.hh b/src/sim/sim_events.hh index 3c4a9dd05..e1576b38c 100644 --- a/src/sim/sim_events.hh +++ b/src/sim/sim_events.hh @@ -42,6 +42,7 @@ class SimLoopExitEvent : public Event // string explaining why we're terminating std::string cause; int code; + Tick repeat; public: // Default constructor. Only really used for derived classes. @@ -49,16 +50,19 @@ class SimLoopExitEvent : public Event : Event(&mainEventQueue, Sim_Exit_Pri) { } - SimLoopExitEvent(Tick _when, const std::string &_cause, int c = 0) - : Event(&mainEventQueue, Sim_Exit_Pri), cause(_cause), - code(c) - { setFlags(IsExitEvent); schedule(_when); } - SimLoopExitEvent(EventQueue *q, - Tick _when, const std::string &_cause, int c = 0) - : Event(q, Sim_Exit_Pri), cause(_cause), code(c) + Tick _when, Tick _repeat, const std::string &_cause, + int c = 0) + : Event(q, Sim_Exit_Pri), cause(_cause), + code(c), repeat(_repeat) { setFlags(IsExitEvent); schedule(_when); } +// SimLoopExitEvent(EventQueue *q, +// Tick _when, const std::string &_cause, +// Tick _repeat = 0, int c = 0) +// : Event(q, Sim_Exit_Pri), cause(_cause), code(c), repeat(_repeat) +// { setFlags(IsExitEvent); schedule(_when); } + std::string getCause() { return cause; } int getCode() { return code; } diff --git a/src/sim/sim_exit.hh b/src/sim/sim_exit.hh index 545bf4ae0..d4b31d1ea 100644 --- a/src/sim/sim_exit.hh +++ b/src/sim/sim_exit.hh @@ -38,6 +38,8 @@ // forward declaration class Callback; +class EventQueue; +class SimLoopExitEvent; /// Register a callback to be called when Python exits. Defined in /// sim/main.cc. @@ -47,12 +49,14 @@ void registerExitCallback(Callback *); /// Python) at the indicated tick. The message and exit_code /// parameters are saved in the SimLoopExitEvent to indicate why the /// exit occurred. -void exitSimLoop(Tick when, const std::string &message, int exit_code = 0); +SimLoopExitEvent *schedExitSimLoop(const std::string &message, Tick when, + Tick repeat = 0, EventQueue *q = NULL, + int exit_code = 0); /// Schedule an event to exit the simulation loop (returning to /// Python) at the end of the current cycle (curTick). The message /// and exit_code parameters are saved in the SimLoopExitEvent to /// indicate why the exit occurred. -void exitSimLoop(const std::string &cause, int exit_code = 0); +void exitSimLoop(const std::string &message, int exit_code = 0); #endif // __SIM_EXIT_HH__ diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc index dfed2a0c8..3fad8beb5 100644 --- a/src/sim/stat_control.cc +++ b/src/sim/stat_control.cc @@ -186,7 +186,7 @@ StatEvent::process() DumpNow(); if (flags & Stats::Reset) { - cprintf("Resetting stats!\n"); + cprintf("Resetting stats at cycle %d!\n", curTick); reset(); } diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py new file mode 100644 index 000000000..881c23156 --- /dev/null +++ b/tests/configs/o3-timing-mp.py @@ -0,0 +1,90 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + +import m5 +from m5.objects import * +m5.AddToPath('../configs/common') +from FullO3Config import * + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = 1 + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = 100 + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +nb_cores = 4 +cpus = [ DetailedO3CPU() for i in xrange(nb_cores) ] + +# system simulated +system = System(cpu = cpus, physmem = PhysicalMemory(), membus = +Bus()) + +# l2cache & bus +system.toL2Bus = Bus() +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port + +# connect l2c to membus +system.l2c.mem_side = system.membus.port + +# add L1 caches +for cpu in cpus: + cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + cpu.mem = cpu.dcache + # connect cpu level-1 caches to shared level-2 cache + cpu.connectMemPorts(system.toL2Bus) + +# connect memory to membus +system.physmem.port = system.membus.port + + +# ----------------------- +# run simulation +# ----------------------- + +root = Root( system = system ) +root.system.mem_mode = 'timing' +root.trace.flags="Bus Cache" +#root.trace.flags = "BusAddrRanges" diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py new file mode 100644 index 000000000..cc1a36dda --- /dev/null +++ b/tests/configs/simple-atomic-mp.py @@ -0,0 +1,86 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + +import m5 +from m5.objects import * + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = 1 + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = 100 + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +nb_cores = 4 +cpus = [ AtomicSimpleCPU() for i in xrange(nb_cores) ] + +# system simulated +system = System(cpu = cpus, physmem = PhysicalMemory(), membus = +Bus()) + +# l2cache & bus +system.toL2Bus = Bus() +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port + +# connect l2c to membus +system.l2c.mem_side = system.membus.port + +# add L1 caches +for cpu in cpus: + cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + cpu.mem = cpu.dcache + # connect cpu level-1 caches to shared level-2 cache + cpu.connectMemPorts(system.toL2Bus) + +# connect memory to membus +system.physmem.port = system.membus.port + + +# ----------------------- +# run simulation +# ----------------------- + +root = Root( system = system ) +root.system.mem_mode = 'atomic' diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py new file mode 100644 index 000000000..9fc5f3874 --- /dev/null +++ b/tests/configs/simple-timing-mp.py @@ -0,0 +1,86 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Ron Dreslinski + +import m5 +from m5.objects import * + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = 1 + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = 100 + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +nb_cores = 4 +cpus = [ TimingSimpleCPU() for i in xrange(nb_cores) ] + +# system simulated +system = System(cpu = cpus, physmem = PhysicalMemory(), membus = +Bus()) + +# l2cache & bus +system.toL2Bus = Bus() +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port + +# connect l2c to membus +system.l2c.mem_side = system.membus.port + +# add L1 caches +for cpu in cpus: + cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + cpu.mem = cpu.dcache + # connect cpu level-1 caches to shared level-2 cache + cpu.connectMemPorts(system.toL2Bus) + +# connect memory to membus +system.physmem.port = system.membus.port + + +# ----------------------- +# run simulation +# ----------------------- + +root = Root( system = system ) +root.system.mem_mode = 'timing' diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index c3a59fbce..903794729 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -110,6 +110,7 @@ numROBEntries=192 numRobs=1 numThreads=1 predType=tournament +progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 @@ -389,11 +390,17 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -409,6 +416,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out index f491a3081..2a9a97255 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out @@ -28,6 +28,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu.dcache] type=BaseCache @@ -208,6 +214,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 cachePorts=200 decodeToFetchDelay=1 renameToFetchDelay=1 @@ -358,6 +365,7 @@ bus_id=0 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -401,3 +409,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index 5d4f9235a..c2c9affca 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -2,39 +2,39 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. global.BPredUnit.BTBHits 542 # Number of BTB hits -global.BPredUnit.BTBLookups 1938 # Number of BTB lookups +global.BPredUnit.BTBLookups 1936 # Number of BTB lookups global.BPredUnit.RASInCorrect 48 # Number of incorrect RAS predictions. global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1304 # Number of conditional branches predicted -global.BPredUnit.lookups 2256 # Number of BP lookups +global.BPredUnit.condPredicted 1302 # Number of conditional branches predicted +global.BPredUnit.lookups 2254 # Number of BP lookups global.BPredUnit.usedRAS 291 # Number of times the RAS was used to get a target. -host_inst_rate 41797 # Simulator instruction rate (inst/s) -host_mem_usage 160344 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 50948 # Simulator tick rate (ticks/s) +host_inst_rate 47059 # Simulator instruction rate (inst/s) +host_mem_usage 160380 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 57322 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 12 # Number of conflicting loads. memdepunit.memDep.conflictingStores 259 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2050 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 2049 # Number of loads inserted to the mem dependence unit. memdepunit.memDep.insertedStores 1221 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5623 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 6870 # Number of ticks simulated +sim_ticks 6868 # Number of ticks simulated system.cpu.commit.COM:branches 862 # Number of branches committed system.cpu.commit.COM:bw_lim_events 74 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 6116 +system.cpu.commit.COM:committed_per_cycle.samples 6115 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 3908 6389.80% - 1 1064 1739.70% - 2 389 636.04% - 3 210 343.36% - 4 153 250.16% - 5 93 152.06% - 6 76 124.26% - 7 149 243.62% - 8 74 120.99% + 0 3908 6390.84% + 1 1063 1738.35% + 2 389 636.14% + 3 210 343.42% + 4 152 248.57% + 5 94 153.72% + 6 76 124.28% + 7 149 243.66% + 8 74 121.01% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist @@ -46,67 +46,67 @@ system.cpu.commit.COM:swp_count 0 # Nu system.cpu.commit.branchMispredicts 337 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4350 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4342 # The number of squashed insts skipped by commit system.cpu.committedInsts 5623 # Number of Instructions Simulated system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.221768 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.221768 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1538 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3.072000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.240000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1413 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 384 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.081274 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 125 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 224 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.065020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 100 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.467742 # average WriteReq miss latency +system.cpu.cpi 1.221412 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.221412 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1536 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.038760 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.235294 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1407 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 392 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.083984 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 129 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 228 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.066406 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 102 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.564246 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.140845 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 635 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 633 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 459 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.226553 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 186 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.220443 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 179 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 108 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_miss_latency 152 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.086480 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.087438 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 71 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 0.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.505618 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.791908 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 5 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 4 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2359 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 843 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.131836 # miss rate for demand accesses -system.cpu.dcache.demand_misses 311 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 133 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 376 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.072488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2348 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.762987 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.196532 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2040 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 851 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.131175 # miss rate for demand accesses +system.cpu.dcache.demand_misses 308 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 135 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 380 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.073680 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 173 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2359 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.710611 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2.198830 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2348 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.762987 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.196532 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2048 # number of overall hits -system.cpu.dcache.overall_miss_latency 843 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.131836 # miss rate for overall accesses -system.cpu.dcache.overall_misses 311 # number of overall misses -system.cpu.dcache.overall_mshr_hits 133 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 376 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.072488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2040 # number of overall hits +system.cpu.dcache.overall_miss_latency 851 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.131175 # miss rate for overall accesses +system.cpu.dcache.overall_misses 308 # number of overall misses +system.cpu.dcache.overall_mshr_hits 135 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 380 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.073680 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -119,43 +119,43 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 119.831029 # Cycle average of tags in use -system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 114.960547 # Cycle average of tags in use +system.cpu.dcache.total_refs 2040 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 387 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 93 # Number of times decode detected a branch misprediction system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch system.cpu.decode.DECODE:DecodedInsts 12349 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 3542 # Number of cycles decode is idle +system.cpu.decode.DECODE:IdleCycles 3541 # Number of cycles decode is idle system.cpu.decode.DECODE:RunCycles 2158 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 754 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashCycles 753 # Number of cycles decode is squashing system.cpu.decode.DECODE:SquashedInsts 286 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 30 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 2256 # Number of branches that fetch encountered +system.cpu.fetch.Branches 2254 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 1582 # Number of cache lines fetched -system.cpu.fetch.Cycles 3905 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 3904 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 13707 # Number of instructions fetch has processed +system.cpu.fetch.Insts 13699 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 456 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.328336 # Number of branch fetches per cycle +system.cpu.fetch.branchRate 0.328141 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 1582 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 833 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.994906 # Number of inst fetches per cycle +system.cpu.fetch.rate 1.994322 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 6871 +system.cpu.fetch.rateDist.samples 6869 system.cpu.fetch.rateDist.min_value 0 - 0 4549 6620.58% - 1 174 253.24% - 2 186 270.70% - 3 157 228.50% - 4 211 307.09% - 5 153 222.68% - 6 171 248.87% - 7 105 152.82% - 8 1165 1695.53% + 0 4548 6621.05% + 1 174 253.31% + 2 186 270.78% + 3 157 228.56% + 4 211 307.18% + 5 153 222.74% + 6 171 248.94% + 7 105 152.86% + 8 1164 1694.57% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist @@ -170,8 +170,8 @@ system.cpu.icache.ReadReq_mshr_hits 6 # nu system.cpu.icache.ReadReq_mshr_miss_latency 641 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.202908 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_refs 3.909657 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked @@ -218,38 +218,38 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 176.393247 # Cycle average of tags in use +system.cpu.icache.tagsinuse 176.439074 # Cycle average of tags in use system.cpu.icache.total_refs 1255 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.iew.EXEC:branches 1206 # Number of branches executed -system.cpu.iew.EXEC:insts 7969 # Number of executed instructions -system.cpu.iew.EXEC:loads 1610 # Number of load instructions executed system.cpu.iew.EXEC:nop 37 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.159802 # Inst execution rate -system.cpu.iew.EXEC:refs 2599 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 419 # Number of squashed instructions skipped in execute -system.cpu.iew.EXEC:stores 989 # Number of stores executed +system.cpu.iew.EXEC:rate 1.157374 # Inst execution rate +system.cpu.iew.EXEC:refs 2595 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 985 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5438 # num instructions consuming a value -system.cpu.iew.WB:count 7722 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.744575 # average fanout of values written-back +system.cpu.iew.WB:consumers 5409 # num instructions consuming a value +system.cpu.iew.WB:count 7670 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.744130 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4049 # num instructions producing a value -system.cpu.iew.WB:rate 1.123854 # insts written-back per cycle -system.cpu.iew.WB:sent 7762 # cumulative count of insts sent to commit +system.cpu.iew.WB:producers 4025 # num instructions producing a value +system.cpu.iew.WB:rate 1.116611 # insts written-back per cycle +system.cpu.iew.WB:sent 7743 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 393 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2050 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2049 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 1221 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9990 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 9982 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1610 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 409 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7950 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 754 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 753 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked @@ -257,1586 +257,19 @@ system.cpu.iew.lsq.thread.0.forwLoads 55 # Nu system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 41 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1071 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1070 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 409 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 296 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.818486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.818486 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntAlu.max_value 0 -system.cpu.iq.IQ:residence:IntAlu.end_dist - -system.cpu.iq.IQ:residence:IntMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntMult.samples 0 -system.cpu.iq.IQ:residence:IntMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntMult.max_value 0 -system.cpu.iq.IQ:residence:IntMult.end_dist - -system.cpu.iq.IQ:residence:IntDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 8388 # Type of FU issued +system.cpu.ipc 0.818725 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.818725 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8359 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 2 0.02% # Type of FU issued - IntAlu 5594 66.69% # Type of FU issued + IntAlu 5573 66.67% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -1845,13 +278,13 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1757 20.95% # Type of FU issued - MemWrite 1032 12.30% # Type of FU issued + MemRead 1757 21.02% # Type of FU issued + MemWrite 1024 12.25% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.013710 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.013758 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available IntAlu 1 0.87% # attempts to use FU when none available @@ -1869,72 +302,74 @@ system.cpu.iq.ISSUE:fu_full.start_dist InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 6871 +system.cpu.iq.ISSUE:issued_per_cycle.samples 6869 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 3753 5462.09% - 1 894 1301.12% - 2 723 1052.25% - 3 614 893.61% - 4 451 656.38% - 5 279 406.05% - 6 104 151.36% - 7 41 59.67% - 8 12 17.46% + 0 3761 5475.32% + 1 891 1297.13% + 2 720 1048.19% + 3 617 898.24% + 4 445 647.84% + 5 278 404.72% + 6 104 151.40% + 7 41 59.69% + 8 12 17.47% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.220783 # Inst issue rate -system.cpu.iq.iqInstsAdded 9932 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8388 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.216917 # Inst issue rate +system.cpu.iq.iqInstsAdded 9924 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8359 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 3985 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2486 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadReq_accesses 499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2.042254 # average ReadReq miss latency +system.cpu.iq.iqSquashedOperandsExamined 2568 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 494 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.071138 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1015 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995992 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 497 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 490 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.981964 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 490 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 1019 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995951 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 492 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 492 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995951 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 492 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReq_accesses 2 # number of WriteReq accesses(hits+misses) +system.cpu.l2cache.WriteReq_hits 2 # number of WriteReq hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004024 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.008130 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 499 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.demand_accesses 496 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.071138 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1015 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995992 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 497 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1019 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.991935 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 492 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 490 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981964 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 492 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.991935 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 492 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 499 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2.042254 # average overall miss latency +system.cpu.l2cache.overall_accesses 496 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.071138 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1015 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995992 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 497 # number of overall misses +system.cpu.l2cache.overall_hits 4 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1019 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.991935 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 492 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 490 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981964 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 490 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 492 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.991935 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 492 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -1947,22 +382,22 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 492 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 295.773395 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 290.948901 # Cycle average of tags in use +system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 6871 # number of cpu cycles simulated +system.cpu.numCycles 6869 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 3758 # Number of cycles rename is idle +system.cpu.rename.RENAME:IdleCycles 3757 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 62 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:RenameLookups 14786 # Number of register rename lookups that rename has made system.cpu.rename.RENAME:RenamedInsts 11555 # Number of instructions processed by rename system.cpu.rename.RENAME:RenamedOperands 8634 # Number of destination operands rename has renamed system.cpu.rename.RENAME:RunCycles 1975 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 754 # Number of cycles rename is squashing +system.cpu.rename.RENAME:SquashCycles 753 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 111 # Number of cycles rename is unblocking system.cpu.rename.RENAME:UndoneMaps 4583 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 269 # count of cycles rename stalled for serializing inst diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index fbb329a2f..14ef519e9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:12 2006 +M5 compiled Oct 7 2006 12:38:12 +M5 started Sat Oct 7 12:38:34 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing -Exiting @ tick 6870 because target called exit() +Exiting @ tick 6868 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index f84372165..f7e73950d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -64,6 +64,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem +progress_interval=0 simulate_stalls=false system=system width=1 @@ -74,11 +75,17 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -94,6 +101,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out index a3621a08a..198d7df5e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out @@ -28,6 +28,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=AtomicSimpleCPU @@ -35,6 +41,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system workload=system.cpu.workload @@ -48,6 +55,7 @@ simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -91,3 +99,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index 17eea9aed..e26480539 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:14 2006 +M5 compiled Oct 7 2006 11:12:49 +M5 started Sat Oct 7 11:13:02 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Exiting @ tick 5641 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index 80d2a27e1..cefcf7f11 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -64,6 +64,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.cpu.dcache +progress_interval=0 system=system workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -197,11 +198,17 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/linux/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -217,6 +224,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out index 09d8f0c22..1ed18ff71 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out @@ -67,6 +67,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=TimingSimpleCPU @@ -74,6 +80,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.cpu.dcache system=system workload=system.cpu.workload @@ -169,6 +176,7 @@ hit_latency=1 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -212,3 +220,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index fe2cd43a5..97d39456e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 113478 # Simulator instruction rate (inst/s) -host_mem_usage 159608 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 165749 # Simulator tick rate (ticks/s) +host_inst_rate 286207 # Simulator instruction rate (inst/s) +host_mem_usage 159648 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 413300 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5642 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 8312 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 981 # number of ReadReq accesses(hits+misses) +sim_ticks 8316 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 891 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 270 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.091743 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 180 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.091743 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 821 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.737500 # average WriteReq miss latency +system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 276 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 184 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 741 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 739 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 219 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.097442 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 80 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.089901 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 146 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.088916 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.089901 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 9.600000 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.854545 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1802 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.876471 # average overall miss latency +system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1632 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 489 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.094340 # miss rate for demand accesses -system.cpu.dcache.demand_misses 170 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1626 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.092127 # miss rate for demand accesses +system.cpu.dcache.demand_misses 165 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 326 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.090455 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 330 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.092127 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 165 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 1802 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.876471 # average overall miss latency +system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1632 # number of overall hits -system.cpu.dcache.overall_miss_latency 489 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.094340 # miss rate for overall accesses -system.cpu.dcache.overall_misses 170 # number of overall misses +system.cpu.dcache.overall_hits 1626 # number of overall hits +system.cpu.dcache.overall_miss_latency 495 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.092127 # miss rate for overall accesses +system.cpu.dcache.overall_misses 165 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 326 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.090455 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 163 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 330 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.092127 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 112.055094 # Cycle average of tags in use -system.cpu.dcache.total_refs 1632 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 107.125526 # Cycle average of tags in use +system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5643 # number of ReadReq accesses(hits+misses) @@ -138,55 +138,57 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 133.267292 # Cycle average of tags in use +system.cpu.icache.tagsinuse 133.213539 # Cycle average of tags in use system.cpu.icache.total_refs 5366 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 447 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 1.968610 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_accesses 442 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 878 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997763 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 446 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 439 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.982103 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 439 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 882 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997738 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 441 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 441 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997738 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 441 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReq_accesses 2 # number of WriteReq accesses(hits+misses) +system.cpu.l2cache.WriteReq_hits 2 # number of WriteReq hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002242 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.006803 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 1.968610 # average overall miss latency +system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 878 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 882 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.993243 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 439 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.982103 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 441 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.993243 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 1.968610 # average overall miss latency +system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 878 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 446 # number of overall misses +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.overall_miss_latency 882 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.993243 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 441 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 439 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.982103 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 441 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.993243 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -199,10 +201,10 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 446 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 441 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 245.259112 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 240.276061 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index 7104aa0ce..a9c37a14d 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:15 2006 +M5 compiled Oct 7 2006 12:38:12 +M5 started Sat Oct 7 12:38:38 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing -Exiting @ tick 8312 because target called exit() +Exiting @ tick 8316 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 790ae6ab3..45904ca08 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -110,6 +110,7 @@ numROBEntries=192 numRobs=1 numThreads=1 predType=tournament +progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 renameToIEWDelay=2 @@ -389,11 +390,17 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/tru64/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -409,6 +416,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out index 474ea3523..c5cec4f22 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out @@ -28,6 +28,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu.dcache] type=BaseCache @@ -208,6 +214,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 cachePorts=200 decodeToFetchDelay=1 renameToFetchDelay=1 @@ -358,6 +365,7 @@ bus_id=0 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -401,3 +409,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt index db582e731..53d94a43f 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt @@ -8,10 +8,10 @@ global.BPredUnit.condIncorrect 222 # Nu global.BPredUnit.condPredicted 441 # Number of conditional branches predicted global.BPredUnit.lookups 888 # Number of BP lookups global.BPredUnit.usedRAS 160 # Number of times the RAS was used to get a target. -host_inst_rate 26468 # Simulator instruction rate (inst/s) -host_mem_usage 159864 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 31894 # Simulator tick rate (ticks/s) +host_inst_rate 45832 # Simulator instruction rate (inst/s) +host_mem_usage 159900 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 55090 # Simulator tick rate (ticks/s) memdepunit.memDep.conflictingLoads 9 # Number of conflicting loads. memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. memdepunit.memDep.insertedLoads 675 # Number of loads inserted to the mem dependence unit. @@ -51,16 +51,16 @@ system.cpu.committedInsts 2387 # Nu system.cpu.committedInsts_total 2387 # Number of Instructions Simulated system.cpu.cpi 1.209049 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.209049 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 535 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses 534 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 469 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 195 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.121495 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.121723 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 65 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_miss_latency 122 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.114019 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.114232 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 3.017241 # average WriteReq miss latency @@ -75,37 +75,37 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # m system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets 1.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.305882 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 8.294118 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 3 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 829 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 828 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 3.008130 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency -system.cpu.dcache.demand_hits 706 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 705 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 370 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.148372 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.148551 # miss rate for demand accesses system.cpu.dcache.demand_misses 123 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 38 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 175 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.102533 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.102657 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 829 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 828 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 3.008130 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2.058824 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 706 # number of overall hits +system.cpu.dcache.overall_hits 705 # number of overall hits system.cpu.dcache.overall_miss_latency 370 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.148372 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.148551 # miss rate for overall accesses system.cpu.dcache.overall_misses 123 # number of overall misses system.cpu.dcache.overall_mshr_hits 38 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 175 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.102533 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.102657 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -122,7 +122,7 @@ system.cpu.dcache.replacements 0 # nu system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 54.161413 # Cycle average of tags in use -system.cpu.dcache.total_refs 706 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 705 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 82 # Number of cycles decode is blocked @@ -222,30 +222,30 @@ system.cpu.icache.tagsinuse 115.538968 # Cy system.cpu.icache.total_refs 550 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.iew.EXEC:branches 533 # Number of branches executed -system.cpu.iew.EXEC:insts 3123 # Number of executed instructions -system.cpu.iew.EXEC:loads 578 # Number of load instructions executed +system.cpu.iew.EXEC:branches 532 # Number of branches executed system.cpu.iew.EXEC:nop 247 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.081746 # Inst execution rate -system.cpu.iew.EXEC:refs 914 # number of memory reference insts executed -system.cpu.iew.EXEC:squashedInsts 148 # Number of squashed instructions skipped in execute +system.cpu.iew.EXEC:rate 1.078628 # Inst execution rate +system.cpu.iew.EXEC:refs 910 # number of memory reference insts executed system.cpu.iew.EXEC:stores 336 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1801 # num instructions consuming a value -system.cpu.iew.WB:count 3070 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.791227 # average fanout of values written-back +system.cpu.iew.WB:consumers 1788 # num instructions consuming a value +system.cpu.iew.WB:count 3053 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.790828 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1425 # num instructions producing a value -system.cpu.iew.WB:rate 1.063388 # insts written-back per cycle -system.cpu.iew.WB:sent 3076 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 159 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 1414 # num instructions producing a value +system.cpu.iew.WB:rate 1.057499 # insts written-back per cycle +system.cpu.iew.WB:sent 3067 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 158 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 675 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 127 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 369 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 3835 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 574 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 143 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3114 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -257,1586 +257,19 @@ system.cpu.iew.lsq.thread.0.forwLoads 30 # Nu system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread.0.squashedLoads 260 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 75 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 106 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 105 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly system.cpu.ipc 0.827096 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.827096 # IPC: Total IPC of All Threads -system.cpu.iq.IQ:residence:(null).start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:(null).samples 0 -system.cpu.iq.IQ:residence:(null).min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:(null).max_value 0 -system.cpu.iq.IQ:residence:(null).end_dist - -system.cpu.iq.IQ:residence:IntAlu.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IntAlu.samples 0 -system.cpu.iq.IQ:residence:IntAlu.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 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-system.cpu.iq.IQ:residence:IntDiv.samples 0 -system.cpu.iq.IQ:residence:IntDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IntDiv.max_value 0 -system.cpu.iq.IQ:residence:IntDiv.end_dist - -system.cpu.iq.IQ:residence:FloatAdd.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatAdd.samples 0 -system.cpu.iq.IQ:residence:FloatAdd.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatAdd.max_value 0 -system.cpu.iq.IQ:residence:FloatAdd.end_dist - -system.cpu.iq.IQ:residence:FloatCmp.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCmp.samples 0 -system.cpu.iq.IQ:residence:FloatCmp.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCmp.max_value 0 -system.cpu.iq.IQ:residence:FloatCmp.end_dist - -system.cpu.iq.IQ:residence:FloatCvt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatCvt.samples 0 -system.cpu.iq.IQ:residence:FloatCvt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatCvt.max_value 0 -system.cpu.iq.IQ:residence:FloatCvt.end_dist - -system.cpu.iq.IQ:residence:FloatMult.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatMult.samples 0 -system.cpu.iq.IQ:residence:FloatMult.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatMult.max_value 0 -system.cpu.iq.IQ:residence:FloatMult.end_dist - -system.cpu.iq.IQ:residence:FloatDiv.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatDiv.samples 0 -system.cpu.iq.IQ:residence:FloatDiv.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatDiv.max_value 0 -system.cpu.iq.IQ:residence:FloatDiv.end_dist - -system.cpu.iq.IQ:residence:FloatSqrt.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:FloatSqrt.samples 0 -system.cpu.iq.IQ:residence:FloatSqrt.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:FloatSqrt.max_value 0 -system.cpu.iq.IQ:residence:FloatSqrt.end_dist - -system.cpu.iq.IQ:residence:MemRead.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemRead.samples 0 -system.cpu.iq.IQ:residence:MemRead.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemRead.max_value 0 -system.cpu.iq.IQ:residence:MemRead.end_dist - -system.cpu.iq.IQ:residence:MemWrite.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:MemWrite.samples 0 -system.cpu.iq.IQ:residence:MemWrite.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:MemWrite.max_value 0 -system.cpu.iq.IQ:residence:MemWrite.end_dist - -system.cpu.iq.IQ:residence:IprAccess.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:IprAccess.samples 0 -system.cpu.iq.IQ:residence:IprAccess.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:IprAccess.max_value 0 -system.cpu.iq.IQ:residence:IprAccess.end_dist - -system.cpu.iq.IQ:residence:InstPrefetch.start_dist # cycles from dispatch to issue -system.cpu.iq.IQ:residence:InstPrefetch.samples 0 -system.cpu.iq.IQ:residence:InstPrefetch.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.IQ:residence:InstPrefetch.max_value 0 -system.cpu.iq.IQ:residence:InstPrefetch.end_dist - -system.cpu.iq.ISSUE:(null)_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:(null)_delay.samples 0 -system.cpu.iq.ISSUE:(null)_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:(null)_delay.max_value 0 -system.cpu.iq.ISSUE:(null)_delay.end_dist - -system.cpu.iq.ISSUE:IntAlu_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntAlu_delay.samples 0 -system.cpu.iq.ISSUE:IntAlu_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntAlu_delay.max_value 0 -system.cpu.iq.ISSUE:IntAlu_delay.end_dist - -system.cpu.iq.ISSUE:IntMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntMult_delay.samples 0 -system.cpu.iq.ISSUE:IntMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntMult_delay.max_value 0 -system.cpu.iq.ISSUE:IntMult_delay.end_dist - -system.cpu.iq.ISSUE:IntDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IntDiv_delay.samples 0 -system.cpu.iq.ISSUE:IntDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IntDiv_delay.max_value 0 -system.cpu.iq.ISSUE:IntDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatAdd_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatAdd_delay.samples 0 -system.cpu.iq.ISSUE:FloatAdd_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatAdd_delay.max_value 0 -system.cpu.iq.ISSUE:FloatAdd_delay.end_dist - -system.cpu.iq.ISSUE:FloatCmp_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCmp_delay.samples 0 -system.cpu.iq.ISSUE:FloatCmp_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCmp_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCmp_delay.end_dist - -system.cpu.iq.ISSUE:FloatCvt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatCvt_delay.samples 0 -system.cpu.iq.ISSUE:FloatCvt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatCvt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatCvt_delay.end_dist - -system.cpu.iq.ISSUE:FloatMult_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatMult_delay.samples 0 -system.cpu.iq.ISSUE:FloatMult_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatMult_delay.max_value 0 -system.cpu.iq.ISSUE:FloatMult_delay.end_dist - -system.cpu.iq.ISSUE:FloatDiv_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatDiv_delay.samples 0 -system.cpu.iq.ISSUE:FloatDiv_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatDiv_delay.max_value 0 -system.cpu.iq.ISSUE:FloatDiv_delay.end_dist - -system.cpu.iq.ISSUE:FloatSqrt_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:FloatSqrt_delay.samples 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.max_value 0 -system.cpu.iq.ISSUE:FloatSqrt_delay.end_dist - -system.cpu.iq.ISSUE:MemRead_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemRead_delay.samples 0 -system.cpu.iq.ISSUE:MemRead_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemRead_delay.max_value 0 -system.cpu.iq.ISSUE:MemRead_delay.end_dist - -system.cpu.iq.ISSUE:MemWrite_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:MemWrite_delay.samples 0 -system.cpu.iq.ISSUE:MemWrite_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:MemWrite_delay.max_value 0 -system.cpu.iq.ISSUE:MemWrite_delay.end_dist - -system.cpu.iq.ISSUE:IprAccess_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:IprAccess_delay.samples 0 -system.cpu.iq.ISSUE:IprAccess_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:IprAccess_delay.max_value 0 -system.cpu.iq.ISSUE:IprAccess_delay.end_dist - -system.cpu.iq.ISSUE:InstPrefetch_delay.start_dist # cycles from operands ready to issue -system.cpu.iq.ISSUE:InstPrefetch_delay.samples 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.min_value 0 - 0 0 - 2 0 - 4 0 - 6 0 - 8 0 - 10 0 - 12 0 - 14 0 - 16 0 - 18 0 - 20 0 - 22 0 - 24 0 - 26 0 - 28 0 - 30 0 - 32 0 - 34 0 - 36 0 - 38 0 - 40 0 - 42 0 - 44 0 - 46 0 - 48 0 - 50 0 - 52 0 - 54 0 - 56 0 - 58 0 - 60 0 - 62 0 - 64 0 - 66 0 - 68 0 - 70 0 - 72 0 - 74 0 - 76 0 - 78 0 - 80 0 - 82 0 - 84 0 - 86 0 - 88 0 - 90 0 - 92 0 - 94 0 - 96 0 - 98 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.max_value 0 -system.cpu.iq.ISSUE:InstPrefetch_delay.end_dist - -system.cpu.iq.ISSUE:FU_type_0 3271 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0 3257 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist (null) 0 0.00% # Type of FU issued - IntAlu 2317 70.83% # Type of FU issued + IntAlu 2308 70.86% # Type of FU issued IntMult 1 0.03% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -1845,13 +278,13 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 609 18.62% # Type of FU issued - MemWrite 344 10.52% # Type of FU issued + MemRead 605 18.58% # Type of FU issued + MemWrite 343 10.53% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist system.cpu.iq.ISSUE:fu_busy_cnt 40 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.012229 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate 0.012281 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist (null) 0 0.00% # attempts to use FU when none available IntAlu 5 12.50% # attempts to use FU when none available @@ -1871,11 +304,11 @@ system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle.samples 2887 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 1603 5552.48% - 1 434 1503.29% - 2 301 1042.60% - 3 220 762.04% - 4 167 578.46% + 0 1607 5566.33% + 1 435 1506.75% + 2 298 1032.21% + 3 221 765.50% + 4 164 568.06% 5 94 325.60% 6 46 159.33% 7 15 51.96% @@ -1883,14 +316,14 @@ system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.133010 # Inst issue rate +system.cpu.iq.ISSUE:rate 1.128161 # Inst issue rate system.cpu.iq.iqInstsAdded 3581 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3271 # Number of instructions issued +system.cpu.iq.iqInstsIssued 3257 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1067 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsExamined 1088 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 477 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 503 # Number of squashed operands that are examined and possibly removed from graph system.cpu.l2cache.ReadReq_accesses 274 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 2.018248 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout index 708b9587a..fa94f7eb9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:16 2006 +M5 compiled Oct 7 2006 12:38:12 +M5 started Sat Oct 7 12:38:40 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing Exiting @ tick 2886 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini index 1ec052afb..34f5c0b32 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -64,6 +64,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem +progress_interval=0 simulate_stalls=false system=system width=1 @@ -74,11 +75,17 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/tru64/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -94,6 +101,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out index ae24ae2a8..a474765ae 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out @@ -28,6 +28,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=AtomicSimpleCPU @@ -35,6 +41,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system workload=system.cpu.workload @@ -48,6 +55,7 @@ simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -91,3 +99,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt index b4747f1f4..b120e12b9 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 46556 # Simulator instruction rate (inst/s) -host_mem_usage 147672 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 46204 # Simulator tick rate (ticks/s) +host_inst_rate 548861 # Simulator instruction rate (inst/s) +host_mem_usage 147820 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 504404 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout index 438e330f5..0c9b00960 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:18 2006 +M5 compiled Oct 7 2006 11:12:49 +M5 started Sat Oct 7 11:13:09 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic tests/run.py quick/00.hello/alpha/tru64/simple-atomic Exiting @ tick 2577 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini index e833d841e..0d7d34e64 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -64,6 +64,7 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.cpu.dcache +progress_interval=0 system=system workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -197,11 +198,17 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=hello +egid=100 env= +euid=100 executable=tests/test-progs/hello/bin/alpha/tru64/hello +gid=100 input=cin output=cout +pid=100 +ppid=99 system=system +uid=100 [system.membus] type=Bus @@ -217,6 +224,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out index 1914b47e7..9b44f8ddd 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out @@ -67,6 +67,12 @@ input=cin output=cout env= system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 [system.cpu] type=TimingSimpleCPU @@ -74,6 +80,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.cpu.dcache system=system workload=system.cpu.workload @@ -169,6 +176,7 @@ hit_latency=1 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -212,3 +220,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt index 47bcc1b3c..916f9dad8 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt @@ -1,22 +1,22 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 73626 # Simulator instruction rate (inst/s) -host_mem_usage 159128 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 106590 # Simulator tick rate (ticks/s) +host_inst_rate 196989 # Simulator instruction rate (inst/s) +host_mem_usage 159172 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 279840 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2578 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated sim_ticks 3777 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 416 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 361 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 165 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.132212 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 110 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.132212 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency @@ -30,37 +30,37 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # m system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 7.658537 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 710 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.demand_hits 628 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 246 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.115493 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 164 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.115493 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 710 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 628 # number of overall hits +system.cpu.dcache.overall_hits 627 # number of overall hits system.cpu.dcache.overall_miss_latency 246 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.115493 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_misses 82 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 164 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.115493 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -77,7 +77,7 @@ system.cpu.dcache.replacements 0 # nu system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.tagsinuse 53.009529 # Cycle average of tags in use -system.cpu.dcache.total_refs 628 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses) diff --git a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout index 4a02e57f0..d152dc89c 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:18 2006 +M5 compiled Oct 7 2006 12:38:12 +M5 started Sat Oct 7 12:38:45 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing Exiting @ tick 3777 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt index 5d054b950..bc5ad3cca 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 129834 # Simulator instruction rate (inst/s) -host_mem_usage 158964 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 194881 # Simulator tick rate (ticks/s) +host_inst_rate 273933 # Simulator instruction rate (inst/s) +host_mem_usage 159012 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 403699 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5657 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated -sim_ticks 8573 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1131 # number of ReadReq accesses(hits+misses) +sim_ticks 8579 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1052 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 237 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.069850 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 79 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 158 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.069850 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 79 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 933 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 2.586207 # average WriteReq miss latency +system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 246 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 164 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 875 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 150 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.062165 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 58 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.054113 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 50 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 100 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.053591 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.054113 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 14.065693 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.560606 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2064 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 2.824818 # average overall miss latency +system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1927 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 387 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.066376 # miss rate for demand accesses -system.cpu.dcache.demand_misses 137 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 1922 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 396 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.064265 # miss rate for demand accesses +system.cpu.dcache.demand_misses 132 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 258 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.062500 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 129 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 264 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.064265 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 132 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2064 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 2.824818 # average overall miss latency +system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1927 # number of overall hits -system.cpu.dcache.overall_miss_latency 387 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.066376 # miss rate for overall accesses -system.cpu.dcache.overall_misses 137 # number of overall misses +system.cpu.dcache.overall_hits 1922 # number of overall hits +system.cpu.dcache.overall_miss_latency 396 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.064265 # miss rate for overall accesses +system.cpu.dcache.overall_misses 132 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 258 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.062500 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 129 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 264 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.064265 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 132 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 137 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 91.822487 # Cycle average of tags in use -system.cpu.dcache.total_refs 1927 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.924009 # Cycle average of tags in use +system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses) @@ -138,55 +138,57 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 138.188010 # Cycle average of tags in use +system.cpu.icache.tagsinuse 138.192774 # Cycle average of tags in use system.cpu.icache.total_refs 5355 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 440 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 1.963470 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_accesses 435 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 860 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.995455 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 438 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 430 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.977273 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 430 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 866 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995402 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 433 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 433 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995402 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 433 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReq_accesses 1 # number of WriteReq accesses(hits+misses) +system.cpu.l2cache.WriteReq_hits 1 # number of WriteReq hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.004566 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.006928 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 440 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 1.963470 # average overall miss latency +system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 860 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995455 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 438 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 866 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.993119 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 430 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.977273 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 430 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 433 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.993119 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 440 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 1.963470 # average overall miss latency +system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 860 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995455 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 438 # number of overall misses +system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.overall_miss_latency 866 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.993119 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 433 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 430 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.977273 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 430 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 433 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.993119 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -199,10 +201,10 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 438 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 433 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 231.300093 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 226.406294 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout index 11009935d..954193ee0 100644 --- a/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/mips/linux/simple-timing/stdout @@ -6,8 +6,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:37:09 -M5 started Tue Sep 5 15:46:32 2006 +M5 compiled Oct 7 2006 12:52:26 +M5 started Sat Oct 7 12:52:42 2006 M5 executing on zizzer.eecs.umich.edu command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing -Exiting @ tick 8573 because target called exit() +Exiting @ tick 8579 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini new file mode 100644 index 000000000..5b6a4c7ff --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -0,0 +1,440 @@ +[root] +type=Root +children=system +checkpoint= +clock=1000000000000 +max_tick=0 +output_file=cout +progress_interval=0 + +[debug] +break_cycles= + +[exetrace] +intel_format=false +pc_symbol=true +print_cpseq=false +print_cycle=true +print_data=true +print_effaddr=true +print_fetchseq=false +print_iregs=false +print_opclass=true +print_thread=true +speculative=true +trace_system=client + +[serialize] +count=10 +cycle=0 +dir=cpt.%012d +period=0 + +[stats] +descriptions=true +dump_cycle=0 +dump_period=0 +dump_reset=false +ignore_events= +mysql_db= +mysql_host= +mysql_password= +mysql_user= +project_name=test +simulation_name=test +simulation_sample=0 +text_compat=true +text_file=m5stats.txt + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +physmem=system.physmem + +[system.cpu] +type=DerivO3CPU +children=dcache fuPool icache l2cache toL2Bus workload0 workload1 +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +choiceCtrBits=2 +choicePredictorSize=8192 +clock=1 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +issueToExecuteDelay=1 +issueWidth=8 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +mem=system.cpu.dcache +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +squashWidth=8 +system=system +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu.workload0 system.cpu.workload1 +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=262144 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList0 +count=6 +opList=system.cpu.fuPool.FUList0.opList0 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList4.opList0 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList0 +count=0 +opList=system.cpu.fuPool.FUList5.opList0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 +count=1 +opList=system.cpu.fuPool.FUList7.opList0 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu.icache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=131072 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.l2cache] +type=BaseCache +adaptive_compression=false +assoc=2 +block_size=64 +compressed_bus=false +compression_latency=0 +do_copy=false +hash_delay=1 +hit_latency=1 +latency=1 +lifo=false +max_miss_count=0 +mshrs=10 +prefetch_access=false +prefetch_cache_check_push=true +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10 +prefetch_miss=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +protocol=Null +repl=Null +size=2097152 +split=false +split_size=0 +store_compressed=false +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[1] + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.workload0] +type=LiveProcess +cmd=hello +egid=100 +env= +euid=100 +executable=tests/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.cpu.workload1] +type=LiveProcess +cmd=hello +egid=100 +env= +euid=100 +executable=tests/test-progs/hello/bin/alpha/linux/hello +gid=100 +input=cin +output=cout +pid=100 +ppid=99 +system=system +uid=100 + +[system.membus] +type=Bus +bus_id=0 +port=system.physmem.port system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=1 +range=0:134217727 +port=system.membus.port[0] + +[trace] +bufsize=0 +cycle=0 +dump_on_exit=false +file=cout +flags= +ignore= +start=0 + diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out new file mode 100644 index 000000000..bfdd7bcde --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out @@ -0,0 +1,429 @@ +[root] +type=Root +clock=1000000000000 +max_tick=0 +progress_interval=0 +output_file=cout + +[system.physmem] +type=PhysicalMemory +file= +range=[0,134217727] +latency=1 + +[system] +type=System +physmem=system.physmem +mem_mode=atomic + +[system.membus] +type=Bus +bus_id=0 + +[system.cpu.workload0] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu.workload1] +type=LiveProcess +cmd=hello +executable=tests/test-progs/hello/bin/alpha/linux/hello +input=cin +output=cout +env= +system=system +uid=100 +euid=100 +gid=100 +egid=100 +pid=100 +ppid=99 + +[system.cpu.dcache] +type=BaseCache +size=262144 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.fuPool.FUList0.opList0] +type=OpDesc +opClass=IntAlu +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList0] +type=FUDesc +opList=system.cpu.fuPool.FUList0.opList0 +count=6 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +opClass=IntMult +opLat=3 +issueLat=1 + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +opClass=IntDiv +opLat=20 +issueLat=19 + +[system.cpu.fuPool.FUList1] +type=FUDesc +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 +count=2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +opClass=FloatAdd +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +opClass=FloatCmp +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +opClass=FloatCvt +opLat=2 +issueLat=1 + +[system.cpu.fuPool.FUList2] +type=FUDesc +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 +count=4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +opClass=FloatMult +opLat=4 +issueLat=1 + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +opClass=FloatDiv +opLat=12 +issueLat=12 + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +opClass=FloatSqrt +opLat=24 +issueLat=24 + +[system.cpu.fuPool.FUList3] +type=FUDesc +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +count=2 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList4] +type=FUDesc +opList=system.cpu.fuPool.FUList4.opList0 +count=0 + +[system.cpu.fuPool.FUList5.opList0] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList5] +type=FUDesc +opList=system.cpu.fuPool.FUList5.opList0 +count=0 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +opClass=MemRead +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +opClass=MemWrite +opLat=1 +issueLat=1 + +[system.cpu.fuPool.FUList6] +type=FUDesc +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 +count=4 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +opClass=IprAccess +opLat=3 +issueLat=3 + +[system.cpu.fuPool.FUList7] +type=FUDesc +opList=system.cpu.fuPool.FUList7.opList0 +count=1 + +[system.cpu.fuPool] +type=FUPool +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 + +[system.cpu] +type=DerivO3CPU +clock=1 +numThreads=1 +activity=0 +workload=system.cpu.workload0 system.cpu.workload1 +mem=system.cpu.dcache +checker=null +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +cachePorts=200 +decodeToFetchDelay=1 +renameToFetchDelay=1 +iewToFetchDelay=1 +commitToFetchDelay=1 +fetchWidth=8 +renameToDecodeDelay=1 +iewToDecodeDelay=1 +commitToDecodeDelay=1 +fetchToDecodeDelay=1 +decodeWidth=8 +iewToRenameDelay=1 +commitToRenameDelay=1 +decodeToRenameDelay=1 +renameWidth=8 +commitToIEWDelay=1 +renameToIEWDelay=2 +issueToExecuteDelay=1 +dispatchWidth=8 +issueWidth=8 +wbWidth=8 +wbDepth=1 +fuPool=system.cpu.fuPool +iewToCommitDelay=1 +renameToROBDelay=1 +commitWidth=8 +squashWidth=8 +trapLatency=13 +backComSize=5 +forwardComSize=5 +predType=tournament +localPredictorSize=2048 +localCtrBits=2 +localHistoryTableSize=2048 +localHistoryBits=11 +globalPredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +choicePredictorSize=8192 +choiceCtrBits=2 +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +LQEntries=32 +SQEntries=32 +LFSTSize=1024 +SSITSize=1024 +numPhysIntRegs=256 +numPhysFloatRegs=256 +numIQEntries=64 +numROBEntries=192 +smtNumFetchingThreads=1 +smtFetchPolicy=SingleThread +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtROBPolicy=Partitioned +smtROBThreshold=100 +smtCommitPolicy=RoundRobin +instShiftAmt=2 +defer_registration=false +function_trace=false +function_trace_start=0 + +[system.cpu.icache] +type=BaseCache +size=131072 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.l2cache] +type=BaseCache +size=2097152 +assoc=2 +block_size=64 +latency=1 +mshrs=10 +tgts_per_mshr=5 +write_buffers=8 +prioritizeRequests=false +do_copy=false +protocol=null +trace_addr=0 +hash_delay=1 +repl=null +compressed_bus=false +store_compressed=false +adaptive_compression=false +compression_latency=0 +block_size=64 +max_miss_count=0 +addr_range=[0,18446744073709551615] +split=false +split_size=0 +lifo=false +two_queue=false +prefetch_miss=false +prefetch_access=false +prefetcher_size=100 +prefetch_past_page=false +prefetch_serial_squash=false +prefetch_latency=10 +prefetch_degree=1 +prefetch_policy=none +prefetch_cache_check_push=true +prefetch_use_cpu_id=true +prefetch_data_accesses_only=false +hit_latency=1 + +[system.cpu.toL2Bus] +type=Bus +bus_id=0 + +[trace] +flags= +start=0 +cycle=0 +bufsize=0 +file=cout +dump_on_exit=false +ignore= + +[stats] +descriptions=true +project_name=test +simulation_name=test +simulation_sample=0 +text_file=m5stats.txt +text_compat=true +mysql_db= +mysql_user= +mysql_password= +mysql_host= +events_start=-1 +dump_reset=false +dump_cycle=0 +dump_period=0 +ignore_events= + +[random] +seed=1 + +[exetrace] +speculative=true +print_cycle=true +print_opclass=true +print_thread=true +print_effaddr=true +print_data=true +print_iregs=false +print_fetchseq=false +print_cpseq=false +print_reg_delta=false +pc_symbol=true +intel_format=false +trace_system=client + +[debug] +break_cycles= + +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt new file mode 100644 index 000000000..a249947ca --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -0,0 +1,726 @@ + +---------- Begin Simulation Statistics ---------- +global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +global.BPredUnit.BTBHits 642 # Number of BTB hits +global.BPredUnit.BTBLookups 3598 # Number of BTB lookups +global.BPredUnit.RASInCorrect 99 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1081 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2449 # Number of conditional branches predicted +global.BPredUnit.lookups 4173 # Number of BP lookups +global.BPredUnit.usedRAS 551 # Number of times the RAS was used to get a target. +host_inst_rate 50082 # Simulator instruction rate (inst/s) +host_mem_usage 161260 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host +host_tick_rate 37535 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 41 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 39 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 194 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 198 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 1868 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 1833 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1109 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1108 # Number of stores inserted to the mem dependence unit. +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 11247 # Number of instructions simulated +sim_seconds 0.000000 # Number of seconds simulated +sim_ticks 8441 # Number of ticks simulated +system.cpu.commit.COM:branches 1724 # Number of branches committed +system.cpu.commit.COM:branches_0 862 # Number of branches committed +system.cpu.commit.COM:branches_1 862 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 126 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits +system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle.samples 8393 +system.cpu.commit.COM:committed_per_cycle.min_value 0 + 0 3957 4714.64% + 1 1909 2274.51% + 2 919 1094.96% + 3 516 614.80% + 4 375 446.80% + 5 235 280.00% + 6 189 225.19% + 7 167 198.98% + 8 126 150.13% +system.cpu.commit.COM:committed_per_cycle.max_value 8 +system.cpu.commit.COM:committed_per_cycle.end_dist + +system.cpu.commit.COM:count 11281 # Number of instructions committed +system.cpu.commit.COM:count_0 5640 # Number of instructions committed +system.cpu.commit.COM:count_1 5641 # Number of instructions committed +system.cpu.commit.COM:loads 1958 # Number of loads committed +system.cpu.commit.COM:loads_0 979 # Number of loads committed +system.cpu.commit.COM:loads_1 979 # Number of loads committed +system.cpu.commit.COM:membars 0 # Number of memory barriers committed +system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed +system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed +system.cpu.commit.COM:refs 3582 # Number of memory references committed +system.cpu.commit.COM:refs_0 1791 # Number of memory references committed +system.cpu.commit.COM:refs_1 1791 # Number of memory references committed +system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed +system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed +system.cpu.commit.branchMispredicts 832 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 7525 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 5623 # Number of Instructions Simulated +system.cpu.committedInsts_1 5624 # Number of Instructions Simulated +system.cpu.committedInsts_total 11247 # Number of Instructions Simulated +system.cpu.cpi_0 1.501156 # CPI: Cycles Per Instruction +system.cpu.cpi_1 1.500889 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.750511 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 2916 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 2916 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3.076923 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency_0 3.076923 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2.231156 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 2.231156 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 2682 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 2682 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 720 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 720 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.080247 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate_0 0.080247 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 234 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 234 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 444 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 444 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.068244 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.068244 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 199 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 199 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 2.762376 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency_0 2.762376 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2.062500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 2.062500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1321 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1321 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 837 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 837 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.186576 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate_0 0.186576 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 303 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 303 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 159 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 159 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 297 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 297 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.088670 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.088670 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 144 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses_0 144 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets 1 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11.670554 # Average number of references to valid blocks. +system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_no_targets 7 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles_no_targets 7 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 4540 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 4540 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 2.899441 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 2.899441 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2.160350 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 2.160350 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency +system.cpu.dcache.demand_hits 4003 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 4003 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1557 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 1557 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.118282 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.118282 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses +system.cpu.dcache.demand_misses 537 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 537 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 194 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 194 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 741 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 741 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.075551 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.075551 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 343 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 343 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses 4540 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 4540 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 2.899441 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 2.899441 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2.160350 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 2.160350 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 4003 # number of overall hits +system.cpu.dcache.overall_hits_0 4003 # number of overall hits +system.cpu.dcache.overall_hits_1 0 # number of overall hits +system.cpu.dcache.overall_miss_latency 1557 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 1557 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.118282 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.118282 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses +system.cpu.dcache.overall_misses 537 # number of overall misses +system.cpu.dcache.overall_misses_0 537 # number of overall misses +system.cpu.dcache.overall_misses_1 0 # number of overall misses +system.cpu.dcache.overall_mshr_hits 194 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 194 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 741 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 741 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.075551 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.075551 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 343 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 343 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.replacements_0 0 # number of replacements +system.cpu.dcache.replacements_1 0 # number of replacements +system.cpu.dcache.sampled_refs 343 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 226.419332 # Cycle average of tags in use +system.cpu.dcache.total_refs 4003 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.writebacks_0 0 # number of writebacks +system.cpu.dcache.writebacks_1 0 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 1682 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 270 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 368 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 22713 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 9663 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3758 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1395 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 233 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 106 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 4173 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 2872 # Number of cache lines fetched +system.cpu.fetch.Cycles 6967 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 203 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 25244 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1143 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.494314 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 2872 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.990287 # Number of inst fetches per cycle +system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist.samples 8442 +system.cpu.fetch.rateDist.min_value 0 + 0 4348 5150.44% + 1 274 324.57% + 2 232 274.82% + 3 248 293.77% + 4 311 368.40% + 5 277 328.12% + 6 296 350.63% + 7 291 344.71% + 8 2165 2564.56% +system.cpu.fetch.rateDist.max_value 8 +system.cpu.fetch.rateDist.end_dist + +system.cpu.icache.ReadReq_accesses 2872 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 2872 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2.982343 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency_0 2.982343 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.995153 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 1.995153 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2249 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2249 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1858 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 1858 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.216922 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate_0 0.216922 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 623 # number of ReadReq misses +system.cpu.icache.ReadReq_misses_0 623 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 4 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1235 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 1235 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.215529 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.215529 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_refs 3.633279 # Average number of references to valid blocks. +system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 2872 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 2872 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2.982343 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 2.982343 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1.995153 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 1.995153 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency +system.cpu.icache.demand_hits 2249 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2249 # number of demand (read+write) hits +system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1858 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 1858 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.216922 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.216922 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses +system.cpu.icache.demand_misses 623 # number of demand (read+write) misses +system.cpu.icache.demand_misses_0 623 # number of demand (read+write) misses +system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 4 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 4 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1235 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 1235 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.215529 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.215529 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses 2872 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 2872 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2.982343 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 2.982343 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1.995153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 1.995153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 2249 # number of overall hits +system.cpu.icache.overall_hits_0 2249 # number of overall hits +system.cpu.icache.overall_hits_1 0 # number of overall hits +system.cpu.icache.overall_miss_latency 1858 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 1858 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.216922 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.216922 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses +system.cpu.icache.overall_misses 623 # number of overall misses +system.cpu.icache.overall_misses_0 623 # number of overall misses +system.cpu.icache.overall_misses_1 0 # number of overall misses +system.cpu.icache.overall_mshr_hits 4 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 4 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1235 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 1235 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.215529 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.215529 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses +system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.icache.replacements 9 # number of replacements +system.cpu.icache.replacements_0 9 # number of replacements +system.cpu.icache.replacements_1 0 # number of replacements +system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 332.429874 # Cycle average of tags in use +system.cpu.icache.total_refs 2249 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.writebacks_0 0 # number of writebacks +system.cpu.icache.writebacks_1 0 # number of writebacks +system.cpu.iew.EXEC:branches 2318 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1160 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1158 # Number of branches executed +system.cpu.iew.EXEC:nop 65 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 31 # number of nop insts executed +system.cpu.iew.EXEC:nop_1 34 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.814854 # Inst execution rate +system.cpu.iew.EXEC:refs 4932 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2474 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 2458 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1873 # Number of stores executed +system.cpu.iew.EXEC:stores_0 937 # Number of stores executed +system.cpu.iew.EXEC:stores_1 936 # Number of stores executed +system.cpu.iew.EXEC:swp 0 # number of swp insts executed +system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed +system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed +system.cpu.iew.WB:consumers 10005 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5007 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 4998 # num instructions consuming a value +system.cpu.iew.WB:count 14809 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 7412 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 7397 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.777111 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.776113 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.778111 # average fanout of values written-back +system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.WB:producers 7775 # num instructions producing a value +system.cpu.iew.WB:producers_0 3886 # num instructions producing a value +system.cpu.iew.WB:producers_1 3889 # num instructions producing a value +system.cpu.iew.WB:rate 1.754205 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.877991 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.876214 # insts written-back per cycle +system.cpu.iew.WB:sent 14942 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 7477 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 7465 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 925 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 3701 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 606 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2217 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 18807 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3059 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1537 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1522 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 927 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15321 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1395 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread.0.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 45 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.0.memOrderViolation 32 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 889 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 297 # Number of stores squashed +system.cpu.iew.lsq.thread.1.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread.1.cacheBlocked 6 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.1.forwLoads 45 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread.1.memOrderViolation 35 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.1.squashedLoads 854 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 296 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 67 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 764 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 161 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.666153 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.666272 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.332425 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 8158 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5514 67.59% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1662 20.37% # Type of FU issued + MemWrite 977 11.98% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0.end_dist +system.cpu.iq.ISSUE:FU_type_1 8090 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1.start_dist + (null) 2 0.02% # Type of FU issued + IntAlu 5481 67.75% # Type of FU issued + IntMult 1 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 2 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 1640 20.27% # Type of FU issued + MemWrite 964 11.92% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1.end_dist +system.cpu.iq.ISSUE:FU_type 16248 # Type of FU issued +system.cpu.iq.ISSUE:FU_type.start_dist + (null) 4 0.02% # Type of FU issued + IntAlu 10995 67.67% # Type of FU issued + IntMult 2 0.01% # Type of FU issued + IntDiv 0 0.00% # Type of FU issued + FloatAdd 4 0.02% # Type of FU issued + FloatCmp 0 0.00% # Type of FU issued + FloatCvt 0 0.00% # Type of FU issued + FloatMult 0 0.00% # Type of FU issued + FloatDiv 0 0.00% # Type of FU issued + FloatSqrt 0 0.00% # Type of FU issued + MemRead 3302 20.32% # Type of FU issued + MemWrite 1941 11.95% # Type of FU issued + IprAccess 0 0.00% # Type of FU issued + InstPrefetch 0 0.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type.end_dist +system.cpu.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 103 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 78 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011140 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.006339 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.004801 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_full.start_dist + (null) 0 0.00% # attempts to use FU when none available + IntAlu 10 5.52% # attempts to use FU when none available + IntMult 0 0.00% # attempts to use FU when none available + IntDiv 0 0.00% # attempts to use FU when none available + FloatAdd 0 0.00% # attempts to use FU when none available + FloatCmp 0 0.00% # attempts to use FU when none available + FloatCvt 0 0.00% # attempts to use FU when none available + FloatMult 0 0.00% # attempts to use FU when none available + FloatDiv 0 0.00% # attempts to use FU when none available + FloatSqrt 0 0.00% # attempts to use FU when none available + MemRead 100 55.25% # attempts to use FU when none available + MemWrite 71 39.23% # attempts to use FU when none available + IprAccess 0 0.00% # attempts to use FU when none available + InstPrefetch 0 0.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full.end_dist +system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle.samples 8442 +system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 + 0 2688 3184.08% + 1 1455 1723.53% + 2 1431 1695.10% + 3 1111 1316.04% + 4 762 902.63% + 5 581 688.23% + 6 288 341.15% + 7 91 107.79% + 8 35 41.46% +system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 +system.cpu.iq.ISSUE:issued_per_cycle.end_dist + +system.cpu.iq.ISSUE:rate 1.924662 # Inst issue rate +system.cpu.iq.iqInstsAdded 18702 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16248 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 6660 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4124 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadReq_accesses 962 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 962 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2.059561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency_0 2.059561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 1 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits_0 5 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1971 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 1971 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994802 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate_0 0.994802 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 957 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses_0 957 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 957 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 957 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994802 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.994802 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 957 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses_0 957 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReq_accesses 4 # number of WriteReq accesses(hits+misses) +system.cpu.l2cache.WriteReq_accesses_0 4 # number of WriteReq accesses(hits+misses) +system.cpu.l2cache.WriteReq_hits 4 # number of WriteReq hits +system.cpu.l2cache.WriteReq_hits_0 4 # number of WriteReq hits +system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.009404 # Average number of references to valid blocks. +system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses 966 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 966 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2.059561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 2.059561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 1 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency +system.cpu.l2cache.demand_hits 9 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 9 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1971 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 1971 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.990683 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.990683 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_1 no value # miss rate for demand accesses +system.cpu.l2cache.demand_misses 957 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_0 957 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses_1 0 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency 957 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 957 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.990683 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.990683 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_1 no value # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 957 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_0 957 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses 966 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 966 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2.059561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 2.059561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 1 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 9 # number of overall hits +system.cpu.l2cache.overall_hits_0 9 # number of overall hits +system.cpu.l2cache.overall_hits_1 0 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1971 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 1971 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.990683 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.990683 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses +system.cpu.l2cache.overall_misses 957 # number of overall misses +system.cpu.l2cache.overall_misses_0 957 # number of overall misses +system.cpu.l2cache.overall_misses_1 0 # number of overall misses +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency 957 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 957 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.990683 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.990683 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 957 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_0 957 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses_1 0 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency_1 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses_0 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses_1 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.replacements_0 0 # number of replacements +system.cpu.l2cache.replacements_1 0 # number of replacements +system.cpu.l2cache.sampled_refs 957 # Sample count of references to valid blocks. +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.tagsinuse 558.911632 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 0 # number of writebacks +system.cpu.l2cache.writebacks_0 0 # number of writebacks +system.cpu.l2cache.writebacks_1 0 # number of writebacks +system.cpu.numCycles 8442 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 338 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 9965 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 695 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 26913 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 21123 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 15786 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3571 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1395 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 763 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7684 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 572 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 1900 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed +system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls +system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr new file mode 100644 index 000000000..890488cd2 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr @@ -0,0 +1,4 @@ +warn: Entering event queue @ 0. Starting simulation... +warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 +warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout new file mode 100644 index 000000000..be25795fb --- /dev/null +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -0,0 +1,14 @@ +Hello world! +Hello world! +M5 Simulator System + +Copyright (c) 2001-2006 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled Oct 7 2006 12:38:12 +M5 started Sat Oct 7 12:38:47 2006 +M5 executing on zizzer.eecs.umich.edu +command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing +Exiting @ tick 8441 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/test.py b/tests/quick/01.hello-2T-smt/test.py new file mode 100644 index 000000000..04ff8c2e6 --- /dev/null +++ b/tests/quick/01.hello-2T-smt/test.py @@ -0,0 +1,32 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Korey Sewell + +process1 = LiveProcess(cmd = 'hello', executable = binpath('hello')) +process2 = LiveProcess(cmd = 'hello', executable = binpath('hello')) + +root.system.cpu.workload = [process1, process2] diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index c2bcb99aa..3d719c501 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -58,6 +58,7 @@ mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh +symbolfile= system_rev=1024 system_type=34 @@ -86,6 +87,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem profile=0 +progress_interval=0 simulate_stalls=false system=system width=1 @@ -116,6 +118,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem profile=0 +progress_interval=0 simulate_stalls=false system=system width=1 @@ -584,6 +587,7 @@ pio=system.iobus.port[24] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out index 737ee6611..b8290213e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out @@ -21,6 +21,7 @@ console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh +symbolfile= init_param=0 system_type=34 system_rev=1024 @@ -86,6 +87,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system itb=system.cpu0.itb @@ -113,6 +115,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system itb=system.cpu1.itb @@ -492,6 +495,7 @@ bus_id=0 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -535,6 +539,9 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + [pseudo_inst] quiesce=true statistics=true diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console index c3c7b2676..4a397ddbf 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console @@ -74,7 +74,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB -
hda: 163296 sectors (83 MB), CHS=162/16/63, UDMA(33) +
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
hda: hda1
hdb: max request size: 128KiB
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) @@ -102,10 +102,6 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 480k freed -
init started: BusyBox v1.00-rc2 (2004.11.18-16:22+0000) multi-call binary - -PTXdist-0.7.0 (2004-11-18T11:23:40-0500) - +
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended -
loading script... +loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt index c7715aeac..376929ebb 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt @@ -1,239 +1,232 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1382023 # Simulator instruction rate (inst/s) -host_mem_usage 194588 # Number of bytes of host memory used -host_seconds 45.78 # Real time elapsed on the host -host_tick_rate 77681401 # Simulator tick rate (ticks/s) +host_inst_rate 1361363 # Simulator instruction rate (inst/s) +host_mem_usage 194440 # Number of bytes of host memory used +host_seconds 45.04 # Real time elapsed on the host +host_tick_rate 78691874 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 63264995 # Number of instructions simulated -sim_seconds 1.778030 # Number of seconds simulated -sim_ticks 3556060806 # Number of ticks simulated -system.cpu0.dtb.accesses 1831687 # DTB accesses -system.cpu0.dtb.acv 360 # DTB access violations -system.cpu0.dtb.hits 12876975 # DTB hits -system.cpu0.dtb.misses 11050 # DTB misses -system.cpu0.dtb.read_accesses 495437 # DTB read accesses -system.cpu0.dtb.read_acv 219 # DTB read access violations -system.cpu0.dtb.read_hits 7121424 # DTB read hits -system.cpu0.dtb.read_misses 9036 # DTB read misses -system.cpu0.dtb.write_accesses 1336250 # DTB write accesses -system.cpu0.dtb.write_acv 141 # DTB write access violations -system.cpu0.dtb.write_hits 5755551 # DTB write hits -system.cpu0.dtb.write_misses 2014 # DTB write misses -system.cpu0.idle_fraction 0.984569 # Percentage of idle cycles -system.cpu0.itb.accesses 2328068 # ITB accesses -system.cpu0.itb.acv 216 # ITB acv -system.cpu0.itb.hits 2323500 # ITB hits -system.cpu0.itb.misses 4568 # ITB misses -system.cpu0.kern.callpal 179206 # number of callpals executed +sim_insts 61314617 # Number of instructions simulated +sim_seconds 1.772124 # Number of seconds simulated +sim_ticks 3544247159 # Number of ticks simulated +system.cpu0.dtb.accesses 1850344 # DTB accesses +system.cpu0.dtb.acv 301 # DTB access violations +system.cpu0.dtb.hits 12691711 # DTB hits +system.cpu0.dtb.misses 8349 # DTB misses +system.cpu0.dtb.read_accesses 509385 # DTB read accesses +system.cpu0.dtb.read_acv 184 # DTB read access violations +system.cpu0.dtb.read_hits 7018751 # DTB read hits +system.cpu0.dtb.read_misses 6579 # DTB read misses +system.cpu0.dtb.write_accesses 1340959 # DTB write accesses +system.cpu0.dtb.write_acv 117 # DTB write access violations +system.cpu0.dtb.write_hits 5672960 # DTB write hits +system.cpu0.dtb.write_misses 1770 # DTB write misses +system.cpu0.idle_fraction 0.984893 # Percentage of idle cycles +system.cpu0.itb.accesses 1981604 # ITB accesses +system.cpu0.itb.acv 161 # ITB acv +system.cpu0.itb.hits 1978255 # ITB hits +system.cpu0.itb.misses 3349 # ITB misses +system.cpu0.kern.callpal 176688 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 91 0.05% 0.05% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.05% # number of callpals executed -system.cpu0.kern.callpal_swpctx 1375 0.77% 0.82% # number of callpals executed -system.cpu0.kern.callpal_tbi 20 0.01% 0.83% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 0.84% # number of callpals executed -system.cpu0.kern.callpal_swpipl 168681 94.13% 94.96% # number of callpals executed -system.cpu0.kern.callpal_rdps 4713 2.63% 97.59% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 97.59% # number of callpals executed -system.cpu0.kern.callpal_wrusp 4 0.00% 97.59% # number of callpals executed -system.cpu0.kern.callpal_rdusp 11 0.01% 97.60% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 97.60% # number of callpals executed -system.cpu0.kern.callpal_rti 3639 2.03% 99.63% # number of callpals executed -system.cpu0.kern.callpal_callsys 461 0.26% 99.89% # number of callpals executed -system.cpu0.kern.callpal_imb 197 0.11% 100.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 97 0.05% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed +system.cpu0.kern.callpal_swpctx 1117 0.63% 0.69% # number of callpals executed +system.cpu0.kern.callpal_tbi 44 0.02% 0.71% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 0.72% # number of callpals executed +system.cpu0.kern.callpal_swpipl 166811 94.41% 95.13% # number of callpals executed +system.cpu0.kern.callpal_rdps 4911 2.78% 97.91% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 97.91% # number of callpals executed +system.cpu0.kern.callpal_wrusp 3 0.00% 97.91% # number of callpals executed +system.cpu0.kern.callpal_rdusp 9 0.01% 97.91% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 97.92% # number of callpals executed +system.cpu0.kern.callpal_rti 3236 1.83% 99.75% # number of callpals executed +system.cpu0.kern.callpal_callsys 325 0.18% 99.93% # number of callpals executed +system.cpu0.kern.callpal_imb 121 0.07% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 197512 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 190918 # number of hwrei instructions executed system.cpu0.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu0.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu0.kern.inst.quiesce 1917 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 174431 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 73383 42.07% 42.07% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 286 0.16% 42.23% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 5540 3.18% 45.41% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 8 0.00% 45.41% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 95214 54.59% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 156222 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 73336 46.94% 46.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 286 0.18% 47.13% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 5540 3.55% 50.67% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 8 0.01% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 77052 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3555570558 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3533670973 99.38% 99.38% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 45785 0.00% 99.39% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 1008642 0.03% 99.41% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 1988 0.00% 99.41% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 20843170 0.59% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.895609 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.999360 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 1922 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 172116 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 72060 41.87% 41.87% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 251 0.15% 42.01% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 5518 3.21% 45.22% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 7 0.00% 45.22% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 94280 54.78% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 153515 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 72019 46.91% 46.91% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 251 0.16% 47.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 5518 3.59% 50.67% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 7 0.00% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 75720 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 3543835079 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 3521923327 99.38% 99.38% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 39982 0.00% 99.38% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 1005040 0.03% 99.41% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 1756 0.00% 99.41% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 20864974 0.59% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used 0.891928 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_0 0.999431 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.809251 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1633 -system.cpu0.kern.mode_good_user 1486 -system.cpu0.kern.mode_good_idle 147 -system.cpu0.kern.mode_switch_kernel 2898 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1486 # number of protection mode switches -system.cpu0.kern.mode_switch_idle 2090 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.504479 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.563492 # fraction of useful protection mode switches +system.cpu0.kern.ipl_used_31 0.803140 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1277 +system.cpu0.kern.mode_good_user 1129 +system.cpu0.kern.mode_good_idle 148 +system.cpu0.kern.mode_switch_kernel 2253 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1129 # number of protection mode switches +system.cpu0.kern.mode_switch_idle 2074 # number of protection mode switches +system.cpu0.kern.mode_switch_good 0.468109 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.566800 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_idle 0.070335 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 29671488 0.83% 0.83% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 2605758 0.07% 0.91% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_idle 3523245106 99.09% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 1376 # number of times the context was actually changed -system.cpu0.kern.syscall 312 # number of syscalls executed -system.cpu0.kern.syscall_fork 9 2.88% 2.88% # number of syscalls executed -system.cpu0.kern.syscall_read 20 6.41% 9.29% # number of syscalls executed -system.cpu0.kern.syscall_write 6 1.92% 11.22% # number of syscalls executed -system.cpu0.kern.syscall_close 36 11.54% 22.76% # number of syscalls executed -system.cpu0.kern.syscall_chdir 1 0.32% 23.08% # number of syscalls executed -system.cpu0.kern.syscall_chmod 1 0.32% 23.40% # number of syscalls executed -system.cpu0.kern.syscall_obreak 26 8.33% 31.73% # number of syscalls executed -system.cpu0.kern.syscall_lseek 9 2.88% 34.62% # number of syscalls executed -system.cpu0.kern.syscall_getpid 8 2.56% 37.18% # number of syscalls executed -system.cpu0.kern.syscall_setuid 2 0.64% 37.82% # number of syscalls executed -system.cpu0.kern.syscall_getuid 4 1.28% 39.10% # number of syscalls executed -system.cpu0.kern.syscall_access 4 1.28% 40.38% # number of syscalls executed -system.cpu0.kern.syscall_dup 4 1.28% 41.67% # number of syscalls executed -system.cpu0.kern.syscall_open 40 12.82% 54.49% # number of syscalls executed -system.cpu0.kern.syscall_getgid 4 1.28% 55.77% # number of syscalls executed -system.cpu0.kern.syscall_sigprocmask 12 3.85% 59.62% # number of syscalls executed -system.cpu0.kern.syscall_ioctl 13 4.17% 63.78% # number of syscalls executed -system.cpu0.kern.syscall_readlink 1 0.32% 64.10% # number of syscalls executed -system.cpu0.kern.syscall_execve 7 2.24% 66.35% # number of syscalls executed -system.cpu0.kern.syscall_pre_F64_stat 22 7.05% 73.40% # number of syscalls executed -system.cpu0.kern.syscall_pre_F64_lstat 1 0.32% 73.72% # number of syscalls executed -system.cpu0.kern.syscall_mmap 28 8.97% 82.69% # number of syscalls executed -system.cpu0.kern.syscall_munmap 4 1.28% 83.97% # number of syscalls executed -system.cpu0.kern.syscall_mprotect 7 2.24% 86.22% # number of syscalls executed -system.cpu0.kern.syscall_gethostname 1 0.32% 86.54% # number of syscalls executed -system.cpu0.kern.syscall_dup2 3 0.96% 87.50% # number of syscalls executed -system.cpu0.kern.syscall_pre_F64_fstat 15 4.81% 92.31% # number of syscalls executed -system.cpu0.kern.syscall_fcntl 11 3.53% 95.83% # number of syscalls executed -system.cpu0.kern.syscall_socket 3 0.96% 96.79% # number of syscalls executed -system.cpu0.kern.syscall_connect 3 0.96% 97.76% # number of syscalls executed -system.cpu0.kern.syscall_setgid 2 0.64% 98.40% # number of syscalls executed -system.cpu0.kern.syscall_getrlimit 2 0.64% 99.04% # number of syscalls executed -system.cpu0.kern.syscall_setsid 3 0.96% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015431 # Percentage of non-idle cycles -system.cpu0.numCycles 54873632 # number of cpu cycles simulated -system.cpu0.num_insts 54868848 # Number of instructions executed -system.cpu0.num_refs 12918621 # Number of memory references -system.cpu1.dtb.accesses 524398 # DTB accesses -system.cpu1.dtb.acv 60 # DTB access violations -system.cpu1.dtb.hits 2058922 # DTB hits -system.cpu1.dtb.misses 5263 # DTB misses -system.cpu1.dtb.read_accesses 337746 # DTB read accesses -system.cpu1.dtb.read_acv 23 # DTB read access violations -system.cpu1.dtb.read_hits 1301369 # DTB read hits -system.cpu1.dtb.read_misses 4766 # DTB read misses -system.cpu1.dtb.write_accesses 186652 # DTB write accesses -system.cpu1.dtb.write_acv 37 # DTB write access violations -system.cpu1.dtb.write_hits 757553 # DTB write hits -system.cpu1.dtb.write_misses 497 # DTB write misses -system.cpu1.idle_fraction 0.997638 # Percentage of idle cycles -system.cpu1.itb.accesses 1711917 # ITB accesses +system.cpu0.kern.mode_switch_good_idle 0.071360 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks_kernel 28710240 0.81% 0.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 2184201 0.06% 0.87% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_idle 3512891779 99.13% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 1118 # number of times the context was actually changed +system.cpu0.kern.syscall 192 # number of syscalls executed +system.cpu0.kern.syscall_fork 7 3.65% 3.65% # number of syscalls executed +system.cpu0.kern.syscall_read 13 6.77% 10.42% # number of syscalls executed +system.cpu0.kern.syscall_write 4 2.08% 12.50% # number of syscalls executed +system.cpu0.kern.syscall_close 28 14.58% 27.08% # number of syscalls executed +system.cpu0.kern.syscall_chdir 1 0.52% 27.60% # number of syscalls executed +system.cpu0.kern.syscall_obreak 7 3.65% 31.25% # number of syscalls executed +system.cpu0.kern.syscall_lseek 6 3.12% 34.37% # number of syscalls executed +system.cpu0.kern.syscall_getpid 4 2.08% 36.46% # number of syscalls executed +system.cpu0.kern.syscall_setuid 1 0.52% 36.98% # number of syscalls executed +system.cpu0.kern.syscall_getuid 3 1.56% 38.54% # number of syscalls executed +system.cpu0.kern.syscall_access 7 3.65% 42.19% # number of syscalls executed +system.cpu0.kern.syscall_dup 2 1.04% 43.23% # number of syscalls executed +system.cpu0.kern.syscall_open 34 17.71% 60.94% # number of syscalls executed +system.cpu0.kern.syscall_getgid 3 1.56% 62.50% # number of syscalls executed +system.cpu0.kern.syscall_sigprocmask 8 4.17% 66.67% # number of syscalls executed +system.cpu0.kern.syscall_ioctl 9 4.69% 71.35% # number of syscalls executed +system.cpu0.kern.syscall_readlink 1 0.52% 71.87% # number of syscalls executed +system.cpu0.kern.syscall_execve 5 2.60% 74.48% # number of syscalls executed +system.cpu0.kern.syscall_mmap 22 11.46% 85.94% # number of syscalls executed +system.cpu0.kern.syscall_munmap 2 1.04% 86.98% # number of syscalls executed +system.cpu0.kern.syscall_mprotect 6 3.12% 90.10% # number of syscalls executed +system.cpu0.kern.syscall_gethostname 1 0.52% 90.62% # number of syscalls executed +system.cpu0.kern.syscall_dup2 2 1.04% 91.67% # number of syscalls executed +system.cpu0.kern.syscall_fcntl 8 4.17% 95.83% # number of syscalls executed +system.cpu0.kern.syscall_socket 2 1.04% 96.87% # number of syscalls executed +system.cpu0.kern.syscall_connect 2 1.04% 97.92% # number of syscalls executed +system.cpu0.kern.syscall_setgid 1 0.52% 98.44% # number of syscalls executed +system.cpu0.kern.syscall_getrlimit 1 0.52% 98.96% # number of syscalls executed +system.cpu0.kern.syscall_setsid 2 1.04% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.015107 # Percentage of non-idle cycles +system.cpu0.numCycles 53543489 # number of cpu cycles simulated +system.cpu0.num_insts 53539979 # Number of instructions executed +system.cpu0.num_refs 12727196 # Number of memory references +system.cpu1.dtb.accesses 460215 # DTB accesses +system.cpu1.dtb.acv 72 # DTB access violations +system.cpu1.dtb.hits 2012555 # DTB hits +system.cpu1.dtb.misses 4236 # DTB misses +system.cpu1.dtb.read_accesses 319867 # DTB read accesses +system.cpu1.dtb.read_acv 26 # DTB read access violations +system.cpu1.dtb.read_hits 1276251 # DTB read hits +system.cpu1.dtb.read_misses 3800 # DTB read misses +system.cpu1.dtb.write_accesses 140348 # DTB write accesses +system.cpu1.dtb.write_acv 46 # DTB write access violations +system.cpu1.dtb.write_hits 736304 # DTB write hits +system.cpu1.dtb.write_misses 436 # DTB write misses +system.cpu1.idle_fraction 0.997806 # Percentage of idle cycles +system.cpu1.itb.accesses 1302484 # ITB accesses system.cpu1.itb.acv 23 # ITB acv -system.cpu1.itb.hits 1709682 # ITB hits -system.cpu1.itb.misses 2235 # ITB misses -system.cpu1.kern.callpal 25990 # number of callpals executed +system.cpu1.itb.hits 1300768 # ITB hits +system.cpu1.itb.misses 1716 # ITB misses +system.cpu1.kern.callpal 27118 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 8 0.03% 0.03% # number of callpals executed -system.cpu1.kern.callpal_wrmces 1 0.00% 0.04% # number of callpals executed +system.cpu1.kern.callpal_wripir 7 0.03% 0.03% # number of callpals executed +system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.04% # number of callpals executed -system.cpu1.kern.callpal_swpctx 554 2.13% 2.17% # number of callpals executed -system.cpu1.kern.callpal_tbi 7 0.03% 2.20% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.03% 2.23% # number of callpals executed -system.cpu1.kern.callpal_swpipl 22366 86.06% 88.28% # number of callpals executed -system.cpu1.kern.callpal_rdps 98 0.38% 88.66% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 88.66% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.02% 88.68% # number of callpals executed -system.cpu1.kern.callpal_rdusp 1 0.00% 88.68% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 88.70% # number of callpals executed -system.cpu1.kern.callpal_rti 2613 10.05% 98.75% # number of callpals executed -system.cpu1.kern.callpal_callsys 208 0.80% 99.55% # number of callpals executed -system.cpu1.kern.callpal_imb 116 0.45% 100.00% # number of callpals executed +system.cpu1.kern.callpal_swpctx 515 1.90% 1.94% # number of callpals executed +system.cpu1.kern.callpal_tbi 10 0.04% 1.97% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.03% 2.00% # number of callpals executed +system.cpu1.kern.callpal_swpipl 23496 86.64% 88.64% # number of callpals executed +system.cpu1.kern.callpal_rdps 251 0.93% 89.57% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 89.57% # number of callpals executed +system.cpu1.kern.callpal_wrusp 4 0.01% 89.59% # number of callpals executed +system.cpu1.kern.callpal_rdusp 1 0.00% 89.59% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 89.60% # number of callpals executed +system.cpu1.kern.callpal_rti 2552 9.41% 99.01% # number of callpals executed +system.cpu1.kern.callpal_callsys 208 0.77% 99.78% # number of callpals executed +system.cpu1.kern.callpal_imb 59 0.22% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 35475 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 35069 # number of hwrei instructions executed system.cpu1.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu1.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu1.kern.inst.quiesce 1946 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 26882 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 9636 35.85% 35.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 5504 20.47% 56.32% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 91 0.34% 56.66% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 11651 43.34% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 26602 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 9607 36.11% 36.11% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 5504 20.69% 56.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 91 0.34% 57.15% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 11400 42.85% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3556060349 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3533823708 99.37% 99.37% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 1040434 0.03% 99.40% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 23860 0.00% 99.40% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 21172347 0.60% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.989584 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.996990 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 1947 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 27951 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 10084 36.08% 36.08% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 5485 19.62% 55.70% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 97 0.35% 56.05% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 12285 43.95% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 27484 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 10061 36.61% 36.61% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 5485 19.96% 56.56% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 97 0.35% 56.92% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 11841 43.08% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 3544246744 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 3521927913 99.37% 99.37% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 1037048 0.03% 99.40% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 25211 0.00% 99.40% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 21256572 0.60% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used 0.983292 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_0 0.997719 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.978457 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 691 -system.cpu1.kern.mode_good_user 692 +system.cpu1.kern.ipl_used_31 0.963858 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 636 +system.cpu1.kern.mode_good_user 637 system.cpu1.kern.mode_good_idle 0 -system.cpu1.kern.mode_switch_kernel 3163 # number of protection mode switches -system.cpu1.kern.mode_switch_user 692 # number of protection mode switches +system.cpu1.kern.mode_switch_kernel 3063 # number of protection mode switches +system.cpu1.kern.mode_switch_user 637 # number of protection mode switches system.cpu1.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.358755 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.218463 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good 0.344054 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.207640 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 3554209770 99.95% 99.95% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 1850577 0.05% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_kernel 3542834137 99.96% 99.96% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1412605 0.04% 100.00% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 555 # number of times the context was actually changed -system.cpu1.kern.syscall 163 # number of syscalls executed -system.cpu1.kern.syscall_fork 1 0.61% 0.61% # number of syscalls executed -system.cpu1.kern.syscall_read 13 7.98% 8.59% # number of syscalls executed -system.cpu1.kern.syscall_write 1 0.61% 9.20% # number of syscalls executed -system.cpu1.kern.syscall_close 13 7.98% 17.18% # number of syscalls executed -system.cpu1.kern.syscall_obreak 18 11.04% 28.22% # number of syscalls executed -system.cpu1.kern.syscall_lseek 4 2.45% 30.67% # number of syscalls executed -system.cpu1.kern.syscall_getpid 2 1.23% 31.90% # number of syscalls executed -system.cpu1.kern.syscall_setuid 2 1.23% 33.13% # number of syscalls executed -system.cpu1.kern.syscall_getuid 4 2.45% 35.58% # number of syscalls executed -system.cpu1.kern.syscall_open 28 17.18% 52.76% # number of syscalls executed -system.cpu1.kern.syscall_getgid 4 2.45% 55.21% # number of syscalls executed -system.cpu1.kern.syscall_sigprocmask 2 1.23% 56.44% # number of syscalls executed -system.cpu1.kern.syscall_ioctl 3 1.84% 58.28% # number of syscalls executed -system.cpu1.kern.syscall_readlink 1 0.61% 58.90% # number of syscalls executed -system.cpu1.kern.syscall_execve 1 0.61% 59.51% # number of syscalls executed -system.cpu1.kern.syscall_pre_F64_stat 9 5.52% 65.03% # number of syscalls executed -system.cpu1.kern.syscall_mmap 27 16.56% 81.60% # number of syscalls executed -system.cpu1.kern.syscall_munmap 2 1.23% 82.82% # number of syscalls executed -system.cpu1.kern.syscall_mprotect 7 4.29% 87.12% # number of syscalls executed -system.cpu1.kern.syscall_gethostname 1 0.61% 87.73% # number of syscalls executed -system.cpu1.kern.syscall_dup2 1 0.61% 88.34% # number of syscalls executed -system.cpu1.kern.syscall_pre_F64_fstat 13 7.98% 96.32% # number of syscalls executed -system.cpu1.kern.syscall_fcntl 3 1.84% 98.16% # number of syscalls executed -system.cpu1.kern.syscall_setgid 2 1.23% 99.39% # number of syscalls executed -system.cpu1.kern.syscall_getrlimit 1 0.61% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.002362 # Percentage of non-idle cycles -system.cpu1.numCycles 8398405 # number of cpu cycles simulated -system.cpu1.num_insts 8396147 # Number of instructions executed -system.cpu1.num_refs 2073144 # Number of memory references +system.cpu1.kern.swap_context 516 # number of times the context was actually changed +system.cpu1.kern.syscall 137 # number of syscalls executed +system.cpu1.kern.syscall_fork 1 0.73% 0.73% # number of syscalls executed +system.cpu1.kern.syscall_read 17 12.41% 13.14% # number of syscalls executed +system.cpu1.kern.syscall_close 15 10.95% 24.09% # number of syscalls executed +system.cpu1.kern.syscall_chmod 1 0.73% 24.82% # number of syscalls executed +system.cpu1.kern.syscall_obreak 8 5.84% 30.66% # number of syscalls executed +system.cpu1.kern.syscall_lseek 4 2.92% 33.58% # number of syscalls executed +system.cpu1.kern.syscall_getpid 2 1.46% 35.04% # number of syscalls executed +system.cpu1.kern.syscall_setuid 3 2.19% 37.23% # number of syscalls executed +system.cpu1.kern.syscall_getuid 3 2.19% 39.42% # number of syscalls executed +system.cpu1.kern.syscall_access 4 2.92% 42.34% # number of syscalls executed +system.cpu1.kern.syscall_open 21 15.33% 57.66% # number of syscalls executed +system.cpu1.kern.syscall_getgid 3 2.19% 59.85% # number of syscalls executed +system.cpu1.kern.syscall_sigprocmask 2 1.46% 61.31% # number of syscalls executed +system.cpu1.kern.syscall_ioctl 1 0.73% 62.04% # number of syscalls executed +system.cpu1.kern.syscall_execve 2 1.46% 63.50% # number of syscalls executed +system.cpu1.kern.syscall_mmap 32 23.36% 86.86% # number of syscalls executed +system.cpu1.kern.syscall_munmap 1 0.73% 87.59% # number of syscalls executed +system.cpu1.kern.syscall_mprotect 10 7.30% 94.89% # number of syscalls executed +system.cpu1.kern.syscall_dup2 1 0.73% 95.62% # number of syscalls executed +system.cpu1.kern.syscall_fcntl 2 1.46% 97.08% # number of syscalls executed +system.cpu1.kern.syscall_setgid 3 2.19% 99.27% # number of syscalls executed +system.cpu1.kern.syscall_getrlimit 1 0.73% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.002194 # Percentage of non-idle cycles +system.cpu1.numCycles 7776377 # number of cpu cycles simulated +system.cpu1.num_insts 7774638 # Number of instructions executed +system.cpu1.num_refs 2025195 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2521088 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 285 # Number of full page size DMA writes. -system.disk0.dma_write_txs 375 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2735104 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 306 # Number of full page size DMA writes. +system.disk0.dma_write_txs 412 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout index c8330eef2..039088577 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:32:34 -M5 started Tue Sep 5 15:43:12 2006 +M5 compiled Oct 5 2006 22:13:02 +M5 started Fri Oct 6 00:24:12 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -Exiting @ tick 3556060806 because m5_exit instruction encountered +Exiting @ tick 3544247159 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index c017495f6..e30428078 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -58,6 +58,7 @@ mem_mode=atomic pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh +symbolfile= system_rev=1024 system_type=34 @@ -86,6 +87,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem profile=0 +progress_interval=0 simulate_stalls=false system=system width=1 @@ -554,6 +556,7 @@ pio=system.iobus.port[24] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out index 018308862..ea63dce8b 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out @@ -21,6 +21,7 @@ console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh +symbolfile= init_param=0 system_type=34 system_rev=1024 @@ -86,6 +87,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system itb=system.cpu.itb @@ -465,6 +467,7 @@ bus_id=0 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -508,6 +511,9 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + [pseudo_inst] quiesce=true statistics=true diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console index ea7a20777..d6e3955cc 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console @@ -69,7 +69,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB -
hda: 163296 sectors (83 MB), CHS=162/16/63, UDMA(33) +
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
hda: hda1
hdb: max request size: 128KiB
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) @@ -97,10 +97,6 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 480k freed -
init started: BusyBox v1.00-rc2 (2004.11.18-16:22+0000) multi-call binary - -PTXdist-0.7.0 (2004-11-18T11:23:40-0500) - +
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended -
loading script... +loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt index 3a7dc1cd4..5c403c0a9 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt @@ -1,130 +1,127 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1346129 # Simulator instruction rate (inst/s) -host_mem_usage 194392 # Number of bytes of host memory used -host_seconds 44.52 # Real time elapsed on the host -host_tick_rate 78470813 # Simulator tick rate (ticks/s) +host_inst_rate 1121378 # Simulator instruction rate (inst/s) +host_mem_usage 194272 # Number of bytes of host memory used +host_seconds 51.72 # Real time elapsed on the host +host_tick_rate 67313414 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 59929520 # Number of instructions simulated -sim_seconds 1.746773 # Number of seconds simulated -sim_ticks 3493545624 # Number of ticks simulated -system.cpu.dtb.accesses 2354955 # DTB accesses -system.cpu.dtb.acv 413 # DTB access violations -system.cpu.dtb.hits 13929995 # DTB hits -system.cpu.dtb.misses 16187 # DTB misses -system.cpu.dtb.read_accesses 832415 # DTB read accesses -system.cpu.dtb.read_acv 242 # DTB read access violations -system.cpu.dtb.read_hits 7718636 # DTB read hits -system.cpu.dtb.read_misses 13695 # DTB read misses -system.cpu.dtb.write_accesses 1522540 # DTB write accesses -system.cpu.dtb.write_acv 171 # DTB write access violations -system.cpu.dtb.write_hits 6211359 # DTB write hits -system.cpu.dtb.write_misses 2492 # DTB write misses -system.cpu.idle_fraction 0.982844 # Percentage of idle cycles -system.cpu.itb.accesses 4037380 # ITB accesses -system.cpu.itb.acv 239 # ITB acv -system.cpu.itb.hits 4030656 # ITB hits -system.cpu.itb.misses 6724 # ITB misses -system.cpu.kern.callpal 184022 # number of callpals executed +sim_insts 58001813 # Number of instructions simulated +sim_seconds 1.740863 # Number of seconds simulated +sim_ticks 3481726167 # Number of ticks simulated +system.cpu.dtb.accesses 2309470 # DTB accesses +system.cpu.dtb.acv 367 # DTB access violations +system.cpu.dtb.hits 13711941 # DTB hits +system.cpu.dtb.misses 12493 # DTB misses +system.cpu.dtb.read_accesses 828530 # DTB read accesses +system.cpu.dtb.read_acv 210 # DTB read access violations +system.cpu.dtb.read_hits 7597829 # DTB read hits +system.cpu.dtb.read_misses 10298 # DTB read misses +system.cpu.dtb.write_accesses 1480940 # DTB write accesses +system.cpu.dtb.write_acv 157 # DTB write access violations +system.cpu.dtb.write_hits 6114112 # DTB write hits +system.cpu.dtb.write_misses 2195 # DTB write misses +system.cpu.idle_fraction 0.983340 # Percentage of idle cycles +system.cpu.itb.accesses 3281346 # ITB accesses +system.cpu.itb.acv 184 # ITB acv +system.cpu.itb.hits 3276356 # ITB hits +system.cpu.itb.misses 4990 # ITB misses +system.cpu.kern.callpal 182718 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 1864 1.01% 1.02% # number of callpals executed -system.cpu.kern.callpal_tbi 28 0.02% 1.03% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 1.03% # number of callpals executed -system.cpu.kern.callpal_swpipl 172016 93.48% 94.51% # number of callpals executed -system.cpu.kern.callpal_rdps 4808 2.61% 97.12% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 97.12% # number of callpals executed -system.cpu.kern.callpal_wrusp 8 0.00% 97.13% # number of callpals executed -system.cpu.kern.callpal_rdusp 12 0.01% 97.13% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 97.14% # number of callpals executed -system.cpu.kern.callpal_rti 4291 2.33% 99.47% # number of callpals executed -system.cpu.kern.callpal_callsys 667 0.36% 99.83% # number of callpals executed -system.cpu.kern.callpal_imb 314 0.17% 100.00% # number of callpals executed +system.cpu.kern.callpal_swpctx 1574 0.86% 0.86% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 0.89% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 0.90% # number of callpals executed +system.cpu.kern.callpal_swpipl 171359 93.78% 94.68% # number of callpals executed +system.cpu.kern.callpal_rdps 5159 2.82% 97.50% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 97.50% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 97.51% # number of callpals executed +system.cpu.kern.callpal_rdusp 10 0.01% 97.51% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 97.51% # number of callpals executed +system.cpu.kern.callpal_rti 3829 2.10% 99.61% # number of callpals executed +system.cpu.kern.callpal_callsys 531 0.29% 99.90% # number of callpals executed +system.cpu.kern.callpal_imb 181 0.10% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 209657 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 202783 # number of hwrei instructions executed system.cpu.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu.kern.inst.quiesce 1868 # number of quiesce instructions executed -system.cpu.kern.ipl_count 178378 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75463 42.31% 42.31% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 286 0.16% 42.47% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 5446 3.05% 45.52% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 97183 54.48% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 160188 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 75397 47.07% 47.07% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 286 0.18% 47.25% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 5446 3.40% 50.65% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 79059 49.35% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3493545167 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3471576124 99.37% 99.37% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 45785 0.00% 99.37% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 934362 0.03% 99.40% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 20988896 0.60% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.898026 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.999125 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 1877 # number of quiesce instructions executed +system.cpu.kern.ipl_count 177218 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74624 42.11% 42.11% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 251 0.14% 42.25% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 5425 3.06% 45.31% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 96918 54.69% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 158463 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 74570 47.06% 47.06% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 251 0.16% 47.22% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 5425 3.42% 50.64% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 78217 49.36% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 3481725752 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 3459659082 99.37% 99.37% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 39982 0.00% 99.37% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 930159 0.03% 99.39% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 21096529 0.61% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used 0.894170 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_0 0.999276 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.813506 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 2342 -system.cpu.kern.mode_good_user 2171 -system.cpu.kern.mode_good_idle 171 -system.cpu.kern.mode_switch_kernel 4092 # number of protection mode switches -system.cpu.kern.mode_switch_user 2171 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2041 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.564066 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.572336 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.807043 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1939 +system.cpu.kern.mode_good_user 1757 +system.cpu.kern.mode_good_idle 182 +system.cpu.kern.mode_switch_kernel 3320 # number of protection mode switches +system.cpu.kern.mode_switch_user 1757 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2061 # number of protection mode switches +system.cpu.kern.mode_switch_good 0.543289 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.584036 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.083782 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 33028385 0.95% 0.95% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 4450361 0.13% 1.07% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3456066419 98.93% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 1865 # number of times the context was actually changed -system.cpu.kern.syscall 475 # number of syscalls executed -system.cpu.kern.syscall_fork 10 2.11% 2.11% # number of syscalls executed -system.cpu.kern.syscall_read 33 6.95% 9.05% # number of syscalls executed -system.cpu.kern.syscall_write 7 1.47% 10.53% # number of syscalls executed -system.cpu.kern.syscall_close 49 10.32% 20.84% # number of syscalls executed -system.cpu.kern.syscall_chdir 1 0.21% 21.05% # number of syscalls executed -system.cpu.kern.syscall_chmod 1 0.21% 21.26% # number of syscalls executed -system.cpu.kern.syscall_obreak 44 9.26% 30.53% # number of syscalls executed -system.cpu.kern.syscall_lseek 13 2.74% 33.26% # number of syscalls executed -system.cpu.kern.syscall_getpid 10 2.11% 35.37% # number of syscalls executed -system.cpu.kern.syscall_setuid 4 0.84% 36.21% # number of syscalls executed -system.cpu.kern.syscall_getuid 8 1.68% 37.89% # number of syscalls executed -system.cpu.kern.syscall_access 4 0.84% 38.74% # number of syscalls executed -system.cpu.kern.syscall_dup 4 0.84% 39.58% # number of syscalls executed -system.cpu.kern.syscall_open 68 14.32% 53.89% # number of syscalls executed -system.cpu.kern.syscall_getgid 8 1.68% 55.58% # number of syscalls executed -system.cpu.kern.syscall_sigprocmask 14 2.95% 58.53% # number of syscalls executed -system.cpu.kern.syscall_ioctl 16 3.37% 61.89% # number of syscalls executed -system.cpu.kern.syscall_readlink 2 0.42% 62.32% # number of syscalls executed -system.cpu.kern.syscall_execve 8 1.68% 64.00% # number of syscalls executed -system.cpu.kern.syscall_pre_F64_stat 31 6.53% 70.53% # number of syscalls executed -system.cpu.kern.syscall_pre_F64_lstat 1 0.21% 70.74% # number of syscalls executed -system.cpu.kern.syscall_mmap 55 11.58% 82.32% # number of syscalls executed -system.cpu.kern.syscall_munmap 6 1.26% 83.58% # number of syscalls executed -system.cpu.kern.syscall_mprotect 14 2.95% 86.53% # number of syscalls executed -system.cpu.kern.syscall_gethostname 2 0.42% 86.95% # number of syscalls executed -system.cpu.kern.syscall_dup2 4 0.84% 87.79% # number of syscalls executed -system.cpu.kern.syscall_pre_F64_fstat 28 5.89% 93.68% # number of syscalls executed -system.cpu.kern.syscall_fcntl 14 2.95% 96.63% # number of syscalls executed -system.cpu.kern.syscall_socket 3 0.63% 97.26% # number of syscalls executed -system.cpu.kern.syscall_connect 3 0.63% 97.89% # number of syscalls executed -system.cpu.kern.syscall_setgid 4 0.84% 98.74% # number of syscalls executed -system.cpu.kern.syscall_getrlimit 3 0.63% 99.37% # number of syscalls executed -system.cpu.kern.syscall_setsid 3 0.63% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.017156 # Percentage of non-idle cycles -system.cpu.numCycles 59936483 # number of cpu cycles simulated -system.cpu.num_insts 59929520 # Number of instructions executed -system.cpu.num_refs 13982880 # Number of memory references +system.cpu.kern.mode_switch_good_idle 0.088307 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 31887159 0.92% 0.92% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 3591270 0.10% 1.02% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 3446247321 98.98% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 1575 # number of times the context was actually changed +system.cpu.kern.syscall 329 # number of syscalls executed +system.cpu.kern.syscall_fork 8 2.43% 2.43% # number of syscalls executed +system.cpu.kern.syscall_read 30 9.12% 11.55% # number of syscalls executed +system.cpu.kern.syscall_write 4 1.22% 12.77% # number of syscalls executed +system.cpu.kern.syscall_close 43 13.07% 25.84% # number of syscalls executed +system.cpu.kern.syscall_chdir 1 0.30% 26.14% # number of syscalls executed +system.cpu.kern.syscall_chmod 1 0.30% 26.44% # number of syscalls executed +system.cpu.kern.syscall_obreak 15 4.56% 31.00% # number of syscalls executed +system.cpu.kern.syscall_lseek 10 3.04% 34.04% # number of syscalls executed +system.cpu.kern.syscall_getpid 6 1.82% 35.87% # number of syscalls executed +system.cpu.kern.syscall_setuid 4 1.22% 37.08% # number of syscalls executed +system.cpu.kern.syscall_getuid 6 1.82% 38.91% # number of syscalls executed +system.cpu.kern.syscall_access 11 3.34% 42.25% # number of syscalls executed +system.cpu.kern.syscall_dup 2 0.61% 42.86% # number of syscalls executed +system.cpu.kern.syscall_open 55 16.72% 59.57% # number of syscalls executed +system.cpu.kern.syscall_getgid 6 1.82% 61.40% # number of syscalls executed +system.cpu.kern.syscall_sigprocmask 10 3.04% 64.44% # number of syscalls executed +system.cpu.kern.syscall_ioctl 10 3.04% 67.48% # number of syscalls executed +system.cpu.kern.syscall_readlink 1 0.30% 67.78% # number of syscalls executed +system.cpu.kern.syscall_execve 7 2.13% 69.91% # number of syscalls executed +system.cpu.kern.syscall_mmap 54 16.41% 86.32% # number of syscalls executed +system.cpu.kern.syscall_munmap 3 0.91% 87.23% # number of syscalls executed +system.cpu.kern.syscall_mprotect 16 4.86% 92.10% # number of syscalls executed +system.cpu.kern.syscall_gethostname 1 0.30% 92.40% # number of syscalls executed +system.cpu.kern.syscall_dup2 3 0.91% 93.31% # number of syscalls executed +system.cpu.kern.syscall_fcntl 10 3.04% 96.35% # number of syscalls executed +system.cpu.kern.syscall_socket 2 0.61% 96.96% # number of syscalls executed +system.cpu.kern.syscall_connect 2 0.61% 97.57% # number of syscalls executed +system.cpu.kern.syscall_setgid 4 1.22% 98.78% # number of syscalls executed +system.cpu.kern.syscall_getrlimit 2 0.61% 99.39% # number of syscalls executed +system.cpu.kern.syscall_setsid 2 0.61% 100.00% # number of syscalls executed +system.cpu.not_idle_fraction 0.016660 # Percentage of non-idle cycles +system.cpu.numCycles 58006987 # number of cpu cycles simulated +system.cpu.num_insts 58001813 # Number of instructions executed +system.cpu.num_refs 13757191 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2521088 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 285 # Number of full page size DMA writes. -system.disk0.dma_write_txs 375 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2735104 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 306 # Number of full page size DMA writes. +system.disk0.dma_write_txs 412 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout index c04cd5050..b3b3e8704 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:32:34 -M5 started Tue Sep 5 15:42:26 2006 +M5 compiled Oct 5 2006 22:13:02 +M5 started Fri Oct 6 00:23:19 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -Exiting @ tick 3493545624 because m5_exit instruction encountered +Exiting @ tick 3481726167 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 97e9007e7..65401b549 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -58,6 +58,7 @@ mem_mode=timing pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh +symbolfile= system_rev=1024 system_type=34 @@ -86,6 +87,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem profile=0 +progress_interval=0 system=system dcache_port=system.membus.port[3] icache_port=system.membus.port[2] @@ -114,6 +116,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem profile=0 +progress_interval=0 system=system dcache_port=system.membus.port[5] icache_port=system.membus.port[4] @@ -580,6 +583,7 @@ pio=system.iobus.port[24] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out index 96c734e15..ed03e445d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out @@ -21,6 +21,7 @@ console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh +symbolfile= init_param=0 system_type=34 system_rev=1024 @@ -86,6 +87,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system itb=system.cpu0.itb @@ -113,6 +115,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system itb=system.cpu1.itb @@ -492,6 +495,7 @@ bus_id=0 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -535,6 +539,9 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + [pseudo_inst] quiesce=true statistics=true diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console index c3c7b2676..4a397ddbf 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console @@ -74,7 +74,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB -
hda: 163296 sectors (83 MB), CHS=162/16/63, UDMA(33) +
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
hda: hda1
hdb: max request size: 128KiB
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) @@ -102,10 +102,6 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 480k freed -
init started: BusyBox v1.00-rc2 (2004.11.18-16:22+0000) multi-call binary - -PTXdist-0.7.0 (2004-11-18T11:23:40-0500) - +
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended -
loading script... +loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 666766e20..bf7320067 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,239 +1,232 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 804715 # Simulator instruction rate (inst/s) -host_mem_usage 194628 # Number of bytes of host memory used -host_seconds 78.40 # Real time elapsed on the host -host_tick_rate 45146741 # Simulator tick rate (ticks/s) +host_inst_rate 825990 # Simulator instruction rate (inst/s) +host_mem_usage 193572 # Number of bytes of host memory used +host_seconds 74.01 # Real time elapsed on the host +host_tick_rate 47654938 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 63088076 # Number of instructions simulated -sim_seconds 1.769718 # Number of seconds simulated -sim_ticks 3539435029 # Number of ticks simulated -system.cpu0.dtb.accesses 1831687 # DTB accesses -system.cpu0.dtb.acv 360 # DTB access violations -system.cpu0.dtb.hits 10286150 # DTB hits -system.cpu0.dtb.misses 11050 # DTB misses -system.cpu0.dtb.read_accesses 495437 # DTB read accesses -system.cpu0.dtb.read_acv 219 # DTB read access violations -system.cpu0.dtb.read_hits 5741423 # DTB read hits -system.cpu0.dtb.read_misses 9036 # DTB read misses -system.cpu0.dtb.write_accesses 1336250 # DTB write accesses -system.cpu0.dtb.write_acv 141 # DTB write access violations -system.cpu0.dtb.write_hits 4544727 # DTB write hits -system.cpu0.dtb.write_misses 2014 # DTB write misses -system.cpu0.idle_fraction 0.984526 # Percentage of idle cycles -system.cpu0.itb.accesses 2328068 # ITB accesses -system.cpu0.itb.acv 216 # ITB acv -system.cpu0.itb.hits 2323500 # ITB hits -system.cpu0.itb.misses 4568 # ITB misses -system.cpu0.kern.callpal 145575 # number of callpals executed +sim_insts 61131962 # Number of instructions simulated +sim_seconds 1.763494 # Number of seconds simulated +sim_ticks 3526987181 # Number of ticks simulated +system.cpu0.dtb.accesses 1987164 # DTB accesses +system.cpu0.dtb.acv 291 # DTB access violations +system.cpu0.dtb.hits 10431590 # DTB hits +system.cpu0.dtb.misses 9590 # DTB misses +system.cpu0.dtb.read_accesses 606328 # DTB read accesses +system.cpu0.dtb.read_acv 174 # DTB read access violations +system.cpu0.dtb.read_hits 5831565 # DTB read hits +system.cpu0.dtb.read_misses 7663 # DTB read misses +system.cpu0.dtb.write_accesses 1380836 # DTB write accesses +system.cpu0.dtb.write_acv 117 # DTB write access violations +system.cpu0.dtb.write_hits 4600025 # DTB write hits +system.cpu0.dtb.write_misses 1927 # DTB write misses +system.cpu0.idle_fraction 0.984514 # Percentage of idle cycles +system.cpu0.itb.accesses 2372045 # ITB accesses +system.cpu0.itb.acv 143 # ITB acv +system.cpu0.itb.hits 2368331 # ITB hits +system.cpu0.itb.misses 3714 # ITB misses +system.cpu0.kern.callpal 145084 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal_wripir 45 0.03% 0.03% # number of callpals executed -system.cpu0.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu0.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.03% # number of callpals executed -system.cpu0.kern.callpal_swpctx 1334 0.92% 0.95% # number of callpals executed -system.cpu0.kern.callpal_tbi 20 0.01% 0.96% # number of callpals executed -system.cpu0.kern.callpal_wrent 7 0.00% 0.97% # number of callpals executed -system.cpu0.kern.callpal_swpipl 135235 92.90% 93.87% # number of callpals executed -system.cpu0.kern.callpal_rdps 4594 3.16% 97.02% # number of callpals executed -system.cpu0.kern.callpal_wrkgp 1 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal_wrusp 4 0.00% 97.02% # number of callpals executed -system.cpu0.kern.callpal_rdusp 11 0.01% 97.03% # number of callpals executed -system.cpu0.kern.callpal_whami 2 0.00% 97.03% # number of callpals executed -system.cpu0.kern.callpal_rti 3660 2.51% 99.55% # number of callpals executed -system.cpu0.kern.callpal_callsys 461 0.32% 99.86% # number of callpals executed -system.cpu0.kern.callpal_imb 197 0.14% 100.00% # number of callpals executed +system.cpu0.kern.callpal_wripir 54 0.04% 0.04% # number of callpals executed +system.cpu0.kern.callpal_wrmces 1 0.00% 0.04% # number of callpals executed +system.cpu0.kern.callpal_wrfen 1 0.00% 0.04% # number of callpals executed +system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.04% # number of callpals executed +system.cpu0.kern.callpal_swpctx 1182 0.81% 0.85% # number of callpals executed +system.cpu0.kern.callpal_tbi 42 0.03% 0.88% # number of callpals executed +system.cpu0.kern.callpal_wrent 7 0.00% 0.89% # number of callpals executed +system.cpu0.kern.callpal_swpipl 135050 93.08% 93.97% # number of callpals executed +system.cpu0.kern.callpal_rdps 4795 3.30% 97.28% # number of callpals executed +system.cpu0.kern.callpal_wrkgp 1 0.00% 97.28% # number of callpals executed +system.cpu0.kern.callpal_wrusp 5 0.00% 97.28% # number of callpals executed +system.cpu0.kern.callpal_rdusp 8 0.01% 97.29% # number of callpals executed +system.cpu0.kern.callpal_whami 2 0.00% 97.29% # number of callpals executed +system.cpu0.kern.callpal_rti 3431 2.36% 99.65% # number of callpals executed +system.cpu0.kern.callpal_callsys 364 0.25% 99.90% # number of callpals executed +system.cpu0.kern.callpal_imb 139 0.10% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 163916 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 160926 # number of hwrei instructions executed system.cpu0.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu0.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu0.kern.inst.quiesce 1952 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 141041 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 56950 40.38% 40.38% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_21 286 0.20% 40.58% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_22 5513 3.91% 44.49% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_30 52 0.04% 44.53% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 78240 55.47% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 123339 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 56917 46.15% 46.15% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_21 286 0.23% 46.38% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_22 5513 4.47% 50.85% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_30 52 0.04% 50.89% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 60571 49.11% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks 3539063979 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3513499166 99.28% 99.28% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_21 60705 0.00% 99.28% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 1354114 0.04% 99.32% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 18748 0.00% 99.32% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 24131246 0.68% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.874490 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.999421 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 1958 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 140584 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 56549 40.22% 40.22% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_21 251 0.18% 40.40% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_22 5487 3.90% 44.31% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_30 51 0.04% 44.34% # number of times we switched to this ipl +system.cpu0.kern.ipl_count_31 78246 55.66% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 122461 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 56518 46.15% 46.15% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_21 251 0.20% 46.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_22 5487 4.48% 50.84% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_30 51 0.04% 50.88% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 60154 49.12% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks 3526986735 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 3501352281 99.27% 99.27% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_21 53019 0.00% 99.27% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_22 1348211 0.04% 99.31% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 18326 0.00% 99.31% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 24214898 0.69% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used 0.871088 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_0 0.999452 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.774169 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1632 -system.cpu0.kern.mode_good_user 1487 -system.cpu0.kern.mode_good_idle 145 -system.cpu0.kern.mode_switch_kernel 2857 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1487 # number of protection mode switches -system.cpu0.kern.mode_switch_idle 2125 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.504560 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.571229 # fraction of useful protection mode switches +system.cpu0.kern.ipl_used_31 0.768781 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1448 +system.cpu0.kern.mode_good_user 1300 +system.cpu0.kern.mode_good_idle 148 +system.cpu0.kern.mode_switch_kernel 2490 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1300 # number of protection mode switches +system.cpu0.kern.mode_switch_idle 2110 # number of protection mode switches +system.cpu0.kern.mode_switch_good 0.490847 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.581526 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_idle 0.068235 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 23634401 0.67% 0.67% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 3241731 0.09% 0.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_idle 3511854943 99.24% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 1335 # number of times the context was actually changed -system.cpu0.kern.syscall 312 # number of syscalls executed -system.cpu0.kern.syscall_fork 9 2.88% 2.88% # number of syscalls executed -system.cpu0.kern.syscall_read 20 6.41% 9.29% # number of syscalls executed -system.cpu0.kern.syscall_write 6 1.92% 11.22% # number of syscalls executed -system.cpu0.kern.syscall_close 36 11.54% 22.76% # number of syscalls executed -system.cpu0.kern.syscall_chdir 1 0.32% 23.08% # number of syscalls executed -system.cpu0.kern.syscall_chmod 1 0.32% 23.40% # number of syscalls executed -system.cpu0.kern.syscall_obreak 26 8.33% 31.73% # number of syscalls executed -system.cpu0.kern.syscall_lseek 9 2.88% 34.62% # number of syscalls executed -system.cpu0.kern.syscall_getpid 8 2.56% 37.18% # number of syscalls executed -system.cpu0.kern.syscall_setuid 2 0.64% 37.82% # number of syscalls executed -system.cpu0.kern.syscall_getuid 4 1.28% 39.10% # number of syscalls executed -system.cpu0.kern.syscall_access 4 1.28% 40.38% # number of syscalls executed -system.cpu0.kern.syscall_dup 4 1.28% 41.67% # number of syscalls executed -system.cpu0.kern.syscall_open 40 12.82% 54.49% # number of syscalls executed -system.cpu0.kern.syscall_getgid 4 1.28% 55.77% # number of syscalls executed -system.cpu0.kern.syscall_sigprocmask 12 3.85% 59.62% # number of syscalls executed -system.cpu0.kern.syscall_ioctl 13 4.17% 63.78% # number of syscalls executed -system.cpu0.kern.syscall_readlink 1 0.32% 64.10% # number of syscalls executed -system.cpu0.kern.syscall_execve 7 2.24% 66.35% # number of syscalls executed -system.cpu0.kern.syscall_pre_F64_stat 22 7.05% 73.40% # number of syscalls executed -system.cpu0.kern.syscall_pre_F64_lstat 1 0.32% 73.72% # number of syscalls executed -system.cpu0.kern.syscall_mmap 28 8.97% 82.69% # number of syscalls executed -system.cpu0.kern.syscall_munmap 4 1.28% 83.97% # number of syscalls executed -system.cpu0.kern.syscall_mprotect 7 2.24% 86.22% # number of syscalls executed -system.cpu0.kern.syscall_gethostname 1 0.32% 86.54% # number of syscalls executed -system.cpu0.kern.syscall_dup2 3 0.96% 87.50% # number of syscalls executed -system.cpu0.kern.syscall_pre_F64_fstat 15 4.81% 92.31% # number of syscalls executed -system.cpu0.kern.syscall_fcntl 11 3.53% 95.83% # number of syscalls executed -system.cpu0.kern.syscall_socket 3 0.96% 96.79% # number of syscalls executed -system.cpu0.kern.syscall_connect 3 0.96% 97.76% # number of syscalls executed -system.cpu0.kern.syscall_setgid 2 0.64% 98.40% # number of syscalls executed -system.cpu0.kern.syscall_getrlimit 2 0.64% 99.04% # number of syscalls executed -system.cpu0.kern.syscall_setsid 3 0.96% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.015474 # Percentage of non-idle cycles +system.cpu0.kern.mode_switch_good_idle 0.070142 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks_kernel 23256451 0.66% 0.66% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 3397192 0.10% 0.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_idle 3500333090 99.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 1183 # number of times the context was actually changed +system.cpu0.kern.syscall 231 # number of syscalls executed +system.cpu0.kern.syscall_fork 6 2.60% 2.60% # number of syscalls executed +system.cpu0.kern.syscall_read 17 7.36% 9.96% # number of syscalls executed +system.cpu0.kern.syscall_write 4 1.73% 11.69% # number of syscalls executed +system.cpu0.kern.syscall_close 31 13.42% 25.11% # number of syscalls executed +system.cpu0.kern.syscall_chdir 1 0.43% 25.54% # number of syscalls executed +system.cpu0.kern.syscall_obreak 11 4.76% 30.30% # number of syscalls executed +system.cpu0.kern.syscall_lseek 6 2.60% 32.90% # number of syscalls executed +system.cpu0.kern.syscall_getpid 4 1.73% 34.63% # number of syscalls executed +system.cpu0.kern.syscall_setuid 2 0.87% 35.50% # number of syscalls executed +system.cpu0.kern.syscall_getuid 4 1.73% 37.23% # number of syscalls executed +system.cpu0.kern.syscall_access 9 3.90% 41.13% # number of syscalls executed +system.cpu0.kern.syscall_dup 2 0.87% 41.99% # number of syscalls executed +system.cpu0.kern.syscall_open 42 18.18% 60.17% # number of syscalls executed +system.cpu0.kern.syscall_getgid 4 1.73% 61.90% # number of syscalls executed +system.cpu0.kern.syscall_sigprocmask 7 3.03% 64.94% # number of syscalls executed +system.cpu0.kern.syscall_ioctl 9 3.90% 68.83% # number of syscalls executed +system.cpu0.kern.syscall_readlink 1 0.43% 69.26% # number of syscalls executed +system.cpu0.kern.syscall_execve 4 1.73% 71.00% # number of syscalls executed +system.cpu0.kern.syscall_mmap 35 15.15% 86.15% # number of syscalls executed +system.cpu0.kern.syscall_munmap 2 0.87% 87.01% # number of syscalls executed +system.cpu0.kern.syscall_mprotect 10 4.33% 91.34% # number of syscalls executed +system.cpu0.kern.syscall_gethostname 1 0.43% 91.77% # number of syscalls executed +system.cpu0.kern.syscall_dup2 2 0.87% 92.64% # number of syscalls executed +system.cpu0.kern.syscall_fcntl 8 3.46% 96.10% # number of syscalls executed +system.cpu0.kern.syscall_socket 2 0.87% 96.97% # number of syscalls executed +system.cpu0.kern.syscall_connect 2 0.87% 97.84% # number of syscalls executed +system.cpu0.kern.syscall_setgid 2 0.87% 98.70% # number of syscalls executed +system.cpu0.kern.syscall_getrlimit 1 0.43% 99.13% # number of syscalls executed +system.cpu0.kern.syscall_setsid 2 0.87% 100.00% # number of syscalls executed +system.cpu0.not_idle_fraction 0.015486 # Percentage of non-idle cycles system.cpu0.numCycles 0 # number of cpu cycles simulated -system.cpu0.num_insts 44447414 # Number of instructions executed -system.cpu0.num_refs 10321518 # Number of memory references -system.cpu1.dtb.accesses 524398 # DTB accesses -system.cpu1.dtb.acv 60 # DTB access violations -system.cpu1.dtb.hits 4612716 # DTB hits -system.cpu1.dtb.misses 5263 # DTB misses -system.cpu1.dtb.read_accesses 337746 # DTB read accesses -system.cpu1.dtb.read_acv 23 # DTB read access violations -system.cpu1.dtb.read_hits 2649302 # DTB read hits -system.cpu1.dtb.read_misses 4766 # DTB read misses -system.cpu1.dtb.write_accesses 186652 # DTB write accesses -system.cpu1.dtb.write_acv 37 # DTB write access violations -system.cpu1.dtb.write_hits 1963414 # DTB write hits -system.cpu1.dtb.write_misses 497 # DTB write misses -system.cpu1.idle_fraction 0.993423 # Percentage of idle cycles -system.cpu1.itb.accesses 1711918 # ITB accesses -system.cpu1.itb.acv 23 # ITB acv -system.cpu1.itb.hits 1709683 # ITB hits -system.cpu1.itb.misses 2235 # ITB misses -system.cpu1.kern.callpal 58341 # number of callpals executed +system.cpu0.num_insts 44155958 # Number of instructions executed +system.cpu0.num_refs 10463340 # Number of memory references +system.cpu1.dtb.accesses 323344 # DTB accesses +system.cpu1.dtb.acv 82 # DTB access violations +system.cpu1.dtb.hits 4234985 # DTB hits +system.cpu1.dtb.misses 2977 # DTB misses +system.cpu1.dtb.read_accesses 222873 # DTB read accesses +system.cpu1.dtb.read_acv 36 # DTB read access violations +system.cpu1.dtb.read_hits 2431648 # DTB read hits +system.cpu1.dtb.read_misses 2698 # DTB read misses +system.cpu1.dtb.write_accesses 100471 # DTB write accesses +system.cpu1.dtb.write_acv 46 # DTB write access violations +system.cpu1.dtb.write_hits 1803337 # DTB write hits +system.cpu1.dtb.write_misses 279 # DTB write misses +system.cpu1.idle_fraction 0.993979 # Percentage of idle cycles +system.cpu1.itb.accesses 912010 # ITB accesses +system.cpu1.itb.acv 41 # ITB acv +system.cpu1.itb.hits 910678 # ITB hits +system.cpu1.itb.misses 1332 # ITB misses +system.cpu1.kern.callpal 57529 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal_wripir 52 0.09% 0.09% # number of callpals executed +system.cpu1.kern.callpal_wripir 51 0.09% 0.09% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.09% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.09% # number of callpals executed -system.cpu1.kern.callpal_swpctx 588 1.01% 1.10% # number of callpals executed -system.cpu1.kern.callpal_tbi 7 0.01% 1.11% # number of callpals executed -system.cpu1.kern.callpal_wrent 7 0.01% 1.13% # number of callpals executed -system.cpu1.kern.callpal_swpipl 54562 93.52% 94.65% # number of callpals executed -system.cpu1.kern.callpal_rdps 217 0.37% 95.02% # number of callpals executed -system.cpu1.kern.callpal_wrkgp 1 0.00% 95.02% # number of callpals executed -system.cpu1.kern.callpal_wrusp 4 0.01% 95.03% # number of callpals executed -system.cpu1.kern.callpal_rdusp 1 0.00% 95.03% # number of callpals executed -system.cpu1.kern.callpal_whami 3 0.01% 95.04% # number of callpals executed -system.cpu1.kern.callpal_rti 2571 4.41% 99.44% # number of callpals executed -system.cpu1.kern.callpal_callsys 208 0.36% 99.80% # number of callpals executed -system.cpu1.kern.callpal_imb 116 0.20% 100.00% # number of callpals executed +system.cpu1.kern.callpal_swpctx 451 0.78% 0.88% # number of callpals executed +system.cpu1.kern.callpal_tbi 12 0.02% 0.90% # number of callpals executed +system.cpu1.kern.callpal_wrent 7 0.01% 0.91% # number of callpals executed +system.cpu1.kern.callpal_swpipl 54081 94.01% 94.92% # number of callpals executed +system.cpu1.kern.callpal_rdps 368 0.64% 95.56% # number of callpals executed +system.cpu1.kern.callpal_wrkgp 1 0.00% 95.56% # number of callpals executed +system.cpu1.kern.callpal_wrusp 2 0.00% 95.56% # number of callpals executed +system.cpu1.kern.callpal_rdusp 2 0.00% 95.57% # number of callpals executed +system.cpu1.kern.callpal_whami 3 0.01% 95.57% # number of callpals executed +system.cpu1.kern.callpal_rti 2337 4.06% 99.63% # number of callpals executed +system.cpu1.kern.callpal_callsys 169 0.29% 99.93% # number of callpals executed +system.cpu1.kern.callpal_imb 41 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 67770 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 63811 # number of hwrei instructions executed system.cpu1.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu1.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu1.kern.inst.quiesce 1892 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 58980 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 25467 43.18% 43.18% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_22 5476 9.28% 52.46% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_30 45 0.08% 52.54% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 27992 47.46% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 58199 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 25424 43.68% 43.68% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_22 5476 9.41% 53.09% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_30 45 0.08% 53.17% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 27254 46.83% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3539434499 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3510645847 99.19% 99.19% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 1415637 0.04% 99.23% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_30 16792 0.00% 99.23% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 27356223 0.77% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.986758 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.998312 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 1898 # number of quiesce instructions executed +system.cpu1.kern.ipl_count 58267 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 25040 42.97% 42.97% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_22 5452 9.36% 52.33% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_30 54 0.09% 52.42% # number of times we switched to this ipl +system.cpu1.kern.ipl_count_31 27721 47.58% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 57331 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 25007 43.62% 43.62% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_22 5452 9.51% 53.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_30 54 0.09% 53.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_31 26818 46.78% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 3526422675 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 3497592433 99.18% 99.18% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 1410084 0.04% 99.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_30 19740 0.00% 99.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_31 27400418 0.78% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used 0.983936 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_0 0.998682 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.973635 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good_kernel 690 -system.cpu1.kern.mode_good_user 691 +system.cpu1.kern.ipl_used_31 0.967425 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good_kernel 465 +system.cpu1.kern.mode_good_user 465 system.cpu1.kern.mode_good_idle 0 -system.cpu1.kern.mode_switch_kernel 3141 # number of protection mode switches -system.cpu1.kern.mode_switch_user 691 # number of protection mode switches +system.cpu1.kern.mode_switch_kernel 2771 # number of protection mode switches +system.cpu1.kern.mode_switch_user 465 # number of protection mode switches system.cpu1.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu1.kern.mode_switch_good 0.360386 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_kernel 0.219675 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good 0.287392 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good_kernel 0.167809 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 3537141786 99.94% 99.94% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 2292711 0.06% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good_idle no value # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks_kernel 3525066043 99.96% 99.96% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 1294184 0.04% 100.00% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 589 # number of times the context was actually changed -system.cpu1.kern.syscall 163 # number of syscalls executed -system.cpu1.kern.syscall_fork 1 0.61% 0.61% # number of syscalls executed -system.cpu1.kern.syscall_read 13 7.98% 8.59% # number of syscalls executed -system.cpu1.kern.syscall_write 1 0.61% 9.20% # number of syscalls executed -system.cpu1.kern.syscall_close 13 7.98% 17.18% # number of syscalls executed -system.cpu1.kern.syscall_obreak 18 11.04% 28.22% # number of syscalls executed -system.cpu1.kern.syscall_lseek 4 2.45% 30.67% # number of syscalls executed -system.cpu1.kern.syscall_getpid 2 1.23% 31.90% # number of syscalls executed -system.cpu1.kern.syscall_setuid 2 1.23% 33.13% # number of syscalls executed -system.cpu1.kern.syscall_getuid 4 2.45% 35.58% # number of syscalls executed -system.cpu1.kern.syscall_open 28 17.18% 52.76% # number of syscalls executed -system.cpu1.kern.syscall_getgid 4 2.45% 55.21% # number of syscalls executed -system.cpu1.kern.syscall_sigprocmask 2 1.23% 56.44% # number of syscalls executed -system.cpu1.kern.syscall_ioctl 3 1.84% 58.28% # number of syscalls executed -system.cpu1.kern.syscall_readlink 1 0.61% 58.90% # number of syscalls executed -system.cpu1.kern.syscall_execve 1 0.61% 59.51% # number of syscalls executed -system.cpu1.kern.syscall_pre_F64_stat 9 5.52% 65.03% # number of syscalls executed -system.cpu1.kern.syscall_mmap 27 16.56% 81.60% # number of syscalls executed -system.cpu1.kern.syscall_munmap 2 1.23% 82.82% # number of syscalls executed -system.cpu1.kern.syscall_mprotect 7 4.29% 87.12% # number of syscalls executed -system.cpu1.kern.syscall_gethostname 1 0.61% 87.73% # number of syscalls executed -system.cpu1.kern.syscall_dup2 1 0.61% 88.34% # number of syscalls executed -system.cpu1.kern.syscall_pre_F64_fstat 13 7.98% 96.32% # number of syscalls executed -system.cpu1.kern.syscall_fcntl 3 1.84% 98.16% # number of syscalls executed -system.cpu1.kern.syscall_setgid 2 1.23% 99.39% # number of syscalls executed -system.cpu1.kern.syscall_getrlimit 1 0.61% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.006577 # Percentage of non-idle cycles +system.cpu1.kern.swap_context 452 # number of times the context was actually changed +system.cpu1.kern.syscall 98 # number of syscalls executed +system.cpu1.kern.syscall_fork 2 2.04% 2.04% # number of syscalls executed +system.cpu1.kern.syscall_read 13 13.27% 15.31% # number of syscalls executed +system.cpu1.kern.syscall_close 12 12.24% 27.55% # number of syscalls executed +system.cpu1.kern.syscall_chmod 1 1.02% 28.57% # number of syscalls executed +system.cpu1.kern.syscall_obreak 4 4.08% 32.65% # number of syscalls executed +system.cpu1.kern.syscall_lseek 4 4.08% 36.73% # number of syscalls executed +system.cpu1.kern.syscall_getpid 2 2.04% 38.78% # number of syscalls executed +system.cpu1.kern.syscall_setuid 2 2.04% 40.82% # number of syscalls executed +system.cpu1.kern.syscall_getuid 2 2.04% 42.86% # number of syscalls executed +system.cpu1.kern.syscall_access 2 2.04% 44.90% # number of syscalls executed +system.cpu1.kern.syscall_open 13 13.27% 58.16% # number of syscalls executed +system.cpu1.kern.syscall_getgid 2 2.04% 60.20% # number of syscalls executed +system.cpu1.kern.syscall_sigprocmask 3 3.06% 63.27% # number of syscalls executed +system.cpu1.kern.syscall_ioctl 1 1.02% 64.29% # number of syscalls executed +system.cpu1.kern.syscall_execve 3 3.06% 67.35% # number of syscalls executed +system.cpu1.kern.syscall_mmap 19 19.39% 86.73% # number of syscalls executed +system.cpu1.kern.syscall_munmap 1 1.02% 87.76% # number of syscalls executed +system.cpu1.kern.syscall_mprotect 6 6.12% 93.88% # number of syscalls executed +system.cpu1.kern.syscall_dup2 1 1.02% 94.90% # number of syscalls executed +system.cpu1.kern.syscall_fcntl 2 2.04% 96.94% # number of syscalls executed +system.cpu1.kern.syscall_setgid 2 2.04% 98.98% # number of syscalls executed +system.cpu1.kern.syscall_getrlimit 1 1.02% 100.00% # number of syscalls executed +system.cpu1.not_idle_fraction 0.006021 # Percentage of non-idle cycles system.cpu1.numCycles 0 # number of cpu cycles simulated -system.cpu1.num_insts 18640662 # Number of instructions executed -system.cpu1.num_refs 4633112 # Number of memory references +system.cpu1.num_insts 16976004 # Number of instructions executed +system.cpu1.num_refs 4251312 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2521088 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 285 # Number of full page size DMA writes. -system.disk0.dma_write_txs 375 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2735104 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 306 # Number of full page size DMA writes. +system.disk0.dma_write_txs 412 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout index 33c194686..2c496b914 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:32:34 -M5 started Tue Sep 5 15:45:11 2006 +M5 compiled Oct 5 2006 22:13:02 +M5 started Fri Oct 6 00:26:09 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -Exiting @ tick 3539435029 because m5_exit instruction encountered +Exiting @ tick 3526987181 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 2a354dee0..7f27ca121 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -58,6 +58,7 @@ mem_mode=timing pal=/dist/m5/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh +symbolfile= system_rev=1024 system_type=34 @@ -86,6 +87,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem profile=0 +progress_interval=0 system=system dcache_port=system.membus.port[3] icache_port=system.membus.port[2] @@ -552,6 +554,7 @@ pio=system.iobus.port[24] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out index 1b99934c9..deba80368 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out @@ -21,6 +21,7 @@ console=/dist/m5/system/binaries/console pal=/dist/m5/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh +symbolfile= init_param=0 system_type=34 system_rev=1024 @@ -86,6 +87,7 @@ max_insts_any_thread=0 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system itb=system.cpu.itb @@ -465,6 +467,7 @@ bus_id=0 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -508,6 +511,9 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + [pseudo_inst] quiesce=true statistics=true diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console index ea7a20777..d6e3955cc 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console @@ -69,7 +69,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
hdb: M5 IDE Disk, ATA DISK drive
ide0 at 0x8410-0x8417,0x8422 on irq 31
hda: max request size: 128KiB -
hda: 163296 sectors (83 MB), CHS=162/16/63, UDMA(33) +
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
hda: hda1
hdb: max request size: 128KiB
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) @@ -97,10 +97,6 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
All bugs added by David S. Miller <davem@redhat.com>
VFS: Mounted root (ext2 filesystem) readonly.
Freeing unused kernel memory: 480k freed -
init started: BusyBox v1.00-rc2 (2004.11.18-16:22+0000) multi-call binary - -PTXdist-0.7.0 (2004-11-18T11:23:40-0500) - +
init started: BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended -
loading script... +loading script... diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 0adb4cc31..1d45d41a9 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,130 +1,127 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 835908 # Simulator instruction rate (inst/s) -host_mem_usage 194192 # Number of bytes of host memory used -host_seconds 71.68 # Real time elapsed on the host -host_tick_rate 48916813 # Simulator tick rate (ticks/s) +host_inst_rate 820839 # Simulator instruction rate (inst/s) +host_mem_usage 193264 # Number of bytes of host memory used +host_seconds 70.65 # Real time elapsed on the host +host_tick_rate 49454399 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 59915182 # Number of instructions simulated -sim_seconds 1.753109 # Number of seconds simulated -sim_ticks 3506218170 # Number of ticks simulated -system.cpu.dtb.accesses 2354955 # DTB accesses -system.cpu.dtb.acv 413 # DTB access violations -system.cpu.dtb.hits 13926686 # DTB hits -system.cpu.dtb.misses 16187 # DTB misses -system.cpu.dtb.read_accesses 832415 # DTB read accesses -system.cpu.dtb.read_acv 242 # DTB read access violations -system.cpu.dtb.read_hits 7716658 # DTB read hits -system.cpu.dtb.read_misses 13695 # DTB read misses -system.cpu.dtb.write_accesses 1522540 # DTB write accesses -system.cpu.dtb.write_acv 171 # DTB write access violations -system.cpu.dtb.write_hits 6210028 # DTB write hits -system.cpu.dtb.write_misses 2492 # DTB write misses -system.cpu.idle_fraction 0.978925 # Percentage of idle cycles -system.cpu.itb.accesses 4037381 # ITB accesses -system.cpu.itb.acv 239 # ITB acv -system.cpu.itb.hits 4030657 # ITB hits -system.cpu.itb.misses 6724 # ITB misses -system.cpu.kern.callpal 183644 # number of callpals executed +sim_insts 57989043 # Number of instructions simulated +sim_seconds 1.746889 # Number of seconds simulated +sim_ticks 3493777466 # Number of ticks simulated +system.cpu.dtb.accesses 2309470 # DTB accesses +system.cpu.dtb.acv 367 # DTB access violations +system.cpu.dtb.hits 13707871 # DTB hits +system.cpu.dtb.misses 12493 # DTB misses +system.cpu.dtb.read_accesses 828530 # DTB read accesses +system.cpu.dtb.read_acv 210 # DTB read access violations +system.cpu.dtb.read_hits 7595606 # DTB read hits +system.cpu.dtb.read_misses 10298 # DTB read misses +system.cpu.dtb.write_accesses 1480940 # DTB write accesses +system.cpu.dtb.write_acv 157 # DTB write access violations +system.cpu.dtb.write_hits 6112265 # DTB write hits +system.cpu.dtb.write_misses 2195 # DTB write misses +system.cpu.idle_fraction 0.979465 # Percentage of idle cycles +system.cpu.itb.accesses 3281347 # ITB accesses +system.cpu.itb.acv 184 # ITB acv +system.cpu.itb.hits 3276357 # ITB hits +system.cpu.itb.misses 4990 # ITB misses +system.cpu.kern.callpal 182454 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 1861 1.01% 1.02% # number of callpals executed -system.cpu.kern.callpal_tbi 28 0.02% 1.03% # number of callpals executed -system.cpu.kern.callpal_wrent 7 0.00% 1.03% # number of callpals executed -system.cpu.kern.callpal_swpipl 171635 93.46% 94.50% # number of callpals executed -system.cpu.kern.callpal_rdps 4808 2.62% 97.11% # number of callpals executed -system.cpu.kern.callpal_wrkgp 1 0.00% 97.11% # number of callpals executed -system.cpu.kern.callpal_wrusp 8 0.00% 97.12% # number of callpals executed -system.cpu.kern.callpal_rdusp 12 0.01% 97.12% # number of callpals executed -system.cpu.kern.callpal_whami 2 0.00% 97.13% # number of callpals executed -system.cpu.kern.callpal_rti 4297 2.34% 99.47% # number of callpals executed -system.cpu.kern.callpal_callsys 667 0.36% 99.83% # number of callpals executed -system.cpu.kern.callpal_imb 314 0.17% 100.00% # number of callpals executed +system.cpu.kern.callpal_swpctx 1571 0.86% 0.86% # number of callpals executed +system.cpu.kern.callpal_tbi 54 0.03% 0.89% # number of callpals executed +system.cpu.kern.callpal_wrent 7 0.00% 0.90% # number of callpals executed +system.cpu.kern.callpal_swpipl 171092 93.77% 94.67% # number of callpals executed +system.cpu.kern.callpal_rdps 5160 2.83% 97.50% # number of callpals executed +system.cpu.kern.callpal_wrkgp 1 0.00% 97.50% # number of callpals executed +system.cpu.kern.callpal_wrusp 7 0.00% 97.50% # number of callpals executed +system.cpu.kern.callpal_rdusp 10 0.01% 97.51% # number of callpals executed +system.cpu.kern.callpal_whami 2 0.00% 97.51% # number of callpals executed +system.cpu.kern.callpal_rti 3834 2.10% 99.61% # number of callpals executed +system.cpu.kern.callpal_callsys 531 0.29% 99.90% # number of callpals executed +system.cpu.kern.callpal_imb 181 0.10% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 209285 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 202524 # number of hwrei instructions executed system.cpu.kern.inst.ivlb 0 # number of ivlb instructions executed system.cpu.kern.inst.ivle 0 # number of ivle instructions executed -system.cpu.kern.inst.quiesce 1867 # number of quiesce instructions executed -system.cpu.kern.ipl_count 178009 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75254 42.28% 42.28% # number of times we switched to this ipl -system.cpu.kern.ipl_count_21 286 0.16% 42.44% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 5465 3.07% 45.51% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 97004 54.49% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 159802 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 75188 47.05% 47.05% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_21 286 0.18% 47.23% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 5465 3.42% 50.65% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 78863 49.35% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3506217640 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3478896122 99.22% 99.22% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_21 60705 0.00% 99.22% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 1274059 0.04% 99.26% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 25986754 0.74% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.897719 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_0 0.999123 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.quiesce 1876 # number of quiesce instructions executed +system.cpu.kern.ipl_count 176961 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 74471 42.08% 42.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count_21 251 0.14% 42.23% # number of times we switched to this ipl +system.cpu.kern.ipl_count_22 5439 3.07% 45.30% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 96800 54.70% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 158180 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 74417 47.05% 47.05% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_21 251 0.16% 47.20% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_22 5439 3.44% 50.64% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 78073 49.36% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 3493777020 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 3466334940 99.21% 99.21% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_21 53019 0.00% 99.22% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_22 1268195 0.04% 99.25% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 26120866 0.75% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used 0.893869 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used_0 0.999275 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.812987 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 2339 -system.cpu.kern.mode_good_user 2168 -system.cpu.kern.mode_good_idle 171 -system.cpu.kern.mode_switch_kernel 4093 # number of protection mode switches -system.cpu.kern.mode_switch_user 2168 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2043 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.563343 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.571463 # fraction of useful protection mode switches +system.cpu.kern.ipl_used_31 0.806539 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1938 +system.cpu.kern.mode_good_user 1757 +system.cpu.kern.mode_good_idle 181 +system.cpu.kern.mode_switch_kernel 3323 # number of protection mode switches +system.cpu.kern.mode_switch_user 1757 # number of protection mode switches +system.cpu.kern.mode_switch_idle 2060 # number of protection mode switches +system.cpu.kern.mode_switch_good 0.542857 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.583208 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.083700 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 40644475 1.16% 1.16% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 5527486 0.16% 1.32% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3460045677 98.68% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 1862 # number of times the context was actually changed -system.cpu.kern.syscall 475 # number of syscalls executed -system.cpu.kern.syscall_fork 10 2.11% 2.11% # number of syscalls executed -system.cpu.kern.syscall_read 33 6.95% 9.05% # number of syscalls executed -system.cpu.kern.syscall_write 7 1.47% 10.53% # number of syscalls executed -system.cpu.kern.syscall_close 49 10.32% 20.84% # number of syscalls executed -system.cpu.kern.syscall_chdir 1 0.21% 21.05% # number of syscalls executed -system.cpu.kern.syscall_chmod 1 0.21% 21.26% # number of syscalls executed -system.cpu.kern.syscall_obreak 44 9.26% 30.53% # number of syscalls executed -system.cpu.kern.syscall_lseek 13 2.74% 33.26% # number of syscalls executed -system.cpu.kern.syscall_getpid 10 2.11% 35.37% # number of syscalls executed -system.cpu.kern.syscall_setuid 4 0.84% 36.21% # number of syscalls executed -system.cpu.kern.syscall_getuid 8 1.68% 37.89% # number of syscalls executed -system.cpu.kern.syscall_access 4 0.84% 38.74% # number of syscalls executed -system.cpu.kern.syscall_dup 4 0.84% 39.58% # number of syscalls executed -system.cpu.kern.syscall_open 68 14.32% 53.89% # number of syscalls executed -system.cpu.kern.syscall_getgid 8 1.68% 55.58% # number of syscalls executed -system.cpu.kern.syscall_sigprocmask 14 2.95% 58.53% # number of syscalls executed -system.cpu.kern.syscall_ioctl 16 3.37% 61.89% # number of syscalls executed -system.cpu.kern.syscall_readlink 2 0.42% 62.32% # number of syscalls executed -system.cpu.kern.syscall_execve 8 1.68% 64.00% # number of syscalls executed -system.cpu.kern.syscall_pre_F64_stat 31 6.53% 70.53% # number of syscalls executed -system.cpu.kern.syscall_pre_F64_lstat 1 0.21% 70.74% # number of syscalls executed -system.cpu.kern.syscall_mmap 55 11.58% 82.32% # number of syscalls executed -system.cpu.kern.syscall_munmap 6 1.26% 83.58% # number of syscalls executed -system.cpu.kern.syscall_mprotect 14 2.95% 86.53% # number of syscalls executed -system.cpu.kern.syscall_gethostname 2 0.42% 86.95% # number of syscalls executed -system.cpu.kern.syscall_dup2 4 0.84% 87.79% # number of syscalls executed -system.cpu.kern.syscall_pre_F64_fstat 28 5.89% 93.68% # number of syscalls executed -system.cpu.kern.syscall_fcntl 14 2.95% 96.63% # number of syscalls executed -system.cpu.kern.syscall_socket 3 0.63% 97.26% # number of syscalls executed -system.cpu.kern.syscall_connect 3 0.63% 97.89% # number of syscalls executed -system.cpu.kern.syscall_setgid 4 0.84% 98.74% # number of syscalls executed -system.cpu.kern.syscall_getrlimit 3 0.63% 99.37% # number of syscalls executed -system.cpu.kern.syscall_setsid 3 0.63% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.021075 # Percentage of non-idle cycles +system.cpu.kern.mode_switch_good_idle 0.087864 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 39254786 1.12% 1.12% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 4685669 0.13% 1.26% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 3449836563 98.74% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 1572 # number of times the context was actually changed +system.cpu.kern.syscall 329 # number of syscalls executed +system.cpu.kern.syscall_fork 8 2.43% 2.43% # number of syscalls executed +system.cpu.kern.syscall_read 30 9.12% 11.55% # number of syscalls executed +system.cpu.kern.syscall_write 4 1.22% 12.77% # number of syscalls executed +system.cpu.kern.syscall_close 43 13.07% 25.84% # number of syscalls executed +system.cpu.kern.syscall_chdir 1 0.30% 26.14% # number of syscalls executed +system.cpu.kern.syscall_chmod 1 0.30% 26.44% # number of syscalls executed +system.cpu.kern.syscall_obreak 15 4.56% 31.00% # number of syscalls executed +system.cpu.kern.syscall_lseek 10 3.04% 34.04% # number of syscalls executed +system.cpu.kern.syscall_getpid 6 1.82% 35.87% # number of syscalls executed +system.cpu.kern.syscall_setuid 4 1.22% 37.08% # number of syscalls executed +system.cpu.kern.syscall_getuid 6 1.82% 38.91% # number of syscalls executed +system.cpu.kern.syscall_access 11 3.34% 42.25% # number of syscalls executed +system.cpu.kern.syscall_dup 2 0.61% 42.86% # number of syscalls executed +system.cpu.kern.syscall_open 55 16.72% 59.57% # number of syscalls executed +system.cpu.kern.syscall_getgid 6 1.82% 61.40% # number of syscalls executed +system.cpu.kern.syscall_sigprocmask 10 3.04% 64.44% # number of syscalls executed +system.cpu.kern.syscall_ioctl 10 3.04% 67.48% # number of syscalls executed +system.cpu.kern.syscall_readlink 1 0.30% 67.78% # number of syscalls executed +system.cpu.kern.syscall_execve 7 2.13% 69.91% # number of syscalls executed +system.cpu.kern.syscall_mmap 54 16.41% 86.32% # number of syscalls executed +system.cpu.kern.syscall_munmap 3 0.91% 87.23% # number of syscalls executed +system.cpu.kern.syscall_mprotect 16 4.86% 92.10% # number of syscalls executed +system.cpu.kern.syscall_gethostname 1 0.30% 92.40% # number of syscalls executed +system.cpu.kern.syscall_dup2 3 0.91% 93.31% # number of syscalls executed +system.cpu.kern.syscall_fcntl 10 3.04% 96.35% # number of syscalls executed +system.cpu.kern.syscall_socket 2 0.61% 96.96% # number of syscalls executed +system.cpu.kern.syscall_connect 2 0.61% 97.57% # number of syscalls executed +system.cpu.kern.syscall_setgid 4 1.22% 98.78% # number of syscalls executed +system.cpu.kern.syscall_getrlimit 2 0.61% 99.39% # number of syscalls executed +system.cpu.kern.syscall_setsid 2 0.61% 100.00% # number of syscalls executed +system.cpu.not_idle_fraction 0.020535 # Percentage of non-idle cycles system.cpu.numCycles 0 # number of cpu cycles simulated -system.cpu.num_insts 59915182 # Number of instructions executed -system.cpu.num_refs 13979549 # Number of memory references +system.cpu.num_insts 57989043 # Number of instructions executed +system.cpu.num_refs 13753099 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_bytes 2521088 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_full_pages 285 # Number of full page size DMA writes. -system.disk0.dma_write_txs 375 # Number of DMA write transactions. +system.disk0.dma_write_bytes 2735104 # Number of bytes transfered via DMA writes. +system.disk0.dma_write_full_pages 306 # Number of full page size DMA writes. +system.disk0.dma_write_txs 412 # Number of DMA write transactions. system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout index 2739943d2..88e69a41f 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout @@ -5,8 +5,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:32:34 -M5 started Tue Sep 5 15:43:59 2006 +M5 compiled Oct 5 2006 22:13:02 +M5 started Fri Oct 6 00:24:58 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing -Exiting @ tick 3506218170 because m5_exit instruction encountered +Exiting @ tick 3493777466 because m5_exit instruction encountered diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini index a4b103732..8722c1b67 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini @@ -64,6 +64,7 @@ max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.physmem +progress_interval=0 simulate_stalls=false system=system width=1 @@ -92,6 +93,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out index 8f236d9cc..6ae80aecf 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.out @@ -33,6 +33,7 @@ max_insts_any_thread=500000 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.physmem system=system workload=system.cpu.workload @@ -46,6 +47,7 @@ simulate_stalls=false [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -89,3 +91,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt index 0132ecf1b..9fdf1d513 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1397534 # Simulator instruction rate (inst/s) -host_mem_usage 147632 # Number of bytes of host memory used +host_inst_rate 1393697 # Simulator instruction rate (inst/s) +host_mem_usage 147652 # Number of bytes of host memory used host_seconds 0.36 # Real time elapsed on the host -host_tick_rate 1395943 # Simulator tick rate (ticks/s) +host_tick_rate 1391995 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000000 # Number of seconds simulated diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout index d3edcdc0a..207a0046c 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:20 2006 +M5 compiled Oct 7 2006 11:12:49 +M5 started Sat Oct 7 11:13:17 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic Exiting @ tick 499999 because a thread reached the max instruction count diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini index 27568ad50..f4bdc8171 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini @@ -64,6 +64,7 @@ max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 mem=system.cpu.dcache +progress_interval=0 system=system workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side @@ -215,6 +216,7 @@ port=system.membus.port[0] [trace] bufsize=0 +cycle=0 dump_on_exit=false file=cout flags= diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out index ba6875a7b..71a6d33c4 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.out @@ -72,6 +72,7 @@ max_insts_any_thread=500000 max_insts_all_threads=0 max_loads_any_thread=0 max_loads_all_threads=0 +progress_interval=0 mem=system.cpu.dcache system=system workload=system.cpu.workload @@ -167,6 +168,7 @@ hit_latency=1 [trace] flags= start=0 +cycle=0 bufsize=0 file=cout dump_on_exit=false @@ -210,3 +212,6 @@ trace_system=client [debug] break_cycles= +[statsreset] +reset_cycle=0 + diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt index 6339e48b7..f8d2c4ea7 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 620120 # Simulator instruction rate (inst/s) -host_mem_usage 159196 # Number of bytes of host memory used +host_inst_rate 618043 # Simulator instruction rate (inst/s) +host_mem_usage 159232 # Number of bytes of host memory used host_seconds 0.81 # Real time elapsed on the host -host_tick_rate 845850 # Simulator tick rate (ticks/s) +host_tick_rate 843177 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 500000 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 682354 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 124564 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 2.987952 # average ReadReq miss latency +sim_ticks 682488 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 124315 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 744 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.001999 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 249 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 496 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001991 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 248 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 56744 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 1.256024 # average WriteReq miss latency +system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 945 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 630 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 56412 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 417 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.005851 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 332 # number of WriteReq misses +system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 278 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002450 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 311.061962 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 181308 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 1.998279 # average overall miss latency +system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency -system.cpu.dcache.demand_hits 180727 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 1161 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003204 # miss rate for demand accesses -system.cpu.dcache.demand_misses 581 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 1362 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses +system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 774 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002134 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 387 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 908 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 181308 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 1.998279 # average overall miss latency +system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 180727 # number of overall hits -system.cpu.dcache.overall_miss_latency 1161 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003204 # miss rate for overall accesses -system.cpu.dcache.overall_misses 581 # number of overall misses +system.cpu.dcache.overall_hits 180321 # number of overall hits +system.cpu.dcache.overall_miss_latency 1362 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses +system.cpu.dcache.overall_misses 454 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 774 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002134 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 387 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 908 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -74,10 +74,10 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 581 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 347.118131 # Cycle average of tags in use -system.cpu.dcache.total_refs 180727 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 291.968600 # Cycle average of tags in use +system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses) @@ -138,54 +138,56 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 268.434590 # Cycle average of tags in use +system.cpu.icache.tagsinuse 268.423238 # Cycle average of tags in use system.cpu.icache.total_refs 499597 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 1.605691 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_accesses 857 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 1580 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 1714 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 984 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 790 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.802846 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 790 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_misses 857 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 857 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 857 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteReq_accesses 165 # number of WriteReq accesses(hits+misses) +system.cpu.l2cache.WriteReq_hits 165 # number of WriteReq hits system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.192532 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 984 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 1.605691 # average overall miss latency +system.cpu.l2cache.demand_accesses 1022 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 1580 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 984 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 165 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 1714 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.838552 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 790 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.802846 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 790 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.838552 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 984 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 1.605691 # average overall miss latency +system.cpu.l2cache.overall_accesses 1022 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 1580 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 984 # number of overall misses +system.cpu.l2cache.overall_hits 165 # number of overall hits +system.cpu.l2cache.overall_miss_latency 1714 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.838552 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 857 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 790 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.802846 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 790 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 857 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.838552 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -198,10 +200,10 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 984 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 857 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 615.553879 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 560.393094 # Cycle average of tags in use +system.cpu.l2cache.total_refs 165 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles diff --git a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout index 158dcfe2b..409068a91 100644 --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout @@ -7,8 +7,8 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Sep 5 2006 15:28:48 -M5 started Tue Sep 5 15:42:20 2006 +M5 compiled Oct 7 2006 12:38:12 +M5 started Sat Oct 7 12:38:52 2006 M5 executing on zizzer.eecs.umich.edu command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing -Exiting @ tick 682354 because a thread reached the max instruction count +Exiting @ tick 682488 because a thread reached the max instruction count |