diff options
| -rw-r--r-- | src/arch/arm/isa/decoder/arm.isa | 18 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/data.isa | 91 |
2 files changed, 92 insertions, 17 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa index d739395a1..be3a8787a 100644 --- a/src/arch/arm/isa/decoder/arm.isa +++ b/src/arch/arm/isa/decoder/arm.isa @@ -117,23 +117,7 @@ format DataOp { 0: AddrMode2::addrMode2(False); 1: decode OPCODE_24_23 { 0x0: ArmParallelAddSubtract::armParallelAddSubtract(); - 0x1: decode MEDIA_OPCODE { - 0x8: decode MISC_OPCODE { - 0x1, 0x9: WarnUnimpl::pkhbt(); - 0x7: WarnUnimpl::sxtab16(); - 0xb: WarnUnimpl::sel(); - 0x5, 0xd: WarnUnimpl::pkhtb(); - 0x3: WarnUnimpl::sign_zero_extend_add(); - } - 0xa, 0xb: decode SHIFT { - 0x0, 0x2: WarnUnimpl::ssat(); - 0x1: WarnUnimpl::ssat16(); - } - 0xe, 0xf: decode SHIFT { - 0x0, 0x2: WarnUnimpl::usat(); - 0x1: WarnUnimpl::usat16(); - } - } + 0x1: ArmPackUnpackSatReverse::armPackUnpackSatReverse(); 0x2: ArmSignedMultiplies::armSignedMultiplies(); 0x3: decode MEDIA_OPCODE { 0x18: decode RN { diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa index 43bd65589..a19c4ea3d 100644 --- a/src/arch/arm/isa/formats/data.isa +++ b/src/arch/arm/isa/formats/data.isa @@ -124,6 +124,97 @@ def format ArmDataProcReg() {{ ''' }}; +def format ArmPackUnpackSatReverse() {{ + decode_block = ''' + { + const uint32_t op1 = bits(machInst, 22, 20); + const uint32_t a = bits(machInst, 19, 16); + const uint32_t op2 = bits(machInst, 7, 5); + if (bits(op2, 0) == 0) { + if (op1 == 0) { + return new WarnUnimplemented("pkh", machInst); + } else if (bits(op1, 2, 1) == 1) { + return new WarnUnimplemented("ssat", machInst); + } else if (bits(op1, 2, 1) == 3) { + return new WarnUnimplemented("usat", machInst); + } + return new Unknown(machInst); + } + switch (op1) { + case 0x0: + if (op2 == 0x3) { + if (a == 0xf) { + return new WarnUnimplemented("sxtb16", machInst); + } else { + return new WarnUnimplemented("sxtab16", machInst); + } + } else if (op2 == 0x5) { + return new WarnUnimplemented("sel", machInst); + } + break; + case 0x2: + if (op2 == 0x1) { + return new WarnUnimplemented("ssat16", machInst); + } else if (op2 == 0x3) { + if (a == 0xf) { + return new WarnUnimplemented("sxtb", machInst); + } else { + return new WarnUnimplemented("sxtab", machInst); + } + } + break; + case 0x3: + if (op2 == 0x1) { + return new WarnUnimplemented("rev", machInst); + } else if (op2 == 0x3) { + if (a == 0xf) { + return new WarnUnimplemented("sxth", machInst); + } else { + return new WarnUnimplemented("sxtah", machInst); + } + } else if (op2 == 0x5) { + return new WarnUnimplemented("rev16", machInst); + } + break; + case 0x4: + if (op2 == 0x3) { + if (a == 0xf) { + return new WarnUnimplemented("uxtb16", machInst); + } else { + return new WarnUnimplemented("uxtab16", machInst); + } + } + break; + case 0x6: + if (op2 == 0x1) { + return new WarnUnimplemented("usat16", machInst); + } else if (op2 == 0x3) { + if (a == 0xf) { + return new WarnUnimplemented("uxtb", machInst); + } else { + return new WarnUnimplemented("uxtab", machInst); + } + } + break; + case 0x7: + if (op2 == 0x1) { + return new WarnUnimplemented("rbit", machInst); + } else if (op2 == 0x3) { + if (a == 0xf) { + return new WarnUnimplemented("uxth", machInst); + } else { + return new WarnUnimplemented("uxtah", machInst); + } + } else if (op2 == 0x5) { + return new WarnUnimplemented("revsh", machInst); + } + break; + } + return new Unknown(machInst); + } + ''' +}}; + def format ArmParallelAddSubtract() {{ decode_block=''' { |