diff options
| -rw-r--r-- | configs/common/CpuConfig.py | 1 | ||||
| -rw-r--r-- | configs/common/Options.py | 2 | ||||
| -rw-r--r-- | configs/example/fs.py | 15 | ||||
| -rw-r--r-- | configs/example/se.py | 14 | ||||
| -rw-r--r-- | src/cpu/simple/AtomicSimpleCPU.py | 1 | ||||
| -rw-r--r-- | src/cpu/simple/NonCachingSimpleCPU.py | 60 | ||||
| -rw-r--r-- | src/cpu/simple/SConscript | 6 | ||||
| -rw-r--r-- | src/cpu/simple/atomic.cc | 28 | ||||
| -rw-r--r-- | src/cpu/simple/atomic.hh | 9 | ||||
| -rw-r--r-- | src/cpu/simple/noncaching.cc | 74 | ||||
| -rw-r--r-- | src/cpu/simple/noncaching.hh | 61 | ||||
| -rw-r--r-- | tests/configs/realview-switcheroo-noncaching-timing.py | 48 | ||||
| -rwxr-xr-x | tests/testing/tests.py | 1 |
13 files changed, 272 insertions, 48 deletions
diff --git a/configs/common/CpuConfig.py b/configs/common/CpuConfig.py index d70e6cfa7..f0d009e95 100644 --- a/configs/common/CpuConfig.py +++ b/configs/common/CpuConfig.py @@ -69,6 +69,7 @@ def _cpu_subclass_tester(name): return tester is_kvm_cpu = _cpu_subclass_tester("BaseKvmCPU") +is_atomic_cpu = _cpu_subclass_tester("AtomicSimpleCPU") def get(name): """Get a CPU class from a user provided class name or alias.""" diff --git a/configs/common/Options.py b/configs/common/Options.py index 29ef74c9a..aed888191 100644 --- a/configs/common/Options.py +++ b/configs/common/Options.py @@ -164,8 +164,6 @@ def addCommonOptions(parser): parser.add_option("-l", "--lpae", action="store_true") parser.add_option("-V", "--virtualisation", action="store_true") - parser.add_option("--fastmem", action="store_true") - # dist-gem5 options parser.add_option("--dist", action="store_true", help="Parallel distributed gem5 simulation.") diff --git a/configs/example/fs.py b/configs/example/fs.py index f299d761c..3997ed76c 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -188,22 +188,13 @@ def build_test_system(np): test_sys.iobridge.master = test_sys.membus.slave # Sanity check - if options.fastmem: - if TestCPUClass != AtomicSimpleCPU: - fatal("Fastmem can only be used with atomic CPU!") - if (options.caches or options.l2cache): - fatal("You cannot use fastmem in combination with caches!") - if options.simpoint_profile: - if not options.fastmem: - # Atomic CPU checked with fastmem option already - fatal("SimPoint generation should be done with atomic cpu and fastmem") + if not CpuConfig.is_atomic_cpu(TestCPUClass): + fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal("SimPoint generation not supported with more than one CPUs") for i in xrange(np): - if options.fastmem: - test_sys.cpu[i].fastmem = True if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: @@ -269,8 +260,6 @@ def build_drive_system(np): drive_sys.cpu.createThreads() drive_sys.cpu.createInterruptController() drive_sys.cpu.connectAllPorts(drive_sys.membus) - if options.fastmem: - drive_sys.cpu.fastmem = True if options.kernel is not None: drive_sys.kernel = binary(options.kernel) diff --git a/configs/example/se.py b/configs/example/se.py index 015a953da..804ef02c5 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -213,16 +213,9 @@ if CpuConfig.is_kvm_cpu(CPUClass) or CpuConfig.is_kvm_cpu(FutureClass): fatal("KvmCPU can only be used in SE mode with x86") # Sanity check -if options.fastmem: - if CPUClass != AtomicSimpleCPU: - fatal("Fastmem can only be used with atomic CPU!") - if (options.caches or options.l2cache): - fatal("You cannot use fastmem in combination with caches!") - if options.simpoint_profile: - if not options.fastmem: - # Atomic CPU checked with fastmem option already - fatal("SimPoint generation should be done with atomic cpu and fastmem") + if not CpuConfig.is_atomic_cpu(TestCPUClass): + fatal("SimPoint/BPProbe should be done with an atomic cpu") if np > 1: fatal("SimPoint generation not supported with more than one CPUs") @@ -234,9 +227,6 @@ for i in xrange(np): else: system.cpu[i].workload = multiprocesses[i] - if options.fastmem: - system.cpu[i].fastmem = True - if options.simpoint_profile: system.cpu[i].addSimPointProbe(options.simpoint_interval) diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index 04592c68a..15a3feb69 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -61,7 +61,6 @@ class AtomicSimpleCPU(BaseSimpleCPU): width = Param.Int(1, "CPU width") simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") - fastmem = Param.Bool(False, "Access memory directly") def addSimPointProbe(self, interval): simpoint = SimPoint() diff --git a/src/cpu/simple/NonCachingSimpleCPU.py b/src/cpu/simple/NonCachingSimpleCPU.py new file mode 100644 index 000000000..2905a79ac --- /dev/null +++ b/src/cpu/simple/NonCachingSimpleCPU.py @@ -0,0 +1,60 @@ +# Copyright (c) 2012, 2018 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Sandberg + +from m5.params import * +from AtomicSimpleCPU import AtomicSimpleCPU + +class NonCachingSimpleCPU(AtomicSimpleCPU): + """Simple CPU model based on the atomic CPU. Unlike the atomic CPU, + this model causes the memory system to bypass caches and is + therefore slightly faster in some cases. However, its main purpose + is as a substitute for hardware virtualized CPUs when + stress-testing the memory system. + + """ + + type = 'NonCachingSimpleCPU' + cxx_header = "cpu/simple/noncaching.hh" + + @classmethod + def memory_mode(cls): + return 'atomic_noncaching' + + @classmethod + def support_take_over(cls): + return True + diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript index 3b6b19c51..991519c6e 100644 --- a/src/cpu/simple/SConscript +++ b/src/cpu/simple/SConscript @@ -36,6 +36,12 @@ if 'AtomicSimpleCPU' in env['CPU_MODELS']: SimObject('AtomicSimpleCPU.py') Source('atomic.cc') + # The NonCachingSimpleCPU is really an atomic CPU in + # disguise. It's therefore always enabled when the atomic CPU is + # enabled. + SimObject('NonCachingSimpleCPU.py') + Source('noncaching.cc') + if 'TimingSimpleCPU' in env['CPU_MODELS']: need_simple_base = True SimObject('TimingSimpleCPU.py') diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 040d1dbf9..e91fafbcc 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -1,6 +1,6 @@ /* * Copyright 2014 Google, Inc. - * Copyright (c) 2012-2013,2015,2017 ARM Limited + * Copyright (c) 2012-2013,2015,2017-2018 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -83,7 +83,7 @@ AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) simulate_inst_stalls(p->simulate_inst_stalls), icachePort(name() + ".icache_port", this), dcachePort(name() + ".dcache_port", this), - fastmem(p->fastmem), dcache_access(false), dcache_latency(0), + dcache_access(false), dcache_latency(0), ppCommit(nullptr) { _status = Idle; @@ -271,6 +271,11 @@ AtomicSimpleCPU::suspendContext(ThreadID thread_num) BaseCPU::suspendContext(thread_num); } +Tick +AtomicSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt) +{ + return port.sendAtomic(pkt); +} Tick AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) @@ -364,13 +369,10 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size, Packet pkt(req, Packet::makeReadCmd(req)); pkt.dataStatic(data); - if (req->isMmappedIpr()) + if (req->isMmappedIpr()) { dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); - else { - if (fastmem && system->isMemAddr(pkt.getAddr())) - system->getPhysMem().access(&pkt); - else - dcache_latency += dcachePort.sendAtomic(&pkt); + } else { + dcache_latency += sendPacket(dcachePort, &pkt); } dcache_access = true; @@ -483,10 +485,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, dcache_latency += TheISA::handleIprWrite(thread->getTC(), &pkt); } else { - if (fastmem && system->isMemAddr(pkt.getAddr())) - system->getPhysMem().access(&pkt); - else - dcache_latency += dcachePort.sendAtomic(&pkt); + dcache_latency += sendPacket(dcachePort, &pkt); // Notify other threads on this CPU of write threadSnoop(&pkt, curThread); @@ -603,10 +602,7 @@ AtomicSimpleCPU::tick() Packet ifetch_pkt = Packet(ifetch_req, MemCmd::ReadReq); ifetch_pkt.dataStatic(&inst); - if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) - system->getPhysMem().access(&ifetch_pkt); - else - icache_latency = icachePort.sendAtomic(&ifetch_pkt); + icache_latency = sendPacket(icachePort, &ifetch_pkt); assert(!ifetch_pkt.isError()); diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index addbe234e..a5151aa18 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013,2015 ARM Limited + * Copyright (c) 2012-2013, 2015, 2018 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -58,7 +58,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU void init() override; - private: + protected: EventFunctionWrapper tickEvent; @@ -103,6 +103,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU */ bool tryCompleteDrain(); + virtual Tick sendPacket(MasterPort &port, const PacketPtr &pkt); + /** * An AtomicCPUPort overrides the default behaviour of the * recvAtomicSnoop and ignores the packet instead of panicking. It @@ -137,7 +139,6 @@ class AtomicSimpleCPU : public BaseSimpleCPU { public: - AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu) : AtomicCPUPort(_name, _cpu), cpu(_cpu) { @@ -158,7 +159,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU AtomicCPUPort icachePort; AtomicCPUDPort dcachePort; - bool fastmem; + RequestPtr ifetch_req; RequestPtr data_read_req; RequestPtr data_write_req; diff --git a/src/cpu/simple/noncaching.cc b/src/cpu/simple/noncaching.cc new file mode 100644 index 000000000..335d38b0c --- /dev/null +++ b/src/cpu/simple/noncaching.cc @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2012, 2018 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Sandberg + */ + +#include "cpu/simple/noncaching.hh" + +NonCachingSimpleCPU::NonCachingSimpleCPU(NonCachingSimpleCPUParams *p) + : AtomicSimpleCPU(p) +{ +} + +void +NonCachingSimpleCPU::verifyMemoryMode() const +{ + if (!(system->isAtomicMode() && system->bypassCaches())) { + fatal("The direct CPU requires the memory system to be in the " + "'atomic_noncaching' mode.\n"); + } +} + +Tick +NonCachingSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt) +{ + if (system->isMemAddr(pkt->getAddr())) { + system->getPhysMem().access(pkt); + return 0; + } else { + return port.sendAtomic(pkt); + } +} + +NonCachingSimpleCPU * +NonCachingSimpleCPUParams::create() +{ + numThreads = 1; + if (!FullSystem && workload.size() != 1) + fatal("only one workload allowed"); + return new NonCachingSimpleCPU(this); +} diff --git a/src/cpu/simple/noncaching.hh b/src/cpu/simple/noncaching.hh new file mode 100644 index 000000000..775aa2155 --- /dev/null +++ b/src/cpu/simple/noncaching.hh @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2012, 2018 ARM Limited + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Sandberg + */ + +#ifndef __CPU_SIMPLE_NONCACHING_HH__ +#define __CPU_SIMPLE_NONCACHING_HH___ + +#include "cpu/simple/atomic.hh" +#include "params/NonCachingSimpleCPU.hh" + +/** + * The NonCachingSimpleCPU is an AtomicSimpleCPU using the + * 'atomic_noncaching' memory mode instead of just 'atomic'. + */ +class NonCachingSimpleCPU : public AtomicSimpleCPU +{ + public: + NonCachingSimpleCPU(NonCachingSimpleCPUParams *p); + + void verifyMemoryMode() const override; + + protected: + Tick sendPacket(MasterPort &port, const PacketPtr &pkt) override; +}; + +#endif // __CPU_SIMPLE_NONCACHING_HH__ diff --git a/tests/configs/realview-switcheroo-noncaching-timing.py b/tests/configs/realview-switcheroo-noncaching-timing.py new file mode 100644 index 000000000..f23c195f8 --- /dev/null +++ b/tests/configs/realview-switcheroo-noncaching-timing.py @@ -0,0 +1,48 @@ +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Sandberg + +from m5.objects import * +from arm_generic import * +import switcheroo + +root = LinuxArmFSSwitcheroo( + cpu_classes=(NonCachingSimpleCPU, TimingSimpleCPU), + ).create_root() + +# Setup a custom test method that uses the switcheroo tester that +# switches between CPU models. +run_test = switcheroo.run_test diff --git a/tests/testing/tests.py b/tests/testing/tests.py index e72ce6815..123d3b1a4 100755 --- a/tests/testing/tests.py +++ b/tests/testing/tests.py @@ -102,6 +102,7 @@ arch_configs = { 'realview-minor-dual', 'realview-switcheroo-atomic', 'realview-switcheroo-timing', + 'realview-switcheroo-noncaching-timing', 'realview-switcheroo-o3', 'realview-switcheroo-full', 'realview64-simple-atomic', |