diff options
| -rw-r--r-- | src/cpu/StaticInstFlags.py | 1 | ||||
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 1 | ||||
| -rw-r--r-- | src/cpu/static_inst.hh | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/StaticInstFlags.py b/src/cpu/StaticInstFlags.py index 55ef456ce..170ca6d09 100644 --- a/src/cpu/StaticInstFlags.py +++ b/src/cpu/StaticInstFlags.py @@ -64,6 +64,7 @@ class StaticInstFlags(Enum): 'IsMemRef', # References memory (load, store, or prefetch) 'IsLoad', # Reads from memory (load or prefetch). 'IsStore', # Writes to memory. + 'IsAtomic', # Does atomic RMW to memory. 'IsStoreConditional', # Store conditional instruction. 'IsIndexed', # Accesses memory with an indexed address # computation diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 2c08a3c67..93cafd694 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -505,6 +505,7 @@ class BaseDynInst : public ExecContext, public RefCounted bool isMemRef() const { return staticInst->isMemRef(); } bool isLoad() const { return staticInst->isLoad(); } bool isStore() const { return staticInst->isStore(); } + bool isAtomic() const { return staticInst->isAtomic(); } bool isStoreConditional() const { return staticInst->isStoreConditional(); } bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index 84b352502..16b5ffd3c 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -144,6 +144,7 @@ class StaticInst : public RefCounted, public StaticInstFlags bool isMemRef() const { return flags[IsMemRef]; } bool isLoad() const { return flags[IsLoad]; } bool isStore() const { return flags[IsStore]; } + bool isAtomic() const { return flags[IsAtomic]; } bool isStoreConditional() const { return flags[IsStoreConditional]; } bool isInstPrefetch() const { return flags[IsInstPrefetch]; } bool isDataPrefetch() const { return flags[IsDataPrefetch]; } |