diff options
| -rw-r--r-- | src/cpu/BaseCPU.py | 4 | ||||
| -rw-r--r-- | src/cpu/base.cc | 12 | ||||
| -rw-r--r-- | src/cpu/base.hh | 5 |
3 files changed, 17 insertions, 4 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 0e131ae0a..1bf2c1e35 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -138,6 +138,10 @@ class BaseCPU(MemObject): pwr_gating_latency = Param.Cycles(300, "Latency to enter power gating state when all contexts are suspended") + power_gating_on_idle = Param.Bool(False, "Control whether the core goes "\ + "to the OFF power state after all thread are disabled for "\ + "pwr_gating_latency cycles") + function_trace = Param.Bool(False, "Enable function trace") function_trace_start = Param.Tick(0, "Tick to start function trace") diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 78cf4196c..af55ee1d6 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -138,6 +138,7 @@ BaseCPU::BaseCPU(Params *p, bool is_checker) addressMonitor(p->numThreads), syscallRetryLatency(p->syscallRetryLatency), pwrGatingLatency(p->pwr_gating_latency), + powerGatingOnIdle(p->power_gating_on_idle), enterPwrGatingEvent([this]{ enterPwrGating(); }, name()) { // if Python did not provide a valid ID, do it here @@ -493,7 +494,8 @@ BaseCPU::schedulePowerGatingEvent() return; } - if (ClockedObject::pwrState() == Enums::PwrState::CLK_GATED) { + if (ClockedObject::pwrState() == Enums::PwrState::CLK_GATED && + powerGatingOnIdle) { assert(!enterPwrGatingEvent.scheduled()); // Schedule a power gating event when clock gated for the specified // amount of time @@ -536,8 +538,12 @@ BaseCPU::suspendContext(ThreadID thread_num) // All CPU threads suspended, enter lower power state for the CPU ClockedObject::pwrState(Enums::PwrState::CLK_GATED); - //Schedule power gating event when clock gated for a configurable cycles - schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency)); + // If pwrGatingLatency is set to 0 then this mechanism is disabled + if (powerGatingOnIdle) { + // Schedule power gating event when clock gated for pwrGatingLatency + // cycles + schedule(enterPwrGatingEvent, clockEdge(pwrGatingLatency)); + } } void diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 7039fcfbc..13c56a945 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -588,10 +588,13 @@ class BaseCPU : public MemObject bool waitForRemoteGDB() const; Cycles syscallRetryLatency; + // Enables CPU to enter power gating on a configurable cycle count protected: - const Cycles pwrGatingLatency; void enterPwrGating(); + + const Cycles pwrGatingLatency; + const bool powerGatingOnIdle; EventFunctionWrapper enterPwrGatingEvent; }; |