diff options
| -rw-r--r-- | arch/SConscript | 1 | ||||
| -rw-r--r-- | arch/alpha/ev5.cc | 12 | ||||
| -rw-r--r-- | arch/alpha/isa_traits.hh | 5 | ||||
| -rw-r--r-- | arch/sparc/isa_traits.hh | 14 | ||||
| -rw-r--r-- | cpu/o3/alpha_cpu.hh | 2 | ||||
| -rw-r--r-- | cpu/o3/alpha_cpu_impl.hh | 3 | ||||
| -rw-r--r-- | cpu/o3/cpu.hh | 9 | ||||
| -rw-r--r-- | cpu/o3/regfile.hh | 3 |
8 files changed, 35 insertions, 14 deletions
diff --git a/arch/SConscript b/arch/SConscript index 380cda307..0533261a2 100644 --- a/arch/SConscript +++ b/arch/SConscript @@ -52,7 +52,6 @@ isa_switch_hdrs = Split(''' stacktrace.hh vtophys.hh faults.hh - ev5.hh ''') # Generate the header. target[0] is the full path of the output diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index e313c1a1c..47ada6de6 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -152,6 +152,18 @@ ExecContext::hwrei() return NoFault; } +int +AlphaISA::MiscRegFile::getInstAsid() +{ + return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); +} + +int +AlphaISA::MiscRegFile::getDataAsid() +{ + return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); +} + void AlphaISA::MiscRegFile::clearIprs() { diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 742539e89..be6d5111d 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -166,6 +166,11 @@ extern const int reg_redir[NumIntRegs]; public: MiscReg readReg(int misc_reg); + //These functions should be removed once the simplescalar cpu model + //has been replaced. + int getInstAsid(); + int getDataAsid(); + MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc); Fault setReg(int misc_reg, const MiscReg &val); diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh index 0fdac1662..73daae8a9 100644 --- a/arch/sparc/isa_traits.hh +++ b/arch/sparc/isa_traits.hh @@ -57,7 +57,7 @@ class StaticInstPtr; namespace SparcISA { typedef uint32_t MachInst; - typedef uint64_t Addr; + typedef uint64_t ExtMachInst; typedef uint8_t RegIndex; enum @@ -179,7 +179,7 @@ namespace SparcISA // The control registers, broken out into fields class MiscRegFile { - public: + private: union { uint16_t pstate; // Process State Register @@ -365,6 +365,16 @@ namespace SparcISA } fprsFields; }; + public: + MiscReg readReg(int misc_reg); + + MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc); + + Fault setReg(int misc_reg, const MiscReg &val); + + Fault setRegWithEffect(int misc_reg, const MiscReg &val, + ExecContext *xc); + void serialize(std::ostream & os); void unserialize(Checkpoint * cp, std::string & section); diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index 38c00a3a9..55fde1f1d 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -42,6 +42,8 @@ class AlphaFullCPU : public FullO3CPU<Impl> protected: typedef TheISA::IntReg IntReg; typedef TheISA::MiscReg MiscReg; + typedef TheISA::RegFile RegFile; + typedef TheISA::MiscRegFile MiscRegFile; public: typedef typename Impl::Params Params; diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index a1c659b51..5ab9e6e75 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -26,6 +26,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include "arch/alpha/faults.hh" #include "base/cprintf.hh" #include "base/statistics.hh" #include "base/timebuf.hh" @@ -257,7 +258,7 @@ Fault AlphaFullCPU<Impl>::hwrei() { if (!inPalMode()) - return new UnimplementedOpcodeFault; + return new AlphaISA::UnimplementedOpcodeFault; this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR)); diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index 02908887e..31a1b604b 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -49,11 +49,6 @@ #include "cpu/exec_context.hh" #include "sim/process.hh" -#if FULL_SYSTEM -#include "arch/ev5.hh" -using namespace EV5; -#endif - class FunctionalMemory; class Process; @@ -152,11 +147,11 @@ class FullO3CPU : public BaseFullCPU /** Get instruction asid. */ int getInstAsid() - { return ITB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_ITB_ASN)); } + { return regFile.miscRegs.getInstAsid(); } /** Get data asid. */ int getDataAsid() - { return DTB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_DTB_ASN)); } + { return regFile.miscRegs.getDataAsid(); } #else bool validInstAddr(Addr addr) { return thread[0]->validInstAddr(addr); } diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index 03ad2da46..1e6e10f29 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -38,10 +38,8 @@ #include "cpu/o3/comm.hh" #if FULL_SYSTEM -#include "arch/ev5.hh" #include "kern/kernel_stats.hh" -using namespace EV5; #endif // This really only depends on the ISA, and not the Impl. It might be nicer @@ -237,7 +235,6 @@ class PhysRegFile private: // This is ISA specifc stuff; remove it eventually once ISAImpl is used // IntReg palregs[NumIntRegs]; // PAL shadow registers - InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs int intrflag; // interrupt flag bool pal_shadow; // using pal_shadow registers #endif |