diff options
| -rw-r--r-- | src/arch/arm/isa/decoder/arm.isa | 46 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/data.isa | 151 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/formats.isa | 3 |
3 files changed, 156 insertions, 44 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa index eeab247d7..8a5ba3e43 100644 --- a/src/arch/arm/isa/decoder/arm.isa +++ b/src/arch/arm/isa/decoder/arm.isa @@ -93,24 +93,7 @@ format DataOp { 0xb, 0xd, 0xf: AddrMode3::addrMode3(); } 0: decode IS_MISC { - 0: decode OPCODE { - 0x0: and({{ Rd = resTemp = Rn & op2; }}); - 0x1: eor({{ Rd = resTemp = Rn ^ op2; }}); - 0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub); - 0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb); - 0x4: add({{ Rd = resTemp = Rn + op2; }}, add); - 0x5: adc({{ Rd = resTemp = Rn + op2 + CondCodes<29:>; }}, add); - 0x6: sbc({{ Rd = resTemp = Rn - op2 - !CondCodes<29:>; }}, sub); - 0x7: rsc({{ Rd = resTemp = op2 - Rn - !CondCodes<29:>; }}, rsb); - 0x8: tst({{ resTemp = Rn & op2; }}); - 0x9: teq({{ resTemp = Rn ^ op2; }}); - 0xa: cmp({{ resTemp = Rn - op2; }}, sub); - 0xb: cmn({{ resTemp = Rn + op2; }}, add); - 0xc: orr({{ Rd = resTemp = Rn | op2; }}); - 0xd: mov({{ Rd = resTemp = op2; }}); - 0xe: bic({{ Rd = resTemp = Rn & ~op2; }}); - 0xf: mvn({{ Rd = resTemp = ~op2; }}); - } + 0: ArmDataProcReg::armDataProcReg(); 1: decode MISC_OPCODE { 0x0: decode OPCODE { 0x8: PredOp::mrs_cpsr({{ @@ -195,32 +178,7 @@ format DataOp { } } 0x1: decode IS_MISC { - 0: decode OPCODE { - format DataImmOp { - 0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }}); - 0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }}); - 0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub); - 0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb); - 0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add); - 0x5: adci({{ - Rd = resTemp = Rn + rotated_imm + CondCodes<29:>; - }}, add); - 0x6: sbci({{ - Rd = resTemp = Rn -rotated_imm - !CondCodes<29:>; - }}, sub); - 0x7: rsci({{ - Rd = resTemp = rotated_imm - Rn - !CondCodes<29:>; - }}, rsb); - 0x8: tsti({{ resTemp = Rn & rotated_imm; }}); - 0x9: teqi({{ resTemp = Rn ^ rotated_imm; }}); - 0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub); - 0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add); - 0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }}); - 0xd: movi({{ Rd = resTemp = rotated_imm; }}); - 0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }}); - 0xf: mvni({{ Rd = resTemp = ~rotated_imm; }}); - } - } + 0: ArmDataProcImm::armDataProcImm(); 1: decode OPCODE { // The following two instructions aren't supposed to be defined 0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }}); diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa new file mode 100644 index 000000000..37a10f160 --- /dev/null +++ b/src/arch/arm/isa/formats/data.isa @@ -0,0 +1,151 @@ +// Copyright (c) 2010 ARM Limited +// All rights reserved +// +// The license below extends only to copyright in the software and shall +// not be construed as granting a license to any other intellectual +// property including but not limited to intellectual property relating +// to a hardware implementation of the functionality of the software +// licensed hereunder. You may use the software subject to the license +// terms below provided that you ensure that this notice is replicated +// unmodified and in its entirety in all distributions of the software, +// modified or unmodified, in source code or in binary form. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Gabe Black + +def format ArmDataProcReg() {{ + instDecode = ''' + case %(opcode)#x: + if (immShift) { + if (setCc) { + return new %(className)sDRegCc(machInst, + rd, rn, rm, imm5, type); + } else { + return new %(className)sDReg(machInst, + rd, rn, rm, imm5, type); + } + } else { + if (setCc) { + return new %(className)sDRegRegCc(machInst, + rd, rn, rm, rs, type); + } else { + return new %(className)sDRegReg(machInst, + rd, rn, rm, rs, type); + } + } + break; + ''' + + def instCode(opcode, mnem): + global instDecode + return instDecode % { "className": mnem.capitalize(), + "opcode": opcode } + + decode_block = ''' + { + const bool immShift = (bits(machInst, 4) == 0); + const bool setCc = (bits(machInst, 20) == 1); + const uint32_t imm5 = bits(machInst, 11, 7); + const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5); + const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; + const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; + const IntRegIndex rm = (IntRegIndex)(uint32_t)RM; + const IntRegIndex rs = (IntRegIndex)(uint32_t)RS; + switch (OPCODE) { + ''' + decode_block += instCode(0x0, "and") + decode_block += instCode(0x1, "eor") + decode_block += instCode(0x2, "sub") + decode_block += instCode(0x3, "rsb") + decode_block += instCode(0x4, "add") + decode_block += instCode(0x5, "adc") + decode_block += instCode(0x6, "sbc") + decode_block += instCode(0x7, "rsc") + decode_block += instCode(0x8, "tst") + decode_block += instCode(0x9, "teq") + decode_block += instCode(0xa, "cmp") + decode_block += instCode(0xb, "cmn") + decode_block += instCode(0xc, "orr") + decode_block += instCode(0xd, "mov") + decode_block += instCode(0xe, "bic") + decode_block += instCode(0xf, "mvn") + decode_block += ''' + default: + return new Unknown(machInst); + } + } + ''' +}}; + +def format ArmDataProcImm() {{ + instDecode = ''' + case %(opcode)#x: + if (setCc) { + return new %(className)sDImmCc(machInst, rd, rn, imm, rotC); + } else { + return new %(className)sDImm(machInst, rd, rn, imm, rotC); + } + break; + ''' + + def instCode(opcode, mnem): + global instDecode + return instDecode % { "className": mnem.capitalize(), + "opcode": opcode } + + decode_block = ''' + { + const bool setCc = (bits(machInst, 20) == 1); + const uint32_t unrotated = bits(machInst, 7, 0); + const uint32_t rotation = (bits(machInst, 11, 8) << 1); + const bool rotC = (rotation != 0); + const uint32_t imm = rotate_imm(unrotated, rotation); + const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; + const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; + switch (OPCODE) { + ''' + decode_block += instCode(0x0, "and") + decode_block += instCode(0x1, "eor") + decode_block += instCode(0x2, "sub") + decode_block += instCode(0x3, "rsb") + decode_block += instCode(0x4, "add") + decode_block += instCode(0x5, "adc") + decode_block += instCode(0x6, "sbc") + decode_block += instCode(0x7, "rsc") + decode_block += instCode(0x8, "tst") + decode_block += instCode(0x9, "teq") + decode_block += instCode(0xa, "cmp") + decode_block += instCode(0xb, "cmn") + decode_block += instCode(0xc, "orr") + decode_block += instCode(0xd, "mov") + decode_block += instCode(0xe, "bic") + decode_block += instCode(0xf, "mvn") + decode_block += ''' + default: + return new Unknown(machInst); + } + } + ''' +}}; diff --git a/src/arch/arm/isa/formats/formats.isa b/src/arch/arm/isa/formats/formats.isa index 59258f2d6..87383c26c 100644 --- a/src/arch/arm/isa/formats/formats.isa +++ b/src/arch/arm/isa/formats/formats.isa @@ -67,3 +67,6 @@ //Include the unknown format ##include "unknown.isa" + +//Include the formats for data processing instructions +##include "data.isa" |