diff options
65 files changed, 2211 insertions, 1227 deletions
diff --git a/configs/common/cpu2000.py b/configs/common/cpu2000.py index 7dc7a7afe..59799eb49 100644 --- a/configs/common/cpu2000.py +++ b/configs/common/cpu2000.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -104,6 +104,8 @@ class Benchmark(object): # dirs for input & output files for this input set inputs_dir = joinpath(data_dir, input_set, 'input') outputs_dir = joinpath(data_dir, input_set, 'output') + # keep around which input set was specified + self.input_set = input_set if not isdir(inputs_dir): raise AttributeError, '%s not found' % inputs_dir @@ -619,6 +621,8 @@ class vortex(Benchmark): def __init__(self, isa, os, input_set): if isa == 'alpha': self.endian = 'lendian' + elif (isa == 'sparc' or isa == 'sparc32'): + self.endian = 'bendian' else: raise AttributeError, "unknown ISA %s" % isa diff --git a/src/SConscript b/src/SConscript index c93605ff7..9d7248213 100644 --- a/src/SConscript +++ b/src/SConscript @@ -131,15 +131,19 @@ base_sources = Split(''' mem/cache/cache_builder.cc python/swig/init.cc + python/swig/core_wrap.cc python/swig/debug_wrap.cc - python/swig/main_wrap.cc python/swig/event_wrap.cc python/swig/random_wrap.cc + python/swig/sim_object_wrap.cc python/swig/stats_wrap.cc python/swig/trace_wrap.cc python/swig/pyevent.cc + python/swig/pyobject.cc + sim/async.cc sim/builder.cc + sim/core.cc sim/debug.cc sim/eventq.cc sim/faults.cc @@ -149,6 +153,7 @@ base_sources = Split(''' sim/serialize.cc sim/sim_events.cc sim/sim_object.cc + sim/simulate.cc sim/startup.cc sim/stat_control.cc sim/system.cc diff --git a/src/arch/alpha/linux/process.hh b/src/arch/alpha/linux/process.hh index 2076f6339..cb22f521b 100644 --- a/src/arch/alpha/linux/process.hh +++ b/src/arch/alpha/linux/process.hh @@ -53,9 +53,6 @@ class AlphaLinuxProcess : public AlphaLiveProcess virtual SyscallDesc* getDesc(int callnum); - /// The target system's hostname. - static const char *hostname; - /// Array of syscall descriptors, indexed by call number. static SyscallDesc syscallDescs[]; diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 39500df36..9b63c8842 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1124,9 +1124,12 @@ def buildOperandTypeMap(userDict, lineno): ctype = 'float' elif size == 64: ctype = 'double' - elif desc == 'twin int': + elif desc == 'twin64 int': is_signed = 0 ctype = 'Twin64_t' + elif desc == 'twin32 int': + is_signed = 0 + ctype = 'Twin32_t' if ctype == '': error(lineno, 'Unrecognized type description "%s" in userDict') operandTypeMap[ext] = (size, ctype, is_signed) @@ -1159,7 +1162,7 @@ class Operand(object): # template must be careful not to use it if it doesn't apply. if self.isMem(): self.mem_acc_size = self.makeAccSize() - if self.ctype == 'Twin64_t': + if self.ctype in ['Twin32_t', 'Twin64_t']: self.mem_acc_type = 'Twin' else: self.mem_acc_type = 'uint' @@ -1392,7 +1395,7 @@ class MemOperand(Operand): # Note that initializations in the declarations are solely # to avoid 'uninitialized variable' errors from the compiler. # Declare memory data variable. - if self.ctype == 'Twin64_t': + if self.ctype in ['Twin32_t','Twin64_t']: return "%s %s; %s.a = 0; %s.b = 0;\n" % (self.ctype, self.base_name, self.base_name, self.base_name) c = '%s %s = 0;\n' % (self.ctype, self.base_name) diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index 8ecb6e3df..b1a6ae919 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -660,6 +660,26 @@ void FillNNormal::invoke(ThreadContext *tc) tc->setNextNPC(fillStart + 2*sizeof(MachInst)); } +void TrapInstruction::invoke(ThreadContext *tc) +{ + //In SE, this mechanism is how the process requests a service from the + //operating system. We'll get the process object from the thread context + //and let it service the request. + + Process *p = tc->getProcessPtr(); + + SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); + assert(lp); + + lp->handleTrap(_n, tc); + + //We need to explicitly advance the pc, since that's not done for us + //on a faulting instruction + tc->setPC(tc->readNextPC()); + tc->setNextPC(tc->readNextNPC()); + tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst)); +} + void PageTableFault::invoke(ThreadContext *tc) { Process *p = tc->getProcessPtr(); diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh index cb0303334..0ba897e67 100644 --- a/src/arch/sparc/faults.hh +++ b/src/arch/sparc/faults.hh @@ -248,9 +248,12 @@ class FillNOther : public EnumeratedFault<FillNOther> class TrapInstruction : public EnumeratedFault<TrapInstruction> { - public: TrapInstruction(uint32_t n) : EnumeratedFault<TrapInstruction>(n) {;} + //In SE, trap instructions are requesting services from the OS. +#if !FULL_SYSTEM + void invoke(ThreadContext * tc); +#endif }; #if !FULL_SYSTEM diff --git a/src/arch/sparc/handlers.hh b/src/arch/sparc/handlers.hh new file mode 100644 index 000000000..ce5b69427 --- /dev/null +++ b/src/arch/sparc/handlers.hh @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2003-2004 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_SPARC_HANDLERS_HH__ +#define __ARCH_SPARC_HANDLERS_HH__ + +#include "arch/sparc/isa_traits.hh" +#include "arch/sparc/types.hh" +#include "sim/byteswap.hh" + +namespace SparcISA { + +//We only use 19 instructions for the trap handlers, but there would be +//space for 32 in a real SPARC trap table. +const int numFillInsts = 32; +const int numSpillInsts = 32; + +const MachInst fillHandler64[numFillInsts] = +{ + htog(0x87802018), //wr %g0, ASI_AIUP, %asi + htog(0xe0dba7ff), //ldxa [%sp + BIAS + (0*8)] %asi, %l0 + htog(0xe2dba807), //ldxa [%sp + BIAS + (1*8)] %asi, %l1 + htog(0xe4dba80f), //ldxa [%sp + BIAS + (2*8)] %asi, %l2 + htog(0xe6dba817), //ldxa [%sp + BIAS + (3*8)] %asi, %l3 + htog(0xe8dba81f), //ldxa [%sp + BIAS + (4*8)] %asi, %l4 + htog(0xeadba827), //ldxa [%sp + BIAS + (5*8)] %asi, %l5 + htog(0xecdba82f), //ldxa [%sp + BIAS + (6*8)] %asi, %l6 + htog(0xeedba837), //ldxa [%sp + BIAS + (7*8)] %asi, %l7 + htog(0xf0dba83f), //ldxa [%sp + BIAS + (8*8)] %asi, %i0 + htog(0xf2dba847), //ldxa [%sp + BIAS + (9*8)] %asi, %i1 + htog(0xf4dba84f), //ldxa [%sp + BIAS + (10*8)] %asi, %i2 + htog(0xf6dba857), //ldxa [%sp + BIAS + (11*8)] %asi, %i3 + htog(0xf8dba85f), //ldxa [%sp + BIAS + (12*8)] %asi, %i4 + htog(0xfadba867), //ldxa [%sp + BIAS + (13*8)] %asi, %i5 + htog(0xfcdba86f), //ldxa [%sp + BIAS + (14*8)] %asi, %i6 + htog(0xfedba877), //ldxa [%sp + BIAS + (15*8)] %asi, %i7 + htog(0x83880000), //restored + htog(0x83F00000), //retry + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000) //illtrap +}; + +const MachInst fillHandler32[numFillInsts] = +{ + htog(0x87802018), //wr %g0, ASI_AIUP, %asi + htog(0xe083a000), //lduwa [%sp + (0*4)] %asi, %l0 + htog(0xe283a004), //lduwa [%sp + (1*4)] %asi, %l1 + htog(0xe483a008), //lduwa [%sp + (2*4)] %asi, %l2 + htog(0xe683a00c), //lduwa [%sp + (3*4)] %asi, %l3 + htog(0xe883a010), //lduwa [%sp + (4*4)] %asi, %l4 + htog(0xea83a014), //lduwa [%sp + (5*4)] %asi, %l5 + htog(0xec83a018), //lduwa [%sp + (6*4)] %asi, %l6 + htog(0xee83a01c), //lduwa [%sp + (7*4)] %asi, %l7 + htog(0xf083a020), //lduwa [%sp + (8*4)] %asi, %i0 + htog(0xf283a024), //lduwa [%sp + (9*4)] %asi, %i1 + htog(0xf483a028), //lduwa [%sp + (10*4)] %asi, %i2 + htog(0xf683a02c), //lduwa [%sp + (11*4)] %asi, %i3 + htog(0xf883a030), //lduwa [%sp + (12*4)] %asi, %i4 + htog(0xfa83a034), //lduwa [%sp + (13*4)] %asi, %i5 + htog(0xfc83a038), //lduwa [%sp + (14*4)] %asi, %i6 + htog(0xfe83a03c), //lduwa [%sp + (15*4)] %asi, %i7 + htog(0x83880000), //restored + htog(0x83F00000), //retry + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000) //illtrap +}; + +const MachInst spillHandler64[numSpillInsts] = +{ + htog(0x87802018), //wr %g0, ASI_AIUP, %asi + htog(0xe0f3a7ff), //stxa %l0, [%sp + BIAS + (0*8)] %asi + htog(0xe2f3a807), //stxa %l1, [%sp + BIAS + (1*8)] %asi + htog(0xe4f3a80f), //stxa %l2, [%sp + BIAS + (2*8)] %asi + htog(0xe6f3a817), //stxa %l3, [%sp + BIAS + (3*8)] %asi + htog(0xe8f3a81f), //stxa %l4, [%sp + BIAS + (4*8)] %asi + htog(0xeaf3a827), //stxa %l5, [%sp + BIAS + (5*8)] %asi + htog(0xecf3a82f), //stxa %l6, [%sp + BIAS + (6*8)] %asi + htog(0xeef3a837), //stxa %l7, [%sp + BIAS + (7*8)] %asi + htog(0xf0f3a83f), //stxa %i0, [%sp + BIAS + (8*8)] %asi + htog(0xf2f3a847), //stxa %i1, [%sp + BIAS + (9*8)] %asi + htog(0xf4f3a84f), //stxa %i2, [%sp + BIAS + (10*8)] %asi + htog(0xf6f3a857), //stxa %i3, [%sp + BIAS + (11*8)] %asi + htog(0xf8f3a85f), //stxa %i4, [%sp + BIAS + (12*8)] %asi + htog(0xfaf3a867), //stxa %i5, [%sp + BIAS + (13*8)] %asi + htog(0xfcf3a86f), //stxa %i6, [%sp + BIAS + (14*8)] %asi + htog(0xfef3a877), //stxa %i7, [%sp + BIAS + (15*8)] %asi + htog(0x81880000), //saved + htog(0x83F00000), //retry + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000) //illtrap +}; + +const MachInst spillHandler32[numSpillInsts] = +{ + htog(0x87802018), //wr %g0, ASI_AIUP, %asi + htog(0xe0a3a000), //stwa %l0, [%sp + (0*4)] %asi + htog(0xe2a3a004), //stwa %l1, [%sp + (1*4)] %asi + htog(0xe4a3a008), //stwa %l2, [%sp + (2*4)] %asi + htog(0xe6a3a00c), //stwa %l3, [%sp + (3*4)] %asi + htog(0xe8a3a010), //stwa %l4, [%sp + (4*4)] %asi + htog(0xeaa3a014), //stwa %l5, [%sp + (5*4)] %asi + htog(0xeca3a018), //stwa %l6, [%sp + (6*4)] %asi + htog(0xeea3a01c), //stwa %l7, [%sp + (7*4)] %asi + htog(0xf0a3a020), //stwa %i0, [%sp + (8*4)] %asi + htog(0xf2a3a024), //stwa %i1, [%sp + (9*4)] %asi + htog(0xf4a3a028), //stwa %i2, [%sp + (10*4)] %asi + htog(0xf6a3a02c), //stwa %i3, [%sp + (11*4)] %asi + htog(0xf8a3a030), //stwa %i4, [%sp + (12*4)] %asi + htog(0xfaa3a034), //stwa %i5, [%sp + (13*4)] %asi + htog(0xfca3a038), //stwa %i6, [%sp + (14*4)] %asi + htog(0xfea3a03c), //stwa %i7, [%sp + (15*4)] %asi + htog(0x81880000), //saved + htog(0x83F00000), //retry + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000), //illtrap + htog(0x00000000) //illtrap +}; + +} // namespace SparcISA +#endif // __ARCH_SPARC_HANDLERS_HH__ diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 0382aa35e..2e85e1274 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -1009,25 +1009,25 @@ decode OP default Unknown::unknown() 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 0x81: FailUnimpl::siam(); } -#if FULL_SYSTEM // M5 special opcodes use the reserved IMPDEP2A opcode space 0x37: decode M5FUNC { - // we have 7 bits of space here to play with... - 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); - }}, No_OpClass, IsNonSpeculative); - 0x50: m5readfile({{ - O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); - }}, IsNonSpeculative); - 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); - }}, IsNonSpeculative); - 0x54: m5panic({{ - panic("M5 panic instruction called at pc=%#x.", xc->readPC()); - }}, No_OpClass, IsNonSpeculative); - - } -#else - 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); +#if FULL_SYSTEM + format BasicOperate { + // we have 7 bits of space here to play with... + 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); + }}, No_OpClass, IsNonSpeculative); + 0x50: m5readfile({{ + O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); + }}, IsNonSpeculative); + 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); + }}, IsNonSpeculative); + 0x54: m5panic({{ + panic("M5 panic instruction called at pc=%#x.", xc->readPC()); + }}, No_OpClass, IsNonSpeculative); + } #endif + default: Trap::impdep2({{fault = new IllegalInstruction;}}); + } 0x38: Branch::jmpl({{ Addr target = Rs1 + Rs2_or_imm13; if(target & 0x3) @@ -1071,27 +1071,17 @@ decode OP default Unknown::unknown() 0x0: Trap::tcci({{ if(passesCondition(Ccr<3:0>, COND2)) { -#if FULL_SYSTEM int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); fault = new TrapInstruction(lTrapNum); -#else - DPRINTF(Sparc, "The syscall number is %d\n", R1); - xc->syscall(R1); -#endif } }}, IsSerializeAfter, IsNonSpeculative); 0x2: Trap::tccx({{ if(passesCondition(Ccr<7:4>, COND2)) { -#if FULL_SYSTEM int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); fault = new TrapInstruction(lTrapNum); -#else - DPRINTF(Sparc, "The syscall number is %d\n", R1); - xc->syscall(R1); -#endif } }}, IsSerializeAfter, IsNonSpeculative); } @@ -1170,9 +1160,8 @@ decode OP default Unknown::unknown() 0x01: ldub({{Rd = Mem.ub;}}); 0x02: lduh({{Rd = Mem.uhw;}}); 0x03: ldtw({{ - uint64_t val = Mem.udw; - RdLow = val<31:0>; - RdHigh = val<63:32>; + RdLow = (Mem.tuw).a; + RdHigh = (Mem.tuw).b; }}); } format Store { @@ -1260,9 +1249,8 @@ decode OP default Unknown::unknown() {{RdLow.udw = (Mem.tudw).a; RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); default: ldtwa({{ - uint64_t val = Mem.udw; - RdLow = val<31:0>; - RdHigh = val<63:32>; + RdLow = (Mem.tuw).a; + RdHigh = (Mem.tuw).b; }}, {{EXT_ASI}}); } } diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 092544aab..038919bd1 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -37,7 +37,8 @@ def operand_types {{ 'uw' : ('unsigned int', 32), 'sdw' : ('signed int', 64), 'udw' : ('unsigned int', 64), - 'tudw' : ('twin int', 64), + 'tudw' : ('twin64 int', 64), + 'tuw' : ('twin32 int', 32), 'sf' : ('float', 32), 'df' : ('float', 64), 'qf' : ('float', 128) diff --git a/src/arch/sparc/linux/process.cc b/src/arch/sparc/linux/process.cc index 565975fe0..10cde3af8 100644 --- a/src/arch/sparc/linux/process.cc +++ b/src/arch/sparc/linux/process.cc @@ -54,7 +54,7 @@ unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process, strcpy(name->sysname, "Linux"); strcpy(name->nodename, "m5.eecs.umich.edu"); - strcpy(name->release, "2.4.20"); + strcpy(name->release, "2.6.12"); strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); strcpy(name->machine, "sparc"); @@ -141,7 +141,7 @@ SyscallDesc SparcLinuxProcess::syscallDescs[] = { /* 41 */ SyscallDesc("dup", unimplementedFunc), /* 42 */ SyscallDesc("pipe", pipePseudoFunc), /* 43 */ SyscallDesc("times", unimplementedFunc), - /* 44 */ SyscallDesc("getuid32", unimplementedFunc), + /* 44 */ SyscallDesc("getuid32", getuidFunc), /* 45 */ SyscallDesc("umount2", unimplementedFunc), /* 46 */ SyscallDesc("setgid", unimplementedFunc), /* 47 */ SyscallDesc("getgid", getgidFunc), @@ -150,7 +150,7 @@ SyscallDesc SparcLinuxProcess::syscallDescs[] = { /* 50 */ SyscallDesc("getegid", getegidFunc), /* 51 */ SyscallDesc("acct", unimplementedFunc), /* 52 */ SyscallDesc("memory_ordering", unimplementedFunc), - /* 53 */ SyscallDesc("getgid32", unimplementedFunc), + /* 53 */ SyscallDesc("getgid32", getgidFunc), /* 54 */ SyscallDesc("ioctl", unimplementedFunc), /* 55 */ SyscallDesc("reboot", unimplementedFunc), /* 56 */ SyscallDesc("mmap2", unimplementedFunc), @@ -160,14 +160,14 @@ SyscallDesc SparcLinuxProcess::syscallDescs[] = { /* 60 */ SyscallDesc("umask", unimplementedFunc), /* 61 */ SyscallDesc("chroot", unimplementedFunc), /* 62 */ SyscallDesc("fstat", fstatFunc<SparcLinux>), - /* 63 */ SyscallDesc("fstat64", unimplementedFunc), + /* 63 */ SyscallDesc("fstat64", fstatFunc<SparcLinux>), /* 64 */ SyscallDesc("getpagesize", unimplementedFunc), /* 65 */ SyscallDesc("msync", unimplementedFunc), /* 66 */ SyscallDesc("vfork", unimplementedFunc), /* 67 */ SyscallDesc("pread64", unimplementedFunc), /* 68 */ SyscallDesc("pwrite64", unimplementedFunc), - /* 69 */ SyscallDesc("geteuid32", unimplementedFunc), - /* 70 */ SyscallDesc("getdgid32", unimplementedFunc), + /* 69 */ SyscallDesc("geteuid32", geteuidFunc), + /* 70 */ SyscallDesc("getegid32", getegidFunc), /* 71 */ SyscallDesc("mmap", mmapFunc<SparcLinux>), /* 72 */ SyscallDesc("setreuid32", unimplementedFunc), /* 73 */ SyscallDesc("munmap", munmapFunc), @@ -184,7 +184,7 @@ SyscallDesc SparcLinuxProcess::syscallDescs[] = { /* 84 */ SyscallDesc("ftruncate64", unimplementedFunc), /* 85 */ SyscallDesc("swapon", unimplementedFunc), /* 86 */ SyscallDesc("getitimer", unimplementedFunc), - /* 87 */ SyscallDesc("setuid32", unimplementedFunc), + /* 87 */ SyscallDesc("setuid32", setuidFunc), /* 88 */ SyscallDesc("sethostname", unimplementedFunc), /* 89 */ SyscallDesc("setgid32", unimplementedFunc), /* 90 */ SyscallDesc("dup2", unimplementedFunc), @@ -333,7 +333,7 @@ SyscallDesc SparcLinuxProcess::syscallDescs[] = { /* 233 */ SyscallDesc("stime", unimplementedFunc), /* 234 */ SyscallDesc("statfs64", unimplementedFunc), /* 235 */ SyscallDesc("fstatfs64", unimplementedFunc), - /* 236 */ SyscallDesc("_llseek", unimplementedFunc), + /* 236 */ SyscallDesc("_llseek", _llseekFunc), /* 237 */ SyscallDesc("mlock", unimplementedFunc), /* 238 */ SyscallDesc("munlock", unimplementedFunc), /* 239 */ SyscallDesc("mlockall", unimplementedFunc), @@ -383,34 +383,79 @@ SyscallDesc SparcLinuxProcess::syscallDescs[] = { /* 283 */ SyscallDesc("keyctl", unimplementedFunc) }; -SparcLinuxProcess::SparcLinuxProcess(const std::string &name, - ObjectFile *objFile, - System * system, - int stdin_fd, - int stdout_fd, - int stderr_fd, - std::vector<std::string> &argv, - std::vector<std::string> &envp, - const std::string &cwd, - uint64_t _uid, uint64_t _euid, - uint64_t _gid, uint64_t _egid, - uint64_t _pid, uint64_t _ppid) - : SparcLiveProcess(name, objFile, system, - stdin_fd, stdout_fd, stderr_fd, argv, envp, cwd, - _uid, _euid, _gid, _egid, _pid, _ppid), - Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)) +SyscallDesc* +SparcLinuxProcess::getDesc(int callnum) +{ + if (callnum < 0 || callnum > Num_Syscall_Descs) + return NULL; + return &syscallDescs[callnum]; +} + + + +SparcLinuxProcess::SparcLinuxProcess() : + Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)) { // The sparc syscall table must be <= 284 entries because that is all there // is space for. assert(Num_Syscall_Descs <= 284); } +Sparc32LinuxProcess::Sparc32LinuxProcess(const std::string &name, + ObjectFile *objFile, + System * system, + int stdin_fd, + int stdout_fd, + int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp, + const std::string &cwd, + uint64_t _uid, uint64_t _euid, + uint64_t _gid, uint64_t _egid, + uint64_t _pid, uint64_t _ppid) + : Sparc32LiveProcess(name, objFile, system, + stdin_fd, stdout_fd, stderr_fd, argv, envp, cwd, + _uid, _euid, _gid, _egid, _pid, _ppid) +{} +void Sparc32LinuxProcess::handleTrap(int trapNum, ThreadContext *tc) +{ + switch(trapNum) + { + case 0x10: //Linux 32 bit syscall trap + tc->syscall(tc->readIntReg(1)); + break; + default: + SparcLiveProcess::handleTrap(trapNum, tc); + } +} -SyscallDesc* -SparcLinuxProcess::getDesc(int callnum) +Sparc64LinuxProcess::Sparc64LinuxProcess(const std::string &name, + ObjectFile *objFile, + System * system, + int stdin_fd, + int stdout_fd, + int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp, + const std::string &cwd, + uint64_t _uid, uint64_t _euid, + uint64_t _gid, uint64_t _egid, + uint64_t _pid, uint64_t _ppid) + : Sparc64LiveProcess(name, objFile, system, + stdin_fd, stdout_fd, stderr_fd, argv, envp, cwd, + _uid, _euid, _gid, _egid, _pid, _ppid) +{} + +void Sparc64LinuxProcess::handleTrap(int trapNum, ThreadContext *tc) { - if (callnum < 0 || callnum > Num_Syscall_Descs) - return NULL; - return &syscallDescs[callnum]; + switch(trapNum) + { + case 0x10: //Linux 32 bit syscall trap + case 0x6d: //Linux 64 bit syscall trap + tc->syscall(tc->readIntReg(1)); + break; + default: + SparcLiveProcess::handleTrap(trapNum, tc); + } } diff --git a/src/arch/sparc/linux/process.hh b/src/arch/sparc/linux/process.hh index e212de973..e3373bb6b 100644 --- a/src/arch/sparc/linux/process.hh +++ b/src/arch/sparc/linux/process.hh @@ -38,12 +38,28 @@ namespace SparcISA { +//This contains all of the common elements of a SPARC Linux process which +//are not shared by other operating systems. The rest come from the common +//SPARC process class. +class SparcLinuxProcess +{ + public: + SparcLinuxProcess(); + + /// Array of syscall descriptors, indexed by call number. + static SyscallDesc syscallDescs[]; + + SyscallDesc* getDesc(int callnum); + + const int Num_Syscall_Descs; +}; + /// A process with emulated SPARC/Linux syscalls. -class SparcLinuxProcess : public SparcLiveProcess +class Sparc32LinuxProcess : public SparcLinuxProcess, public Sparc32LiveProcess { public: /// Constructor. - SparcLinuxProcess(const std::string &name, + Sparc32LinuxProcess(const std::string &name, ObjectFile *objFile, System * system, int stdin_fd, int stdout_fd, int stderr_fd, @@ -54,19 +70,40 @@ class SparcLinuxProcess : public SparcLiveProcess uint64_t _gid, uint64_t _egid, uint64_t _pid, uint64_t _ppid); - virtual SyscallDesc* getDesc(int callnum); + SyscallDesc* getDesc(int callnum) + { + return SparcLinuxProcess::getDesc(callnum); + } - /// The target system's hostname. - static const char *hostname; + void handleTrap(int trapNum, ThreadContext *tc); +}; - /// Array of syscall descriptors, indexed by call number. - static SyscallDesc syscallDescs[]; +/// A process with emulated 32 bit SPARC/Linux syscalls. +class Sparc64LinuxProcess : public SparcLinuxProcess, public Sparc64LiveProcess +{ + public: + /// Constructor. + Sparc64LinuxProcess(const std::string &name, + ObjectFile *objFile, + System * system, + int stdin_fd, int stdout_fd, int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp, + const std::string &cwd, + uint64_t _uid, uint64_t _euid, + uint64_t _gid, uint64_t _egid, + uint64_t _pid, uint64_t _ppid); - const int Num_Syscall_Descs; + SyscallDesc* getDesc(int callnum) + { + return SparcLinuxProcess::getDesc(callnum); + } + + void handleTrap(int trapNum, ThreadContext *tc); }; SyscallReturn getresuidFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc); } // namespace SparcISA -#endif // __ALPHA_LINUX_PROCESS_HH__ +#endif // __SPARC_LINUX_PROCESS_HH__ diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 1e639b9a5..c3b833562 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -30,6 +30,7 @@ */ #include "arch/sparc/asi.hh" +#include "arch/sparc/handlers.hh" #include "arch/sparc/isa_traits.hh" #include "arch/sparc/process.hh" #include "arch/sparc/types.hh" @@ -59,14 +60,6 @@ SparcLiveProcess::SparcLiveProcess(const std::string &nm, ObjectFile *objFile, brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); brk_point = roundUp(brk_point, VMPageSize); - // Set up stack. On SPARC Linux, stack goes from the top of memory - // downward, less the hole for the kernel address space. - stack_base = (Addr)0x80000000000ULL; - - // Set up region for mmaps. Tru64 seems to start just above 0 and - // grow up from there. - mmap_start = mmap_end = 0xfffff80000000000ULL; - // Set pointer for next thread stack. Reserve 8M for main stack. next_thread_stack_base = stack_base - (8 * 1024 * 1024); @@ -75,10 +68,22 @@ SparcLiveProcess::SparcLiveProcess(const std::string &nm, ObjectFile *objFile, spillStart = 0; } +void SparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc) +{ + switch(trapNum) + { + case 0x03: //Flush window trap + warn("Ignoring request to flush register windows.\n"); + break; + default: + panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); + } +} + void -SparcLiveProcess::startup() +Sparc32LiveProcess::startup() { - argsInit(sizeof(IntReg), VMPageSize); + argsInit(32 / 8, VMPageSize); //From the SPARC ABI @@ -117,94 +122,64 @@ SparcLiveProcess::startup() threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY); } -m5_auxv_t buildAuxVect(int64_t type, int64_t val) +void +Sparc64LiveProcess::startup() { - m5_auxv_t result; - result.a_type = TheISA::htog(type); - result.a_val = TheISA::htog(val); - return result; -} + argsInit(sizeof(IntReg), VMPageSize); + + //From the SPARC ABI + + //The process runs in user mode + threadContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02); + + //Setup default FP state + threadContexts[0]->setMiscReg(MISCREG_FSR, 0); -//We only use 19 instructions for the trap handlers, but there would be -//space for 32 in a real SPARC trap table. -const int numFillInsts = 32; -const int numSpillInsts = 32; + threadContexts[0]->setMiscReg(MISCREG_TICK, 0); + // + /* + * Register window management registers + */ + + //No windows contain info from other programs + //threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0); + threadContexts[0]->setIntReg(NumIntArchRegs + 6, 0); + //There are no windows to pop + //threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0); + threadContexts[0]->setIntReg(NumIntArchRegs + 4, 0); + //All windows are available to save into + //threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2); + threadContexts[0]->setIntReg(NumIntArchRegs + 3, NWindows - 2); + //All windows are "clean" + //threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows); + threadContexts[0]->setIntReg(NumIntArchRegs + 5, NWindows); + //Start with register window 0 + threadContexts[0]->setMiscReg(MISCREG_CWP, 0); + //Always use spill and fill traps 0 + //threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0); + threadContexts[0]->setIntReg(NumIntArchRegs + 7, 0); + //Set the trap level to 0 + threadContexts[0]->setMiscReg(MISCREG_TL, 0); + //Set the ASI register to something fixed + threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY); +} -MachInst fillHandler[numFillInsts] = +M5_32_auxv_t::M5_32_auxv_t(int32_t type, int32_t val) { - htog(0x87802018), //wr %g0, ASI_AIUP, %asi - htog(0xe0dba7ff), //ldxa [%sp + BIAS + (0*8)] %asi, %l0 - htog(0xe2dba807), //ldxa [%sp + BIAS + (1*8)] %asi, %l1 - htog(0xe4dba80f), //ldxa [%sp + BIAS + (2*8)] %asi, %l2 - htog(0xe6dba817), //ldxa [%sp + BIAS + (3*8)] %asi, %l3 - htog(0xe8dba81f), //ldxa [%sp + BIAS + (4*8)] %asi, %l4 - htog(0xeadba827), //ldxa [%sp + BIAS + (5*8)] %asi, %l5 - htog(0xecdba82f), //ldxa [%sp + BIAS + (6*8)] %asi, %l6 - htog(0xeedba837), //ldxa [%sp + BIAS + (7*8)] %asi, %l7 - htog(0xf0dba83f), //ldxa [%sp + BIAS + (8*8)] %asi, %i0 - htog(0xf2dba847), //ldxa [%sp + BIAS + (9*8)] %asi, %i1 - htog(0xf4dba84f), //ldxa [%sp + BIAS + (10*8)] %asi, %i2 - htog(0xf6dba857), //ldxa [%sp + BIAS + (11*8)] %asi, %i3 - htog(0xf8dba85f), //ldxa [%sp + BIAS + (12*8)] %asi, %i4 - htog(0xfadba867), //ldxa [%sp + BIAS + (13*8)] %asi, %i5 - htog(0xfcdba86f), //ldxa [%sp + BIAS + (14*8)] %asi, %i6 - htog(0xfedba877), //ldxa [%sp + BIAS + (15*8)] %asi, %i7 - htog(0x83880000), //restored - htog(0x83F00000), //retry - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000) //illtrap -}; - -MachInst spillHandler[numSpillInsts] = + a_type = TheISA::htog(type); + a_val = TheISA::htog(val); +} + +M5_64_auxv_t::M5_64_auxv_t(int64_t type, int64_t val) { - htog(0x87802018), //wr %g0, ASI_AIUP, %asi - htog(0xe0f3a7ff), //stxa %l0, [%sp + BIAS + (0*8)] %asi - htog(0xe2f3a807), //stxa %l1, [%sp + BIAS + (1*8)] %asi - htog(0xe4f3a80f), //stxa %l2, [%sp + BIAS + (2*8)] %asi - htog(0xe6f3a817), //stxa %l3, [%sp + BIAS + (3*8)] %asi - htog(0xe8f3a81f), //stxa %l4, [%sp + BIAS + (4*8)] %asi - htog(0xeaf3a827), //stxa %l5, [%sp + BIAS + (5*8)] %asi - htog(0xecf3a82f), //stxa %l6, [%sp + BIAS + (6*8)] %asi - htog(0xeef3a837), //stxa %l7, [%sp + BIAS + (7*8)] %asi - htog(0xf0f3a83f), //stxa %i0, [%sp + BIAS + (8*8)] %asi - htog(0xf2f3a847), //stxa %i1, [%sp + BIAS + (9*8)] %asi - htog(0xf4f3a84f), //stxa %i2, [%sp + BIAS + (10*8)] %asi - htog(0xf6f3a857), //stxa %i3, [%sp + BIAS + (11*8)] %asi - htog(0xf8f3a85f), //stxa %i4, [%sp + BIAS + (12*8)] %asi - htog(0xfaf3a867), //stxa %i5, [%sp + BIAS + (13*8)] %asi - htog(0xfcf3a86f), //stxa %i6, [%sp + BIAS + (14*8)] %asi - htog(0xfef3a877), //stxa %i7, [%sp + BIAS + (15*8)] %asi - htog(0x81880000), //saved - htog(0x83F00000), //retry - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000), //illtrap - htog(0x00000000) //illtrap -}; + a_type = TheISA::htog(type); + a_val = TheISA::htog(val); +} void -SparcLiveProcess::argsInit(int intSize, int pageSize) +Sparc64LiveProcess::argsInit(int intSize, int pageSize) { + typedef M5_64_auxv_t auxv_t; Process::startup(); string filename; @@ -265,34 +240,34 @@ SparcLiveProcess::argsInit(int intSize, int pageSize) if(elfObject) { //Bits which describe the system hardware capabilities - auxv.push_back(buildAuxVect(SPARC_AT_HWCAP, hwcap)); + auxv.push_back(auxv_t(SPARC_AT_HWCAP, hwcap)); //The system page size - auxv.push_back(buildAuxVect(SPARC_AT_PAGESZ, SparcISA::VMPageSize)); + auxv.push_back(auxv_t(SPARC_AT_PAGESZ, SparcISA::VMPageSize)); //Defined to be 100 in the kernel source. //Frequency at which times() increments - auxv.push_back(buildAuxVect(SPARC_AT_CLKTCK, 100)); + auxv.push_back(auxv_t(SPARC_AT_CLKTCK, 100)); // For statically linked executables, this is the virtual address of the // program header tables if they appear in the executable image - auxv.push_back(buildAuxVect(SPARC_AT_PHDR, elfObject->programHeaderTable())); + auxv.push_back(auxv_t(SPARC_AT_PHDR, elfObject->programHeaderTable())); // This is the size of a program header entry from the elf file. - auxv.push_back(buildAuxVect(SPARC_AT_PHENT, elfObject->programHeaderSize())); + auxv.push_back(auxv_t(SPARC_AT_PHENT, elfObject->programHeaderSize())); // This is the number of program headers from the original elf file. - auxv.push_back(buildAuxVect(SPARC_AT_PHNUM, elfObject->programHeaderCount())); + auxv.push_back(auxv_t(SPARC_AT_PHNUM, elfObject->programHeaderCount())); //This is the address of the elf "interpreter", It should be set //to 0 for regular executables. It should be something else //(not sure what) for dynamic libraries. - auxv.push_back(buildAuxVect(SPARC_AT_BASE, 0)); + auxv.push_back(auxv_t(SPARC_AT_BASE, 0)); //This is hardwired to 0 in the elf loading code in the kernel - auxv.push_back(buildAuxVect(SPARC_AT_FLAGS, 0)); + auxv.push_back(auxv_t(SPARC_AT_FLAGS, 0)); //The entry point to the program - auxv.push_back(buildAuxVect(SPARC_AT_ENTRY, objFile->entryPoint())); + auxv.push_back(auxv_t(SPARC_AT_ENTRY, objFile->entryPoint())); //Different user and group IDs - auxv.push_back(buildAuxVect(SPARC_AT_UID, uid())); - auxv.push_back(buildAuxVect(SPARC_AT_EUID, euid())); - auxv.push_back(buildAuxVect(SPARC_AT_GID, gid())); - auxv.push_back(buildAuxVect(SPARC_AT_EGID, egid())); + auxv.push_back(auxv_t(SPARC_AT_UID, uid())); + auxv.push_back(auxv_t(SPARC_AT_EUID, euid())); + auxv.push_back(auxv_t(SPARC_AT_GID, gid())); + auxv.push_back(auxv_t(SPARC_AT_EGID, egid())); //Whether to enable "secure mode" in the executable - auxv.push_back(buildAuxVect(SPARC_AT_SECURE, 0)); + auxv.push_back(auxv_t(SPARC_AT_SECURE, 0)); } //Figure out how big the initial stack needs to be @@ -419,8 +394,8 @@ SparcLiveProcess::argsInit(int intSize, int pageSize) int spillSize = sizeof(MachInst) * numSpillInsts; fillStart = stack_base; spillStart = fillStart + fillSize; - initVirtMem->writeBlob(fillStart, (uint8_t*)fillHandler, fillSize); - initVirtMem->writeBlob(spillStart, (uint8_t*)spillHandler, spillSize); + initVirtMem->writeBlob(fillStart, (uint8_t*)fillHandler64, fillSize); + initVirtMem->writeBlob(spillStart, (uint8_t*)spillHandler64, spillSize); //Set up the thread context to start running the process threadContexts[0]->setIntReg(ArgumentReg0, argc); @@ -437,3 +412,230 @@ SparcLiveProcess::argsInit(int intSize, int pageSize) // num_processes++; } + +void +Sparc32LiveProcess::argsInit(int intSize, int pageSize) +{ + typedef M5_32_auxv_t auxv_t; + Process::startup(); + + string filename; + if(argv.size() < 1) + filename = ""; + else + filename = argv[0]; + + //Even though this is a 32 bit process, the ABI says we still need to + //maintain double word alignment of the stack pointer. + Addr alignmentMask = ~(8 - 1); + + // load object file into target memory + objFile->loadSections(initVirtMem); + + //These are the auxilliary vector types + enum auxTypes + { + SPARC_AT_HWCAP = 16, + SPARC_AT_PAGESZ = 6, + SPARC_AT_CLKTCK = 17, + SPARC_AT_PHDR = 3, + SPARC_AT_PHENT = 4, + SPARC_AT_PHNUM = 5, + SPARC_AT_BASE = 7, + SPARC_AT_FLAGS = 8, + SPARC_AT_ENTRY = 9, + SPARC_AT_UID = 11, + SPARC_AT_EUID = 12, + SPARC_AT_GID = 13, + SPARC_AT_EGID = 14, + SPARC_AT_SECURE = 23 + }; + + enum hardwareCaps + { + M5_HWCAP_SPARC_FLUSH = 1, + M5_HWCAP_SPARC_STBAR = 2, + M5_HWCAP_SPARC_SWAP = 4, + M5_HWCAP_SPARC_MULDIV = 8, + M5_HWCAP_SPARC_V9 = 16, + //This one should technically only be set + //if there is a cheetah or cheetah_plus tlb, + //but we'll use it all the time + M5_HWCAP_SPARC_ULTRA3 = 32 + }; + + const int64_t hwcap = + M5_HWCAP_SPARC_FLUSH | + M5_HWCAP_SPARC_STBAR | + M5_HWCAP_SPARC_SWAP | + M5_HWCAP_SPARC_MULDIV | + M5_HWCAP_SPARC_V9 | + M5_HWCAP_SPARC_ULTRA3; + + + //Setup the auxilliary vectors. These will already have endian conversion. + //Auxilliary vectors are loaded only for elf formatted executables. + ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); + if(elfObject) + { + //Bits which describe the system hardware capabilities + auxv.push_back(auxv_t(SPARC_AT_HWCAP, hwcap)); + //The system page size + auxv.push_back(auxv_t(SPARC_AT_PAGESZ, SparcISA::VMPageSize)); + //Defined to be 100 in the kernel source. + //Frequency at which times() increments + auxv.push_back(auxv_t(SPARC_AT_CLKTCK, 100)); + // For statically linked executables, this is the virtual address of the + // program header tables if they appear in the executable image + auxv.push_back(auxv_t(SPARC_AT_PHDR, elfObject->programHeaderTable())); + // This is the size of a program header entry from the elf file. + auxv.push_back(auxv_t(SPARC_AT_PHENT, elfObject->programHeaderSize())); + // This is the number of program headers from the original elf file. + auxv.push_back(auxv_t(SPARC_AT_PHNUM, elfObject->programHeaderCount())); + //This is the address of the elf "interpreter", It should be set + //to 0 for regular executables. It should be something else + //(not sure what) for dynamic libraries. + auxv.push_back(auxv_t(SPARC_AT_BASE, 0)); + //This is hardwired to 0 in the elf loading code in the kernel + auxv.push_back(auxv_t(SPARC_AT_FLAGS, 0)); + //The entry point to the program + auxv.push_back(auxv_t(SPARC_AT_ENTRY, objFile->entryPoint())); + //Different user and group IDs + auxv.push_back(auxv_t(SPARC_AT_UID, uid())); + auxv.push_back(auxv_t(SPARC_AT_EUID, euid())); + auxv.push_back(auxv_t(SPARC_AT_GID, gid())); + auxv.push_back(auxv_t(SPARC_AT_EGID, egid())); + //Whether to enable "secure mode" in the executable + auxv.push_back(auxv_t(SPARC_AT_SECURE, 0)); + } + + //Figure out how big the initial stack needs to be + + // The unaccounted for 0 at the top of the stack + int mysterious_size = intSize; + + //This is the name of the file which is present on the initial stack + //It's purpose is to let the user space linker examine the original file. + int file_name_size = filename.size() + 1; + + int env_data_size = 0; + for (int i = 0; i < envp.size(); ++i) { + env_data_size += envp[i].size() + 1; + } + int arg_data_size = 0; + for (int i = 0; i < argv.size(); ++i) { + arg_data_size += argv[i].size() + 1; + } + + //The info_block + int info_block_size = + (file_name_size + + env_data_size + + arg_data_size); + + //Each auxilliary vector is two 8 byte words + int aux_array_size = intSize * 2 * (auxv.size() + 1); + + int envp_array_size = intSize * (envp.size() + 1); + int argv_array_size = intSize * (argv.size() + 1); + + int argc_size = intSize; + int window_save_size = intSize * 16; + + int space_needed = + mysterious_size + + aux_array_size + + envp_array_size + + argv_array_size + + argc_size + + window_save_size; + + stack_min = stack_base - space_needed; + stack_min &= alignmentMask; + stack_size = stack_base - stack_min; + + // map memory + pTable->allocate(roundDown(stack_min, pageSize), + roundUp(stack_size, pageSize)); + + // map out initial stack contents + uint32_t window_save_base = stack_min; + uint32_t argc_base = window_save_base + window_save_size; + uint32_t argv_array_base = argc_base + argc_size; + uint32_t envp_array_base = argv_array_base + argv_array_size; + uint32_t auxv_array_base = envp_array_base + envp_array_size; + //The info block is pushed up against the top of the stack, while + //the rest of the initial stack frame is aligned to an 8 byte boudary. + uint32_t arg_data_base = stack_base - info_block_size; + uint32_t env_data_base = arg_data_base + arg_data_size; + uint32_t file_name_base = env_data_base + env_data_size; + uint32_t mysterious_base = file_name_base + file_name_size; + + DPRINTF(Sparc, "The addresses of items on the initial stack:\n"); + DPRINTF(Sparc, "0x%x - file name\n", file_name_base); + DPRINTF(Sparc, "0x%x - env data\n", env_data_base); + DPRINTF(Sparc, "0x%x - arg data\n", arg_data_base); + DPRINTF(Sparc, "0x%x - auxv array\n", auxv_array_base); + DPRINTF(Sparc, "0x%x - envp array\n", envp_array_base); + DPRINTF(Sparc, "0x%x - argv array\n", argv_array_base); + DPRINTF(Sparc, "0x%x - argc \n", argc_base); + DPRINTF(Sparc, "0x%x - window save\n", window_save_base); + DPRINTF(Sparc, "0x%x - stack min\n", stack_min); + + // write contents to stack + + // figure out argc + uint32_t argc = argv.size(); + uint32_t guestArgc = TheISA::htog(argc); + + //Write out the mysterious 0 + uint64_t mysterious_zero = 0; + initVirtMem->writeBlob(mysterious_base, + (uint8_t*)&mysterious_zero, mysterious_size); + + //Write the file name + initVirtMem->writeString(file_name_base, filename.c_str()); + + //Copy the aux stuff + for(int x = 0; x < auxv.size(); x++) + { + initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize, + (uint8_t*)&(auxv[x].a_type), intSize); + initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize, + (uint8_t*)&(auxv[x].a_val), intSize); + } + //Write out the terminating zeroed auxilliary vector + const uint64_t zero = 0; + initVirtMem->writeBlob(auxv_array_base + 2 * intSize * auxv.size(), + (uint8_t*)&zero, 2 * intSize); + + copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); + copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); + + initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); + + //Stuff the trap handlers into the processes address space. + //Since the stack grows down and is the highest area in the processes + //address space, we can put stuff above it and stay out of the way. + int fillSize = sizeof(MachInst) * numFillInsts; + int spillSize = sizeof(MachInst) * numSpillInsts; + fillStart = stack_base; + spillStart = fillStart + fillSize; + initVirtMem->writeBlob(fillStart, (uint8_t*)fillHandler32, fillSize); + initVirtMem->writeBlob(spillStart, (uint8_t*)spillHandler32, spillSize); + + //Set up the thread context to start running the process + threadContexts[0]->setIntReg(ArgumentReg0, argc); + threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base); + threadContexts[0]->setIntReg(StackPointerReg, stack_min); + + uint32_t prog_entry = objFile->entryPoint(); + threadContexts[0]->setPC(prog_entry); + threadContexts[0]->setNextPC(prog_entry + sizeof(MachInst)); + threadContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst))); + + //Align the "stack_min" to a page boundary. + stack_min = roundDown(stack_min, pageSize); + +// num_processes++; +} diff --git a/src/arch/sparc/process.hh b/src/arch/sparc/process.hh index 1cf7ec224..2512441c6 100644 --- a/src/arch/sparc/process.hh +++ b/src/arch/sparc/process.hh @@ -39,27 +39,13 @@ class ObjectFile; class System; -typedef struct -{ - int64_t a_type; - union { - int64_t a_val; - Addr a_ptr; - Addr a_fcn; - }; -} m5_auxv_t; - class SparcLiveProcess : public LiveProcess { protected: - static const Addr StackBias = 2047; - //The locations of the fill and spill handlers Addr fillStart, spillStart; - std::vector<m5_auxv_t> auxv; - SparcLiveProcess(const std::string &nm, ObjectFile *objFile, System *_system, int stdin_fd, int stdout_fd, int stderr_fd, std::vector<std::string> &argv, @@ -69,11 +55,10 @@ class SparcLiveProcess : public LiveProcess uint64_t _gid, uint64_t _egid, uint64_t _pid, uint64_t _ppid); - void startup(); - public: - void argsInit(int intSize, int pageSize); + //Handles traps which request services from the operating system + virtual void handleTrap(int trapNum, ThreadContext *tc); Addr readFillStart() { return fillStart; } @@ -83,4 +68,107 @@ class SparcLiveProcess : public LiveProcess }; +struct M5_32_auxv_t +{ + int32_t a_type; + union { + int32_t a_val; + int32_t a_ptr; + int32_t a_fcn; + }; + + M5_32_auxv_t() + {} + + M5_32_auxv_t(int32_t type, int32_t val); +}; + +class Sparc32LiveProcess : public SparcLiveProcess +{ + protected: + + std::vector<M5_32_auxv_t> auxv; + + Sparc32LiveProcess(const std::string &nm, ObjectFile *objFile, + System *_system, int stdin_fd, int stdout_fd, int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp, + const std::string &cwd, + uint64_t _uid, uint64_t _euid, + uint64_t _gid, uint64_t _egid, + uint64_t _pid, uint64_t _ppid) : + SparcLiveProcess(nm, objFile, _system, + stdin_fd, stdout_fd, stderr_fd, + argv, envp, cwd, + _uid, _euid, _gid, _egid, _pid, _ppid) + { + // Set up stack. On SPARC Linux, stack goes from the top of memory + // downward, less the hole for the kernel address space. + stack_base = (Addr)0xf0000000ULL; + + // Set up region for mmaps. + mmap_start = mmap_end = 0x70000000; + } + + void startup(); + + public: + + void argsInit(int intSize, int pageSize); + +}; + +struct M5_64_auxv_t +{ + int64_t a_type; + union { + int64_t a_val; + int64_t a_ptr; + int64_t a_fcn; + }; + + M5_64_auxv_t() + {} + + M5_64_auxv_t(int64_t type, int64_t val); +}; + +class Sparc64LiveProcess : public SparcLiveProcess +{ + protected: + + static const Addr StackBias = 2047; + + std::vector<M5_64_auxv_t> auxv; + + Sparc64LiveProcess(const std::string &nm, ObjectFile *objFile, + System *_system, int stdin_fd, int stdout_fd, int stderr_fd, + std::vector<std::string> &argv, + std::vector<std::string> &envp, + const std::string &cwd, + uint64_t _uid, uint64_t _euid, + uint64_t _gid, uint64_t _egid, + uint64_t _pid, uint64_t _ppid) : + SparcLiveProcess(nm, objFile, _system, + stdin_fd, stdout_fd, stderr_fd, + argv, envp, cwd, + _uid, _euid, _gid, _egid, _pid, _ppid) + { + // Set up stack. On SPARC Linux, stack goes from the top of memory + // downward, less the hole for the kernel address space. + stack_base = (Addr)0x80000000000ULL; + + // Set up region for mmaps. Tru64 seems to start just above 0 and + // grow up from there. + mmap_start = mmap_end = 0xfffff80000000000ULL; + } + + void startup(); + + public: + + void argsInit(int intSize, int pageSize); + +}; + #endif // __SPARC_PROCESS_HH__ diff --git a/src/base/bigint.hh b/src/base/bigint.hh index aa60eeb04..d533e662a 100644 --- a/src/base/bigint.hh +++ b/src/base/bigint.hh @@ -42,9 +42,22 @@ struct m5_twin64_t { } }; +struct m5_twin32_t { + uint32_t a; + uint32_t b; + inline m5_twin32_t& operator=(const uint32_t x) + { + a = x; + b = x; + return *this; + } +}; + + // This is for twin loads (two 64 bit values), not 1 128 bit value (as far as // endian conversion is concerned! typedef m5_twin64_t Twin64_t; +typedef m5_twin32_t Twin32_t; #endif // __BASE_BIGINT_HH__ diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc index d59affe85..b56dc5aa6 100644 --- a/src/base/loader/elf_object.cc +++ b/src/base/loader/elf_object.cc @@ -78,9 +78,14 @@ ElfObject::tryFile(const string &fname, int fd, size_t len, uint8_t *data) //just assume if it wasn't something else and it's 64 bit, that's //what it must be. if (ehdr.e_machine == EM_SPARC64 || - ehdr.e_machine == EM_SPARC || + (ehdr.e_machine == EM_SPARC && + ehdr.e_ident[EI_CLASS] == ELFCLASS64)|| ehdr.e_machine == EM_SPARCV9) { - arch = ObjectFile::SPARC; + arch = ObjectFile::SPARC64; + } else if (ehdr.e_machine == EM_SPARC32PLUS || + (ehdr.e_machine == EM_SPARC && + ehdr.e_ident[EI_CLASS] == ELFCLASS32)) { + arch = ObjectFile::SPARC32; } else if (ehdr.e_machine == EM_MIPS && ehdr.e_ident[EI_CLASS] == ELFCLASS32) { arch = ObjectFile::Mips; diff --git a/src/base/loader/object_file.hh b/src/base/loader/object_file.hh index 18e6482be..49c7363e6 100644 --- a/src/base/loader/object_file.hh +++ b/src/base/loader/object_file.hh @@ -47,7 +47,8 @@ class ObjectFile enum Arch { UnknownArch, Alpha, - SPARC, + SPARC64, + SPARC32, Mips }; diff --git a/src/base/stats/mysql.cc b/src/base/stats/mysql.cc index d4035986b..39a687fff 100644 --- a/src/base/stats/mysql.cc +++ b/src/base/stats/mysql.cc @@ -930,7 +930,7 @@ MySql::visit(const FormulaData &data) bool initMySQL(string host, string user, string password, string database, - string name, string sample, string project) + string project, string name, string sample) { extern list<Output *> OutputList; static MySql mysql; @@ -938,9 +938,6 @@ initMySQL(string host, string user, string password, string database, if (mysql.connected()) return false; - if (user.empty()) - user = username(); - mysql.connect(host, user, password, database, name, sample, project); OutputList.push_back(&mysql); diff --git a/src/base/stats/mysql.hh b/src/base/stats/mysql.hh index 52f93ac61..0ce381c2f 100644 --- a/src/base/stats/mysql.hh +++ b/src/base/stats/mysql.hh @@ -187,15 +187,15 @@ class MySql : public Output void configure(const FormulaData &data); }; -bool initMySQL(std::string host, std::string database, std::string user = "", - std::string passwd = "", std::string name = "test", - std::string sample = "0", std::string project = "test"); +bool initMySQL(std::string host, std::string database, std::string user, + std::string passwd, std::string project, std::string name, + std::string sample); #if !USE_MYSQL inline bool initMySQL(std::string host, std::string user, std::string password, - std::string database, std::string name, std::string sample, - std::string project) + std::string database, std::string project, std::string name, + std::string sample) { return false; } diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 3001241fe..df7e780e6 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -321,6 +321,10 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) template Fault +AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); + +template +Fault AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); template diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index ff3606a74..7f857c68d 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -317,6 +317,10 @@ TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); template Fault +TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); + +template +Fault TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); template diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 16e491fd3..a24dc49da 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -254,6 +254,8 @@ class ThreadContext // Same with st cond failures. virtual Counter readFuncExeInst() = 0; + virtual void syscall(int64_t callnum) = 0; + // This function exits the thread context in the CPU and returns // 1 if the CPU has no more active threads (meaning it's OK to exit); // Used in syscall-emulation mode when a thread calls the exit syscall. @@ -441,6 +443,9 @@ class ProxyThreadContext : public ThreadContext void setSyscallReturn(SyscallReturn return_value) { actualTC->setSyscallReturn(return_value); } + void syscall(int64_t callnum) + { actualTC->syscall(callnum); } + Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } #endif diff --git a/src/mem/packet_access.hh b/src/mem/packet_access.hh index 882aa98d0..552b6dd27 100644 --- a/src/mem/packet_access.hh +++ b/src/mem/packet_access.hh @@ -53,6 +53,18 @@ Packet::get() return d; } +template<> +inline Twin32_t +Packet::get() +{ + Twin32_t d; + assert(staticData || dynamicData); + assert(sizeof(Twin32_t) <= size); + d.a = TheISA::gtoh(*(uint32_t*)data); + d.b = TheISA::gtoh(*((uint32_t*)data + 1)); + return d; +} + /** return the value of what is pointed to in the packet. */ template <typename T> diff --git a/src/python/SConscript b/src/python/SConscript index 8c7e47909..94db1a747 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -107,10 +107,11 @@ def swig_it(module): '-o ${TARGETS[0]} $SOURCES') swig_modules.append(module) -swig_it('main') +swig_it('core') swig_it('debug') swig_it('event') swig_it('random') +swig_it('sim_object') swig_it('stats') swig_it('trace') diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index ba79d3729..42266a80e 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -693,7 +693,7 @@ class SimObject(object): def getCCObject(self): if not self._ccObject: self._ccObject = -1 # flag to catch cycles in recursion - self._ccObject = internal.main.createSimObject(self.path()) + self._ccObject = internal.sim_object.createSimObject(self.path()) elif self._ccObject == -1: raise RuntimeError, "%s: recursive call to getCCObject()" \ % self.path() @@ -727,13 +727,13 @@ class SimObject(object): # i don't know if there's a better way to do this - calling # setMemoryMode directly from self._ccObject results in calling # SimObject::setMemoryMode, not the System::setMemoryMode - system_ptr = internal.main.convertToSystemPtr(self._ccObject) + system_ptr = internal.sim_object.convertToSystemPtr(self._ccObject) system_ptr.setMemoryMode(mode) for child in self._children.itervalues(): child.changeTiming(mode) def takeOverFrom(self, old_cpu): - cpu_ptr = internal.main.convertToBaseCPUPtr(old_cpu._ccObject) + cpu_ptr = internal.sim_object.convertToBaseCPUPtr(old_cpu._ccObject) self._ccObject.takeOverFrom(cpu_ptr) # generate output file for 'dot' to display as a pretty graph. diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index f39cc670a..1c4a79020 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -27,14 +27,16 @@ # Authors: Nathan Binkert # Steve Reinhardt -import atexit, os, sys +import atexit +import os +import sys # import the SWIG-wrapped main C++ functions import internal # import a few SWIG-wrapped items (those that are likely to be used # directly by user scripts) completely into this module for # convenience -from internal.main import simulate, SimLoopExitEvent +from internal.event import SimLoopExitEvent # import the m5 compile options import defines @@ -85,27 +87,60 @@ def instantiate(root): root.print_ini() sys.stdout.close() # close config.ini sys.stdout = sys.__stdout__ # restore to original - internal.main.loadIniFile(resolveSimObject) # load config.ini into C++ + + # load config.ini into C++ + internal.core.loadIniFile(resolveSimObject) + + # Initialize the global statistics + internal.stats.initSimStats() + root.createCCObject() root.connectPorts() - internal.main.finalInit() - noDot = True # temporary until we fix dot - if not noDot: - dot = pydot.Dot() - instance.outputDot(dot) - dot.orientation = "portrait" - dot.size = "8.5,11" - dot.ranksep="equally" - dot.rank="samerank" - dot.write("config.dot") - dot.write_ps("config.ps") + + # Do a second pass to finish initializing the sim objects + internal.sim_object.initAll() + + # Do a third pass to initialize statistics + internal.sim_object.regAllStats() + + # Check to make sure that the stats package is properly initialized + internal.stats.check() + + # Reset to put the stats in a consistent state. + internal.stats.reset() + +def doDot(root): + dot = pydot.Dot() + instance.outputDot(dot) + dot.orientation = "portrait" + dot.size = "8.5,11" + dot.ranksep="equally" + dot.rank="samerank" + dot.write("config.dot") + dot.write_ps("config.ps") + +need_resume = [] +need_startup = True +def simulate(*args, **kwargs): + global need_resume, need_startup + + if need_startup: + internal.core.SimStartup() + need_startup = False + + for root in need_resume: + resume(root) + need_resume = [] + + return internal.event.simulate(*args, **kwargs) # Export curTick to user script. def curTick(): - return internal.main.cvar.curTick + return internal.event.cvar.curTick # register our C++ exit callback function with Python -atexit.register(internal.main.doExitCleanup) +atexit.register(internal.core.doExitCleanup) +atexit.register(internal.stats.dump) # This loops until all objects have been fully drained. def doDrain(root): @@ -119,7 +154,7 @@ def doDrain(root): # be drained. def drain(root): all_drained = False - drain_event = internal.main.createCountedDrain() + drain_event = internal.event.createCountedDrain() unready_objects = root.startDrain(drain_event, True) # If we've got some objects that can't drain immediately, then simulate if unready_objects > 0: @@ -127,7 +162,7 @@ def drain(root): simulate() else: all_drained = True - internal.main.cleanupCountedDrain(drain_event) + internal.event.cleanupCountedDrain(drain_event) return all_drained def resume(root): @@ -135,16 +170,16 @@ def resume(root): def checkpoint(root, dir): if not isinstance(root, objects.Root): - raise TypeError, "Object is not a root object. Checkpoint must be called on a root object." + raise TypeError, "Checkpoint must be called on a root object." doDrain(root) print "Writing checkpoint" - internal.main.serializeAll(dir) + internal.sim_object.serializeAll(dir) resume(root) def restoreCheckpoint(root, dir): print "Restoring from checkpoint" - internal.main.unserializeAll(dir) - resume(root) + internal.sim_object.unserializeAll(dir) + need_resume.append(root) def changeToAtomic(system): if not isinstance(system, objects.Root) and not isinstance(system, objects.System): @@ -152,7 +187,7 @@ def changeToAtomic(system): "called on a root object." doDrain(system) print "Changing memory mode to atomic" - system.changeTiming(internal.main.SimObject.Atomic) + system.changeTiming(internal.sim_object.SimObject.Atomic) def changeToTiming(system): if not isinstance(system, objects.Root) and not isinstance(system, objects.System): @@ -160,7 +195,7 @@ def changeToTiming(system): "called on a root object." doDrain(system) print "Changing memory mode to timing" - system.changeTiming(internal.main.SimObject.Timing) + system.changeTiming(internal.sim_object.SimObject.Timing) def switchCpus(cpuList): print "switching cpus" @@ -180,7 +215,7 @@ def switchCpus(cpuList): raise TypeError, "%s is not of type BaseCPU" % cpu # Drain all of the individual CPUs - drain_event = internal.main.createCountedDrain() + drain_event = internal.event.createCountedDrain() unready_cpus = 0 for old_cpu in old_cpus: unready_cpus += old_cpu.startDrain(drain_event, False) @@ -188,7 +223,7 @@ def switchCpus(cpuList): if unready_cpus > 0: drain_event.setCount(unready_cpus) simulate() - internal.main.cleanupCountedDrain(drain_event) + internal.event.cleanupCountedDrain(drain_event) # Now all of the CPUs are ready to be switched out for old_cpu in old_cpus: old_cpu._ccObject.switchOut() @@ -198,6 +233,14 @@ def switchCpus(cpuList): new_cpu._ccObject.resume() index += 1 +def dumpStats(): + print 'Dumping stats' + internal.stats.dump() + +def resetStats(): + print 'Resetting stats' + internal.stats.reset() + # Since we have so many mutual imports in this package, we should: # 1. Put all intra-package imports at the *bottom* of the file, unless # they're absolutely needed before that (for top-level statements diff --git a/src/python/m5/main.py b/src/python/m5/main.py index 37df884d0..54368b91e 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -240,7 +240,7 @@ def main(): print "M5 Simulator System" print brief_copyright print - print "M5 compiled %s" % internal.main.cvar.compileDate; + print "M5 compiled %s" % internal.core.cvar.compileDate; print "M5 started %s" % datetime.now().ctime() print "M5 executing on %s" % socket.gethostname() print "command line:", @@ -256,7 +256,7 @@ def main(): usage(2) # tell C++ about output directory - internal.main.setOutputDir(options.outdir) + internal.core.setOutputDir(options.outdir) # update the system path with elements from the -p option sys.path[0:0] = options.path diff --git a/src/python/m5/params.py b/src/python/m5/params.py index f8a9f9ddd..e71e1c3c5 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -894,9 +894,8 @@ class PortRef(object): if self.ccConnected: # already done this return peer = self.peer - internal.main.connectPorts(self.simobj.getCCObject(), self.name, - self.index, peer.simobj.getCCObject(), - peer.name, peer.index) + internal.sim_object.connectPorts(self.simobj.getCCObject(), self.name, + self.index, peer.simobj.getCCObject(), peer.name, peer.index) self.ccConnected = True peer.ccConnected = True diff --git a/src/python/m5/stats.py b/src/python/m5/stats.py new file mode 100644 index 000000000..041a3f58d --- /dev/null +++ b/src/python/m5/stats.py @@ -0,0 +1,46 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +import internal + +from internal.stats import dump +from internal.stats import initSimStats +from internal.stats import reset +from internal.stats import StatEvent as event + +def initText(filename, desc=True, compat=True): + internal.stats.initText(filename, desc, compat) + +def initMySQL(host, database, user='', passwd='', project='test', name='test', + sample='0'): + if not user: + import getpass + user = getpass.getuser() + + internal.stats.initMySQL(host, database, user, passwd, project, name, + sample) diff --git a/src/python/swig/core.i b/src/python/swig/core.i new file mode 100644 index 000000000..116890763 --- /dev/null +++ b/src/python/swig/core.i @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + */ + +%module core + +%{ +#include "python/swig/pyobject.hh" + +#include "sim/core.hh" +#include "sim/host.hh" +#include "sim/startup.hh" + +extern const char *compileDate; +%} + +%include "std_string.i" + +void setOutputDir(const std::string &dir); +void loadIniFile(PyObject *); +void SimStartup(); +void doExitCleanup(); + +char *compileDate; + +%wrapper %{ +// fix up module name to reflect the fact that it's inside the m5 package +#undef SWIG_name +#define SWIG_name "m5.internal._core" +%} diff --git a/src/python/swig/event.i b/src/python/swig/event.i index 554c9fa0e..51d7d89f0 100644 --- a/src/python/swig/event.i +++ b/src/python/swig/event.i @@ -33,19 +33,48 @@ %{ #include "python/swig/pyevent.hh" -inline void -create(PyObject *object, Tick when) -{ - new PythonEvent(object, when); -} +#include "sim/sim_events.hh" +#include "sim/sim_exit.hh" +#include "sim/simulate.hh" %} %include "stdint.i" +%include "std_string.i" %include "sim/host.hh" -%inline %{ -extern void create(PyObject *object, Tick when); -%} +void create(PyObject *object, Tick when); + +class Event; +class CountedDrainEvent : public Event { + public: + void setCount(int _count); +}; + +CountedDrainEvent *createCountedDrain(); +void cleanupCountedDrain(Event *drain_event); + +%immutable curTick; +Tick curTick; + +// minimal definition of SimExitEvent interface to wrap +class SimLoopExitEvent { + public: + std::string getCause(); + int getCode(); + SimLoopExitEvent(EventQueue *q, Tick _when, Tick _repeat, + const std::string &_cause, int c = 0); +}; + +%exception simulate { + $action + if (!result) { + return NULL; + } +} +SimLoopExitEvent *simulate(Tick num_cycles = MaxTick); +void exitSimLoop(const std::string &message, int exit_code); + +Tick curTick; %wrapper %{ // fix up module name to reflect the fact that it's inside the m5 package diff --git a/src/python/swig/pyevent.hh b/src/python/swig/pyevent.hh index 16af85a84..65e80e9e4 100644 --- a/src/python/swig/pyevent.hh +++ b/src/python/swig/pyevent.hh @@ -32,6 +32,7 @@ #define __PYTHON_SWIG_PYEVENT_HH__ #include "sim/eventq.hh" +#include "sim/sim_events.hh" class PythonEvent : public Event { @@ -45,4 +46,29 @@ class PythonEvent : public Event virtual void process(); }; +inline void +create(PyObject *object, Tick when) +{ + new PythonEvent(object, when); +} + +inline Event * +createCountedDrain() +{ + return new CountedDrainEvent(); +} + +inline void +cleanupCountedDrain(Event *counted_drain) +{ + CountedDrainEvent *event = + dynamic_cast<CountedDrainEvent *>(counted_drain); + if (event == NULL) { + fatal("Called cleanupCountedDrain() on an event that was not " + "a CountedDrainEvent."); + } + assert(event->getCount() == 0); + delete event; +} + #endif // __PYTHON_SWIG_PYEVENT_HH__ diff --git a/src/python/swig/pyobject.cc b/src/python/swig/pyobject.cc new file mode 100644 index 000000000..11141fa84 --- /dev/null +++ b/src/python/swig/pyobject.cc @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +#include <Python.h> + +#include <string> + +#include "base/inifile.hh" +#include "base/output.hh" +#include "mem/mem_object.hh" +#include "mem/port.hh" +#include "sim/builder.hh" +#include "sim/sim_object.hh" + +using namespace std; + +/** + * Look up a MemObject port. Helper function for connectPorts(). + */ +Port * +lookupPort(SimObject *so, const std::string &name, int i) +{ + MemObject *mo = dynamic_cast<MemObject *>(so); + if (mo == NULL) { + warn("error casting SimObject %s to MemObject", so->name()); + return NULL; + } + + Port *p = mo->getPort(name, i); + if (p == NULL) + warn("error looking up port %s on object %s", name, so->name()); + return p; +} + + +/** + * Connect the described MemObject ports. Called from Python via SWIG. + */ +int +connectPorts(SimObject *o1, const std::string &name1, int i1, + SimObject *o2, const std::string &name2, int i2) +{ + Port *p1 = lookupPort(o1, name1, i1); + Port *p2 = lookupPort(o2, name2, i2); + + if (p1 == NULL || p2 == NULL) { + warn("connectPorts: port lookup error"); + return 0; + } + + p1->setPeer(p2); + p2->setPeer(p1); + + return 1; +} + +inline IniFile & +inifile() +{ + static IniFile inifile; + return inifile; +} + +SimObject * +createSimObject(const string &name) +{ + return SimObjectClass::createObject(inifile(), name); +} + +/** + * Pointer to the Python function that maps names to SimObjects. + */ +PyObject *resolveFunc = NULL; + +/** + * Convert a pointer to the Python object that SWIG wraps around a C++ + * SimObject pointer back to the actual C++ pointer. See main.i. + */ +extern "C" SimObject *convertSwigSimObjectPtr(PyObject *); + +SimObject * +resolveSimObject(const string &name) +{ + PyObject *pyPtr = PyEval_CallFunction(resolveFunc, "(s)", name.c_str()); + if (pyPtr == NULL) { + PyErr_Print(); + panic("resolveSimObject: failure on call to Python for %s", name); + } + + SimObject *simObj = convertSwigSimObjectPtr(pyPtr); + if (simObj == NULL) + panic("resolveSimObject: failure on pointer conversion for %s", name); + + return simObj; +} + +/** + * Load config.ini into C++ database. Exported to Python via SWIG; + * invoked from m5.instantiate(). + */ +void +loadIniFile(PyObject *_resolveFunc) +{ + resolveFunc = _resolveFunc; + configStream = simout.find("config.out"); + + // The configuration database is now complete; start processing it. + inifile().load(simout.resolve("config.ini")); +} + diff --git a/src/python/swig/pyobject.hh b/src/python/swig/pyobject.hh new file mode 100644 index 000000000..d8efc9149 --- /dev/null +++ b/src/python/swig/pyobject.hh @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +#include <Python.h> + +#include "cpu/base.hh" +#include "sim/host.hh" +#include "sim/serialize.hh" +#include "sim/sim_object.hh" +#include "sim/system.hh" + +SimObject *createSimObject(const std::string &name); +extern "C" SimObject *convertSwigSimObjectPtr(PyObject *); +SimObject *resolveSimObject(const std::string &name); +void loadIniFile(PyObject *_resolveFunc); + + +/** + * Connect the described MemObject ports. Called from Python via SWIG. + */ +int connectPorts(SimObject *o1, const std::string &name1, int i1, + SimObject *o2, const std::string &name2, int i2); + +inline BaseCPU * +convertToBaseCPUPtr(SimObject *obj) +{ + BaseCPU *ptr = dynamic_cast<BaseCPU *>(obj); + + if (ptr == NULL) + warn("Casting to BaseCPU pointer failed"); + return ptr; +} + +inline System * +convertToSystemPtr(SimObject *obj) +{ + System *ptr = dynamic_cast<System *>(obj); + + if (ptr == NULL) + warn("Casting to System pointer failed"); + return ptr; +} + +inline void +initAll() +{ + SimObject::initAll(); +} + +inline void +regAllStats() +{ + SimObject::regAllStats(); +} + +inline void +serializeAll(const std::string &cpt_dir) +{ + Serializable::serializeAll(cpt_dir); +} + +inline void +unserializeAll(const std::string &cpt_dir) +{ + Serializable::unserializeAll(cpt_dir); +} + diff --git a/src/python/swig/sim_object.i b/src/python/swig/sim_object.i new file mode 100644 index 000000000..b2af72c61 --- /dev/null +++ b/src/python/swig/sim_object.i @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +%module sim_object + +%{ +#include "python/swig/pyobject.hh" +%} + +// import these files for SWIG to wrap +%include "stdint.i" +%include "std_string.i" +%include "sim/host.hh" + +class BaseCPU; + +class SimObject { + public: + enum State { + Running, + Draining, + Drained + }; + + enum MemoryMode { + Invalid, + Atomic, + Timing + }; + + unsigned int drain(Event *drain_event); + void resume(); + void switchOut(); + void takeOverFrom(BaseCPU *cpu); + SimObject(const std::string &_name); +}; + +class System { + private: + System(); + public: + void setMemoryMode(SimObject::MemoryMode mode); +}; + +SimObject *createSimObject(const std::string &name); + +int connectPorts(SimObject *o1, const std::string &name1, int i1, + SimObject *o2, const std::string &name2, int i2); + +BaseCPU *convertToBaseCPUPtr(SimObject *obj); +System *convertToSystemPtr(SimObject *obj); + +void serializeAll(const std::string &cpt_dir); +void unserializeAll(const std::string &cpt_dir); + +void initAll(); +void regAllStats(); + +%wrapper %{ +// fix up module name to reflect the fact that it's inside the m5 package +#undef SWIG_name +#define SWIG_name "m5.internal._sim_object" + +// Convert a pointer to the Python object that SWIG wraps around a +// C++ SimObject pointer back to the actual C++ pointer. +SimObject * +convertSwigSimObjectPtr(PyObject *pyObj) +{ + SimObject *so; + if (SWIG_ConvertPtr(pyObj, (void **) &so, SWIGTYPE_p_SimObject, 0) == -1) + return NULL; + return so; +} +%} diff --git a/src/python/swig/stats.i b/src/python/swig/stats.i index d6b39c2cb..d36f82dbc 100644 --- a/src/python/swig/stats.i +++ b/src/python/swig/stats.i @@ -42,12 +42,13 @@ namespace Stats { void initSimStats(); void initText(const std::string &filename, bool desc=true, bool compat=true); -void initMySQL(std::string host, std::string database, std::string user = "", - std::string passwd = "", std::string name = "test", - std::string sample = "0", std::string project = "test"); +void initMySQL(std::string host, std::string database, std::string user, + std::string passwd, std::string project, std::string name, + std::string sample); void StatEvent(bool dump, bool reset, Tick when = curTick, Tick repeat = 0); +void check(); void dump(); void reset(); diff --git a/src/sim/async.cc b/src/sim/async.cc new file mode 100644 index 000000000..1a8e499f7 --- /dev/null +++ b/src/sim/async.cc @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2000-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + */ + +volatile bool async_event = false; +volatile bool async_statdump = false; +volatile bool async_statreset = false; +volatile bool async_exit = false; +volatile bool async_io = false; +volatile bool async_alarm = false; +volatile bool async_exception = false; + diff --git a/src/sim/async.hh b/src/sim/async.hh index 6ee5eb46a..932f975d2 100644 --- a/src/sim/async.hh +++ b/src/sim/async.hh @@ -43,7 +43,8 @@ /// @note See the PollQueue object (in pollevent.hh) for the use of async_io and async_alarm. //@{ extern volatile bool async_event; ///< Some asynchronous event has happened. -extern volatile bool async_dump; ///< Async request to dump stats. +extern volatile bool async_statdump; ///< Async request to dump stats. +extern volatile bool async_statreset; ///< Async request to reset stats. extern volatile bool async_exit; ///< Async request to exit simulator. extern volatile bool async_io; ///< Async I/O request (SIGIO). extern volatile bool async_alarm; ///< Async alarm event (SIGALRM). diff --git a/src/sim/core.cc b/src/sim/core.cc new file mode 100644 index 000000000..24cc33da2 --- /dev/null +++ b/src/sim/core.cc @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + */ + +#include <iostream> +#include <string> + +#include "base/callback.hh" +#include "base/output.hh" + +using namespace std; + +void +setOutputDir(const string &dir) +{ + simout.setDirectory(dir); +} + +/** + * Queue of C++ callbacks to invoke on simulator exit. + */ +inline CallbackQueue & +exitCallbacks() +{ + static CallbackQueue theQueue; + return theQueue; +} + +/** + * Register an exit callback. + */ +void +registerExitCallback(Callback *callback) +{ + exitCallbacks().add(callback); +} + +/** + * Do C++ simulator exit processing. Exported to SWIG to be invoked + * when simulator terminates via Python's atexit mechanism. + */ +void +doExitCleanup() +{ + exitCallbacks().process(); + exitCallbacks().clear(); + + cout.flush(); +} diff --git a/src/sim/core.hh b/src/sim/core.hh new file mode 100644 index 000000000..2ef21c4b6 --- /dev/null +++ b/src/sim/core.hh @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + */ + +#include <Python.h> +#include <string> + +#include "base/callback.hh" + +void setOutputDir(const std::string &dir); + +void registerExitCallback(Callback *callback); +void doExitCleanup(); diff --git a/src/sim/main.cc b/src/sim/main.cc index 8e47ac6a0..0341b7d5f 100644 --- a/src/sim/main.cc +++ b/src/sim/main.cc @@ -25,79 +25,39 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Steve Raasch - * Nathan Binkert - * Steve Reinhardt + * Authors: Nathan Binkert */ -/// -/// @file sim/main.cc -/// -#include <Python.h> // must be before system headers... see Python docs - -#include <sys/types.h> -#include <sys/stat.h> -#include <errno.h> -#include <libgen.h> -#include <stdlib.h> +#include <Python.h> #include <signal.h> -#include <getopt.h> -#include <list> +#include <iostream> #include <string> -#include <vector> -#include "base/callback.hh" -#include "base/inifile.hh" +#include "base/cprintf.hh" #include "base/misc.hh" -#include "base/output.hh" -#include "base/pollevent.hh" -#include "base/statistics.hh" -#include "base/stats/output.hh" -#include "base/str.hh" -#include "base/time.hh" #include "config/pythonhome.hh" -#include "cpu/base.hh" -#include "cpu/smt.hh" -#include "mem/mem_object.hh" -#include "mem/port.hh" #include "python/swig/init.hh" #include "sim/async.hh" -#include "sim/builder.hh" #include "sim/host.hh" -#include "sim/serialize.hh" -#include "sim/sim_events.hh" -#include "sim/sim_exit.hh" -#include "sim/sim_object.hh" -#include "sim/system.hh" -#include "sim/stat_control.hh" -#include "sim/stats.hh" #include "sim/root.hh" using namespace std; -// See async.h. -volatile bool async_event = false; -volatile bool async_dump = false; -volatile bool async_dumpreset = false; -volatile bool async_exit = false; -volatile bool async_io = false; -volatile bool async_alarm = false; -volatile bool async_exception = false; - /// Stats signal handler. void dumpStatsHandler(int sigtype) { async_event = true; - async_dump = true; + async_statdump = true; } void dumprstStatsHandler(int sigtype) { async_event = true; - async_dumpreset = true; + async_statdump = true; + async_statreset = true; } /// Exit signal handler. @@ -112,7 +72,7 @@ exitNowHandler(int sigtype) void abortHandler(int sigtype) { - cerr << "Program aborted at cycle " << curTick << endl; + ccprintf(cerr, "Program aborted at cycle %d\n", curTick); } int @@ -160,301 +120,3 @@ main(int argc, char **argv) // clean up Python intepreter. Py_Finalize(); } - - -void -setOutputDir(const string &dir) -{ - simout.setDirectory(dir); -} - - -IniFile inifile; - -SimObject * -createSimObject(const string &name) -{ - return SimObjectClass::createObject(inifile, name); -} - - -/** - * Pointer to the Python function that maps names to SimObjects. - */ -PyObject *resolveFunc = NULL; - -/** - * Convert a pointer to the Python object that SWIG wraps around a C++ - * SimObject pointer back to the actual C++ pointer. See main.i. - */ -extern "C" SimObject *convertSwigSimObjectPtr(PyObject *); - - -SimObject * -resolveSimObject(const string &name) -{ - PyObject *pyPtr = PyEval_CallFunction(resolveFunc, "(s)", name.c_str()); - if (pyPtr == NULL) { - PyErr_Print(); - panic("resolveSimObject: failure on call to Python for %s", name); - } - - SimObject *simObj = convertSwigSimObjectPtr(pyPtr); - if (simObj == NULL) - panic("resolveSimObject: failure on pointer conversion for %s", name); - - return simObj; -} - - -/** - * Load config.ini into C++ database. Exported to Python via SWIG; - * invoked from m5.instantiate(). - */ -void -loadIniFile(PyObject *_resolveFunc) -{ - resolveFunc = _resolveFunc; - configStream = simout.find("config.out"); - - // The configuration database is now complete; start processing it. - inifile.load(simout.resolve("config.ini")); - - // Initialize statistics database - Stats::initSimStats(); -} - - -/** - * Look up a MemObject port. Helper function for connectPorts(). - */ -Port * -lookupPort(SimObject *so, const std::string &name, int i) -{ - MemObject *mo = dynamic_cast<MemObject *>(so); - if (mo == NULL) { - warn("error casting SimObject %s to MemObject", so->name()); - return NULL; - } - - Port *p = mo->getPort(name, i); - if (p == NULL) - warn("error looking up port %s on object %s", name, so->name()); - return p; -} - - -/** - * Connect the described MemObject ports. Called from Python via SWIG. - */ -int -connectPorts(SimObject *o1, const std::string &name1, int i1, - SimObject *o2, const std::string &name2, int i2) -{ - Port *p1 = lookupPort(o1, name1, i1); - Port *p2 = lookupPort(o2, name2, i2); - - if (p1 == NULL || p2 == NULL) { - warn("connectPorts: port lookup error"); - return 0; - } - - p1->setPeer(p2); - p2->setPeer(p1); - - return 1; -} - -/** - * Do final initialization steps after object construction but before - * start of simulation. - */ -void -finalInit() -{ - // Do a second pass to finish initializing the sim objects - SimObject::initAll(); - - // Restore checkpointed state, if any. -#if 0 - configHierarchy.unserializeSimObjects(); -#endif - - SimObject::regAllStats(); - - // Check to make sure that the stats package is properly initialized - Stats::check(); - - // Reset to put the stats in a consistent state. - Stats::reset(); - - SimStartup(); -} - -/** Simulate for num_cycles additional cycles. If num_cycles is -1 - * (the default), do not limit simulation; some other event must - * terminate the loop. Exported to Python via SWIG. - * @return The SimLoopExitEvent that caused the loop to exit. - */ -SimLoopExitEvent * -simulate(Tick num_cycles = MaxTick) -{ - warn("Entering event queue @ %d. Starting simulation...\n", curTick); - - if (num_cycles < 0) - fatal("simulate: num_cycles must be >= 0 (was %d)\n", num_cycles); - else if (curTick + num_cycles < 0) //Overflow - num_cycles = MaxTick; - else - num_cycles = curTick + num_cycles; - - Event *limit_event = schedExitSimLoop("simulate() limit reached", - num_cycles); - - while (1) { - // there should always be at least one event (the SimLoopExitEvent - // we just scheduled) in the queue - assert(!mainEventQueue.empty()); - assert(curTick <= mainEventQueue.nextTick() && - "event scheduled in the past"); - - // forward current cycle to the time of the first event on the - // queue - curTick = mainEventQueue.nextTick(); - Event *exit_event = mainEventQueue.serviceOne(); - if (exit_event != NULL) { - // hit some kind of exit event; return to Python - // event must be subclass of SimLoopExitEvent... - SimLoopExitEvent *se_event = dynamic_cast<SimLoopExitEvent *>(exit_event); - if (se_event == NULL) - panic("Bogus exit event class!"); - - // if we didn't hit limit_event, delete it - if (se_event != limit_event) { - assert(limit_event->scheduled()); - limit_event->deschedule(); - delete limit_event; - } - - return se_event; - } - - if (async_event) { - async_event = false; - if (async_dump) { - async_dump = false; - Stats::StatEvent(true, false); - } - - if (async_dumpreset) { - async_dumpreset = false; - Stats::StatEvent(true, true); - } - - if (async_exit) { - async_exit = false; - exitSimLoop("user interrupt received"); - } - - if (async_io || async_alarm) { - async_io = false; - async_alarm = false; - pollQueue.service(); - } - - if (async_exception) { - async_exception = false; - return NULL; - } - } - } - - // not reached... only exit is return on SimLoopExitEvent -} - -Event * -createCountedDrain() -{ - return new CountedDrainEvent(); -} - -void -cleanupCountedDrain(Event *counted_drain) -{ - CountedDrainEvent *event = - dynamic_cast<CountedDrainEvent *>(counted_drain); - if (event == NULL) { - fatal("Called cleanupCountedDrain() on an event that was not " - "a CountedDrainEvent."); - } - assert(event->getCount() == 0); - delete event; -} - -void -serializeAll(const std::string &cpt_dir) -{ - Serializable::serializeAll(cpt_dir); -} - -void -unserializeAll(const std::string &cpt_dir) -{ - Serializable::unserializeAll(cpt_dir); -} - -/** - * Queue of C++ callbacks to invoke on simulator exit. - */ -CallbackQueue& -exitCallbacks() -{ - static CallbackQueue theQueue; - return theQueue; -} - -/** - * Register an exit callback. - */ -void -registerExitCallback(Callback *callback) -{ - exitCallbacks().add(callback); -} - -BaseCPU * -convertToBaseCPUPtr(SimObject *obj) -{ - BaseCPU *ptr = dynamic_cast<BaseCPU *>(obj); - - if (ptr == NULL) - warn("Casting to BaseCPU pointer failed"); - return ptr; -} - -System * -convertToSystemPtr(SimObject *obj) -{ - System *ptr = dynamic_cast<System *>(obj); - - if (ptr == NULL) - warn("Casting to System pointer failed"); - return ptr; -} - - -/** - * Do C++ simulator exit processing. Exported to SWIG to be invoked - * when simulator terminates via Python's atexit mechanism. - */ -void -doExitCleanup() -{ - exitCallbacks().process(); - exitCallbacks().clear(); - - cout.flush(); - - // print simulation stats - Stats::dump(); -} diff --git a/src/sim/process.cc b/src/sim/process.cc index e5d868115..b3ce182e5 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -300,24 +300,6 @@ DEFINE_SIM_OBJECT_CLASS_NAME("Process", Process) //////////////////////////////////////////////////////////////////////// -void -copyStringArray(vector<string> &strings, Addr array_ptr, Addr data_ptr, - TranslatingPort* memPort) -{ - Addr data_ptr_swap; - for (int i = 0; i < strings.size(); ++i) { - data_ptr_swap = htog(data_ptr); - memPort->writeBlob(array_ptr, (uint8_t*)&data_ptr_swap, sizeof(Addr)); - memPort->writeString(data_ptr, strings[i].c_str()); - array_ptr += sizeof(Addr); - data_ptr += strings[i].size() + 1; - } - // add NULL terminator - data_ptr = 0; - - memPort->writeBlob(array_ptr, (uint8_t*)&data_ptr, sizeof(Addr)); -} - LiveProcess::LiveProcess(const string &nm, ObjectFile *_objFile, System *_system, int stdin_fd, int stdout_fd, int stderr_fd, @@ -475,14 +457,23 @@ LiveProcess::create(const std::string &nm, System *system, int stdin_fd, fatal("Unknown/unsupported operating system."); } #elif THE_ISA == SPARC_ISA - if (objFile->getArch() != ObjectFile::SPARC) + if (objFile->getArch() != ObjectFile::SPARC64 && objFile->getArch() != ObjectFile::SPARC32) fatal("Object file architecture does not match compiled ISA (SPARC)."); switch (objFile->getOpSys()) { case ObjectFile::Linux: - process = new SparcLinuxProcess(nm, objFile, system, - stdin_fd, stdout_fd, stderr_fd, - argv, envp, cwd, - _uid, _euid, _gid, _egid, _pid, _ppid); + if (objFile->getArch() == ObjectFile::SPARC64) { + process = new Sparc64LinuxProcess(nm, objFile, system, + stdin_fd, stdout_fd, stderr_fd, + argv, envp, cwd, + _uid, _euid, _gid, + _egid, _pid, _ppid); + } else { + process = new Sparc32LinuxProcess(nm, objFile, system, + stdin_fd, stdout_fd, stderr_fd, + argv, envp, cwd, + _uid, _euid, _gid, + _egid, _pid, _ppid); + } break; diff --git a/src/sim/process.hh b/src/sim/process.hh index bf65c6e06..dd64fa607 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -41,9 +41,12 @@ #if !FULL_SYSTEM +#include <string> #include <vector> #include "base/statistics.hh" +#include "mem/translating_port.hh" +#include "sim/host.hh" #include "sim/sim_object.hh" class ThreadContext; @@ -57,9 +60,27 @@ namespace TheISA class RemoteGDB; } +//This needs to be templated for cases where 32 bit pointers are needed. +template<class AddrType> void -copyStringArray(std::vector<std::string> &strings, Addr array_ptr, - Addr data_ptr, TranslatingPort* memPort); +copyStringArray(std::vector<std::string> &strings, + AddrType array_ptr, AddrType data_ptr, + TranslatingPort* memPort) +{ + AddrType data_ptr_swap; + for (int i = 0; i < strings.size(); ++i) { + data_ptr_swap = htog(data_ptr); + memPort->writeBlob(array_ptr, (uint8_t*)&data_ptr_swap, + sizeof(AddrType)); + memPort->writeString(data_ptr, strings[i].c_str()); + array_ptr += sizeof(AddrType); + data_ptr += strings[i].size() + 1; + } + // add NULL terminator + data_ptr = 0; + + memPort->writeBlob(array_ptr, (uint8_t*)&data_ptr, sizeof(AddrType)); +} class Process : public SimObject { diff --git a/src/sim/simulate.cc b/src/sim/simulate.cc new file mode 100644 index 000000000..55cbb50a9 --- /dev/null +++ b/src/sim/simulate.cc @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + */ + +#include "base/misc.hh" +#include "base/pollevent.hh" +#include "sim/stat_control.hh" +#include "sim/async.hh" +#include "sim/eventq.hh" +#include "sim/host.hh" +#include "sim/sim_events.hh" +#include "sim/sim_exit.hh" +#include "sim/simulate.hh" + +/** Simulate for num_cycles additional cycles. If num_cycles is -1 + * (the default), do not limit simulation; some other event must + * terminate the loop. Exported to Python via SWIG. + * @return The SimLoopExitEvent that caused the loop to exit. + */ +SimLoopExitEvent * +simulate(Tick num_cycles) +{ + warn("Entering event queue @ %d. Starting simulation...\n", curTick); + + if (num_cycles < 0) + fatal("simulate: num_cycles must be >= 0 (was %d)\n", num_cycles); + else if (curTick + num_cycles < 0) //Overflow + num_cycles = MaxTick; + else + num_cycles = curTick + num_cycles; + + Event *limit_event; + limit_event = schedExitSimLoop("simulate() limit reached", num_cycles); + + while (1) { + // there should always be at least one event (the SimLoopExitEvent + // we just scheduled) in the queue + assert(!mainEventQueue.empty()); + assert(curTick <= mainEventQueue.nextTick() && + "event scheduled in the past"); + + // forward current cycle to the time of the first event on the + // queue + curTick = mainEventQueue.nextTick(); + Event *exit_event = mainEventQueue.serviceOne(); + if (exit_event != NULL) { + // hit some kind of exit event; return to Python + // event must be subclass of SimLoopExitEvent... + SimLoopExitEvent *se_event; + se_event = dynamic_cast<SimLoopExitEvent *>(exit_event); + + if (se_event == NULL) + panic("Bogus exit event class!"); + + // if we didn't hit limit_event, delete it + if (se_event != limit_event) { + assert(limit_event->scheduled()); + limit_event->deschedule(); + delete limit_event; + } + + return se_event; + } + + if (async_event) { + async_event = false; + if (async_statdump || async_statreset) { + async_statdump = false; + async_statreset = false; + + Stats::StatEvent(async_statdump, async_statreset); + } + + if (async_exit) { + async_exit = false; + exitSimLoop("user interrupt received"); + } + + if (async_io || async_alarm) { + async_io = false; + async_alarm = false; + pollQueue.service(); + } + + if (async_exception) { + async_exception = false; + return NULL; + } + } + } + + // not reached... only exit is return on SimLoopExitEvent +} + diff --git a/src/sim/simulate.hh b/src/sim/simulate.hh new file mode 100644 index 000000000..139bddb82 --- /dev/null +++ b/src/sim/simulate.hh @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + */ + +#include "sim/host.hh" +#include "sim/sim_events.hh" + +SimLoopExitEvent *simulate(Tick num_cycles = MaxTick); diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc index ab44c0a35..876f39e99 100644 --- a/src/sim/syscall_emul.cc +++ b/src/sim/syscall_emul.cc @@ -184,6 +184,39 @@ lseekFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc) SyscallReturn +_llseekFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc) +{ + int fd = p->sim_fd(tc->getSyscallArg(0)); + uint64_t offset_high = tc->getSyscallArg(1); + uint32_t offset_low = tc->getSyscallArg(2); + Addr result_ptr = tc->getSyscallArg(3); + int whence = tc->getSyscallArg(4); + + uint64_t offset = (offset_high << 32) | offset_low; + + uint64_t result = lseek(fd, offset, whence); + result = TheISA::htog(result); + + if (result == (off_t)-1) { + //The seek failed. + return -errno; + } else { + //The seek succeeded. + //Copy "result" to "result_ptr" + //XXX We'll assume that the size of loff_t is 64 bits on the + //target platform + BufferArg result_buf(result_ptr, sizeof(result)); + memcpy(result_buf.bufferPtr(), &result, sizeof(result)); + result_buf.copyOut(tc->getMemPort()); + return 0; + } + + + return (result == (off_t)-1) ? -errno : result; +} + + +SyscallReturn munmapFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc) { // given that we don't really implement mmap, munmap is really easy diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh index f57bd5272..5ca2f6be5 100644 --- a/src/sim/syscall_emul.hh +++ b/src/sim/syscall_emul.hh @@ -211,6 +211,10 @@ SyscallReturn writeFunc(SyscallDesc *desc, int num, SyscallReturn lseekFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc); +/// Target _llseek() handler. +SyscallReturn _llseekFunc(SyscallDesc *desc, int num, + LiveProcess *p, ThreadContext *tc); + /// Target munmap() handler. SyscallReturn munmapFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc); diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini index 0c49d9f08..452538e49 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.ini @@ -186,7 +186,7 @@ cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing egid=100 env= euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin output=cout diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out index 7858bd7a1..602da9705 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/config.out @@ -27,7 +27,7 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon input=cin output=cout env= diff --git a/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt index 6f6923231..328856ce7 100644 --- a/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 595543 # Simulator instruction rate (inst/s) -host_mem_usage 157792 # Number of bytes of host memory used -host_seconds 669.41 # Real time elapsed on the host -host_tick_rate 892368 # Simulator tick rate (ticks/s) +host_inst_rate 689508 # Simulator instruction rate (inst/s) +host_mem_usage 185012 # Number of bytes of host memory used +host_seconds 578.19 # Real time elapsed on the host +host_tick_rate 1033135 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664450 # Number of instructions simulated sim_seconds 0.000597 # Number of seconds simulated -sim_ticks 597363012 # Number of ticks simulated +sim_ticks 597346012 # Number of ticks simulated system.cpu.dcache.ReadReq_accesses 94754482 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 3956.610526 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2956.610526 # average ReadReq mshr miss latency @@ -19,49 +19,49 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 2808780 # system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3939.646399 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2939.646399 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73517520 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 12634446 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 3940.471580 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2940.471580 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73517525 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 12617390 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 3207 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 9427446 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 9415390 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 3207 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40478.963676 # Average number of references to valid blocks. +system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 40527.711224 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 168275209 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3943.523214 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2943.523214 # average overall mshr miss latency -system.cpu.dcache.demand_hits 168271052 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 16393226 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_avg_miss_latency 3944.164258 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency +system.cpu.dcache.demand_hits 168271057 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 16376170 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_misses 4157 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 12236226 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 12224170 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 4157 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.overall_accesses 168275209 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3943.523214 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2943.523214 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 168271052 # number of overall hits -system.cpu.dcache.overall_miss_latency 16393226 # number of overall miss cycles +system.cpu.dcache.overall_avg_miss_latency 3944.164258 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 168271057 # number of overall hits +system.cpu.dcache.overall_miss_latency 16376170 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_misses 4157 # number of overall misses +system.cpu.dcache.overall_misses 4152 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 12236226 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 12224170 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 4157 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -74,24 +74,24 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.sampled_refs 4157 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3222.448687 # Cycle average of tags in use -system.cpu.dcache.total_refs 168271052 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3222.413784 # Cycle average of tags in use +system.cpu.dcache.total_refs 168271057 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 625 # number of writebacks system.cpu.icache.ReadReq_accesses 398664451 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3820.892216 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.892216 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 3820.906097 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.906097 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 398660777 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 14037958 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 14038009 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 3674 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 10363958 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10364009 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 3674 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked system.cpu.icache.avg_refs 108508.649156 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked @@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 398664451 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3820.892216 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2820.892216 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 3820.906097 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency system.cpu.icache.demand_hits 398660777 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 14037958 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 14038009 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses system.cpu.icache.demand_misses 3674 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 10363958 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10364009 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 3674 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.overall_accesses 398664451 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3820.892216 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2820.892216 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_miss_latency 3820.906097 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 398660777 # number of overall hits -system.cpu.icache.overall_miss_latency 14037958 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 14038009 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses system.cpu.icache.overall_misses 3674 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 10363958 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10364009 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 3674 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -138,57 +138,57 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.icache.replacements 1770 # number of replacements system.cpu.icache.sampled_refs 3674 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1765.884663 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1765.882838 # Cycle average of tags in use system.cpu.icache.total_refs 398660777 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 7831 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2982.860028 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.618942 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 7826 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2983.265505 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.984530 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 21416935 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.916869 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 7180 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13818764 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916869 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 7180 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 21404930 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.916816 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 7175 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 13811764 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916816 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 7175 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.177716 # Average number of references to valid blocks. +system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.177840 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 7831 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2982.860028 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.618942 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 7826 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2983.265505 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 21416935 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.916869 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7180 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 21404930 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.916816 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7175 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 13818764 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.916869 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 13811764 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.916816 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7175 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 8456 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2982.860028 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.618942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency +system.cpu.l2cache.overall_accesses 8451 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2983.265505 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1276 # number of overall hits -system.cpu.l2cache.overall_miss_latency 21416935 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.849101 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7180 # number of overall misses +system.cpu.l2cache.overall_miss_latency 21404930 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.849012 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7175 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 13818764 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.849101 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 13811764 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.849012 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7175 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -201,14 +201,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 7180 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 7175 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 6344.085280 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 6344.042673 # Cycle average of tags in use system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 597363012 # number of cpu cycles simulated +system.cpu.numCycles 597346012 # number of cpu cycles simulated system.cpu.num_insts 398664450 # Number of instructions executed system.cpu.num_refs 174183390 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini index 81e1071eb..59c6e25e2 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -74,11 +59,11 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic egid=100 env= euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin output=cout @@ -100,14 +85,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out index e5012d953..c6e4aa136 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -26,11 +27,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic system=system uid=100 euid=100 @@ -57,15 +58,6 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -83,25 +75,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt index f553125a6..9db3f64bc 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 906784 # Simulator instruction rate (inst/s) -host_mem_usage 147280 # Number of bytes of host memory used -host_seconds 2215.51 # Real time elapsed on the host -host_tick_rate 906784 # Simulator tick rate (ticks/s) +host_inst_rate 1149393 # Simulator instruction rate (inst/s) +host_mem_usage 177516 # Number of bytes of host memory used +host_seconds 1747.87 # Real time elapsed on the host +host_tick_rate 1149393 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2008987724 # Number of instructions simulated +sim_insts 2008987607 # Number of instructions simulated sim_seconds 0.002009 # Number of seconds simulated -sim_ticks 2008987723 # Number of ticks simulated +sim_ticks 2008987606 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 2008987724 # number of cpu cycles simulated -system.cpu.num_insts 2008987724 # Number of instructions executed -system.cpu.num_refs 722390480 # Number of memory references +system.cpu.numCycles 2008987607 # number of cpu cycles simulated +system.cpu.num_insts 2008987607 # Number of instructions executed +system.cpu.num_refs 722390435 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr index 9135960d0..bc72461c8 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr @@ -1,2 +1,3 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: ignoring syscall sigprocmask(1, 0, ...) diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini index fa4ee72da..5f64dcebd 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -197,11 +182,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing egid=100 env= euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin output=cout @@ -223,14 +208,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out index ea12fcb9a..6998f4828 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -26,11 +27,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing system=system uid=100 euid=100 @@ -178,15 +179,6 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -204,25 +196,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt index 4d20e663a..45f793ab7 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 502967 # Simulator instruction rate (inst/s) -host_mem_usage 217744 # Number of bytes of host memory used -host_seconds 3994.27 # Real time elapsed on the host -host_tick_rate 1895851 # Simulator tick rate (ticks/s) +host_inst_rate 752631 # Simulator instruction rate (inst/s) +host_mem_usage 230876 # Number of bytes of host memory used +host_seconds 2669.29 # Real time elapsed on the host +host_tick_rate 2836913 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2008987724 # Number of instructions simulated +sim_insts 2008987607 # Number of instructions simulated sim_seconds 0.007573 # Number of seconds simulated -sim_ticks 7572549003 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 511070058 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3107.171711 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2107.171711 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 509611866 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4530852932 # number of ReadReq miss cycles +sim_ticks 7572532003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3107.171986 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2107.171986 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4530853333 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3072660932 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3072661333 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 210794909 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 3884.294897 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2884.294897 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 210722955 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 279490555 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 3884.267929 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2884.267929 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 279480846 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 71954 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 207536555 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 207528846 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71954 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 470.762150 # Average number of references to valid blocks. +system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 721864967 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 3143.715362 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 2143.715362 # average overall mshr miss latency -system.cpu.dcache.demand_hits 720334821 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4810343487 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 3143.713388 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency +system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4810334179 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1530146 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3280197487 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3280190179 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1530146 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 721864967 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 3143.715362 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 2143.715362 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 720334821 # number of overall hits -system.cpu.dcache.overall_miss_latency 4810343487 # number of overall miss cycles +system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 3143.713388 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 720334778 # number of overall hits +system.cpu.dcache.overall_miss_latency 4810334179 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1530146 # number of overall misses +system.cpu.dcache.overall_misses 1530144 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3280197487 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3280190179 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1530146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -73,57 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 1526050 # number of replacements -system.cpu.dcache.sampled_refs 1530146 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1526048 # number of replacements +system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4087.472566 # Cycle average of tags in use -system.cpu.dcache.total_refs 720334821 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35194000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 74591 # number of writebacks -system.cpu.icache.ReadReq_accesses 2008987725 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 3103.752500 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 2103.752500 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2008977127 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 32893569 # number of ReadReq miss cycles +system.cpu.dcache.tagsinuse 4087.479154 # Cycle average of tags in use +system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35165000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 74589 # number of writebacks +system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 3103.627312 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 2103.627312 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 32886035 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10598 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 22295569 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 22290035 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10598 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 189561.910455 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 189597.679502 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 2008987725 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 3103.752500 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 2103.752500 # average overall mshr miss latency -system.cpu.icache.demand_hits 2008977127 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 32893569 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 3103.627312 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency +system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 32886035 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses -system.cpu.icache.demand_misses 10598 # number of demand (read+write) misses +system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 22295569 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 22290035 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10598 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 2008987725 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 3103.752500 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 2103.752500 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2008977127 # number of overall hits -system.cpu.icache.overall_miss_latency 32893569 # number of overall miss cycles +system.cpu.icache.overall_accesses 2008987608 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 3103.627312 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 2008977012 # number of overall hits +system.cpu.icache.overall_miss_latency 32886035 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses -system.cpu.icache.overall_misses 10598 # number of overall misses +system.cpu.icache.overall_misses 10596 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 22295569 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 22290035 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10598 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -135,64 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 9048 # number of replacements -system.cpu.icache.sampled_refs 10598 # Sample count of references to valid blocks. +system.cpu.icache.replacements 9046 # number of replacements +system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1472.251444 # Cycle average of tags in use -system.cpu.icache.total_refs 2008977127 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1471.254279 # Cycle average of tags in use +system.cpu.icache.total_refs 2008977012 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 1540744 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 2153.831026 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1111.660796 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 1540740 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 2153.828221 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1111.659139 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 3245534743 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 3245521901 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1506866 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1675123857 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_misses 1506862 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1675116913 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1506866 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 74591 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 73517 # number of WriteReqNoAck|Writeback hits -system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.014399 # miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_misses 1074 # number of WriteReqNoAck|Writeback misses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.014399 # mshr miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 1074 # number of WriteReqNoAck|Writeback MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.071270 # Average number of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_misses 1506862 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 73515 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.014399 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 1074 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.014399 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 1074 # number of Writeback MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 0.071269 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1540744 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 2153.831026 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1111.660796 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 2153.828221 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3245534743 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 3245521901 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1506866 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses 1506862 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1675123857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 1675116913 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1506866 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses 1506862 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 1615335 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 2152.297003 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1111.660796 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 107395 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3245534743 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.933515 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1507940 # number of overall misses +system.cpu.l2cache.overall_accesses 1615329 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 2152.294196 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 107393 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3245521901 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.933516 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1507936 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1675123857 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.932850 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1506866 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1675116913 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.932851 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1506862 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -204,17 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 1474098 # number of replacements -system.cpu.l2cache.sampled_refs 1506866 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1474094 # number of replacements +system.cpu.l2cache.sampled_refs 1506862 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 32444.673070 # Cycle average of tags in use -system.cpu.l2cache.total_refs 107395 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 164218000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 66806 # number of writebacks +system.cpu.l2cache.tagsinuse 32444.706916 # Cycle average of tags in use +system.cpu.l2cache.total_refs 107393 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 164189000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 66804 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 7572549003 # number of cpu cycles simulated -system.cpu.num_insts 2008987724 # Number of instructions executed -system.cpu.num_refs 722390480 # Number of memory references +system.cpu.numCycles 7572532003 # number of cpu cycles simulated +system.cpu.num_insts 2008987607 # Number of instructions executed +system.cpu.num_refs 722390435 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr index 9135960d0..bc72461c8 100644 --- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr @@ -1,2 +1,3 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... warn: ignoring syscall sigprocmask(1, 0, ...) diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini index 6d8732496..179e8ea77 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -74,11 +59,11 @@ icache_port=system.membus.port[1] [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic egid=100 env= euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin output=cout @@ -100,14 +85,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out index 38f919464..725aaed50 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -26,11 +27,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-atomic +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic system=system uid=100 euid=100 @@ -57,15 +58,6 @@ function_trace=false function_trace_start=0 simulate_stalls=false -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -83,25 +75,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt index d73ff13a7..9c60e1316 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 857494 # Simulator instruction rate (inst/s) -host_mem_usage 149092 # Number of bytes of host memory used -host_seconds 103.05 # Real time elapsed on the host -host_tick_rate 857491 # Simulator tick rate (ticks/s) +host_inst_rate 1347543 # Simulator instruction rate (inst/s) +host_mem_usage 179988 # Number of bytes of host memory used +host_seconds 65.56 # Real time elapsed on the host +host_tick_rate 1347535 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 88361899 # Number of instructions simulated +sim_insts 88340674 # Number of instructions simulated sim_seconds 0.000088 # Number of seconds simulated -sim_ticks 88361898 # Number of ticks simulated +sim_ticks 88340673 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 88361899 # number of cpu cycles simulated -system.cpu.num_insts 88361899 # Number of instructions executed -system.cpu.num_refs 35229376 # Number of memory references -system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls +system.cpu.numCycles 88340674 # number of cpu cycles simulated +system.cpu.num_insts 88340674 # Number of instructions executed +system.cpu.num_refs 35224019 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr index 87866a2a5..eb1796ead 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr +++ b/tests/long/50.vortex/ref/alpha/linux/simple-atomic/stderr @@ -1 +1,2 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini index 3e5bdc569..0e1a3c9f1 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -197,11 +182,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing egid=100 env= euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin output=cout @@ -223,14 +208,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out index 9ecf4b55d..0dc85858d 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -26,11 +27,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing system=system uid=100 euid=100 @@ -178,15 +179,6 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -204,25 +196,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt index ae340ffef..9a9778162 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 471701 # Simulator instruction rate (inst/s) -host_mem_usage 255440 # Number of bytes of host memory used -host_seconds 187.33 # Real time elapsed on the host -host_tick_rate 6446013 # Simulator tick rate (ticks/s) +host_inst_rate 704446 # Simulator instruction rate (inst/s) +host_mem_usage 275648 # Number of bytes of host memory used +host_seconds 125.40 # Real time elapsed on the host +host_tick_rate 9716991 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 88361899 # Number of instructions simulated -sim_seconds 0.001208 # Number of seconds simulated -sim_ticks 1207510003 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 20281385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3631.637073 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2631.637073 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20223321 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 210867375 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002863 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 58064 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 152803375 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 58064 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 14615683 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4569.538784 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3569.538784 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 14473602 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 649244640 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.009721 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 142081 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 507163640 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009721 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 142081 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 173.358930 # Average number of references to valid blocks. +sim_insts 88340674 # Number of instructions simulated +sim_seconds 0.001219 # Number of seconds simulated +sim_ticks 1218558003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3613.021476 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2613.021476 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 219545250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 158780250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 4540.238491 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3540.238491 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 651878362 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 508300362 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34897068 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4297.444428 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3297.444428 # average overall mshr miss latency -system.cpu.dcache.demand_hits 34696923 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 860112015 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005735 # miss rate for demand accesses -system.cpu.dcache.demand_misses 200145 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4264.514136 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency +system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 871423612 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses +system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 659967015 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005735 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 200145 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 667080612 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34897068 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4297.444428 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3297.444428 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 34696923 # number of overall hits -system.cpu.dcache.overall_miss_latency 860112015 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005735 # miss rate for overall accesses -system.cpu.dcache.overall_misses 200145 # number of overall misses +system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4264.514136 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 34685672 # number of overall hits +system.cpu.dcache.overall_miss_latency 871423612 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses +system.cpu.dcache.overall_misses 204343 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 659967015 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005735 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 200145 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 667080612 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -73,57 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 196049 # number of replacements -system.cpu.dcache.sampled_refs 200145 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200247 # number of replacements +system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4056.501584 # Cycle average of tags in use -system.cpu.dcache.total_refs 34696923 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 28890000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147135 # number of writebacks -system.cpu.icache.ReadReq_accesses 88361900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2933.039863 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1933.039863 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 88285387 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 224415679 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000866 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 76513 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 147902679 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000866 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 76513 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1153.861265 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 4056.438323 # Cycle average of tags in use +system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 28900000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147714 # number of writebacks +system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2932.969818 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1932.969818 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 224184481 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 147748481 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 88361900 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2933.039863 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1933.039863 # average overall mshr miss latency -system.cpu.icache.demand_hits 88285387 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 224415679 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000866 # miss rate for demand accesses -system.cpu.icache.demand_misses 76513 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2932.969818 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency +system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 224184481 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses +system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 147902679 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000866 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 76513 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 147748481 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 88361900 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2933.039863 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1933.039863 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 88285387 # number of overall hits -system.cpu.icache.overall_miss_latency 224415679 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000866 # miss rate for overall accesses -system.cpu.icache.overall_misses 76513 # number of overall misses +system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2932.969818 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 88264239 # number of overall hits +system.cpu.icache.overall_miss_latency 224184481 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses +system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 147902679 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000866 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 76513 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 147748481 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -135,64 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 74468 # number of replacements -system.cpu.icache.sampled_refs 76513 # Sample count of references to valid blocks. +system.cpu.icache.replacements 74391 # number of replacements +system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1798.721885 # Cycle average of tags in use -system.cpu.icache.total_refs 88285387 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1796.106842 # Cycle average of tags in use +system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 276658 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3650.746755 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.771607 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 108220 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 614924482 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.608831 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 168438 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 332289704 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.608831 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 168438 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 147135 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 146550 # number of WriteReqNoAck|Writeback hits -system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.003976 # miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_misses 585 # number of WriteReqNoAck|Writeback misses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.003976 # mshr miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 585 # number of WriteReqNoAck|Writeback MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.512545 # Average number of references to valid blocks. +system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3650.218185 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.851350 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 615711503 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 332776620 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147276 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.002965 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 276658 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3650.746755 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.771607 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 108220 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 614924482 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.608831 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 168438 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3650.218185 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 615711503 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 332289704 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.608831 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 168438 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 332776620 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 423793 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3638.111275 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.771607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 254770 # number of overall hits -system.cpu.l2cache.overall_miss_latency 614924482 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.398834 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 169023 # number of overall misses +system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3640.764345 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 259377 # number of overall hits +system.cpu.l2cache.overall_miss_latency 615711503 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 169116 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 332289704 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.397453 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 168438 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 332776620 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -204,17 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 135670 # number of replacements -system.cpu.l2cache.sampled_refs 168438 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 135910 # number of replacements +system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30358.430189 # Cycle average of tags in use -system.cpu.l2cache.total_refs 254770 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 475381000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 115647 # number of writebacks +system.cpu.l2cache.tagsinuse 30401.731729 # Cycle average of tags in use +system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 667816000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 115911 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1207510003 # number of cpu cycles simulated -system.cpu.num_insts 88361899 # Number of instructions executed -system.cpu.num_refs 35229376 # Number of memory references -system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls +system.cpu.numCycles 1218558003 # number of cpu cycles simulated +system.cpu.num_insts 88340674 # Number of instructions executed +system.cpu.num_refs 35224019 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr index 87866a2a5..eb1796ead 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr @@ -1 +1,2 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation... |