diff options
| -rw-r--r-- | cpu/o3/alpha_dyn_inst.hh | 8 | ||||
| -rw-r--r-- | cpu/o3/bpred_unit_impl.hh | 2 | ||||
| -rw-r--r-- | cpu/o3/commit_impl.hh | 9 | ||||
| -rw-r--r-- | cpu/o3/cpu.cc | 6 | ||||
| -rw-r--r-- | cpu/o3/lsq_unit.hh | 2 | ||||
| -rw-r--r-- | cpu/o3/lsq_unit_impl.hh | 39 |
6 files changed, 38 insertions, 28 deletions
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh index e0b73f17e..24774bd0a 100644 --- a/cpu/o3/alpha_dyn_inst.hh +++ b/cpu/o3/alpha_dyn_inst.hh @@ -183,25 +183,25 @@ class AlphaDynInst : public BaseDynInst<Impl> void setIntReg(const StaticInst *si, int idx, uint64_t val) { this->cpu->setIntReg(_destRegIdx[idx], val); - this->instResult.integer = val; + BaseDynInst<Impl>::setIntReg(si, idx, val); } void setFloatRegSingle(const StaticInst *si, int idx, float val) { this->cpu->setFloatRegSingle(_destRegIdx[idx], val); - this->instResult.fp = val; + BaseDynInst<Impl>::setFloatRegSingle(si, idx, val); } void setFloatRegDouble(const StaticInst *si, int idx, double val) { this->cpu->setFloatRegDouble(_destRegIdx[idx], val); - this->instResult.dbl = val; + BaseDynInst<Impl>::setFloatRegDouble(si, idx, val); } void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) { this->cpu->setFloatRegInt(_destRegIdx[idx], val); - this->instResult.integer = val; + BaseDynInst<Impl>::setFloatRegInt(si, idx, val); } /** Returns the physical register index of the i'th destination diff --git a/cpu/o3/bpred_unit_impl.hh b/cpu/o3/bpred_unit_impl.hh index 872c0c62e..d20b31e55 100644 --- a/cpu/o3/bpred_unit_impl.hh +++ b/cpu/o3/bpred_unit_impl.hh @@ -107,11 +107,13 @@ template <class Impl> void TwobitBPredUnit<Impl>::takeOverFrom() { +/* for (int i = 0; i < Impl::MaxThreads; ++i) RAS[i].reset(); BP.reset(); BTB.reset(); +*/ } template <class Impl> diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh index 7834460e2..034565f90 100644 --- a/cpu/o3/commit_impl.hh +++ b/cpu/o3/commit_impl.hh @@ -1117,6 +1117,10 @@ head_inst->isWriteBarrier())*/ panic("Barrier instructions are not handled yet.\n"); } + if (!head_inst->isStore()) { + head_inst->setCompleted(); + } + // Check if the instruction caused a fault. If so, trap. Fault inst_fault = head_inst->getFault(); @@ -1126,6 +1130,11 @@ head_inst->isWriteBarrier())*/ DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n", head_inst->seqNum, head_inst->readPC()); + if (iewStage->hasStoresToWB()) { + DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); + return false; + } + assert(!thread[tid]->inSyscall); thread[tid]->inSyscall = true; diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc index fc8372026..59308d6a9 100644 --- a/cpu/o3/cpu.cc +++ b/cpu/o3/cpu.cc @@ -666,6 +666,12 @@ FullO3CPU<Impl>::switchOut(Sampler *sampler) rename.switchOut(); iew.switchOut(); commit.switchOut(); + + instList.clear(); + while (!removeList.empty()) { + removeList.pop(); + } + if (tickEvent.scheduled()) tickEvent.squash(); sampler->signalSwitched(); diff --git a/cpu/o3/lsq_unit.hh b/cpu/o3/lsq_unit.hh index d17efe96a..623dbdb4b 100644 --- a/cpu/o3/lsq_unit.hh +++ b/cpu/o3/lsq_unit.hh @@ -82,7 +82,9 @@ class LSQUnit { /** The writeback event for the store. Needed for store * conditionals. */ + public: Event *wbEvent; + private: /** The pointer to the LSQ unit that issued the store. */ LSQUnit<Impl> *lsqPtr; }; diff --git a/cpu/o3/lsq_unit_impl.hh b/cpu/o3/lsq_unit_impl.hh index c5ce34c70..3bb9a81f8 100644 --- a/cpu/o3/lsq_unit_impl.hh +++ b/cpu/o3/lsq_unit_impl.hh @@ -672,11 +672,6 @@ LSQUnit<Impl>::writebackStores() req->paddr, *(req->data), storeQueue[storeWBIdx].inst->seqNum); -// if (fault != NoFault) { - //What should we do if there is a fault??? - //for now panic -// panic("Page Table Fault!!!!!\n"); -// } switch(storeQueue[storeWBIdx].size) { case 1: cpu->write(req, (uint8_t &)storeQueue[storeWBIdx].data); @@ -693,8 +688,16 @@ LSQUnit<Impl>::writebackStores() default: panic("Unexpected store size!\n"); } + if (!(req->flags & LOCKED)) { + storeQueue[storeWBIdx].inst->setCompleted(); + } if (dcacheInterface) { + assert(!req->completionEvent); + StoreCompletionEvent *store_event = new + StoreCompletionEvent(storeWBIdx, NULL, this); + req->completionEvent = store_event; + MemAccessResult result = dcacheInterface->access(req); if (isStalled() && @@ -710,16 +713,12 @@ LSQUnit<Impl>::writebackStores() if (result != MA_HIT && dcacheInterface->doEvents()) { typename IEW::LdWritebackEvent *wb = NULL; if (req->flags & LOCKED) { - // Stx_C does not generate a system port transaction. -/* - if (cpu->lockFlag && cpu->lockAddr == req->paddr) { - req->result=1; - } else { - req->result = 0; - } -*/ - wb = new typename IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst, - iewStage); + // Stx_C should not generate a system port transaction, + // but that might be hard to accomplish. + wb = new typename + IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst, + iewStage); + store_event->wbEvent = wb; } DPRINTF(LSQUnit,"D-Cache Write Miss!\n"); @@ -727,12 +726,6 @@ LSQUnit<Impl>::writebackStores() DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", storeQueue[storeWBIdx].inst->seqNum); - // Will stores need their own kind of writeback events? - // Do stores even need writeback events? - assert(!req->completionEvent); - req->completionEvent = new - StoreCompletionEvent(storeWBIdx, wb, this); - lastDcacheStall = curTick; // _status = DcacheMissStall; @@ -766,10 +759,8 @@ LSQUnit<Impl>::writebackStores() typename IEW::LdWritebackEvent *wb = new typename IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst, iewStage); - wb->schedule(curTick); + store_event->wbEvent = wb; } - - completeStore(storeWBIdx); } incrStIdx(storeWBIdx); |