diff options
| -rw-r--r-- | configs/common/FSConfig.py | 12 | ||||
| -rw-r--r-- | configs/example/fs.py | 7 | ||||
| -rw-r--r-- | src/mem/Bridge.py | 17 | ||||
| -rw-r--r-- | src/mem/SConscript | 2 | ||||
| -rw-r--r-- | src/mem/bridge.cc | 268 | ||||
| -rw-r--r-- | src/mem/bridge.hh | 138 | ||||
| -rw-r--r-- | tests/configs/twosys-tsunami-simple-atomic.py | 6 |
7 files changed, 187 insertions, 263 deletions
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 0e26242aa..0515fc53a 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -71,7 +71,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None): self.membus = MemBus() # By default the bridge responds to all addresses above the I/O # base address (including the PCI config space) - self.bridge = Bridge(delay='50ns', nack_delay='4ns', + self.bridge = Bridge(delay='50ns', ranges = [AddrRange(IO_address_space_base, Addr.max)]) self.physmem = SimpleMemory(range = AddrRange(mdesc.mem())) self.bridge.master = self.iobus.slave @@ -174,7 +174,7 @@ def makeSparcSystem(mem_mode, mdesc = None): self.readfile = mdesc.script() self.iobus = NoncoherentBus() self.membus = MemBus() - self.bridge = Bridge(delay='50ns', nack_delay='4ns') + self.bridge = Bridge(delay='50ns') self.t1000 = T1000() self.t1000.attachOnChipIO(self.membus) self.t1000.attachIO(self.iobus) @@ -240,7 +240,7 @@ def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): self.iobus = NoncoherentBus() self.membus = MemBus() self.membus.badaddr_responder.warn_access = "warn" - self.bridge = Bridge(delay='50ns', nack_delay='4ns') + self.bridge = Bridge(delay='50ns') self.bridge.master = self.iobus.slave self.bridge.slave = self.membus.master @@ -322,7 +322,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None): self.readfile = mdesc.script() self.iobus = NoncoherentBus() self.membus = MemBus() - self.bridge = Bridge(delay='50ns', nack_delay='4ns') + self.bridge = Bridge(delay='50ns') self.physmem = SimpleMemory(range = AddrRange('1GB')) self.bridge.master = self.iobus.slave self.bridge.slave = self.membus.master @@ -368,7 +368,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs): # North Bridge x86_sys.iobus = NoncoherentBus() - x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') + x86_sys.bridge = Bridge(delay='50ns') x86_sys.bridge.master = x86_sys.iobus.slave x86_sys.bridge.slave = x86_sys.membus.master # Allow the bridge to pass through the IO APIC (two pages), @@ -387,7 +387,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs): # Create a bridge from the IO bus to the memory bus to allow access to # the local APIC (two pages) - x86_sys.apicbridge = Bridge(delay='50ns', nack_delay='4ns') + x86_sys.apicbridge = Bridge(delay='50ns') x86_sys.apicbridge.slave = x86_sys.iobus.master x86_sys.apicbridge.master = x86_sys.membus.slave x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, diff --git a/configs/example/fs.py b/configs/example/fs.py index b0eb2f1ae..724e32813 100644 --- a/configs/example/fs.py +++ b/configs/example/fs.py @@ -126,8 +126,7 @@ if options.caches or options.l2cache: test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave else: - test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', - ranges = [test_sys.physmem.range]) + test_sys.iobridge = Bridge(delay='50ns', ranges = [test_sys.physmem.range]) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave @@ -162,8 +161,8 @@ if len(bm) == 2: drive_sys.cpu.fastmem = True if options.kernel is not None: drive_sys.kernel = binary(options.kernel) - drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', - ranges = [drive_sys.physmem.range]) + drive_sys.iobridge = Bridge(delay='50ns', + ranges = [drive_sys.physmem.range]) drive_sys.iobridge.slave = drive_sys.iobus.master drive_sys.iobridge.master = drive_sys.membus.slave diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py index ea8684e1b..62dfb7351 100644 --- a/src/mem/Bridge.py +++ b/src/mem/Bridge.py @@ -1,3 +1,15 @@ +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # @@ -25,6 +37,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Ali Saidi +# Andreas Hansson from m5.params import * from MemObject import MemObject @@ -34,9 +47,7 @@ class Bridge(MemObject): slave = SlavePort('Slave port') master = MasterPort('Master port') req_size = Param.Int(16, "The number of requests to buffer") - resp_size = Param.Int(16, "The number of requests to buffer") + resp_size = Param.Int(16, "The number of responses to buffer") delay = Param.Latency('0ns', "The latency of this bridge") - nack_delay = Param.Latency('0ns', "The latency of this bridge") - write_ack = Param.Bool(False, "Should this bridge ack writes") ranges = VectorParam.AddrRange([AllMemory], "Address ranges to pass through the bridge") diff --git a/src/mem/SConscript b/src/mem/SConscript index d290da875..7aba4f0e7 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -65,7 +65,7 @@ DebugFlag('NoncoherentBus') CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus', 'NoncoherentBus']) -DebugFlag('BusBridge') +DebugFlag('Bridge') DebugFlag('CommMonitor') DebugFlag('LLSC') DebugFlag('MMU') diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc index e9dc68a03..ca3fde0ed 100644 --- a/src/mem/bridge.cc +++ b/src/mem/bridge.cc @@ -49,43 +49,37 @@ */ #include "base/trace.hh" -#include "debug/BusBridge.hh" +#include "debug/Bridge.hh" #include "mem/bridge.hh" #include "params/Bridge.hh" -Bridge::BridgeSlavePort::BridgeSlavePort(const std::string &_name, - Bridge* _bridge, +Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name, + Bridge& _bridge, BridgeMasterPort& _masterPort, - int _delay, int _nack_delay, - int _resp_limit, + int _delay, int _resp_limit, std::vector<Range<Addr> > _ranges) - : SlavePort(_name, _bridge), bridge(_bridge), masterPort(_masterPort), - delay(_delay), nackDelay(_nack_delay), - ranges(_ranges.begin(), _ranges.end()), - outstandingResponses(0), inRetry(false), + : SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort), + delay(_delay), ranges(_ranges.begin(), _ranges.end()), + outstandingResponses(0), retryReq(false), respQueueLimit(_resp_limit), sendEvent(*this) { } -Bridge::BridgeMasterPort::BridgeMasterPort(const std::string &_name, - Bridge* _bridge, +Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name, + Bridge& _bridge, BridgeSlavePort& _slavePort, int _delay, int _req_limit) - : MasterPort(_name, _bridge), bridge(_bridge), slavePort(_slavePort), - delay(_delay), inRetry(false), reqQueueLimit(_req_limit), - sendEvent(*this) + : MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort), + delay(_delay), reqQueueLimit(_req_limit), sendEvent(*this) { } Bridge::Bridge(Params *p) : MemObject(p), - slavePort(p->name + ".slave", this, masterPort, p->delay, - p->nack_delay, p->resp_size, p->ranges), - masterPort(p->name + ".master", this, slavePort, p->delay, p->req_size), - ackWrites(p->write_ack), _params(p) + slavePort(p->name + ".slave", *this, masterPort, p->delay, p->resp_size, + p->ranges), + masterPort(p->name + ".master", *this, slavePort, p->delay, p->req_size) { - if (ackWrites) - panic("No support for acknowledging writes\n"); } MasterPort& @@ -133,7 +127,7 @@ Bridge::BridgeSlavePort::respQueueFull() bool Bridge::BridgeMasterPort::reqQueueFull() { - return requestQueue.size() == reqQueueLimit; + return transmitList.size() == reqQueueLimit; } bool @@ -141,12 +135,12 @@ Bridge::BridgeMasterPort::recvTimingResp(PacketPtr pkt) { // all checks are done when the request is accepted on the slave // side, so we are guaranteed to have space for the response - DPRINTF(BusBridge, "recvTiming: response %s addr 0x%x\n", + DPRINTF(Bridge, "recvTimingResp: %s addr 0x%x\n", pkt->cmdString(), pkt->getAddr()); - DPRINTF(BusBridge, "Request queue size: %d\n", requestQueue.size()); + DPRINTF(Bridge, "Request queue size: %d\n", transmitList.size()); - slavePort.queueForSendTiming(pkt); + slavePort.schedTimingResp(pkt, curTick() + delay); return true; } @@ -154,95 +148,52 @@ Bridge::BridgeMasterPort::recvTimingResp(PacketPtr pkt) bool Bridge::BridgeSlavePort::recvTimingReq(PacketPtr pkt) { - DPRINTF(BusBridge, "recvTiming: request %s addr 0x%x\n", + DPRINTF(Bridge, "recvTimingReq: %s addr 0x%x\n", pkt->cmdString(), pkt->getAddr()); - DPRINTF(BusBridge, "Response queue size: %d outresp: %d\n", - responseQueue.size(), outstandingResponses); + // ensure we do not have something waiting to retry + if(retryReq) + return false; - if (masterPort.reqQueueFull()) { - DPRINTF(BusBridge, "Request queue full, nacking\n"); - nackRequest(pkt); - return true; - } + DPRINTF(Bridge, "Response queue size: %d outresp: %d\n", + transmitList.size(), outstandingResponses); - if (pkt->needsResponse()) { + if (masterPort.reqQueueFull()) { + DPRINTF(Bridge, "Request queue full\n"); + retryReq = true; + } else if (pkt->needsResponse()) { if (respQueueFull()) { - DPRINTF(BusBridge, - "Response queue full, no space for response, nacking\n"); - DPRINTF(BusBridge, - "queue size: %d outstanding resp: %d\n", - responseQueue.size(), outstandingResponses); - nackRequest(pkt); - return true; + DPRINTF(Bridge, "Response queue full\n"); + retryReq = true; } else { - DPRINTF(BusBridge, "Request Needs response, reserving space\n"); + DPRINTF(Bridge, "Reserving space for response\n"); assert(outstandingResponses != respQueueLimit); ++outstandingResponses; + retryReq = false; + masterPort.schedTimingReq(pkt, curTick() + delay); } } - masterPort.queueForSendTiming(pkt); - - return true; + // remember that we are now stalling a packet and that we have to + // tell the sending master to retry once space becomes available, + // we make no distinction whether the stalling is due to the + // request queue or response queue being full + return !retryReq; } void -Bridge::BridgeSlavePort::nackRequest(PacketPtr pkt) +Bridge::BridgeSlavePort::retryStalledReq() { - // Nack the packet - pkt->makeTimingResponse(); - pkt->setNacked(); - - // The Nack packets are stored in the response queue just like any - // other response, but they do not occupy any space as this is - // tracked by the outstandingResponses, this guarantees space for - // the Nack packets, but implicitly means we have an (unrealistic) - // unbounded Nack queue. - - // put it on the list to send - Tick readyTime = curTick() + nackDelay; - DeferredResponse resp(pkt, readyTime, true); - - // nothing on the list, add it and we're done - if (responseQueue.empty()) { - assert(!sendEvent.scheduled()); - bridge->schedule(sendEvent, readyTime); - responseQueue.push_back(resp); - return; + if (retryReq) { + DPRINTF(Bridge, "Request waiting for retry, now retrying\n"); + retryReq = false; + sendRetry(); } - - assert(sendEvent.scheduled() || inRetry); - - // does it go at the end? - if (readyTime >= responseQueue.back().ready) { - responseQueue.push_back(resp); - return; - } - - // ok, somewhere in the middle, fun - std::list<DeferredResponse>::iterator i = responseQueue.begin(); - std::list<DeferredResponse>::iterator end = responseQueue.end(); - std::list<DeferredResponse>::iterator begin = responseQueue.begin(); - bool done = false; - - while (i != end && !done) { - if (readyTime < (*i).ready) { - if (i == begin) - bridge->reschedule(sendEvent, readyTime); - responseQueue.insert(i, resp); - done = true; - } - i++; - } - assert(done); } void -Bridge::BridgeMasterPort::queueForSendTiming(PacketPtr pkt) +Bridge::BridgeMasterPort::schedTimingReq(PacketPtr pkt, Tick when) { - Tick readyTime = curTick() + delay; - // If we expect to see a response, we need to restore the source // and destination field that is potentially changed by a second // bus @@ -257,18 +208,18 @@ Bridge::BridgeMasterPort::queueForSendTiming(PacketPtr pkt) // need to schedule an event to do the transmit. Otherwise there // should already be an event scheduled for sending the head // packet. - if (requestQueue.empty()) { - bridge->schedule(sendEvent, readyTime); + if (transmitList.empty()) { + bridge.schedule(sendEvent, when); } - assert(requestQueue.size() != reqQueueLimit); + assert(transmitList.size() != reqQueueLimit); - requestQueue.push_back(DeferredRequest(pkt, readyTime)); + transmitList.push_back(DeferredPacket(pkt, when)); } void -Bridge::BridgeSlavePort::queueForSendTiming(PacketPtr pkt) +Bridge::BridgeSlavePort::schedTimingResp(PacketPtr pkt, Tick when) { // This is a response for a request we forwarded earlier. The // corresponding request state should be stored in the packet's @@ -278,119 +229,124 @@ Bridge::BridgeSlavePort::queueForSendTiming(PacketPtr pkt) // set up new packet dest & senderState based on values saved // from original request req_state->fixResponse(pkt); + delete req_state; // the bridge assumes that at least one bus has set the // destination field of the packet assert(pkt->isDestValid()); - DPRINTF(BusBridge, "response, new dest %d\n", pkt->getDest()); - delete req_state; - - Tick readyTime = curTick() + delay; + DPRINTF(Bridge, "response, new dest %d\n", pkt->getDest()); // If we're about to put this packet at the head of the queue, we // need to schedule an event to do the transmit. Otherwise there // should already be an event scheduled for sending the head // packet. - if (responseQueue.empty()) { - bridge->schedule(sendEvent, readyTime); + if (transmitList.empty()) { + bridge.schedule(sendEvent, when); } - responseQueue.push_back(DeferredResponse(pkt, readyTime)); + + transmitList.push_back(DeferredPacket(pkt, when)); } void -Bridge::BridgeMasterPort::trySend() +Bridge::BridgeMasterPort::trySendTiming() { - assert(!requestQueue.empty()); + assert(!transmitList.empty()); - DeferredRequest req = requestQueue.front(); + DeferredPacket req = transmitList.front(); - assert(req.ready <= curTick()); + assert(req.tick <= curTick()); PacketPtr pkt = req.pkt; - DPRINTF(BusBridge, "trySend request: addr 0x%x\n", pkt->getAddr()); + DPRINTF(Bridge, "trySend request addr 0x%x, queue size %d\n", + pkt->getAddr(), transmitList.size()); if (sendTimingReq(pkt)) { // send successful - requestQueue.pop_front(); + transmitList.pop_front(); + DPRINTF(Bridge, "trySend request successful\n"); // If there are more packets to send, schedule event to try again. - if (!requestQueue.empty()) { - req = requestQueue.front(); - DPRINTF(BusBridge, "Scheduling next send\n"); - bridge->schedule(sendEvent, - std::max(req.ready, curTick() + 1)); + if (!transmitList.empty()) { + req = transmitList.front(); + DPRINTF(Bridge, "Scheduling next send\n"); + bridge.schedule(sendEvent, std::max(req.tick, + bridge.nextCycle())); } - } else { - inRetry = true; + + // if we have stalled a request due to a full request queue, + // then send a retry at this point, also note that if the + // request we stalled was waiting for the response queue + // rather than the request queue we might stall it again + slavePort.retryStalledReq(); } - DPRINTF(BusBridge, "trySend: request queue size: %d\n", - requestQueue.size()); + // if the send failed, then we try again once we receive a retry, + // and therefore there is no need to take any action } void -Bridge::BridgeSlavePort::trySend() +Bridge::BridgeSlavePort::trySendTiming() { - assert(!responseQueue.empty()); + assert(!transmitList.empty()); - DeferredResponse resp = responseQueue.front(); + DeferredPacket resp = transmitList.front(); - assert(resp.ready <= curTick()); + assert(resp.tick <= curTick()); PacketPtr pkt = resp.pkt; - DPRINTF(BusBridge, "trySend response: dest %d addr 0x%x\n", - pkt->getDest(), pkt->getAddr()); - - bool was_nacked_here = resp.nackedHere; + DPRINTF(Bridge, "trySend response addr 0x%x, outstanding %d\n", + pkt->getAddr(), outstandingResponses); if (sendTimingResp(pkt)) { - DPRINTF(BusBridge, " successful\n"); // send successful - responseQueue.pop_front(); + transmitList.pop_front(); + DPRINTF(Bridge, "trySend response successful\n"); - if (!was_nacked_here) { - assert(outstandingResponses != 0); - --outstandingResponses; - } + assert(outstandingResponses != 0); + --outstandingResponses; // If there are more packets to send, schedule event to try again. - if (!responseQueue.empty()) { - resp = responseQueue.front(); - DPRINTF(BusBridge, "Scheduling next send\n"); - bridge->schedule(sendEvent, - std::max(resp.ready, curTick() + 1)); + if (!transmitList.empty()) { + resp = transmitList.front(); + DPRINTF(Bridge, "Scheduling next send\n"); + bridge.schedule(sendEvent, std::max(resp.tick, + bridge.nextCycle())); + } + + // if there is space in the request queue and we were stalling + // a request, it will definitely be possible to accept it now + // since there is guaranteed space in the response queue + if (!masterPort.reqQueueFull() && retryReq) { + DPRINTF(Bridge, "Request waiting for retry, now retrying\n"); + retryReq = false; + sendRetry(); } - } else { - DPRINTF(BusBridge, " unsuccessful\n"); - inRetry = true; } - DPRINTF(BusBridge, "trySend: queue size: %d outstanding resp: %d\n", - responseQueue.size(), outstandingResponses); + // if the send failed, then we try again once we receive a retry, + // and therefore there is no need to take any action } void Bridge::BridgeMasterPort::recvRetry() { - inRetry = false; - Tick nextReady = requestQueue.front().ready; + Tick nextReady = transmitList.front().tick; if (nextReady <= curTick()) - trySend(); + trySendTiming(); else - bridge->schedule(sendEvent, nextReady); + bridge.schedule(sendEvent, nextReady); } void Bridge::BridgeSlavePort::recvRetry() { - inRetry = false; - Tick nextReady = responseQueue.front().ready; + Tick nextReady = transmitList.front().tick; if (nextReady <= curTick()) - trySend(); + trySendTiming(); else - bridge->schedule(sendEvent, nextReady); + bridge.schedule(sendEvent, nextReady); } Tick @@ -402,12 +358,12 @@ Bridge::BridgeSlavePort::recvAtomic(PacketPtr pkt) void Bridge::BridgeSlavePort::recvFunctional(PacketPtr pkt) { - std::list<DeferredResponse>::iterator i; + std::list<DeferredPacket>::iterator i; pkt->pushLabel(name()); // check the response queue - for (i = responseQueue.begin(); i != responseQueue.end(); ++i) { + for (i = transmitList.begin(); i != transmitList.end(); ++i) { if (pkt->checkFunctional((*i).pkt)) { pkt->makeResponse(); return; @@ -429,9 +385,9 @@ bool Bridge::BridgeMasterPort::checkFunctional(PacketPtr pkt) { bool found = false; - std::list<DeferredRequest>::iterator i = requestQueue.begin(); + std::list<DeferredPacket>::iterator i = transmitList.begin(); - while(i != requestQueue.end() && !found) { + while(i != transmitList.end() && !found) { if (pkt->checkFunctional((*i).pkt)) { pkt->makeResponse(); found = true; diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh index cc428e44d..cf7673c47 100644 --- a/src/mem/bridge.hh +++ b/src/mem/bridge.hh @@ -52,15 +52,10 @@ #define __MEM_BRIDGE_HH__ #include <list> -#include <queue> -#include <string> #include "base/types.hh" #include "mem/mem_object.hh" -#include "mem/packet.hh" -#include "mem/port.hh" #include "params/Bridge.hh" -#include "sim/eventq.hh" /** * A bridge is used to interface two different busses (or in general a @@ -71,9 +66,9 @@ * The bridge comprises a slave port and a master port, that buffer * outgoing responses and requests respectively. Buffer space is * reserved when a request arrives, also reserving response space - * before forwarding the request. An incoming request is always - * accepted (recvTiming returns true), but is potentially NACKed if - * there is no request space or response space. + * before forwarding the request. If there is no space present, then + * the bridge will delay accepting the packet until space becomes + * available. */ class Bridge : public MemObject { @@ -106,40 +101,18 @@ class Bridge : public MemObject }; /** - * A deferred request stores a packet along with its scheduled - * transmission time, and whether we can expect to see a response - * or not. + * A deferred packet stores a packet along with its scheduled + * transmission time */ - class DeferredRequest + class DeferredPacket { public: - Tick ready; + Tick tick; PacketPtr pkt; - bool expectResponse; - DeferredRequest(PacketPtr _pkt, Tick t) - : ready(t), pkt(_pkt), expectResponse(_pkt->needsResponse()) - { } - }; - - /** - * A deferred response stores a packet along with its scheduled - * transmission time. It also contains information of whether the - * bridge NACKed the packet to be able to correctly maintain - * counters of outstanding responses. - */ - class DeferredResponse { - - public: - - Tick ready; - PacketPtr pkt; - bool nackedHere; - - DeferredResponse(PacketPtr _pkt, Tick t, bool nack = false) - : ready(t), pkt(_pkt), nackedHere(nack) + DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt) { } }; @@ -157,21 +130,18 @@ class Bridge : public MemObject private: - /** A pointer to the bridge to which this port belongs. */ - Bridge *bridge; + /** The bridge to which this port belongs. */ + Bridge& bridge; /** - * Master port on the other side of the bridge - * (connected to the other bus). + * Master port on the other side of the bridge (connected to + * the other bus). */ BridgeMasterPort& masterPort; /** Minimum request delay though this bridge. */ Tick delay; - /** Min delay to respond with a nack. */ - Tick nackDelay; - /** Address ranges to pass through the bridge */ AddrRangeList ranges; @@ -180,13 +150,13 @@ class Bridge : public MemObject * queue for a specified delay to model the processing delay * of the bridge. */ - std::list<DeferredResponse> responseQueue; + std::list<DeferredPacket> transmitList; /** Counter to track the outstanding responses. */ unsigned int outstandingResponses; - /** If we're waiting for a retry to happen. */ - bool inRetry; + /** If we should send a retry when space becomes available. */ + bool retryReq; /** Max queue size for reserved responses. */ unsigned int respQueueLimit; @@ -199,22 +169,15 @@ class Bridge : public MemObject bool respQueueFull(); /** - * Turn the request packet into a NACK response and put it in - * the response queue and schedule its transmission. - * - * @param pkt the request packet to NACK - */ - void nackRequest(PacketPtr pkt); - - /** * Handle send event, scheduled when the packet at the head of * the response queue is ready to transmit (for timing * accesses only). */ - void trySend(); + void trySendTiming(); /** Send event for the response queue. */ - EventWrapper<BridgeSlavePort, &BridgeSlavePort::trySend> sendEvent; + EventWrapper<BridgeSlavePort, + &BridgeSlavePort::trySendTiming> sendEvent; public: @@ -225,44 +188,50 @@ class Bridge : public MemObject * @param _bridge the structural owner * @param _masterPort the master port on the other side of the bridge * @param _delay the delay from seeing a response to sending it - * @param _nack_delay the delay from a NACK to sending the response * @param _resp_limit the size of the response queue * @param _ranges a number of address ranges to forward */ - BridgeSlavePort(const std::string &_name, Bridge *_bridge, + BridgeSlavePort(const std::string& _name, Bridge& _bridge, BridgeMasterPort& _masterPort, int _delay, - int _nack_delay, int _resp_limit, - std::vector<Range<Addr> > _ranges); + int _resp_limit, std::vector<Range<Addr> > _ranges); /** * Queue a response packet to be sent out later and also schedule * a send if necessary. * * @param pkt a response to send out after a delay + * @param when tick when response packet should be sent + */ + void schedTimingResp(PacketPtr pkt, Tick when); + + /** + * Retry any stalled request that we have failed to accept at + * an earlier point in time. This call will do nothing if no + * request is waiting. */ - void queueForSendTiming(PacketPtr pkt); + void retryStalledReq(); protected: /** When receiving a timing request from the peer port, pass it to the bridge. */ - virtual bool recvTimingReq(PacketPtr pkt); + bool recvTimingReq(PacketPtr pkt); /** When receiving a retry request from the peer port, pass it to the bridge. */ - virtual void recvRetry(); + void recvRetry(); /** When receiving a Atomic requestfrom the peer port, pass it to the bridge. */ - virtual Tick recvAtomic(PacketPtr pkt); + Tick recvAtomic(PacketPtr pkt); /** When receiving a Functional request from the peer port, pass it to the bridge. */ - virtual void recvFunctional(PacketPtr pkt); + void recvFunctional(PacketPtr pkt); /** When receiving a address range request the peer port, pass it to the bridge. */ - virtual AddrRangeList getAddrRanges() const; + AddrRangeList getAddrRanges() const; }; @@ -276,12 +245,12 @@ class Bridge : public MemObject private: - /** A pointer to the bridge to which this port belongs. */ - Bridge* bridge; + /** The bridge to which this port belongs. */ + Bridge& bridge; /** - * Pointer to the slave port on the other side of the bridge - * (connected to the other bus). + * The slave port on the other side of the bridge (connected + * to the other bus). */ BridgeSlavePort& slavePort; @@ -293,10 +262,7 @@ class Bridge : public MemObject * queue for a specified delay to model the processing delay * of the bridge. */ - std::list<DeferredRequest> requestQueue; - - /** If we're waiting for a retry to happen. */ - bool inRetry; + std::list<DeferredPacket> transmitList; /** Max queue size for request packets */ unsigned int reqQueueLimit; @@ -306,10 +272,11 @@ class Bridge : public MemObject * the outbound queue is ready to transmit (for timing * accesses only). */ - void trySend(); + void trySendTiming(); /** Send event for the request queue. */ - EventWrapper<BridgeMasterPort, &BridgeMasterPort::trySend> sendEvent; + EventWrapper<BridgeMasterPort, + &BridgeMasterPort::trySendTiming> sendEvent; public: @@ -322,7 +289,7 @@ class Bridge : public MemObject * @param _delay the delay from seeing a request to sending it * @param _req_limit the size of the request queue */ - BridgeMasterPort(const std::string &_name, Bridge *_bridge, + BridgeMasterPort(const std::string& _name, Bridge& _bridge, BridgeSlavePort& _slavePort, int _delay, int _req_limit); @@ -338,8 +305,9 @@ class Bridge : public MemObject * a send if necessary. * * @param pkt a request to send out after a delay + * @param when tick when response packet should be sent */ - void queueForSendTiming(PacketPtr pkt); + void schedTimingReq(PacketPtr pkt, Tick when); /** * Check a functional request against the packets in our @@ -355,11 +323,11 @@ class Bridge : public MemObject /** When receiving a timing request from the peer port, pass it to the bridge. */ - virtual bool recvTimingResp(PacketPtr pkt); + bool recvTimingResp(PacketPtr pkt); /** When receiving a retry request from the peer port, pass it to the bridge. */ - virtual void recvRetry(); + void recvRetry(); }; /** Slave port of the bridge. */ @@ -368,17 +336,7 @@ class Bridge : public MemObject /** Master port of the bridge. */ BridgeMasterPort masterPort; - /** If this bridge should acknowledge writes. */ - bool ackWrites; - public: - typedef BridgeParams Params; - - protected: - Params *_params; - - public: - const Params *params() const { return _params; } virtual MasterPort& getMasterPort(const std::string& if_name, int idx = -1); @@ -386,6 +344,8 @@ class Bridge : public MemObject virtual void init(); + typedef BridgeParams Params; + Bridge(Params *p); }; diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py index 84f70db14..d0c90e135 100644 --- a/tests/configs/twosys-tsunami-simple-atomic.py +++ b/tests/configs/twosys-tsunami-simple-atomic.py @@ -41,8 +41,7 @@ test_sys.cpu.connectAllPorts(test_sys.membus) # In contrast to the other (one-system) Tsunami configurations we do # not have an IO cache but instead rely on an IO bridge for accesses # from masters on the IO bus to the memory bus -test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', - ranges = [AddrRange(0, '8GB')]) +test_sys.iobridge = Bridge(delay='50ns', ranges = [AddrRange(0, '8GB')]) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave @@ -52,8 +51,7 @@ drive_sys.cpu = AtomicSimpleCPU(cpu_id=0) # create the interrupt controller drive_sys.cpu.createInterruptController() drive_sys.cpu.connectAllPorts(drive_sys.membus) -drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', - ranges = [AddrRange(0, '8GB')]) +drive_sys.iobridge = Bridge(delay='50ns', ranges = [AddrRange(0, '8GB')]) drive_sys.iobridge.slave = drive_sys.iobus.master drive_sys.iobridge.master = drive_sys.membus.slave |