diff options
| -rw-r--r-- | src/arch/x86/isa/microops/ldstop.isa | 2 | ||||
| -rw-r--r-- | src/arch/x86/tlb.cc | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 8bcf55c99..75519f417 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -361,7 +361,7 @@ let {{ exec_output = "" calculateEA = ''' - EA = bits(SegBase + scale * Index + Base + disp, addressSize * 8 - 1, 0); + EA = SegBase + bits(scale * Index + Base + disp, addressSize * 8 - 1, 0); ''' def defineMicroLoadOp(mnemonic, code, bigCode='', diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 89561f851..100f8cf0f 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -281,6 +281,9 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, return new GeneralProtection(0); } } + if (m5Reg.mode != LongMode || + (flags & (AddrSizeFlagBit << FlagShift))) + vaddr &= mask(32); // If paging is enabled, do the translation. if (m5Reg.paging) { DPRINTF(TLB, "Paging enabled.\n"); |