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-rw-r--r--src/arch/x86/tlb.cc3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index f5e214a88..5d101a5ae 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -571,6 +571,9 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
// If we're not in 64-bit mode, do protection/limit checks
if (!efer.lma || !csAttr.longMode) {
DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
+ // Check for a NULL segment selector.
+ if (!tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
+ return new GeneralProtection(0);
SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
if (!attr.writable && write)
return new GeneralProtection(0);