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-rw-r--r--configs/test/test.py2
-rw-r--r--src/cpu/base.cc2
-rw-r--r--src/cpu/base.hh5
-rw-r--r--src/cpu/simple/atomic.cc22
-rw-r--r--src/cpu/simple/atomic.hh2
-rw-r--r--src/cpu/simple/timing.cc26
-rw-r--r--src/cpu/simple/timing.hh2
-rw-r--r--src/mem/cache/base_cache.cc18
-rw-r--r--src/mem/cache/base_cache.hh29
9 files changed, 78 insertions, 30 deletions
diff --git a/configs/test/test.py b/configs/test/test.py
index 625304a08..e7b0971ef 100644
--- a/configs/test/test.py
+++ b/configs/test/test.py
@@ -75,6 +75,8 @@ else:
cpu = AtomicSimpleCPU()
cpu.workload = process
cpu.mem = magicbus
+cpu.icache_port=magicbus.port
+cpu.dcache_port=magicbus.port
system = System(physmem = mem, cpu = cpu)
mem.port = magicbus.port
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 0b9c80591..548f012df 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -63,7 +63,7 @@ BaseCPU::BaseCPU(Params *p)
params(p), number_of_threads(p->numberOfThreads), system(p->system)
#else
BaseCPU::BaseCPU(Params *p)
- : SimObject(p->name), clock(p->clock), params(p),
+ : MemObject(p->name), clock(p->clock), params(p),
number_of_threads(p->numberOfThreads), system(p->system)
#endif
{
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 5256a411f..2be6e4e81 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -37,15 +37,16 @@
#include "base/statistics.hh"
#include "config/full_system.hh"
#include "sim/eventq.hh"
-#include "sim/sim_object.hh"
+#include "mem/mem_object.hh"
#include "arch/isa_traits.hh"
class BranchPred;
class CheckerCPU;
class ThreadContext;
class System;
+class Port;
-class BaseCPU : public SimObject
+class BaseCPU : public MemObject
{
protected:
// CPU's clock period in terms of the number of ticks of curTime.
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index b7202cbbb..12bfdeb9b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -55,18 +55,28 @@ AtomicSimpleCPU::TickEvent::description()
return "AtomicSimpleCPU tick event";
}
+Port *
+AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
+{
+ if (if_name == "dcache_port")
+ return &dcachePort;
+ else if (if_name == "icache_port")
+ return &icachePort;
+ else
+ panic("No Such Port\n");
+}
void
AtomicSimpleCPU::init()
{
//Create Memory Ports (conect them up)
- Port *mem_dport = mem->getPort("");
- dcachePort.setPeer(mem_dport);
- mem_dport->setPeer(&dcachePort);
+// Port *mem_dport = mem->getPort("");
+// dcachePort.setPeer(mem_dport);
+// mem_dport->setPeer(&dcachePort);
- Port *mem_iport = mem->getPort("");
- icachePort.setPeer(mem_iport);
- mem_iport->setPeer(&icachePort);
+// Port *mem_iport = mem->getPort("");
+// icachePort.setPeer(mem_iport);
+// mem_iport->setPeer(&icachePort);
BaseCPU::init();
#if FULL_SYSTEM
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 951a8da06..179b4a721 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -122,6 +122,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
public:
+ virtual Port *getPort(const std::string &if_name, int idx = -1);
+
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index eb5895949..e55301c6b 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -37,19 +37,20 @@
using namespace std;
using namespace TheISA;
+Port *
+TimingSimpleCPU::getPort(const std::string &if_name, int idx)
+{
+ if (if_name == "dcache_port")
+ return &dcachePort;
+ else if (if_name == "icache_port")
+ return &icachePort;
+ else
+ panic("No Such Port\n");
+}
void
TimingSimpleCPU::init()
{
- //Create Memory Ports (conect them up)
- Port *mem_dport = mem->getPort("");
- dcachePort.setPeer(mem_dport);
- mem_dport->setPeer(&dcachePort);
-
- Port *mem_iport = mem->getPort("");
- icachePort.setPeer(mem_iport);
- mem_iport->setPeer(&icachePort);
-
BaseCPU::init();
#if FULL_SYSTEM
for (int i = 0; i < threadContexts.size(); ++i) {
@@ -463,12 +464,7 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
bool
TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
{
- if (cpu->_status == DcacheWaitResponse)
- cpu->completeDataAccess(pkt);
- else if (cpu->_status == IcacheWaitResponse)
- cpu->completeIfetch(pkt);
- else
- assert("OOPS" && 0);
+ cpu->completeIfetch(pkt);
return true;
}
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index f9bc0f352..0a3f91e6c 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -132,6 +132,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
public:
+ virtual Port *getPort(const std::string &if_name, int idx = -1);
+
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 4fbda4074..be9769fdc 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -59,7 +59,7 @@ void
BaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
{
- cache->getAddressRanges(resp, snoop);
+ cache->getAddressRanges(resp, snoop, isCpuSide);
}
int
@@ -144,7 +144,13 @@ BaseCache::getPort(const std::string &if_name, int idx)
cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
return cpuSidePort;
}
- if (if_name == "functional")
+ else if (if_name == "functional")
+ {
+ if(cpuSidePort == NULL)
+ cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
+ return cpuSidePort;
+ }
+ else if (if_name == "cpu_side")
{
if(cpuSidePort == NULL)
cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
@@ -161,6 +167,14 @@ BaseCache::getPort(const std::string &if_name, int idx)
}
void
+BaseCache::init()
+{
+ if (!cpuSidePort || !memSidePort)
+ panic("Cache not hooked up on both sides\n");
+ cpuSidePort->sendStatusChange(Port::RangeChange);
+}
+
+void
BaseCache::regStats()
{
Request temp_req((Addr) NULL, 4, 0);
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index f832735db..0d1bfdfdb 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -143,9 +143,19 @@ class BaseCache : public MemObject
fatal("No implementation");
}
- virtual void recvStatusChange(Port::Status status, bool isCpuSide)
+ void recvStatusChange(Port::Status status, bool isCpuSide)
{
- fatal("No implementation");
+ if (status == Port::RangeChange)
+ {
+ if (!isCpuSide)
+ {
+ cpuSidePort->sendStatusChange(Port::RangeChange);
+ }
+ else
+ {
+ memSidePort->sendStatusChange(Port::RangeChange);
+ }
+ }
}
virtual Packet *getPacket()
@@ -320,6 +330,8 @@ class BaseCache : public MemObject
memSidePort = NULL;
}
+ virtual void init();
+
/**
* Query block size of a cache.
* @return The block size
@@ -519,9 +531,18 @@ class BaseCache : public MemObject
*/
void rangeChange() {}
- void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop)
+ void getAddressRanges(AddrRangeList &resp, AddrRangeList &snoop, bool isCpuSide)
{
- panic("Unimplimented\n");
+ if (isCpuSide)
+ {
+ AddrRangeList dummy;
+ memSidePort->getPeerAddressRanges(resp, dummy);
+ }
+ else
+ {
+ //This is where snoops get updated
+ return;
+ }
}
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 11:34:47 +0000