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-rw-r--r--cpu/simple/cpu.cc17
-rw-r--r--cpu/simple/cpu.hh4
-rw-r--r--mem/physical.cc62
-rw-r--r--mem/physical.hh11
-rw-r--r--python/m5/objects/BaseCPU.py2
-rw-r--r--sim/process.cc2
6 files changed, 42 insertions, 56 deletions
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index c34cf9079..7da000a35 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -143,6 +143,17 @@ SimpleCPU::SimpleCPU(Params *p)
memPort = &dcachePort;
+ //Create Memory Ports (conect them up)
+ p->mem->addPort("DCACHE");
+ dcachePort.setPeer(p->mem->getPort("DCACHE"));
+ (p->mem->getPort("DCACHE"))->setPeer(&dcachePort);
+
+ p->mem->addPort("ICACHE");
+ icachePort.setPeer(p->mem->getPort("ICACHE"));
+ (p->mem->getPort("ICACHE"))->setPeer(&icachePort);
+
+
+
req = new CpuRequest;
req->asid = 0;
@@ -1019,11 +1030,11 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
#if FULL_SYSTEM
SimObjectParam<AlphaITB *> itb;
SimObjectParam<AlphaDTB *> dtb;
- SimObjectParam<FunctionalMemory *> mem;
SimObjectParam<System *> system;
Param<int> cpu_id;
Param<Tick> profile;
#else
+ SimObjectParam<Memory *> mem;
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
@@ -1050,11 +1061,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
#if FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
INIT_PARAM(dtb, "Data TLB"),
- INIT_PARAM(mem, "memory"),
INIT_PARAM(system, "system object"),
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM(profile, ""),
#else
+ INIT_PARAM(mem, "memory"),
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
@@ -1085,11 +1096,11 @@ CREATE_SIM_OBJECT(SimpleCPU)
#if FULL_SYSTEM
params->itb = itb;
params->dtb = dtb;
- params->mem = mem;
params->system = system;
params->cpu_id = cpu_id;
params->profile = profile;
#else
+ params->mem = mem;
params->process = workload;
#endif
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 6df553fe2..3354166cc 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -46,7 +46,7 @@
class Processor;
class AlphaITB;
class AlphaDTB;
-class PhysicalMemory;
+class Memory;
class RemoteGDB;
class GDBListener;
@@ -164,8 +164,8 @@ class SimpleCPU : public BaseCPU
#if FULL_SYSTEM
AlphaITB *itb;
AlphaDTB *dtb;
- FunctionalMemory *mem;
#else
+ Memory *mem;
Process *process;
#endif
};
diff --git a/mem/physical.cc b/mem/physical.cc
index 58c9ea408..d7c6345be 100644
--- a/mem/physical.cc
+++ b/mem/physical.cc
@@ -40,9 +40,6 @@
#include "base/misc.hh"
#include "config/full_system.hh"
-#if FULL_SYSTEM
-#include "mem/functional/memory_control.hh"
-#endif
#include "mem/physical.hh"
#include "sim/host.hh"
#include "sim/builder.hh"
@@ -71,46 +68,8 @@ PhysicalMemory::MemResponseEvent::description()
return "Physical Memory Timing Access respnse event";
}
-#if FULL_SYSTEM
-PhysicalMemory::PhysicalMemory(const string &n, Range<Addr> range,
- MemoryController *mmu, const std::string &fname)
- : Memory(n), base_addr(range.start), pmem_size(range.size()),
- pmem_addr(NULL)
-{
- if (pmem_size % TheISA::PageBytes != 0)
- panic("Memory Size not divisible by page size\n");
-
- mmu->add_child(this, range);
-
- int fd = -1;
-
- if (!fname.empty()) {
- fd = open(fname.c_str(), O_RDWR | O_CREAT, 0644);
- if (fd == -1) {
- perror("open");
- fatal("Could not open physical memory file: %s\n", fname);
- }
- ftruncate(fd, pmem_size);
- }
-
- int map_flags = (fd == -1) ? (MAP_ANON | MAP_PRIVATE) : MAP_SHARED;
- pmem_addr = (uint8_t *)mmap(NULL, pmem_size, PROT_READ | PROT_WRITE,
- map_flags, fd, 0);
-
- if (fd != -1)
- close(fd);
-
- if (pmem_addr == (void *)MAP_FAILED) {
- perror("mmap");
- fatal("Could not mmap!\n");
- }
-
- page_ptr = 0;
-}
-#endif
-
PhysicalMemory::PhysicalMemory(const string &n)
- : Memory(n), memoryPort(this), base_addr(0), pmem_addr(NULL)
+ : Memory(n), base_addr(0), pmem_addr(NULL)
{
// Hardcoded to 128 MB for now.
pmem_size = 1 << 27;
@@ -134,6 +93,7 @@ PhysicalMemory::~PhysicalMemory()
{
if (pmem_addr)
munmap(pmem_addr, pmem_size);
+ //Remove memPorts?
}
Addr
@@ -146,6 +106,13 @@ PhysicalMemory::new_page()
return return_addr;
}
+Port *
+PhysicalMemory::addPort(std::string portName)
+{
+ memoryPortList[portName] = new MemoryPort(this);
+ return memoryPortList[portName];
+}
+
//
// little helper for better prot_* error messages
//
@@ -174,11 +141,11 @@ PhysicalMemory::deviceBlockSize()
}
bool
-PhysicalMemory::doTimingAccess (Packet &pkt)
+PhysicalMemory::doTimingAccess (Packet &pkt, MemoryPort* memoryPort)
{
doFunctionalAccess(pkt);
- MemResponseEvent* response = new MemResponseEvent(pkt, &memoryPort);
+ MemResponseEvent* response = new MemResponseEvent(pkt, memoryPort);
response->schedule(curTick + lat);
return true;
@@ -210,7 +177,10 @@ PhysicalMemory::doFunctionalAccess(Packet &pkt)
Port *
PhysicalMemory::getPort(const char *if_name)
{
- return &memoryPort;
+ if (memoryPortList.find(if_name) != memoryPortList.end())
+ return memoryPortList[if_name];
+ else
+ panic("Looking for a port that didn't exist\n");
}
void
@@ -245,7 +215,7 @@ PhysicalMemory::MemoryPort::deviceBlockSize()
bool
PhysicalMemory::MemoryPort::recvTiming(Packet &pkt)
{
- return memory->doTimingAccess(pkt);
+ return memory->doTimingAccess(pkt, this);
}
Tick
diff --git a/mem/physical.hh b/mem/physical.hh
index b31e45ac5..fb2d0d743 100644
--- a/mem/physical.hh
+++ b/mem/physical.hh
@@ -37,7 +37,8 @@
#include "mem/packet.hh"
#include "mem/port.hh"
#include "sim/eventq.hh"
-
+#include <map>
+#include <string>
//
// Functional model for a contiguous block of physical memory. (i.e. RAM)
//
@@ -67,10 +68,14 @@ class PhysicalMemory : public Memory
virtual int deviceBlockSize();
};
- MemoryPort memoryPort;
+ std::map<std::string, MemoryPort*> memoryPortList;
Port * PhysicalMemory::getPort(const char *if_name);
+ Port * addPort(std::string portName);
+
+ int numPorts;
+
int lat;
struct MemResponseEvent : public Event
@@ -114,7 +119,7 @@ class PhysicalMemory : public Memory
// fast back-door memory access for vtophys(), remote gdb, etc.
// uint64_t phys_read_qword(Addr addr) const;
private:
- bool doTimingAccess(Packet &pkt);
+ bool doTimingAccess(Packet &pkt, MemoryPort *memoryPort);
Tick doAtomicAccess(Packet &pkt);
void doFunctionalAccess(Packet &pkt);
diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py
index a90203729..fac452285 100644
--- a/python/m5/objects/BaseCPU.py
+++ b/python/m5/objects/BaseCPU.py
@@ -8,10 +8,10 @@ class BaseCPU(SimObject):
if build_env['FULL_SYSTEM']:
dtb = Param.AlphaDTB("Data TLB")
itb = Param.AlphaITB("Instruction TLB")
- mem = Param.FunctionalMemory("memory")
system = Param.System(Parent.any, "system object")
cpu_id = Param.Int(-1, "CPU identifier")
else:
+ mem = Param.Memory("memory")
workload = VectorParam.Process("processes to run")
max_insts_all_threads = Param.Counter(0,
diff --git a/sim/process.cc b/sim/process.cc
index 2335d5cc8..ac2aae5d4 100644
--- a/sim/process.cc
+++ b/sim/process.cc
@@ -154,7 +154,7 @@ Process::startup()
if (execContexts.empty())
fatal("Process %s is not associated with any CPUs!\n", name());
- initVirtMem = new TranslatingPort((system->physmem->getPort("any"))->getPeer(), pTable);
+ initVirtMem = new TranslatingPort((system->physmem->getPort("DCACHE"))->getPeer(), pTable);
// first exec context for this process... initialize & enable
ExecContext *xc = execContexts[0];
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-06 00:27:49 +0000