diff options
| -rw-r--r-- | src/arch/arm/isa.hh | 15 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.hh | 6 |
2 files changed, 18 insertions, 3 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index f6ad56dd4..a9c404351 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -112,6 +112,21 @@ namespace ArmISA */ miscRegs[MISCREG_CPACR] = 0x0fffffff; + /* One region, unified map. */ + miscRegs[MISCREG_MPUIR] = 0x100; + + /* + * Implemented = '5' from "M5", + * Variant = 0, + */ + miscRegs[MISCREG_MIDR] = + (0x35 << 24) | //Implementor is '5' from "M5" + (0 << 20) | //Variant + (0xf << 16) | //Architecture from CPUID scheme + (0 << 4) | //Primary part number + (0 << 0) | //Revision + 0; + //XXX We need to initialize the rest of the state. } diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index a43bb2fe5..bce761962 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -102,12 +102,12 @@ namespace ArmISA MISCREG_BPIMVA, MISCREG_BPIALLIS, MISCREG_BPIALL, + MISCREG_MPUIR, + MISCREG_MIDR, MISCREG_CP15_UNIMP_START, MISCREG_CTR = MISCREG_CP15_UNIMP_START, MISCREG_TCMTR, - MISCREG_MPUIR, MISCREG_MPIDR, - MISCREG_MIDR, MISCREG_ID_PFR0, MISCREG_ID_PFR1, MISCREG_ID_DFR0, @@ -164,7 +164,7 @@ namespace ArmISA "clidr", "ccsidr", "csselr", "icialluis", "iciallu", "icimvau", "bpimva", "bpiallis", "bpiall", - "ctr", "tcmtr", "mpuir", "mpidr", "midr", + "mpuir", "midr", "ctr", "tcmtr", "mpidr", "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", |