diff options
| -rw-r--r-- | src/mem/DRAMCtrl.py | 18 | ||||
| -rw-r--r-- | src/mem/dram_ctrl.cc | 2 | ||||
| -rw-r--r-- | src/mem/dram_ctrl.hh | 1 |
3 files changed, 20 insertions, 1 deletions
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py index e729e9d78..c53e90e87 100644 --- a/src/mem/DRAMCtrl.py +++ b/src/mem/DRAMCtrl.py @@ -119,6 +119,9 @@ class DRAMCtrl(AbstractMemory): # timing behaviour and constraints - all in nanoseconds + # the base clock period of the DRAM + tCK = Param.Latency("Clock period") + # the amount of time in nanoseconds from issuing an activate command # to the data being available in the row buffer for a read/write tRCD = Param.Latency("RAS to CAS delay") @@ -195,6 +198,9 @@ class DDR3_1600_x64(DRAMCtrl): # DDR3 has 8 banks in all configurations banks_per_rank = 8 + # 800 MHz + tCK = '1.25ns' + # DDR3-1600 11-11-11-28 tRCD = '13.75ns' tCL = '13.75ns' @@ -256,6 +262,9 @@ class DDR3_1333_x64_DRAMSim2(DRAMCtrl): # DDR3 has 8 banks in all configurations banks_per_rank = 8 + # 666 MHs + tCK = '1.5ns' + tRCD = '15ns' tCL = '15ns' tRP = '15ns' @@ -307,6 +316,9 @@ class LPDDR2_S4_1066_x32(DRAMCtrl): # LPDDR2-S4 has 8 banks in all configurations banks_per_rank = 8 + # 533 MHz + tCK = '1.876ns' + # Fixed at 15 ns tRCD = '15ns' @@ -367,6 +379,9 @@ class WideIO_200_x128(DRAMCtrl): # WideIO has 4 banks in all configurations banks_per_rank = 4 + # 200 MHz + tCK = '5ns' + # WIO-200 tRCD = '18ns' tCL = '18ns' @@ -421,6 +436,9 @@ class LPDDR3_1600_x32(DRAMCtrl): # LPDDR3 has 8 banks in all configurations banks_per_rank = 8 + # 800 MHz + tCK = '1.25ns' + # Fixed at 15 ns tRCD = '15ns' diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc index 1e00dd606..dc47818e3 100644 --- a/src/mem/dram_ctrl.cc +++ b/src/mem/dram_ctrl.cc @@ -74,7 +74,7 @@ DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) : writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0), minWritesPerSwitch(p->min_writes_per_switch), writesThisTime(0), readsThisTime(0), - tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST), + tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST), tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR), tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD), tXAW(p->tXAW), activationLimit(p->activation_limit), diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh index 24f9729c5..0dbff7eaf 100644 --- a/src/mem/dram_ctrl.hh +++ b/src/mem/dram_ctrl.hh @@ -468,6 +468,7 @@ class DRAMCtrl : public AbstractMemory * Basic memory timing parameters initialized based on parameter * values. */ + const Tick tCK; const Tick tWTR; const Tick tRTW; const Tick tBURST; |